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1 for more information www.linear.com/lt8616 typical a pplica t ion fea t ures descrip t ion dual 42v synchronous monolithic step-down regulator with 6.5a quiescent curr ent the lt ? 8616 is a high efficiency, high speed, dual synchro- nous monolithic step-down switching regulator that con- sumes only 6.5 a of quiescent current with both channels enabled. both channels contain all switches and necessary circuitry to minimize the need for external components. low ripple burst mode operation enables high efficiency down to very low output currents while minimizing output ripple. a sync pin allows synchronization to an external clock. internal compensation with peak current mode topology allows the use of small inductors and results in fast transient response and good loop stability. the en - able pins have accurate 1 v thresholds and can be used to program undervoltage lockout. capacitors on the tr/ss pins programs the output voltage ramp rate during start- up while the pg pins signal when each output is within 10% of the programmed output voltage. the lt8616 is available in a tssop package for high reliability. a pplica t ions n wide input voltage range: 3.4v to 42v n 2.5a and 1.5 a buck regulators with separate inputs n fast minimum switch on-time: 35ns n ultralow quiescent current burst mode ? operation: n 6.5a i q regulating 12v in to 5v out and 3.3v out n output ripple < 15mv n 180 out of phase switching n adjustable and synchronizable: 200khz to 3mhz n accurate 1v enable pin thresholds n internal compensation n output soft-start and tracking n tssop package: output stays at or below regulation v oltage during adjacent pin short or when a pin is left floating n thermally enhanced 28-lead tssop package n automotive and industrial supplies n general purpose step-down l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. boost1 v in1 en/uv1 intv cc rt pg1 pg2 sync/mode tr/ss1 tr/ss2 sw1 lt8616 gnd fb1 bias boost2 sw2 8616 ta01a fb2 0.1f 0.1f v out1 5v, 1.5a 10pf 2 x 47f 4.7f v in 12v v out2 3.3v, 2.5a 10nf 10h 4.7h 1m 316k 1m 1m 187k 56.2k v in2 en/uv2 4.7f 5.6pf 47f 1f 5v, 3.3v, 700khz step-down converter efficiency load (ma) 0.01 30 efficiency (%) 90 80 70 60 50 40 100 1 10 100 1000 0.1 8616 ta01b ch2, 3.3v out ch1, 5v out v in1 = v in2 = 12v f sw = 700khz lt 8616 8616f
2 for more information www.linear.com/lt8616 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in 1 , v in 2 , en / uv 1, en / uv 2, pg 1, pg 2 ..................... 42 v b ias .......................................................................... 30 v bs t 1 above sw 1, bst 2 above sw 2, fb 1, fb 2, tr / ss 1, tr / ss 2 ..................................................... 4 v sync / mode ............................................................... 6 v operating junction temperature range ( note 2) lt 86 16 e ............................................. C 40 c to 125 c lt 86 16 i .............................................. C 40 c to 125 c lt 86 16 h ............................................ C 40 c to 150 c storage temperature range .................. C 60 c to 150 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 en/uv2 pg2 sw2 sw2 sw2 boost2 nc boost1 sw1 sw1 pg1 tr/ss1 fb1 fb1 tr/ss2 fb2 fb2 nc v in2 nc bias intv cc nc v in1 nc sync/mode en/uv1 rt 29 gnd t jmax = 150c, ja = 30c/w, jc = 10c/w exposed pad ( pin 29) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt8616efe#pbf lt8616efe#trpbf lt8616fe 28-lead plastic tssop C40 to 125c lt8616ife#pbf lt8616ife#trpbf lt8616fe 28-lead plastic tssop C40 to 125c lt8616hfe#pbf lt8616hfe#trpbf lt8616fe 28-lead plastic tssop C40 to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ (note 1) lt 8616 8616f
3 for more information www.linear.com/lt8616 e lec t rical c harac t eris t ics parameter conditions min typ max units common quiescent current en/uv1 = en/uv2 = 0v, current from v in1 l 1.7 1.7 4.0 8.0 a a en/uv1 = en/uv2 = 2v, sync = 0v (burst mode), not switching, current from v in1 l 3.0 3.0 5.0 12.0 a a en/uv1 = en/uv2 = 2v, sync = 3v (pulse-skipping mode), not switching, current from bias or v in1 l 0.5 1.0 ma fb voltage v in = 6v, load = 0.5a l 782 778 790 790 798 802 mv mv fb v oltage line regulation v in = 4v to 25v, load = 0.5a 0.005 %/v fb pin input current fb = 0.79v C20 20 na en/uv pin threshold rising l 0.97 1.03 1.09 v en/uv pin hysteresis 50 mv en/uv pin current en/uv = 2v C20 20 na pg upper threshold from v fb fb rising l 6 10 13 % pg lower threshold from v fb fb falling l C6 C10 C13 % pg hysteresis 1 % pg leakage pg = 3.3v C100 100 na pg pull-down resistance pg = 0.1v 350 tr/ss source current 1 2 3 a tr/ss pull-down resistance tr/ss = 0.1v 250 bias pin current consumption v out1 = 3.3v , load 1 = 0.5a , v out2 = 3.3v , load2 = 0.5a , f sw = 1mhz 7 ma oscillator frequency r t = 14.7k r t = 37.4k r t = 221k l l l 1.85 900 160 2.05 1000 200 2.25 1100 240 mhz khz khz sync threshold sync falling sync rising 0.4 2.4 v v sync pin current sync = 3v C100 100 na channel 1 minimum v in1 voltage l 3.0 3.4 v supply current in regulation v in = 6v, v out1 = 3.3v, load = 100a v in = 6v, v out1 = 3.3v load = 1ma 80 620 110 910 a a sw1 minimum on-t ime load = 0.25a, pulse-skipping mode l 20 35 55 ns sw1 top nmos on-resistance 310 m sw1 peak current limit (note 3) l 3.2 4.2 5.2 a sw1 bottom nmos on-resistance 190 m sw1 valley current limit l 1.5 2.0 3.0 a sw1 leakage current v in1 = 42v, v sw1 = 0v, 42v C2 2 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. lt 8616 8616f
4 for more information www.linear.com/lt8616 parameter conditions min typ max units channel 2 minimum v in1 voltage to use channel2 l 3.0 3.4 v supply current in regulation v in = 6v, v out2 = 3.3v, load2 = 100a v in = 6v, v out2 = 3.3v load2 = 1ma 80 620 110 910 a a sw2 minimum on-t ime load = 0.25a, pulse-skipping mode l 20 35 55 ns sw2 top nmos on-resistance 145 m sw2 peak current limit (note 3) l 4.5 5.5 6.5 a sw2 bottom nmos on-resistance 120 m sw2 valley current limit l 2.5 3.5 4.5 a sw2 leakage current v in2 = 42v, v sw2 = 0v, 42v C2 2 a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8616e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8616i is guaranteed over the full C40c to 125c operating junction temperature range. the lt8616h is guaranteed over the full C40c to 150c operating junction temperature range. note 3: current limit guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycle. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. see high temperature considerations section. lt 8616 8616f
5 for more information www.linear.com/lt8616 typical p er f or m ance c harac t eris t ics efficiency at 3.3v out efficiency at 3.3v out no load supply current no load supply current bias current vs switching frequency en/uv threshold efficiency at 5v out efficiency at 5v out efficiency vs frequency load (a) 0 80 efficiency (%) 98 96 94 92 90 88 86 84 82 100 0.25 1.5 1.75 2.0 2.25 2.5 0.5 0.75 1.0 8616 g01 1.25 ch2, 24v in ch2, 12v in ch1, 24v in ch1, 12v in f sw = 700khz load (ma) 0.01 30 efficiency (%) 95 90 85 80 75 70 65 60 55 50 45 40 35 100 0.1 100 1000 1 8616 g02 10 f sw = 700khz ch2, 24v in ch2, 12v in ch1, 24v in ch1, 12v in frequency (mhz) 0.2 85 efficiency (%) 95 94 93 92 91 90 89 88 87 86 1.4 2.6 3.0 1.8 8616 g03 2.2 1.00.6 v in1 = v in2 = 12v ch2, 3.3v, 1.5a ch1, 5v, 1a load (a) 0 80 efficiency (%) 100 98 96 94 92 90 88 86 84 82 0.75 1.0 1.25 2.0 2.25 2.5 1.5 8616 g04 1.75 0.50.25 ch2, 24v in ch2, 12v in ch1, 24v in ch1, 12v in f sw = 700khz load (ma) 0.01 30 efficiency (%) 100 90 95 85 80 75 70 65 60 55 50 45 40 35 0.1 1 10 1000 8616 g05 100 ch2, 24v in ch2, 12v in ch1, 24v in ch1, 12v in f sw = 700khz v in (v) 0 0 input current (a) 10 9 8 7 6 5 4 3 2 1 5 10 15 20 25 30 40 8616 g06 35 v out1 = 3.3v v out2 = 5v temperature (c) ?50 0 supply current (a) 30 25 20 15 10 5 ?25 0 25 50 75 100 150 8616 g07 125 v in1 = v in2 = 12v v out1 = 5v v out2 = 3.3v in regulation frequency (mhz) 0 0 bias current (ma) 18 16 14 12 10 8 6 4 2 0.5 1.0 1.5 2.0 3.0 8616 g08 2.5 v in1 = v in2 = 12v v out1 = 5v load1 = 1a v out2 = 3.3v load2 = 1a temperature (c) ?50 0.92 en threshold (v) 1.1 1.08 1.06 1.04 0.98 0.96 0.94 1.02 1.0 ?25 50250 75 100 150 8616 g09 125 en falling en rising lt 8616 8616f
6 for more information www.linear.com/lt8616 typical p er f or m ance c harac t eris t ics power-good thresholds soft-start tracking switching frequency switching period vs r t minimum on-time minimum off-time fb voltage vs temperature line regulation vs v in1 load regulation temperature (c) ?50 774 voltage (mv) 802 800 798 796 794 792 790 788 786 784 782 780 778 776 806 804 75 100 125 150 ?25 0 25 8616 g10 50 v in1 (v) 0 ?0.1 voltage (%) 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 0.1 0.08 25 30 35 40 5 10 8616 g11 15 20 v in1 = v in2 load (a) 0 ?0.2 change in v out (%) 0.1 0.05 0 ?0.05 ?0.1 ?0.15 0.2 0.15 1.75 2.0 2.25 2.5 0.25 1.00.750.5 8616 g12 1.25 1.5 fb2 fb1 temperature (c) ?50 ?15 pg threshold relative to fb (%) 5 0 ?5 ?10 15 10 75 100 125 150 ?25 0 8616 g13 25 50 pg high falling pg low rising pg high rising pg low falling ss/tr voltage (mv) 0 0 fb voltage (mv) 700 300 400 500 600 200 100 900 800 700 800 900 1000 100 200 300 8616 g14 400 500 600 temperature (c) ?50 1.85 frequency (mhz) 2.15 2.1 2.05 2 1.95 1.9 2.25 2.2 75 100 125 150 ?25 0 8616 g15 25 50 r t = 14.7k switching period (s) 0 0 r t resistor (k) 200 180 160 140 120 100 80 60 40 20 240 220 2 3 4 5 8616 g16 1 temperature (c) ?50 20 time (ns) 45 40 35 30 25 50 75 100 125 150 8616 g17 ?25 0 25 50 temperature (c) ?50 50 time (ns) 85 80 75 70 65 60 55 90 75 100 125 150 8616 g18 ?25 0 25 50 lt 8616 8616f
7 for more information www.linear.com/lt8616 typical p er f or m ance c harac t eris t ics current limit vs temperature switch resistance vs temperature dropout voltage vs load start-up dropout (ch1, 5v) start-up dropout (ch2, 3.3v) burst frequency vs load minimum load for full frequency top fet current limit vs duty cycle load current (ma) 0 0 switching frequency (khz) 700 600 500 400 300 200 100 800 50 200 250 300 350 400 100 8616 g19 150 v in1 = v in2 =12v f sw = 700khz sync = 0v ch2, 3.3v ch1, 5v ch2, 3.3v ch1, 5v v in (v) 0 0 load current (ma) 70 60 50 40 30 20 10 80 5 20 25 30 35 40 10 8616 g20 15 f sw = 700khz sync = 3v ch2 ch1 duty cycle (%) 0 2.0 current limit (a) 5.0 4.5 4.0 3.5 3.0 2.5 5.5 20 40 60 80 100 8616 g21 temperature (c) ?50 0 current limit (a) 5 4 3 2 1 6 75 100 125 150 ?25 0 25 8616 g22 50 ch2, valley ch2, 0% dc peak ch1, valley ch1, 0% dc peak temperature (c) ?50 0 resistance (m) 500 400 300 200 100 600 75 100 125 150 ?25 0 25 8616 g23 50 ch2, bottom ch2, top ch1, bottom ch1, top load (a) 0 0 dropout voltage (mv) 900 800 700 600 500 400 300 200 100 1000 1 1.5 2 2.5 0.5 8616 g24 ch2, 5v ch1, 5v f sw = 2mhz 100ms/div v in1 1v/div v out1 1v/div 8616 g26 r load1 = 3.33 (1.5a) 100ms/div v in1 and v in2 1v/div v out2 1v/div 8616 g27 v in1 = v in2 r load2 = 1.32 (2.5a) start-up dropout (ch2, 3.3v) 100ms/div v in2 1v/div v out2 1v/div 8616 g28 v in1 = 6v r load2 = 1.32 (2.5a) lt 8616 8616f
8 for more information www.linear.com/lt8616 typical p er f or m ance c harac t eris t ics ccm burst mode dcm ch1 ccm, ch2 ccm ch1 ccm, ch2 burst mode ch1 shorted, ch2 ccm transient ch1, 5v transient ch2, 3.3v 20s/div v out1 (ac) 200mv/div i l1 500ma/div 8616 g29 v in1 = 12v v out1 = 5v l1 = 10h c out1 = 47f c ff = 5.6pf 20s/div 8616 g30 v out2 (ac) 50mv/div i l2 1a/div v in2 = 12v v out2 = 3.3v l2 = 4.7h c out2 = 2 x 47f c ff2 = 10pf 1s/div v sw 5v/div i l 500ma/div 8616 g31 12v in to 5v out at 500ma 1s/div v sw 5v/div i l 500ma/div 8616 g32 12v in to 5v out at 50ma sync = 0v 1s/div v sw 5v/div i l 500ma/div 8616 g33 12v in to 5v out at 50ma sync = 3v 500ns/div sw1 5v/div sw2 5v/div 8616 g34 v in = 12v ch1 = 5v, 1a ch2 = 3.3v, 1a sync = 0v 1s/div sw1 5v/div sw2 5v/div 8616 g35 v in = 12v ch1 = 5v, 1a ch2 = 3.3v, 0.1a sync = 0v 5s/div sw1 5v/div sw2 5v/div 8616 g36 v in = 12v ch1 = 0v short ch2 = 3.3v, 1a sync = 0v v in1 uvlo temperature (c) ?50 2.0 v in1 (v) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 3.6 75 100 125 150 ?25 0 25 50 8616 g25 lt 8616 8616f
9 for more information www.linear.com/lt8616 p in func t ions bias: the bias pin supplies the internal regulator when tied to a voltage higher than 3.1v . for output voltages of 3.3v and above this pin should be tied to the appropriate v out . connect a 1 f bypass capacitor to this pin if it is connected to a supply other than v out1 or v out2 . ground if unused. boost1, boost2: the boost pins are used to provide drive voltages, higher than the input voltage, to the internal topside power switches. place 0.1 f capacitors between boost and its corresponding sw pin as close as possible to the ic. boost nodes should be kept small on the pcb for good performance. en/uv1, en/uv2: the en/uv pins are used to indepen - dently disable each channel when pulled low and enable when pulled high. the hysteretic threshold voltage is 1.03v going up and 0.98 v going down. tie to v in supply if the shutdown feature is not used. external resistor dividers from v in can be used to program thresholds below which each channel is disabled. dont float these pins. fb1, fb2: the fb pins are regulated to 0.790 v. connect the feedback resistor divider taps to the fb pins. also connect phase lead capacitors between fb pins and v out nodes. typical phase lead capacitors are 1.5pf to 10pf. gnd: the gnd pins and exposed pad must be con - nected to the negative terminal of the input capacitors and soldered to the pcb in order to lower the thermal resistance. intv cc : the intv cc pin provides power to internal gate drivers and control circuits. intv cc current will be sup- plied from bias if v bias > 3.1 v, otherwise current will be drawn from v in1 . decouple this pin to ground with at least a 1 f low esr ceramic capacitor. do not load the intv cc pin with external circuitry. nc: the nc pins have no internal connection. float nc pins to increase fault tolerance or connect to ground to facilitate pcb layout. pg1, pg2: the pg pins are the open-drain outputs of the internal power good comparators. each channel's pg pin remains low until the respective fb pin is within 10% of the final regulation voltage and there are no fault conditions. rt : a resistor is tied between rt and ground to set the switching frequency. sw1, sw2: the sw pins are the outputs of each chan- nel's internal power switches. connect these pins to the inductors and boost capacitors. sw nodes should be kept small on the pcb for good performance. sync/mode: ground the sync/mode pin for low ripple burst mode operation at low output loads. tie to a clock source for synchronization to an external frequency. apply a dc voltage of 2.4 v or higher or tie to intv cc for pulse- skipping mode. when in pulse-skipping mode, the i q will increase to several hundred a. channel 1 will align its positive switching edge to the positive edge of the external clock and channel 2 will align its positive switching edge to the negative external clock edge. do not float this pin. tr/ss1, tr/ss2: the tr/ ss pins are used to soft- start the two channels, to allow one channel to track the other output, or to allow both channels to track another output. for tracking, tie a resistor divider to the tr/ ss pin from the tracked output. for soft- start, tie a capacitor to tr/ ss. internal 2 a pull- up currents from intv cc charge soft- start capacitors to create voltage ramps. a tr/ ss voltage below 0.79v for ces the lt8616 to regulate the corresponding fb pins to equal the tr/ ss pin voltage. when tr/ ss voltages are above 0.79v , the tracking func - tion is disabled and the internal reference resumes control of the error amplifiers. tr / ss pins are individually pulled to ground with internal 250 mosfets during shutdown and fault conditions; use series resistors if driving from a low impedance output. v in1 : v in1 supplies current to the lt8616 's internal circuitry and to channel 1' s topside power switch. this pin must be locally bypassed. be sure to place the positive terminal of the input capacitor as close as possible to the pin, and the negative capacitor terminal as close as possible to the gnd pins. v in1 must be connected to 3.4 v or above even if only channel 2 is in use. v in2 : v in2 supplies current to internal channel 2' s topside power switch. this pin must be locally bypassed. be sure to place the positive terminal of the input capacitor as close as possible to the pin, and the negative capacitor terminal as close as possible to the gnd pins. please note v in1 must be 3.4v or above to operate channel 2. lt 8616 8616f
10 for more information www.linear.com/lt8616 b lock diagra m + ? + ? + + ? internal reference and 3.3v regulator driver switch logic and anti- shoot through burst logic + + ? oscillator 200khz to 3mhz burst logic v in1 v in2 r5 r6 r7 r8 en/uv2 en/uv1 shdn1 shdn2 1.03v 1.03v intv cc v c1 intv cc c v cc c ff1 c ff2 bias boost1 sw1 gnd v in2 boost2 c bst2 l2 sw2 gnd 8616 bd gnd c bst1 v in1 v in1 v out1 v in2 v out2 c out2 c in2 c out1 c in1 l1 intv cc intv cc v c2 shdn2 tr/ss2 fb2 r3 r4 r1 r2 pg2 sync/mode rt tr/ss1 fb1 2a 2a pg1 c ss1 r t tsd v in1 uvlo shdn2 v in1 uvlo intv cc uvlo tsd shdn1 v in1 uvlo intv cc uvlo tsd shdn1 10% 0.79v v in1 uvlo intv cc tsd c ss2 v out2 v out1 error amp error amp slope comp slope comp driver switch logic and anti- shoot through 10% 0.79v lt 8616 8616f
11 for more information www.linear.com/lt8616 o pera t ion foreword the lt8616 is a dual monolithic step down regulator. the two channels differ in maximum current and input range. the following sections describe the operation of channel 1 and common circuits. they will highlight channel 2 dif - ferences and interactions only when relevant. to simplify the application, both v in1 and v in2 are assumed to be con- nected to the same input supply. however, note that v in1 must be greater than 3.4v for either channel to operate. operation the lt8616 is a dual monolithic, constant frequency, peak current mode step-down dc/dc converter. an oscillator, with frequency set using a resistor on the rt pin, turns on the internal top power switch at the beginning of each clock cycle. current in the inductor then increases until the top switch current comparator trips and turns off the top power switch. the peak inductor current at which the top switch turns off is controlled by the voltage on the internal v c node. the error amplifier servos the v c node by comparing the voltage on the fb pin with an internal 0.790 v reference. when the load current increases it causes a reduction in the feedback voltage relative to the reference, causing the error amplifier to raise the v c voltage until the average inductor current matches the new load current. when the top power switch turns off, the synchronous power switch turns on until the next clock cycle begins or inductor current falls to zero. if overload conditions result in more than the valley current limit flowing through the bottom switch, the next clock cycle will be delayed until current returns to a safe level. if either en/uv pin is low, the corresponding channel is shut down. if both en/uv pins are low, the lt8616 is fully shut down and draws 1.7 a from the input supply. when the en/uv pins are above 1.03 v, the corresponding switching regulators will become active . 1.3 a is supplied by v in1 to common bias circuits for both channels. each channel can independently enter burst mode opera- tion to optimize efficiency at light load. between bursts, all circuitry associated with controlling the output switch is shut down, reducing the channel's contribution to in - put supply current. in a typical application , 6.5 a will be consumed from the input supply when regulating both channels with no load. ground the sync/mode pin for burst mode operation or apply a dc voltage above 2.4v to use pulse-skipping mode. if a clock is applied to the sync/mode pin, both channels will synchronize to the external clock frequency and operate in pulse-skipping mode. while in pulse- skipping mode the oscillator operates continuously and sw transitions are aligned to the clock. during light loads, switch pulses are skipped to regulate the output and the quiescent current per channel will be several hundred a. to improve efficiency across all loads, supply current to internal circuitry can be sourced from the bias pin when biased at 3.1v or above. otherwise, the internal circuitry will draw current exclusively from v in1 . the bias pin should be connected to the lowest v out programmed at 3.3v or above. comparators monitoring the fb pin voltage will pull the corresponding pg pin low if the output voltage varies more than 10% ( typical) from the regulation voltage or if a fault condition is present. tracking soft-start is implemented by providing constant current via the tr/ss pin to an external soft-start capaci - tor to generate a voltage ramp. fb voltage is regulated to the voltage at the tr/ss pin until it exceeds 0.790 v; fb is then regulated to the 0.790v reference. soft-start also reduces the valley current limit to avoid inrush current during start- up. the ss capacitor is reset during shutdown, v in1 undervoltage, or thermal shutdown. channel 1 is designed for 1.5 a load, whereas channel 2 is designed for 2.5 a load. channel 1 has a minimum v in1 requirement of 3.4 v, but channel 2 can operate with no minimum v in2 provided that the minimum v in1 has been satisfied. lt 8616 8616f
12 for more information www.linear.com/lt8616 achieving ultralow quiescent current to enhance efficiency at light loads, the lt8616 operates in low ripple burst mode operation, which keeps the out - put capacitor charged to the desired output voltage while minimizing the input quiescent current and output voltage ripple. 1.7 a is supplied by v in1 to common bias circuits. in burst mode operation the lt8616 delivers single small pulses of current to the output capacitor followed by sleep periods where the output power is supplied by the output capacitor. while in sleep mode the lt8616 consumes 3 a. as the output load decreases, the frequency of single cur - rent pulses decreases ( see figure 1 a) and the percentage of time that the lt8616 is in sleep mode increases, result- ing in much higher light load efficiency than for typical converters. by maximizing the time between pulses, the converter quiescent current approaches 6.5 a for a typi - cal application when there is no output load. therefore, to optimize the quiescent current performance at light loads, the current in the feedback resistor divider must be minimized as it appears to the output as load current. while in burst mode operation the current limit of the top switch is approximately 400 ma for channel 1 (600 ma for channel 2) resulting in output voltage ripple shown in figure 2. increasing the output capacitance will decrease the output ripple. as load increases from zero the switch - ing frequency will increase but only up to the switching frequency programmed by the resistor at the rt pin as shown in figure 1 a. the output load at which the lt8616 reaches the programmed frequency varies based on input voltage, output voltage, and inductor value. for some applications it is desirable to select pulse- skipping mode to maintain full switching frequency at lower output load (see figure 1b). see pulse-skipping mode section. fb resistor network the output voltage is programmed with a resistor divider between the output and the fb pin ( r1 to r2 for channel 1, r3 to r4 for channel 2). choose the resistor values ac- cording to: r1 = r2 v out1 0.790v ? 1 ? ? ? ? ? ? (1) a pplica t ions i n f or m a t ion figure 1a. frequency vs load in burst mode operation figure 1b. minimum load for full frequency in pulse-skipping mode figure 2. burst mode operation load current (ma) 0 0 switching frequency (khz) 800 700 600 500 400 300 200 100 200 350 400 250 8616 f01a 300 15010050 v in1 = v in2 = 12v f sw = 700khz sync = 0v ch2, 3.3v ch1, 5v v in (v) 0 0 load current (ma) 80 70 60 50 40 30 20 10 20 35 40 25 8616 f01b 30 15105 f sw = 700khz sync = 3v ch2, 3.3v ch1, 5v 5s/div v out (ac) 5mv/div i l 200ma/div 8616 f02 ch1 = 5v, 25ma lt 8616 8616f
13 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion figure 3. switching frequency vs r t reference designators refer to the block diagram. 1% resis - tors are recommended to maintain output voltage accuracy. if low input quiescent current and good light - load efficiency are desired, use large resistor values for the fb resistor divider. the current flowing in the divider acts as a load current and will increase the no-load input current to the converter, which is approximately: i q = 3a + v out1 r1 + r2 ? ? ? ? ? ? v out1 v in1 ? ? ? ? ? ? 1 ? ? ? ? ? ? (2) where 3 a is the quiescent current, the second term is the current in the feedback divider reflected to the input of channel 1 operating at its light load efficiency m . for a 3.3v application with r 1 = 1 m and r2 = 316 k, the feedback divider draws 2.5 a. with v in = 12 v and m = 70%, this adds 1 a to the 3 a quiescent current resulting in 4a no-load current from the 12v supply. substitute r1 and r2 with r3 and r4 in the above equa - tion if v in1 and v in2 are connected to the same voltage. assuming channel 2 feedback divider contributes 2.5a to the quiescent current, then the total quiescent current is 6.5a. for a typical fb resistor of 1 m, a 1.5 pf to 10 pf phase- lead capacitor should be connected from v out to fb. setting the switching frequency the lt8616 uses a constant frequency pwm architecture that can be programmed to switch from 200 khz to 3mhz by using a resistor tied from the rt pin to ground. table 1 and figure 3 show the necessary r t value for a desired switching frequency. the r t resistor required for a desired switching frequency can be calculated using: r t = 0.6 f sw 2 + 42.6 f sw ? 6. 1 (3) where r t is in k and f sw is the desired switching fre- quency in mhz. table 1. sw frequency vs r t value f sw (mhz) r t k) f sw (mhz) r t k) 0.2 221 1.6 20.5 0.3 143 1.8 17.8 0.4 105 2.0 15.4 0.5 80.6 2.05 14.7 0.6 66.5 2.2 13.3 0.7 56.2 2.4 11.8 0.8 47.5 2.6 10.3 1.0 37.4 2.8 9.31 1.2 29.4 3.0 8.25 1.4 24.3 the two channels of the lt8616 operate 180 out of phase to avoid aligned switching edge noise and input current ripple. operating frequency selection and trade-offs selection of the operating frequency is a trade-off between efficiency, component size, and input voltage range. the advantage of high frequency operation is that smaller induc - tor and capacitor values may be used. the disadvantages are lower efficiency and a smaller input voltage range for full frequency operation. switching period (s) 0 0 r t resistor (k) 120 140 160 180 200 220 100 80 60 40 20 240 1 2 3 4 5 8616 f03 lt 8616 8616f
14 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion the highest switching frequency (f sw(max) ) for a given application can be calculated as follows: f sw(max) = v out + v sw(bot) t on(min) v in ? v sw(top) + v sw(bot) ( ) (4) where v in is the typical input voltage, v out is the output voltage, v sw(top) and v sw(bot) are the internal switch drops (~0.53v, ~0.38 v, respectively at maximum load for channel 1 and ~0.78v, ~0.48 v for channel 2) and t on(min) is the minimum top switch on-time of 55ns (see the electrical characteristics). this equation shows that a lower switching frequency is necessary to accommodate a high v in /v out ratio. choose the lower frequency between channel 1 and 2. for transient operation, v in may go as high as the absolute maximum rating of 42 v regardless of the r t value, how- ever the lt8616 will reduce switching frequency on each channel independently as necessary to maintain control of inductor current to assure safe operation. the lt8616 is capable of a maximum duty cycle of greater than 99%, and the v in to v out dropout is limited by the r ds(on) of the top switch. in this mode the channel that enters dropout skips switch cycles, resulting in a lower than programmed switching frequency. for applications that cannot allow deviation from the pro - grammed switching frequency at low v in /v out ratios, use the following formula to set switching frequency: v in(min) = v out + v sw(bot) 1? f sw ? t off(min) ? v sw(bot) + v sw(top) (5) where v in(min) is the minimum input voltage without skipped cycles, v out is the output voltage, v sw(top) and v sw(bot) are the internal switch drops (~0.53v, ~0.38v, respectively at maximum load for channel 1 and ~0.78v, ~0.48v for channel 2), f sw is the switching frequency (set by r t ), and t off(min) is the minimum switch off-time. note that higher switching frequency will increase the minimum input voltage below which cycles will be dropped to achieve higher duty cycle. note there is no minimum v in2 voltage requirement as it does not supply the internal common bias circuits, mak- ing channel 2 uniquely capable of operating from very low input voltages. inductor selection and maximum output current the lt8616 is designed to minimize solution size by allowing the inductor to be chosen based on the output load requirements of the application. during overload or short-circuit conditions the lt8616 safely tolerates opera - tion with a saturated inductor through the use of a high speed peak-current mode ar chitecture. a good first choice for the inductor value is: l1 = v out1 + v sw1(bot) f sw ? 1.6 l2 = v out2 + v sw2(bot) f sw (6a) (6b) where f sw is the switching frequency in mhz, v out is the output voltage, v sw(bot) is the bottom switch drop (~0.38v, ~0.48 v) and l is the inductor value in h. to avoid overheating and poor efficiency, an inductor must be chosen with an rms current rating that is greater than the maximum expected output load of the application. in addition, the saturation current ( typically labeled i sat ) rat- ing of the inductor must be higher than the load current plus 1/2 of in inductor ripple current: i l(peak) = i load(max) + 1 2 i l (7) where ? i l is the inductor ripple current as calculated in equation 9 and i load(max) is the maximum output load for a given application. as a quick example, an application requiring 1 a output should use an inductor with an rms rating of greater than 1a and an i sat of greater than 1.3 a. during long duration overload or short-circuit conditions, the inductor rms rating requirement is greater to avoid overheating of the inductor. to keep the efficiency high, the series resistance (dcr) should be less than 0.04, and the core material should be intended for high frequency applications. lt 8616 8616f
15 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion the lt8616 limits the peak switch current in order to protect the switches and the system from overload faults. the top switch current limit (i lim ) is 4.2 a at 0% duty cycle and decreases linearly to 2.9 a at dc = 80% (channel 2 current limit are 5.5 a at 0% duty cycle and 3.7 a at dc = 80%). the inductor value must then be sufficient to supply the desired maximum output current (i out(max) ), which is a function of the switch current limit (i lim ) and the ripple current. i out(max) = i lim ? i l 2 (8) the peak-to-peak ripple current in the inductor can be calculated as follows: i l = v out l ? f sw ? 1? v out v in(max) ? ? ? ? ? ? (9) where f sw is the switching frequency of the lt8616, and l is the value of the inductor. therefore, the maximum output current that the lt8616 will deliver depends on the switch current limit, the inductor value, and the input and output voltages. each channel has a secondary valley current limit. after the top switch has turned off, the bottom switch carries the inductor current. if for any reason the inductor current is too high, the bottom switch will remain on, delaying the top switch turning on until the inductor current returns to a safe level. this level is specified as the valley current limit, and is independent of duty cycle. maximum output current in the application circuit is limited to this valley current plus one half of the inductor ripple current. in most cases current limit is enforced by the top switch. the bottom switch limit controls the inductor current when the minimum on-time condition is violated ( high input voltage, high frequency or saturated inductor). the bottom switch current limit is designed to avoid any contribution to the maximum rated current of the lt8616. the optimum inductor for a given application may differ from the one indicated by this design guide. a larger value inductor provides a higher maximum load current and reduces the output voltage ripple. for applications requir- ing smaller load currents, the value of the inductor may be lower and the lt8616 may operate with higher ripple current. this allows use of a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. be aware that low inductance may result in discontinuous mode operation, which further reduces maximum load current. for more information about maximum output current and discontinuous operation, see linear technologys application note 44. finally, for duty cycles greater than 50% ( v out /v in > 0.5), a minimum inductance is required to avoid sub-harmonic oscillation. see application note 19. table 2. inductor manufacturers vendor url coilcraft www.coilcraft.com sumida www.sumida.com toko www.toko.com wrth elektronik www.we-online.com vishay www.vishay.com input capacitor bypass the input of the lt8616 circuit with a ceramic ca- pacitor of x7r or x5r type placed as close as possible to the v in and gnd pins. y5v types have poor performance over temperature and applied voltage, and should not be used. a 2.2 f to 10 f ceramic capacitor is adequate to bypass the lt8616 and will easily handle the ripple current . note that larger input capacitance is required when a lower switching frequency is used. if the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. this can be provided with a low performance electrolytic capacitor. step-down regulators draw current from the input sup - ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt8616 and to force this very high frequency lt 8616 8616f
16 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion switching current into a tight local loop, minimizing emi. a 2.2 f capacitor is capable of this task, but only if it is placed close to the lt8616 ( see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt8616. a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped) tank cir - cuit. if the lt8616 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the lt8616s voltage rating. this situation is easily avoided ( see linear technology application note 88). output capacitor and output ripple the output capacitor has two essential functions. along with the inductor, it filters the square wave generated by the lt8616 to produce the dc output. in this role it deter - mines the output voltage ripple, thus, low impedance at the switching frequency is important. the second function is to store energy in order to satisfy transient loads and stabilize the lt8616s control loop. ceramic capacitors have very low equivalent series resistance ( esr) and provide the best ripple performance. for good starting values, see the typical applications section. use x5r or x7r types. this choice will provide low output ripple and good transient response. transient performance can be improved with a higher value output capacitor and the addition of a feed forward capacitor placed between v out and fb. increasing the output capacitance will also decrease the output voltage ripple. a lower value of output capacitor can be used to save space and cost but transient performance will suffer and may cause loop instability. see the typical applications in this data sheet for suggested capacitor values. when choosing a capacitor, special attention should be given to the data sheet to calculate the effective capacitance under the relevant operating conditions of voltage bias and temperature. a physically larger capacitor or one with a higher voltage rating may be required. ceramic capacitors ceramic capacitors are small, robust and have very low esr. however, ceramic capacitors can cause problems when used with the lt8616 due to their piezoelectric nature. when in burst mode operation, the lt8616s switching frequency depends on the load current, and at very light loads the lt8616 can excite the ceramic capacitor at audio frequencies, generating audible noise. since the lt8616 operates at a lower current limit during burst mode op- eration, the noise is typically very quiet to a casual ear. if this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. low noise ceramic capacitors are also available. enable pin the lt8616 is in shutdown when both en/uv pins are low and active when either pin is high. the rising threshold of the en/uv comparator is 1.03 v, with 50 mv of hysteresis. the en/uv pins can be tied to v in if the shutdown feature is not used, or tied to a logic level if shutdown control is required. adding a resistor divider from v in to en/uv programs the lt8616 to operate only when v in is above a desired voltage ( see the block diagram). typically, this threshold, v in(en) , is used in situations where the input supply is cur- rent limited , or has a relatively high source resistance. a switching regulator draws constant power from the source , so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low table 3. ceramic capacitor manufacturers manufacturer web taiyo yuden www.t-yuden.com avx www.avxcorp.com murata www.murata.com tdk www.tdk.com lt 8616 8616f
17 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion source voltage conditions. the v in(en) threshold prevents the regulator from operating at source voltages where the problems might occur. this threshold can be adjusted by setting the values r5 and r 6 ( r7, r8 for channel 2) such that they satisfy the following equation: r5 = r6 v in1(en) 1.03v ? 1 ? ? ? ? ? ? (10) where the corresponding channel will remain off until v in is above v in(en) . due to the comparators hysteresis, switch- ing will not stop until the input falls slightly below v in(en) . when operating in burst mode operation for light load currents, the current through the v in(en) resistor network can easily be greater than the supply current consumed by the lt8616. therefore, the v in(en) resistors should be large to minimize their effect on efficiency at low loads. intv cc regulator an internal low dropout ( ldo) regulator produces the 3.4 v supply from v in1 that powers the drivers and the internal bias circuitry. for this reason, v in1 must be present and valid to use either channel. the intv cc pin supplies cur- rent for the lt8616s circuitry and must be bypassed to ground with a 1 f ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the power mosfet gate drivers. to improve efficiency, the internal ldo will draw current from the bias pin when the bias pin is at 3.1 v or higher. typically, the bias pin is tied to the lowest output or external supply above 3.1 v. if bias is connected to a supply other than v out , bypass it with a local ceramic capacitor. if the bias pin is below 3.0v, the internal ldo will consume current from v in1 . applications with high input voltage and high switching frequency where the internal ldo pulls current from v in1 will increase die temperature because of the higher power dissipation across the ldo. do not connect an external load to the intv cc pin. output voltage tracking and soft-start the lt8616 allows the user to program its output voltage ramp rate with the tr/ss pin. an internal 2 a current pulls up the tr/ss pin to intv cc . putting an external capacitor on tr/ss enables soft starting the output to prevent cur- rent surge on the input supply. during the soft-start ramp the output voltage will proportionally track the tr/ss pin voltage. for output tracking applications, tr/ss can be externally driven by another voltage source. from 0 v to 0.790v, the tr/ss voltage will override the internal 0.790 v reference input to the error amplifier, thus regulating the fb pin voltage to that of tr/ss pin (figure 4). when tr/ss is above 0.790 v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. the tr/ss pin may be left floating if the function is not needed. note the lt8616 will not discharge the output to regulate to a lower tr/ss voltage (figure 5). an active pull-down circuit is connected to the tr/ss pin which will discharge the external soft-start capacitor in the case of fault conditions and restart the ramp when the faults are cleared. fault conditions that clear the soft-start capacitor are the corresponding en/uv pin below 0.92v, v in1 voltage falling too low, or thermal shutdown. figure 4. fb tracking tr/ss voltage until 0.790v tr/ss voltage (mv) 0 0 fb voltage (mv) 600 700 800 500 400 300 200 100 900 600500400300200100 700 800 900 1000 8616 f04 lt 8616 8616f
18 for more information www.linear.com/lt8616 output power good when the lt8616s output voltage is within the 10% window of the regulation point, which is a fb voltage in the range of 0.72 v to 0.88v ( typical), the output voltage is considered good and the open-drain pg pin goes high impedance and is typically pulled high with an external resistor. otherwise, the internal pull-down device will pull the pg pin low. to prevent glitching, both the upper and lower thresholds include 1% of hysteresis. see figure 6. the pg pin is also actively pulled low during several fault conditions: corresponding en / uv pin below 0.92 v , intv cc voltage falling too low, v in1 uvlo, or thermal shutdown. a pplica t ions i n f or m a t ion figure 5. tr/ss does not discharge v out figure 6. power-good thresholds synchronization to select low ripple burst mode operation, tie the sync/ mode pin below 0.4v (this can be ground or a logic low output). to select pulse skip mode, tie the sync/mode pin above 2.4v ( sync/mode can be tied to intv cc ). to synchronize the lt8616 oscillator to an external frequency connect a square wave (with 20% to 80% duty cycle) to the sync/mode pin. the square wave amplitude should have valleys that are below 0.4 v and peaks above 2.4 v (up to 6v). channel 1 will synchronize its positive switch edge transi - tions to the positive edge of the sync signal, and channel 2 will synchronize to the negative edge of the sync signal. the lt8616 will not enter burst mode operation at low output loads while synchronized to an external clock, but instead will pulse skip to maintain regulation. the lt8616 may be synchronized over a 200 khz to 3 mhz range. the r t resistor should be chosen to set the lt8616 switching frequency to 20% below the lowest synchronization input. for example, if the synchronization signal will be 500khz and higher, the r t should be selected for 400khz. the slope compensation is set by the r t value, while the minimum slope compensation required to avoid subhar- monic oscillations is established by the inductor size, input voltage, and output voltage. since the synchroniza- tion frequency will not change the slopes of the inductor current waveform, if the inductor is large enough to avoid subharmonic oscillations at the frequency set by r t , then the slope compensation will be sufficient for all synchro- nization frequencies. the duty cycle of the sync signal can be used to set the relative phasing of the two channels for minimizing input ripple. the lt8616 does not operate in forced continuous mode regardless of the sync signal. never leave the sync/ mode pin floating. 2ms/div tr/ss 500mv/div v out 2v/div 8616 f05 temperature (c) ?50 ?15 pg threshold relative to fb (%) 10 5 0 ?5 ?10 15 75 100 125 150 ?25 0 25 8616 f06 50 pg high falling pg low rising pg high rising pg low falling lt 8616 8616f
19 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion figure 7. reverse v in protection for tw o independent input voltages pulse-skipping mode pulse-skipping mode is activated by applying logic high (above 2.4 v) or an external clock to the sync/mode pin. while in pulse-skipping mode, the oscillator operates continuously and sw transitions are aligned to the clock. during light loads, switch pulses are skipped to regulate the output and the quiescent current per channel will be several hundred a. full switching frequency is reached at lower output load than in burst mode operation. shorted and reversed input protection the lt8616 will tolerate a shorted output. the bottom switch current is monitored such that if inductor current is beyond safe levels, turn on of the top switch will be delayed until the inductor current falls to safe levels. a fault condition of one channel will not affect the operation of the other. there is another situation to consider in systems where the output will be held high when the input to the lt8616 is absent. this may occur in battery charging applications or in battery-backup systems where a battery or some other supply is or-ed with channel 1' s output. if the v in1 pin is allowed to float and either en/uv pin is held high ( either by a logic signal or because it is tied to v in1 ), then the lt8616s internal circuitry will pull its quiescent current through its sw1 pin. this is acceptable if the system can tolerate current draw in this state. if both en/uv pins are grounded the sw1 pin current will drop to near 1a. however, if the v in1 pin is grounded while channel 1 output is held high, regardless of en/uv1, parasitic body diodes inside the lt8616 can pull current from the output through the sw1 pin and the v in1 pin, damaging the ic v in2 is not connected to the shared internal supply and will not draw any current if left floating. if both v in1 and v in2 are floating, regardless of en/uv pins states, no-load will be present at the output of channel 2. however, if the v in2 pin is grounded while channel 2 output is held high, parasitic body diodes inside the lt8616 can pull current from the output through the sw2 pin and the v in2 pin, damaging the ic figure 7 shows a connection of the v in and en/uv pins that will allow the lt8616 to run only when the input voltage is present and that protects against a shorted or reversed input. d1 lt8616 gnd d2 8616 f07 v in2 v in2 v in1 v in1 en/uv1 en/uv2 pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 8 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents flow in the lt8616s v in pins, gnd pins, and the input capacitors (c in1 and c in2 ). the loop formed by the input capacitor should be as small as possible. when using a physically large input capacitor the resulting loop may become too large in which case using a small case/value capacitor placed close to the v in and gnd pins plus a larger capacitor further away is preferred. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. the sw and boost nodes should be as small as possible. finally, keep the fb and r t nodes small so that the ground traces will shield them from the sw and boost nodes. the exposed pad acts as a heat sink and is connected electrically to ground . the exposed pad of the tssop package is the only electrical connection to ground and must be soldered to ground. to keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the lt8616 to additional ground planes within the circuit board and on the bottom side. lt 8616 8616f
20 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion figure 8. recommended layout high temperature considerations for higher ambient temperatures, care should be taken in the layout of the pcb to ensure good heat sinking of the lt8616. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to large copper layers below with thermal vias; these layers will spread heat dissipated by the lt8616. placing additional vias can reduce thermal resistance further. the maximum load current should be derated as the ambient temperature approaches the maximum junction rating. power dissipation within the lt8616 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss. the die temperature is calculated by multiplying the lt8616 power dissipation by the thermal resistance from junction to ambient. the lt8616 will stop switching and indicate a fault condition if safe junction temperature is exceeded. open pins and shorting neighboring pins the lt8616 in tssop package is designed to tolerate faults to each pin. output voltages will stay at or below regulation if adjacent pins are shorted or a pin is left float - ing. see t able 4 for pin fault behavior when the lt8616 in the tssop package is connected in the application shown on figure 9. boost1 v in1 en/uv1 intv cc rt pg1 pg2 sync/mode tr/ss1 tr/ss2 sw1 lt8616 gnd fb1 bias boost2 sw2 8616 f09 fb2 0.1f 0.1f v out1 5v, 1.5a 10pf 2 47f 4.7f 1m 5v, 3.3v, 700khz step-down converter 200k v in 12v v out2 3.3v, 2.5a 10nf 10h 4.7h 1m 316k 1m 1m 187k 56.2k v in2 en/uv2 4.7f 5.6pf 47f 1f figure 9. see table 4 for open and short pin behavior of this application in the tssop package 8616 f08 r2 note: c vcc is below the package on the back side r1 l1 l2 r4 r3 c ff1 c bst1 c bst2 c ff2 c in2 c in1 r t r pg1 c out1 c out2 r pg2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 en/uv2 pg2 sw2 sw2 sw2 boost2 nc boost1 sw1 sw1 pg1 tr/ss1 fb1 fb1 tr/ss2 fb2 fb2 nc v in2 nc bias intv cc nc v in1 nc sync/mode en/uv1 rt 29 gnd lt 8616 8616f
21 for more information www.linear.com/lt8616 a pplica t ions i n f or m a t ion table 4. lt8616xfe pin fault behavior for circuit in figure 9 lt8616 pin float short to next pin en/uv2 1 part may be on or off part may be on or off pg2 2 no change no change sw2 3 no change no change sw2 4 no change no change sw2 5 no change out2 below regulation boost2 6 out2 below regulation no change nc 7 no change no change boost1 8 out1 below regulation out1 below regulation sw1 9 no change no change sw1 10 no change no change pg1 11 no change no change tr/ss1 12 no change no change fb1 13 no change out1 below regulation fb1 14 no change rt 15 switching frequency reduces ch1, ch2 off en/uv1 16 part may be on or off ch1, ch2 off sync/mode 17 no change no change nc 18 no change no change v in1 19 ch1, ch2 off no change nc 20 no change no change intv cc 21 out1, out2 below regulation no change bias 22 no change no change nc 23 no change no change v in2 24 ch2 off no change nc 25 no change no change fb2 26 no change no change fb2 27 no change out2 below regulation tr/ss2 28 no change lt 8616 8616f
22 for more information www.linear.com/lt8616 typical a pplica t ions boost1 v in1 en/uv1 intv cc rt pg1 pg2 sync/mode tr/ss1 tr/ss2 sw1 lt8616 gnd fb1 bias boost2 sw2 8616 ta02 fb2 0.1f 0.1f v out1 5v, 1.5a 10pf 100f 6.3v, 1210 4.7f v in 5.8v to 42v v out2 2.5v, 2.5a 10nf 3.3h ihlp-2525cz-01 ihlp-2020bz-01 1.5h 1m 464k 1m 1m 187k 14.7k v in2 en/uv2 4.7f 5.6pf 47f 10v, 1210 1f 5v, 2.5v, 2.05mhz step-down converter boost1 v in1 en/uv1 intv cc rt pg1 pg2 sync/mode tr/ss1 tr/ss2 sw1 lt8616 gnd fb1 bias boost2 sw2 8616 ta03 fb2 0.1f 0.1f xfl4020-102me xfl4020-472me v out1 3.3v, 0.8a 2 100f 6.3v, 1210 4.7f v in 4.2v to 42v v out1 v out2 0.79v, 2.5a 10nf 4.7h 1h 1m 1m 316k 3.3v 1.5a 0.7a 37.4k v in2 en/uv2 1m 4.7f 5.6pf 47f 10v, 1210 1f 10nf 3.3v, 0.79v, 1mhz 2-stage step-down converter, sequenced start-up lt 8616 8616f
23 for more information www.linear.com/lt8616 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe28 (eb) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation eb lt 8616 8616f
24 for more information www.linear.com/lt8616 ? linear technology corporation 2015 lt 0415 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8616 r ela t e d p ar t s typical a pplica t ion part number description comments lt8609 42v, 2a, 95% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3v, v in(max) = 42v, v out(min) = 0.8v, i q = 2.5a, i sd = <1a, msop-10e package lt8610a/ab 42v, 3.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd = <1a, msop-10e package lt8610ac 42v, 3.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3v, v in(max) = 42v, v out(min) = 0.8v, i q = 2.5a, i sd = <1a, msop-10e package lt8610 42v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd = <1a, msop-10e package lt8611 42v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a and input/output current limit/monitor v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd = <1a, 3 5 qfn-24 package lt8620 65v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 65v, v out(min) = 0.97v, i q = 2.5a, i sd = <1a, 3 5 qfn-24 package lt8614 42v, 4a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd = <1a, 3 5 qfn-18 package lt8612 42v, 6a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 3.0a, i sd = <1a, 3 6 qfn-28 package lt8640 42v, 6a, 96% efficiency, 3mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in(min) = 3.4v, v in(max) = 42v, v out(min) = 0.97v, i q = 2.5a, i sd = <1a, 3 4 qfn-18 package lt8602 42v, quad output (2.5a+1.5a+1.5a+1.5a) 95% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 25a v in(min) = 3v, v in(max) = 42v, v out(min) = 0.8v, i q = 25a, i sd = <1a, 6 6 qfn-40 package boost1 v in1 en/uv1 intv cc rt pg1 pg2 sync/mode tr/ss1 tr/ss2 sw1 lt8616 gnd fb1 bias boost2 sw2 8616 ta04 fb2 0.1f 0.1f v out1 5v, 1.5a 4.7pf 47f 10v, 1210 2.2f v in 5.8v to 42v v out2 3.3v, 2.5a 10nf 3.3h xal4030-332me xfl4020-222me 2.2h 1m 316k 1m 1m 187k 14.7k v in2 en/uv2 2.2f 4.7pf 22f 10v, 1210 1f 10nf 0.1f 0.1f 0.1f 0.1f 5v, 3.3v, 2.05mhz step-down converter lt 8616 8616f

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