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datasheet rl78/i1a renesas mcu true low power platform (as low as 156.25 a/mhz, and 0.60 a for rtc + lvd), 2.7 v to 5.5 v operation, 32 to 64 kbyte flash, for lighting control applications page 1 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 r01ds0171ej0210 rev.2.10 jul 31, 2013 1. outline 1.1 features ultra-low power technology ? 2.7 v to 5.5 v operation from a single supply ? stop (ram retained): 0.23 a, (lvd enabled): 0.31 a ? halt (rtc + lvd): 0.60 a ? operating: 156.25 a/mhz 16-bit rl78 cpu core ? delivers 41 dmips at maximum operating frequency of 32 mhz ? instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle ? mac: 16 x 16 to 32-bit result in 2 clock cycles ? 16-bit barrel shifter for shi ft & rotate in 1 clock cycle ? 1-wire on-chip debug function main flash memory ? density: 32 kb to 64 kb ? block size: 1 kb ? on-chip single voltage flash memory with protection from block erase/writing ? self-programming with secure boot swap function and flash shield window function data flash memory ? data flash with background operation ? data flash size: 4 kb ? erase cycles: 1 million (typ.) ? erase/programming voltage: 2.7 v to 5.5 v ram ? 2 kb to 4 kb size options ? supports operands or instructions ? back-up retention in all modes high-speed on-chip oscillator ? 32 mhz with +/ ? 1% accuracy over voltage (2.7 v to 5.5 v) and temperature ( ? 20 c to 85 c) ? pre-configured settings: 32 mhz, 24 mhz, 16 mhz, 12 mhz, 8 mhz, 4 mhz & 1 mhz reset and supply management ? power-on reset (por) monitor/generator ? low voltage detection (lvd) with 6 setting options (interrupt and/or reset function) data memory access (dma) controller ? up to 2 fully programmable channels ? transfer unit: 8- or 16-bit 16-bit timers kb0 to kb2, and kc0 for pwm output 16-bit timers kb0 to kb2: maximum 6 outputs (3 ch 2) ? smooth start function, dithering function, forced output stop function (unsyncronized with comparator or external interrupt), and interleave pfc function ? average resolution < 1 nsec output, 64 mhz (when using pll) + dithering option 16-bit timer kc0 (3 ch) ? pwm output gating function by interlocking with 16- bit timers kb0, kb1, and kb2 extended-function timers ? multi-function 16-bit timers: up to 8 channels ? real-time clock (rtc): 1 channel (full calendar and alarm function with watch correction function) ? interval timer: 12-bit, 1 channel ? 15 khz watchdog timer : 1 channel (window function) multiple communication interfaces ? up to 1 x i 2 c multi-master (sm/pm bus support) ? up to 1 x csi/spi (7-, 8-bit) ? up to 3 x uart (7-, 8-, 9-bit), dali support 1ch ? up to 1 x lin rich analog ? adc: up to 11 channels, 8/10-bit resolution, 2.125 s conversion time ? supports 2.7 v ? internal voltage reference (1.45 v) ? comparator: up to 6 channels, internal dac 3ch 8bit resolution, window comparator mode ? pga (x4 to x32):6 input ? on-chip temperature sensor safety features (iec or ul 60730 compliance) ? flash memory crc calculation ? ram parity error check ? ram/sfr write protection ? illegal memory access detection ? clock stop/ frequency detection ? adc self-test general purpose i/o ? 5v tolerant, high-current (up to 8.5 ma per pin) ? open-drain, internal pull-up support operating ambient temperature ? standard: ? 40 c to +105 c ? extend: ? 40 c to +125 c package type and pin count ssop: 20, 30, 38
rl78/i1a 1. outline page 2 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 { rom, ram capacities rl78/i1a flash rom data flash ram 20 pins 30 pins 38 pins 64 kb 4 kb 4 kb note ? r5f107ae r5f107de 32 kb 4 kb 2 kb r5f1076c r5f107ac ? note this is about 3 kb when the self-programmi ng function and data flash function are used.
rl78/i1a 1. outline page 3 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.2 ordering information pin count package operating ambient temperature part number t a = ? 40 to +105 c r5f1076cgsp#v0, r5f1076cgsp#x0 20 pin 20-pin plastic ssop (4.4 x 6.5) t a = ? 40 to +125 c r5f1076cmsp#v0, r5f1076cmsp#x0 t a = ? 40 to +105 c r5f107acgsp#v0, r5f107aegsp#v0, r5f107acgsp#x0, r5f107aegsp#x0 30 pin 30-pin plastic ssop (7.62 mm (300)) t a = ? 40 to +125 c r5f107acmsp#v0, r5f107aemsp#v0, r5f107acmsp#x0, r5f107aemsp#x0 t a = ? 40 to +105 c r5f107degsp#v0, r5f107degsp#x0 38 pin 38-pin plastic ssop (7.62 mm (300)) t a = ? 40 to +125 c r5f107demsp#v0, r5f107demsp#x0 caution the rl78/i1a has an on-ch ip debug functi on, which is pr ovided for development and evaluation. do not use the on-chip debug func tion in products designa ted for mass production, because the guaranteed number of rewritable times of the flash me mory may be exceeded when this function is used, a nd product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurri ng when the on-chip debug function is used.
rl78/i1a 1. outline page 4 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 figure 1-1. part number, memo ry size, and package of rl78/i1a part no. r 5 f 1 0 7 d e g x x x s p # v 0 package type: rom number (omitted with blank products) rom capacity: rl78/i1a group renesas mcu renesas semiconductor product sp: ssop, 0.65 mm pitch c: 32 kb e: 64 kb pin count: 6: 20-pin a: 30-pin d: 38-pin classification: g: operating ambient temperature: ? 40 c to 105 c m: operating ambient temperature: ? 40 c to 125 c memory type: f: flash memory package specification: #v0: tray (ssop) #x0: embossed tape (ssop)
rl78/i1a 1. outline page 5 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.3 pin configuration (top view) 1.3.1 20-pin products ? 20-pin plastic tssop (4.4 x 6.5) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 p22/ani2/cmp0p p24/ani4/cmp1p p25/ani5/cmp2p p147/cmpcom/ani18/(cmp3p) p10/txd0/tkco00/intp20/scla0/(dalitxd4) p11/rxd0/tkco01/intp21/sdaa0/(ti07)/(dalirxd4)/(txrx4) p200/tkbo00/intp22 p201/tkbo01 p202/tkbo10/(intp21) p203/tkbo11/tkco02/(intp20) p21/ani1 /av refm p20/ani0 /av refp p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior1) or the input switch control register (isc). 3. the shared function cmp3p can be assigned to p147 by setting the cmpsel0 bit in the comparator input switch control register (cmpsel).
rl78/i1a 1. outline page 6 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.3.2 30-pin products ? 30-pin plastic ssop (7.62 mm (300)) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p21/ani1 /av refm p22/ani2/cmp0p p24/ani4/cmp1p p25/ani5/cmp2p p26/ani6/cmp3p p27/ani7/cmp4p p147/cmpcom/ani18 p10/txd0/tkco00/intp20/scla0/(dalitxd4) p11/rxd0/tkco01/intp21/sdaa0/(ti07)/(dalirxd4)/(txrx4) p200/tkbo00/intp22 p201/tkbo01 p202/tkbo10/(intp21) p203/tkbo11/tkco02/(intp20) p204/tkbo20/tkco03 p205/tkbo21/tkco04/dalitxd4 p20/ani0 /av refp p03/rxd1/cmp5p/ani16 p02/txd1/ani17 p120/ani19 p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p31/ti03/to03/intp4 p77/intp11 p206/tkco05/dalirxd4/txrx4/intp23 caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior1) or the input switch control register (isc).
rl78/i1a 1. outline page 7 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.3.3 38-pin products ? 38-pin plastic ssop (7.62 mm (300)) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p20/ani0/av refp p03/rxd1/cmp5p/ani16 p02/txd1/ani17 p120/ani19 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p31/ti03/to03/intp4 p77/intp11 p76/intp10 p75/intp9 p06/ti06/to06 p21/ani1/av refm p22/ani2/cmp0p p24/ani4/cmp1p p25/ani5/cmp2p p26/ani6/cmp3p p27/ani7/cmp4p p147/cmpcom/ani18 p10/so00/txd0/tkco00/intp20/scla0/(dalitxd4) p11/si00/rxd0/tkco01/intp21/sdaa0/(ti07)/(dalirxd4)/(txrx4) p12/sck00/(tkco03) p200/tkbo00/intp22 p201/tkbo01 p202/tkbo10/(intp21) p203/tkbo11/tkco02/(intp20) p204/tkbo20/tkco03 p205/tkbo21/tkco04/dalitxd4 p206/tkco05/dalirxd4/txrx4/intp23 p30/intp3/rtc1hz p05/ti05/to05 caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior1) or the input switch control register (isc).
rl78/i1a 1. outline page 8 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.4 pin identification ani0 to ani2, ani4 to ani7, ani16 to ani19: analog input av refm : analog reference voltage minus av refp : analog reference voltage plus cmp0p to cmp5p: comparator analog input cmpcom: comparator external reference voltage exclk: external clo ck input (main system clock) exclks: external clock input (subsystem clock) intp0, intp3, intp4, intp9, intp10, intp11, intp20 to intp23: interrupt request from peripheral p02, p03, p05, p06: port 0 p10 to p12: port 1 p20 to p22, p24 to p27: port 2 p30, p31: port 3 p40: port 4 p75 to p77: port 7 p120 to p124: port 12 p137: port 13 p147: port 14 p200 to p206: port 20 regc: regulator capacitance reset: reset rtc1hz: real-time clock correction clock (1 hz) output rxd0, rxd1, dalirxd4: receive data sck00: serial clock input/output scla0: serial clock input/output sdaa0: serial da ta input/output si00: serial data input so00: serial data output ti03, ti05, ti06, ti07: timer input to03, to05, to06, tkbo00, tkbo01 to tkbo20, tkbo21, tkco00-tkco05: timer output tool0: data input/output for tool txrx4: serial data in put/output for single wired uart txd0, txd1 dalitxd4: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillator (main system clock) xt1, xt2: crystal oscillator (subsystem clock)
rl78/i1a 1. outline page 9 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.5 block diagram 1.5.1 20-pin products port 1 p10, p11 port 2 p20 to p22, p24, p25 5 port 4 2 port 12 p121, p122 p40 voltage regulator regc interrupt control ram data flash memory power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 rxd0/p11 txd0/p10 timer array unit (8ch) ch2 ch3 ch0 ch1 ch4 ch5 ch6 ch7 intp0/p137 rxd0/p11 a/d converter 5 3 4 ani0/p20 to ani2/p22, ani4/p24, ani5/p25 cmp0p/p22, cmp1p/p24, cmp2p/p25, (cmp3p/p147) av refp /p20 cmpcom/p147 av refm /p21 2 port 13 p137 (ti07/p11) bcd adjustment v ss v dd serial interface iica sdaa0/p11 scla0/p10 intp22/p200 intp20/p10(intp20/p203) intp21/p11(intp21/p202) multiplier& divider, mulitiply- accumulator programmable gain amplifier 3 cmp0p/p22, cmp1p/p24, cmp2p/p25, (cmp3p/p147) comparator 3 16-bit timer kb0, kb1 16-bit timer kc0 ani18/p147 serial array unit4 (2ch) uart4 dali, dmx512 single-wire uart lin-bus, dmx512 (dalirxd4/p11) (dalitxd4/p10) (txrx4/p11) direct memory access control port 20 p200 to p203 4 port 14 p147 tkbo00/p200, tkbo01/p201, tkbo10/p202, tkbo11/p203 tkco00/p10, tkco01/p11, tkco02/p203 rxd0/p11 (lin-bus, dmx512) rl78 cpu core code flash memory data flash memory low-speed on-chip oscillator 12- bit interval timer window watchdog timer real-time clock crc remarks 1. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior1) or the input switch control register (isc). 2. the shared function cmp3p can be assigned to p147 by setting the cmpsel0 bit in the comparator input switch control register (cmpsel).
rl78/i1a 1. outline page 10 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.5.2 30-pin products port 1 p10, p11 port 2 p20 to p22, p24 to p27 7 port 3 p31 port 4 2 port 12 p121, p122 p40 voltage regulator regc interrupt control ram data flash memory power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 rxd0/p11 txd0/p10 rxd1/p03 txd1/p02 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ch6 ch7 intp11/p77 intp0/p137 intp4/p31 rxd0/p11 a/d converter 7 6 6 ani0/p20 to ani2/p22, ani4/p24 to ani7/p27 cmp0p/p22, cmp1p/p24 to cmp4p/p27, cmp5p/p03 av refp /p20 cmpcom/p147 av refm /p21 2 p120 port 13 p137 (ti07/p11) bcd adjustment v ss v dd serial interface iica sdaa0/p11 scla0/p10 intp22/p200 intp23/p206 intp20/p10(intp20/p203) intp21/p11(intp21/p202) multiplier& divider, mulitiply- accumulator port 0 p02, p03 2 programmable gain amplifier 6 cmp0p/p22, cmp1p/p24 to cmp4p/p27, cmp5p/p03 comparator 6 16-bit timer kb0 to kb2 16-bit timer kc0 4 ani16/p03, ani17/p02, ani18/p147, ani19/p120 serial array unit4 (2ch) uart4 single-wire uart dalirxd4/p206(dalirxd4/p11) dalitxd4/p205(dalitxd4/p10) txrx4/p206(txrx4/p11) direct memory access control port 7 p77 port 20 p200 to p206 7 port 14 p147 tkbo00/p200, tkbo01/p201, tkbo10/p202, tkbo11/p203, tkbo20/p204, tkbo21/p205 tkco00/p10, tkco01/p11, tkco02/p203,tkco03/p204, tkco04/p205,tkco05/p206 rxd0/p11 ( lin-bus, dmx512 ) rl78 cpu core code flash memory data flash memory lin-bus, dmx512 window watchdog timer real-time clock low-speed on-chip oscillator 12- bit interval timer crc dali, dmx512 remark functions in parentheses in the above figure c an be assigned via settings in the peripheral i/o redirection register (pior1) or the input switch control register (isc).
rl78/i1a 1. outline page 11 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.5.3 38-pin products port 1 p10 to p12 port 2 p20 to p22, p24 to p27 7 port 3 p30, p31 2 port 4 3 port 12 p121 to p124 p40 voltage regulator regc interrupt control ram data flash memory power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 rxd0/p11 txd0/p10 rxd1/p03 txd1/p02 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ti05/to05/p05 ch6 ti06/to06/p06 ch7 intp9/p75 to intp11/p77 intp0/p137 intp3/p30, intp4/p31 rxd0/p11 a/d converter 7 6 6 ani0/p20 to ani2/p22, ani4/p24 to ani7/p27 cmp0p/p22, cmp1p/p24 to cmp4p/p27, cmp5p/p03 av refp /p20 cmpcom/p147 av refm /p21 4 p120 port 13 p137 (ti07/p11) bcd adjustment sck00/p12 so00/p10 si00/p11 csi00 v ss v dd serial interface iica sdaa0/p11 scla0/p10 3 2 intp22/p200 intp23/p206 intp20/p10(intp20/p203) intp21/p11(intp21/p202) multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p02, p03, p05, p06 4 programmable gain amplifier 6 cmp0p/p22, cmp1p/p24 to cmp4p/p27, cmp5p/p03 comparator 6 16-bit timer kc0 4 ani16/p03, ani17/p02, ani18/p147, ani19/p120 serial array unit4 (2ch) uart4 single-wire uart dalirxd4/p206(dalirxd4/p11) dalitxd4/p205(dalitxd4/p10) txrx4/p206(txrx4/p11) direct memory access control port 7 p75 to p77 3 port 20 p200 to p206 7 port 14 p147 tkbo00/p200, tkbo01/p201, tkbo10/p202, tkbo11/p203, tkbo20/p204, tkbo21/p205 tkco00/p10, tkco01/p11, tkco02/p203,tkco03/p204(tkco03/p12), tkco04/p205,tkco05/p206 rxd0/p11 ( lin-bus, dmx512 ) rl78 cpu core code flash memory data flash memory 16-bit timer kb0 to kb2 lin-bus, dmx512 window watchdog timer real-time clock low-speed on-chip oscillator 12- bit interval timer crc dali, dmx512 remark functions in parentheses in the above figure c an be assigned via settings in the peripheral i/o redirection register (pior1) or the input switch control register (isc).
rl78/i1a 1. outline page 12 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 1.6 outline of functions caution this outline describes the f unctions at the time when periphera l i/o redirection register (pior1) is set to 00h. (1/3) 20-pin 30-pin 38-pin item r5f1076c r5f107ac r5f107ae r5f107de code flash memory (kb) 32 32 64 64 data flash memory (kb) 4 4 4 4 ram (kb) 2 2 4 note 1 4 note 1 memory space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 5.5 v main system clock high-speed on-chip oscillator hs (high-speed main) mode: 1 to 32 mhz (v dd = 2.7 to 5.5 v), ls (low-speed main) mode: 1 to 8 mhz (v dd = 2.7 to 5.5 v) clock for 16-bit timers kb0 to kb2, and kc0 64 mhz (typ.) subsystem clock (38-pin products only) xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz low-speed on-chip oscillator 15 khz (typ.) general-purpose register (8-bit register 8) 4 banks 0.03125 s (high-speed on-chip oscillator: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) minimum instruction execution time 30.5 s (subsystem clock: f sub = 32.768 khz operation) (38-pin products only) instruction set ? 8-bit operation, 16-bit operation ? multiplication (8 bits 8 bits) ? bit manipulation (set, reset, test, and boolean operation), etc. i/o port total 16 26 34 cmos i/o 13 23 29 cmos input 3 3 5 cmos output ? ? ? 16-bit timer tau 8 channels (no timer output) 8 channels (timer output: 1, pwm output: 1 note 2 ) 8 channels (timer outputs: 3, pwm outputs: 3 note 2 ) 16-bit timer kb 2 channels (pwm outputs: 4) 3 channels (pwm outputs: 6) timer 16-bit timer kc 1 channel (pwm outputs: 3) 1 channel (pwm outputs: 6) notes 1. this is about 3 kb when the self-programming func tion and data flash function are used. (for details, see chapter 3 ) 2. the number of pwm outputs varies depending on the setting of channels in use (the number of masters and slaves). (see 6.8.3 operation as multiple pwm output function ).
rl78/i1a 1. outline page 13 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (2/3) 20-pin 30-pin 38-pin item r5f1076c r5f 107ac, r5f107ae r5f 107de watchdog timer 1 channel timer real-time clock (rtc) 1 channel notes 1, 2 12-bit interval timer (it) 1 channel rtc output ? 1 1 hz (subsystem clock: f sub = 32.768 khz) 8/10-bit resolution a/d converter 6 channels 11 channels 11 channels comparator 4 channels 6 channels 6 channels programmable gain amplifier 1 channel input note 3 4 channels 6 channels 6 channels serial interface [20-pin] ? uart (supporting lin-bus and dmx512): 1 channel ? uart (supporting dali communication): 1 channel [30-pin products] ? uart (supporting lin-bus and dmx512): 1 channel ? uart: 1 channel ? uart (supporting dali communication): 1 channel [38-pin products] ? csi: 1 channel/uart (supporting lin-bus and dmx512): 1 channel ? uart: 1 channel ? uart (supporting dali communication): 1 channel i 2 c bus 1 channel 1 channel 1 channel multiplier and divider/multiply- accumulator ? 16 bits 16 bits = 32 bits (unsigned or signed) ? 32 bits 32 bits = 32 bits (unsigned) ? 16 bits 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 2 channels internal 27 30 30 vectored interrupt sources external 7 10 11 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note 4 ? internal reset by ram parity error ? internal reset by illegal-memory access notes 1. the subsystem clock (f sub ) can be selected as the operating clock only for 38-pin products. 2. the 20- and 30-pin products can only be used as the constant-period interrupt function. 3. the comparator input is alternativel y used with analog input pin (ani pin). 4. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not iss ued by emulation with the in -circuit emulator or on- chip debug emulator.
rl78/i1a 1. outline page 14 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (3/3) 20-pin 30-pin 38-pin item r5f1076c r5f 107ac, r5f107ae r5f 107de power-on-reset circuit ? power-on-reset: 1.51 0.03 v ? power-down-reset: 1.50 0.03 v voltage detector ? rising edge: 2.81 v to 4.06 v (6 stages) ? falling edge: 2.75 v to 3.98 v (6 stages) on-chip debug function provided power supply voltage v dd = 2.7 to 5.5 v operating ambient temperature t a = ? 40 to +105 c t a = ? 40 to +125 c
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 15 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2. electrical specifications (t a = ? 40 to +105 c) target products : t a = ? 40 to +105 c r5f1076cgsp#v0, r5f1076cgsp#x0, r5f107acgsp#v0, r5f107acgsp#x0, r5f107aegsp#v0, r5f107aegsp#x0, r5f107degsp#v0, r5f107degsp#x0 caution the rl78/i1a have an on-chip debug f unction, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guarant eed number of rewritable ti mes of the flash memory may be exceeded when this function is used, a nd product reliability therefore cannot be guaranteed. renesas electronics is not liabl e for problems occurri ng when the on-chip debug function is used.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 16 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit supply voltage v dd ? 0.5 to +6.5 v regc pin input voltage v iregc regc ? 0.3 to +2.8 and ? 0.3 to v dd +0.3 note 1 v input voltage v i1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120 to p124, p137, p147, p200 to p206, exclk, exclks, reset ? 0.3 to v dd +0.3 note 2 v output voltage v o1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 ? 0.3 to v dd +0.3 note 2 v analog input voltage v ai1 ani0 to ani2, ani4 to ani7, ani16 to ani19 ? 0.3 to v dd +0.3 and ? 0.3 to av ref(+) +0.3 notes 2, 3 v notes 1. connect the regc pin to vss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. do not exceed av ref(+) + 0.3 v in case of a/d conversion target pin . caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the abso lute maximum ratings are rated values at which the product is on the verge of suffering physi cal damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remarks 1. unless specified otherwise, the char acteristics of alternate-function pins are the same as those of the port pins. 2. av ref (+) : + side reference voltage of the a/d converter. 3. v ss : reference voltage
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 17 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit per pin p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 ? 40 ma p02, p03, p40, p120 ? 70 ma i oh1 total of all pins ? 170 ma p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 ? 100 ma per pin ? 0.5 ma output current, high i oh2 total of all pins p20 to p22, p24 to p27 ? 2 ma per pin p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 40 ma p02, p03, p40, p120 70 ma i ol1 total of all pins 170 ma p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 100 ma per pin 1 ma output current, low i ol2 total of all pins p20 to p22, p24 to p27 5 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +105 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physi cal damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 18 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.2 oscillator characteristics 2.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter resonator recommended circuit conditions min. typ. max. unit x1 clock oscillation frequency (f x ) note ceramic resonator/ crystal resonator c1 x2 x1 c2 v ss rd 1.0 20.0 mhz xt1 clock oscillation frequency (f xt ) note crystal resonator xt1 xt2 c4 c3 rd v ss 32 32.768 35 khz note indicates only permissible oscillator frequency ranges. re fer to ac characteristics for instruction execution time. request evaluation by the manufacturer of t he oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator cl ock after a reset release, check the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. dete rmine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 19 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.2.2 on-chip oscillator characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency note 1 f ih 1 32 mhz t a = ? 20 to 85 c ? 1 +1 % high-speed on-chip oscillator clock frequency accuracy note 2 t a = ? 40 to 105 c ? 1.5 +1.5 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy ? 15 +15 % notes 1. frequency can be selected in a high-speed on-chip oscillator. selected by bits 0 to 3 of option byte (000c2h/010c2h). 2. this indicates the oscillator characteristics only. refer to ac characteristics for instruction execution time. 2.2.3 pll characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit high-speed system clock is selected (f mx = 4 mhz) 3.94 4.00 4.06 mhz pll input clock frequency note f pllin high-speed on-chip oscillator clock is selected (f ih = 4 mhz) 3.94 4.00 4.06 mhz pll output clock frequency note f pll f pllin 16 mhz note this only indicates the oscillator charac teristics. refer to ac characteri stics for instruction execution time.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 20 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 note 2 ma per pin for p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd < 4.0 v ? 1.0 ma 4.0 v v dd 5.5 v ? 12.0 ma total of p02, p03, p40, p120 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v ? 4.0 ma 4.0 v v dd 5.5 v ? 30.0 ma total of p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v ? 10.0 ma 4.0 v v dd 5.5 v ? 30.0 ma i oh1 total of all pins (when duty 70% note 3 ) 2.7 v v dd < 4.0 v ? 14.0 ma per pin for p20 to p22, p24 to p27 2.7 v v dd 5.5 v ? 0.1 note 2 ma output current, high note 1 i oh2 total of all pins (when duty 70% note 3 ) 2.7 v v dd 5.5 v ? 0.7 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the dut y factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p02, p10 to p12 do not output hi gh level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 21 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 8.5 note 2 ma per pin for p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd < 4.0 v 1.5 note 2 ma 4.0 v v dd 5.5 v 40.0 ma total of p02, p03, p40, p120 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v 7.5 ma 4.0 v v dd 5.5 v 40.0 ma total of p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v 17.5 ma 4.0 v v dd 5.5 v 80.0 ma i ol1 total of all pins (when duty 70% note 3 ) 2.7 v v dd < 4.0 v 25.0 ma per pin for p20 to p22, p24 to p27 2.7 v v dd 5.5 v 0.4 note 2 ma output current, low note 1 i ol2 total of all pins (when duty 70% note 3 ) 2.7 v v dd 5.5 v 2.8 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the v ss pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the dut y factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 22 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit v ih1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120 to p124, p137, p147, p200 to p206, exclk, exclks, reset normal input buffer 0.8v dd v dd v ttl input buffer 4.0 v v dd 5.5 v 2.1 v dd v ttl input buffer 3.3 v v dd < 4.0 v 2.0 v dd v input voltage, high v ih2 p03, p10, p11 ttl input buffer 2.7 v v dd < 3.3 v 1.5 v dd v v il1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40,p75 to p77, p120 to p124, p137, p147, p200 to p206, exclk, exclks, reset normal input buffer 0 0.2v dd v ttl input buffer 4.0 v v dd 5.5 v 0 0.8 v ttl input buffer 3.3 v v dd < 4.0 v 0 0.5 v input voltage, low v il2 p03, p10, p11 ttl input buffer 2.7 v v dd < 3.3 v 0 0.32 v cautions the maximum value of v ih of pins p02, p10 to p12 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of the port pins.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 23 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v v oh1 p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd 5.5 v, i oh1 = ? 1.0 ma v dd ? 0.5 v output voltage, high v oh2 p20 to p22, p24 to p27 2.7 v v dd 5.5 v, i oh2 = ? 100 a v dd ? 0.5 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 4.0 v v dd 5.5 v, i ol1 = 4.0 ma 0.4 v v ol1 p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.4 v output voltage, low v ol2 p20 to p22, p24 to p27 2.7 v v dd 5.5 v, i ol2 = 400 a 0.4 v caution p02, p10 to p12 do not output hi gh level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 24 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit i lih1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120, p137, p147, p200 to p206, reset v i = v dd 1 a in input port or external clock input 1 a input leakage current, high i lih2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in resonator connection 10 a i lil1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120, p137, p147, p200 to p206, reset v i = v ss ? 1 a in input port or external clock input ? 1 a input leakage current, low i lil2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in resonator connection ? 10 a on-chip pll-up resistance r u p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 v i = v ss , in input port 10 20 100 k remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 25 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.3.2 supply current characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 5.0 7.5 ma f ih = 32 mhz note 3 v dd = 3.0 v 5.0 7.5 ma v dd = 5.0 v 3.9 5.8 ma f ih = 24 mhz note 3 v dd = 3.0 v 3.9 5.8 ma v dd = 5.0 v 2.9 4.2 ma hs (high- speed main) mode note 5 f ih = 16 mhz note 3 v dd = 3.0 v 2.9 4.2 ma ls (low- speed main) mode note 5 f ih = 8 mhz note 3 , t a = ? 40 to + 85 c v dd = 3.0 v 1.3 2.0 ma square wave input 3.2 4.9 ma f mx = 20 mhz note 2 , v dd = 5.0 v resonator connection 3.3 5.0 ma square wave input 3.2 4.9 ma f mx = 20 mhz note 2 , v dd = 3.0 v resonator connection 3.3 5.0 ma square wave input 2.0 2.9 ma f mx = 10 mhz note 2 , v dd = 5.0 v resonator connection 2.0 2.9 ma square wave input 2.0 2.9 ma hs (high- speed main) mode note 5 f mx = 10 mhz note 2 , v dd = 3.0 v resonator connection 2.0 2.9 ma square wave input 1.2 1.8 ma ls (low- speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 3.0 v, t a = ? 40 to + 85 c resonator connection 1.2 1.8 ma v dd = 5.0 v 5.4 8.5 ma f ih = 4 mhz note 3 f pll = 64 mhz, f clk = 32 mhz v dd = 3.0 v 5.4 8.5 ma v dd = 5.0 v 3.3 5.7 ma hs (high- speed main) mode note 5 f ih = 4 mhz note 3 f pll = 64 mhz, f clk = 16 mhz v dd = 3.0 v 3.3 5.7 ma square wave input 4.2 6.0 a f sub = 32.768 khz note 4 t a = ? 40 c resonator connection 4.4 6.2 a square wave input 4.2 6.0 a f sub = 32.768 khz note 4 t a = +25 c resonator connection 4.4 6.2 a square wave input 4.3 7.2 a f sub = 32.768 khz note 4 t a = +50 c resonator connection 4.5 7.4 a square wave input 4.4 8.1 a f sub = 32.768 khz note 4 t a = +70 c resonator connection 4.6 8.3 a square wave input 5.2 11.4 a f sub = 32.768 khz note 4 t a = +85 c resonator connection 5.4 11.6 a square wave input 6.9 20.8 a supply current note 1 i dd1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +105 c resonator connection 7.1 21.0 a ( notes and remarks are listed on the next page.)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 26 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 notes 1. total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, comparator, programmable gain amplifier, lvd circuit, i/o port, and on-chip pull-up/pull- down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-spee d system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the curr ent flowing into the rtc, 12- bit interval timer, and watchdog timer. 5. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz ls (low-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 8 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 c
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 27 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 0.72 2.9 ma f ih = 32 mhz note 4 v dd = 3.0 v 0.72 2.9 ma v dd = 5.0 v 0.57 2.3 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.57 2.3 ma v dd = 5.0 v 0.50 1.7 ma hs (high- speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.50 1.7 ma ls (low- speed main) mode note 7 f ih = 8 mhz note 4 , t a = ? 40 to +85 c v dd = 3.0 v 320 910 a square wave input 0.40 1.9 ma f mx = 20 mhz note 3 , v dd = 5.0 v resonator connection 0.50 2.0 ma square wave input 0.40 1.9 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.50 2.0 ma square wave input 0.24 1.02 ma f mx = 10 mhz note 3 , v dd = 5.0 v resonator connection 0.30 1.08 ma square wave input 0.24 1.02 ma hs (high- speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.30 1.08 ma square wave input 130 720 a ls (low- speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 3.0 v, t a = ? 40 to +85 c resonator connection 170 760 a v dd = 5.0 v 1.15 4.0 ma f ih = 4 mhz note 4 f pll = 64 mhz, f clk = 32 mhz v dd = 3.0 v 1.15 4.0 ma v dd = 5.0 v 0.95 3.2 ma hs (high- speed main) mode note 7 f ih = 4 mhz note 4 f pll = 64 mhz, f clk = 16 mhz v dd = 3.0 v 0.95 3.2 ma square wave input 0.28 0.70 a f sub = 32.768 khz note 5 t a = ? 40 c resonator connection 0.47 0.89 a square wave input 0.33 0.70 a f sub = 32.768 khz note 5 t a = +25 c resonator connection 0.52 0.89 a square wave input 0.41 1.90 a f sub = 32.768 khz note 5 t a = +50 c resonator connection 0.60 2.09 a square wave input 0.54 2.80 a f sub = 32.768 khz note 5 t a = +70 c resonator connection 0.73 2.99 a square wave input 1.27 6.10 a f sub = 32.768 khz note 5 t a = +85 c resonator connection 1.46 6.29 a square wave input 3.04 15.5 a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +105 c resonator connection 3.23 15.7 a t a = ? 40 c 0.18 0.50 a t a = +25 c 0.23 0.50 a t a = +50 c 0.27 1.70 a t a = +70 c 0.44 2.60 a t a = +85 c 1.17 5.90 a supply current note 1 i dd3 note 6 stop mode note 8 t a = +105 c 2.94 15.3 a ( notes and remarks are listed on the next page.)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 28 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 notes 1. total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, comparator, programmable gain amplifier, lvd circuit, i/o port, and on-chip pull-up/pull- down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-spee d system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. 7. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 32 mhz ls (low-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 8 mhz 8. regarding the value for current operate the subsystem cl ock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25 c
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 29 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-speed on- chip oscillator operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma a/d converter operating current i adc notes 1, 6 when conversion at maximum speed low voltage mode, av refp = v dd = 3.0 v 0.5 0.7 ma a/d converter reference voltage current i adref note 1 75.0 a temperature sensor operating current i tmps note 1 75.0 a lvd operating current i lvi notes 1, 7 0.08 a self- programming operating current i fsp notes 1, 8 2.50 12.2 ma av refp = v dd = 5.0 v 0.21 0.31 ma programmable gain amplifier operating current i pga note 9 av refp = v dd = 3.0 v 0.18 0.29 ma av refp = v dd = 5.0 v 41.4 62 a i cmp note 10 when one comparator channel is operating av refp = v dd = 3.0 v 37.2 59 a av refp = v dd = 5.0 v 14.8 26 a comparator operating current i vref when one internal reference voltage circuit is operating av refp = v dd = 3.0 v 8.9 20 a av refp = v dd = 5.0 v 3.2 5.1 a programmable gain amplifier/ comparator reference current source i iref note 11 av refp = v dd = 3.0 v 2.9 4.9 a bgo operating current i bgo note 12 2.50 12.2 ma the mode is performed 0.50 1.1 ma adc operation the a/d conversion operations are performed, standard mode, av refp = v dd = 5.0 v 2.0 3.04 ma snooze operating current i snoz note 1 csi/uart operation 0.70 1.54 ma ( notes and remarks are listed on the next page.)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 30 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 notes 1. current flowing to the v dd . 2. when the high-speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (e xcluding the operating current of the low-speed on- chip ocsillator and the xt1 oscillator). the supply curr ent of the rl78 microcontro llers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. when the low-speed on-chip o scillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (excluding the operating current of the xt1 oscillator and f il operating current). the current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. 5. current flowing only to the watchdog timer (inclu ding the operating current of the low-speed on-chip oscillator). the supply current of t he rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer is in operation. 6. current flowing only to the a/d converter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 7. current flowing only to the lvd circuit. the supply cu rrent of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. 8. current flowing during self-programming operation. 9. current flowing only to the programmable gain am plifier. the supply cu rrent value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 , and i pga , when the programmable gain amplifier is operating in operating mode or in halt mode. 10. current flowing only to the comparator. the supply current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 , and i cmp , when the comparator is operating. 11. this is the current required to flow to v dd pin of the current circuit that is used as the programmable gain amplifier and the comparator. 12. current flowing only during data flash rewrite. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 c 5. example of calculating current value when us ing programmable gain amplifier and comparator. examples 1) typ. operating current value when th ree comparator channels, one internal reference voltage generator, and pga are operating (when av refp = v dd = 5.0 v) i cmp 3 + i vref + i pga + i iref = 41.4 [ a] 3 + 14.8 [ a] 1 + 210 [ a] + 3.2 [ a] = 352.2 [ a] examples 2) typ. operating cu rrent value when using two com parator channels, without using internal reference voltage generator (when av refp = v dd = 5.0 v) i cmp 2 + i iref = 41.4 [ a] 2 + 3.2 [ a] = 86.0 [ a]
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 31 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.4 ac characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit hs (high-speed main) mode 0.03125 1 s main system clock (f main ) operation ls (low-speed main) mode t a = ? 40 to +85 c 0.125 1 s subsystem clock (f sub ) operation 28.5 30.5 31.3 s hs (high-speed main) mode 0.03125 1 s instruction cycle (minimum instruction execution time) t cy in the self programming mode ls (low-speed main) mode t a = ? 40 to +85 c 0.125 1 s f ex 1.0 20.0 mhz external system clock frequency f exs 32 35 khz t exh , t exl 24 ns external system clock input high- level width, low-level width t exhs , t exls 13.7 s ti03, ti05, ti06, ti07 input high- level width, low-level width t tih , t til 2/f mck +10 ns 4.0 v v dd 5.5 v 8 mhz hs (high-speed main) mode 2.7 v v dd < 4.0 v 4 mhz 4.0 v v dd 5.5 v 4 mhz to03, to05, to06, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21, tkco00 to tkco05 output frequency (when duty = 50%) f to ls (low-speed main) mode, t a = ? 40 to +85 c 2.7 v v dd < 4.0 v 2 mhz interrupt input high-level width, low-level width t inth , t intl intp0, intp3, intp4, intp9 to intp11, intp20 to intp23 1 s reset low-level width t rsl 10 s remark f mck : timer array unit operation clock frequency (operation clock to be set by the cks0n bit of timer mode register 0n (tmr0n). n: channel number (n = 0 to 7))
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 32 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 minimum instruction execution time dur ing main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 0.03125 0.05 when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected cycle time t cy [ms] supply voltage v dd [v] t cy vs v dd (ls (low-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 2.7 0.125 cycle time t cy [ms] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 33 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 ac timing test points v ih v il test points v ih v il external system clock timing exclk 0.7v dd (min.) 0.3v dd (max.) 1/f ex t exl t exh ti/to timing ti03, ti05, ti06, ti07 t til t tih to03, to05, to06, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21, tkco00-tkco05 1/f to interrupt request input timing intp0, intp3, intp4, intp9 to intp11, intp20 to intp23 t intl t inth reset input timing reset t rsl
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 34 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.5 peripheral functions characteristics 2.5.1 serial array unit 0, 4 (uart0, uart1, csi00, dali/uart4) (1) during communication at same potential (uart mode) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit 2.7 v v dd 5.5 v f mck /6 f mck /6 bps transfer rate note 1 theoretical value of the maximum transfer rate f mck = f clk note 2 5.3 1.3 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (2.7 v v dd 5.5 v), ta = ? 40 to +85 c caution select the normal input buffer for the rxdq pi n and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (duri ng communication at same potential) user's device txdq rxdq rx tx rl78/i1a uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq caution select the normal input buffer for the rxdq pi n and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). remarks 1. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03))
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 35 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (2) during communication at same pot ential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit sckp cycle time t kcy1 t kcy1 4/f clk 125 500 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 12 t kcy1 /2 ? 50 ns sckp high-/low-level width t kh1 , t kl1 2.7 v v dd 5.5 v t kcy1 /2 ? 18 t kcy1 /2 ? 50 ns 4.0 v v dd 5.5 v 44 110 ns sip setup time (to sckp ) note 1 t sik1 2.7 v v dd 5.5 v 44 110 ns sip hold time (from sckp ) note 2 t ksi1 19 19 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 25 25 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. 5 . operating condtions of ls (low-speed main) mode is t a = -40 to +85 c. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remarks 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00))
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 36 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (3) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbo l conditions min. max. min. max. unit 20 mhz < f mck 8/f mck ? ns 4.0 v v dd 5.5 v f mck 20 mhz 6/f mck 6/f mck ns 16 mhz < f mck 8/f mck ? ns sckp cycle time note 5 t kcy2 2.7 v v dd 5.5 v f mck 16 mhz 6/f mck 6/f mck ns sckp high-/low- level width t kh2 , t kl2 t kcy2 /2 t kcy2 /2 ns sip setup time (to sckp ) note 1 t sik2 1/f mck +20 1/f mck +30 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck +31 1/f mck +31 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2/f mck + 44 2/f mck + 110 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. 5. transfer rate in the snooze mode: max. 1 mbps 6. operating condtions of ls (low-speed main) mode is t a = -40 to +85 c. caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port out put mode register g (pomg). remarks 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 37 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 csi mode connection diagram (duri ng communication at same potential) user's device sckp sop sck si sip so rl78/i1a csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00) 2. m: unit number, n: channel number (mn = 00)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 38 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (4) communication at different potential (2.5 v, 3 v) (uart mode) (1/2) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit 4.0 v v dd 5.5 v,2.7 v v b 4.0 v f mck /6 note 1 f mck /6 note 1 bps theoretical value of the maximum transfer rate f mck = f clk note 2 5.3 1.3 mbps 2.7 v v dd < 4.0 v,2.3 v v b 2.7 v f mck /6 note 1 f mck /6 note 1 bps transfer rate recep- tion theoretical value of the maximum transfer rate f mck = f clk note 2 5.3 1.3 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the maximum operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 32 mhz (2.7 v v dd 5.5 v) ls (low-speed main) mode: 8 mhz (2.7 v v dd 5.5 v), t a = -40 to +85 c. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 39 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (4) communication at different potential (2.5 v, 3 v) (uart mode) (2/2) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v note 1 note 1 bps theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 2.8 note 2 mbps 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v note 3 note 3 bps transfer rate transmission theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 1.2 note 4 mbps notes 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd 5.5 v and 2.7 v v b 4.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 2.2 v b )} 3 1 transfer rate 2 ? { ? c b r b ln (1 ? 2.2 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 1 above to calculate the maxi mum transfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 4.0 v and 2.3 v v b 2.7 v 1 maximum transfer rate = { ? c b r b ln (1 ? 2.0 v b )} 3 [bps] 1 transfer rate 2 ? { ? c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 3 above to calculate the maxi mum transfer rate under conditions of the customer. 5. operating condtions of ls (low-speed main) mode is t a = -40 to +85 c. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 40 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 remarks 1. r b [ ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03)) uart mode connection diagram (during communication at different potential) user's device txdq rxdq rx tx v b r b rl78/i1a uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regist er g (pimg) and port output mode register g (pomg). remarks 1. r b [ ]:communication line (txdq) pull-up resistance, v b [v]: communication line voltage 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 41 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (5) communication at different potentia l (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 200 1150 ns sckp cycle time t kcy1 t kcy1 2/f clk 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 300 1150 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 50 t kcy1 /2 ? 75 ns sckp high-level width t kh1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 120 t kcy1 /2 ? 170 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 7 t kcy1 /2 ? 50 ns sckp low-level width t kl1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 10 t kcy1 /2 ? 50 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 81 479 ns sip setup time (to sckp ) note 1 t sik1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 479 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 10 19 ns sip hold time (from sckp ) note 1 t ksi1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 10 19 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 60 100 ns delay time from sckp to sop output note 1 t kso1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 130 195 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 44 110 ns sip setup time (to sckp ) note 2 t sik1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 110 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 10 19 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 10 19 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 10 25 ns delay time from sckp to sop output note 2 t kso1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 10 25 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. operating condtions of ls (low-speed main) mode is t a = -40 to +85 c.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 42 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 43 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (6) communication at different potential (2.5 v, 3 v) (c si mode) (master mode, sckp ... internal clock output) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 300 1150 ns sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 500 1150 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 75 t kcy1 /2 ? 75 ns sckp high-level width t kh1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 170 t kcy1 /2 ? 170 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 12 t kcy1 /2 ? 50 ns sckp low-level width t kl1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 18 t kcy1 /2 ? 50 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 81 479 ns sip setup time (to sckp ) note 1 t sik1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 479 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 19 19 ns sip hold time (from sckp ) note 1 t ksi1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 100 100 ns delay time from sckp to sop output note 1 t kso1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 195 195 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 44 110 ns sip setup time (to sckp ) note 2 t sik1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 110 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, cb = 30 pf, rb = 1.4 k 19 19 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, cb = 30 pf, rb = 2.7 k 19 19 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, cb = 30 pf, rb = 1.4 k 25 25 ns delay time from sckp to sop output note 2 t kso1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, cb = 30 pf, rb = 2.7 k 25 25 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. operating condtions of ls (low-speed main) mode is t a = -40 to +85 c.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 44 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. csi mode connection diagram (during communication at different potential) v b r b user's device sckp sop sck si sip so v b r b rl78/i1a remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 45 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1)
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 46 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (7) dali/uart4 mode (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit f mck /12 f mck /12 bps transfer rate maximum transfer rate theoretical value hs: f clk = 32 mhz, f mck = f clk ls: f clk = 8 mhz, f mck = f clk 2.6 0.6 mbps remark f mck : operation clock frequency of dali/uart. (operation clock to be set by the se rial clock select re gister mn (sps4).) caution operating condtions of ls (low-speed main) mode is t a = -40 to +85 c.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 47 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.5.2 serial interface iica (1) i 2 c standard mode (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit scla0 clock frequency f scl standard mode: f clk 1 mhz 0 100 0 100 khz setup time of restart condition t su:sta 4.7 4.7 s hold time note 1 t hd:sta 4.0 4.0 s hold time when scla0 = ?l? t low 4.7 4.7 s hold time when scla0 = ?h? t high 4.0 4.0 s data setup time (reception) t su:dat 250 250 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 3.45 s setup time of stop condition t su:sto 4.0 4.0 s bus-free time t buf 4.7 4.7 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. 3. operating condtions of ls (low-speed main) mode is t a = -40 to +85 c. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 48 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (2) i 2 c fast mode (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode ls (low-speed main) mode parameter symbol conditions min. max. min. max. unit scla0 clock frequency f scl fast mode: f clk 3.5 mhz 0 400 0 400 khz setup time of restart condition t su:sta 0.6 0.6 s hold time note 1 t hd:sta 0.6 0.6 s hold time when scla0 = ?l? t low 1.3 1.3 s hold time when scla0 = ?h? t high 0.6 0.6 s data setup time (reception) t su:dat 100 100 ns data hold time (transmission) note 2 t hd:dat 0 0.9 0 0.9 s setup time of stop condition t su:sto 0.6 0.6 s bus-free time t buf 1.3 1.3 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. 3. operating condtions of ls (low-speed main) mode is t a = -40 to +85 c. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. fast mode: c b = 320 pf, r b = 1.1 k iica serial transfer timing t low t low t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scla0 sdaa0
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 49 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.6 analog characteristics 2.6.1 a/d converter characteristics classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani2, ani4 to ani7 refer to 2.6.1 (1) . ani16 to ani19 refer to 2.6.1 (2) . refer to 2.6.1 (4) . internal reference voltage temperature sensor output voltage refer to 2.6.1 (1) . refer to 2.6.1 (3) . ?
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 50 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin : ani2, ani4 to ani7, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +105 c, 2.7 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.2 3.5 lsb 3.6 v v dd 5.5 v 2.125 39 s 10-bit resolution target pin: ani2, ani4 to ani7 2.7 v v dd 5.5 v 3.1875 39 s 3.6 v v dd 5.5 v 2.375 39 s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.7 v v dd 5.5 v 3.5625 39 s zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd note 3 0.25 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd note 3 0.25 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 1.5 lsb ani2, ani4 to ani7 0 av refp v internal reference voltage (hs (high-speed main) mode) v bgr note 4 v analog input voltage v ain temperature sensor output voltage (hs (high-speed main) mode) v tmps25 note 4 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . 4. refer to 2.6.2 temperature sensor/internal reference voltage characteristics .
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 51 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin : ani16 to ani19 (t a = ? 40 to +105 c, 2.7 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd notes 3 1.2 5.0 lsb 3.6 v v dd 5.5 v 2.125 39 s conversion time t conv 10-bit resolution target ani pin : ani16 to ani19 2.7 v v dd 5.5 v 3.1875 39 s zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd notes 3 0.35 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd notes 3 0.35 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd notes 3 3.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd notes 3 2.0 lsb analog input voltage v ain ani16 to ani19 0 av refp and v dd v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd .
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 52 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target pin : ani0 to ani2, ani4 to ani7, ani16 to ani19, internal reference voltage, and temperature sensor output voltage (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution 1.2 7.0 lsb 3.6 v v dd 5.5 v 2.125 39 s conversion time t conv 10-bit resolution target pin: ani0 to ani2, ani4 to ani7, ani16 to ani19 2.7 v v dd 5.5 v 3.1875 39 s 3.6 v v dd 5.5 v 2.375 39 s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.7 v v dd 5.5 v 3.5625 39 s zero-scale error notes 1, 2 e zs 10-bit resolution 0.60 %fsr full-scale error notes 1, 2 e fs 10-bit resolution 0.60 %fsr integral linearity error note 1 ile 10-bit resolution 4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.0 lsb ani0 to ani2, ani4 to ani7 0 v dd v ani16 to ani19 0 v dd v internal reference voltage (hs (high-speed main) mode) v bgr note 3 v analog input voltage v ain temperature sensor output voltage (hs (high-speed main) mode) v tmps25 note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 2.6.2 temperature sensor/internal reference voltage characteristics .
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 53 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (4) when reference voltage (+) = internal reference voltage (adrefp1 = 1, adrefp0 = 0), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin : ani0, ani2, ani4 to ani7, ani16 to ani19 (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm = 0 v note 4 , hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution res 8 bit conversion time t conv 8-bit resolution 17 39 s zero-scale error notes 1, 2 e zs 8-bit resolution 0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.0 lsb differential linearity error note 1 dle 8-bit resolution 1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 2.6.2 temperature sensor/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage ( ? ) = av refm . 2.6.2 temperature sensor/internal reference voltage characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v internal reference voltage v bgrt setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature ? 3.6 mv/c operation stabilization wait time t amp 5 s
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 54 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.6.3 programmable gain amplifier (t a = ? 40 to +105 c, 2.7 v av refp = v dd 5.5 v, v ss = av refm = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage v iopga 5 10 mv input voltage range v ipga 0 0.9v dd / gain v 4, 8 times 1 % 16 times 1.5 % gain error note 1 32 times 2 % 4, 8 times 4 v/ s 4.0 v v dd 5.5 v 16, 32 times 1.4 v/ s 4, 8 times 1.8 v/ s sr rpga rising edge 2.7 v v dd < 4.0 v 16, 32 times 0.5 v/ s 4, 8 times 3.2 v/ s 4.0 v v dd 5.5 v 16, 32 times 1.4 v/ s 4, 8 times 1.2 v/ s slew rate note 1 sr fpga falling edge 2.7 v v dd < 4.0 v 16, 32 times 0.5 v/ s 4, 8 times 5 s operation stabilization wait time note 2 t pga 16, 32 times 10 s notes 1. when v ipga = 0.1v dd /gain to 0.9v dd /gain. 2. time required until a state is entered where the dc and ac specifications of the pga are satisfied after the pga operation has been enabled (pgaen = 1). remark these characteristics apply when av refm is selected as gnd of the pga by using the cvrvs1 bit.
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 55 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.6.4 comparator (t a = ? 40 to +105 c, 2.7 v av refp = v dd 5.5 v, v ss = av refm = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage v iocmp 5 40 mv cmp0p to cmp5p 0 v dd v input voltage range v icmp cmpcom 0.045 0.9v dd v cmrvm register values: 7fh to 80h (m = 0 to 2) 2 lsb internal reference voltage deviation v iref other than above 1 lsb response time t cr , t cf input amplitude = 100 mv 70 150 ns 3.3 v v dd 5.5 v 1 s operation stabilization wait time note 1 t cmp 2.7 v v dd < 3.3 v 3 s reference voltage stabilization wait time t vr cvre: 0 to 1 note 2 10 s notes 1. time required until a state is ent ered where the dc and ac specific ations of the comparator are satisfied after the operation of the comparator has been enabled (cmpnen bit = 1: n = 0 to 5) 2. enable comparator output (cnoe bit = 1; n = 0 to 5) after enabling operation of the internal reference voltage generator (by setting the cvrem bit to 1; m = 0 to 2) and waiting for the operation stabilization time to elapse. remark these characteristics apply when av refp is selected as the power supply source of the internal reference voltage by using the cvrvs0 bit, and when av refm is selected as gnd of the internal reference voltage by using the cvrvs1 bit. t cr t cf +100 mv -100 mv comparator ref. voltage output voltage v o input voltage v in
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 56 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.6.5 por circuit characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.45 1.51 1.57 v detection voltage v pdr power supply fall time 1.44 1.50 1.56 v minimum pulse width note t pw 300 s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through se tting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). t pw v por v pdr or 0.7 v supply voltage (v dd ) 2.6.6 lvd circuit characteristics lvd detection voltage of reset mode and interruput mode (t a = ? 40 to +105 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 3.97 4.06 4.14 v v lvd0 power supply fall time 3.89 3.98 4.06 v power supply rise time 3.67 3.75 3.82 v v lvd1 power supply fall time 3.59 3.67 3.74 v power supply rise time 3.06 3.13 3.19 v v lvd2 power supply fall time 2.99 3.06 3.12 v power supply rise time 2.95 3.02 3.08 v v lvd3 power supply fall time 2.89 2.96 3.02 v power supply rise time 2.85 2.92 2.97 v v lvd4 power supply fall time 2.79 2.86 2.91 v power supply rise time 2.75 2.81 2.87 v detection voltage supply voltage level v lvd5 power supply fall time 2.70 2.75 2.81 v minimum pulse width t lw 300 s detection delay time 300 s
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 57 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +105 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvdd0 v poc2 , v poc1 , v poc0 = 0, 1, 1, falling reset voltage: 2.7 v 2.70 2.75 2.81 v rising release reset voltage 2.85 2.92 2.97 v v lvdd1 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.79 2.86 2.91 v rising release reset voltage 2.95 3.02 3.08 v v lvdd2 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.89 2.96 3.02 v rising release reset voltage 3.97 4.06 4.14 v interrupt and reset mode v lvdd3 lvis1, lvis0 = 0, 0 falling interrupt voltage 3.89 3.98 4.06 v 2.6.7 supply voltage rise inclination characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply voltage rise sv dd 54 v/ms caution keep the internal reset status by using the lvd circuit or an external reset signal until v dd rises to within the operating voltage range shown in 2.4 ac characteristics. 2.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the por detec tion voltage. when the voltage drops , the data is retained before a por reset is effected, but data is not re tained when a por reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 58 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.8 flash memory programming characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.7 v v dd 5.5 v 1 32 mhz number of code flash rewrites notes 1, 2, 3 retained for 20 years t a = 85 c note 3 1,000 retained for 1 year t a = 25 c note 3 1,000,000 retained for 5 years t a = 85 c note 3 100,000 number of data flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85 c note 3 10,000 times notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library 3. these are the characteristics of t he flash memory and the results obtained from reliability testing by renesas electronics corporation. 2.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115.2 k 1 m bps
rl78/i1a 2. electric al specifications (t a = ? 40 to +105 c) page 59 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 2.10 timing specs for switching flash memory programming modes (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after a reset ends (except soft processing time) t hd por and lvd reset must end before the external reset ends. 1 ms reset tool0 <1> <2> <3> t suinit t hd + soft processing time t su <4> <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the pin reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programmi ng mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until an external reset ends t hd : how long to keep the tool0 pin at the low level from when the external and internal resets end (except soft processing time)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 60 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3. electrical specifications (t a = ? 40 to +125 c) target products : t a = ? 40 to +125 c r5f1076cmsp#v0, r5f1076cmsp#x0, r5f107acmsp#v0,r5f107acmsp#x0, r5f107aemsp#v0, r5f107aemsp#x0, r5f107demsp#v0, r5f107demsp#x0 cautions 1. the rl78/i1a has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guarant eed number of rewritable ti mes of the flash memory may be exceeded when this function is used, a nd product reliability therefore cannot be guaranteed. renesas electronics is not liabl e for problems occurri ng when the on-chip debug function is used. 2. when any of these products are used at 105c or lower, refer to ?2. electrical specifications (t a = ? 40 to +105c)?.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 61 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit supply voltage v dd ? 0.5 to +6.5 v regc pin input voltage v iregc regc ? 0.3 to +2.8 and ? 0.3 to v dd +0.3 note 1 v input voltage v i1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120 to p124, p137, p147, p200 to p206, exclk, exclks, reset ? 0.3 to v dd +0.3 note 2 v output voltage v o1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 ? 0.3 to v dd +0.3 note 2 v analog input voltage v ai1 ani0 to ani2, ani4 to ani7, ani16 to ani19 ? 0.3 to v dd +0.3 and ? 0.3 to av ref(+) +0.3 notes 2, 3 v notes 1. connect the regc pin to vss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 4. must be 6.5 v or lower. 5. do not exceed av ref(+) + 0.3 v in case of a/d conversion target pin . caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physi cal damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remarks 1. unless specified otherwise, the char acteristics of alternate-function pins are the same as those of the port pins. 2. av ref (+) : + side reference voltage of the a/d converter. 3. v ss : reference voltage
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 62 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit per pin p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 ? 40 ma p02, p03, p40, p120 ? 70 ma i oh1 total of all pins ? 170 ma p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 ? 100 ma per pin ? 0.5 ma output current, high i oh2 total of all pins p20 to p22, p24 to p27 ? 2 ma per pin p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 40 ma p02, p03, p40, p120 70 ma i ol1 total of all pins 170 ma p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 100 ma per pin 1 ma output current, low i ol2 total of all pins p20 to p22, p24 to p27 5 ma in normal operation mode ? 40 to +125 operating ambient temperature t a in flash memory programming mode ? 40 to +105 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physi cal damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 63 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.2 oscillator characteristics 3.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter resonator recommended circuit conditions min. typ. max. unit x1 clock frequency (f x ) note ceramic resonator/ crystal resonator c1 x2 x1 c2 v ss rd 1.0 20.0 mhz xt1 clock frequency (f xt ) note crystal resonator xt1 xt2 c4 c3 rd v ss 32 32.768 35 khz note indicates only permissible oscillator frequency ranges . refer to ac characteristics for instruction execution time. request evaluation by the manufactu rer of the oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high -speed on-chip oscillator clock after a reset release, check the x1 cl ock oscillation stabilization time usin g the oscillation stabilization time counter status register (ostc) by the user. de termine the oscillation stabilization time of the ostc register and the oscillation stabilization time select register (o sts) after sufficiently evaluating the oscillation stabilization ti me with the resonator to be used.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 64 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.2.2 on-chip oscillator characteristics (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency note 1 f ih 1 32 mhz t a = ? 20 to 85 c ? 1 +1 % t a = ? 40 to 105 c ? 1.5 +1.5 % high-speed on-chip oscillator clock frequency accuracy note 2 t a = ? 40 to 125 c when 16 mhz selected ? 2 +2 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy ? 15 +15 % notes 1. frequency can be selected in a high-speed on-chip oscillator. selected by bits 0 to 3 of option byte (000c2h/010c2h). 2. this indicates the oscillator characteristics only. see ac characteristics for instruction execution time. remark when using the device at an ambi ent temperature that exceeds t a = 105 c, the selectable oscillation frequency is 16 mhz max.. 3.2.3 pll characteristics (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit high-speed system clock is selected (f mx = 4 mhz) 3.92 4.00 4.08 mhz pll input clock frequency note f pllin high-speed on-chip oscillator clock is selected (f ih = 4 mhz) 3.92 4.00 4.08 mhz pll output clock frequency note f pll f pllin 16 mhz note this only indicates the oscillator characteristics. see ac characteristics for instruction execution time. remark when using the device at an ambi ent temperature that exceeds t a = 105 c, only 16 mhz (f pll x 1/4) can be selected as the cpu operating frequency.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 65 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.3 dc characteristics 3.3.1 pin characteristics (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 note 2 ma per pin for p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd < 4.0 v ? 1.0 ma 4.0 v v dd 5.5 v ? 9.0 ma total of p02, p03, p40, p120 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v ? 3.0 ma 4.0 v v dd 5.5 v ? 21.0 ma total of p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v ? 6.0 ma 4.0 v v dd 5.5 v ? 21.0 ma i oh1 total of all pins (when duty 70% note 3 ) 2.7 v v dd < 4.0 v ? 9.0 ma per pin for p20 to p22, p24 to p27 2.7 v v dd 5.5 v ? 0.1 note 2 ma output current, high note 1 i oh2 total of all pins (when duty 70% note 3 ) 2.7 v v dd 5.5 v ? 0.4 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the dut y factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 80% and i oh = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p02, p10 to p12 do not output hi gh level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 66 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 8.5 note 2 ma per pin for p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd < 4.0 v 1.5 note 2 ma 4.0 v v dd 5.5 v 20.0 ma total of p02, p03, p40, p120 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v 5.0 ma 4.0 v v dd 5.5 v 20.0 ma total of p05, p06, p10 to p12, p30, p31, p75 to p77, p147, p200 to p206 (when duty 70% note 3 ) 2.7 v v dd < 4.0 v 10.0 ma 4.0 v v dd 5.5 v 40.0 ma i ol1 total of all pins (when duty 70% note 3 ) 2.7 v v dd < 4.0 v 15.0 ma per pin for p20 to p22, p24 to p27 2.7 v v dd 5.5 v 0.4 note 2 ma output current, low note 1 i ol2 total of all pins (when duty 70% note 3 ) 2.7 v v dd 5.5 v 1.6 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the v ss pin. 2. however, do not exceed the total current value. 3. specification under conditi ons where the duty factor 70%. the output current value that has changed to the dut y factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 80% and i ol = ? 10.0 ma total output current of pins = ( ? 10.0 0.7)/(80 0.01) ? ? 8.7 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 67 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit v ih1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120 to p124, p137, p147, p200 to p206, exclk, exclks, reset normal input buffer 0.8v dd v dd v ttl input buffer 4.0 v v dd 5.5 v 2.1 v dd v ttl input buffer 3.3 v v dd < 4.0 v 2.0 v dd v input voltage, high v ih2 p03, p10, p11 ttl input buffer 2.7 v v dd < 3.3 v 1.5 v dd v v il1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120 to p124, p137, p147, p200 to p206, exclk, exclks, reset normal input buffer 0 0.2v dd v ttl input buffer 4.0 v v dd 5.5 v 0 0.8 v ttl input buffer 3.3 v v dd < 4.0 v 0 0.5 v input voltage, low v il2 p03, p10, p11 ttl input buffer 2.7 v v dd < 3.3 v 0 0.32 v caution the maximum value of v ih of pins p02, p10 to p12 is v dd , even in the n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 68 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v v oh1 p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd 5.5 v, i oh1 = ? 1.0 ma v dd ? 0.5 v output voltage, high v oh2 p20 to p22, p24 to p27 2.7 v v dd 5.5 v, i oh2 = ? 100 a v dd ? 0.5 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 4.0 v v dd 5.5 v, i ol1 = 4.0 ma 0.4 v v ol1 p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.4 v output voltage, low v ol2 p20 to p22, p24 to p27 2.7 v v dd 5.5 v, i ol2 = 400 a 0.4 v caution p02, p10 to p12 do not output hi gh level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 69 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit i lih1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120, p137, p147, p200 to p206, reset v i = v dd 1 a in input port or external clock input 1 a input leakage current, high i lih2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in resonator connection 10 a i lil1 p02, p03, p05, p06, p10 to p12, p20 to p22, p24 to p27, p30, p31, p40, p75 to p77, p120, p137, p147, p200 to p206, reset v i = v ss ? 1 a in input port or external clock input ? 1 a input leakage current, low i lil2 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in resonator connection ? 10 a on-chip pll-up resistance r u p02, p03, p05, p06, p10 to p12, p30, p31, p40, p75 to p77, p120, p147, p200 to p206 v i = v ss , in input port 10 20 100 k remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 70 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.3.2 supply current characteristics (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 2.9 4.8 ma hs (high- speed main) mode note 5 f ih = 16 mhz note 3 v dd = 3.0 v 2.9 4.8 ma square wave input 3.2 5.6 ma f mx = 20 mhz note 2 , v dd = 5.0 v resonator connection 3.3 5.7 ma square wave input 3.2 5.6 ma f mx = 20 mhz note 2 , v dd = 3.0 v resonator connection 3.3 5.7 ma square wave input 2.0 3.3 ma f mx = 10 mhz note 2 , v dd = 5.0 v resonator connection 2.0 3.3 ma square wave input 2.0 3.3 ma hs (high- speed main) mode note 5 f mx = 10 mhz note 2 , v dd = 3.0 v resonator connection 2.0 3.3 ma v dd = 5.0 v 3.3 6.5 ma hs (high- speed main) mode note 5 f ih = 4 mhz note 3 f pll = 64 mhz, f clk = 16 mhz v dd = 3.0 v 3.3 6.5 ma square wave input 4.2 6.0 a f sub = 32.768 khz note 4 t a = ? 40 c resonator connection 4.4 6.2 a square wave input 4.2 6.0 a f sub = 32.768 khz note 4 t a = +25 c resonator connection 4.4 6.2 a square wave input 4.3 7.2 a f sub = 32.768 khz note 4 t a = +50 c resonator connection 4.5 7.4 a square wave input 4.4 8.1 a f sub = 32.768 khz note 4 t a = +70 c resonator connection 4.6 8.3 a square wave input 5.2 11.4 a f sub = 32.768 khz note 4 t a = +85 c resonator connection 5.4 11.6 a square wave input 6.9 20.8 a f sub = 32.768 khz note 4 t a = +105 c resonator connection 7.1 21.0 a square wave input 11.1 51.2 a supply current note 1 i dd1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +125 c resonator connection 11.3 51.4 a ( notes and remarks are listed on the next page.)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 71 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 notes 1. total current flowing into v dd , including the input leakage current fl owing when the level of the input pin is fixed to v dd or v ss . the values below the max. column in clude the peripheral operation current. however, not including the current flowing into the a/d converter, comparator, programmable gain amplifier, lvd circuit, i/o port, and on-chip pull-up/p ull-down resistors and the current flowing during data flash rewrite. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-spee d system clock are stopped. when amphs1 = 1 (ultra-low power consumption oscillation). however, not including the curr ent flowing into the rtc, 12- bit interval timer, and watchdog timer. 5. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 20 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 c
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 72 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 0.50 2.0 ma hs (high- speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.50 2.0 ma square wave input 0.40 2.2 ma f mx = 20 mhz note 3 , v dd = 5.0 v resonator connection 0.50 2.3 ma square wave input 0.40 2.2 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.50 2.3 ma square wave input 0.24 1.22 ma f mx = 10 mhz note 3 , v dd = 5.0 v resonator connection 0.30 1.28 ma square wave input 0.24 1.22 ma hs (high- speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.30 1.28 ma v dd = 5.0 v 0.95 3.7 ma hs (high- speed main) mode note 7 f ih = 4 mhz note 4 f pll = 64 mhz, f clk = 16 mhz v dd = 3.0 v 0.95 3.7 ma square wave input 0.28 0.70 a f sub = 32.768 khz note 5 t a = ? 40 c resonator connection 0.47 0.89 a square wave input 0.33 0.70 a f sub = 32.768 khz note 5 t a = +25 c resonator connection 0.52 0.89 a square wave input 0.41 1.90 a f sub = 32.768 khz note 5 t a = +50 c resonator connection 0.60 2.09 a square wave input 0.54 2.80 a f sub = 32.768 khz note 5 t a = +70 c resonator connection 0.73 2.99 a square wave input 1.27 6.10 a f sub = 32.768 khz note 5 t a = +85 c resonator connection 1.46 6.29 a square wave input 3.04 15.5 a f sub = 32.768 khz note 5 t a = +105 c resonator connection 3.23 15.7 a square wave input 7.20 45.2 a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +125 c resonator connection 7.53 45.5 a t a = ? 40 c 0.18 0.50 a t a = +25 c 0.23 0.50 a t a = +50 c 0.27 1.70 a t a = +70 c 0.44 2.60 a t a = +85 c 1.17 5.90 a t a = +105 c 2.94 15.3 a supply current note 1 i dd3 note 6 stop mode note 8 t a = +125 c 7.14 45.1 a ( notes and remarks are listed on the next page.)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 73 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 notes 1. total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the a/d converter, comparator, programmable gain amplifier, lvd circuit, i/o port, and on-chip pull-up/pull- down resistors and the current flowing during data flash rewrite. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-spee d system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). the current flowing into the rtc is included. however, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. not including the current flowing into the rt c, 12-bit interval timer, and watchdog timer. 7. relationship between operation voltage width, operat ion frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 5.5 v@1 mhz to 20 mhz 8. regarding the value for current operate the subsystem cl ock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25 c
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 74 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-speed on- chip oscillator operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a a/d converter operating current i adc notes 1, 6 when conversion at maximum speed normal mode, av refp = v dd = 5.0 v 1.3 1.7 ma a/d converter reference voltage current i adref note 1 75.0 a temperature sensor operating current i tmps note 1 75.0 a lvd operating current i lvi notes 1, 7 0.08 a self- programming operating current i fsp notes 1, 8 2.5 12.2 ma av refp = v dd = 5.0 v 0.21 0.37 ma programmable gain amplifier operating current i pga note 9 av refp = v dd = 3.0 v 0.18 0.35 ma av refp = v dd = 5.0 v 41.4 74 a i cmp note 10 when one comparator channel is operating av refp = v dd = 3.0 v 37.2 71 a av refp = v dd = 5.0 v 14.8 31 a comparator operating current i vref when one internal reference voltage circuit is operating av refp = v dd = 3.0 v 8.9 24 a av refp = v dd = 5.0 v 3.2 6.1 a programmable gain amplifier/ comparator reference current source i iref note 11 av refp = v dd = 3.0 v 2.9 4.9 a bgo operating current i bgo note 12 2.50 12.2 ma the mode is performed 0.50 1.10 ma a/d converter operation the a/d conversion operations are performed, normal mode, av refp = v dd = 5.0 v 1.20 2.17 ma snooze operating current i snoz note 1 csi/uart operation 0.70 1.27 ma ( notes and remarks are listed on the next page.)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 75 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 notes 1. current flowing to the v dd . 2. when the high-speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (e xcluding the operating current of the low-speed on- chip ocsillator and the xt1 oscillator). the supply curr ent of the rl78 microcontro llers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock is operat ing in operating mode or in halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (excluding the operating current of the xt1 oscillator and f il operating current). the current of the rl78 microcontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low- speed on-chip oscillator is selected, i fil should be added. 5. current flowing only to the watchdog timer (inclu ding the operating current of the low-speed on-chip oscillator). the supply current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 , and i wdt , when f clk = f sub when the watchdog timer is operating. 6. current flowing only to the a/d conv erter. the supply current value of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc , when the a/d converter is operating in operating mode or in halt mode. 7. current flowing only to the lvd circuit. the supply cu rrent of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. 8. current flowing during self-programming operation. 9. current flowing only to the programmable gain am plifier. the supply cu rrent value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 , and i pga , when the programmable gain amplifier is operating in operating mode or in halt mode. 10. current flowing only to the comparator. the supply current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 , and i cmp , when the comparator is operating. 11. this is the current required to flow to v dd pin of the current circuit that is used as the programmable gain amplifier and the comparator. 12. current flowing only during data flash rewrite. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 c 5. example of calculating current value when us ing programmable gain amplifier and comparator. examples 1) typ. operating current value when th ree comparator channels, one internal reference voltage generator, and pga are operating (when av refp = v dd = 5.0 v) i cmp 3 + i vref + i pga + i iref = 41.4 [ a] 3 + 14.8 [ a] 1 + 210 [ a] + 3.2 [ a] = 352.2 [ a] examples 2) typ. operating cu rrent value when using two com parator channels, without using internal reference voltage generator (when av refp = v dd = 5.0 v) i cmp 2 + i iref = 41.4 [ a] 2 + 3.2 [ a] = 86.0 [ a]
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 76 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.4 ac characteristics (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit main system clock (f main ) operation hs (high-speed main) mode 0.05 1 s subsystem clock (f sub ) operation 28.5 30.5 31.3 s instruction cycle (minimum instruction execution time) t cy in the self programming mode hs (high-speed main) mode t a = ? 40 to +105 c 0.05 1 s f ex 1.0 20.0 mhz external system clock frequency f exs 32 35 khz t exh , t exl 24 ns external system clock input high- level width, low-level width t exhs , t exls 13.7 s ti03, ti05, ti06, ti07 input high- level width, low-level width t tih , t til 2/f mck +10 ns 4.0 v v dd 5.5 v 5 mhz to03, to05, to06, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21, tkco00 to tkco05 output frequency (when duty = 50%) f to hs (high-speed main) mode 2.7 v v dd < 4.0 v 4 mhz interrupt input high-level width, low-level width t inth , t intl intp0, intp3, intp4, intp9 to intp11, intp20 to intp23 2.7 v v dd 5.5 v 1 s reset low-level width t rsl 10 s remark f mck : timer array unit operation clock frequency (operation clock to be set by the cks0n bit of timer mode register 0n (tmr0n). n: channel number (n = 0 to 7))
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 77 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 minimum instruction execution time dur ing main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 0.05 when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected cycle time t cy [ms] supply voltage v dd [v] ac timing test points v ih v il test points v ih v il external system clock timing exclk 0.7v dd (min.) 0.3v dd (max.) 1/f ex t exl t exh
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 78 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 ti/to timing ti03, ti05, ti06, ti07 t til t tih to03, to05, to06, tkbo00, tkbo01, tkbo10, tkbo11, tkbo20, tkbo21, tkco00 to tkco05 1/f to interrupt request input timing intp0, intp3, intp4, intp9 to intp11, intp20 to intp23 t intl t inth reset input timing reset t rsl
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 79 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.5 peripheral functions characteristics 3.5.1 serial array unit 0, 4 (uart0, uart1, csi00, dali/uart4) (1) during communication at same potential (uart mode) (dedicat ed baud rate ge nerator output) (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v f mck /6 bps transfer rate note theoretical value of the maximum transfer rate f clk = 20 mhz, f mck = f clk 3.3 mbps note transfer rate in the snooze mode is max. 9600 bps, min. 4800 bps. uart mode connection diagram (duri ng communication at same potential) user's device txdq rxdq rx tx rl78/i1a uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq caution select the normal input buffer for the rxdq pi n and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). remarks 1. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03))
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 80 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (2) during communication at same pot ential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remarks 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v v dd 5.5 v 250 ns sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd 5.5 v 500 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 ns sckp high-/low-level width t kh1 , t kl1 2.7 v v dd 5.5 v t kcy1 /2 ? 40 ns 4.0 v v dd 5.5 v 80 ns sip setup time (to sckp ) note 1 t sik1 2.7 v v dd 5.5 v 80 ns sip hold time (from sckp ) note 2 t ksi1 40 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 80 ns
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 81 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (3) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v v dd 5.5 v f mck 20 mhz 6/f mck ns 16 mhz < f mck 8/f mck ns sckp cycle time note 5 t kcy2 2.7 v v dd 5.5 v f mck 16 mhz 6/f mck ns sckp high-/low-level width t kh2 , t kl2 t kcy2 /2 ns sip setup time (to sckp ) note 1 t sik2 1/f mck +40 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck +60 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2/f mck +80 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. 5. transfer rate in the snooze mode: max. 1 mbps caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port out put mode register g (pomg). remarks 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 82 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 csi mode connection diagram (duri ng communication at same potential) user's device sckp sop sck si sip so rl78/i1a csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00) 2. m: unit number, n: channel number (mn = 00)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 83 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (4) communication at different potential (2.5 v, 3 v) (uart mode) (1/2) (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit f mck /6 note 1 bps 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v theoretical value of the maximum transfer rate f mck = f clk note 2 3.3 mbps f mck /6 note 1 bps transfer rate reception 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate f mck = f clk note 2 3.3 mbps notes 1. transfer rate in the snooze mode is 4800 bps only. 2. the operating frequencies of the cpu/peripheral hardware clock (f clk ) are: hs (high-speed main) mode: 20 mhz (2.7 v v dd 5.5 v) caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regist er g (pimg) and port output mode register g (pomg). remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 84 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (4) communication at different potential (2.5 v, 3 v) (uart mode) (2/2) (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit note 1 bps 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 mbps note 3 bps transfer rate transmission 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 mbps notes 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd 5.5 v and 2.7 v v b 4.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 2.2 v b )} 3 1 transfer rate 2 ? { ? c b r b ln (1 ? 2.2 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. see note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd < 4.0 v and 2.3 v v b 2.7 v 1 maximum transfer rate = { ? c b r b ln (1 ? 2.0 v b )} 3 [bps] 1 transfer rate 2 ? { ? c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference betwee n the transmission and reception sides. 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. see note 3 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). remarks 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03))
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 85 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 uart mode connection diagram (during communication at different potential) user's device txdq rxdq rx tx v b r b rl78/i1a uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regist er g (pimg) and port output mode register g (pomg). remarks 1. r b [ ]: communication line (txdq) pull-up resistance, v b [v]: communicati on line voltage 2. q: uart number (q = 0, 1), g: pim and pom number (g = 0, 1)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 86 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (5) communication at different potentia l (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 600 ns sckp cycle time t kcy1 t kcy1 4/f clk 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 1000 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 80 ns sckp high-level width t kh1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 170 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 28 ns sckp low-level width t kl1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 40 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 160 ns sip setup time (to sckp ) note 1 t sik1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 250 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 40 ns sip hold time (from sckp ) note 1 t ksi1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 40 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 160 ns delay time from sckp to sop output note 1 t kso1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 250 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 80 ns sip setup time (to sckp ) note 2 t sik1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 80 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 40 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 40 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 80 ns delay time from sckp to sop output note 2 t kso1 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 80 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. ( caution and remark are listed on the next page.)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 87 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. csi mode connection diagram (during communication at different potential) v b r b user's device sckp sop sck si sip so v b r b rl78/i1a remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 88 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remark p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 89 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (6) dali/uart4 mode (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit f mck /12 bps transfer rate maximum transfer rate theoretical value f clk = 20 mhz, f mck = f clk 1.6 mbps remark f mck : operation clock frequency of dali/uart. (operation clock to be set by the seri al clock select register 4 (sps4).)
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 90 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.5.2 serial interface iica (1) i 2 c standard mode (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit scla0 clock frequency f scl standard mode: f clk 1 mhz 0 100 khz setup time of restart condition t su:sta 4.7 s hold time note 1 t hd:sta 4.0 s hold time when scla0 = ?l? t low 4.7 s hold time when scla0 = ?h? t high 4.0 s data setup time (reception) t su:dat 250 ns data hold time (transmission) note 2 t hd:dat 0 3.45 s setup time of stop condition t su:sto 4.0 s bus-free time t buf 4.7 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 91 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (2) i 2 c fast mode (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v) hs (high-speed main) mode parameter symbol conditions min. max. unit scla0 clock frequency f scl fast mode: f clk 3.5 mhz 0 400 khz setup time of restart condition t su:sta 0.6 s hold time note 1 t hd:sta 0.6 s hold time when scla0 = ?l? t low 1.3 s hold time when scla0 = ?h? t high 0.6 s data setup time (reception) t su:dat 100 ns data hold time (transmission) note 2 t hd:dat 0 0.9 s setup time of stop condition t su:sto 0.6 s bus-free time t buf 1.3 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. fast mode: c b = 320 pf, r b = 1.1 k iica serial transfer timing t low t low t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scla0 sdaa0
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 92 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.6 analog characteristics 3.6.1 a/d converter characteristics classification of a/d converter characteristics reference voltage input channel reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = v dd reference voltage ( ? ) = v ss reference voltage (+) = v bgr reference voltage ( ? ) = av refm ani0 to ani2, ani4 to ani7 refer to 3.6.1 (1) . ani16 to ani19 refer to 3.6.1 (2) . refer to 3.6.1 (4) . internal reference voltage temperature sensor output voltage refer to 3.6.1 (1) . refer to 3.6.1 (3) . ?
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 93 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target ani pin: ani2, ani 4 to ani7, internal re ference voltage, and temperature sensor output voltage (t a = ? 40 to +125 c, 2.7 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.2 3.5 lsb 3.6 v v dd 5.5 v 2.125 39 s 10-bit resolution target pin: ani2, ani4 to ani7 2.7 v v dd 5.5 v 3.4 39 s 3.6 v v dd 5.5 v 2.375 39 s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.7 v v dd 5.5 v 3.8 39 s zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd note 3 0.25 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd note 3 0.25 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 2.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 1.5 lsb ani2, ani4 to ani7 0 av refp v internal reference voltage (hs (high-speed main) mode) v bgr note 4 v analog input voltage v ain temperature sensor output voltage (hs (high-speed main) mode) v tmps25 note 4 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 1.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.05%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 0.5 lsb to the max. value when av refp = v dd . 4. refer to 3.6.2 temperature sensor/internal reference voltage characteristics .
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 94 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani16 to ani19 (t a = ? 40 to +125 c, 2.7 v av refp v dd 5.5 v, v ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution av refp = v dd note 3 1.2 5.0 lsb 3.6 v v dd 5.5 v 2.125 39 s conversion time t conv 10-bit resolution target ani pin : ani16 to ani19 2.7 v v dd < 5.5 v 3.4 39 s zero-scale error notes 1, 2 e zs 10-bit resolution av refp = v dd note 3 0.35 %fsr full-scale error notes 1, 2 e fs 10-bit resolution av refp = v dd note 3 0.35 %fsr integral linearity error note 1 ile 10-bit resolution av refp = v dd note 3 3.5 lsb differential linearity error note 1 dle 10-bit resolution av refp = v dd note 3 2.0 lsb analog input voltage v ain ani16 to ani19 0 av refp and v dd v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. when av refp < v dd , the max. values are as follows. overall error: add 4.0 lsb to the max. value when av refp = v dd . zero-scale error/full-scale error: add 0.2%fsr to the max. value when av refp = v dd . integral linearity error/ differential linearity error: add 2.0 lsb to the max. value when av refp = v dd .
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 95 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (3) when reference voltage (+) = v dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = v ss (adrefm = 0), target pin: ani0 to ani2, ani4 to ani7, ani16 to ani19, in ternal reference voltage, and temperature sensor output voltage (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v dd , reference voltage ( ? ) = v ss ) parameter symbol conditions min. typ. max. unit resolution res 8 10 bit overall error note 1 ainl 10-bit resolution 1.2 7.0 lsb 3.6 v v dd 5.5 v 2.125 39 s conversion time t conv 10-bit resolution target pin: ani0 to ani2, ani4 to ani7, ani16 to ani19 2.7 v v dd 5.5 v 3.4 39 s 3.6 v v dd 5.5 v 2.375 39 s conversion time t conv 10-bit resolution target pin: internal reference voltage, and temperature sensor output voltage (hs (high-speed main) mode) 2.7 v v dd 5.5 v 3.8 39 s zero-scale error notes 1, 2 e zs 10-bit resolution 0.60 %fsr full-scale error notes 1, 2 e fs 10-bit resolution 0.60 %fsr integral linearity error note 1 ile 10-bit resolution 4.0 lsb differential linearity error note 1 dle 10-bit resolution 2.0 lsb ani0 to ani2, ani4 to ani7 0 v dd v ani16 to ani19 0 v dd v internal reference voltage (hs (high-speed main) mode) v bgr note 3 v analog input voltage v ain temperature sensor output voltage (hs (high-speed main) mode) v tmps25 note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature sensor/internal reference voltage characteristics .
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 96 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 (4) when reference voltage (+) = internal reference voltage (adrefp 1 = 1, adrefp0 = 0), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target pin: ani 0, ani2, ani4 to ani7, ani16 to ani19 (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v, reference voltage (+) = v bgr note 3 , reference voltage ( ? ) = av refm note 4 = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution res 8 bit conversion time t conv 8-bit resolution 17 39 s zero-scale error notes 1, 2 e zs 8-bit resolution 0.60 %fsr integral linearity error note 1 ile 8-bit resolution 2.0 lsb differential linearity error note 1 dle 8-bit resolution 1.0 lsb analog input voltage v ain 0 v bgr note 3 v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. refer to 3.6.2 temperature sensor/internal reference voltage characteristics . 4. when reference voltage ( ? ) = v ss , the max. values are as follows. zero-scale error: add 0.35%fsr to the max. value when reference voltage ( ? ) = av refm . integral linearity error: add 0.5 lsb to the max. value when reference voltage ( ? ) = av refm . differential linearity error: add 0.2 lsb to the max. value when reference voltage ( ? ) = av refm . 3.6.2 temperature sensor characteristics (t a = ? 40 to +125 c, 2.7 v v dd 5.5 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v reference output voltage v const setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature ? 3.6 mv/c operation stabilization wait time t amp 5 s
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 97 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.6.3 programmable gain amplifier (t a = ? 40 to +125 c, 2.7 v av refp = v dd 5.5 v, v ss = av refm = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage v iopga 5 10 mv input voltage range v ipga 0 0.9v dd / gain v 4, 8 times 1 % 16 times 1.5 % gain error note 1 32 times 2 % 4, 8 times 4 v/ s 4.0 v v dd 5.5 v 16, 32 times 1.4 v/ s 4, 8 times 1.8 v/ s sr rpga rising edge 2.7 v v dd < 4.0 v 16, 32 times 0.5 v/ s 4, 8 times 3.2 v/ s 4.0 v v dd 5.5 v 16, 32 times 1.4 v/ s 4, 8 times 1.2 v/ s slew rate note 1 sr fpga falling edge 2.7 v v dd < 4.0 v 16, 32 times 0.5 v/ s 4, 8 times 5 s operation stabilization wait time note 2 t pga 16, 32 times 10 s notes 1. when v ipga = 0.1v dd /gain to 0.9v dd /gain. 2. time required until a state is entered where the dc and ac specifications of the pga are satisfied after the pga operation has been enabled (pgaen = 1). remark these characteristics apply when av refm is selected as gnd of the pga by using the cvrvs1 bit.
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 98 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.6.4 comparator (t a = ? 40 to +125 c, 2.7 v av refp = v dd 5.5 v, v ss = av refm = 0 v) parameter symbol conditions min. typ. max. unit input offset voltage v iocmp 5 40 mv cmp0p to cmp5p 0 v dd v input voltage range v icmp cmpcom 0.045 0.9v dd v cmrvm register values: 7fh to 80h (m = 0 to 2) 2 lsb internal reference voltage deviation v iref other than above 1 lsb response time t cr , t cf input amplitude = 100 mv 70 150 ns 3.3 v v dd 5.5 v 1 s operation stabilization wait time note 1 t cmp 2.7 v v dd < 3.3 v 3 s reference voltage stabilization wait time t vr cvre: 0 to 1 note 2 10 s notes 1. time required until a state is ent ered where the dc and ac specific ations of the comparator are satisfied after the operation of the comparator has been enabled (cmpnen bit = 1: n = 0 to 5) 2. enable comparator output (cnoe bit = 1; n = 0 to 5) after enabling operation of the internal reference voltage generator (by setting the cvrem bit to 1; m = 0 to 2) and waiting for the operation stabilization time to elapse. remark these characteristics apply when av refp is selected as the power supply source of the internal reference voltage by using the cvrvs0 bit, and when av refm is selected as gnd of the internal reference voltage by using the cvrvs1 bit. t cr t cf +100 mv -100 mv comparator ref. voltage output voltage v o input voltage v in
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 99 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.6.5 por circuit characteristics (t a = ? 40 to +125 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.45 1.51 1.62 v detection voltage v pdr power supply fall time 1.44 1.50 1.61 v minimum pulse width note t pw 300 s note minimum time required for a por reset when v dd exceeds below v pdr . this is also the minimum time required for a por reset from when v dd exceeds below 0.7 v to when v dd exceeds v por while stop mode is entered or the main system clock is stopped through se tting bit 0 (hiostop) and bit 7 (mstop) in the clock operation status control register (csc). t pw v por v pdr or 0.7 v supply voltage (v dd ) 3.6.6 lvd circuit characteristics lvd detection voltage of reset mode and interruput mode (t a = ? 40 to +125 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 3.97 4.06 4.25 v v lvd0 power supply fall time 3.89 3.98 4.15 v power supply rise time 3.67 3.75 3.93 v v lvd1 power supply fall time 3.59 3.67 3.83 v power supply rise time 3.06 3.13 3.28 v v lvd2 power supply fall time 2.99 3.06 3.20 v power supply rise time 2.95 3.02 3.17 v v lvd3 power supply fall time 2.89 2.96 3.09 v power supply rise time 2.85 2.92 3.07 v v lvd4 power supply fall time 2.79 2.86 2.99 v power supply rise time 2.75 2.81 2.95 v detection voltage supply voltage level v lvd5 power supply fall time 2.70 2.75 2.88 v minimum pulse width t lw 300 s detection delay time 300 s
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 100 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +125 c, v pdr v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvdd0 v poc2 , v poc1 , v poc0 = 0, 1, 1, falling reset voltage: 2.7 v 2.70 2.75 2.88 v rising release reset voltage 2.85 2.92 3.07 v v lvdd1 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.79 2.86 2.99 v rising release reset voltage 2.95 3.02 3.17 v v lvdd2 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.89 2.96 3.09 v rising release reset voltage 3.97 4.06 4.25 v interrupt and reset mode v lvdd3 lvis1, lvis0 = 0, 0 falling interrupt voltage 3.89 3.98 4.15 v 3.6.7 supply voltage rise inclination characteristics (t a = ? 40 to +125 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply voltage rise sv dd 54 v/ms caution keep the internal reset status by using the lvd circuit or an external reset signal until v dd rises to within the operating voltage range shown in 3.4 ac characteristics. 3.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.47 note 5.5 v note the value depends on the por detec tion voltage. when the voltage drops , the data is retained before a por reset is effected, but data is not re tained when a por reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 101 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.8 flash memory programming characteristics (t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.7 v v dd 5.5 v 1 32 mhz number of code flash rewrites notes 1, 2, 3 retained for 20 years t a = 85 c note 3 1,000 retained for 1 year t a = 25 c note 3 1,000,000 retained for 5 years t a = 85 c note 3 100,000 number of data flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85 c note 3 10,000 times notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library 3. these are the characteristics of t he flash memory and the results obtained from reliability testing by renesas electronics corporation. 3.9 dedicated flash memory programmer communication (uart) t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during serial programming 115.2 k 1 m bps
rl78/i1a 3. electric al specifications (t a = ? 40 to +125 c) page 102 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 3.10 timing specs for switching flash memory programming modes t a = ? 40 to +105 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after a reset ends (except soft processing time) t hd por and lvd reset must end before the external reset ends. 1 ms reset tool0 <1> <2> <3> t suinit t hd + soft processing time t su <4> <1> the low level is input to the tool0 pin. <2> the external reset ends (por and lvd reset must end before the pin reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programmi ng mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until an external reset ends t hd : how long to keep the tool0 pin at the low level from when the external and internal resets end (except soft processing time)
rl78/i1a 4. package drawings page 103 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 4. package drawings 4.1 20-pin products r5f1076cgsp#v0, r5 f1076cgsp#x0, r5f1076cms p#v0, r5f1076cmsp#x0 2012 renesas electronics corporation. all rights reserved. jeita package code renesas code previous code mass (typ.) [g] p-lssop20-4.4x6.5-0.65 plsp0020jb-a p20ma-65-naa-1 0.1 20 1 10 detail of lead end item dimensions d e e a1 a a2 l c y bp 0.10 0.10 0 to 10 (unit:mm) a a2 a1 e y he c 6.50 4.40 0.20 0.10 6.40 0.10 0.10 1.45 max. 1.15 0.65 0.12 0.10 0.05 0.22 0.05 0.02 0.15 0.50 0.20 11 bp he e d l 3 2 1 note 1.dimensions ? 1? and ? 2? 2.dimension ? ? does not include tr
rl78/i1a 4. package drawings page 104 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 4.2 30-pin products r5f107acgsp#v0, r5f107aegsp#v0, r5f107acg sp#x0, r5f107aegsp#x0, r5f107acmsp#v0, r5f107aemsp#v0, r5f107acmsp#x0, r5f107aemsp#x0 jeita package code renesas code previous code mass (typ.) [g] p-lssop30-0300-0.65 plsp0030jb-b s30mc-65-5a4-3 0.18 s s h j t i g d e f c b k p l u n item b c i l m n a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2012 renesas electronics corporation. all rights reserved.
rl78/i1a 4. package drawings page 105 of 105 r01ds0171ej0210 rev.2.10 jul 31, 2013 4.3 38-pin products r5f107degsp#v0, r5f1 07degsp#x0, r5f107demsp# v0, r5f107demsp#x0 jeita package code re n esas code pre v io u s code mass (typ.) [g] p-ssop3 8 -6.1x12.3-0.65 prsp003 8 ja-b p3 8 mc-65-gaa-2 0.3 20 3 8 1 m s s v detail of lead end note each lead centerline is located w ithin 0.10 mm of its tr u e position (t.p.) at maxim u m material condition . item dimensions a b c e f g h i j l m n d 0.30 0.65 (t.p. ) 0.125 0.075 2.00 max. 1.70 0.10 8 .10 0.20 6.10 0.10 1.00 0.20 0.50 0.10 0.10 0.30 + 0.10 ? 0.05 k 0.15 + 0.10 ? 0.05 p 3 + 5 ? 3 (u n it:mm) v w w a i f g e c n d m b k h j p u t l 12.30 0.10 t u v 0.25(t.p. ) 0.60 0.15 0.25 max. w 0.15 max. 19 2012 renesas electronics cor poration. all ri g hts reserved.
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the corre ct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. 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