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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. 2002 mos integrated circuit pd160062 420-output tft-lcd source driver (compatible with 64-gray scale) document no. s16449ej1v0ds00 (1st edition) date published july 2003 ns cp(k) printed in japan data sheet description the pd160062 is a source driver for tft-l cds capable of dealing with displays wi th 64-gray scale. data input is based on digital input configured as 6 bits by 6 dots (2 pixels ), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 +0.1 v to v dd2 ?0.1 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this s ource driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respec tively output gray scale voltages of differing polarity. assuring a clock frequency of 45 mhz when driving at 2.3 v, th is driver is applicable to sxga+ standard tft-lcd panels. features cmos level input (2.3 to 3.6 v) 420 outputs input of 6 bits (gray scale data) by 6 dots capable of outputting 64 values by means of 5-by-2 ex ternal power modules (10 units) and a d/a converter (r-dac) logic power supply voltage (v dd1 ) : 2.3 to 3.6 v driver power supply voltage (v dd2 ) : 8.0 to 9.0 v high-speed data transfer: f clk = 45 mhz (internal data transf er speed when operating at v dd1 = 2.3 v) output dynamic range v ss2 +0.1 v to v dd2 ?0.1 v apply for dot-line inversion, n-line inversion and column line inversion output voltage polarity inversion function (pol) input data inversion function (capable of co ntrolling by each input port) (pol21, pol22) current consumption contro l function (lpc, hpc, bcont) slim chip ordering information part number package pd160062n- tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, pleas e contact one of our sales representatives.
data sheet s16449ej1v0ds 2 pd160062 1. block diagram sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 to v 9 pol d 00 to d 05 c 1 c 2 c 69 c 70 stb clk 70-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 to d 15 d 20 to d 25 s 3 s 420 pol21, pol22 d 30 to d 35 d 40 to d 45 d 50 to d 55 bcont hpc lpc remark /xxx indicates active low signal. 2. relationship between output circuit and d/a converter s 1 s 2 s 419 6-bit d/a converter s 420 v 4 5 5 pol multi- plexer v 9 v 0 v 5
data sheet s16449ej1v0ds 3 pd160062 3. pin configuration ( pd160062n-xxx: tcp) (copper foil surface, face-up) s 420 s 419 sthl s 418 d 55 s 417 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 v dd1 r ,/ l v 9 v 8 v 7 v 6 v 5 v dd2 v ss2 bcont v 4 v 3 v 2 v 1 v 0 hp c v ss1 lpc c lk stb p o l pol21 pol22 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 s 4 d 02 s 3 d 01 s 2 d 00 s 1 sthr co pp er foil surface remark this figure does not specify the tcp package.
data sheet s16449ej1v0ds 4 pd160062 4. pin functions (1/2) pin symbol pin name i/o description s 1 to s 420 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a widt h of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input the shift direction control pin of shift register. the shift di rections of the shift registers are as follows. r,/l = h (right shift) : sthr input, s 1 s 420 , sthl output r,/l = l (left shift) : sthl input, s 420 s 1 , sthr output sthr right shift start pulse i/o sthl left shift start pulse i/o these refer to the start pulse i/o pins when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. r,/l = h (right shift) : sthr input, sthl output r,/l = l (left shift) : sthl input, sthr output a h level should be input as the puls e of one cycle of the clock signal. if the start pulse input is more than 2 clk, the first 1 clk of the h level input is valid. clk shift clock input refers to the shift register?s shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 70th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. if 72 clock pulses are input after input of the start pulse, input of display data is halt ed automatically. the contents of the shift register are cleared at the stb?s rising edge. stb latch input the contents of the data register ar e transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input input pol = l: the s 2n?1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2n?1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n ? 1 indicates the odd output and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stb?s rising edge. pol21, pol22 data inversion input data inversion can invert when display data is loaded. pol21: invert/not invert of display data d 00 to d 05 , d 10 to d 15 , d 20 to d 25 pol22: invert/not invert of display data d 30 to d 35 , d 40 to d 45 , d 50 to d 55 pol21, pol22 = h: data inversion loads display data after inverting it. pol21, pol22 = l: data inversion does not invert input data. lpc low power control input hpc high power control input controls the write function of the driver section by digitally controlling the bypass current of the output amplifier. refer to 9. current consumption control function for details. this pin is pulled up to the v dd1 power supply inside the ic. bcont bias control input this pin can be used to finely control the bias current inside the output amplifier. refer to 9. current consumption control function for details. when this fine-control function is not required, leave this pin open.
data sheet s16449ej1v0ds 5 pd160062 (2/2) pin symbol pin name i/o description v 0 to v 9 -corrected power supplies ? input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 +0.1 v v dd1 logic power supply ? 2.3 to 3.6 v v dd2 driver power supply ? 8.0 to 9.0 v v ss1 logic ground ? grounding v ss2 driver ground ? grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down. 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also recommended between the -corrected power supply terminals (v 0 , v 1 , v 2 , , v 9 ) and v ss2 .
data sheet s16449ej1v0ds 6 pd160062 5. relationship between input data and output voltage value the pd160062 incorporates a 6-bit d/a converter whose odd out put pins and even output pins output respectively gray scale voltages of differing polarity with respect to th e lcd?s counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors (r0 to r62) are designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ? to v 63 ? is almost equivalent. for the 2 sets of five -compensated power supplies, v 0 to v 4 and v 5 to v 9 , respectively, input gray scale voltages of the same polarity with respect to t he common voltage. when fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the -compensated power supplies v 1 to v 3 and v 6 to v 8 . figure 5 ? 1 shows the relationship between the driving volt ages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships of v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 +0.1 v figures 5 ? 2 shows -corrected power supply voltage and ladder resistors ratio and figure 5 ? 3 shows the relationship between the input data a nd the output voltage. figure 5 ? 1. relationship between input data and -corrected power supplies v 1 v 2 v 3 v 4 v ss2 00 10 20 30 3f v 0 v 6 v 8 v dd2 16 v 9 16 16 16 15 0.1 v 0.1 v input data (hex) 15 16 16 0.5 v dd2 v 5 v 7 v com split interval
data sheet s16449ej1v0ds 7 pd160062 figure 5 ? 2. -corrected voltages and ladder resistors ratio v 0 v 17 ?? v 16 ?? v 15 ?? v 1 ?? v 2 ?? v 0 ?? v 61 ?? v 60 ?? v 49 ?? v 48 ?? v 47 ?? r60 r59 r49 r48 r47 r46 v 6 r61 r17 r16 r15 r14 v 8 v 62 ?? r62 v 9 v 63 ?? v 5 v 47 ? v 48 ? v 49 ? v 61 ? v 62 ? v 63 ? v 2 ? v 3 ? v 15 ? v 16 ? v 17 ? r2 r3 r14 r15 r16 r17 v 1 r1 r46 r47 r48 r49 r60 r61 r62 v 3 v 4 v 1 ? r0 r2 r1 r0 v 0 ? rn ratio 1 ratio 2 value ( ) r0 8.00 0.0505 544 r1 7.50 0.0473 510 r2 7.00 0.0442 476 r3 6.50 0.0410 442 r4 6.00 0.0379 408 r5 5.50 0.0347 374 r6 5.50 0.0347 374 r7 5.00 0.0315 340 r8 5.00 0.0315 340 r9 4.00 0.0252 272 r10 4.00 0.0252 272 r11 3.50 0.0221 238 r12 3.50 0.0221 238 r13 3.50 0.0221 238 r14 3.00 0.0189 204 r15 3.00 0.0189 204 r16 3.00 0.0189 204 r17 2.50 0.0158 170 r18 2.50 0.0158 170 r19 2.50 0.0158 170 r20 2.00 0.0126 136 r21 2.00 0.0126 136 r22 2.00 0.0126 136 r23 1.50 0.0095 102 r24 1.50 0.0095 102 r25 1.50 0.0095 102 r26 1.50 0.0095 102 r27 1.00 0.0063 68 r28 1.00 0.0063 68 r29 1.00 0.0063 68 r30 1.00 0.0063 68 r31 1.00 0.0063 68 r32 1.00 0.0063 68 r33 1.00 0.0063 68 r34 1.00 0.0063 68 r35 1.00 0.0063 68 r36 1.00 0.0063 68 r37 1.00 0.0063 68 r38 1.00 0.0063 68 r39 1.00 0.0063 68 r40 1.00 0.0063 68 r41 1.00 0.0063 68 r42 1.00 0.0063 68 r43 1.00 0.0063 68 r44 1.00 0.0063 68 r45 1.00 0.0063 68 r46 1.00 0.0063 68 r47 1.00 0.0063 68 r48 1.00 0.0063 68 r49 1.00 0.0063 68 r50 1.00 0.0063 68 r51 1.00 0.0063 68 r52 1.00 0.0063 68 r53 1.50 0.0095 102 r54 1.50 0.0095 102 r55 1.50 0.0095 102 r56 2.00 0.0126 136 r57 2.00 0.0126 136 r58 2.50 0.0158 170 r59 2.50 0.0158 170 r60 3.00 0.0189 204 r61 5.00 0.0315 340 r62 8.00 0.0505 544 10778 68 total resistance minimum resistance value remark the resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. the resistance ratio2 is a relative ratio in t he case of setting the to tal resistance to 1. caution there is no connection between v 4 and v 5 terminal in the chip.
data sheet s16449ej1v0ds 8 pd160062 figure 5 ? 3. relationship between input data a nd output voltage (pol21, pol22 = l) (output voltage 1) v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 (output voltage 2) 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 +0.1 v in p ut data 00h v 0 ' v 0 v 0 '' v 9 01h v 1 ' v 1 + ( v 0 -v 1 ) 4930 / 5474 v 1 '' v 9 + ( v 8 -v 9 ) 544 / 5474 02h v 2 ' v 1 + ( v 0 -v 1 ) 4420 / 5474 v 2 '' v 9 + ( v 8 -v 9 ) 1054 / 5474 03h v 3 ' v 1 + ( v 0 -v 1 ) 3944 / 5474 v 3 '' v 9 + ( v 8 -v 9 ) 1530 / 5474 04h v 4 ' v 1 + ( v 0 -v 1 ) 3502 / 5474 v 4 '' v 9 + ( v 8 -v 9 ) 1972 / 5474 05h v 5 ' v 1 + ( v 0 -v 1 ) 3094 / 5474 v 5 '' v 9 + ( v 8 -v 9 ) 2380 / 5474 06h v 6 ' v 1 + ( v 0 -v 1 ) 2720 / 5474 v 6 '' v 9 + ( v 8 -v 9 ) 2754 / 5474 07h v 7 ' v 1 + ( v 0 -v 1 ) 2346 / 5474 v 7 '' v 9 + ( v 8 -v 9 ) 3128 / 5474 08h v 8 ' v 1 + ( v 0 -v 1 ) 2006 / 5474 v 8 '' v 9 + ( v 8 -v 9 ) 3468 / 5474 09h v 9 ' v 1 + ( v 0 -v 1 ) 1666 / 5474 v 9 '' v 9 + ( v 8 -v 9 ) 3808 / 5474 0ah v 10 ' v 1 + ( v 0 -v 1 ) 1394 / 5474 v 10 '' v 9 + ( v 8 -v 9 ) 4080 / 5474 0bh v 11 ' v 1 + ( v 0 -v 1 ) 1122 / 5474 v 11 '' v 9 + ( v 8 -v 9 ) 4352 / 5474 0ch v 12 ' v 1 + ( v 0 -v 1 ) 884 / 5474 v 12 '' v 9 + ( v 8 -v 9 ) 4590 / 5474 0dh v 13 ' v 1 + ( v 0 -v 1 ) 646 / 5474 v 13 '' v 9 + ( v 8 -v 9 ) 4828 / 5474 0eh v 14 ' v 1 + ( v 0 -v 1 ) 408 / 5474 v 14 '' v 9 + ( v 8 -v 9 ) 5066 / 5474 0fh v 15 ' v 1 + ( v 0 -v 1 ) 204 / 5474 v 15 '' v 9 + ( v 8 -v 9 ) 5270 / 5474 10h v 16 ' v 1 v 16 '' v 8 11h v 17 ' v 2 + ( v 1 -v 2 ) 1666 / 1870 v 17 '' v 8 + ( v 7 -v 8 ) 204 / 1870 12h v 18 ' v 2 + ( v 1 -v 2 ) 1496 / 1870 v 18 '' v 8 + ( v 7 -v 8 ) 374 / 1870 13h v 19 ' v 2 + ( v 1 -v 2 ) 1326 / 1870 v 19 '' v 8 + ( v 7 -v 8 ) 544 / 1870 14h v 20 ' v 2 + ( v 1 -v 2 ) 1156 / 1870 v 20 '' v 8 + ( v 7 -v 8 ) 714 / 1870 15h v 21 ' v 2 + ( v 1 -v 2 ) 1020 / 1870 v 21 '' v 8 + ( v 7 -v 8 ) 850 / 1870 16h v 22 ' v 2 + ( v 1 -v 2 ) 884 / 1870 v 22 '' v 8 + ( v 7 -v 8 ) 986 / 1870 17h v 23 ' v 2 + ( v 1 -v 2 ) 748 / 1870 v 23 '' v 8 + ( v 7 -v 8 ) 1122 / 1870 18h v 24 ' v 2 + ( v 1 -v 2 ) 646 / 1870 v 24 '' v 8 + ( v 7 -v 8 ) 1224 / 1870 19h v 25 ' v 2 + ( v 1 -v 2 ) 544 / 1870 v 25 '' v 8 + ( v 7 -v 8 ) 1326 / 1870 1ah v 26 ' v 2 + ( v 1 -v 2 ) 442 / 1870 v 26 '' v 8 + ( v 7 -v 8 ) 1428 / 1870 1bh v 27 ' v 2 + ( v 1 -v 2 ) 340 / 1870 v 27 '' v 8 + ( v 7 -v 8 ) 1530 / 1870 1ch v 28 ' v 2 + ( v 1 -v 2 ) 272 / 1870 v 28 '' v 8 + ( v 7 -v 8 ) 1598 / 1870 1dh v 29 ' v 2 + ( v 1 -v 2 ) 204 / 1870 v 29 '' v 8 + ( v 7 -v 8 ) 1666 / 1870 1eh v 30 ' v 2 + ( v 1 -v 2 ) 136 / 1870 v 30 '' v 8 + ( v 7 -v 8 ) 1734 / 1870 1fh v 31 ' v 2 + ( v 1 -v 2 ) 68 / 1870 v 31 '' v 8 + ( v 7 -v 8 ) 1802 / 1870 20h v 32 ' v 2 v 32 '' v 7 21h v 33 ' v 3 + ( v 2 -v 3 ) 1020 / 1088 v 33 '' v 7 + ( v 6 -v 7 ) 68 / 1088 22h v 34 ' v 3 + ( v 2 -v 3 ) 952 / 1088 v 34 '' v 7 + ( v 6 -v 7 ) 136 / 1088 23h v 35 ' v 3 + ( v 2 -v 3 ) 884 / 1088 v 35 '' v 7 + ( v 6 -v 7 ) 204 / 1088 24h v 36 ' v 3 + ( v 2 -v 3 ) 816 / 1088 v 36 '' v 7 + ( v 6 -v 7 ) 272 / 1088 25h v 37 ' v 3 + ( v 2 -v 3 ) 748 / 1088 v 37 '' v 7 + ( v 6 -v 7 ) 340 / 1088 26h v 38 ' v 3 + ( v 2 -v 3 ) 680 / 1088 v 38 '' v 7 + ( v 6 -v 7 ) 408 / 1088 27h v 39 ' v 3 + ( v 2 -v 3 ) 612 / 1088 v 39 '' v 7 + ( v 6 -v 7 ) 476 / 1088 28h v 40 ' v 3 + ( v 2 -v 3 ) 544 / 1088 v 40 '' v 7 + ( v 6 -v 7 ) 544 / 1088 29h v 41 ' v 3 + ( v 2 -v 3 ) 476 / 1088 v 41 '' v 7 + ( v 6 -v 7 ) 612 / 1088 2ah v 42 ' v 3 + ( v 2 -v 3 ) 408 / 1088 v 42 '' v 7 + ( v 6 -v 7 ) 680 / 1088 2bh v 43 ' v 3 + ( v 2 -v 3 ) 340 / 1088 v 43 '' v 7 + ( v 6 -v 7 ) 748 / 1088 2ch v 44 ' v 3 + ( v 2 -v 3 ) 272 / 1088 v 44 '' v 7 + ( v 6 -v 7 ) 816 / 1088 2dh v 45 ' v 3 + ( v 2 -v 3 ) 204 / 1088 v 45 '' v 7 + ( v 6 -v 7 ) 884 / 1088 2eh v 46 ' v 3 + ( v 2 -v 3 ) 136 / 1088 v 46 '' v 7 + ( v 6 -v 7 ) 952 / 1088 2fh v 47 ' v 3 + ( v 2 -v 3 ) 68 / 1088 v 47 '' v 7 + ( v 6 -v 7 ) 1020 / 1088 30h v 48 ' v 3 v 48 '' v 6 31h v 49 ' v 4 + ( v 3 -v 4 ) 2278 / 2346 v 49 '' v 6 + ( v 5 -v 6 ) 68 / 2346 32h v 50 ' v 4 + ( v 3 -v 4 ) 2210 / 2346 v 50 '' v 6 + ( v 5 -v 6 ) 136 / 2346 33h v 51 ' v 4 + ( v 3 -v 4 ) 2142 / 2346 v 51 '' v 6 + ( v 5 -v 6 ) 204 / 2346 34h v 52 ' v 4 + ( v 3 -v 4 ) 2074 / 2346 v 52 '' v 6 + ( v 5 -v 6 ) 272 / 2346 35h v 53 ' v 4 + ( v 3 -v 4 ) 2006 / 2346 v 53 '' v 6 + ( v 5 -v 6 ) 340 / 2346 36h v 54 ' v 4 + ( v 3 -v 4 ) 1904 / 2346 v 54 '' v 6 + ( v 5 -v 6 ) 442 / 2346 37h v 55 ' v 4 + ( v 3 -v 4 ) 1802 / 2346 v 55 '' v 6 + ( v 5 -v 6 ) 544 / 2346 38h v 56 ' v 4 + ( v 3 -v 4 ) 1700 / 2346 v 56 '' v 6 + ( v 5 -v 6 ) 646 / 2346 39h v 57 ' v 4 + ( v 3 -v 4 ) 1564 / 2346 v 57 '' v 6 + ( v 5 -v 6 ) 782 / 2346 3ah v 58 ' v 4 + ( v 3 -v 4 ) 1428 / 2346 v 58 '' v 6 + ( v 5 -v 6 ) 918 / 2346 3bh v 59 ' v 4 + ( v 3 -v 4 ) 1258 / 2346 v 59 '' v 6 + ( v 5 -v 6 ) 1088 / 2346 3ch v 60 ' v 4 + ( v 3 -v 4 ) 1088 / 2346 v 60 '' v 6 + ( v 5 -v 6 ) 1258 / 2346 3dh v 61 ' v 4 + ( v 3 -v 4 ) 884 / 2346 v 61 '' v 6 + ( v 5 -v 6 ) 1462 / 2346 3eh v 62 ' v 4 + ( v 3 -v 4 ) 544 / 2346 v 62 '' v 6 + ( v 5 -v 6 ) 1802 / 2346 3fh v 63 ' v 4 v 63 '' v 5 out p ut volta g e 1 out p ut volta g e 2
data sheet s16449ej1v0ds 9 pd160062 6. relationship between input data and output pin data format: 6 bits 2 rgbs (6 dots) input width: 36 bits (2-pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 xxx s 419 s 420 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 (2) r,/l = l (left shift) output s 1 s 2 s 3 s 4 xxx s 419 s 420 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 pol s 2n ? 1 note s 2n note l v 0 to v 4 v 5 to v 9 h v 5 to v 9 v 0 to v 4 note s 2n ? 1 (odd output), s 2n (even output) 7. relationship between stb, pol and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. selected voltage v 0 to v 4 hi-z stb pol s 2n s 2n-1 hi-z hi-z selected voltage v 5 to v 9 selected voltage v 0 to v 4 selected voltage v 0 to v 4 selected voltage v 5 to v 9 selected voltage v 5 to v 9 remark hi-z: high impedance
data sheet s16449ej1v0ds 10 pd160062 8. relationship between stb, clk and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. figure 8 ? 1. output circuit block diagram dac + ? sw1 s n (v x ) v amp(in) output amp. figure 8 ? 2. output circuit timing waveform stb (external input) clk (external input) v amp(in) hi-z sw1: on sw1: off sw1: on [1] [2] s n (v out : external output) output output remarks 1. stb = l: sw1 = on, stb = h: sw1 = off 2. stb = h is acknowledged at timing [1] . 3. the display data latch is completed at timing [2] and the input voltage (v amp(in) : gray-scale level voltage) of the output amplifier changes.
data sheet s16449ej1v0ds 11 pd160062 9. current consumption control function the pd160062 has a power control function which can switch t he bias current of the output amplifier between four levels and a bias control function (bcont) which can be used to finely control the bias current. < power control function (lpc, hpc) > the bias current of the output amplif ier can be switched between four levels using lpc (low power control) pins and hpc (high power control) pins (show in below table). power mode lpc hpc high l l middle h or open l normal l h or open low h or open h or open following graph shows the relationship between each power modes and bias current. high middle normal low 6.00 8.00 7.00 9.00 v dd2 i dd2 remark this relationship is founded on results of simulati on and don?t assuring a characteristics of this product.
data sheet s16449ej1v0ds 12 pd160062 < bias current control function (bcont) > it is possible to fine-control the current consumption by using the bias current contro l function (bcont pin). when using this function, connect this pin to the stabilized ground potential (v ss2 ) via an external resistor (r ext ). when not using this function, leave this pin open. figure 9 ? 1. bias current control function (bcont) pd160062 b cont hpc r ext h/l v ss2 lpc h/l refer to the table below for the percentage of current regulation when using the bias current control function. table 9 ? 1. current consumption regulation percentage compared to normal mode (v dd1 = 3.3 v, v dd2 = 8.7 v) current consumption regulation percentage (%) r ext (k ) lpc = l lpc = h/open (open) 100 65 50 110 70 20 115 80 10 120 85 remark the above current consumpt ion regulation percentages are founded on results of simulation and don?t assuring a characteristics of this product. caution because the power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver ic, when this occurs, the characteristics of the output amplifier will simultaneously cha nge. therefore, when using these functions, be sure to sufficiently evaluate the picture quality.
data sheet s16449ej1v0ds 13 pd160062 10. electrical specifications absolute maximum ratings (t a = 25c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ? 0.5 to +4.0 v driver part supply voltage v dd2 ? 0.5 to +10.0 v logic part input voltage v i1 ? 0.5 to v dd1 +0.5 v driver part input voltage v i2 ? 0.5 to v dd2 +0.5 v logic part output voltage v o1 ? 0.5 to v dd1 +0.5 v driver part output voltage v o2 ? 0.5 to v dd2 +0.5 v operating ambient temperature t a ? 10 to +75 c storage temperature t stg ? 55 to +125 c caution product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter/ that is, the absolute maximum ratings ar e rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ? 10 to +75c, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic part supply voltage v dd1 2.3 3.6 v driver part supply voltage v dd2 8.0 8.5 9.0 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.3 v dd1 v v 0 to v 4 0.5 v dd2 v dd2 ? 0.1 v -corrected voltage v 5 to v 9 v ss2 +0.1 0.5 v dd2 v driver part output voltage v o v ss2 +0.1 v dd2 ? 0.1 v maximum clock frequency f clk v dd1 = 2.3 v 45 mhz
data sheet s16449ej1v0ds 14 pd160062 electrical characteristics (t a = ? 10 to +75c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.0 to 9.0 v, v ss1 = v ss2 = 0 v, unless otherwise specified, power mode = normal, bcont = open.) parameter symbol conditions min. typ. max. unit input leak current i il 1.0 a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v -corrected resistance r v dd2 = 8.5 v, v 0 to v 4 = v 5 to v 9 = 4.0 v 5.4 10.8 21.6 k i voh v x = 7.0 v, v out = 6.5 v note ? 30 a driver output current i vol v x = 1.0 v, v out = 1.5 v note 30 a output voltage deviation v o 7 20 mv output swing difference deviation v p?p t a = 25c, v dd1 = 3.3 v, v dd2 = 8.5 v, v out = 2.0 v, 4.25 v, 6.5 v 2 15 mv logic part dynamic current consumption i dd1 v dd1 1.0 6.5 ma driver part dynamic current consumption i dd2 v dd2 , with no load 3.0 6.5 ma note v x refers to the output voltage of analog output pins s 1 to s 420 . v out refers to the voltage applied to analog output pins s 1 to s 420 . cautions 1. f stb = 64 khz, f clk = 40 mhz 2. the typ. values refer to an all black or all wh ite input pattern. the ma x. value refers to the measured values in the dot checkerboard input pattern. 3. refers to the current consumption per driver when cascades ar e connected under the assumption of sxga+ single-s ided mounting (10 units). switching characteristics (t a = ? 10 to +75c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.0 to 9.0 v, v ss1 = v ss2 = 0 v, unless otherwise specified, power mode = normal, bcont = open.) parameter symbol conditions min. typ. max. unit start pulse delay time t plh1 c l = 10 pf 10 20 ns t plh2 2.5 5 s t plh3 5 8 s t phl2 2.5 5 s driver output delay time t phl3 c l = 75 pf, r l = 5 k 5 8 s c i1 sthr (sthl) excluded, t a = 25c 10 pf input capacitance c i2 sthr (sthl), t a = 25c 10 pf
data sheet s16449ej1v0ds 15 pd160062 timing requirement (t a = ? 10 to +75c, v dd1 = 2.3 to 3.6 v, v ss1 = 0 v, t r = t f = 5.0 ns) parameter symbol conditions min. typ. max. unit clock pulse width pw clk 22 ns clock pulse high period pw clk(h) 4 ns clock pulse low period pw clk(l) 4 ns data setup time t setup1 4 ns data hold time t hold1 0 ns start pulse setup time t setup2 4 ns start pulse hold time t hold2 0 ns pol21, pol22 setup time t setup3 4 ns pol21, pol22 hold time t hold3 0 ns stb pulse width pw stb 2 clk last data timing t ldt 2 clk clk-stb time t clk-stb clk stb 6 ns stb-clk time t stb-clk stb clk 9 ns time between stb and start pulse t stb-sth stb sthr(sthl) 2 clk pol-stb time t pol-stb pol or stb ?5 ns stb-pol time t stb-pol stb pol or 6 ns remark unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 .
data sheet s16449ej1v0ds 16 pd160062 switching characteristics waveform (r,/l = h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol (v x ) s n stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3707172 513 514 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage 0.1 v dd2 6-bit accuracy t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 409 to d 414 d 415 to d 420 d 421 to d 426 d 3067 to d 3072 invalid invalid v dd1 v ss1 t setup3 t hold3 pol21, pol22 (1st dr.) (1st dr.) invalid
data sheet s16449ej1v0ds 17 pd160062 11. recommended mounting conditions the following conditions must be met for soldering conditions of the pd160062. for more details, refer to the semiconductor device mount manual (http://www.necel.com/pkg /en/mount/index.html). please consult with our sales offices in case other solderin g process is used, or in case the soldering is done under different conditions. pd160062n- : tcp (tab package) mounting condition mounting method condition soldering heating tool 300 to 350c, heating for 2 to 3 seconds, pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c, pressure 3 to 8 kg/cm 2 , time 3 to 5 seconds. real bonding 165 to 180c, pressure 25 to 45 kg/cm 2 , time 30 to 40 seconds. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for packag ing the acf part, please contact the acf manufacturing company. be sure to avoid usin g two or more packagi ng methods at a time.
data sheet s16449ej1v0ds 18 pd160062 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd160062 reference documents nec semiconductor device reliability /quality control system (c10983e) quality grades on nec semi conductor devices (c11531e) the information in this document is current as of july, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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