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SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 1 version 1.1 SN8F2250B series user?s manual sn8f2251b sn8f22511b sn8f22521b sn8f2253b sn8f22531b sn8f2255b s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or desig n. sonix does not assume any liability arising out of the application or use of an y product or circuit described her ein; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to suppor t or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and re asonable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 2 version 1.1 amendment history version date description ver1.0 2009/3/14 version 1.0 ver1.1 2009/5/11 modify wakeup time?s description
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 3 version 1.1 table of content amendment history .............................................................................................................. 2 1 product o verview ............................................................................................................ 7 1.1 featur es ....................................................................................................................... ...... 7 1.2 system block diagram ................................................................................................... 8 1.3 pin assign ment.................................................................................................................. 9 1.4 pin descript ions............................................................................................................. 11 1.5 pin circuit diagrams ..................................................................................................... 12 2 central processo r unit (c pu) ................................................................................... 13 2.1 memory map ..................................................................................................................... 13 2.1.1 program me mory (rom) ........................................................................................ 13 2.1.1.1 reset ve ctor ( 0000h) ....................................................................................... 14 2.1.1.2 interrupt vector (0008h)............................................................................... 15 2.1.1.3 look-up ta ble desc ription ........................................................................... 17 2.1.1.4 jump t able desc ription ................................................................................. 19 2.1.1.5 checksu m calculation .................................................................................. 21 2.1.2 code op tion table .................................................................................................. 22 2.1.3 data me mory (ram) ................................................................................................. 23 2.1.4 system registe r ..................................................................................................... 24 2.1.4.1 system re gister t able................................................................................... 24 2.1.4.2 system regis ter desc ription ..................................................................... 24 2.1.4.3 bit definition of system register ............................................................... 25 2.1.4.4 a ccumulat or ..................................................................................................... 27 2.1.4.5 progr am flag .................................................................................................... 28 2.1.4.6 progr am co unter............................................................................................ 29 2.1.4.7 y, z regis ters ..................................................................................................... 32 2.1.4.8 r registe rs......................................................................................................... 33 2.2 addressing mode ........................................................................................................... 34 2.2.1 immediate addressing mode ............................................................................... 34 2.2.2 directly ad dressing mode ................................................................................. 34 2.2.3 indirectly addressing mode.............................................................................. 34 2.3 stack operation ............................................................................................................ 35 2.3.1 o vervi ew ................................................................................................................. ... 35 2.3.2 stack registe rs...................................................................................................... 36 2.3.3 stack oper ation ex ample.................................................................................... 37 3 reset .......................................................................................................................... .......... 38 3.1 overvi ew....................................................................................................................... .... 38 3.2 power on reset.............................................................................................................. 39 3.3 watchdog reset ............................................................................................................ 39 3.4 brown out reset ........................................................................................................... 40 3.4.1 brown ou t descri ption........................................................................................ 40 3.4.2 the system operatin g voltage de csription ............................................... 41 3.4.3 brown out r eset impro vement......................................................................... 42 3.5 external reset............................................................................................................... 43 3.6 external reset circuit ............................................................................................... 43 3.6.1 simply rc reset cir cuit ................................................................................................. 43
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 4 version 1.1 3.6.2 diode & rc reset cir cuit ............................................................................................... 44 3.6.3 zener diode reset cir cuit .............................................................................................. 44 3.6.4 voltage bias reset circuit.............................................................................................. 45 3.6.5 external reset ic ........................................................................................................ ... 45 4 system cl ock ................................................................................................................... . 46 4.1 overvi ew....................................................................................................................... .... 46 4.2 clock block diagram ................................................................................................... 46 4.3 oscm registe r ................................................................................................................ 47 4.4 system high clock......................................................................................................... 48 4.4.1 external high clock ............................................................................................. 48 4.4.1.1 cryst al/ceramic............................................................................................... 49 4.1.1.2 external clock s ignal................................................................................... 50 4.2 system low clock ......................................................................................................... 51 4.2.1 system cloc k measure ment............................................................................... 51 5 system operat ion mode................................................................................................ 52 5.1 overvi ew....................................................................................................................... .... 52 5.2 system mode switching example ............................................................................. 53 5.3 wakeup......................................................................................................................... ...... 55 5.3.1 o vervi ew ................................................................................................................. ... 55 5.3.2 wakeu p time .............................................................................................................. 55 6 interr upt...................................................................................................................... ...... 56 6.1 overvi ew....................................................................................................................... .... 56 6.2 inten interrupt enable register ............................................................................ 57 6.3 intrq interrupt request register......................................................................... 58 6.4 gie global interrupt operation.............................................................................. 59 6.5 push, pop routine .......................................................................................................... 59 6.6 int0 (p0.0) & int1 (p0.1) interrupt operation........................................................... 60 6.7 t0 interrupt operation............................................................................................... 62 6.8 t1 interrupt operation............................................................................................... 63 6.9 tc0 interrupt operation ............................................................................................ 64 6.10 tc1 interrupt operation .......................................................................................... 65 6.11 usb interrupt operation.......................................................................................... 66 6.12 wakeup interrupt operation.................................................................................. 67 6.13 sio interrupt operation ........................................................................................... 68 6.14 multi-interrupt operation ...................................................................................... 69 7 i/o port....................................................................................................................... .......... 70 7.1 i/o port mode ................................................................................................................... 70 7.2 i/o pull up register....................................................................................................... 71 7.3 i/o port data register ................................................................................................. 72 7.4 i/o port1 wakeup control registe r ....................................................................... 73 8 timers......................................................................................................................... .......... 74 8.1 watchdog timer ............................................................................................................. 74 8.2 timer 0 (t0)......................................................................................................................... 76 8.2.1 o vervi ew ................................................................................................................. ... 76 8.2.2 t0m mode register ................................................................................................. 76 8.2.3 t0c count ing register ......................................................................................... 77 8.2.4 t0 timer o peration se quence ............................................................................ 78
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 5 version 1.1 8.3 timer t1 (t1)....................................................................................................................... 79 8.3.1 o vervi ew ................................................................................................................. ... 79 8.3.2 t1m mode register ................................................................................................. 79 8.3.3 t1c count ing register ......................................................................................... 80 8.3.4 t1 timer o peration se quence ............................................................................ 81 8.4 timer/counter 0 (tc0).................................................................................................... 82 8.4.1 o vervi ew ................................................................................................................. ... 82 8.4.2 tc0m mo de regis ter............................................................................................... 83 8.4.3 tc0c count ing register....................................................................................... 84 8.4.4 tc0r auto -load re gister ..................................................................................... 85 8.4.5 tc0 clock freque ncy output (buzzer)........................................................... 86 8.4.6 tc0 timer o peration seq uence ......................................................................... 87 8.5 pwm0 mode........................................................................................................................ 88 8.5.1 o vervi ew ................................................................................................................. ... 88 8.5.2 tcxirq and pwm duty ................................................................................................. 89 8.5.3 pwm duty wit h tcxr ch anging..................................................................................... 90 8.5.4 pwm progr am exam ple ......................................................................................... 91 8.6 timer/counter 1 (tc1).................................................................................................... 92 8.6.1 o vervi ew ................................................................................................................. ... 92 8.6.2 tc1m mo de regis ter............................................................................................... 93 8.6.3 tc1c count ing register....................................................................................... 94 8.6.4 tc1r auto -load re gister ..................................................................................... 95 8.6.5 tc1 clock freque ncy output (buzzer)........................................................... 96 8.6.6 tc1 timer o peration seq uence ......................................................................... 97 8.7 pwm1 mode........................................................................................................................ 98 8.7.1 o vervi ew ................................................................................................................. ... 98 8.7.2 tcxirq and pwm duty ................................................................................................. 99 8.7.3 pwm duty wit h tcxr ch anging................................................................................... 100 8.7.4 pwm progr am exam ple ....................................................................................... 101 9 universal seria l bus (u sb) ........................................................................................ 102 9.1 overvi ew....................................................................................................................... .. 102 9.2 usb machine ................................................................................................................... 102 9.3 usb interrupt................................................................................................................ 102 9.4 usb enumeration.......................................................................................................... 103 9.5 usb registe rs ............................................................................................................... 104 9.5.1 usb device address re gister .......................................................................... 104 9.5.2 usb stat us register............................................................................................ 104 9.5.3 usb data count re gister................................................................................... 105 9.5.4 usb enable control re gister ......................................................................... 105 9.5.5 usb endpoint?s ack han dshaking flag register ..................................................... 105 9.5.6 usb endpoint?s nak han dshaking flag register ..................................................... 106 9.5.7 usb endpoint 0 enable re gister ..................................................................... 106 9.5.8 usb endpoint 1 enable re gister ..................................................................... 107 9.5.9 usb endpoint 2 enable re gister ..................................................................... 107 9.5.10 usb endpoint 3 enable re gister ................................................................... 108 9.5.11 usb data p ointer re gister ............................................................................. 108 9.5.12 usb data read /write re gister....................................................................... 108 9.5.13 usb endpoint out to ken data byt es count er......................................... 109 9.5.14 upid register........................................................................................................ 109 9.5.15 endpoint toggle bi t control register..................................................... 109
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 6 version 1.1 10 serial input/output transc eiver........................................................................ 110 10.1 overvi ew....................................................................................................................... 110 10.2 siom mode register .................................................................................................. 113 10.3 siob data buff er ........................................................................................................ 114 10.4 sior register description ..................................................................................... 114 11 flash.......................................................................................................................... ..... 115 11.1 overvi ew....................................................................................................................... 115 11.2 flash programming/erase control register................................................ 115 11.3 programming/erase address register ............................................................ 116 11.4 programming/erase data register.................................................................... 117 11.4.1 f lash i n - system - programming mapping address ......................................................... 117 12 instruction table ..................................................................................................... 118 13 developmen t tool..................................................................................................... 119 13.1 ice (i n c ircuit e mulation ) ............................................................................................ 119 13.2 sn8f2250 ev- kit ........................................................................................................... 120 13.3 sn8f2250 t ransition b oard ........................................................................................ 120 14 electrical ch aracteristic ................................................................................... 121 14.1 absolute maximum rating.................................................................................... 121 14.2 electrical characte ristic ................................................................................. 121 15 flash rom prog ramming pin.................................................................................. 122 16 package in formation............................................................................................... 124 16.1 lqfp32 pin ................................................................................................................... 124 16.2 sop 24 pin .................................................................................................................... 125 16.3 sop 20 pin .................................................................................................................... 125 16.4 ssop 20 pin.................................................................................................................. 127 16.5 qfn 24 pin .................................................................................................................... 128 16.6 qfn 16 pin .................................................................................................................... 129 16.7 ssop 16 pin.................................................................................................................. 130 17 marking de finition .................................................................................................... 131 17.1 introd uction............................................................................................................ 131 17.2 marking indetification system.......................................................................... 131 17.3 marking example..................................................................................................... 132 17.4 datecode system .................................................................................................. 132
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 7 version 1.1 1 product overview 1.1 features ) features selection table timer chip rom ram stack t0 t1 tc0 tc1 sio pwm wake-up pin no. i/o pin package sn8f2251b 10k*16 512*8 8 v v v v v v 3 8 qfn sn8f22511b 10k*16 512*8 8 v v v v v v 3 8 ssop sn8f22521b 10k*16 512*8 8 v v v v v v 5 12 sop/ssop sn8f2253b 10k*16 512*8 8 v v v v v v 7 16 sop sn8f22531b 10k*16 512*8 8 v v v v v v 7 16 qfn sn8f2255b 10k*16 512*8 8 v v v v v v 13 24 lqfp ? memory configuration ? 9 interrupt sources. flash rom size : 10k x 16 bits, including in system programming function. 20000 erase/write cycles. seven internal interrupts: t0, t1, tc0, tc1, usb, sio, wakeup ram size : 512 x 8 bits. two external interrupt: int0, int1. ? 8 levels stack buffer ? one sio function for data transfer (serial peripheral interface) ? i/o pin configuration bi-directional: p0, p1, p2, p5 ? one 16-bit timer counters. (t1) wake-up: p0/p1 level change. pull-up resistors: p0, p1, p2, p5. ? three 8 bits timer counter (t0, tc0, tc1) external interrupt: p0 .0, p0.1 controlled by pedge. tc0, tc1. each has 8 bit pwm function (duty/cycle programmable). ? full speed usb 2.0 ? two system clocks. conforms to usb specification, version 2.0. internal low clock: rc type 24khz which fosc = 24khz. 3.3v regulator output for usb d+ pin internal external x?tal: 6mhz/12mhz/16mhz x?tal which the fosc will be 12mhz. 1.5k ohm pull-up resistor. integrated usb transceiver. ? four operating modes. supports 1 full speed usb device address, normal mode: both high and low clocks active. 1 control endpoint slow mode: low clock only. 3 interrupt in/out endpoints, each has 16 bytes sleep: both high and low clocks stop. fifo green mode: periodical wakeup by timer. ? powerful instructions ? package one clocks per instruction cycle (1t) qfn16, ssop16,sop20, ssop20, sop24, qfn24, most of instructions are one cycle only. lqfp32 all rom area jmp instruction. all rom area call address instruction. ? on chip watchdog timer. all rom area lookup table function (movc) ? in-system re-programmability allows easy firmware update
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 8 version 1.1 1.2 system block diagram interrupt control 6mhz/12mhz/16mhz oscillator acc internal low rc timing generator ram system registers lvd watchdog timer timer & counter sio alu pc flags ir flash memory full speed usb sie 3.3v regulator vreg33 d+ d- pll p0 p1 p2 p5 2.5v regulator vreg25 pwm buzzer
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 9 version 1.1 1.3 pin assignment sn8f2251bj (qfn 16 pins) p1.1 p1.0 p5.0/sck p5.1/sdi 16 15 14 13 p0.1/int1 1 12 p5.2/sdo xin 2 11 vdd xout 3 f2251bj 10 p2.0 vreg25 4 9 p2.1 5678 vss dp dn vreg33 sn8f22511bx (ssop 16 pins) p5.0/sck 1 u 16 p2.1 p5.2/sdo 2 15 p2.0 p5.1/sdi 3 14 vdd p1.0 4 13 vreg33 p1.1 5 12 dn p0.1/int1 6 11 dp xin 7 10 vss xout 8 9 vreg25 sn8f22511bx sn8f22521bs (sop 20 pins) sn8f22521bx (ssop 20 pins) p5.0/sck 1 u 20 p2.1 p5.2/sdo 2 19 p2.0 p5.1/sdi 3 18 vdd p5.3/pwm1 4 17 vreg33 p5.4/pwm0 5 16 dn p1.0 6 15 dp p1.1 7 14 vss p0.0/int0 8 13 vreg25 p0.1/int1 9 12 xout p0.4/rst 10 11 xin sn8f22521bs sn8f22521bx
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 10 version 1.1 sn8f2253bs (sop 24 pins) p5.0/sck 1 u 24 p2.3 p5.2/sdo 2 23 p2.2 p5.1/sdi 3 22 p2.1 p5.3/pwm1 4 21 p2.0 p5.4/pwm0 5 20 vdd p1.0 6 19 vreg33 p1.1 7 18 dn p1.2 8 17 dp p1.3 9 16 vss p0.0/int0 10 15 vreg25 p0.1/int1 11 14 xout p0.4/rst 12 13 xin sn8f2253bs sn8f22531bj (qfn 24 pins) p2.0 vdd vreg33 dn dp vss 24 23 22 21 20 19 p2.1 1 18 vreg25 p2.2 2 17 xout p2.3 3 sn8f22531bj 16 xin p5.0/sck 4 15 p0.4/rst p5.2/sdo 5 14 p0.1/int1 p5.1/sdi 6 13 p0.0/int0 7 8 9 10 11 12 p5.3/pwm1 p5.4/pwm0 p1.0 p1.1 p1.2 p1.3 sn8f2255bf (lqfp 32 pins) p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p5.4/pwm0 32 31 30 29 28 27 26 25 p1.7 1 24 p5.3/pwm1 p0.0/int0 2 23 p5.1/sdi p0.1/int1 3 22 p5.2/sdo p0.2 4 sn8f2255bf 21 p5.0/sck p0.3 5 20 p2.5 p0.4/rst 6 19 p2.4 xin 7 18 p2.3 xout 8 17 p2.2 9 10 11 12 13 14 15 16 vreg25 vss dp dn vreg33 vdd p2.0 p2.1
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 11 version 1.1 1.4 pin descriptions pin name type description vdd, vss p power supply input pins for digital circuit. p0.0/int0 i/o p0.0: port 0.0 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. built wakeup function. int0: external interrupt 0 input pin. p0.1/int1 i/o p0.1: port 0.1 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. built wakeup function. int1: external interrupt 1 input pin. p0[3:2] i/o p0: port 0 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. built wakeup function. p0.4/rst i rst is system external reset input pin under ext_rst mode, schmitt trigger structure, active ?low?, and normal stay to ?high?. p0.4 is input only pin with pull-up resistor under p0.4 mode. built wakeup function. p1[7:0] i/o p1: port 1 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. built wakeup function. p2[5:0] i/o p2: port 2 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. p5.0/sck i/o p5.0: port 5.0 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. sck: sio output clock pin. p5.1 /sdi i/o p5.1: port 5.1 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. sdi: sio data input pin. p5.2/sdo i/o p5.2: port 5.2 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. sdo: sio data output pin. p5.3/pwm1 i/o p5: port 5 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. pwm1: pmw 1 output pin. p5.4/pwm0 i/o p5: port 5 bi-direction pin. schmitt trigger structure and built-i n pull-up resisters as input mode. pwm0: pmw 0 output pin. xout i/o xout: oscillator output pi n while external crystal enable. xin i/o xin: oscillator input pin while exte rnal oscillator enable (crystal and rc). vreg25 p 2.5v power pin. please connect 1uf capacitor to gnd. vreg33 p 3.3v power pin. please con nect xuf capacitor to gnd. x=1~10. d+, d- i/o usb differential data line.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 12 version 1.1 1.5 pin circuit diagrams port 0, 1, 2, 5 structures: pull-up pin output latch pnur input bus pnm output bus port 0.4 structure: pi n ext. reset code option int. bus int. rst pull-up
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 13 version 1.1 2 central processor unit (cpu) 2.1 memory map 2.1.1 program memory (rom) ) 10k words rom rom 0000h reset vector user reset vector jump to user start address 0001h . . 0007h general purpose area 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . . . . general purpose area end of user program 27f8h . . 27ffh reserved
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 14 version 1.1 2.1.1.1 reset vector (0000h) a one-word vector address area is used to execute system reset. ) power on reset (nt0=1, npd=0). ) watchdog reset (nt0=0, npd=0). ) external reset (nt0=1, npd=1). after power on reset, external reset or watchdog timer over flow reset, then the chip will restart the program from address 0000h an d all system registers will be set as default values . it is easy to know rese t status from nt0, npd flags of pflag register. the following example shows the way to define the reset vector in the program memory. ? example: defining reset vector org 0 ; 0000h jmp start ; jump to user program address. ? org 10h start: ; 0010h, the head of user program. ? ; user program ? endp ; end of program
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 15 version 1.1 2.1.1.2 interrupt vector (0008h) a 1-word vector address area is used to execute interr upt request. if any interrupt se rvice executes, the program counter (pc) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. users have to define the interr upt vector. the following example shows the wa y to define the interrupt vector in the program memory. ? note:?push?, ?pop? instructions save and load ac c/pflag without (nt0, npd) . push/pop buffer is a unique buffer and only one level. ? example: defining interrupt vector. the in terrupt service routine is following org 8. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. push ; save acc and pflag register to buffers. ? ? pop ; load acc and pflag register from buffers. reti ; end of interrupt service routine ? start: ; the head of user program. ? ; user program ? jmp start ; end of user program ? endp ; end of program
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 16 version 1.1 ? example: defining interrupt vector. the interru pt service routine is following user program. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. jmp my_irq ; 0008h, jump to interrupt service routine address. org 10h start: ; 0010h, the head of user program. ? ; user program. ? ? jmp start ; end of user program. ? my_irq: ;the head of interrupt service routine. push ; save acc and pflag register to buffers. ? ? pop ; load acc and pflag register from buffers. reti ; end of interrupt service routine. ? endp ; end of program. ? note: it is easy to understand the rules of sonix program from demo programs given above. these points are as following: 1. the address 0000h is a ?jmp? instruction to make the program starts from the beginning. 2. the address 0008h is interrupt vector. 3. user?s program is a loop routine for main purpose application.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 17 version 1.1 2.1.1.3 look-up table description in the rom?s data lookup function, y register is pointed to middle byte address (bit 8~bit 15) and z register is pointed to low byte address (bit 0~bit 7) of rom. after movc instruction executed, t he low-byte data will be stored in acc and high-byte data stored in r register. ? example: to look up the rom data located ?table1?. b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h ; increment the index address for next address. incms z ; z+1 jmp @f ; z is not overflow. incms y ; z overflow (ffh ? 00), ? y=y+1 nop ; ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? ? note: the y register will not increase automatically when z register crosses boundary from 0xff to 0x00. therefore, user must take care such situation to avoid loop-up table errors. if z register overflows, y register must be added one. the following inc_yz macro shows a simple method to process y and z registers automatically. ? example: inc_yz macro. inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 18 version 1.1 ? example: modify above exam ple by ?inc_yz? macro. b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h inc_yz ; increment the index address for next address. ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? the other example of loop-up table is to add y or z index regi ster by accumulator. please be careful if ?carry? happen. ? example: increase y and z register by b0add/add instruction. b0mov y, #table1$m ; to set lookup table?s middle address. b0mov z, #table1$l ; to set lookup table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 ? table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ?
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 19 version 1.1 2.1.1.4 jump table description the jump table operation is one of multi-address jumpin g function. add low-byte program counter (pcl) and acc value to get one new pcl. if pcl is overflow after pcl+ acc, pch adds one automatically. the new program counter (pc) points to a series jump instructions as a listing t able. it is easy to make a multi-jump program depends on the value of the accumulator (a). ? note: pch only support pc up counting result and doesn?t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl?acc, pch keeps value and not change. ? example: jump table. org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, pch + 1 when pcl overflow occurs . jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point sonix provides a macro for safe jump table function. th is macro will check the rom boundary and move the jump table to the right position automatically. the side e ffect of this macro maybe wastes some rom size. ? example: if ?jump table? crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm ? note: ?val? is the number of the jump table listing number.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 20 version 1.1 ? example: ?@jmp_a? application in sonix macro file called ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is across a rom boundary (0x00ff~ 0x0100), the ?@jmp_a? macro will adjust the jump table routine begin from next ram boundary (0x0100). ? example: ?@jmp_a? operation. ; before compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x00fd jmp a0point ; acc = 0, jump to a0point 0x00fe jmp a1point ; acc = 1, jump to a1point 0x00ff jmp a2point ; acc = 2, jump to a2point 0x0100 jmp a3point ; acc = 3, jump to a3point 0x0101 jmp a4point ; acc = 4, jump to a4point ; after compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x0100 jmp a0point ; acc = 0, jump to a0point 0x0101 jmp a1point ; acc = 1, jump to a1point 0x0102 jmp a2point ; acc = 2, jump to a2point 0x0103 jmp a3point ; acc = 3, jump to a3point 0x0104 jmp a4point ; acc = 4, jump to a4point
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 21 version 1.1 2.1.1.5 checksum calculation the last rom addresses are reserved area. user should av oid these addresses (last address) when calculate the checksum value. ? example: the demo program shows how to calculated checksum from 00h to the end of user?s code. mov a,#end_user_code$l b0mov end_addr1, a ; save low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2, a ; save middle end address to end_addr2 clr y ; set y to 00h clr z ; set z to 00h @@: movc b0bset fc ; clear c flag add data1, a ; add a to data1 mov a, r adc data2, a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; if z = 00h increase y end_check: mov a, end_addr1 cmprs a, z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a, end_addr2 cmprs a, y ; if yes, check if y = middle end address jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is done. y_add_1: incms y ; increase y nop jmp @b ; jump to checksum calculate checksum_end: ? ? end_user_code: ; label of program end
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 22 version 1.1 2.1.2 code option table code option content function description 6mhz 6mhz crystal /resonator for external oscillator. 12mhz 12mhz crystal /resonator for external oscillator. ext_osc 16mhz 16mhz crystal /resonator for external oscillator. always_on watchdog timer is always on enable even in power down and green mode. enable enable watchdog timer. watchdog timer stops in power down mode and green mode. watch_dog disable disable watchdog function. fhosc/1 instruction cycle is 12 mhz clock. fhosc/2 instruction cycle is 6 mhz clock. fcpu fhosc/4 instruction cycle is 3 mhz clock. reset enable external reset pin. reset_pin p04 enable p0.4 input only, with pull-up resistor function. enable enable rom code security function. security0 disable disable rom code security function. enable enable rom code lock address (0x2000~0x27ff) security function. security1 disable disable rom code lock address (0x2000~0x27ff) security function. ? note: fcpu code option is only available for high clock. fcpu of slow mode is flosc/4.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 23 version 1.1 2.1.3 data memory (ram) ) 512 x 8-bit ram address ram location 000h ? ? ? ? ? 07fh general purpose area bank 0 080h ? ? ? ? ? system register bank 0 0ffh end of bank 0 area 80h~ffh of bank 0 store system registers (128 bytes). 100h ? ? ? ? ? bank1 1ffh general purpose area bank1 200h ? ? ? ? ? bank2 27fh general purpose area bank2 ) 56 x 8-bit ram for usb data fifo 56 x 8 ram (fifo) 00h ~ 07h endpoint 0 ram (8 byte) 08h ~ 17h endpoint 1 ram (16 byte) 18h ~ 27h endpoint 2 ram (16byte) 28h ~ 37h endpoint 3 ram (16 byte)
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 24 version 1.1 2.1.4 system register 2.1.4.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag rbank tc0m tc0c tc0r tc1m tc1c tc1r - - 9 uda ustat us ep0ou t_cnt usb_in t_en ep _ack ep _nak ue0r ue1r ue2r ue3r a - - - udp0 - udr0_ r udr0_ w ep1ou t_cnt ep2ou t_cnt ep3ou t_cnt upid utoggle - - - b - - - - siom sior siob - p0m - pecmd perom l perom h peram l peram cnt pedge c p1w p1m p2m - - p5m intrq1 inten1 intrq inten oscm - wdtr - pcl pch d p0 p1 p2 - - p5 - - t0m t0c t1m t1c_l t1c_h - - stkp e p0ur p1ur p2ur - - p5ur - @yz - - - - - - - - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.1.4.2 system regis ter description r = working register and rom look-up data buffer. y, z = working, @yz and rom addressing register. pflag = rom page and special flag register . rbank = ram bank selection register. uda = usb control register. ue0r~ue3r = endpoint 0~3 control registers. udp0 = usb fifo address pointer. udr0_r = usb fifo read data buffer by udp0 point to. udr0_w = usb fifo write data buffer by udp0 point to. ep_nak = endpoint nak flag register. ep_ack = endpoint ack flag register. udr0_w = usb fifo write data buffer by udp1 point to. utoggle = usb endpoint toggle bit control regi ster. upid = usb bus control register. ustatus = usb status register. usb_int_en = u sb interrupt enable/disable control register. epxout_cnt = usb endpoint 1~3 out token data byte counter sior = sio?s clock reload buffer siom = sio mode control register. pedge = p0.0, p0.1 edge direction register. siob = sio?s data buffer. inten = interrupt enable register. pnm = port n input/output mode register. inten1 = interrupt1 enable register. intrq = interrupt request register. wdtr = watchdog timer clear register. intrq1 = interrupt1 request register. pch, pcl = program counter. oscm = oscillator mode register. tnm = tn mode register. n = 0, 1, c0, c1 tc0r = tc0 auto-reload data buffer. tnr = tn register. n = c0, c1 pn = port n data buffer. stkp = stack pointer buffer. tnc = t0 counting register. n = 0, 1, c0, c1 @yz = ram yz indirect addressing index pointer. pnur = port n pull-up resister control regi ster. stk0~stk7 = stack 0 ~ stack 7 buffer. p1w = port 1 wakeup control register. pecmd = isp command register. perom = isp rom address. peram = isp ram mapping address. peramcnt = isp ram programming counter register.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 25 version 1.1 2.1.4.3 bit definition of system register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w remarks 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h nt0 npd c dc z r/w pflag 087h rbnks1 rbnks0 r/w rbank 088h tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out r/w tc0m 089h tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 08ah tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 r/w tc0r 08bh tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload0 tc1out pwm0out r/w tc1m 08ch tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 08dh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 r/w tc1r 090h ude uda6 uda5 uda4 uda3 uda2 uda1 uda0 r/w uda 091h sof bus_rst suspend ep0_setup ep0_in ep0_out r/w ustatus 092h uep0oc3 uep0oc2 uep0oc1 uep0oc0 r/w ep0out_cnt 093h reg_en dp_pu_en sof_int _en ep3nak _int_en ep2nak _int_en ep1nak _int_en r/w usb_int_en 094h ep3_ack ep2_ack ep1_ack r/w ep_ack 095h ep3_nak ep2_nak ep1_nak r/w ep_nak 096h ue0m1 ue0m0 ue0c3 ue0c2 ue0c1 ue0c0 r/w ue0r 097h ue1e ue1m1 ue1m0 ue1c4 ue1c3 ue1c2 ue1c1 ue1c0 r/w ue1r 098h ue2e ue2m1 ue2m0 ue2c4 ue2c3 ue2c2 ue2c1 ue2c0 r/w ue2r 099h ue3e ue3m1 ue3m0 ue3c4 ue3c3 ue3c2 ue3c1 ue3c0 r/w ue3r 0a3h udp07 udp06 udp05 udp04 udp03 udp02 udp01 udp00 r/w udp0 0a5h udr0_r7 udr0_r6 udr0_r5 udr0_r4 udr0_r3 udr0_r2 udr0_r1 udr0_r0 r/w udr0_r 0a6h udr0_w7 udr0_w6 udr0_w5 udr0_w4 udr 0_w3 udr0_w2 udr0_w1 udr0_w0 r/w udr0_w 0a7h uep1oc4 uep1oc3 uep1oc2 uep1oc1 uep1oc0 r/w ep1out_cnt 0a8h uep2oc4 uep2oc3 uep2oc2 uep2oc1 uep2oc0 r/w ep2out_cnt 0a9h uep3oc4 uep3oc3 uep3oc2 uep3oc1 uep3oc0 r/w ep3out_cnt 0abh ubde ddp ddn r/w upid 0ach ep3_data0 /1 ep2_data0 /1 ep1_data0 /1 r/w utoggle 0b4h senb start srate1 srat e0 mlsb sckmd sedge sp r/w siom 0b5h sior7 sior6 sior5 sior4 sior3 sior2 sior1 sior0 w sior 0b6h siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w siob 0b8h p03m p02m p01m p00m r/w p0m 0bah pecmd7 pecmd6 pecmd5 pecmd4 pec md3 pecmd2 pecmd1 pecmd0 w pecmd 0bbh peroml7 peroml6 peroml5 peroml4 peroml3 peroml2 peroml1 peroml0 r/w peroml 0bch peormh7 peormh6 peormh5 peormh4 peo rmh3 peormh2 peormh1 peormh0 r/w peormh 0bdh peraml7 peraml6 peraml5 peraml4 peraml3 peraml2 peraml1 peraml0 r/w peraml 0beh peramcnt 4 peramcnt 3 peramcnt 2 peramcnt 1 peramcnt 0 peraml8 r/w peramcnt 0bfh p01g1 p01g0 p00g1 p00g0 r/w pedge 0c0h p17w p16w p15w p14w p 13w p12w p11w p10w r/w p1w 0c1h p17m p16m p15m p14m p13m p12m p11m p10m r/w p1m 0c2h p25m p24m p23m p22m p21m p20m r/w p2m 0c5h p54m p53m p52m p51m p50m r/w p5m 0c6h tc1irq tc0irq r/w intrq1 0c7h tc1ien tc0ien r/w inten1 0c8h sofirq usbirq t1irq t0irq sioirq wakeirq p01irq p00irq r/w intrq 0c9h sofien usbien t1ien t0ien sioien wakeien p01ien p00ien r/w inten 0cah cpum1 cpum0 clkmd stphx r/w oscm 0cch wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 w wdtr 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh pc13 pc12 pc11 pc10 pc9 pc8 r/w pch 0d0h p04 p03 p02 p01 p00 r/w p0 0d1h p17 p16 p15 p14 p13 p12 p11 p10 r/w p1 0d2h p25 p24 p23 p22 p21 p10 r/w p2 0d5h p54 p53 p52 p51 p50 r/w p5 0d8h t0enb t0rate2 t0rate1 t0rate0 r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah t1enb t1rate2 t1rate1 t1rate0 r/w t1m 0dbh t1c7 t1c6 t1c5 t1c4 t1c3 t1c2 t1c1 t1c0 r/w t1c_l 0dch t1c15 t1c14 t1c13 t1c12 t1c11 t1c10 t1c9 t1c8 r/w t1c_h 0dfh gie stkpb2 stkpb1 stkpb0 r/w stkp 0e0h p03r p02r p01r p00r w p0ur 0e1h p17r p16r p15r p14r p13r p12r p11r p10r w p1ur 0e2h p25r p24r p23r p22r p21r p20r w p2ur
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 26 version 1.1 0e5h p54r p53r p52r p51r p50r w p5ur 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h s7pc13 s7pc12 s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h s6pc13 s6pc12 s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h s5pc13 s5pc12 s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h s4pc13 s4pc12 s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h s3pc13 s3pc12 s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh s2pc13 s2pc12 s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh s1pc13 s1pc12 s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh s0pc13 s0pc12 s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h ? note: 1. to avoid system error, please be sure to put all the ?0? and ?1? as it indicates in the above table . 2. all of register names had been declared in sn8asm assembler. 3. one-bit name had been declared in sn8asm assembler with ?f? prefix code. 4. ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instructi ons are only available to the ?r/w? registers. 5. for detail description, please refer to the ?system register quick reference table? .
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 27 version 1.1 2.1.4.4 accumulator the acc is an 8-bit data register responsible for trans ferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc can?t be acce ss by ?b0mov? instruction dur ing the instant addressing mode. ? example: read and write acc value. ; read acc data and store in buf data memory. mov buf, a ; write a immediate data into acc. mov a, #0fh ; write acc data from buf data memory. mov a, buf ; or b0mov a, buf the system doesn?t store acc and pfla g value when interrupt executed. a cc and pflag data must be saved to other data memories. ?push?, ?pop? save and load acc, pflag data into buffers. ? example: protect acc and working registers. int_service: push ; save acc and pflag to buffers. ? . ? pop ; load acc and pflag from buffers. reti ; exit interrupt service vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 28 version 1.1 2.1.4.5 program flag the pflag register contains the arithm etic status of alu operat ion, system reset status and lvd detecting status. nt0, npd bits indicate system reset status including po wer on reset, lvd reset, reset by external pin active and watchdog reset. c, dc, z bits indicate t he result status of alu operation. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd reset status 0 0 watch-dog time out 0 1 reserved 1 0 reset by lvd 1 1 reset by external reset pin bit 2 c: carry flag 1 = addition with carry, subtraction without borrowing, ro tation with shifting out logic ?1?, comparison result 0. 0 = addition without carry, s ubtraction with borrowing signal, rotation wi th shifting out logic ?0?, comparison result < 0. bit 1 dc: decimal carry flag 1 = addition with carry from low nibble, s ubtraction without borrow from high nibble. 0 = addition without carry from low nibble, subtraction with borrow from high nibble. bit 0 z: zero flag 1 = the result of an arithmetic/logic/branch operation is zero. 0 = the result of an arithmetic/logic/branch operation is not zero. ? note: refer to instruction set table for detailed information of c, dc and z flags.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 29 version 1.1 2.1.4.6 program counter the program counter (pc) is a 14-bit binary counter sepa rated into the high-byte 6 and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by execut ing call or jmp instruction. when jmp or call instruction is executed, the desti nation address will be inserted to bit 0 ~ bit 13. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl ) one address skipping there are nine instructions (cmprs, incs, incms, de cs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. ? ? c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. ? ? c1step: nop if the acc is equal to the immediat e data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step. ? ? c0step: nop
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 30 version 1.1 if the destination increased by 1, wh ich results overflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop if the destination decreased by 1, which results underflo w of 0x00 to 0xff, the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 31 version 1.1 ) multi-address jumping users can jump around the mult i-address by either jmp inst ruction or add m, a instruction (m = pcl) to activate multi-address jumping function. program counter supports ?add m,a? , ?adc m,a? and ?b0add m,a? instructions for carry to pch when pcl overflow automatically. for jump t able or others applications, users can calculate pc value by the three instructions and don?t care pcl overflow problem. ? note: pch only support pc up counting result and doesn?t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl?acc, pch keeps value and not change. ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ? ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to address 0300h ? ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + ac c, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point ? ?
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 32 version 1.1 2.1.4.7 y, z registers the y and z registers are the 8-bit buffers. there ar e three major functions of these registers. z can be used as general working registers z can be used as ram data pointers with @yz register z can be used as rom data pointer with the movc instruction for look-up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z ? 1, if z= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memory area of bank 0 ?
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 33 version 1.1 2.1.4.8 r registers r register is an 8-bit buffer. there ar e two major functions of the register. z can be used as working register z for store high-byte data of look-up table (movc instruction executed, the high- byte data of specified rom address will be stored in r register and the low-byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - ? note: please refer to the ?look-up table description? about r regi ster look-up table application.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 34 version 1.1 2.2 addressing mode 2.2.1 immediate addressing mode the immediate addressing mode uses an immediate data to set up the location in acc or specific ram. ? example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into acc. ? example: move the immediate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. ? note: in immediate addressing mode application, th e specific ram must be 0x80~0x87 working register. 2.2.2 directly addressing mode the directly addressing mode moves the cont ent of ram location in or out of acc. ? example: move 0x12 ram location data into acc. b0mov a, 12h ; to get a content of ram location 0x12 of bank 0 and save in acc. ? example: move acc data into 0x12 ram location. b0mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. 2.2.3 indirectly addressing mode the indirectly addressing mode is to access the memory by the data pointer registers (y/z). ? example: indirectly addressing mode with @yz register. b0mov y, #0 ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 35 version 1.1 2.3 stack operation 2.3.1 overview the stack buffer has 8-level. these buffers are designed to push and pop up program counter?s (pc) data when interrupt service routine and ?call? inst ruction are executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack buffer. the stknh and stknl are the stack buffers to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 36 version 1.1 2.3.2 stack registers the stack pointer (stkp) is a 3-bit register to store t he address used to access the st ack buffer, 14-bit data memory (stknh and stknl) set aside for temp orary storage of stack addresses. the two stack operations are writing to the top of the stac k (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always point to the top address of stack buffer and wr ite the last program counter val ue (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction ex ecuted or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in t he system register area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit[2:0] stkpbn: stack pointer (n = 0 ~ 2) bit 7 gie: global interrupt control bit. 0 = disable. 1 = enable. please refer to the interrupt chapter. ? example: stack pointer (stkp) reset, we strongl y recommended to clear the stack pointers in the beginning of the program. mov a, #00000111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - snpc13 snpc12 snpc11 snpc10 snpc9 snpc8 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 37 version 1.1 2.3.3 stack operation example the two kinds of stack-save operations re fer to the stack pointer (stkp) and writ e the content of program counter (pc) to the stack buffer are call instructi on and interrupt service. under each conditi on, the stkp decreases and points to the next available stack location. the stack buffer stor es the program counter about the op-code address. the stack-save operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - 5 0 1 0 stk4h stk4l - 6 0 0 1 stk5h stk5l - 7 0 0 0 stk6h stk6l - 8 1 1 1 stk7h stk7l - > 8 1 1 0 - - stack over, error there are stack-restore operations correspond to each push operation to restore the prog ram counter (pc). the reti instruction uses for interrupt service routine. the ret inst ruction is for call instruction. when a pop operation occurs, the stkp is incremented and points to the next free stack loca tion. the stack buffer restores the last program counter (pc) to the program counter registers. the stac k-restore operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 8 1 1 1 stk7h stk7l - 7 0 0 0 stk6h stk6l - 6 0 0 1 stk5h stk5l - 5 0 1 0 stk4h stk4l - 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free -
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 38 version 1.1 3 reset 3.1 overview the system would be reset in three conditions as following. z power on reset z watchdog reset z brown out reset z external reset (only supports external reset pin enable situation) when any reset condition occurs, all syst em registers keep initial status, progra m stops and program counter is cleared. after reset status released, the system boots up and progra m starts to execute from org 0. the nt0, npd flags indicate system reset status. the system can depend on nt0, npd status and go to diffe rent paths by program. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd condition description 0 0 watchdog reset watchdog timer overflow. 0 1 reserved - 1 0 power on reset and lvd reset. power voltage is lower than lvd detecting level. 1 1 external reset external reset pin detect low level status. finishing any reset sequence needs some time. the system provides complete procedures to make the power on reset successful. for different oscillat or types, the reset time is different. that causes the vdd rise rate and start-up time of different oscillator is not fixed. rc ty pe oscillator?s start-up time is very shor t, but the crystal type is longer. under clie nt terminal application, users have to take care the power on reset time for the master terminal requirement. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 39 version 1.1 3.2 power on reset the power on reset depend no lvd operation for most power- up situations. the power supplying to system is a rising curve and needs some time to achieve the normal voltage. power on reset sequence is as following. z power-up: system detects the power voltage up and waits for power stable. z external reset (only external reset pin enable): system checks external reset pin status. if external reset pin is not high level, the system keeps reset stat us and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal condition, system works well and clears watchdog timer by program. under error condition, system is in unknown situation and watchdog can?t be clear by program before watchdog timer overflow. watchdog timer overflow occurs and the system is reset. after watchdog reset, the system restarts and returns normal mode. watchdog reset sequence is as following. z watchdog timer status: system checks watchdog timer overflow stat us. if watchdog timer ov erflow occurs, the system is reset. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? note: please refer to the ?watchdog timer? about watchdog timer detail information.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 40 version 1.1 3.4 brown out reset 3.4.1 brown out description the brown out reset is a power dropping condition. the powe r drops from normal voltage to low voltage by external factors (e.g. eft interference or extern al loading changed). the brown out reset would make the system not work well or executing program error. vdd vss v1 v2 v3 system work well area system work error area brown out reset diagram the power dropping might through the voltage range that ?s the system dead-band. the dead-band means the power range can?t offer the system minimum operation power re quirement. the above diagram is a typical brown out reset diagram. there is a serious noise under the vdd, and vdd voltage drops very deep. there is a dotted line to separate the system working area. the above area is the system work well area. the below area is the system work error area called dead-band. v1 doesn?t touch the below area and not effe ct the system operation. but the v2 and v3 is under the below area and may induce the system error occurrence. let system under dead-band includes some conditions. dc application: the power source of dc application is usually using battery . when low battery condition and mcu drive any loading, the power drops and keeps in dead-band. under the situat ion, the power won?t drop dee per and not touch the system reset voltage. that makes the system under dead-band. ac application: in ac power application, the dc power is regulated from ac power source. this kind of power usually couples with ac noise that makes the dc power dirty. or the external loading is very heavy, e. g. driving motor. the loading operating induces noise and overlaps with the dc power. vdd drop s by the noise, and the system works under unstable power situation. the power on duration and power down duration are longer in ac application. the system power on sequence protects the power on successful, but the power do wn situation is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead-band for a while.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 41 version 1.1 3.4.2 the system operat ing voltage decsription to improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. differe nt system executing rates have differe nt system minimum operating voltage. the electrical characteristic section shows the system voltage to executing rate relationship. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area normally the system operation voltage ar ea is higher than the system reset voltage to vdd, and the reset voltage is decided by lvd detect level. the system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. the dead-band definition is the system minimum operat ing voltage above the system reset voltage.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 42 version 1.1 3.4.3 brown out reset improvement how to improve the brown reset condition? there are some methods to improve brown out reset as following. z lvd reset z watchdog reset z reduce the system executing rate z external reset circuit. (zener diode reset circuit, voltage bias reset circuit, external reset ic) ? note: 1. the ? zener diode reset circuit?, ?volta g e bias reset circuit? and ?external reset ic? can completely improve the brown out reset, dc low battery and ac slow power down conditions. 2. for ac power application and enhance eft performance, the s y stem clock is 4mhz/4 ( 1 mips ) and use external reset (? zener diode reset circui t?, ?voltage bias reset circuit?, ?external reset ic?). the structure can improve noise effective and get good eft characteristic. lvd reset: vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset. the lvd (low voltage detector) is built-in sonix 8-bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be triggered, an d the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of volt age and not easy to cover all dead-band range. using lvd to improve brown out reset is depend on application requiremen t and environment. if the power variation is very deep, violent and trigger the lvd, the lvd ca n be the protection. if the power variation can touch the lvd detect level and make system work error, the lvd can? t be the protection and need to other reset methods. more detail lvd information is in the electrical characteristic section. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog timer in several addresses. the system executes normally and the watchdog won?t reset system. when the system is under dea d-band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously counti ng until overflow occurrence. the overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is still in dead-band, the system reset sequence won?t be successful and the system stays in reset status until the power return to normal range. reduce the system executing rate: if the system rate is fast and the dead-band exists, to redu ce the system executing rate can improve the dead-band. the lower system rate is with lower minimum operating voltage. select the power voltage that?s no dead-band issue and find out the mapping system rate. adjust the system ra te to the value and the syst em exits the dead-band issue. this way needs to modify whole program timing to fit the application requirement. external reset circuit: the external reset methods also can improve brown out rese t and is the complete solution. there are three external reset circuits to improve brown out reset including ?zener di ode reset circuit?, ?voltage bias reset circuit? and ?external reset ic?. these three reset structures use external rese t signal and control to make sure the mcu be reset under power dropping and under dead-band. the external rese t information is described in the next section.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 43 version 1.1 3.5 external reset external reset function is controlled by ?reset_pin? c ode option. set the code option as ?reset? option to enable external reset function. external reset pin is schmitt trigge r structure and low level active. the system is running when reset pin is high level voltage input. the reset pin receives the low voltage and the system is reset. the external reset operation actives in power on and normal running mode. duri ng system power-up, the external reset pin must be high level input, or the system keeps in reset stat us. external reset sequence is as following. z external reset (only external reset pin enable): system checks external reset pin status. if external reset pin is not high level, the system keeps reset stat us and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in ac power application? 3.6 external reset circuit 3.6.1 simply rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow rising signal into reset pin as power up. the reset signal is slower than vdd power up timing, and system occurs a power on signal from the timing difference. ? note: the reset circuit is no any protection against unusual power or brown out reset.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 44 version 1.1 3.6.2 diode & rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm this is the better reset circuit. the r1 and c1 circuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against unusual po wer. the diode offers a power positive path to conduct higher power to vdd. it is can make reset pin voltage le vel to synchronize with v dd voltage. the structure can improve slight brown out reset condition. ? note: the r2 100 ohm resistor of ?simpl y reset circuit? and ?diode & rc reset circuit? is necessar y to limit an y current flowin g into reset pin from external capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or electrical over-stress (eos). 3.6.3 zener diode reset circuit mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b the zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vdd vo ltage level is above ?vz + 0. 7v?, the c terminal of the pnp transistor outputs high voltage and mcu operates normal ly. when vdd is below ?vz + 0.7v?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by zener specification. select the right zene r voltage to conform the application.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 45 version 1.1 3.6.4 voltage bias reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b the voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diode reset ci rcuit. use r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to ?0.7v x (r1 + r2) / r1?, the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below ?0.7v x (r 1 + r2) / r1?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistances. select the right r1, r2 value to conform the application. in the circuit diagram condition, the mcu?s reset pin level varies with vdd voltage variation, and the differential voltage is 0.7v. if the vdd drops and the voltage lower than reset pin det ect level, the system would be reset. if want to make the reset active earlier, set the r2 > r1 and the cap between vd d and c terminal voltage is larger than 0.7v. the external reset circuit is with a stable current through r1 and r2 . for power consumption issue application, e.g. dc power system, the current must be considered to whole system power consumption. ? note: under unstable power condition as brown out re set, ?zener diode rest circuit? and ?volta g e bias reset circuit? can protects s y stem no an y error occurrence as power droppin g . when power drops below the reset detect volta g e, the s y stem reset would be tri gg ered, and then s y stem executes reset sequence. that makes sure the system work well under unstable power situation. 3.6.5 external reset ic mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf the external reset circuit also use external reset ic to enhance mcu reset performance. this is a high cost and good effect solution. by different application and system require ment to select suitable reset ic. the reset circuit can improve all power variation
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 46 version 1.1 4 system clock 4.1 overview the micro-controller is a dual clock sy stem. there are high-speed clock and low-speed clock. the high-speed clock is generated from the external oscillator & on-chip pll circui t. the low-speed clock is generated from on-chip low-speed rc oscillator circuit (ilrc 24 khz). both the high-speed clock and the low-sp eed clock can be system clock (fosc). the system clock in slow mode is divided by 4 to be the instruction cycle (fcpu). ) normal mode (high clock): fcpu = fhosc / n , n = 1 ~ 4, select n by fcpu code option. ) slow mode (low clock): fcpu = flosc/4. sonix provides a ?noise filter? controlled by code option. in high noisy sit uation, the noise filter can isolate noise outside and protect system works well. the mi nimum fcpu of high clock is limited at fhosc/4 when noise filter enable. 4.2 clock block diagram fhosc. fcpu = fhosc/1 ~ fhosc/4, noise filter disable. fcpu = fhosc/4, noise filter enable. flosc. fcpu = flosc/4 cpum[1:0] xin xout stphx hosc fcpu code option fosc fosc clkmd fcpu z hosc: high_clk code option. z fhosc: external high-speed clock. z flosc: internal low-speed rc clock (typical 24 khz). z fosc: system clock source. z fcpu: instruction cycle.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 47 version 1.1 4.3 oscm register the oscm register is an oscillator control regi ster. it controls oscillator status, system mode. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm - - - cpum1 cpum0 clkmd stphx - read/write - - - r/w r/w r/w r/w - after reset - - - 0 0 0 0 - bit 1 stphx: external high-speed os cillator control bit. 0 = external high-speed oscillator free run. 1 = external high-speed oscillator free run stop. internal low-speed rc oscillator is still running. bit 2 clkmd: system high/low clock mode control bit. 0 = normal (dual) mode. syst em clock is high clock. 1 = slow mode. system clock is internal low clock. bit[4:3] cpum[1:0]: cpu operating mode control bits. 00 = normal. 01 = sleep (power down) mode. 10 = green mode. 11 = reserved. ? example: stop high-speed o scillator and pll circuit. b0bset fstphx ; to stop exter nal high-speed oscillator only. example: when entering the power down mode (sleep mo de), both high-speed extern al oscillator, pll circuit and internal low-speed o scillator will be stopped. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode).
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 48 version 1.1 4.4 system high clock the system high clock is from the in circ uit pll. user must select the external oscillator 6mhz x?tal, 12mhz x?tal or 16mhz x?tal by the code option ?ext_osc?, and the entire thr ee clock source will input to the on-chip pll circuit. pll will output 12mhz to sy stem clock (fosc). 4.4.1 external high clock external high clock includes three modules (crystal and exte rnal clock signal). the start up time of crystal and ceramic oscillator is different. the oscillator st art-up time decides reset time length.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 49 version 1.1 4.4.1.1 crystal crystal devices are driven by xin, xout pins. mcu vcc gnd c 20pf xin x o u t vdd vss c 20pf crystal ? note: connect the crystal and c as near as possible to the xin/xout/vss pins of micro-controller.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 50 version 1.1 4.1.1.2 external clock signal selecting external clock signal input to be the input clock source is by the ?ext _osc? code option. the external clock signal is input from xin pin. xout pin is general purpose i/o pin. mcu vcc gnd vss vdd xin xout external clock input ? note: the gnd of exte rnal oscillator circuit must be as near as possible to vss pin of micro-controller.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 51 version 1.1 4.2 system low clock the system low clock source is the internal low-speed oscill ator built in the micro-contro ller. the low-sp eed oscillator uses rc type oscillator circuit. the frequency is affect ed by the voltage and temperature of the system. in common condition, the frequency of the rc oscillator is about 24khz. the internal low rc supports watchdog clock source and system slow mode controlled by clkmd. ) flosc = internal low rc oscillator (24khz). ) slow mode fcpu = flosc / 4 there are two conditions to stop internal low rc. one is power down mode, and the other is green mode of 24k mode and watchdog disable. if system is in 24k mode and watchdog disable, only 24k oscillator actives and system is under low power consumption. ? example: stop internal low-speed oscillator by power down mode. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode). ? note: the internal low-speed clock can?t be turned off individually. it is controlled by cpum0, cpum1 (24k, watchdog disable) bits of oscm register. 4.2.1 system clock measurement under design period, the users can meas ure system clock speed by software instruction cycle (fcpu). this way is useful in rc mode. example: fcpu instruction cycl e of external oscillator. b0bset p0m.0 ; set p0.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p0.0 ; output fcpu toggle signal in low-sp eed clock mode. b0bclr p0.0 ; measure the fcpu frequency by oscilloscope. jmp @b ? note: do not measure the rc frequency directly from xin; the probe impendence will affect the rc frequency.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 52 version 1.1 5 system operation mode 5.1 overview the chip is featured with low power consumption by switching around four different modes as following. z high-speed mode z low-speed mode z power-down mode (sleep mode) z green mode power down mode (sleep mode) slow mode green mode normal mode clkmd = 1 clkmd = 0 p0, p1 wake-up function active. usb bus. external reset circuit active. cpum1, cpum0 = 01. cpum1, cpum0 = 10. p0, p1 wake-up function active. t0 timer time out. usb bus. external reset circuit active. p0, p1 wake-up function active. t0 timer time out. usb bus. external reset circuit active. system mode switching diagram operating mode description mode normal slow green power down (sleep) remark ehosc running by stphx by stphx stop ilrc running running running stop cpu instruction executi ng executing stop stop t0 timer *active *active *active inactive * active if t0enb=1 t1 timer *active *active inactive inactive * active if t1enb=1 tc0 timer *active *active inactive inactive * active if tc0enb=1 tc1 timer *active *active inactive inactive * active if tc1enb=1 usb running inactive inactive inactive * active if usbe=1 watchdog timer by watch_dog code option by watch_dog code option by watch_dog code option by watch_dog code option refer to code option description internal interrupt all active all active t0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, t0, reset p0, p1, reset z ehosc: external high clock (external x?tal) z ilrc: internal low clock (24khz rc oscillator)
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 53 version 1.1 5.2 system mode switching example ? example: switch normal/slow mode to power down (sleep) mode. b0bset fcpum0 ; set cpum0 = 1. ? note: during the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. ? example: switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high -speed oscillator for power saving. ? example: switch slow mode to normal mode ( the external high-speed oscillator is still running). b0bclr fclkmd ;to set clkmd = 0 example: switch slow mode to normal mode (the external high-speed oscillator stops). if external high clock stop and program want to switch back normal mode. it is necessary to delay at least 10ms for external clock stable. b0bclr fstphx ; turn on the external high-speed oscillator. mov a, #20 ; internal rc=24khz (typical) will delay b0mov z, a @@: decms z ; 0.33ms x 30 ~ 10ms for external clock stable jmp @b ; b0bclr fclkmd ; change the system back to the normal mode example: switch normal/slow mode to green mode. b0bset fcpum1 ; set cpum1 = 1. ? note: if t0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 54 version 1.1 example: switch normal/slow mode to green mode and enable t0 wake-up function. ; set t0 timer wakeup function. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial val ue = 74h (to set t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer ; go into green mode b0bclr fcpum0 ;to set cpumx = 10 b0bset fcpum1 ? note: during the green mode with t0 wake-up function, the wakeup pin and t0 wakeup the system back to the last mode. t0 wake-up period is controlled by program.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 55 version 1.1 5.3 wakeup 5.3.1 overview under power down mode (sleep mode) or green mode, progra m doesn?t execute. the wakeup trigger can wake the system up to normal mode or slow mode. the wakeup tri gger sources are external trigger (p0, p1 level change), internal trigger (t0 timer overflow) and usb bus toggle. z power down mode is waked up to normal mode. the wakeup trigger is only external trigger (p0, p1 level change and usb bus toggle) z green mode is waked up to last mode (normal mode or slow mode). the wakeup triggers are external trigger (p0, p1 level change), internal trigger (t0 timer overflow) and usb bus toggle. 5.3.2 wakeup time when the system is in power down mo de (sleep mode), the high clock oscilla tor stops. when wake d up from power down mode, mcu waits for 16384 external 6mhz clocks as t he wakeup time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. ? note: wakeup from green mode is no wakeup time because the clock doesn?t stop in green mode. the value of the wakeup time is as the following. ?16m_x?tal/12m_x?tal/6m_x?tal? mode: the wakeup time = 1/fosc * 16384 (sec) + high clock start-up time ? note: the high clock start-u p time is depended on the vdd a nd oscillator type of high clock. example: in 16m_x?tal/12m_x?tal/6m_x?tal mode and powe r down mode (sleep mode), the system is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/6mhz * 16384 = 2.72 ms the total wakeup time = 2.72 ms + oscillator start-up time
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 56 version 1.1 6 interrupt 6.1 overview this mcu provides 9 interrupt sources, including 6 inte rnal interrupt (t0/t1/tc0/tc1/usb/sio) and two external interrupt (int0/int1). the external inte rrupt can wakeup the chip while the syst em is switched from power down mode to high-speed normal mode. once interrupt service is executed, the gie bit in stkp register will clear to ?0? for stopping other interrupt request. on the contrast, when interrupt service exits, the gie bit will set to ?1? to accept the next interrupts? request. all of the interrupt r equest signals are stored in intrq register. inten interrupt enable register interrupt enabl e gating intr q 2- bit latchs p00ir q t0irq interrupt vector address (0008h) global interrupt request signal int0 trigger t0 time out t1 time out usb process end sio transmit ready t1irq usbir q sioirq i/o pin wakeup trigger wakeir q p01ir q int1 trigger tc0 time out tc1 time out tc0irq tc1irq ? note: the gie bit must enable during all interrupt operation.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 57 version 1.1 6.2 inten interrupt enable register inten is the interrupt request control register including one internal interrupts, one exte rnal interrupts enable control bits. one of the register to be set ?1? is to enable the interrupt request function. once of the interrupt occur, the stack is incremented and program jump to org 8 to execute interrupt service routines. t he program exits the interrupt service routine when the returning interrupt service routine instruction (reti) is executed. 0c7h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten1 tc1ien tc0ien read/write r/w r/w after reset 0 0 bit 0 tc0ien: tc0 timer interrupt control bit. 0 = disable tc0 interrupt function. 1 = enable tc0 interrupt function. bit 1 tc1ien: tc1 timer interrupt control bit. 0 = disable tc1 interrupt function. 1 = enable tc1 interrupt function. 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten sofien usbien t1ien t0ien si oien wakeien p01ien p00ien read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = disable int0 interrupt function. 1 = enable int0 interrupt function. bit 1 p01ien: external p0.1 interrupt (int1) control bit. 0 = disable int1 interrupt function. 1 = enable int1 interrupt function. bit 2 wakeien: i/o port0 & port 1 wakeup interrupt control bit. 0 = disable wakeup interrupt function. 1 = enable wakeup interrupt function. bit 3 sioien: sio interrupt control bit. 0 = disable sio interrupt function. 1 = enable sio interrupt function. bit 4 t0ien: t0 timer interrupt control bit. 0 = disable t0 interrupt function. 1 = enable t0 interrupt function. bit 5 t1ien: t1 timer interrupt control bit. 0 = disable t1 interrupt function. 1 = enable t1 interrupt function. bit 6 usbien: usb interrupt control bit. 0 = disable usb interrupt function. 1 = enable usb interrupt function. bit 7 sofien: usb sof interrupt control bit. control this so f interrupt with the usb_int_en register. 0 = disable usb sof interrupt function. 1 = enable usb sof interrupt function.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 58 version 1.1 6.3 intrq interrupt request register intrq is the interrupt request flag register. the register incl udes all interrupt request indication flags. each one of the interrupt requests occurs; the bit of the intrq register would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vect or of program, users know the any interrupt requests occurring by the register and do the routi ne corresponding of the interrupt request. 0c6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq1 tc1irq tc0irq read/write r/w r/w after reset 0 0 bit 0 tc0irq: tc0 timer interrupt request flag. 0 = none tc0 interrupt request. 1 = t0 interrupt request. bit 1 tc1irq: tc1 timer interrupt request flag. 0 = none tc1 interrupt request. 1 = t0 interrupt request. 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq sofirq usbirq t1irq t0irq si oirq wakeirq p01irq p00irq read/write rw r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 p00irq: external p0.0 interrupt (int0) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. bit 1 p01irq: external p0.1 interrupt (int1) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. bit 2 wakeirq: i/o port0 & port1 wakeup interrupt request flag. 0 = none wakeup interrupt request. 1 = wakeup interrupt request. bit 3 sioirq: sio interrupt request flag. 0 = none sio interrupt request. 1 = sio interrupt request. bit 4 t0irq: t0 timer interrupt request flag. 0 = none t0 interrupt request. 1 = t0 interrupt request. bit 5 t1irq: t1 timer interrupt request flag. 0 = none t1 interrupt request. 1 = t1 interrupt request. bit 6 usbirq: usb interrupt request flag. 0 = none usb interrupt request. 1 = usb interrupt request. bit 7 sofirq: usb sof interrupt request flag. control this sof interrupt with the ustatus register. 0 = none usb sof interrupt request. 1 = usb sof interrupt request.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 59 version 1.1 6.4 gie global interrupt operation gie is the global interrupt control bit. all interrupts start wo rk after the gie = 1 it is necessary for interrupt service request. one of the interrupt requests occurs, and the program co unter (pc) points to the interrupt vector (org 8) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable global interrupt. 1 = enable global interrupt. example: set global interrupt control bit (gie). b0bset fgie ; enable gie ? note: the gie bit must enable during all interrupt operation. 6.5 push, pop routine when any interrupt occurs, system will jump to org 8 and ex ecute interrupt service routine. it is necessary to save acc, pflag data. the chip includes ?pus h?, ?pop? for in/out interrupt service r outine. the two instructions save and load acc , pflag data into buffers and avoid main routine erro r after interrupt service routine finishing. ? note: ?push?, ?pop? instructions save and load a cc/pflag without (nt0, npd). push/pop buffer is an unique buffer and only one level. ? example: store acc and paflg data by push, po p instructions when interrupt service routine executed. org 0 jmp start org 8 jmp int_service org 10h start: ? int_service: push ; save acc and pflag to buffers. ? ? pop ; load acc and pflag from buffers. reti ; exit interrupt service vector ? endp
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 60 version 1.1 6.6 int0 (p0.0) & int1 (p0.1) interrupt operation when the int0/int1 trigger oc curs, the p00irq/p01irq will be set to ?1? no matter the p00ien/p01ien is enable or disable. if the p00ien/p01ien = 1 and the trigger event p00irq/p01irq is also set to be ?1?. as the result, the system will execute the interrupt vector (org 8). if the p00ien/p01ien = 0 and the trigger event p00irq/p01irq is still set to be ?1?. moreover, t he system won?t execute interrupt vector even when the p00irq/p01irq is set to be ?1?. users need to be cautious with the opera tion under multi-interrupt situation. if the interrupt trigger direction is identical with wake-u p trigger direction, the int0/int1 interrupt request flag (int0irq/int1irq) is latched while system wake-up from power down mode or green mode by p0.0 wake-up trigger. system inserts to interrupt vector (org 8) after wake-up immediately. ? note: int0 interrupt request can be latched by p0.0 wake-up trigger. ? note: int1 interrupt request can be latched by p0.1 wake-up trigger. ? note: the interrupt trigger direction of p0.0/p0.1 is control by pedge register. 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge p01g1 p01g0 p00g1 p00g0 read/write r/w r/w r/w r/w after reset 1 0 1 0 bit[1:0] p00g[1:0]: p0.0 interrupt trigger edge control bits. 00 = reserved. 01 = rising edge. 10 = falling edge. 11 = rising/falling bi-direction (level change trigger). bit[3:2] p01g[1:0]: p0.1 interrupt trigger edge control bits. 00 = reserved. 01 = rising edge. 10 = falling edge. 11 = rising/falling bi-direction (level change trigger). example: setup int0 interrupt request and bi-direction edge trigger. mov a, #18h b0mov pedge, a ; set int0 interr upt trigger as bi-direction edge. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 61 version 1.1 example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq ? ; int0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 62 version 1.1 6.7 t0 interrupt operation when the t0c counter occurs overflow, the t0irq will be se t to ?1? however the t0ien is enable or disable. if the t0ien = 1, the trigger event will make the t0irq to be ?1? a nd the system enter interrupt ve ctor. if the t0ien = 0, the trigger event will make the t0irq to be ?1? but the system will not enter interr upt vector. users need to care for the operation under multi-interrupt situation. ? example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m, a ; set t0 clock = fcpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. ? ; t0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 63 version 1.1 6.8 t1 interrupt operation when the t1c counter overflows, the t1irq will be set to ?1? no matter the t1ien is enable or disable. if the t1ien and the trigger event t1irq is set to be ?1?. as the result, the system will execute the inte rrupt vector. if the t1ien = 0, the trigger event t1irq is still set to be ?1?. moreover, the system won? t execute interrupt vector even when the t1ien is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation. ? example: t1 interrupt request setup. b0bclr ft1ien ; disable t1 interrupt service b0bclr ft1enb ; disable t1 timer mov a, #00h ; b0mov t1m, a ; set t1 clock = fcpu / 256 mov a, #0e5h ; set t1c_l initial value = e5h b0mov t1c_l, a mov a, #48h ; set t1c_h initial value = 48h b0mov t1c_h, a ; set t1 interval = 1s b0bset ft1ien ; enable t1 interrupt service b0bclr ft1irq ; clear t1 interrupt request flag b0bset ft1enb ; enable t1 timer b0bset fgie ; enable gie example: t1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ft1irq ; check t1irq jmp exit_int ; t1irq = 0, exit interrupt vector b0bclr ft1irq ; reset t1irq mov a, #0e5h b0mov t1c_l, a ; reset t1c_l. mov a, #48h b0mov t1c_h, a ; reset t1c_h. ? ; t1 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 64 version 1.1 6.9 tc0 interrupt operation when the tc0c counter overflows, the tc0irq will be set to ?1? no matter the tc0ien is enable or disable. if the tc0ien and the trigger event tc0irq is set to be ?1?. as t he result, the system will execute the interrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set to be ?1?. moreover, the system won?t execute interrupt vector even when the tc0ien is set to be ?1?. users need to be cautio us with the operation under multi-interrupt situation. ? example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie ? example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. ? ; tc0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 65 version 1.1 6.10 tc1 interrupt operation when the tc1c counter overflows, the tc1irq will be set to ?1? no matter the tc1ien is enable or disable. if the tc1ien and the trigger event tc1irq is set to be ?1?. as t he result, the system will execute the interrupt vector. if the tc1ien = 0, the trigger event tc1irq is still set to be ?1?. moreover, the system won?t execute interrupt vector even when the tc1ien is set to be ?1?. users need to be cautio us with the operation under multi-interrupt situation. ? example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ftc1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = fcpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie ? example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. ? ; tc1 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 66 version 1.1 6.11 usb interrupt operation when the usb process finished, the usbirq will be set to ?1? no matter the usbien is enable or disable. if the usbien and the trigger event usbirq is set to be ?1?. as the result, the system will exec ute the interrupt vector. if the usbien = 0, the trigger event usbirq is still set to be ?1?. moreover, the system won?t execute interrupt vector. users need to be cautious with the opera tion under multi-interrupt situation. ? example: usb interrupt request setup. b0bclr fusbien ; disable usb interrupt service b0bclr fusbirq ; clear usb interrupt request flag b0bset fusbien ; enable usb interrupt service ? ; usb initializes. ? ; usb operation. b0bset fgie ; enable gie example: usb interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: push ; push routine to save acc and pflag to buffers. b0bts1 fusbirq ; check usbirq jmp exit_int ; usbirq = 0, exit interrupt vector b0bclr fusbirq ; reset usbirq ? ; usb interrupt service routine ? exit_int: pop ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 67 version 1.1 6.12 wakeup interrupt operation when the i/o port 1 or i/o port 0 wakeup the mcu from the sleep mode, the wakeirq will be set to ?1? no matter the wakeien is enable or disable. if the w akeien and the trigger event wakeirq is set to be ?1?. as the result, the system will execute the interr upt vector. if the wakeien = 0, the trigger event wakeir q is still set to be ?1?. moreover, the system won?t execute inte rrupt vector. users need to be cautious with the operation under multi-interrupt situation. ? example: wake interrupt request setup. b0bclr fwakeien ; disable wake interrupt service b0bclr fwakeirq ; clear wake interrupt request flag b0bset fwakeien ; enable wake interrupt service ? ; pin wakeup initialize. ? ; pin wakeup operation. b0bset fgie ; enable gie example: wake interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: push ; push routine to save acc and pflag to buffers. b0bts1 fwakeirq ; check wakeirq jmp exit_int ; wakeirq = 0, exit interrupt vector b0bclr fwakeirq ; reset wakeirq ? ; wake interrupt service routine ? exit_int: pop ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 68 version 1.1 6.13 sio interrupt operation when the sio converting successfully, t he sioirq will be set to ?1? no matter t he sioien is enable or disable. if the sioien and the trigger event sioirq is set to be ?1?. as t he result, the system will execute the interrupt vector. if the sioien = 0, the trigger event sioirq is still set to be ?1?. moreover, t he system won?t execute interrupt vector even when the sioien is set to be ?1?. users need to be cauti ous with the operation under multi-interrupt situation. ? example: sio interrupt request setup. b0bset fsioien ; enable sio interrupt service b0bclr fsioirq ; clear sio interrupt request flag b0bset fgie ; enable gie ? example: sio interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 fsioirq ; check sioirq jmp exit_int ; sioirq = 0, exit interrupt vector b0bclr fsioirq ; reset sioirq ? ; sio interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 69 version 1.1 6.14 multi-interrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi-interrupt request requires setting the priority of the interrupt requests. the irq flags of interrupts are controlled by the interrupt event. nevertheless, the irq flag ?1? doesn?t mean the syst em will execute the interrupt vector. in addition, which means the irq flags can be set ?1? by the events without enable the interrupt. once the event occurs, the irq will be logic ?1?. the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge t0irq t0c overflow t1irq t1c overflow usbirq usb process finished waekirq i/o port0 & port1 wakeup mcu sioirq sio process finished for multi-interrupt conditions, two things need to be taking care of. one is to set the priority for these interrupt requests. two is using ien and irq flags to decide which interrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine. ? example: check the interrupt request under multi-interrupt operation org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intt0chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp intt1chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine intt1chk: ; check t1 interrupt request b0bts1 ft1ien ; check t1ien jmp inttc1chk ; jump check to next interrupt b0bts0 ft1irq ; check t1irq jmp intt1 ; jump to t1 interrupt service routine intusbchk: ; check usb interrupt request b0bts1 fusbien ; check usbien jmp intwakechk ; jump check to next interrupt b0bts0 fusbirq ; check usbirq jmp intusb ; jump to usb interrupt service routine intwakechk: ; check usb interrupt request b0bts1 fwakeien ; check wakeien jmp intsiochk ; jump check to next interrupt b0bts0 fwakeirq ; check wakeirq jmp intwakeup ; jump to wakeu p interrupt service routine intsiochk: ; check sio interrupt request b0bts1 fsioien ; check sioien jmp int_exit ; jump check to next interrupt b0bts0 fsioirq ; check sioirq jmp intsio ; jump to sio interrupt service routine int_exit: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 70 version 1.1 7 i/o port 7.1 i/o port mode the port direction is programmed by pnm register. a ll i/o ports can select input or output direction. 0b8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0m - - - - p03m p02m p01m p00m read/write - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m p17m p16m p15m p14m p13m p12m p11m p10m read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m - - p25m p24m p23m p22m p21m p20m read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m - - - p54m p53m p52m p51m p50m read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~3). 0 = pn is input mode. 1 = pn is output mode. ? note: 1. users can program them by bit c ontrol instructions (b0bset, b0bclr). 2. p0.4 is input only pin, so there is no p0.4 mode control bit. ? example: i/o mode selecting clr p0m ; set all ports to be input mode. clr p1m clr p5m mov a, #0ffh ; set all ports to be output mode. b0mov p0m, a b0mov p1m, a b0mov p5m, a b0bclr p1m.2 ; set p1.2 to be input mode. b0bset p1m.2 ; set p1.2 to be output mode.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 71 version 1.1 7.2 i/o pull up register 0e0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0ur - - - - p03r p02r p01r p00r read/write - - - - w w w w after reset - - - - 0 0 0 0 0e1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1ur p17r p16r p15r p16r p13r p12r p11r p10r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0e2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2ur - - p25r p24r p23r p22r p21r p20r read/write - - w w w w w w after reset - - 0 0 0 0 0 0 0e5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5ur - - - p54r p53r p52r p51r p50r read/write - - - w w w w w after reset - - - 0 0 0 0 0 ? note: p0.4 is input only pin with pull-up resister. ? example: i/o pull up register mov a, #0ffh ; enable port0, 1, 5 pull-up register, b0mov p0ur, a ; b0mov p1ur, a b0mov p5ur, a
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 72 version 1.1 7.3 i/o port data register 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - p04 p03 p02 p01 p00 read/write - - - r r/w r/w r/w r/w after reset - - - 0 0 0 0 0 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 - - p25 p24 p23 p22 p21 p20 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 - - - p54 p53 p52 p51 p50 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 ? note: the p0.4 keeps ?1? when external reset enable by code option. ? example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 1 b0mov a, p5 ; read data from port 5 ? example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p0, a b0mov p1, a b0mov p5, a ? example: write one bit data to output port. b0bset p1.3 ; set p1.3 and p5.3 to be ?1?. b0bset p5.3 b0bclr p1.3 ; set p1.3 and p5.3 to be ?0?. b0bclr p5.3
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 73 version 1.1 7.4 i/o port1 wakeup control register 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w p17w p16w p15w p14w p13w p12w p11w p10w read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] p1nw: port 1 wakeup function control bit. 0 = disable port 1 wakeup function. 1 = enable port 1 wakeup function.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 74 version 1.1 8 timers 8.1 watchdog timer the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program goes into the unknown status by noise interferen ce, wdt overflow signal raises and resets mcu. watchdog clock controlled by code option and the clock source is in ternal low-speed oscillator (24khz). watchdog overflow time = 8192 / inte rnal low-speed oscillator (sec). vdd internal low rc freq. watchdog overflow time 5v 24khz 341ms ? note: if watchdog is ?always_on? mode, it keeps running event under power down mode or green mode. watchdog clear is controlled by wdtr register. moving 0x5a data into wdtr is to reset watchdog timer. 0cch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdtr wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: mov a,#5ah ; clear the watchdog timer. b0mov wdtr,a ? call sub1 call sub2 ? ? ? jmp main
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 75 version 1.1 watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: ? ; check i/o. ? ; check ram err: jmp $ ; i/o or ram error. program jump here and don?t ; clear watchdog. wait watchdog timer overflow to reset ic. correct: ; i/o and ram are correct. clear watchdog timer and ; execute program. b0bset fwdrst ; only one clearing watchdog timer of whole program. ? call sub1 call sub2 ? ? ? jmp main
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 76 version 1.1 8.2 timer 0 (t0) 8.2.1 overview the t0 is an 8-bit binary up timer and event counter. if t0 ti mer occurs an overflow (from ffh to 00h), it will continue counting and issue a time-out signal to trigger t0 interrupt to request interrupt service. the main purpose of the t0 timer is as following. ) 8-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) green mode wakeup function: t0 can be green mode wake -up time as t0enb = 1. system will be wake-up by t0 time out. fcpu t0 rate (fcpu/2~fcpu/256) t0enb cpum0,1 t0c 8-bit binary up counting counter t0 time out load internal data bus 8.2.2 t0m mode register 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 - - - read/write r/w r/w r/w r/w - - - after reset 0 0 0 0 - - - bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 77 version 1.1 8.2.3 t0c counting register t0c is an 8-bit counter register for t0 interval time control. 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) example: to set 1ms interval time for t0 interrupt . high clock is 12mhz. fcpu=fosc/2. select t0rate=010 (fcpu/64). t0c initial value = 256 - (t0 interrupt interval time * input clock) = 256 - (1ms * 6mhz / 1 / 64) = 256 - (10 -3 * 6 * 10 6 / 1 / 64) = 162 = a2h the basic timer table interval time of t0. high speed mode (fcpu = 12mhz / 2) t0rate t0clock max overflow interval one step = max/256 000 fcpu/256 10.923 ms 42.67 us 001 fcpu/128 5.461 ms 21.33 us 010 fcpu/64 2.731 ms 10.67 us 011 fcpu/32 1.365 ms 5.33 us 100 fcpu/16 0.683 ms 2.67 us 101 fcpu/8 0.341 ms 1.33 us 110 fcpu/4 0.171 ms 0.67 us 111 fcpu/2 0.085 ms 0.33 us
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 78 version 1.1 8.2.4 t0 timer operation sequence t0 timer operation sequence of setup t0 timer is as following. ) stop t0 timer counting, disable t0 interrupt function and clear t0 interrupt request flag. b0bclr ft0enb ; t0 timer. b0bclr ft0ien ; t0 interrupt function is disabled. b0bclr ft0irq ; t0 interrupt request flag is cleared. ) set t0 timer rate. mov a, #0xxx0000b ;the t0 rate control bi ts exist in bit4~bit6 of t0m. the ; value is from x000xxxxb~x111xxxxb. b0mov t0m,a ; t0 timer is disabled. ) set t0 interrupt interval time. mov a,#7fh b0mov t0c,a ; set t0c value. ) set t0 timer function mode. b0bset ft0ien ; enable t0 interrupt function. ) enable t0 timer. b0bset ft0enb ; enable t0 timer.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 79 version 1.1 8.3 timer t1 (t1) 8.3.1 overview the t1 is an 16-bit binary up timer and event counter. if t1 timer occurs an overflow (from ffffh to 0000h), it will continue counting and issue a time-out signal to trig ger t1 interrupt to request interrupt service. the main purpose of the t1 timer is as following. ) 16-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) green mode wakeup function: t1 can be green mode wake -up time as t1enb = 1. system will be wake-up by t1 time out. fcpu t1 rate (fcpu/2~fcpu/256) t1enb cpum0,1 t1c 16-bit binary up counting counter t1 time out load internal data bus 8.3.2 t1m mode register 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1m t1enb t1rate2 t1rate1 t1rate0 - - - read/write r/w r/w r/w r/w - - - after reset 0 0 0 0 - - - bit [6:4] t1rate[2:0]: t1 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t1enb: t1 counter control bit. 0 = disable t1 timer. 1 = enable t1 timer.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 80 version 1.1 8.3.3 t1c counting register t1c_l with t1c_h is an 16-bit counter register for t1 interval time control. 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1c_l t1c7 t1c6 t1c5 t1c4 t1c3 t1c2 t1c1 t1c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1c_h t1c15 t1c14 t1c13 t1c12 t1c11 t1c10 t1c9 t1c8 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t1c initial value is as following. t1c initial value = 65536 - (t1 interrupt interval time * input clock) example: to set 1ms interval time for t1 interrupt . high clock is 12mhz. fcpu=fosc/2. select t1rate=001 (fcpu/128). t1c initial value = 65536 - (t1 interrupt interval time * input clock) = 65536 - (1s * 12mhz / 2 / 128) = 65536 - (10 * 6 * 10 6 / 1 / 128) = 18661 = 48e5h the basic timer table interval time of t1. high speed mode (fcpu = 12mhz / 2) t1rate t1clock max overflow interval one step = max/256 000 fcpu/256 2.796 s 42.67 us 001 fcpu/128 1.398 s 21.33 us 010 fcpu/64 699.051 ms 10.67 us 011 fcpu/32 349.525 ms 5.33 us 100 fcpu/16 174.763 ms 2.67 us 101 fcpu/8 87.381 ms 1.33 us 110 fcpu/4 43.691 ms 0.67 us 111 fcpu/2 21.845 ms 0.33 us
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 81 version 1.1 8.3.4 t1 timer operation sequence t1 timer operation sequence of setup t1 timer is as following. ) stop t1 timer counting, disable t1 interrupt function and clear t1 interrupt request flag. b0bclr ft1enb ; t1 timer. b0bclr ft1ien ; t1 interrupt function is disabled. b0bclr ft1irq ; t1 interrupt request flag is cleared. ) set t1 timer rate. mov a, #0xxx0000b ;the t1 rate control bi ts exist in bit4~bit6 of t1m. the ; value is from x000xxxxb~x111xxxxb. b0mov t1m,a ; t1 timer is disabled. ) set t1 interrupt interval time. mov a,#0e5h b0mov t1c_l,a ; set t1c_l value. mov a,#48h b0mov t1c_h,a ; set t1c_h value. ) set t1 timer function mode. b0bset ft1ien ; enable t1 interrupt function. ) enable t1 timer. b0bset ft1enb ; enable t1 timer.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 82 version 1.1 8.4 timer/counter 0 (tc0) 8.4.1 overview the tc0 is an 8-bit binary up counting timer with double buffers. tc0 has two clock sources including internal clock and external clock for counting a precision time. the internal cl ock source is from fcpu. the external clock is int0 from p0.0 pin (falling edge trigger). using tc0m register selects tc 0c?s clock source from internal or external. if tc0 timer occurs an overflow, it will continue counting and issue a time -out signal to trigger tc0 interrupt to request interrupt service. tc0 overflow time is 0xff to 0x00 normally. under pwm mode, tc0 overflow is decided by pwm cycle controlled by aload0 and tc0out bits. the main purposes of the tc0 timer is as following. ) 8-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) external event counter: counts system ?events? based on falling edge detection of external clock signals at the int0 input pin. ) buzzer output ) pwm output fcpu tc0 rate (fcpu/2~fcpu/256) int0 (schmitter trigger) tc0cks tc0enb cpum0,1 tc0c 8-bit binary up counting counter tc0r reload data buffer up counting reload value tc0 time out compare aload0 r s tc0 time out auto. reload tc0 / 2 buzzer internal p5.4 i/o circuit p5.4 pwm pwm0out tc0out aload0, tc0out load
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 83 version 1.1 8.4.2 tc0m mode register 088h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm0out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc0out, aload0 bits. bit 1 tc0out: tc0 time out toggle signal output control bit. only valid when pwm0out = 0. 0 = disable, p5.4 is i/o function. 1 = enable, p5.4 is output tc0out signal. bit 2 aload0: auto-reload control bit. only valid when pwm0out = 0. 0 = disable tc0 auto-reload function. 1 = enable tc0 auto-reload function. bit 3 tc0cks: tc0 clock source select bit. 0 = internal clock (fcpu or fosc). 1 = external clock from p0.0/int0 pin. bit [6:4] tc0rate[2:0]: tc0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 tc0enb: tc0 counter control bit. 0 = disable tc0 timer. 1 = enable tc0 timer. ? note: when tc0cks=1, tc0 became an external event counter and tc0rate is useless. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0).
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 84 version 1.1 8.4.3 tc0c counting register tc0c is an 8-bit counter register for tc0 interval time control. 089h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc0c initial value is as following. tc0c initial value = n - (tc0 interrupt interval time * input clock) n is tc0 overflow boundary number. tc0 timer overflow time has six types (tc0 timer, tc0 event counter, tc0 fcpu clock source, tc0 fosc clock source, pwm mode and no pw m mode). these parameters decide tc0 overflow time and valid value as follow table. tc0cks pwm0 aload0 tc0out n tc0c valid value tc0c value binary type remark 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b overflow per 32 count 0 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 1 - - - 256 0x00~0xff 00000000b~11111111b overflow per 256 count ? example: to set 1ms interval time for tc0 interr upt. tc0 clock source is fcpu (tc0ks=0) and no pwm output (pwm0=0). high clock is internal 6mhz . fcpu=fosc/1. select tc0rate=010 (fcpu/64). tc0c initial value = n - (tc0 interrupt interval time * input clock) = 256 - (1ms * 6mhz / 1 / 64) = 256 - (10 -3 * 6 * 10 6 / 1 / 64) = 162 = a2h the basic timer table interval time of tc0. high speed mode (fcpu = 6mhz / 1) tc0rate tc0clock max overflow interval one step = max/256 000 fcpu/256 10.923 ms 42.67 us 001 fcpu/128 5.461 ms 21.33 us 010 fcpu/64 2.731 ms 10.67 us 011 fcpu/32 1.365 ms 5.33 us 100 fcpu/16 0.683 ms 2.67 us 101 fcpu/8 0.341 ms 1.33 us 110 fcpu/4 0.171 ms 0.67 us 111 fcpu/2 0.085 ms 0.33 us
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 85 version 1.1 8.4.4 tc0r auto-load register tc0 timer is with auto-load function controlled by aload0 bit of tc0m. when tc0c overflow occurring, tc0r value will load to tc0c by system. it is easy to generate an ac curate time, and users don?t reset tc0c during interrupt service routine. tc0 is double buffer design. if new tc0r value is set by program, the new value is stored in 1 st buffer. until tc0 overflow occurs, the new value moves to real tc0r buffer. this way can avoid tc0 interval time error and glitch in pwm and buzzer output. ? note: under pwm mode, auto-load is enabled automatically. the aload0 bit is selecting overflow boundary. 08ah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc0r initial value is as following. tc0r initial value = n - (tc0 interrupt interval time * input clock) n is tc0 overflow boundary number. tc0 timer overflow time has six types (tc0 timer, tc0 event counter, tc0 fcpu clock source, tc0 fosc clock source, pwm mode and no pw m mode). these parameters decide tc0 overflow time and valid value as follow table. tc0cks pwm0 aload0 tc0out n tc0r valid value tc0r value binary type 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - 256 0x00~0xff 00000000b~11111111b ? example: to set 1ms interval time for tc0 interr upt. tc0 clock source is fcpu (tc0ks=0) and no pwm output (pwm0=0). high clock is internal 6mhz . fcpu=fosc/1. select tc0rate=010 (fcpu/64). tc0r initial value = n - (tc0 interrupt interval time * input clock) = 256 - (1ms * 6mhz / 1 / 64) = 256 - (10 -3 * 6 * 10 6 / 1 / 64) = 162 = a2h
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 86 version 1.1 8.4.5 tc0 clock freque ncy output (buzzer) buzzer output (tc0out) is from tc0 timer/counter frequen cy output function. by setting the tc0 clock frequency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-disable. the tc0out frequency is divided by 2 from tc0 interval time. tc0out frequency is 1/2 tc0 frequency. the tc0 clock has many combinations and easily to make difference frequency. the tc0out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc0 overflow clock tc0out (buzzer) output clock ? example: setup tc0out output from tc0 to tc0out (p5.4). the external high-speed clock is 4mhz. the tc0out frequency is 0.5khz. because the tc0out signal is divided by 2, set the tc0 clock to 1khz. the tc0 clock source is from external o scillator clock. t0c rate is fcpu/ 4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 131. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc0c,a b0mov tc0r,a b0bset ftc0out ; enable tc0 output to p5.4 and disable p5.4 i/o function b0bset faload1 ; enable tc0 auto-reload function b0bset ftc0enb ; enable tc0 timer ? note: buzzer output is enable, and ?pwm0out? must be ?0?.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 87 version 1.1 8.4.6 tc0 timer operation sequence tc0 timer operation includes timer interrupt, event counter , tc0out and pwm. the sequence of setup tc0 timer is as following. ) stop tc0 timer counting, disable tc0 interrupt function and clear tc0 interrupt request flag. ) b0bclr ftc0enb ; tc0 timer, tc0out and pwm stop. b0bclr ftc0ien ; tc0 inte rrupt function is disabled. b0bclr ftc0irq ; tc0 interrupt request flag is cleared. ) set tc0 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc0 rate control bi ts exist in bit4~bit6 of tc0m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc0m,a ; tc0 interr upt function is disabled. ) set tc0 timer clock source. ; select tc0 internal / external clock source. b0bclr ftc0cks ; select tc0 internal clock source. or b0bset ftc0cks ; select tc 0 external clock source. ) set tc0 timer auto-load mode. b0bclr faload0 ; enable tc0 auto reload function. or b0bset faload0 ; disable tc0 auto reload function. ) set tc0 interrupt interval time, tc0out (buzzer) frequency or pwm duty cycle. ; set tc0 interrupt interval time, tc 0out (buzzer) frequency or pwm duty. mov a,#7fh ; tc0c and tc0r value is decided by tc0 mode. b0mov tc0c,a ; set tc0c value. b0mov tc0r,a ; set tc0r value unde r auto reload mode or pwm mode. ; in pwm mode, set pwm cycle. b0bclr faload0 ; aload0, tc0out = 00, pwm cycle boundary is b0bclr ftc0out ; 0~255. or b0bclr faload0 ; aload0, tc0out = 01, pwm cycle boundary is b0bset ftc0out ; 0~63. or b0bset faload0 ; aload0, tc0out = 10, pwm cycle boundary is b0bclr ftc0out ; 0~31. or b0bset faload0 ; aload0, tc0out = 11, pwm cycle boundary is b0bset ftc0out ; 0~15. ) set tc0 timer function mode. b0bset ftc0ien ; enable tc0 interrupt function. or b0bset ftc0out ; enable tc 0out (buzzer) function. or b0bset fpwm0out ; enable pwm function. ) enable tc0 timer. b0bset ftc0enb ; enable tc0 timer.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 88 version 1.1 8.5 pwm0 mode 8.5.1 overview pwm function is generated by tc0 timer counter and output the pwm signal to pwm0out pin (p5.4). the 8-bit counter counts modulus 256, 64, 32, 16 controlled by aload0, tc0out bits. the value of the 8-bit counter (tc0c) is compared to the contents of the referenc e register (tc0r). when the reference register value (tc0r) is equal to the counter value (tc0c), the pwm output goes low. when the co unter reaches zero, the pwm output is forced high. the low-to-high ratio (duty) of the pw m0 output is tc0r/256, 64, 32, 16. pwm output can be held at low level by continuously loading the reference register with 00h. under pwm operating, to change the pwm?s duty cycle is to modify the tc0r. ? note: tc0 is double buffer design. modifying tc0r to change pwm duty by program, there is no glitch and error duty signal in pwm output waveform. users can change tc0r any time, and the new reload value is loaded to tc0r buffer at tc0 overflow. aload0 tc0out pwm duty range tc0c valid value tc0r valid bits value max. pwm frequency (fcpu = 6mhz) remark 0 0 0/256~255/256 0x00~0xff 0x00~0xff 11.719k overflow per 256 count 0 1 0/64~63/64 0x00~0x3f 0x00~0x3f 46.875k overflow per 64 count 1 0 0/32~31/32 0x00~0x1f 0x00~0x1f 93.75k overflow per 32 count 1 1 0/16~15/16 0x00~0x0f 0x00~0x0f 187.5k overflow per 16 count the output duty of pwm is with different tc0r. duty range is from 0/256~255/256. tc0 clock tc0r=00h tc0r=01h tc0r=80h tc0r=ffh 0 1 128 254 255 0 1 128 254 255 low low low high high low high
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 89 version 1.1 8.5.2 tcxirq and pwm duty in pwm mode, the frequency of tc0irq is depended on pwm duty range. from following diagram, the tc0irq frequency is related with pwm duty. tc0 overflow, tc0irq = 1 pwm0 output (duty range 0~15) 0xff tc0c value 0x00 pwm0 output (duty range 0~31) 0xff tc0c value 0x00 pwm0 output (duty range 0~63) 0xff tc0c value 0x00 0xff tc0c value 0x00 pwm0 output (duty range 0~255) tc0 overflow, tc0irq = 1 tc0 overflow, tc0irq = 1 tc0 overflow, tc0irq = 1
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 90 version 1.1 8.5.3 pwm duty with tcxr changing in pwm mode, the system will compare tc0c and tc0r all the time. when tc0c = tc0r pwm high > low tc0c < tc0r pwm low > high in period 2 and period 4, new duty (tc0r) is set. tc0 is double buffer de sign. the pwm still keeps the same duty in period 2 and period 4, and the new duty is changed in ne xt period. by the way, sy stem can avoid the pwm not changing or h/l changing twice in the same cycle an d will prevent the unexpected or error operation.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 91 version 1.1 8.5.4 pwm program example ? example: setup pwm0 output from tc0 to pwm0out (p5.4). the clock source is internal 6mhz. fcpu = fosc/1. the duty of pwm is 30/256. the pwm frequenc y is about 6khz. the pwm clock source is from external oscillator clock. tc0 rate is fcpu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 30. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc0c,a b0mov tc0r,a b0bclr ftc0out ; set duty range as 0/256~255/256. b0bclr faload0 b0bset fpwm0out ; enable pwm0 output to p5.4 and disable p5.4 i/o function b0bset ftc0enb ; enable tc0 timer ? note: the tc0r is write-only register. don?t pr ocess them using incms, decms instructions. ? example: modify tc0r registers? value. mov a, #30h ; input a number using b0mov instruction. b0mov tc0r, a incms buf0 ; get the new tc0r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc0r, a ? note: the pwm can work with interrupt request.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 92 version 1.1 8.6 timer/counter 1 (tc1) 8.6.1 overview the tc1 is an 8-bit binary up counting timer with double buffers. tc1 has two clock sources including internal clock and external clock for counting a precision time. the internal cl ock source is from fcpu. the external clock is int0 from p0.0 pin (falling edge trigger). using tc1m register selects tc 1c?s clock source from internal or external. if tc1 timer occurs an overflow, it will continue counting and issue a time -out signal to trigger tc1 interrupt to request interrupt service. tc1 overflow time is 0xff to 0x00 normally. under pwm mode, tc1 overflow is decided by pwm cycle controlled by aload0 and tc1out bits. the main purposes of the tc1 timer is as following. ) 8-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) external event counter: counts system ?events? based on falling edge detection of external clock signals at the int0 input pin. ) buzzer output ) pwm output fcpu tc0 rate (fcpu/2~fcpu/256) int0 (schmitter trigger) tc0cks tc0enb cpum0,1 tc0c 8-bit binary up counting counter tc0r reload data buffer up counting reload value tc0 time out compare aload0 r s tc0 time out auto. reload tc0 / 2 buzzer internal p5.4 i/o circuit p5.4 pwm pwm0out tc0out aload0, tc0out load
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 93 version 1.1 8.6.2 tc1m mode register 08bh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload0 tc1out pwm0out read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm0out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc1out, aload0 bits. bit 1 tc1out: tc1 time out toggle signal output control bit. only valid when pwm0out = 0. 0 = disable, p5.3 is i/o function. 1 = enable, p5.3 is output tc1out signal. bit 2 aload0: auto-reload control bit. only valid when pwm0out = 0. 0 = disable tc1 auto-reload function. 1 = enable tc1 auto-reload function. bit 3 tc1cks: tc1 clock source select bit. 0 = internal clock (fcpu or fosc). 1 = external clock from p0.0/int0 pin. bit [6:4] tc1rate[2:0]: tc1 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 tc1enb: tc1 counter control bit. 0 = disable tc1 timer. 1 = enable tc1 timer. ? note: when tc1cks=1, tc1 became an external event counter and tc1rate is useless. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0).
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 94 version 1.1 8.6.3 tc1c counting register tc1c is an 8-bit counter register for tc1 interval time control. 08ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc1c initial value is as following. tc1c initial value = n - (tc1 interrupt interval time * input clock) n is tc1 overflow boundary number. tc1 timer overflow time has six types (tc1 timer, tc1 event counter, tc1 fcpu clock source, tc1 fosc clock source, pwm mode and no pw m mode). these parameters decide tc1 overflow time and valid value as follow table. tc1cks pwm0 aload0 tc1out n tc1c valid value tc1c value binary type remark 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b overflow per 32 count 0 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 1 - - - 256 0x00~0xff 00000000b~11111111b overflow per 256 count ? example: to set 1ms interval time for tc1 interr upt. tc1 clock source is fcpu (tc1ks=0) and no pwm output (pwm0=0). high clock is internal 6mhz . fcpu=fosc/1. select tc1rate=010 (fcpu/64). tc1c initial value = n - (tc1 interrupt interval time * input clock) = 256 - (1ms * 6mhz / 1 / 64) = 256 - (10 -3 * 6 * 10 6 / 1 / 64) = 162 = a2h the basic timer table interval time of tc1. high speed mode (fcpu = 6mhz / 1) tc1rate tc1clock max overflow interval one step = max/256 000 fcpu/256 10.923 ms 42.67 us 001 fcpu/128 5.461 ms 21.33 us 010 fcpu/64 2.731 ms 10.67 us 011 fcpu/32 1.365 ms 5.33 us 100 fcpu/16 0.683 ms 2.67 us 101 fcpu/8 0.341 ms 1.33 us 110 fcpu/4 0.171 ms 0.67 us 111 fcpu/2 0.085 ms 0.33 us
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 95 version 1.1 8.6.4 tc1r auto-load register tc1 timer is with auto-load function controlled by aload0 bit of tc1m. when tc1c overflow occurring, tc1r value will load to tc1c by system. it is easy to generate an ac curate time, and users don?t reset tc1c during interrupt service routine. tc1 is double buffer design. if new tc1r value is set by program, the new value is stored in 1 st buffer. until tc1 overflow occurs, the new value moves to real tc1r buffer. this way can avoid tc1 interval time error and glitch in pwm and buzzer output. ? note: under pwm mode, auto-load is enabled automatically. the aload0 bit is selecting overflow boundary. 08dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1r tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc1r initial value is as following. tc1r initial value = n - (tc1 interrupt interval time * input clock) n is tc1 overflow boundary number. tc1 timer overflow time has six types (tc1 timer, tc1 event counter, tc1 fcpu clock source, tc1 fosc clock source, pwm mode and no pw m mode). these parameters decide tc1 overflow time and valid value as follow table. tc1cks pwm0 aload0 tc1out n tc1r valid value tc1r value binary type 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - 256 0x00~0xff 00000000b~11111111b ? example: to set 1ms interval time for tc1 interr upt. tc1 clock source is fcpu (tc1ks=0) and no pwm output (pwm0=0). high clock is internal 6mhz . fcpu=fosc/1. select tc1rate=010 (fcpu/64). tc1r initial value = n - (tc1 interrupt interval time * input clock) = 256 - (1ms * 6mhz / 1 / 64) = 256 - (10 -3 * 6 * 10 6 / 1 / 64) = 162 = a2h
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 96 version 1.1 8.6.5 tc1 clock freque ncy output (buzzer) buzzer output (tc1out) is from tc1 timer/counter frequen cy output function. by setting the tc1 clock frequency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-disable. the tc1out frequency is divided by 2 from tc1 interval time. tc1out frequency is 1/2 tc1 frequency. the tc1 clock has many combinations and easily to make difference frequency. the tc1out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc1 overflow clock tc1out (buzzer) output clock ? example: setup tc1out output from tc1 to tc1out (p5.4). the external high-speed clock is 4mhz. the tc1out frequency is 0.5khz. because the tc1out signal is divided by 2, set the tc1 clock to 1khz. the tc1 clock source is from external o scillator clock. t0c rate is fcpu/ 4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 131. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc1c,a b0mov tc1r,a b0bset ftc1out ; enable tc1 output to p5.4 and disable p5.4 i/o function b0bset faload1 ; enable tc1 auto-reload function b0bset ftc1enb ; enable tc1 timer ? note: buzzer output is enable, and ?pwm0out? must be ?0?.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 97 version 1.1 8.6.6 tc1 timer operation sequence tc1 timer operation includes timer interrupt, event counter , tc1out and pwm. the sequence of setup tc1 timer is as following. ) stop tc1 timer counting, disable tc1 interrupt function and clear tc1 interrupt request flag. ) b0bclr ftc1enb ; tc1 timer, tc1out and pwm stop. b0bclr ftc1ien ; tc1 inte rrupt function is disabled. b0bclr ftc1irq ; tc1 interrupt request flag is cleared. ) set tc1 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc1 rate control bi ts exist in bit4~bit6 of tc1m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc1m,a ; tc1 interr upt function is disabled. ) set tc1 timer clock source. ; select tc1 internal / external clock source. b0bclr ftc1cks ; select tc1 internal clock source. or b0bset ftc1cks ; select tc 1 external clock source. ) set tc1 timer auto-load mode. b0bclr faload0 ; enable tc1 auto reload function. or b0bset faload0 ; disable tc1 auto reload function. ) set tc1 interrupt interval time, tc1out (buzzer) frequency or pwm duty cycle. ; set tc1 interrupt interval time, tc 1out (buzzer) frequency or pwm duty. mov a,#7fh ; tc1c and tc1r value is decided by tc1 mode. b0mov tc1c,a ; set tc1c value. b0mov tc1r,a ; set tc1r value unde r auto reload mode or pwm mode. ; in pwm mode, set pwm cycle. b0bclr faload0 ; aload0, tc1out = 00, pwm cycle boundary is b0bclr ftc1out ; 0~255. or b0bclr faload0 ; aload0, tc1out = 01, pwm cycle boundary is b0bset ftc1out ; 0~63. or b0bset faload0 ; aload0, tc1out = 10, pwm cycle boundary is b0bclr ftc1out ; 0~31. or b0bset faload0 ; aload0, tc1out = 11, pwm cycle boundary is b0bset ftc1out ; 0~15. ) set tc1 timer function mode. b0bset ftc1ien ; enable tc1 interrupt function. or b0bset ftc1out ; enable tc 1out (buzzer) function. or b0bset fpwm0out ; enable pwm function. ) enable tc1 timer. b0bset ftc1enb ; enable tc1 timer.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 98 version 1.1 8.7 pwm1 mode 8.7.1 overview pwm function is generated by tc1 timer counter and out put the pwm signal to pwm1out pin (p5.3). the 8-bit counter counts modulus 256, 64, 32, 16 controlled by aload0, tc1out bits. the value of the 8-bit counter (tc1c) is compared to the contents of the referenc e register (tc1r). when the reference register value (tc1r) is equal to the counter value (tc1c), the pwm output goes low. when the co unter reaches zero, the pwm output is forced high. the low-to-high ratio (duty) of the pw m1 output is tc1r/256, 64, 32, 16. pwm output can be held at low level by continuously loading the reference register with 00h. under pwm operating, to change the pwm?s duty cycle is to modify the tc1r. ? note: tc1 is double buffer design. modifying tc1r to change pwm duty by program, there is no glitch and error duty signal in pwm output waveform. users can change tc1r any time, and the new reload value is loaded to tc1r buffer at tc1 overflow. aload0 tc1out pwm duty range tc1c valid value tc1r valid bits value max. pwm frequency (fcpu = 6mhz) remark 0 0 0/256~255/256 0x00~0xff 0x00~0xff 11.719k overflow per 256 count 0 1 0/64~63/64 0x00~0x3f 0x00~0x3f 46.875k overflow per 64 count 1 0 0/32~31/32 0x00~0x1f 0x00~0x1f 93.75k overflow per 32 count 1 1 0/16~15/16 0x00~0x0f 0x00~0x0f 187.5k overflow per 16 count the output duty of pwm is with different tc1r. duty range is from 0/256~255/256. tc1 clock tc1r=00h tc1r=01h tc1r=80h tc1r=ffh 0 1 128 254 255 0 1 128 254 255 low low low high high low high
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 99 version 1.1 8.7.2 tcxirq and pwm duty in pwm mode, the frequency of tc1irq is depended on pwm duty range. from following diagram, the tc1irq frequency is related with pwm duty. tc1 overflow, tc1irq = 1 pwm1 output (duty range 0~15) 0xff tc1c value 0x00 pwm1 output (duty range 0~31) 0xff tc1c value 0x00 pwm1 output (duty range 0~63) 0xff tc1c value 0x00 0xff tc1c value 0x00 pwm1 output (duty range 0~255) tc1 overflow, tc1irq = 1 tc1 overflow, tc1irq = 1 tc1 overflow, tc1irq = 1
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 100 version 1.1 8.7.3 pwm duty with tcxr changing in pwm mode, the system will compare tc1c and tc1r all the time. when tc1c SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 101 version 1.1 8.7.4 pwm program example ? example: setup pwm1 output from tc1 to pwm1out (p5.4). the clock source is internal 6mhz. fcpu = fosc/1. the duty of pwm is 30/256. the pwm frequenc y is about 6khz. the pwm clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 30. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc1c,a b0mov tc1r,a b0bclr ftc1out ; set duty range as 0/256~255/256. b0bclr faload0 b0bset fpwm1out ; enable pwm1 output to p5.4 and disable p5.4 i/o function b0bset ftc1enb ; enable tc1 timer ? note: the tc1r is write-only register. don?t pr ocess them using incms, decms instructions. ? example: modify tc1r registers? value. mov a, #30h ; input a number using b0mov instruction. b0mov tc1r, a incms buf0 ; get the new tc1r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc1r, a ? note: the pwm can work with interrupt request.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 102 version 1.1 9 universal serial bus (usb) 9.1 overview the usb is the answer to connectivity for the pc architectu re. a fast, bi-directional interrupt pipe, low-cost, dynamically attachable serial interface is consistent with the require ments of the pc platform of today and tomorrow. the sonix usb microcontrollers are optimized for human-interface com puter peripherals such as a mouse, joystick, game pad. usb specification compliance ? conforms to usb specifications, version 2.0. ? supports 1 full-speed usb device address. ? supports 1 control endpoint, 3 interrupt endpoints. ? integrated usb transceiver. ? 5v to 3.3v regulator output for d+ 1.5k ohm internal resistor pull up. 9.2 usb machine the usb machine allows the microcontroller to communica te with the usb host. the hardware handles the following usb bus activity independently of the microcontroller. the usb machine will do: ? translate the encoded received data and fo rmat the data to be transmitted on the bus. ? crc checking and generation by hardware. if crc is not corr ect, hardware will not send any response to usb host. ? send and update the data toggle bit (dat a1/0) automatically by hardware. ? send appropriate ack/nak/stall handshakes. ? setup, in, or out token type identification. set t he appropriate bit once a valid token is received. ? place valid received data in the appropriate endpoint fifos. ? bit stuffing/unstuffing. ? address checking. ignore the transa ctions not addressed to the device. ? endpoint checking. check the endpoint?s request from usb host, and set the appropriate bit of registers. firmware is required to handle the rest of the following tasks: ? coordinate enumeration by dec oding usb device requests. ? fill and empty the fifos. ? suspend/resume coordination. ? remote wake up function. ? determine the right interrupt request of usb communication. 9.3 usb interrupt the usb function will accept the usb host command and generate the relative interrupts, and the program counter will go to 0x08 vector. firmware is required to check the usb st atus bit to realize what r equest comes from the usb host. the usb function interrupt is generated when: ? the endpoint 0 is set to accept a setup token. ? the device receives an ack handshake after a su ccessful read transaction (in) from the host. ? if the endpoint is in ack out modes, an in terrupt is generated when data is received. ? the usb host send usb suspend request to the device. ? usb bus reset event occurs. ? the usb endpoints interrupt after a usb transaction complete is on the bus. ? the sof packet received if the sof interrupt enable. ? the nak handshaking when the nak interrupt enable. the following examples show how to avoid the error of reading or writing the endpoint fifos and to do the right usb request routine according to the flag.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 103 version 1.1 9.4 usb enumeration a typical usb enumeration sequence is shown below. 1. the host computer sends a setup packet followed by a data packet to usb address 0 requesting the device descriptor. 2. firmware decodes the request and retrieves its de vice descriptor from the program memory tables. 3. the host computer performs a control read sequence and firmware responds by sending the device descriptor over the usb bus, via the on-chip fifo. 4. after receiving the descriptor, the host sends a setup packet followed by a data packet to address 0 assigning a new usb address to the device. 5. firmware stores the new address in its usb device address register after t he no-data control sequence completes. 6. the host sends a request for the devi ce descriptor using the new usb address. 7. firmware decodes the request and retrieves the device descriptor from program memory tables. 8. the host performs a control read sequence and firmware responds by sending its device descriptor over the usb bus. 9. the host generates control reads from the device to request the configuration and report descriptors. 10. once the device receives a set configurat ion request, its functions may now be used. 11. firmware should take appropriate action for endpoint 0~3 transactions, which may occur from this point.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 104 version 1.1 9.5 usb registers 9.5.1 usb device address register the usb device address register (uda) contains a 7-bit usb device address and one bit to enable the usb function. this register is cleared during a reset, setting the usb device address to zero and disable the usb function. 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uda ude uda6 uda5 uda4 uda3 uda2 uda1 uda0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [6:0] uda [6:0]: these bits must be set by firmware during the usb enumeration process (i.e., setaddress) to the non-zero address assigned by the usb host. bit 7 ude: device function enable. this bit must be enabled by firmware to enable the usb device function. 0 = disable usb device function. 1 = enable usb device function. 9.5.2 usb status register the usb status register indicates the status of usb. 091h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ustatus sof bus_rst suspend ep0_setup ep0_in ep0_out read/write r/w r r r/w r/w r/w after reset 0 0 0 0 0 0 bit 0 ep0_out : endpoint 0 out token received. 0 = endpoint 0 has no out token received. 1 = a valid out packet has been received. the bit is se t to 1 after the last received packet in an out transaction. bit 1 ep0_in : endpoint 0 in token received. 0 = endpoint 0 has no in token received. 1 = a valid in packet has been received. the bit is se t to 1 after the last received packet in an in transaction. bit 2 ep0_setup : endpoint 0 setup token received. 0 = endpoint 0 has no setup token received. 1 = a valid setup packet has been received. the bit is set to 1 after the last received packet in an setup transaction. while the bit is set to 1, the host can not write any data in to ep0 fifo. this prevents sie from overwriting an incoming setup transaction befor e firmware has a chance to read the setup data. bit 3 suspend: indicate usb suspend status. 0 = non-suspend status. when mcu wakeup from sleep mode by usb resume wakeup request, the bit will changes from 1 to 0 automatically. 1 = set to 1 by hardware when usb suspend request. bit 4 bus_rst: usb bus reset. 0 = non-usb bus reset. 1 = set to 1 by hardware when usb bus reset request. bit 5 sof: indicate the usb sie?s sof packet is received 0 = non usb sie?s sof packet received. 1 = if sof_int_en = 1 then this bit will set to 1 by hardware when the sof packet is received. otherwise the bit will always be 0. clear this bit and also the bit 7 of intrq register (0x c8) by firmware.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 105 version 1.1 9.5.3 usb data count register the usb ep0 out token data byte counter. 092h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep0out_cnt uep0oc4 uep0 oc3 uep0oc2 u ep0oc1 uep0oc0 read/write r/w r/w r/w r/w r/w after reset 0 0 0 0 0 bit [4:0] uep0c [4:0]: usb endpoint 0 out token data counter. 9.5.4 usb enable control register the register control the regulator output 3.3 volts enable, sof packet receive interrupt, nak handshaking interrupt and d+ internal 1.5k ohm pull up. 093h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usb_int_en reg_en dp _up_en sof_int_en ep3nak _int_en ep2nak _int_en ep1nak _int_en read/write r/w r/w r/w r/w r/w r/w after reset 1 0 0 0 0 0 bit [2:0] epnnak_int_en [2:0]: ep1~ep3 nak transaction interrupts enable control bits . n = 1, 2, 3. 0 = disable nak transaction interrupt request. 1 = enable nak transaction interrupt request. bit 5 sof_int_en: usb sie?s sof packet receive interrupt enable. clear the bit and the bit 7 of inten register (0x c9) = disable usb sie?s sof interrupt request. set the bit and the bit 7 of inten register (0x c9) to 1 = enable usb sie?s sof interrupt request. the bit 6 dp_up_en: d+ internal 1.5k ohm pull up resistor control bit. 0 = disable d+ pull up 1.5k ohm to 3.3volts. 1 = enable d+ pull up 1.5k ohm to 3.3volts. bit 7 reg_en: 3.3volts regulator control bit. 0 = disable regulator output 3.3volts. 1 = enable regulator output 3.3volts. 9.5.5 usb endpoint?s ack handshaking flag register the status of endpoint?s ack transaction. 094h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep_ack ep3_ack ep2_ack ep1_ack read/write r/w r/w r/w after reset 0 0 0 bit [2:0] epn_ack [2:0]: ep1~ep3 ack transaction . n= 1, 2, 3 . the bit is set whenever the endpoint that completes with an ack received. 0 = the endpoint (interrupt pipe) doesn?t complete with an ack. 1 = the endpoint (interrupt pipe) complete with an ack.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 106 version 1.1 9.5.6 usb endpoint?s nak handshaking flag register the status of endpoint?s nak transaction. 095h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep_nak ep3_nak ep2_nak ep1_nak read/write r/w r/w r/w after reset 0 0 0 bit [2:0] epn_nak [2:0]: ep1~ep3 nak transaction . n = 1, 2, 3 . the bit is set whenever the endpoint that completes with an nak received. 0 = the epnnak_int_en = 0 or the endpoint (inte rrupt pipe) doesn?t complete with an nak. 1 = the epnnak_int_en = 1 and the endpoint (interrupt pipe) complete with an nak. 9.5.7 usb endpoint 0 enable register an endpoint 0 (ep0) is used to initialize and control the usb dev ice. ep0 is bi-directional (control pipe), as the device, can both receive and transmit data, whic h provides to access the device configuration information and allows generic usb status and control accesses. 096h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue0r - ue0m1 ue0m0 - ue 0c3 ue0c ue0c1 ue0c0 read/write - r/w r/ w - r/w r/w r/w r/w after reset - 0 0 - 0 0 0 0 bit [3:0] ue0c [3:0]: indicate the number of data bytes in a transac tion: for in transactions, firmware loads the count with the number of bytes to be transmi tted to the host from the endpoint 0 fifo. bit [6:5] ue0m [1:0]: the endpoint 0 modes determine how the sie responds to usb traffic that the host sends to the endpoint 0. for example, if the endpoi nt 0?s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 0.the bit 5 ue0m0 will auto reset to zero when the ack transaction complete. usb endpoint 0?s mode table ue0m1 ue0m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 107 version 1.1 9.5.8 usb endpoint 1 enable register the communication with the usb host using endpoint 1, endpoi nt 1?s fifo is implemented as 16 bytes of dedicated ram. the endponit1 is an interrupt endpoint. 097h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue1r ue1e ue1m1 ue1m0 ue1c 4 ue1c3 ue1c2 ue1c1 ue1c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [4:0] ue1c [4:0]: indicate the number of data bytes in a transac tion: for in transactions, firmware loads the count with the number of bytes to be transmi tted to the host from the endpoint 1 fifo. bit [6:5] ue1m [1:0]: the endpoint 1 modes determine how the sie responds to usb traffic that the host sends to the endpoint 1. for example, if the endpoi nt 1?s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 1.the bit 5 ue1m0 will auto reset to zero when the ack transaction complete. usb endpoint 1?s mode table ue1m1 ue1m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall bit 7 ue1e: usb endpoint 1 function enable bit. 0 = disable usb endpoint 1 function. 1 = enable usb endpoint 1 function. 9.5.9 usb endpoint 2 enable register the communication with the usb host using endpoint 2, endpoi nt 2?s fifo is implemented as 16 bytes of dedicated ram. the endpoint 2 is an interrupt endpoint. 098h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue2r ue2e ue2m1 ue2m0 ue2c 4 ue2c3 ue2c2 ue2c1 ue2c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [4:0] ue2c [4:0]: indicate the number of data bytes in a transac tion: for in transactions, firmware loads the count with the number of bytes to be transmi tted to the host from the endpoint 2 fifo. bit [6:5] ue2m [1:0]: the endpoint 2 modes determine how the sie responds to usb traffic that the host sends to the endpoint 2. for example, if the endpoi nt 2?s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 2. the bit 5 ue2m0 will auto reset to zero when the ack transaction complete. usb endpoint 2?s mode table ue2m1 ue2m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall bit 7 ue2e: usb endpoint 2 function enable bit. 0 = disable usb endpoint 2 function. 1 = enable usb endpoint 2 function.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 108 version 1.1 9.5.10 usb endpoint 3 enable register the communication with the usb host using endpoint 3, endpoi nt 3?s fifo is implemented as 8 bytes of dedicated ram. the endpoint 3 is an interrupt endpoint. 099h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue3r ue3e ue3m1 ue3m0 ue3c 4 ue3c3 ue3c2 ue3c1 ue3c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [4:0] ue3c [4:0]: indicate the number of data bytes in a transac tion: for in transactions, firmware loads the count with the number of bytes to be transmi tted to the host from the endpoint 3 fifo. bit [6:5] ue3m [1:0]: the endpoint 3 modes determine how the sie responds to usb traffic that the host sends to the endpoint 3. for example, if the endpoi nt 3?s mode bit is set to 00 that is nak in/out mode as shown in table, the usb sie will send nak handshakes in response to any in/out token set to the endpoint 3. the bit 5 ue3m0 will auto reset to zero when the ack transaction complete. usb endpoint 3?s mode table ue3m1 ue3m0 in/out token handshake 0 0 nak 0 1 ack 1 0 stall 1 1 stall bit 7 ue3e: usb endpoint 3 function enable bit. 0 = disable usb endpoint 3 function. 1 = enable usb endpoint 3 function. 9.5.11 usb data pointer register usb fifo address pointer. use the point to set the fifo addr ess for reading data from usb fifo and writing data to usb fifo. 0a3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 udp0 udp07 udp06 udp05 udp04 udp03 udp02 udp01 udp00 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 address [07]~address [00]: data buffer for endpoint 0. address [17]~address [08]: data buffer for endpoint 1. address [27]~address [18]: data buffer for endpoint 2. address [37]~address [28]: data buffer for endpoint 3. 9.5.12 usb data read/write register 0a5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 udr0_r udr0_r7 udr0_r6 udr0_r5 udr0_r4 udr0_r3 udr0_r2 udr0_r1 udr0_r0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 udr0_r: read the data from usb fifo which udp0 register point to. 0a6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 udr0_w udr0_w7 udr0_w6 udr0_w5 udr0_w4 udr0_w3 udr0_w2 udr0_w1 udr0_w0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 udr0_w: write the data to usb fifo which udp0 register point to.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 109 version 1.1 9.5.13 usb endpoint out token data bytes counter endpoint 1?s out token data bytes counter. 0a7h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep1out_cnt - - - uep1oc4 uep1 oc3 uep1oc2 u ep1oc1 uep1oc0 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 bit [4:0] uep1cn: bytes counter of ep1 token data. reset by firmware. 9.5.14 endpoint 2?s out to ken data bytes counter. 0a8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep2out_cnt - - - uep2oc4 uep2 oc3 uep2oc2 u ep2oc1 uep2oc0 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 bit [4:0] uep2cn: bytes counter of ep2 token data. reset by firmware. 9.5.15 endpoint 3?s out to ken data bytes counter. 0a9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep3out_cnt - - - uep3oc4 uep3 oc3 uep3oc2 u ep3oc1 uep3oc0 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 bit [4:0] uep3cn: bytes counter of ep3 token data. reset by firmware. 9.5.16 upid register forcing bits allow firmware to directly drive the d+ and d? pins. 0abh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 upid ep0out_en - - - - ubde ddp ddn read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 0 0 0 bit 0 ddn: drive d- on the usb bus. 0 = drive d- low. 1 = drive d- high. bit 1 ddp: drive d+ on the usb bus. 0 = drive d+ low. 1 = drive d+ high. bit 2 ubde: enable to direct drive usb bus. 0 = disable. 1 = enable. bit 7 ep0out_en: enable ep0 control data out. 0 = disable. 1 = enable to receive the ep0 cont inuous out token data over 8 bytes. 9.5.17 endpoint toggle bit control register 0ach bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 utoggle - - - - - ep3 _data0/1 ep2 _data0/1 ep1 _data0/1 read/write - - - - - r/w r/w r/w after reset - - - - - 1 1 1 bit [2:0] endpoint 1~3?s data0/1 toggle bit control. 0 = clear the endpoint 1~3?s toggle bit to data0 1 = hardware set toggle bit automatically.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 110 version 1.1 10 serial input/output transceiver 10.1 overview the sio (serial input/output) transceiver allows high-speed synchronous data transfer between the SN8F2250B series mcu and peripheral devices or between several SN8F2250B devices. these peripheral devices may be serial eeproms, shift registers, display drivers, etc. the SN8F2250B sio features include the following: z full-duplex, 3-wire synchronous data transfer z tx/rx or tx only mode z master (sck is clock output) or sl ave (sck is clock input) operation z msb/lsb first data transfer z sdo (p5.2) is programmable open-drain output pin for multiple salve devices application z two programmable bit rates (only in master mode) z end-of-transfer interrupt the siom register can control sio operating function, such as: transmit/receive, clock rate, transfer edge and starting this circuit. this sio circuit will tran smit or receive 8-bit data automatically by setting senb and start bits in siom register. the siob is an 8-bit buffer, which is design ed to store transfer data. sioc and sior are designed to generate sio?s clock source with auto-reload function. the 3-bit i/o counter can monitor the operation of sio and announce an interrupt request after transmitting/receiving 8- bit data. after transferring 8-bit data, this circuit will be disabled automatically and re-transfer data by programming siom register. 1 8 16 32 fcpu cpum1,0 senb sck senb sclkmd sio 8-bit counter cpum1,0 sior register auto-reload cpol sio 3-bit i/o counter sio time out siob 8-bit buffer 8-bit receive buffer mlsb so senb cpum1,0 si senb cpum1,0 mlsb cpha srate1,0 start sio interface circuit diagram
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 111 version 1.1 the system is single-buffered in the tran smit direction and double-buffered in t he receive direction. this means that bytes to be transmitted cannot be written to the siob data register before the entire shift cycle is completed. when receiving data, however, a received byte must be read from the siob data register before the next byte has been completely shifted in. otherwise, the first byte is lo st. following figure shows a typical sio transfer between two SN8F2250B micro-controllers. master mcu sends sck for initial the data tr ansfer. both master and slave mcu must work in the same clock edge direction, and then both cont rollers would send and receive data at the same time. sio data transfer diagram shift register (siob) 2nd receive buffer (address = siob) internal bus read siob write siob sio master (sckmd = 0) so si sck shift register (siob) 2nd receive buffer (address = siob) internal bus read siob write siob sio slave (sckmd = 1) si so sck
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 112 version 1.1 the sio data transfer timing as following figure: m l s b c p o l c p h a sck idle status diagrams 0 0 1 low bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 1 1 high bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 low bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 next data 0 1 0 high bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 next data 1 0 1 low bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 1 1 high bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 0 0 low next data bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 1 0 high next data bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 sio data transfer timing
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 113 version 1.1 10.2 siom mode register 0b4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siom senb start srate1 srate0 mlsb sckmd cpol cpha read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 senb: sio function control bit. 0 = disable (p5.0~p5.2 is general purpose i/o port). 1 = enable (p5.0~p5.2 is sio pins). bit 6 start: sio progress control bit. 0 = end of transfer. 1 = progressing. bit [5:4] srate1:0: sio?s transfer rate select bit. these 2-bits are workless when sckmd=1. 00 = fcpu. 01 = fcpu/32 10 = fcpu/16 11 = fcpu/8. bit 3 mlsb: msb/lsb transfer first. 0 = msb transmit first. 1 = lsb transmit first. bit 2 sckmd: sio?s clock mode select bit. 0 = internal. (master mode) 1 = external. (slave mode) bit 1 cpol: sio?s transfer clock edge select bit. 0 = sck idle status is low status 1 = sck idle status is high status bit 0 cpha: the clock phase bit controls the phase of the clock on which data is sampled. 0 = data receive at the fisrt clock phase. 1 = data receive at t he second clock phase. ? note: 1. if sckmd=1 for external clock, the sio is in slave mode. if sckmd=0 for internal clock, the sio is in master mode. 2. don?t set senb and start bits in the same time. that makes the sio function error. because sio function is shared with port5 for p5.0 as sck, p5.1 as sdi and p5.2 as sdo. the following table shown the port5[2:0] i/o mode be havior and setting when sio function enable and disable. senb=1 (sio function enable) (sckmd=1) sio source = external clock p5.0 will change to input mode automatically, no matter what p5m setting p5.0/sck (sckmd=0) sio source = internal clock p5.0 will change to output mode automatically, no matter what p5m setting p5.1/sdi p5.1 must be set as input mode in p5m ,or the sio function will be abnormal p5.2/sdo sio = transmitter/receiver p5.2 will change to output mode automatically, no matter what p5m setting senb=0 (sio function disable) p5.0/p5.1/p5.2 port5[2:0] i/o mode are fully c ontrolled by p5m when sio function is disable
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 114 version 1.1 10.3 siob data buffer 0b6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siob siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 siob is the sio data buffer register. it stores serial i/o transmit and receive data. 10.4 sior register description 0b5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sior sior7 sior6 sior5 sior4 sior3 sior2 sior1 sior0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the sior is designed for the sio counter to reload the count ed value when end of counting. it is like a post-scaler of sio clock source and let sio has more flexible to setti ng sck range. users can set the sior value to setup sio transfer time. the valid sior value = 0x0 to 0xfd. to setup sior value equation to desire transfer time is as following. sck frequency = sio rate / (256 - sior); sior = 256 - ( 1 / ( sck frequency ) * sio rate ) example: setup the sio clock to be 2mhz. fosc = 12mhz. sio?s rate = fcpu/2. fcpu = fosc/1 = 12mhz. sior = 256 ? (1/(2mhz) * 12mhz/2) = 256 ? 3 = 253 = 0xfd example: master, duplex transfer and transmit data on rising edge mov a,txdata ; load transmitted data into siob register. b0mov siob,a mov a,#0feh ; set sio clock b0mov sior,a mov a,#10000000b ; setup siom and enable sio function. b0mov siom,a b0bset fstart ; start trans fer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a example: slave, duplex transfer and transmit data on rising edge mov a,txdata ; load transfer data into siob register. b0mov siob,a mov a,# 10000100b ; setup siom and enable sio function. b0mov siom,a b0bset fstart ; start trans fer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 115 version 1.1 11 flash 11.1 overview the SN8F2250B series usb mcu integrated device feat ure in-system programmable (isp) flash memory for convenient, upgradeable code storage. the flash me mory may be programmed via the sonix 8 bit mcu programming interface or by application code and usb inte rface for maximum flexibility. the SN8F2250B provides security options at the disposal of the designer to prevent unauthorized access to information stored in flash memory. ? the mcu is stalled during flash write (program) and eras e operations, although peripherals (usb, timers, wdt, i/o, pwm, etc.) remain active. ? interrupts will disable by firmware du ring a flash write or erase operation. ? the flash page containing the boot loader and code op tion (rom address 0x2000 ~ 0x27ff) cannot be erased from application code when the code option?s security1 enable. ? watch dog timer should be clear before the flash write or erase operation. ? the erase operation sets all the bi ts in the flash page to logic 1. ? hardware will hold system clock and automatically move out data from ram and do programming, after programming finished, hardware will release system cl ock and let mcu execute the next instruction.(recommend add two nop instructions after this active) . 11.2 flash programming/erase control register 0bah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pecmd pecmd7 pecmd6 pecmd5 pecmd4 pecmd3 pecmd2 pecmd1 pecmd0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit [7:0] pecmd[7:0]: 0x5a: page program (32 words/page) , 0xc3: page erase (128 words/page)
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 116 version 1.1 11.3 programming/erase address register 0bbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peroml peroml7 peroml6 per oml5 peroml4 peroml3 per oml2 peroml1 peroml0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] peroml[7:0]: define the target starting low byte address [7:0 ] of flash memory (10k x 16) which is going to be programmed or erased. 0bch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peromh peromh7 peromh6 per omh5 peromh4 peromh3 per omh2 peromh1 peromh0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:0] peromh [7:0]: define the target starting high address [15:8] of flash memory (10k x 16) which is going to be programmed or erased. the valid page erase starting addresses are 0x0, 0x80, 0x100, 0x180, 0x 200, 0x280, 0x300, 0x380 ? 0x2780. the page erase function is used to erase a page of 128 contiguous words in flash rom. note: if the code option security1 = 0 (security1 disable), the code option address 0x27fc ~ 0x27ff will not be protected by hardware. and the code option can be ?erase and program? by the in-system-programming function. to avoid the error occur, when secuirty1 = 0 (security1 disable), please do not set the page erase starting address at 0x2780. the valid page program starting addresses are 0x0, 0x20, 0x40, 0x60, 0x80, 0xa 0, 0xc0, 0xe0 ? 0x27e0. the page program function is used to program a page of 32 contiguous words in flash rom. 10kx16 flash 0000h reset vector user reset vector jump to user start address 0001h . . 0007h general purpose area 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . . general purpose area 2000h . 27fbh end of user program 27fch 27fdh 27feh 27ffh security1 protect & reserved (code option) flash rom mapping note: 1. if the code option security1 = 1 (sec urity1 enable), the flash rom address = 0x2000 ~ 0x27ff will not allow to do the ?page erase and page program?. 2. if the code option security1 = 0 (security1 disable), the code option address 0x27fc ~ 0x27ff will not be protected by hardwa re. and the code option can be ?erase and program? by the in-system-programming function.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 117 version 1.1 11.4 programming/erase data register 0bdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peraml peraml7 peraml6 peraml5 peraml4 peraml3 peraml2 peraml1 peraml0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0beh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peramcnt peramcnt4 peramcnt3 peramcnt2 peram cnt1 peramcnt0 - - peraml8 read/write r/w r/w r/w r/w r/w - - r/w after reset 0 0 0 0 0 - - 0 {peramcnt [1:0], peraml [7:0]} : define the starting ram address [9:0], which stores the data wanted to be programmed. the valid ram addresses are 00h ~ 07fh and 0100h ~ 01ffh. peramcnt [7:3] : defines the number of words wanted to be programmed. the maximum peramcnt [7:3] is 01fh, which program 32 words (64 bytes ram) to the flash. the minimum peramcnt [7:3] is 00h, which program only 1 word to the flash. 11.4.1 flash in-system-programming mapping address ram (byte) flash rom (word) bit7 ~ bit0 bit15 ~ bit8 bit7 ~ bit0 x data0 y data1 data0 x+1 data1 y+1 data3 data2 x+2 data2 => y+2 x+3 data3 y+3 ? ? x+n datan y+m datan datan-1
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 118 version 1.1 12 instruction table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bank 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, ?m? only supports 0x80~0x87 registers (e.g. pflag,r,y,z?) - - - 1 xch a,m a m - - - 1+n b0xch a,m a m (bank 0) - - - 1+n movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1+n r add a,m a ( a + m, if occur carry, then c=1, else c=0 1 i add m,a m ( a + m, if occur carry, then c=1, else c=0 1+n t b0add m,a m (bank 0) ( m (bank 0) + a, if occur carry, then c=1, else c=0 1+n h add a,i a ( a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a ( a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m ( a - m - /c, if occur borrow, then c=0, else c=1 1+n t sub a,m a ( a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m ( a - m, if occur borrow, then c=0, else c=1 1+n c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 and a,m a a and m - - 1 l and m,a m a and m - - 1+n o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1+n c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1+n xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1+n r rrc m a rrc m -- 1 o rrcm m m rrc m -- 1+n c rlc m a rlc m -- 1 e rlcm m m rlc m -- 1+n s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1+n bset m.b m.b 1 - - - 1+n b0bclr m.b m(bank 0).b 0 - - - 1+n b0bset m.b m(bank 0).b 1 - - - 1+n cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1+ s a incms m m m + 1, if m = 0, then skip next instruction - - - 1+n+s n decs m a m - 1, if a = 0, then skip next instruction - - - 1+ s c decms m m m - 1, if m = 0, then skip next instruction - - - 1+n+s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s push to push acc and pflag (except nt0, npd bit) into buffers. - - - 1 c pop to pop acc and pflag (except nt0, npd bit) from buffers. 1 nop no operation - - - 1 note: 1. ?m? is system register or ram. if ?m? is system registers then ?n? = 0, otherwise ?n? = 1. 2. if branch condition is true then ?s = 1?, otherwise ?s = 0?.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 119 version 1.1 13 development tool sonix provides ice (in circuit emulation), ide (integrate d development environment), ev-kit and firmware library for usb application development. ice and ev-kit is external hard ware device and ide is a friendly user interface for firmware development and emulation. 13.1 ice (in circuit emulation) the ice called ?sn8ice2k plus?
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 120 version 1.1 13.2 SN8F2250B ev-kit the SN8F2250B and sn8f2250 use the same ev-kit. the ev-ki t includes ice interface, gpio interface, usb interface, and vreg 3.3v power supply. z ice interface: interface connected to sn8ice2k plus z gpio interface: sn8f2251/11/21/ 53/531/55 package form connector. z usb interface: usb mini-b connector. z vreg 3.3v power supply: use sn8p2212?s vr eg to supply 3.3v power for vreg pin. the outline of sn8f2250/SN8F2250B ev-kit is as following. z j1: jumper to connect between the 5v vdd from sn8ice2k plus and vdd_ic on sn8f2251/11/21/53/531/55 package form socket. z j4: usb mini-b connector. z u8: sn8p2212 to supply 3.3v pow er for vreg pin and usb phy. z u9-u14: sn8f2251/11/21/53/531/55 conne ctor for user?s target board. 13.3 sn8f2250/SN8F2250B transition board the sn8f2250 and SN8F2250B use the same transition boards. the transition boards includes total 6 models, and each of them is designated to each ic package. the following shows the transition board outline for sn8f22531. among the board, both c1 and c2 must be welded by 1uf capacitor.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 121 version 1.1 14 electrical characteristic 14.1 absolute maximum rating supply voltage (vdd)????????????????????????????????????????????.?????? - 0.3v ~ 6.0v input in voltage (vin)????????????????????????????????????????????.? vss ? 0.2v ~ vdd + 0.2v operating ambient temperature (topr) sn8f2251bj, sn8f22521b/2253bs, sn8f22521bx, sn8f2253bj, sn8f2255bf ?????????...?. ??????? 0 c ~ + 70 c storage ambient temperature (tstor) ?????????????????????????.???????????????? ?30 c ~ + 125 c 14.2 electrical characteristic (all of voltages refer to vss, vdd = 5.0v, fosc = 12mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit vdd1 normal mode except usb transmitter specifications, vpp = vdd 4.0 5 5.5 v operating voltage vdd2 usb mode 4.25 5 5.25 v ram data retention voltage vdr - 1.5* - v vdd rise rate vpor vdd rise rate to ensure power-on reset 0.05 - - v/ms vil1 p0, p1, p5.3, p5.4 input ports vss - 0.3vdd v input low voltage vil2 p2, p5.0, p5.1, p5.2 input ports vss - 0.2 vreg33 v vih1 p0, p1, p5.3, p5.4 input ports 0.7vdd - vdd v input high voltage vih2 p2, p5.0, p5.1, p5.2 input ports 0.8 vreg33 - vdd v reset pin leakage current ilekg vin = vdd - - 2 ua i/o port pull-up resistor rup1 rup1 p0, p1, p5 .3, p5.4 ?s vin = vss, vdd = 5v 25 40* 70 k i/o port pull-up resistor rup2 rup2 p2, p5.0, p5.1, p5.2?s vin = vss, vdd = 5v 50 100* 150 k d+ pull-up resistor rd+ vdd = 5v, vreg = 3.3v 1.35 1.5 1.65 k i/o port input leakage current ilekg pull-up resistor disable, vin = vdd - - 2 ua i/o output source current ioh vop = vdd ? 1v 15 20* sink current iol vop = vss + 0.4v 15* 20 ma intn trigger pulse width tint0 int0 inte rrupt request pulse width 2/fcpu - - cycle page erase (128 words) terase flash rom page erase time - 25* tbd ms page program (32 words) tpg flash rom page pr ogram time (program 32 words) - 1* tbd ms vreg33 regulator current ivreg33 vreg33 max regulator output current, vcc > 4.35 volt with 10uf to gnd - - 60 ma vreg33 regulator gnd current ivreg33 _gnl no loading. vreg33 pin output 3.3v ((regulator enable) - 70 100 ua vreg25 regulator gnd current ivreg25 _gnl no loading.vreg25 pin output 2.5v ((regulator enable) - 120 150 ua vreg1 vcc > 4.35v, 0 < temp < 40c, ivreg 60 ma with 10uf to gnd Q 3.0 - 3.6 v vreg33 regulator output voltage vreg2 vcc > 4.35v, 0 < temp < 40c, ivreg 25 ma with 10uf to gnd Q 3.1 - 3.6 v idd1 normal mode (no loading, fcpu = fosc/1) vdd= 5v, 12mhz - 10 15 ma idd2 slow mode (internal low rc) vdd= 5v, 24khz - 190 250 ua idd3 sleep mode vdd= 5v - 190 250 ua vdd= 5v, 12mhz - 5 10 ma supply current idd4 green mode (no loading, fcpu = fosc/4 watchdog disable) vdd=5v, ilrc 24khz - 190 250 ua lvd voltage vdet low voltage reset level. 2.0 2.4 2.9 v * these parameters are for design reference, not tested.
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 122 version 1.1 15 flash rom programming pin programming information of sn8f2250 series chip name sn8f2251bj sn8f22521bs/x sn8f2253bs sn8f22531bj sn8f2255bf ez writer / mp writer connector flash ic / jp3 pin assigment numbe r name number pin number pin number pin number pin number pin 1 vdd 11 vdd 18 vdd 20 vdd 23 vdd 14 vdd 2 gnd 5 vss 14 vss 16 vss 19 vss 10 vss 3 clk 10 p2.0 19 p2.0 21 p2.0 24 p2.0 15 p2.0 4 ce 5 pgm 15 p1.0 6 p1.0 6 p1.0 9 p1.0 26 p1.0 6 oe 9 p2.1 20 p2.1 22 p2.1 1 p2.1 16 p2.1 7 d1 8 d0 9 d3 10 d2 11 d5 12 d4 13 d7 14 d6 15 vdd 16 - 17 hls 18 rst 19 - 20 alsb/pdb 16 p1.1 7 p1.1 7 p1.1 10 p1.1 27 p1.1
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 123 version 1.1 programming information of sn8f2250 series chip name sn8f22511bx ez writer / mp writer connector flash ic / jp3 pin assigment numbe r name number pin 1 vdd 14 vdd 2 gnd 10 vss 3 clk 15 p2.0 4 ce 5 pgm 4 p1.0 6 oe 16 p2.1 7 d1 8 d0 9 d3 10 d2 11 d5 12 d4 13 d7 14 d6 15 vdd 16 - 17 hls 18 rst 19 - 20 alsb/pdb 5 p1.1
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 124 version 1.1 16 package information 16.1 lqfp32 pin min. max. symbols (mm) a -- 1.6 a1 0.05 0.15 a2 1.35 1.45 c1 0.09 0.16 d 9.00 bsc d1 7.00 bsc e 9.00 bsc e1 7.00 bsc e 0.8 bsc b 0.30 0.45 l 0.45 0.75 l1 1 ref
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 125 version 1.1 16.2 sop 24 pin min nor max min nor max symbols (inch) (mm) a - - 0.104 - - 2.642 a1 0.004 - - 0.102 - - d 0.599 0.600 0.624 15.214 15.24 15.84 e 0.291 0.295 0.299 7.391 7.493 7.595 h 0.394 0.407 0.419 10.008 10.337 10.643 l 0.016 0.035 0.050 0.406 0.889 1.270 0 4 8 0 4 8 16.3 sop 20 pin
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 126 version 1.1 min nor max min nor max symbols (inch) (mm) a 0.093 0.099 0.104 2.362 2.502 2.642 a1 0.004 0.008 0.012 0.102 0.203 0.305 d 0.496 0.502 0.508 12.598 12.751 12.903 e 0.291 0.295 0.299 7.391 7.493 7.595 h 0.394 0.407 0.419 10.008 10.325 10.643 l 0.016 0.033 0.050 0.406 0.838 1.270 0 4 8 0 4 8
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 127 version 1.1 16.4 ssop 20 pin min nor max min nor max symbols (inch) (mm) a 0.053 0.063 0.069 1.350 1.600 1.750 a1 0.004 0.006 0.010 0.100 0.150 0.250 a2 - - 0.059 - - 1.500 b 0.008 0.010 0.012 0.200 0.254 0.300 c 0.007 0.008 0.010 0.180 0.203 0.250 d 0.337 0.341 0.344 8.560 8.660 8.740 e 0.228 0.236 0.244 5.800 6.000 6.200 e1 0.150 0.154 0.157 3.800 3.900 4.000 [e] 0.025 0.635 h 0.010 0.017 0.020 0.250 0.420 0.500 l 0.016 0.025 0.050 0.400 0.635 1.270 l1 0.039 0.041 0.043 1.000 1.050 1.100 zd 0.059 1.500 y - - 0.004 - - 0.100 0 - 8 0 - 8
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 128 version 1.1 16.5 qfn 24 pin
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 129 version 1.1 16.6 qfn 16 pin
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 130 version 1.1 16.7 ssop 16 pin min nor max min nor max symbols (inch) (mm) a 0.053 - 0.069 1.3462 - 1.7526 a1 0.004 - 0.010 0.1016 - 0.254 a2 - - 0.059 - - 1.4986 b 0.008 - 0.012 0.2032 - 0.3048 b1 0.008 - 0.011 0.2032 - 0.2794 c 0.007 - 0.010 0.1778 - 0.254 c1 0.007 - 0.009 0.1778 - 0.2286 d 0.189 - 0.197 4.8006 - 5.0038 e1 0.150 - 0.157 3.81 - 3.9878 e 0.228 - 0.244 5.7912 - 6.1976 l 0.016 - 0.050 0.4064 - 1.27 e 0.025 basic 0.635 basic 0 - 8 0 - 8
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 131 version 1.1 17 marking definition 17.1 introduction there are many different types in sonix 8-bit mcu production line. this note listed the produ ction definition of all 8-bit mcu for order or obtain information. 17.2 marking indetification system title sonix 8-bit mcu production rom type p=otp f=flash material b = pb-free package g = green package temperature range - = 0 ~ 70 d = -40 ~ 85 shipping package w = wafer h = dice k = sk-dip p = p-dip s = sop x = ssop f = lqfp j = qfn device device part no. sn8 x part no. x x x
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 132 version 1.1 17.3 marking example name rom type device package temperature material sn8f2253bsb flash memory 2253b sop 0 ~70 pb-free package sn8f2253bxb flash memory 2253b ssop 0 ~70 pb-free package sn8f2251bjg flash memory 2251b qfn 0 ~70 green package sn8f2253bsg flash memory 2253b sop 0 ~70 green package sn8f2253bxg flash memory 2253b ssop 0 ~70 green package sn8f2255bfg flash memory 2255b lqfp 0 ~70 green package sn8f2253bw flash memory 2253b wafer 0 ~7 0 - sn8f2253bh flash memory 2253b dice 0 ~70 - 17.4 datecode system x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . .
SN8F2250B series usb 2.0 full-speed 8-bit micro-controller sonix technology co., ltd page 133 version 1.1 sonix reserves the right to make change without further notic e to any products herein to im prove reliability, function or design. sonix does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey any license under its patent rights no r the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cos t, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 10f-1, no. 36, taiyuan stree., chupei city, hsinchu, taiwan r.o.c. tel: 886-3-5600 888 fax: 886-3-5600 889 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: unit no.705,level 7 tower 1,grand central plaza 138 shatin rural committee road,shatin,new territories,hong kong. tel: 852-2723-8086 fax: 852-2723-9179 technical support by email: sn8fae@sonix.com.tw

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