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  www.irf.com 1 05/18/04 irl7833pbf IRL7833SPBF irl7833lpbf hexfet   power mosfet notes   through  are on page 12 applications benefits  very low rds(on) at 4.5v v gs  ultra-low gate impedance  fully characterized avalanche voltage and current  high frequency synchronous buck converters for computer processor power  high frequency isolated dc-dc converters with synchronous rectification for telecom and consumer use  lead-free d 2 pak irl7833s to-220ab irl7833 to-262 irl7833l v dss r ds(on) max qg 30v 3.8m 32nc absolute maximum ratings parameter units v ds drain-to-source voltage v v gs gate-to-source voltage i d @ t c = 25c continuous drain current, v gs @ 10v i d @ t c = 100c continuous drain current, v gs @ 10v a i dm pulsed drain current p d @t c = 25c maximum power dissipation  w p d @t c = 100c maximum power dissipation  linear derating factor w/c t j operating junction and c t stg storage temperature range mounting torque, 6-32 or m3 screw thermal resistance parameter typ. max. units r jc junction-to-case ??? 1.04 r cs case-to-sink, flat, greased surface  0.50 ??? c/w r ja junction-to-ambient  ??? 62 r ja junction-to-ambient (pcb mount)  ??? 40 max. 150  110  600 20 30 10 lbf  in (1.1n  m) -55 to + 175 140 0.96 72 

2 www.irf.com s d g static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units bv dss drain-to-source breakdown voltage 30 ??? ??? v ? v dss / ? t j breakdown voltage temp. coefficient ??? 18 ??? mv/c r ds(on) static drain-to-source on-resistance ??? 3.1 3.8 m ? ??? 3.7 4.5 v gs(th) gate threshold voltage 1.4 ??? 2.3 v ? v gs(th) / ? t j gate threshold voltage coefficient ??? -11 ??? mv/c i dss drain-to-source leakage current ??? ??? 1.0 a ??? ??? 150 i gss gate-to-source forward leakage ??? ??? 100 na gate-to-source reverse leakage ??? ??? -100 gfs forward transconductance 150 ??? ??? s q g total gate charge ??? 32 47 q gs1 pre-vth gate-to-source charge ??? 8.7 ??? q gs2 post-vth gate-to-source charge ??? 5.1 ??? nc q gd gate-to-drain charge ??? 13 ??? q godr gate charge overdrive ??? 5.3 ??? see fig. 16 q sw switch charge (q gs2 + q gd ) ??? 18 ??? q oss output charge ??? 22 ??? nc t d(on) turn-on delay time ??? 18 ??? t r rise time ??? 50 ??? ns t d(off) turn-off delay time ??? 21 ??? t f fall time ??? 6.9 ??? c iss input capacitance ??? 4170 ??? c oss output capacitance ??? 950 ??? pf c rss reverse transfer capacitance ??? 470 ??? avalanche characteristics parameter units e as single pulse avalanche energy  mj i ar avalanche current  a e ar repetitive avalanche energy  mj diode characteristics parameter min. typ. max. units i s continuous source current ??? ??? 150  (body diode) a i sm pulsed source current ??? ??? 600 (body diode)  v sd diode forward voltage ??? ??? 1.2 v t rr reverse recovery time ??? 42 63 ns q rr reverse recovery charge ??? 34 51 nc v gs = 20v v gs = -20v conditions 14 max. 560 30 ? = 1.0mhz conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 38a  v ds = v gs , i d = 250a v ds = 24v, v gs = 0v v ds = 24v, v gs = 0v, t j = 125c clamped inductive load v ds = 15v, i d = 30a v ds = 16v, v gs = 0v v dd = 15v, v gs = 4.5v  i d = 26a v ds = 16v t j = 25c, i f = 30a, v dd = 15v di/dt = 100a/s  t j = 25c, i s = 30a, v gs = 0v  showing the integral reverse p-n junction diode. mosfet symbol v gs = 4.5v, i d = 30a  ??? v gs = 4.5v typ. ??? ??? i d = 30a v gs = 0v v ds = 15v

www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 100 1000 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 2.7v 20s pulse width tj = 25c vgs top 10v 7.0v 4.5v 3.7v 3.5v 3.3v 3.0v bottom 2.7v 0.1 1 10 100 1000 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 2.7v 20s pulse width tj = 175c vgs top 10v 7.0v 4.5v 3.7v 3.5v 3.3v 3.0v bottom 2.7v -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 75a v gs = 10v 2.0 3.0 4.0 5.0 6.0 7.0 8.0 v gs , gate-to-source voltage (v) 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) t j = 25c t j = 175c v ds = 15v 20s pulse width

4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 v ds , drain-to-source voltage (v) 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v sd , source-to-drain voltage (v) 0.10 1.00 10.00 100.00 1000.00 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec 0 5 10 15 20 25 30 35 40 q g total gate charge (nc) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 24v v ds = 15v i d = 30a

www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10. threshold voltage vs. temperature 25 50 75 100 125 150 175 0 40 80 120 160 i , drain current (a) d limited by package    

  -75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 0.0 0.5 1.0 1.5 2.0 2.5 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)

6 www.irf.com d.u.t. v d s i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13. gate charge test circuit fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as fig 12c. maximum avalanche energy vs. drain current r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs 25 50 75 100 125 150 175 0 400 800 1200 1600 2000 e , single pulse avalanche energy (mj) as i d top bottom 12a 21a 30a fig 14a. switching time test circuit fig 14b. switching time waveforms v gs v ds 9 0% 10% t d(on) t d(off) t r t f v gs pulse width < 1s duty factor < 0.1% v dd v ds l d d.u.t + -

www.irf.com 7 fig 15. 
 



   for n-channel hexfet   power mosfets 
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    ?      ?            p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop r e-applied v oltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period    
  + - + + + - - -        ?   
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#  $$ ? !"!!%"     fig 16. gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr

8 www.irf.com control fet  

   

     
 
   
 
 
         
   
   
 
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    #' p loss = p conduction + p switching + p drive + p output this can be expanded and approximated by; p loss = i rms 2 r ds(on ) () + i q gd i g v in f ? ? ? ? ? ? + i q gs 2 i g v in f  ?   1  ?  + q g v g f () + q oss 2 v in f ? ? ? ? "     (
  

          
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 synchronous fet the power loss equation for q2 is approximated by; p loss = p conduction + p drive + p output * p loss = i rms 2 r ds(on) () + q g v g f () + q oss 2 v in f ? ? ? ? ? + q rr v in f *dissipated primarily in q1. for the synchronous mosfet q2, r ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. under light load the mosfet must still be turned on and off by the con- trol ic so the gate drive losses become much more significant. secondly, the output charge q oss and re- verse recovery charge q rr both generate losses that are transfered to q1 and increase the dissipation in that device. thirdly, gate charge will impact the mosfets? susceptibility to cdv/dt turn on. the drain of q2 is connected to the switching node of the converter and therefore sees transitions be- tween ground and v in . as q1 turns on and off there is a rate of change of drain voltage dv/dt which is ca- pacitively coupled to the gate of q2 and can induce a voltage spike on the gate that is sufficient to turn the mosfet on, resulting in shoot-through current . the ratio of q gd /q gs1 must be minimized to reduce the potential for cdv/dt turn on. power mosfet selection for non-isolated dc/dc converters figure a: q oss characteristic

www.irf.com 9 lead assignments 1 - gate 2 - drain 3 - source 4 - drain - b - 1.32 (.052) 1.22 (.048) 3x 0.55 (.022) 0.46 (.018) 2.92 (.115) 2.64 (.104) 4.69 (.185) 4.20 (.165) 3x 0.93 (.037) 0.69 (.027) 4.06 (.160) 3.55 (.140) 1.15 (.045) min 6.47 (.255) 6.10 (.240) 3.78 (.149) 3.54 (.139) - a - 10.54 (.415) 10.29 (.405) 2.87 (.113) 2.62 (.103) 15.24 (.600) 14.84 (.584) 14.09 (.555) 13.47 (.530) 3x 1.40 (.055) 1.15 (.045) 2.54 (.100) 2x 0.36 (.014) m b a m 4 1 2 3 n otes: 1 dimensioning & tolerancing per ansi y14.5m, 1982. 3 outline conforms to jedec outline to-220ab. 2 controlling dimension : inch 4 heatsink & lead measurements do no t include burrs . 

 
 

  dimensions are shown in millimeters (inches) example: in the assembly line "c" t his is an irf 1010 lot code 1789 as s e mb le d on ww 19, 1997 part numbe r as s e mb l y lot code dat e code year 7 = 1997 line c week 19 logo re ctifier int e rnat ional note: "p" in assembly line position indicates "lead-free"

10 www.irf.com  


 
  


  note: "p" in assembly line pos i ti on i ndi cates " l ead- f r ee" f 530s this is an irf530s with lot code 8024 as s e mble d on ww 02, 2000 in the assembly line "l" assembly lot code international rect ifier logo part numbe r dat e code year 0 = 2000 we e k 02 line l  f530s a = assembly site code we e k 0 2 p = designates lead-free product (optional) rectifier int ernat ional logo lot code assembly ye ar 0 = 2000 dat e code part number

www.irf.com 11 to-262 part marking information to-262 package outline assembly lot code rectifier int ernat ional as s e mble d on ww 19, 1997 note: "p" in as s embly line pos i ti on i ndi cates "l ead-f r ee" in the assembly line "c" logo t his is an irl3103l lot code 1789 example: line c dat e code week 19 ye ar 7 = 1997 part number part number logo lot code assembly int ernat ional rectifier product (optional) p = designates lead-free a = as s e mb l y s i t e code week 19 ye ar 7 = 1997 dat e code or

12 www.irf.com 
  repetitive rating; pulse width limited by max. junction temperature.   starting t j = 25c, l = 1.3mh, r g = 25 ? , i as = 30a.  pulse width 400s; duty cycle 2%.  calculated continuous current based on maximum allowable junction temperature. package limitation current is 75a.  when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994.  this is only applied to to-220ab package. data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 05/04 0       
 -  .  

 
 3 4 4 trr f eed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl f eed direction 10.90 (.429) 10.70 (.421) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 4.72 (.136) 4.52 (.178) 24.30 (.957 ) 23.90 (.941 ) 0.368 (.0145) 0.342 (.0135) 1.60 (.063) 1.50 (.059) 13.50 (.532) 12.80 (.504) 330.00 (14.173) max. 27.40 (1.079) 23.90 (.941) 60.00 (2.362 ) min. 30.40 (1.197) max. 26.40 (1.039) 24.40 (.961) notes : 1. comforms to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge. to-220ab package isnot recommended for surface mount application.
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: international rectifier: ? irl7833pbf? IRL7833SPBF? irl7833strlpbf


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