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fedl9460-01 issue date: jan 29, 2009 ML9460 common driver for dot matrix stn liquid crystal display 1/27 1. product overview 1.1 general description the ML9460 is a 240-output common driver for driving a dot matrix lcd panel. it enables switching between 240 outputs and 200 outputs and 160 outputs and 120 outputs. the ML9460 is used in combination with the segment driver ml9461b. 1.2 features ? 240-channel common driver ? display duty: up to 1/240 ? lcd drive voltage: 43 v max. ? operating voltage: 2.5 to 5.5 v ? intermediate voltage interface ? built-in alternating signal generation circuit; pin programmable ? built-in display off control circuit ? can switch output modes: 240-output mode/200-output mode/160-output mode/120-output mode ? clock cycle time: 245 ns min. @ 4.5 v 330 ns @ 2.5 v ? package au bump chip product name: ML9460cvwa tcp product name: ML9460advva
fedl9460-01 lapis semiconductor ML9460 2/27 2. pin description 2.1 pin description pin name i/o polarity descripiton initial value handling when not used attribute remarks vdd ? ? logic power supply pin ? ? power vss ? ? logic power supply pin ? ? vss v2l v2r ? ? power supply pins for liquid crystal drive level output. selective level. ? ? power v2l and v2r are connected internally with each other. mv2l mv2r ? ? power supply pins for liquid crystal drive level output. selective level. ? ? power mv2l and mv2r are connected internally with each other. vcl vcr ? ? power supply pins for liquid crystal drive level output. nonselective level. ? ? power vcl and vcr are connected internally with each other. yscl i ? shift clock input pin. data is shifted in on the falling edge of the shift clock yscl of the shift register. low ? clk fr i/o ? input-output pin for alternating signal for liquid crystal drive output low ? digital see sections 4.1.1, ?liquid crystal drive circuit,? and 4.2.1, ?timing of connection with the segment driver.? frws0 frws1 frws2 frws3 frws4 i ? alternating signal (fr signal) period setting pins. specify the number of lines with an integer from 2 to 31. for operation using an external alternating signal, set the number of lines to 0. tied high or low ? digital see sections 4.1.4, ?alternating signal generation circuit.? sel1 sel2 i ? liquid crystal drive output pin switching pins tied high or low ? digital see sections 4.1.1, ?liquid crystal drive circuit,? and 4.1.3, ?bidirectional shift register.? dio1 dio2 i/o ? serial i/o (shift register data input-output) pins tied high or low ? digital see section 4.1.3, ?bidirectional shift register.? frres i negative pin for initializing the counter for the alternating signal generation circuit. setting this pin to ?l? level sets initializes the altemating signal(fr signal) circuit. a ?h? level frres is normally used. low ? digital dspof i negative a ?l? level on this pin sets each of the liquid crystal drive outputs o1?o240 to the vc level. no internal register will be cleared. low ? digital dspms i ? pin for selecting the method of processing the dspof signal internally tied high or low ? digital see section 4.1.5, ?control circuit.?
fedl9460-01 lapis semiconductor ML9460 3/27 pin name i/o polarity descripiton initial value handling when not used attribute remarks doc o negative dispoff signal output pin low ? digital see sections 4.1.5, ?control circuit,? and 4.2.3, ? doc signal waveforms.? shl i ? shift direction switching pin. switches the shift direction of the shift register. tied high or low ? digital see section 4.1.3, ?bidirectional shift register.? o1 to o240 o ? liquid crystal drive output pins. when the vdd voltage is input to the dspof pin, one of the three levels (v2, mv2, vc) is selected and output according to the combination of the fr signal and display data. ? pins that are made disabled by the sel1 and sel2 pins will output the nonselective level signal (vc). analog see section 4.1.1, ?liquid crystal drive circuit.? note: in the initial value column, - a dash ??? for an input pin indicates that the initial value is don?t care. - a dash ??? for an output pin indicates that the initial value is undefined.
fedl9460-01 lapis semiconductor ML9460 4/27 2.2 inupt and output configuration vdd vss vss vdd vdd vss vdd vss vdd vss vdd vdd vss vss v2 mv2 v2 mv2 vc applicable to pins yscl, frws0 4,sel1,sel2, frres, dspof ,dspms, and shl. applicable to pins fr,dio1,and dio2. applicable to pins doc . applicable to pins o1 240.
fedl9460-01 lapis semiconductor ML9460 5/27 3. block diagram level shifter x1?x240 bidirectional shift register v2r vcr liquid crystal drive circuit v2l mv2l vcl vdd vss o1?o240 f r frws0 frws1 frws2 frws3 frws4 frre s alternating signal generation circuit dio2 shl sel1 sel2 dspms dspo f dio1 do c yscl control circuit x1 x2 ? ? x239 x240 o1 o2 ? ? o239 o240 mv2r
fedl9460-01 lapis semiconductor ML9460 6/27 4. functional description 4.1 internal blocks 4.1.1 liquid crystal drive circuit the liquid crystal drive circuit outputs three levels for liquid crystal drive. one of the three liquid crystal drive levels (v2, mv2, vc) is selected and output according to the combination of data stored n the shift register circuit and fr, as shown below. fr display data dspof output level * * "l" vc "l" "l" "h" vc "l" "h" "h" v2 "h" "l" "h" vc "h" "h" "h" mv2 *: don't care the number of output pins is set by the sel1 and sel2 settings, as shown below. sel1 sel2 number of output pins "h" "h" 240 outputs (o1, o2, o3, ? , o239, o240) "h" "l" 200 outputs (o21, o22, o23, ? , o219, o220) "l" "h" 160 outputs (o41, o42, o43, ? , o199, o200) "l" "l" 120 outputs (o61, o62, o63, ? , o179, o180) pins that are made disabled by the sel1 and sel2 pins will output the nonselective level signal (vc) synchronized with the fr signal. 4.1.2 level shifter t he level shifter converts 5 v signals to high-voltage signals used for liquid crystal drive by multiplying the voltage. 4.1.3 bidirectional shift register t he device is equipped with a 240-bit bidirectional shift register, where the first line signals that are input from the dio1 and dio2 pins are shifted sequentially. the shift direction is deterrmined by the shl pin setting. relationship between shl, dio1, and dio2 shl dio1 dio2 "h" serial output serial input "l" serial input serial output
fedl9460-01 lapis semiconductor ML9460 7/27 relationship between sel1/sel2 and shift direction shl sel1 sel2 shift direction "h" "h" dio2 ?x1 ??? x240 ? dio1 "h" "l" dio2 ? x21 ??? x220 ? dio1 "l" "h" dio2 ? x41 ??? x200 ? dio1 "h" "l" "l" dio2 ? x61 ??? x180 ? dio1 "h" "h" dio1 ? x240 ???x1 ? dio2 "h" "l" dio1 ? x220 ??? x21 ? dio2 "l" "h" dio1 ? x200 ??? x41 ? dio2 "l" "l" "l" dio1 ? x180 ??? x61 ? dio2 4.1.4 alternating signal generation circuit t he alternating signal generation circuit generates the a lternation signal fro liquid crystal display (fr signal). alternating is enabled by setting each pin from frws0 to frws4 to vdd or vss. when inputting alternating signals externally, alternating is enabled by setting all the pins from frws0 to frws4 to vss. number of lines frws4 frws3 frws2 frws1 frws0 line alternating waveform fr pin status remarks 0 0 0 0 0 0 ? input 1 0 0 0 0 1 1 line alternated (*1) 2 0 0 0 1 0 2 lines alternated 3 0 0 0 1 1 3 lines alternated ~ ~ ~ ~ ~ ~ ~ 31 1 1 1 1 1 31 lines alternated output *1: this setting is prohitited. 4.1.5 control circuit b ased on the dspms pin status, the control circuit processes the dspof signal internally and outputs the generated signal to the doc signal. dspms dspof signal and internal processing "h" the liquid crystal output is set to the vc level during the ?l? period of the dspof signal. "l" holds the liquid crystal output at the vc level until 16 frames of data are input to dio1 and dio2 after a level change from "l" ? "h" on the dspof signal. dspms doc outputs "l" while the dspof signal is at ?l?. "h" outputs "h" while the dspof signal is at ?h?. "l" even if the dspof signal level changes from "l" ? "h", a "l" level is output until 16 frames of data are input to dio1 and dio2.
fedl9460-01 lapis semiconductor ML9460 8/27 4.2 timing diagram 4.2.1 timing of connection with the segment driver input signal fr is latched at the rise of input signal yscl and is propagated to the liquid crystal drive circuit at the next fall of yscl. the data signal that is input from the dio1 and dio2 pins is latched at the fall of the yscl signal and propagated to the liquid crystal drive circuit. the liquid crystal drive signal level (v2, mc, mv2) is determined by the operation between the fr signal propagated to the liquid crystal drive circuit and the data signal. when using output of the fr signal through the fr signal generation circuit, connect the fr signal to the fr pin of the ml9461b directly. the fr signal inside of the lsi is processed by delaying it by two yscl signals for the fr signal output from the common driver. timing diagram when the fr pin is configured as input yscl data d1 d2 d3 fr m1 m2 m3 data d1 d2 d3 fr m1 m2 m3 operation between d1 and m1 operation between d2 and m2 operation between d3 and m3 timing diagram when the fr pin is configured as output yscl data d1 d2 d3 fr m1 m2 m3 data d1 d2 d3 fr m1 m2 m3 operation between d1 and m1 operation between d2 and m2 operation between d3 and m3 input signal o1 ? o240 pin outputs li qu id crysta l d r i ve circuit (lsi internal signal) input signal o1 ? o240 pin outputs output signal li qu id crysta l d r i ve circuit (lsi internal signal)
fedl9460-01 lapis semiconductor ML9460 9/27 4.2.2 driver output waveform common voltage peirod of normal display dispoff period v2 (21.75 v) vdd (3.3 v) vc (1.75 v) vss (0.0 v) mv2 (?18.25 v) 4.2.3 doc si gnal waveforms when dspms = ?h? dspof doc when dspms = ?l? dspof 1 2 3 4 14 15 16 dio1, dio2 doc
fedl9460-01 lapis semiconductor ML9460 10/27 4.2.4 timing waveforms of ac characteristics yscl dio1 dio2 (during input) dio1 dio2 (during output) fr (during output) o1?o240 yscl fr (during input) t f v dd ? 0.7 v dd ? 0.3 t cwl t cwh t cyc t r t ds t dh v dd ? 0.7 v dd ? 0.3 v oh v ol t dd t fpd v oh v ol 0.8 ? v 2 t pd v dd ? 0.7 v dd ? 0.3 t frs t frh v dd ? 0.7 v dd ? 0.7 v dd ? 0.3 v dd ? 0.3 0.2 ? v 2 0.2 ? v mv2 0.8 ? v mv2
fedl9460-01 lapis semiconductor ML9460 11/27 dspof dio1 dio2 (during input) doc o1?o240 (dspms=h) o1?o240 (dspms=l) frres t doc1 t doc2 v dd ? 0.3 v dd ? 0.7 v dd ? 0.3 t disp v dd ? 0.3 t frres v dd ? 0.3 0.2 ? v 2 0.2 ? v mv2 t p doff1 0.8 ? v 2 0.8 ? v mv2 t pdon1 0.2 ? v 2 0.2 ? v mv2 t pdoff2 0.8 ? v 2 0.8 ? v mv2 t pdon2 v dd ? 0.7 v dd ? 0.3
fedl9460-01 lapis semiconductor ML9460 12/27 4.2.5 alternating waveforms s el1="h", sel2="h"(240output), shl="h", fr signal internal generation, 3 lines inverted yscl dio2(input) fr(output) 2 clock delay fr(internal) dspof shift register q1 q2 q3 q240 dio1(output) o1 o2 o3 o4 o240 v2 vc mv2 1frame (240lines) 240lines v2 vc mv2 v2 vc mv2 v2 vc mv2 v2 vc mv2
fedl9460-01 lapis semiconductor ML9460 13/27 sel1="h", sel2="h"(240output), shl="h", fr signal internal generation, 3 lines inverted yscl dio2(input) fr(output) fr(latch) 2 clock delay fr(internal) dspof shift register q1 q2 q3 q240 dio1(output) o1 o2 o3 o4 o240 v2 vc mv2 1frame (240lines) 240lines v2 vc mv2 v2 vc mv2 v2 vc mv2 v2 vc mv2
fedl9460-01 lapis semiconductor ML9460 14/27 5. power supply system 5.1 power supply group level shifter x1?x240 bidirectional shift register liquid crystal drive circuit o1?o240 alternating signal generation circuit control circuit x1 x2 ? ? x239 x240 o1 o2 ? ? o239 o240 v2l vcl mv2l mv2r vcr v2r vdd vss this lsi does completely separate liquid crystal drive voltage and operating voltage on its circuit architecture. please do an anti-noise measure on a panel so that anoise liquid crystal drive voltage does not round it in operating voltage.
fedl9460-01 lapis semiconductor ML9460 15/27 5.2 power-on/shutdown sequence 5.2.1 power-on sequence 1. apply power to (1)vss?vdd, (2)vss?v2, (3)vc, and (4)mv2 in this order. then, input the vss potential to the dspof pin. 2. the o1?o240 pins forcibly outputs the vc level by the dispoff function. 3. even if an input signal is disturbed immediately after vdd is applied, priority is given to the dispoff function. 4. input the predetermined signal(s) to initialize the registers in the driver. in this case, take at least one frame for the initialization period. 5. input the vdd voltage to the dspof pin to release the dispoff function. at this point, the levels of the mv2, v2, and vc pin must have reached their respective predetermined potentials. 5.2.2 shutdown sequence 1. t he dspof pin must remain set to the vss potential. 2. shut down the power supplies for liquid crystal in the order of (1)vss?v2, (2)vc, and (3)mv2. 3. reduce the voltage of vdd and the levels of the input signals to the vss potential. at this point, the v2 and vc pin must completely drop to 3 v or lower. vdd v2 vc mv2 dspof input signal, clock, data, etc. signal uncertain period initialization period (1 frame or more) "v2" "vc" "vc" "vc" "vc" "vc" o1?o240 "mv2" ? 0 ms ? 0 ms ? 0 ms ? 0ms 2.5v ? 0 ms ? 0 ms 2.5v 0 v 0 v 0 v 0 v 0 v 0 v ? 0 ms 0 v
fedl9460-01 lapis semiconductor ML9460 16/27 6. electrical specifications 6.1 absolute maximum ratings v ss = 0v parameter symbol condition rating unit applicable pins logic circuit v dd tj = ?30c to +75c ?0.3 to +7.0 v vdd v 2 tj = ?30c to +75c ?0.3 to +25.0 v v2l, v2r v mv2 tj = ?30c to +75c ?22.5 to +0.3 v mv2l, mv2r power supply voltage liquid crystal drive circuit v m -v mv2 tj = ?30c to +75c ?0.3 to +45.0 v v2l,v2r,mv2l, mv2r input voltage (1) v t1 tj = ?30c to +75c ?0.3 to v dd +0.3 v dio1, dspof , shl, fr, frws0, frws1, frws2, frws3, frws4, frres , sel1, sel2, yscl, dspms, dio2 input voltage (2) v 2 tj = ?30c to +75c ?0.3 to +25.0 v v2l, v2r input voltage (3) v mv2 tj = ?30c to +75c ?22.5 to +0.3 v mv2l, mv2r input voltage (4) v c tj = ?30c to +75c ?0.3 to +5.0 v vcl, vcr output current/ output short-circuit current i o tj = ?30c to +75c 10 ma fr, dio1, dio2, doc , o1?o240 junction temperature tj ? ?55 to +110 c ? storate temperature range t stg ? ?55 to +110 c ?
fedl9460-01 lapis semiconductor ML9460 17/27 6.2 recommended operating conditions (guaranteed operating range) v ss = 0v, v 2 ? v mv2 = 15 to 43v, tj = ? 30 to +75c range parameter symbol condition min. typ. max. unit applicable pins logic circuit v dd ? 2.5 ? 5.5 v vdd v 2 ? 8.8 ? 24 v v2l, v2r power supply voltage liquid crystal drive circuit v mv2 ? ?21.5 ? ?4 v mv2l, mv2r ?h? input voltage v ih ? 0.7 ? v dd ? v dd v ?l? input voltage v il ? 0 ? 0.3 ? v dd v dio1, dspof , shl, fr, dspms, frws0, frws1, frws2, frws3, frws4, frres , yscl, sel1, sel2, doc , dio2 liquid crystal drive input voltage (1) v 2 ? 8.8 ? 24 v v2l, v2r liquid crystal drive input voltage (2) v mv2 ? ?21.5 ? ?4 v mv2l, mv2r liquid crystal drive input voltage (3) v c ? 0 ? 3.5 v vcl, vcr v dd =5v (*1) ? 4 mhz yscl operating frequency f ck v dd =3v (*1) ? 3 mhz yscl operating temperature (tj) topr ? ?30 ? 75 c ? load condition 1 c l1 ? ? ? 30 pf dio1, dio2 load condition 2 c l2 ? ? ? 100 pf doc , o1?o240 input rise waveform t r ? ? ? 30 ns yscl input fall waveform t f ? ? ? 30 ns yscl clock ?high? period t cwh ? 20 ? ? ns yscl clock ?low? period t cwl ? 250 ? ? ns yscl data setup time t ds ? 70 ? ? ns dio1, dio2, yscl data hold time t dh ? 10 ? ? ns dio1, dio2, yscl fr setup time t frs ? 20 ? ? ns fr, yscl fr hold time t frh ? 20 ? ? ns fr, yscl ??? indicates that no particular value is specified. *1: 5khz is specified for the test condition. note: insert bypass capacitors by referring to the application circuit described later so that power supplies will be stabilized. it is recommended that 0.1 ? f ca capacitors (jis (japanese industrial standards) fj(f) equivalent) be used.
fedl9460-01 lapis semiconductor ML9460 18/27 6.3 dc characteristics v dd = 2.5 to 5.5v, v ss = 0v, v 2 ? v mv2 = 15 to 43v, tj = ?30 to +75c no. parameter symbol condition min. typ. max. unit applicable pins 1 ?h? level input voltage v ih ? v dd ? 0.7 ? v dd v 2 ?l? level input voltage v il ? 0 ? v dd ? 0.3 v dio1, dspof , shl, fr, dspms, frws0, frws1, frws2, frws3, frws4, frres , yscl, sel1, sel2, dio2 3 ?h? level output voltage v oh i oh = ? 0.4ma v dd ? 0.4 ? ? v 4 ?l? level output voltage v ol i ol = 0.4ma ? ? 0.4 v fr, dio1, dio2, doc 5 supply current (1) i cc1 v dd = 3.3v v 2 ? v mv2 = 40v fyscl = 19.2khz f fr = 1.5khz 240-output mode ta = 25c no load ? 10 40 ? a vdd 6 supply current (2) i cc2 v dd = 5.0v v 2 ? v mv2 = 40v f yscl = 19.2khz f fr = 1.5khz 240-output mode ta = 25c no load ? 20 50 ? a vdd 7 supply current (3) i cc3 v dd = 3.3v v 2 ? v mv2 = 40v f yscl = 19.2khz f fr = 1.5khz 240-output mode ta = 25c no load ? 25 50 ? a v2 8 static supply current i dds ta = 25c ? ? 10 ? a vdd 9 input leakage current 1 i il1 v in = v dd to v ss ?5 ? 5 ? a dio1, dspof , shl, fr, dspms, frws0, frws1, frws2, frws3, frws4, frres , yscl, sel1, sel2, dio2 10 input leakage current 2 i il2 ? ?25 ? 25 ? a vcl, vcr ? von = 0.5v v 2 = 21.75v v mv2 = ?18.25v v c = 1.75v ? 0.7 2.0 k ? o1?o240 11 on resistance between vi and oj r on ? von = 0.5v v 2 = 11.75v v mv2 = ?8.25v v c = 1.75v ? 1.2 3.3 k ? o1?o240 values in the typ. column are for reference only. ??? indicates that no particular value is specified.
fedl9460-01 lapis semiconductor ML9460 19/27 6.4 ac characteristics 6.4.1 ac characteristics 1 v dd = 2.5 to 4.5v, v ss = 0v, v 2 = 21.5v, v c = 0v, v mv2 =-21.5v, tj = ?30 to +75c no. parameter symbol condition min. typ. max. unit applicable pins 1 clock cycle time t cyc ? 330 ? ? ns yscl 2 yscl ?h? level width t cwh ? 20 ? ? ns yscl 3 yscl ?l? level width t cwl ? 250 ? ? ns yscl 4 yscl rise time t r ? ? ? 30 ns yscl 5 yscl fall time t f ? ? ? 30 ns yscl 6 data setup time t ds ? 70 ? ? ns dio1, dio2, yscl 7 data hold time t dh ? 10 ? ? ns dio1, dio2, yscl 8 data output delay time t dd (*1) ? ? 200 ns dio1, dio2, yscl 9 fr output delay time t frd (*1) ? ? 140 ns fr, yscl 10 fr setup time t frs ? 20 ? ? ns fr, yscl 11 fr hold time t frh ? 20 ? ? ns fr, yscl dspms = h (*2) ? ? 200 ns dspof , doc 12 doc output delay time 1 t doc1 dspms = l (*2) ? ? 1500 ns dspof , doc 13 doc output delay time 2 t doc2 (*2) ? ? 300 ns dio1, dio2, doc t pdff1 dspms = h (*2) ? ? 1200 ns dspof , o1 to o240 14 common output delay time from dspof fall t pdoff2 dspms = l (*2) ? ? 2500 ns dspof , o1 to o240 15 common output delay time from dspof rise t pdon1 dspms = h (*2) ? ? 1200 ns dspof , o1 to o240 16 common output delay time from dio fall t pdon2 dspms = l (*2) ? ? 1200 ns dio1, dio2, o1 to o240 17 dspof ?l? level width (*3) t disp dspms = l 100 ? ? ns dspof 18 frres ?l? level width (*3) t frres ? 100 ? ? ns frres values in the typ. column are for reference only. ??? indicates that no particular value is specified.
fedl9460-01 lapis semiconductor ML9460 20/27 v dd = 4.5 to 5.5v, v ss = 0v, v 2 = 21.5v, v c = 0v, v mv2 =-21.5v, tj = ?30 to +75c no. parameter symbol condition min. typ. max. unit applicable pins 1 clock cycle time t cyc ? 245 ? ? ns yscl 2 yscl ?h? level width t cwh ? 15 ? ? ns yscl 3 yscl ?l? level width t cwl ? 170 ? ? ns yscl 4 yscl rise time t r ? ? ? 30 ns yscl 5 yscl fall time t f ? ? ? 30 ns yscl 6 data setup time t ds ? 50 ? ? ns dio1, dio2, yscl 7 data hold time t dh ? 10 ? ? ns dio1, dio2, yscl 8 data output delay time t dd (*1) ? ? 150 ns dio1, dio2, yscl 9 fr output delay time t frd (*1) ? ? 100 ns fr, yscl 10 fr setup time t frs ? 15 ? ? ns fr, yscl 11 fr hold time t frh ? 15 ? ? ns fr, yscl dspms = h (*2) ? ? 140 ns dspof , doc 12 doc output delay time 1 t doc1 dspms = l (*2) ? ? 1000 ns dspof , doc 13 doc output delay time 2 t doc2 (*2) ? ? 200 ns dio1, dio2, doc t pdoff1 dspms = h (*2) ? ? 700 ns dspof , o1 to o240 14 common output delay time from dspof fall t pdoff2 dspms = l (*2) ? ? 2000 ns dspof , o1 to o240 15 common output delay time from dspof rise t pdon1 dspms = h (*2) ? ? 700 ns dspof , o1 to o240 16 common output delay time from dio fall t pdon2 dspms = l (*2) ? ? 700 ns dio1, dio2, o1 to o240 17 dspof ?l? level width(*3) t disp dspms = l 100 ? ? ns dspof 18 frres ?l? level width(*3) t frres ? 100 ? ? ns frres values in the typ. column are for reference only. ??? indicates that no particular value is specified.
fedl9460-01 lapis semiconductor ML9460 21/27 6.4.2 ac characteristics 2 v dd = 2.5 to 4.5v, v ss = 0v, v 2 = 21.5v, v c = 0v, v mv2 =-21.5v, tj = ?30 to +75c no. parameter symbol condition min. typ. max. unit applicable pins 1 output delay time t pd (*2) ? ? 1.2 ? s o1?o240, fr ??? indicates that no particular value is specified. 6.4.3 ac characteristics 3 v dd = 4.5 to 5.5v, v ss = 0v, v 2 = 21.5v, v c = 0v, v mv2 =-21.5v, tj = ?30 to +75c no. parameter symbol condition min. typ. max. unit applicable pins 1 output delay time t pd (*2) ? ? 0.7 ? s o1?o240, fr ??? indicates that no particular value is specified. *1: load condition *2: load condition *3: if any signal whose pulse width is shorter than this value, the device may not operate normally. 30 pf 100 p f
fedl9460-01 lapis semiconductor ML9460 22/27 7. pad configuration 7.1 pad coordinates (au bump chip: ML9460cvwa) no. pad name x-coordinate y-coordinate no. pad name x-coordinate y-coordinate no. pad name x-coordinate y-coordinate no. pad name x-coordinate y-coordinate [ ? m] [ ? m] [ ? m] [ ? m] [ ? m] [ ? m] [ ? m] [ ? m] 1 dummy -5936 -604.2 81 dummy 3406.8 -604.2 161 o186 3275 606.3 241 o106 -725 606.3 2 dummy -5870 -604.2 82 dummy 3472.8 -604.2 162 o185 3225 606.3 242 o105 -775 606.3 3 v2l -5804 -604.2 83 dummy 3538.8 -604.2 163 o184 3175 606.3 243 o104 -825 606.3 4 v2l -5738 -604.2 84 yscl 3779 -604.2 164 o183 3125 606.3 244 o103 -875 606.3 5 v2l -5672 -604.2 85 yscl 3845 -604.2 165 o182 3075 606.3 245 o102 -925 606.3 6 vcl -5539.4 -604.2 86 dspms 4141.6 -604.2 166 o181 3025 606.3 246 o101 -975 606.3 7 vcl -5473.4 -604.2 87 dspms 4207.6 -604.2 167 o180 2975 606.3 247 o100 -1025 606.3 8 vcl -5407.4 -604.2 88 dummy 4447.8 -604.2 168 o179 2925 606.3 248 o99 -1075 606.3 9 mv2l -5320.1 -604.2 89 dummy 4513.8 -604.2 169 o178 2875 606.3 249 o98 -1125 606.3 10 mv2l -5254.1 -604.2 90 dio1 4871 -604.2 170 o177 2825 606.3 250 o97 -1175 606.3 11 mv2l -5188.1 -604.2 91 dio1 4937 -604.2 171 o176 2775 606.3 251 o96 -1225 606.3 12 dio2 -5017.1 -604.2 92 dummy 5108 -604.2 172 o175 2725 606.3 252 o95 -1275 606.3 13 dio2 -4951.1 -604.2 93 dummy 5174 -604.2 173 o174 2675 606.3 253 o94 -1325 606.3 14 fr -4543.2 -604.2 94 mv2r 5240 -604.2 174 o173 2625 606.3 254 o93 -1375 606.3 15 fr -4477.2 -604.2 95 mv2r 5306 -604.2 175 o172 2575 606.3 255 o92 -1425 606.3 16 dummy -4306.2 -604.2 96 mv2r 5372 -604.2 176 o171 2525 606.3 256 o91 -1475 606.3 17 dummy -4240.2 -604.2 97 vcr 5459.3 -604.2 177 o170 2475 606.3 257 o90 -1525 606.3 18 dummy -4174.2 -604.2 98 vcr 5525.3 -604.2 178 o169 2425 606.3 258 o89 -1575 606.3 19 dummy -4108.2 -604.2 99 vcr 5591.3 -604.2 179 o168 2375 606.3 259 o88 -1625 606.3 20 dummy -4042.2 -604.2 100 v2r 5723.9 -604.2 180 o167 2325 606.3 260 o87 -1675 606.3 21 dummy -3976.2 -604.2 101 v2r 5789.9 -604.2 181 o166 2275 606.3 261 o86 -1725 606.3 22 frres -3784.4 -604.2 102 v2r 5855.9 -604.2 182 o165 2225 606.3 262 o85 -1775 606.3 23 frres -3718.4 -604.2 103 dummy 5921.9 -604.2 183 o164 2175 606.3 263 o84 -1825 606.3 24 frws4 -3310.5 -604.2 104 dummy 5987.9 -604.2 184 o163 2125 606.3 264 o83 -1875 606.3 25 frws4 -3244.5 -604.2 105 dummy 6075.1 606.3 185 o162 2075 606.3 265 o82 -1925 606.3 26 dummy -3052.7 -604.2 106 dummy 6025.1 606.3 186 o161 2025 606.3 266 o81 -1975 606.3 27 dummy -2986.7 -604.2 107 o240 5975 606.3 187 o160 1975 606.3 267 o80 -2025 606.3 28 dummy -2920.7 -604.2 108 o239 5925 606.3 188 o159 1925 606.3 268 o79 -2075 606.3 29 dummy -2854.7 -604.2 109 o238 5875 606.3 189 o158 1875 606.3 269 o78 -2125 606.3 30 frws3 -2663 -604.2 110 o237 5825 606.3 190 o157 1825 606.3 270 o77 -2175 606.3 31 frws3 -2597 -604.2 111 o236 5775 606.3 191 o156 1775 606.3 271 o76 -2225 606.3 32 frws2 -2189.1 -604.2 112 o235 5725 606.3 192 o155 1725 606.3 272 o75 -2275 606.3 33 frws2 -2123.1 -604.2 113 o234 5675 606.3 193 o154 1675 606.3 273 o74 -2325 606.3 34 dummy -1931.3 -604.2 114 o233 5625 606.3 194 o153 1625 606.3 274 o73 -2375 606.3 35 dummy -1865.3 -604.2 115 o232 5575 606.3 195 o152 1575 606.3 275 o72 -2425 606.3 36 dummy -1799.3 -604.2 116 o231 5525 606.3 196 o151 1525 606.3 276 o71 -2475 606.3 37 dummy -1733.3 -604.2 117 o230 5475 606.3 197 o150 1475 606.3 277 o70 -2525 606.3 38 dummy -1667.3 -604.2 118 o229 5425 606.3 198 o149 1425 606.3 278 o69 -2575 606.3 39 dummy -1601.3 -604.2 119 o228 5375 606.3 199 o148 1375 606.3 279 o68 -2625 606.3 40 frws1 -1409.4 -604.2 120 o227 5325 606.3 200 o147 1325 606.3 280 o67 -2675 606.3 41 frws1 -1343.4 -604.2 121 o226 5275 606.3 201 o146 1275 606.3 281 o66 -2725 606.3 42 frws0 -935.6 -604.2 122 o225 5225 606.3 202 o145 1225 606.3 282 o65 -2775 606.3 43 frws0 -869.6 -604.2 123 o224 5175 606.3 203 o144 1175 606.3 283 o64 -2825 606.3 44 dummy -677.7 -604.2 124 o223 5125 606.3 204 o143 1125 606.3 284 o63 -2875 606.3 45 dummy -611.7 -604.2 125 o222 5075 606.3 205 o142 1075 606.3 285 o62 -2925 606.3 46 dummy -545.7 -604.2 126 o221 5025 606.3 206 o141 1025 606.3 286 o61 -2975 606.3 47 dummy -479.7 -604.2 127 o220 4975 606.3 207 o140 975 606.3 287 o60 -3025 606.3 48 dummy -413.7 -604.2 128 o219 4925 606.3 208 o139 925 606.3 288 o59 -3075 606.3 49 dummy -347.7 -604.2 129 o218 4875 606.3 209 o138 875 606.3 289 o58 -3125 606.3 50 vdd -281.7 -604.2 130 o217 4825 606.3 210 o137 825 606.3 290 o57 -3175 606.3 51 vdd -215.7 -604.2 131 o216 4775 606.3 211 o136 775 606.3 291 o56 -3225 606.3 52 vdd -149.7 -604.2 132 o215 4725 606.3 212 o135 725 606.3 292 o55 -3275 606.3 53 sel2 352.6 -604.2 133 o214 4675 606.3 213 o134 675 606.3 293 o54 -3325 606.3 54 sel2 418.6 -604.2 134 o213 4625 606.3 214 o133 625 606.3 294 o53 -3375 606.3 55 sel1 715.1 -604.2 135 o212 4575 606.3 215 o132 575 606.3 295 o52 -3425 606.3 56 sel1 781.1 -604.2 136 o211 4525 606.3 216 o131 525 606.3 296 o51 -3475 606.3 57 doc 1138.2 -604.2 137 o210 4475 606.3 217 o130 475 606.3 297 o50 -3525 606.3 58 doc 1204.2 -604.2 138 o209 4425 606.3 218 o129 425 606.3 298 o49 -3575 606.3 59 dummy 1375.8 -604.2 139 o208 4375 606.3 219 o128 375 606.3 299 o48 -3625 606.3 60 dummy 1441.8 -604.2 140 o207 4325 606.3 220 o127 325 606.3 300 o47 -3675 606.3 61 dummy 1507.8 -604.2 141 o206 4275 606.3 221 o126 275 606.3 301 o46 -3725 606.3 62 dummy 1573.8 -604.2 142 o205 4225 606.3 222 o125 225 606.3 302 o45 -3775 606.3 63 dummy 1639.8 -604.2 143 o204 4175 606.3 223 o124 175 606.3 303 o44 -3825 606.3 64 dummy 1705.8 -604.2 144 o203 4125 606.3 224 o123 125 606.3 304 o43 -3875 606.3 65 dummy 1771.8 -604.2 145 o202 4075 606.3 225 o122 75 606.3 305 o42 -3925 606.3 66 dummy 1837.8 -604.2 146 o201 4025 606.3 226 o121 25 606.3 306 o41 -3975 606.3 67 dspof 2078 -604.2 147 o200 3975 606.3 227 o120 -25 606.3 307 o40 -4025 606.3 68 dspof 2144 -604.2 148 o199 3925 606.3 228 o119 -75 606.3 308 o39 -4075 606.3 69 shl 2440.6 -604.2 149 o198 3875 606.3 229 o118 -125 606.3 309 o38 -4125 606.3 70 shl 2506.6 -604.2 150 o197 3825 606.3 230 o117 -175 606.3 310 o37 -4175 606.3 71 dummy 2746.8 -604.2 151 o196 3775 606.3 231 o116 -225 606.3 311 o36 -4225 606.3 72 dummy 2812.8 -604.2 152 o195 3725 606.3 232 o115 -275 606.3 312 o35 -4275 606.3 73 vss 2878.8 -604.2 153 o194 3675 606.3 233 o114 -325 606.3 313 o34 -4325 606.3 74 vss 2944.8 -604.2 154 o193 3625 606.3 234 o113 -375 606.3 314 o33 -4375 606.3 75 vss 3010.8 -604.2 155 o192 3575 606.3 235 o112 -425 606.3 315 o32 -4425 606.3 76 dummy 3076.8 -604.2 156 o191 3525 606.3 236 o111 -475 606.3 316 o31 -4475 606.3 77 dummy 3142.8 -604.2 157 o190 3475 606.3 237 o110 -525 606.3 317 o30 -4525 606.3 78 dummy 3208.8 -604.2 158 o189 3425 606.3 238 o109 -575 606.3 318 o29 -4575 606.3 79 dummy 3274.8 -604.2 159 o188 3375 606.3 239 o108 -625 606.3 319 o28 -4625 606.3 80 dummy 3340.8 -604.2 160 o187 3325 606.3 240 o107 -675 606.3 320 o27 -4675 606.3 note: leave dummy pads open.
fedl9460-01 lapis semiconductor ML9460 23/27 no. pad name x-coordinate y-coordinate no. pad name x-coordinate y-coordinate no. pad name x-coordinate y-coordinate [ ? m] [ ? m] [ ? m] [ ? m] [ ? m] [ ? m] 321 o26 -4725 606.3 331 o16 -5225 606.3 341 o6 -5725 606.3 322 o25 -4775 606.3 332 o15 -5275 606.3 342 o5 -5775 606.3 323 o24 -4825 606.3 333 o14 -5325 606.3 343 o4 -5825 606.3 324 o23 -4875 606.3 334 o13 -5375 606.3 344 o3 -5875 606.3 325 o22 -4925 606.3 335 o12 -5425 606.3 345 o2 -5925 606.3 326 o21 -4975 606.3 336 o11 -5475 606.3 346 o1 -5975 606.3 327 o20 -5025 606.3 337 o10 -5525 606.3 347 dummy -6025 606.3 328 o19 -5075 606.3 338 o9 -5575 606.3 348 dummy -6075 606.3 329 o18 -5125 606.3 339 o8 -5625 606.3 330 o17 -5175 606.3 340 o7 -5675 606.3 note: leave dummy pads open. b b b=45.0 fedl9460-01 lapis semiconductor ML9460 24/27 7.2 pin configuration (tcp: ML9460advva) top view dummy dummy dummy o1 o2 o3 nc nc v2l vcl mv2l nc nc nc nc dio2 fr frresb frws4 frws3 frws2 frws1 frws0 vdd sel2 sel1 docb dspofb nc shl vss yscl nc dspms dio1 nc mv2r vcr v2r nc nc o238 o239 o240 dummy dummy dummy oki ML9460a dvva 24 240 the drawing shown does not specify the exact outline of the tcp;it only specifies the pin layout. t. b . d
fedl9460-01 lapis semiconductor ML9460 25/27 8. application circuit (with external components connected) ML9460 yscl frres dspof dspms doc f r frws0?frws4 v2l, v2r vcl, vc r mv2l, mv2r shl dio1 vs s vdd power supply circuit vlcd v1 vdd vc mv2 mv1 gnd dio2 o1 ? o240 lcd panel 320 ? 3(rgb) ? 240 1/240 duty o1 ? o320 ml9461b (no.1) sh l eio2 sel1 vss vd d fr lp scl d0?d 7 dms d s p o f vcl , vcr mv1l,mv1 r v1 l,v1 r eio1 o1 ? o320 ml9461b (no.2) o1 ? o320 ml9461b (no.3) controller lp scl d0?d7 dspof flm frws0?4 com1 com2 com239 c o m240 seg 960 seg 959 seg 2 seg 1 ca ca ca ca cb cb cb fr lp scl d0?d7 dms dspof vcl,vcr mv1l,mv1r v1 l,v1 r shl eio2 sel1 vss vd d sh l eio2 sel1 vss vdd fr lp scl d0?d7 dms dspof vcl,vcr mv1l , mv1r v1l,v1r eio1 eio1 insert a capacitor ca,cb specified in the recommended operating conditions (guaranteed operating range). it is recommended that 0.1 ? f ca capacitors (jis (japanese industrial standards) fj(f) equivalent) be used.
fedl9460-01 lapis semiconductor ML9460 26/27 revision history page document no. date previous edition current edition description pedl9460-01 may 21, 2007 ? ? preliminary edition 1 1 1 au bump chip product name dvwa cvwa 13 13 additional comment. ? 23 additional 7.2 pin configuration. pedl9460-02 dec 5, 2007 23 24 changed application circuit. ? ? changed to oki semiconductor?s format pedl9460-03 dec 17,2008 1,7,24 1,7,24 ml9461 ml9461b ? ? final edition 1 2 2 additional comment for frres pin ? 4 additional 2.2 inupt and output configuration 13 14 changed explanation fedl9460-01 jan 29,2009 22 23 additional alignment mark information
fedl9460-01 lapis semiconductor ML9460 27/27 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-a utomation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or no t in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (suc h as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2009 - 2011 lapis semiconductor co., ltd.

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