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l5991 l5991a primary controller with standby current-mode control pwm switching frequency up to 1mhz low start-up current (< 120 m a) high-current output drive suitable for power mosfet (1a) fully latched pwm logic with dou- ble pulse suppression programmable duty cycle 100% and 50% maximum duty cycle limit standby function programmable soft start primary overcurrent fault detec- tion with re-start delay pwm uvlo with hysteresis in/out synchronization latched disable internal 100ns leading edge blank- ing of current sense package: dip16 and so16 description this primary controller i.c., developed in bcd60ii technology, has been designed to implement off line or dc-dc power supply applications using a fixed frequency current mode control. based on a standard current mode pwm control- ler this device includes some features such as programmable soft start, in/out synchronization, disable (to be used for over voltage protection and for power management), precise maximum duty cycle control, 100ns leading edge blanking on current sense, pulse by pulse current limit, over- current protection with soft start intervention, and standby function for oscillator frequency reduction when the converter is lightly loaded. august 2001 ? + - + - timing 2 3 + - 14 t vref clk 2.5v + - 1.2v 13 blanking pwm fault soft-start r sq 25v 15v/10v vref ok dis + - e/a 1v r 2r dis 2.5v 7 6 5 11 10 9 4 8 15 1 13v pwm uvlo 12 sgnd comp ss isen dis dc rct sync dc-lim v cc vref d97in725a vfb pgnd out v c over current stand-by st-by vref 16 block diagram ordering numbers: l5991/l5991a (dip16) l5991d/l5991ad (so16) multipower bcd technology dip16 so16 1/23
absolute maximum ratings symbol parameter value unit v cc supply voltage (i cc < 50ma) (*) selflimit v i out output peak pulse current 1.5 a analog inputs & outputs (6,7) -0.3 to 8 v analog inputs & outputs (1,2,3,4,5,15,14, 13, 16) -0.3 to 6 v p tot power dissipation @ t amb = 70 c (dip16) @ t amb = 50 c (so16) 1 0.83 w w t j junction temperature, operating range -40 to 150 c t stg storage temperature, operating range -55 to 150 c (*) maximum package power dissipation limits must be observed thermal data symbol parameter value unit r th j-amb thermal resistance junction -ambient (dip16) 80 c/w thermal resistance junction -ambient (so16) 120 c/w pin functions n. name function 1 sync synchronization. a synchronization pulse terminates the pwm cycle and discharges ct 2 rct oscillator pin for external c t , r a , r b components 3 dc duty cycle control 4 vref 5.0v +/-1.5% reference voltage @ 25c 5 vfb error amplifier inverting input 6 comp error amplifier output 7 ss soft start pin for external capacitor css 8v cc supply for internal "signal" circuitry 9v c supply for power section 10 out high current totem pole output 11 pgnd power ground 12 sgnd signal ground 13 isen current sense 14 dis disable. it must never be left floating. tie to sgnd if not used. 15 dc-lim connecting this pin to vref, dc is limited to 50%. if it is left floating or grounded no limitation is imposed 16 st-by standby. connect a resistor to rct. connect to vref or floating if not used. sync rct dc vref vfb ss comp 1 3 2 4 5 6 7out sgnd pgnd isen dis dc-lim st-by 16 15 14 13 12 10 11 v cc 8v c 9 pin connection l5991 - l5991a 2/23
electrical characteristics (v cc = 15v; t j = 0 to 105 c; r t = 13.3k w (*) c t = 1nf; unless otherwise specified.) symbol parameter test condition min. typ. max. unit reference section v ref output voltage t j = 25 c; i o = 1ma 4.925 5.0 5.075 v line regulation v cc = 12 to 20v; t j = 25c 2.0 10 mv load regulation i o = 1 to 10ma; t j = 25c 2.0 10 mv t s temperature stability 0.4 mv/ c total variation line, load, temperature 4.80 5.0 5.130 v i os short circuit current vref = 0v 30 150 ma power down/uvlo v cc = 6v; i sink = 0.5ma 0.2 0.5 v oscillator section initial accuracy pin 15 = vref; t j = 25c; v comp = 4.5v 95 100 105 khz pin 15 = vref; v cc = 12 to 20v v comp = 4.5v 93 100 107 khz pin 15 = vref; v cc = 12 to 20v v comp = 2v 46.5 50 53.5 khz duty cycle pin 3 = 0,7v, pin 15 = v ref pin 3 = 0.7v, pin 15 = open 0 0 % % pin 3 = 3.2v, pin 15 = v ref pin 3 = 3.2v, pin 15 = open 47 93 % % duty cycle accuracy pin 3 = 2.79v, pin 15 = open 75 80 85 % oscillator ramp peak 2.8 3.0 3.2 v oscillator ramp valley 0.75 0.9 1.05 v error amplifier section input bias current v fb to gnd 0.2 3.0 m a v i input voltage v comp = v fb 2.42 2.5 2.58 v g opl open loop gain v comp = 2 to 4v 60 90 db svr supply voltage rejection v cc = 12 to 20v 85 db v ol output low voltage i sink = 2ma 1.1 v v oh output high voltage i source = 0.5ma, v fb = 2.3v 5 6 v i o output source current v comp > 4v, v fb = 2.3v 0.5 1.3 2.5 ma output sink current v comp = 1.1v, v fb = 2.7v 2 6 ma unit gain bandwidth 1.7 4 mhz s r slew rate 8 v/ m s pwm current sense section i b input bias current i sen = 0 3 15 m a i s maximum input signal v comp = 5v 0.92 1.0 1.08 v delay to output 70 100 ns gain 2.85 3 3.15 v/v v t fault threshold voltage 1.1 1.2 1.3 v soft start section i ssc ss charge current t j = 25 c 142026 m a i ssd ss discharge current vss = 0.6v t j = 25 c 5 10 15 m a v sssat ss saturation voltage dc = 0% 0.6 v v ssclamp ss clamp voltage 7 v leading edge blanking internal masking time 100 ns output section v ol output low voltage i o = 250ma 1.0 v v oh output high voltage i o = 20ma; v cc = 12v 10 10.5 v i o = 200ma; v cc = 12v 9 10 v v out clamp output clamp voltage i o = 5ma; v cc = 20v 13 v collector leakage v cc = 20v v c = 24v 2 20 m a (*) r t = r a //r b , r a = r b = 27k w , see fig. 23. l5991 - l5991a 3/23
6 8 20 30 v14 = 0, pin2 = open tj = 25c 04 8 12 16 20 24 0 0.05 0.1 0.15 0.2 4 vcc [v] iq [m a] 28 x y figure 1. l5991 - quiescent current vs. input voltage. (x = 7.6v and y= 8.4v for l5991a) 0 4 8 12 16 20 24 0 50 100 150 200 250 300 350 vcc [v] iq [ a ] v14 = vref tj = 25 c x y figure 2. l5991 - quiescent current vs. input voltage (after disable). (x = 7.6v and y= 8.4v for l5991a) electrical characteristics (continued.) symbol parameter test condition min. typ. max. unit output section fall time c o = 1nf c o = 2.5nf 20 35 60 ns ns rise time c o = 1nf c o = 2.5nf 50 70 100 ns ns uvlo saturation v cc = v c = 0 to v ccon; i sink = 10ma 1.0 v supply section v ccon startup voltage l5991 l5991a 14 7.8 15 8.4 16 9 v v v ccoff minimum operating voltage l5991 l5991a 9 7 10 7.6 11 8.2 v v v hys uvlo hysteresis l5991 l5991a 4.5 0.5 5 0.8 v v i s start up current before turn-on at: v cc = v c = v ccon -0.5v 40 75 120 m a i op operating current c t = 1nf, r t = 13.3k w , c o =1nf 9 13 ma i q quiescent current (after turn on), ct = 1nf, r t = 13.3k w , c o =0nf 7.0 10 ma v z zener voltage i 8 = 20ma 21 25 30 v standby function v ref -v st-by i st-by = 2ma 45 mv v t1 standby threshold v comp falling 2.5 v v comp rising 4.0 v synchronization section master operation v 1 clock amplitude i source = 0.8ma 4 v i 1 clock source current vclock = 3.5v 3 7 ma slave operation v 1 sync pulse low level 1 v high level 3.5 v i 1 sync pulse current vsync = 3.5v 0.5 ma over current protection v t fault threshold voltage 1.1 1.2 1.3 v disable section shutdown threshold 2.4 2.5 2.6 v input bias current v pin14 = 0 to 3v -1 1 m a i qsh quiescent current after disable v cc = 15v 330 m a l5991 - l5991a 4/23
8 1012141618202224 7.0 7.5 8.0 8.5 9.0 vcc [v] iq [m a] v14 = 0, v5 = vref rt = 4.5kohm,tj = 25c 500khz 300khz 1mhz 100khz figure 3. quiescent current vs. input voltage. 0 5 10 15 20 25 4.9 4.95 5 5.05 5.1 iref [ma] vref [v] vcc=15v tj = 25c figure 7. reference voltage vs. load current. -50 -25 0 25 50 75 100 125 150 4.9 4.95 5 5.05 5.1 t j ( c ) vref [v]) vcc = 15v iref = 1ma figure 8. vref vs. junction temperature. 8 10121416182022 0 6 12 18 24 30 36 vcc [v] iq [m a] co = 1nf, tj = 25c dc = 0% 1mhz 500khz 300khz 100khz figure 4. quiescent current vs. input voltage and switching frequency. 8 10121416182022 0 6 12 18 24 30 36 vcc [v] iq [ma] co = 1nf, tj = 25c dc = 100% 1mhz 500khz 300khz 100khz figure 5. quiescent current vs. input voltage and switching frequency. -50 -25 0 25 50 75 100 125 150 0.01 0.1 1 10 100 junction temperature [?c] [ma] start-up current vc=vcc= vccon-0.5v, before turn-on operating current vcc =15v, after turn-on rt=13.3k w , ct=1nf dc=75%, co=1nf quiescent current vcc =15v, after turn-on rt=13.3 k w , ct=1nf dc = 0 figure 6. ic consumption vs. temperature. l5991 - l5991a 5/23
10 0 0.2 0.4 0.6 0.8 1 1.2 6 8 10 12 14 16 isource [a] vsat = v [v] vcc = vc = 15v tj = 25c figure 11. output saturation. 0 0.2 0.4 0.6 0.8 1 1.2 0 0.5 1 1.5 2 2.5 isink [a] 10 vsat = v [v] vcc = vc = 15v tj = 25c figure 12. output saturation. 1 10 100 1000 10000 0 40 80 120 fsw (hz) svrr (db) vcc=15v vp-p=1v figure 10. vref svrr vs. switching frequency. 0 200 400 600 800 1,000 1,200 1,400 0 10 20 30 40 50 vpin10 [mv] ipin10 [ma] vcc < vccon before turn-on figure 13. uvlo saturation 10 20 30 40 10 20 50 100 200 500 1000 2000 5000 rt (kohm) fsw (khz) 100pf 220pf 470pf 1nf 2.2nf 5.6nf tj = 25c vcc = 15v, v15 =0v figure 14. timing resistor vs. switching frequency. -50 -25 0 25 50 75 100 125 150 4.9 4.95 5 5.05 5.1 tj (c) vref [v] vcc = 15v iref= 20ma figure 9. vref vs. junction temperature. l5991 - l5991a 6/23
0.01 0.1 1 10 100 1000 10000 100000 0 50 100 150 20 40 60 80 100 120 140 f (khz) g [db] phase figure 20. e/a frequency response. -50 -25 0 25 50 75 100 125 150 28 30 32 34 36 38 40 42 t j ( c ) dela y to output (ns) pin10 = open 1v pulse on pin13 figure 19. delay to output vs junction temperature. -50 -25 0 25 50 75 100 125 150 280 290 300 310 320 tj (c) fsw (khz) rt= 4.5kohm, ct = 1nf vcc = 15v, v15= 0 figure 16. switching frequency vs. temperature. 246810 300 600 900 1,200 1,500 timing capacitor ct [nf] dead time [ns] rt =4.5kohm v15 = 0v v15 = vref figure 17. dead time vs ct. 0 102030405060708090100 1 1.5 2 2.5 3 3.5 duty cycle [%] dc control voltage vpin3 [v] rt = 4.5kohm, ct = 1nf v15 = 0v v15 = vref figure 18. maximum duty cycle vs vpin3. -50 -25 0 25 50 75 100 125 150 280 290 300 310 320 tj (c) fsw (khz) rt= 4.5kohm, ct = 1nf vcc = 15v, v15=vref figure 15. switching frequency vs. tempera- ture. l5991 - l5991a 7/23
standby function the standby function, optimized for flyback topol- ogy, automatically detects a light load condition for the converter and decreases the oscillator fre- quency on that occurrence. the normal oscillation frequency is automatically resumed when the out- put load builds up and exceeds a defined thresh- old. this function allows to minimize power losses re- lated to switching frequency, which represent the majority of losses in a lightly loaded flyback, with- out giving up the advantages of a higher switching frequency at heavy load. this is accomplished by monitoring the output of the error amplifier (v comp ) that depends linearly on the peak primary current, except for an offset. if the the peak primary current decreases (as a re- sult of a decrease of the power demanded by the load) and v comp falls below a fixed threshold (v t1 ), the oscillator frequency will be set to a lower value (f sb ). when the peak primary current increases and v comp exceeds a second threshold (v t2 ) the oscillator frequency is set to the normal value (f osc ). an appropriate hysteresis (v t2 -v t1 ) prevents undesired frequency change when power is such that v comp moves close to the threshold. this operation is shown in fig. 21. both the normal and the standby frequency are externally programmable. v t1 and v t2 are inter- nally fixed but it is possible to adjust the thresh- olds in terms of input power level. application information detailed pin function description pin 1. sync (in/out synchronization). this func- tion allows the ics oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave). as a master, the pin delivers positive pulses dur- ing the falling edge of the oscillator (see pin 2). in slave operation the circuit is edge triggered. refer to fig. 23 to see how it works. when several ic work in parallel no master-slave designation is needed because the fastest one becomes auto- matically the master. during the ramp-up of the oscillator the pin is pulled low by a 600 m a internal sink current gener- ator. during the falling edge, that is when the pulse is released, the 600 m a pull-down is discon- nected. the pin becomes a generator whose source capability is typically 7ma (with a voltage still higher than 3.5v). in fig. 22, some practical examples of synchroniz- ing the l5991 are given. since the device automatically diminishes its op- erating frequency under light load conditions, it is reasonable to suppose that synchronization will refer to normal operation and not to standby. pin 2. rct (oscillator). two resistors (r a and r b ) and one capacitor (c t ), connected as shown in fig. 23, allow to set separately the operating fre- quency of the oscillator in normal operation (f osc ) and in standby mode (f sb ). c t is charged from vref through r a and r b in nor- mal operation ( standby = high), through r a only in standby ( standby = low). see pin 16 description to see how the standby signal is gen- erated. when the voltage on c t reaches 3v, the capaci- tor is quickly internally discharged. as the voltage has dropped to 1v it starts being charged again. 1234 vcomp pin f osc f sb stand-by normal operation v t 1 p no p sb v t 2 figure 21. standby dynamic operation. l5991 l5991 r a vref sync sync rct rct l4981a (master) l5991 (slave) r a vref sync rct r osc c osc c t l5991 (master) l4981a (slave) sync r osc c t c osc sync (a) (b) (c) r a d97in728a c t vref 4 1 2 1 2 16 18 17 4 2 1 rct 1 2 4 16 17 18 st-by 16 r b st-by 16 r b r b 16 st-by figure 22. synchronizing the l5991. l5991 - l5991a 8/23
the oscillation frequency can be established with the aid of the diagrams of fig. 14, where r t will be intended as the parallel of r a and r b in normal operation and r t = r a in standby, or considering the following approximate relationships: f osc @ 1 c t ( 0.693 ( r a // r b ) + k t ( 1 ) , which gives the normal operating frequency, and: f sb @ 1 c t ( 0.693 r a + k t ) ( 2 ) , which gives the standby frequency, that is the one the converter will operate at when lightly loaded. in the above expressions, ra // rb means: r a // r b = r a r b r a + r b , while k t is defined as: k t = ? 90 v 15 = vref 160 v 15 = gnd /open ( 3 ) , and is related to the duration of the falling-edge of the sawtooth: t d ? 30 10 - 9 + k t c t ( 4 ) . t d is also the duration of the sync pulses deliv- ered at pin 1 and defines the upper extreme of the duty cycle range, d x (see pin 15 for d x definition and calculation) since the output is held low dur- ing the falling edge. in case v15 is connected to vref, however, the switching frequency will be a half the values taken from fig. 14 or resulting from (1) and (2). to prevent the oscillator frequency from switching back and forth from f osc to f sb , the ratio f osc / f sb must not exceed 5.5. if during normal operation the ic is to be synchro- nized to an external oscillator, r a , r b and c t should be selected for a f osc lower than the master frequency in any condition (typically, 10-20% ), depending also on the tolerance of the parts. pin 3. dc (duty cycle control). by biasing this pin with a voltage between 1 and 3 v it is possible to set the maximum duty cycle between 0 and the upper extreme d x (see pin 15). if d max is the desired maximum duty cycle, the voltage v3 to be applied to pin 3 is: v 3 = 5 - 2 (2-dmax) (5) d max is determined by internal comparison be- tween v3 and the oscillator ramp (see fig. 24), thus in case the device is synchronized to an ex- ternal frequency f ext (and therefore the oscillator amplitude is reduced), (5) changes into: v 3 = 5 - 4 exp ? ? - d max r t c t f ext ? ? (6) a voltage below 1v will inhibit the driver output stage. this could be used for a not-latched device disable, for example in case of overvoltage pro- tection (see application ideas). if no limitation on the maximum duty cycle is re- quired (i.e. d max = d x ), the pin has to be left float- ing. an internal pull-up (see fig. 24) holds the volt- age above 3v. should the pin pick up noise (e.g. + - r2 r3 r1 clamp d1 50 w r a c t d r q 600 m a d97in729a v ref rct sync clk 2 4 1 16 st-by r b standby figure 23. oscillator and synchronization internal schematic. l5991 - l5991a 9/23
during esd tests), it can be connected to vref through a 4.7k w resistor. pin 4. vref (reference voltage). the device is provided with an accurate voltage reference (5v 1.5%) able to deliver some ma to an external circuit. a small film capacitor (0.1 m f typ.), connected between this pin and sgnd, is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. before device turn-on, this pin has a sink current ca- pability of 0.5ma. pin 5. vfb (error amplifier inverting input). the feedback signal is applied to this pin and is com- pared to the e/a internal reference (2.5v). the e/a output generates the control voltage which fixes the duty cycle. the e/a features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current ca- pability, which improves its large signal behavior. usually the compensation network, which stabi- lizes the overall control loop, is connected be- tween this pin and comp (pin 6). pin 6. comp (error amplifier output). usually, this pin is used for frequency compensation and the relevant network is connected between this pin and vfb (pin 5). compensation networks to- wards ground are not possible since the l5991 e/a is a voltage mode amplifier (low output im- pedance). see application ideas for some exam- ple of compensation techniques. it is worth mentioning that the calculation of the part values of the compensation network must take the standby frequency operation into ac- count. in particular, this means that the open-loop crossover frequency must not exceed f sb /4 ? f sb /5. the voltage on pin 6 is monitored in order to re- duce the oscillator frequency when the converter is lightly loaded (standby). pin 7. ss (soft-start). at device start-up, a ca- pacitor (css) connected between this pin and sgnd (pin 12) is charged by an internal current generator, issc, up to about 7v. during this ramp, the e/a output is clamped by the voltage across css itself and allowed to rise linearly, start- ing from zero, up to the steady-state value im- posed by the control loop. the maximum time in- terval during which the e/a is clamped, referred to as soft-start time, is approximately: t ss @ 3 r sense i qpk i ssc c ss (7) where r sense is the current sense resistor (see pin 13) and i qpk is the switch peak current (flowing through r sense ), which depends on the output load. usually, c ss is selected for a t ss in the or- der of milliseconds. as mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. referring to fig. 25, pulse-by-pulse current limitation is somehow effective as long as the on-time of the power switch can be reduced (from a to b). after the minimum on-time is reached (from b onwards) the current is out of control. to prevent this risk, a comparator trips an over- current handling procedure, named hiccup mode operation, when a voltage above 1.2v (point c) is detected on current sense input (isen, pin 13). basically, the ic is turned off and then soft-started as long as the fault condition is detected. as a re- sult, the operating point is moved abruptly to d, creating a foldback effect. fig. 26 illustrates the operation. the oscillation frequency appearing on the soft- start capacitor in case of permanent fault, referred to as hiccup" period, is approximately given by: t hic @ 4.5 ? ? 1 i ssc + 1 i ssd ? ? c ss ( 8 ) + - r2 r1 r a c t d97in727a v ref rct dc to pwm logic 4 3 2 23k 28k 3 m a r b st-by 16 figure 24. duty cycle control. v out t on d.c.m. c.c.m. d a b c i qpk t on(min) 1-2 i qpk i qpk(max) i out i short i out(max) d97in495 figure 25. regulation characteristic and re- lated quantities. l5991 - l5991a 10/23
since the system tries restarting each hiccup cy- cle, there is not any latchoff risk. "hiccup" keeps the system in control in case of short circuits but does not eliminate power com- ponents overstress during pulse-by-pulse limita- tion (from a to c). other external protection cir- cuits are needed if a better control of overloads is required. pin 8. vcc (controller supply). this pin supplies the signal part of the ic. the device is enabled as vcc voltage exceeds the start threshold and works as long as the voltage is above the uvlo threshold. otherwise the device is shut down and the current consumption is extremely low (<150 m a). this is particularly useful for reducing the consumption of the start-up circuit (in the sim- plest case, just one resistor), which is one of the most significant contributions to power losses in standby. an internal zener limits the voltage on vcc to 25v. the ic current consumption increases con- siderably if this limit is exceeded. a small film capacitor between this pin and sgnd (pin 12), placed as close as possible to the ic, is recommended to filter high frequency noise. pin 9. vc (supply of the power stage). it supplies the driver of the external switch and therefore ab- sorbs a pulsed current. thus it is recommended to place a buffer capacitor (towards pgnd, pin 11, as close as possible to the ic) able to sustain these current pulses and in order to avoid them inducing disturbances. this pin can be connected to the buffer capacitor directly or through a resistor, as shown in fig. 27, to control separately the turn-on and turn-off speed of the external switch, typically a power- mos. at turn-on the gate resistance is r g + r g , at turn-off is r g only. pin 10. out (driver output). this pin is the out- put of the driver stage of the external power switch. usually, this will be a powermos, al- though the driver is powerful enough to drive bjts (1.6a source, 2a sink, peak). the driver is made up of a totem pole with a high- side npn darlington and a low-side vdmos, thus there is no need of an external diode clamp to prevent voltage from going below ground. an in- ternal clamp limits the voltage delivered to the gate at 13v. thus it is possible to supply the driver (pin 9) with higher voltages without any risk of damage for the gate oxide of the external mos. the clamp does not cause any additional in- crease of power dissipation inside the chip since the current peak of the gate charge occurs when the gate voltage is few volts and the clamp is not active. besides, no current flows when the gate voltage is 13v, steady state. under uvlo conditions an internal circuit (shown 7v t hic time short i out i sen fault ss 5v 0.5v d98in986 figure 26. hiccup mode operation. out rg drive & control 13v v c v cc rg' pgnd rg(on)=rg+rg' rg(off)=rg d97in726 l5991 9 10 11 8 figure 27. turn-on and turn-off speeds adjust- ment. l5991 - l5991a 11/23
in fig.28) holds the pin low in order to ensure that the external mos cannot be turned on acciden- tally. the peculiarity of this circuit is its ability to mantain the same sink capability (typically, 20ma @ 1v) from v cc = 0v up to the start-up threshold. when the threshold is exceeded and the l5991 starts operating, v refok is pulled high (refer to fig. 28) and the circuit is disabled. it is then possible to omit the "bleeder" resistor (connected between the gate and the source of the mos) ordinarily used to prevent undesired switching-on of the external mos because of some leakage current. pin 11. pgnd (power ground). the current loop during the discharge of the gate of the external mos is closed through this pin. this loop should be as short as possible to reduce emi and run separately from signal currents return. pin 12 . sgnd (signal ground). this ground refer- ences the control circuitry of the ic, so all the ground connections of the external parts related to control functions must lead to this pin. in laying out the pcb, care must be taken in preventing switched high currents from flowing through the sgnd path. pin 13. isen (current sense). this pin is to be connected to the "hot" lead of the current sense resistor r sense (being the other one grounded), to get a voltage ramp which is an image of the cur- rent of the switch (i q ). when this voltage is equal to: v 13pk = i qpk r sense = v comp - 1.4 3 ( 9 ) the conduction of the switch is terminated. to increase the noise immunity, a "leading edge blanking" of about 100ns is internally realized as shown in fig. 29. because of that, the smoothing rc filter between this pin and r sense could be re- moved or, at least, considerably reduced. pin 14. dis (device disable). when the voltage on pin 14 rises above 2.5v the ic is shut down and it is necessary to pull vcc (ic supply voltage, pin 8) below the uvlo threshold to allow the de- vice to restart. the pin can be driven by an external logic signal in case of power management, as shown in fig. 30. it is also possible to realize an overvoltage protection, as shown in the section " application ideas".if used, bypass this pin to ground with a fil- ter capacitor to avoid spurious activation due to noise spikes. if not, it must be connected to sgnd. pin 15. dc-lim (maximum duty cycle limit). the upper extreme, dx, of the duty cycle range de- pends on the voltage applied to this pin. approxi- mately, d x @ r t r t + 230 ( 10 ) if dc-lim is grounded or left floating. instead, + - i d97in503 isen 0 3v clk 2v + - + - 1.2v from e/a overcurrent comparator pwm comparator to pwm logic to fault logic 13 figure 29. internal leb. 10 12 sgnd out v refok d97in538 figure 28. pull-down of the output in uvlo. l5991 - l5991a 12/23
connecting dc-lim to vref (half duty cycle op- tion), dx will be set approximately at: d x @ r t 2 r t + 260 ( 11 ) and the output switching frequency will be halved with respect to the oscillator one because an in- ternal t flip-flop (see block diagram) is activated. fig. 31 shows the operation. the half duty cycle option speeds up the dis- charge of the timing capacitor c t (in order to get duty cycles as close to 50% as possible) so the oscillator frequency - with the same timing compo- nents will be slightly higher. pin 16 . s-by (standby function). the resistor r b , along with r a , sets the operating frequency of the oscillator in normal operation (f osc ). in fact, as long as the standby signal is high, the pin is inter- nally connected to the reference voltage vref by a n-channel fet (see fig. 32), so the timing ca- pacitor c t is charged through r a and r b . when the standby signal goes low the n-channel fet is turned off and the pin becomes floating. r b is + - c d97in502 dis d r q disable uvlo 2.5v 14 disable signal figure 30. disable (latched). v15=gnd v5=v13=gnd v15=vref v5=v13=gnd t d t d t c t c v2 v10 v2 v10 d x = t c t c + t d d x = t c 2 t c + t d d97in498 figure 31. half duty cycle option. - + - + 2.5 2.5/4 r standby 10v level shift comp fb vref st-by 4 16 6 rct c t r a r b 2 5 low high standby d97in752b v t1 2.5v v t2 4v v comp - + isen 13 r driver out standby block 2r figure 32. standby function internal schematic and operation. l5991 - l5991a 13/23
now disconnected and c t is charged through r a only. in this way the oscillator frequency (f sb ) will be lower. refer to pin 2 description to see how to calculate the timing components. typical values for v t1 and v t2 are 2.5 v and 4v respectively. this 1.5v hysteresis is enough to prevent undesired frequency change up to a 5.5 to 1 f osc / f sb ratio. the value of v t1 is such that in a discontinuous flyback the standby frequency is activated when the input power is about 13% of the maximum. if necessary, it is possible to decrease the power threshold below 13% by adding a dc offset (v o ) on the current sense pin (13, isen). this will also allow a frequency change greater than 5.5 to 1. the following equations, useful for design, apply: p insb = 1 2 l p | osc ? ? 0.367 - v o r sense ? ? 2 ( 12 ) , p inno = 1 2 l p | sb ? ? 0.867 - v o r sense ? ? 2 ( 13 ) , | osc | sb < ? ? 0.867 - v o 0.367 - v o ? ? 2 ( 14 ) , where p insb is the input power below which the l5991 recognizes a light load and switches the oscillator frequency from | osc to f sb , p inno is the input power above which the l5991 switches back from | sb to | osc and l p the primary induc- tance of the flyback transformer. connect to vref or leave open this pin when stand-by function is not used. layout hints generally speaking a proper circuitboard layout is vital for correct operation but is not an easy task. careful component placing, correct traces routing, appropriate traces widths and, in case of high voltages, compliance with isolation distances are the major issues. the l5991 eases this task by putting two pins at disposal for separate current returns of bias (sgnd) and switch drive currents (pgnd) the matter is complex and only few im- portant points will be here reminded. 1) all current returns (signal ground, power ground, shielding, etc.) should be routed sepa- rately and should be connected only at a single ground point. 2) noise coupling can be reduced by minimizing the area circumscribed by current loops. this applies particularly to loops where high pulsed currents flow. 3) for high current paths, the traces should be doubled on the other side of the pcb whenever possible: this will reduce both the resistance and the inductance of the wiring. 4) magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying switched currents as short as possible. 5) in general, traces carrying signal currents should run far from traces carrying pulsed cur- rents or with quickly swinging voltages. from this viewpoint, particular care should be taken of the high impedance points (current sense in- put, feedback input, ...). it could be a good idea to route signal traces on one pcb side and power traces on the other side. 6) provide adequate filtering of some crucial points of the circuit, such as voltage references, ics supply pins, etc. l5991 - l5991a 14/23
application ideas here follows a series of ideas/suggestions aimed at either improving performance or solving common application problems of l5991 based supplies. c02 0.1 m f c01 0.1 m f f01 ac 250v t3.15a 88 to 270 vac bd01 r01 3.3 c03 220 m f 400v r18 47k 3w c10 10nf 100v lf01 r03 47k 10 r08 22 13 r11 1k 12 c05 100pf 11 r10 0.22 c04 47 m f 8 9 14 16 r06 27 r12 330k r13 47k r9 24k 2 4 16 c07 1 m f r5 12k 6800pf 1 3 8 7 d06 1n4148 5 7 c09 8.2nf r21 100 c08 3.3nf 6 q01 stp6 na60fi 4n35 18 15 13 14 16 17 c56 470 m f 25v c57 470 m f 25v 11 12 10 d04 1n4148 r07 47 d05 1n4937 c52 100 m f 250v c54 220 m f 100v r52 47 c58 47 m f 25v d55 byw100-100 d56 byw100-100 r53 4.7k r54 1k c61 0.056 m f r58 4.7k q51 tl431 vr51 100k r55 300k r56 4.3k c59 0.01 m f 180v 65w 80v 10w gnd 6.3v 5w +15v 5w -15v 5w d97in730a c62 100 m f 100v c55 1000 m f 16v d54 byw100-100 d53 byt11-600 d52 byt13-800 c11 4700pf 4kv c12 r19 4.7m r20 4.7m l5991 r04 47k r16 750k r17 750k c06 c11 2.2nf vac(v) pin(w) pout(w) 88 2.95 110 3.10 220 3.90 270 4.40 2 figure 33. typical application circuit for computer monitors (90w). l5991 - l5991a 15/23
4700pf 4kv 4700pf 4kv 4.7m stp4na60 4n35 220 2 x 330 m f 35v 1k 0.022 m f 2.7k 3.9k 28v / 0.7a gnd 470 m f 16v byw100-50 byw98-100 byw100-200 4.7m 12v / 1.5a 5v / 0.5a c02 0.1 m f c01 0.1 m f f01 ac 250v t1a 85 to 265 vac bd01 2.2 lf01 10k 1.1m bc337 10 22 13 1k 12 470pf 11 0.47 1/2 w 33 m f/25v 8 9 14 15 22 33k 4.7k 47k 2 3 4 1 100nf 22k 3.3nf 16 7 330nf 470 470pf 6 bat46 tl431 l5991 22v 1.1m stk2n50 1n4937 5 5.6k n1 n2 n3 n4 naux 5.6k 5.6k 2 x 470 m f 16v 5.1k 270k 100 m f 400v bzw06-154 d97in618 vac(v) pin(w) pout(w) 85 0.90 110 0.93 220 1.14 265 1.57 0.55 figure 34. typical application circuit for inkjet printers (40w). l5991 - l5991a 16/23
l5991 12 413 sgnd vref isen optional d97in751a 10 r sense r a r figure 35. standby thresholds adjustment. d97in761 l5991 pgnd isen out v c sgnd v in isolation boundary 10 9 13 11 12 figure 36. isolated mosfet drive & current transformer sensing in 2-switch topologies. l5991 v ref t v cc v in 20v d97in762b 2.2m w 33k w self-supply winding 8 4 12 11 47k w std1nb50-1 figure 37. low consumption start-up. d97in763 l5991 pgnd isen out v c v in 9 10 13 11 8 v cc figure 38. bipolar transistor driver. l5991 - l5991a 17/23
d97in507 + - ea r i + 1.3ma r d r 2r 12 c f r f 6 5 from v o 2.5v + - ea r p + 1.3ma r d r 2r 12 c f r f 6 5 from v o 2.5v error amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. c p r i error amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. vfb vfb comp comp sgnd sgnd figure 39. typical e/a compensation networks. l5991 comp d97in759 tl431 v out vfb 6 5 figure 40. feedback with optocoupler. l5991 optional d97in760a i v ref sgnd r a c t rct r slope r sense isen l5991 optional i v ref sgnd r a c t rct r slope r sense isen l5991 optional out sgnd r r slope r sense isen c slope 4 2 13 12 4 2 13 12 13 12 10 r b 16 st-by 16 st-by r b figure 41. slope compensation techniques. l5991 - l5991a 18/23
figure 42. protection against overvoltage/feedback disconnection (latched) l5991 d97in755a dc v cc vref r start 3 12 8 4 11 figure 43 protection against overvoltage/feed- back disconnection (not latched) d97in756a pgnd l5991 optional vref sgnd dis isen i 4 14 13 12 11 r sense r 2 r 1 i pk i pk max @ 2.5 r sense 1- r 2 r 1 figure 44. device shutdown on overcurrent d97in757 pgnd l5991 out sgnd isen l p r ff r v in r ff = 610 6 rl p r sense r sense 13 10 12 11 80 ? 400v dc figure 45. constant power in pulse-by-pulse current limitation (flyback discontinuous) l5991 dc 10k comp 3 6 12 13 sgnd isen d97in758a figure 46. voltage mode operation. l5991 d98in905 sgnd dis v cc r start pgnd 8 14 12 11 v z 2.2k l5991 d97in754 sgnd dis v cc r start pgnd 8 14 12 11 l5991 - l5991a 19/23
l5991 4 3 12 11 vref sgnd pgnd 10k w r2 5.1 r1 4.7k v in 80400v dc d97in750b figure 47. device shutdown on mains undervoltage. l5991 1 12 sync sgnd 1k w 5.1v d97in753a figure 48. synchronization to flyback pulses (for monitors). l5991 - l5991a 20/23
dip16 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 outline and mechanical data l5991 - l5991a 21/23
so16 narrow dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45? (typ.) d (1) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4 0.150 0.157 g 4.6 5.3 0.181 0.209 l 0.4 1.27 0.016 0.050 m 0.62 0.024 s (1) d and f do not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch). outline and mechanical data 8?(max.) l5991 - l5991a 22/23
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com l5991 - l5991a 23/23

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