!
" #
!"
#$%& % '()*
+
,, -%.
&+ &- +
/ 0 " %% 1 2
-314/5/ 6 7 $
7 89 "
,4-, "
,4+, ,9"
#$ )3 . 3
+/ :; !
,-,:,--5""6
,--:,+,5""6 '
,
!
,
'-#!
.#'+/!'! =! !0 - - 3 > "! ( ' ' ' + 1+ ;/$' ' + + ' 9 ! "
+4,+ ! " + 4*+ /
0## '
*? . =! !0 - - 3 > ' 5;6 ' ' &, ,+ ,, ' ' 5;/$6 ' &1 ' @. ' ' a,+ +1' ' 4+ ' = ' ;( ' ' a,+ + +' ' 5;6 = 5' ' a,+'6 * !) 5;/$6 = +&& !)
! " # !$%&' ( ( # $%)' * +
,-
" +-. ,-
! # / ,-
! !-# 0 1 ,- 2 1 ,- 3 1 ,- 1( ,- ( 1* ,- * 1" ,- " ( 1 ,- * 10 ,- 0 " $ $
+ ?% #2/ read cycle (v dd = 5.0v, gnd = v ee = 0v, t a = 25 q c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 1 t whe enable "h" level pulse width 300 - - ns figure 1 t re , t fe enable rise/fall time - - 25 ns figure 1 t as rs, r/w setup time 60 1 - - ns figure 1 100 2 t ah rs, r/w address hold time 10 - - ns figure 1 t rd read data output delay - - 190 ns figure 1 t dhr read data hold time 20 - - ns figure 1 write cycle (v dd = 5.0v, gnd = v ee = 0v, t a = 25 q c) symbol parameter min. typ. max. unit conditions t cyce enable cycle time 500 - - ns figure 2 t whe enable "h" level pulse width 300 - - ns figure 2 t re , t fe enable rise/fall time - - 25 ns figure 2 t as rs, r/w setup time 60 1 - - ns figure 2 100 2 t ah rs, r/w address hold time 10 - - ns figure 2 t ds data output delay 100 - - ns figure 2 t dhr data hold time 10 - - ns figure 2 notes: 1: 8-bit operation mode 2: 4-bit operation mode
timing waveforms read operation rs r/w e db0~db7 v ih1 v il1 v ih1 v il1 v ih1 v il1 v il1 v ih1 v il1 v il1 v ih1 vald data t dhr t ah t fe t wem t re v ih1 v il1 t as t ah t rd t cyce figure 1. bus read operation sequence (reading out data from nt3881d to mpu) write operation rs r/w e db0 ~ db7 v ih1 v il1 v ih1 v il1 v il1 v il1 v ih1 v il1 v il1 v ih1 vald data t dhw t ah t fe t wem t re v ih1 v il1 t as t ah v ih1 v il1 v il1 t ds t cyce figure 2. bus write operation sequence (writing data from mpu to nt3881d)
+(?2 instruction code function execution time (max) rs rw db7 db6 db5 db4 db3 db2 db1 db0 (f osc = 250khz) display clear0000000001 clear entire display area, restore display from shift, and load address counter with dd ram address 00h. 1.64ms display/ cursor home000000001* restore display from shift and load address counter with dd ram address 00h. 1.64ms entry mode set 00000001i/ds specify direction of cursor movement and display shift mode. this operation takes place after each data transfer (read/write). 40 p s display on/off 0000001dcb specify activation of display (d) cursor (c) and blinking of character at cursor position (b). 40 p s display/ cursor shift 0 0 0 0 0 1 s/c r/l * * shift display or move cursor. 40 p s function set 0 0 0 0 1 dl n f * * set interface data length (dl), number of display line (n), and character font (f). 40 p s ram address set 00 0 1 acg load the address counter with a cg ram address. subsequent data access is for cg ram data. 40 p s dd ram address set 00 1 add load the address counter with a dd ram address. subsequent data access is for dd ram data. 40 p s busy flag/ address counter read 01 ac read busy flag (bf) and contents of address counter (ac). 40 p s cg ram/ dd ram data write 10 write data write data to cg ram or dd ram. 40 p s cg ram/ dd ram data read 1 1 read data read data from cg ram or dd ram. 40 p s i/d = 1 : increment i/d = 0 : decrement s = 1 : display shift on d = 1 : display on c = 1 : cursor display on b = 1 : cursor blink on s/c = 1 : shift display s/c = 0 : move cursor r/l = 1 : shift right r/l = 0 : shift left dl = 1 : 8-bit dl = 0 : 4-bit n = 1 : dual line n = 0 : signal line f = 1 : 5x10 dots f = 0 : 5x8 dots bf = 1 : internal operation bf = 1 : ready for instruction dd ram : display data ram cg ram : character generator ram acg : character generator ram address add : display data ram address ac : address counter note 1: symbol "*" signifies an insignificant bit (disregard). note 2: correct input value for "n" is predetermined for each model.
1#
19 /. a, =! !0 / - - 3 > a+ ,+ '() / 2 a+ ++ / " / a+ a+ &+ ,+ " ! ## a+ a+ ,+ !
1##9 /. 1##'() !! 1##/ "
- /
6)!0!
, e62 !#f
*&@ 1##"! !
! a 4 ##!
"" a 4 - /
69 '
&1' 62 !#f
*&@
2## 7/#" 0 a, =! /# @.! ? ... ! # ! *+ 8*@ ;(! ? .( ! # ! + 8*@ @.! 9 ? . 5$ 6 . .! .!# ! ,+ 8*@ & ;(! 9 ? . (! # ! + 8*@ , @.! %@! ? ... ! ...! # ! &+ 8+g"@ 8*@ * ! / ? .( ..! + , *+ , +! ,! +! ,! + %*+ + 1 '0 5 6 ? . $0 +@ b,+@ c ,+!% c &+! 7 . 5 6 ? .. @ #( $c ++!% c ! 8 )!. ? . !. 0 &+ *@
72 h!/ =! / =! &,*178 2 h!/ # ??????? 9#.0 # ? # ??? 9#. # -. # ? 9#.!. # 9 /. ???? 9#. # 2!#7 "! # a 9 # 4 -. #
345*67** = ?3 ! ) a, 5.( 6 - - 3 > =; )i; ?3 ' = > ! ! . c . 0( ;/ ,! )3) == - j + - , # > ! ! . c )3 == - j + - ,
- j#
9!!!c.c ! c; -#
9. ! #! 77
$8' 5*
+'# +@ +. ! # 0j !. . 0 #! .. c +=#. ! .f 0 c0
!.c#.0 ! (. .c! ( .## ( + 3$#. # . j .! .$ +&. $. # #.;/!# .@ . # +, =# . # ! c 0 . . # ( (. # . =# ! c ! . (.#.#($
= . ?. . $.. .! 0$! ! . ? c.#(
< d )! $ +* ! !0.;/- +1=#.(##c . +7 $ # . ! 0 c 0 # ! !!($! . 0 (.. .;/- 0f# !0 c. c!0 . !# c !0 .( .;/- (. #!. # (.##.$#! ! 0
+ +<..;/!c $3.. .## ! +.;/!.0. ! =# .;/!(0# !c.!!
!
+ &+ " $ .!
7+g +. ;/ ! . 0 . ! (. c . !# + . ;/ ! . 0 # $ . c . $ 3$ c ( c ! .
!
"
#$ ! $ ! $ % & '
!
(#$ ) $ ) ( $ % " * + , (-*.,/)
!
" * + , #$ $) $ $) $ $% ) $ ! *,
& +
!
"#$ % $ % " $ & "'()*+,&
&
-
(./+ #$ % $ % $ & .#$ &0 !
!
"#$ % $ % " $ & 1 ( + "'()*+,&
!
1 ( + #$ $& $ $& $ $0
* $ 0 ! (+
/- =! # #56 =! / / - 3# ( 3 +!! +!! 3 +!! 3a5 406% - 3# ( +!! +!! +!! l+ - 3 # ( # ! #! - 3# ( +7< < a! $ #(. |