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| ds-25sf041?044c?7/2014 features ? single 2.5v - 3.6v supply ? serial peripheral inte rface (spi) compatible ? supports spi modes 0 and 3 ? supports dual and quad output read ? 104mhz maximum operating frequency ? clock-to-output (t v ) of 6 ns ? flexible, optimized erase architecture for code + data storage applications ? uniform 4-kbyte block erase ? uniform 32-kbyte block erase ? uniform 64-kbyte block erase ? full chip erase ? hardware controlled locking of protected blocks via wp pin ? 3 protected programmable security register pages ? flexible programming ? byte/page program (1 to 256 bytes) ? fast program and erase times ? 0.7ms typical page program (256 bytes) time ? 70ms typical 4-kbyte block erase time ? 300ms typical 32-kbyte block erase time ? 600ms typical 64-kbyte block erase time ? jedec standard manufacturer and device id read methodology ? low power dissipation ? 2a deep power-down current (typical) ? 10a standby current (typical) ? 4ma active read current (typical) ? endurance: 100,000 pr ogram/erase cycles ? data retention: 20 years ? complies with full industrial temperature range ? industry standard green (pb/halide-fr ee/rohs compliant) package options ? 8-lead soic (150-mil and 208-mil) ? 8-pad ultra thin dfn (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm ) (1) ? 8-lead tssop (4 x 4 mm) (1) 1. dfn and tssop packages are not currently in pr oduction. package outline di mensions are subject ? to change. AT25SF041 4-mbit, 2.5v minimum spi serial flash memory with dual-i/o and quad-i/o support
2 AT25SF041 ds-25sf041?044c?7/2014 description the adesto ? AT25SF041 is a serial interface flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is s hadowed from flash memory into embedded or external ram for execution. the flexible erase architecture of the at25 sf041 is ideal for data storage as well, eliminating the need for additional data storage devices. the erase block sizes of the AT25SF041 have been optimized to meet the needs of today's code and data storage applications. by optimizing the size of the erase blocks, the memory space can be used much more efficiently. because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large block erase flash memory devices can be greatly reduced. this increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. the device also contains three pages of security regist er that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. these security register pages can be individually locked. 1. pin descriptions and pinouts table 1-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in standby mode (not deep power-down mode), and the so pin will be in a high-impedanc e state. when the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command , address, and input data present on the si pin is always latched in on the rising edge of sc k, while output data on the so pin is always clocked out on the falling edge of sck. - input si (i/o 0 ) serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched in on the rising edge of sck. with the dual-output and quad- output read commands, the si pin becomes an output pin (i/o 0 ) in conjunction with other pins to allow two or four bits of data on (i/o 3-0 ) to be clocked in on every falling edge of sck to maintain consistency with the spi nomenclature, the si (i/o 0 ) pin will be referenced as the si pin unless specifically addressing the d ual-i/o and quad-i/o modes in which case it will be referenced as i/o 0 data present on the si pin will be ignored whenever the device is deselected (cs is deasserted). - input/output 3 AT25SF041 ds-25sf041?044c?7/2014 so (i/o 1 ) serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. with the dual-output read commands, the so pin remains an output pin (i/o 0 ) in conjunction with other pins to allow two bits of data on (i/o 1-0 ) to be clocked in on every falling edge of sck to maintain consistency with the spi nomenclature, the so (i/o 1 ) pin will be referenced as the so pin unless specifically addressing the dual-i/o modes in which case it will be referenced as i/o 1 the so pin will be in a high-impedance stat e whenever the device is deselected (cs is deasserted). - input/output wp (i/o 2 ) write protect: the wp pin controls the hardware locking feature of the device. please refer to ?erase suspend (75h)? on page 17 for more details on protection features and the wp pin. with the quad-output read commands, the wp pin becomes an output pin (i/o 2 ) in conjunction with other pins to al low four bits of data on (i/o3 3-0 ) to be clocked in on every falling edge of sck. to maintain consistency with the spi nomenclature, the wp (i/o 2 ) pin will be referenced as the wp pin unless specifically addressing the quad-i/o modes in which case it will be referenced as i/o 2 the wp pin is internally pulled-high and may be le ft floating if hardware controlled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. - input/output hold (i/o 3 ) hold: the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. please refer to ?hold function? on page 31 for additional details on the hold operation. with the quad-output read commands, the hold pin becomes an output pin (i/o 3 ) in conjunction with other pins to al low four bits of data on (i/o3 3-0 ) to be clocked in on every falling edge of sck. to maintain consistency with the spi nomenclature, the hold (i/o 3 ) pin will be referenced as the hold pin unless specifically addressing the quad-i/o modes in which case it will be referenced as i/o 3 the hold pin is internally pulled-high and may be left floating if the hold function will not be used. however, it is recommended that the hold pin also be externally connected to v cc whenever possible. - input/output v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. - power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. - power table 1-1. pin descriptions (continued) symbol name and function asserted state type 4 AT25SF041 ds-25sf041?044c?7/2014 2. block diagram figure 2-1. block diagram 3. memory array to provide the greatest flexibility, the memory array of the AT25SF041 can be erased in four levels of granularity including a full chip erase. the size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. the memory architecture diagram illustrates the breakdown of each erase level. figure 1-1. 8-soic, 8-tssop (top view) figure 1-2. 8-udfn (top view) 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si cs so wp gnd 1 2 3 4 8 7 6 5 vcc hold sck si flash memory array y-gating cs sck note: i/o 3-0 pin naming convention is used for dual-i/o and quad-i/o commands. so (i/o 1 ) si (i/o 0 ) y-decoder address latch x-decoder i/o buffers and latches control and protection logic sram data buffer wp (i/o 2 ) interface control and logic hold (i/o 3 ) 5 AT25SF041 ds-25sf041?044c?7/2014 figure 3-1. memory architecture diagram 4kb 07ffffh ? 07f000h 256 bytes 07ffffh ? 07ff00h 4kb 07efffh ? 07e000h 256 bytes 07feffh ? 07fe00h 4kb 07dfffh ? 07d000h 256 bytes 07fdffh ? 07fd00h 4kb 07cfffh ? 07c000h 256 bytes 07fcffh ? 07fc00h 4kb 07bfffh ? 07b000h 256 bytes 07fbffh ? 07fb00h 4kb 07afffh ? 07a000h 256 bytes 07faffh ? 07fa00h 4kb 079fffh ? 079 000h 256 bytes 07f9ffh ? 07f900h 4kb 078fffh ? 078 000h 256 bytes 07f8ffh ? 07f800h 4kb 077fffh ? 077 000h 256 bytes 07f7ffh ? 07f700h 4kb 076fffh ? 076 000h 256 bytes 07f6ffh ? 07f600h 4kb 075fffh ? 075 000h 256 bytes 07f5ffh ? 07f500h 4kb 074fffh ? 074 000h 256 bytes 07f4ffh ? 07f400h 4kb 073fffh ? 073 000h 256 bytes 07f3ffh ? 07f300h 4kb 072fffh ? 072 000h 256 bytes 07f2ffh ? 07f200h 4kb 071fffh ? 071 000h 256 bytes 07f1ffh ? 07f100h 4kb 070fffh ? 070 000h 256 bytes 07f0ffh ? 07f000h 4kb 06ffffh ? 06f000h 256 bytes 07efffh ? 07ef00h 4kb 06efffh ? 06e000h 256 bytes 07eeffh ? 07ee00h 4kb 06dfffh ? 06d000h 256 bytes 07edffh ? 07ed00h 4kb 06cfffh ? 06c000h 256 bytes 07ecffh ? 07ec00h 4kb 06bfffh ? 06b000h 256 bytes 07ebffh ? 07eb00h 4kb 06afffh ? 06a000h 256 bytes 07eaffh ? 07ea00h 4kb 069fffh ? 069 000h 256 bytes 07e9ffh ? 07e900h 4kb 068fffh ? 068 000h 256 bytes 07e8ffh ? 07e800h 4kb 067fffh ? 067 000h 4kb 066fffh ? 066 000h 4kb 065fffh ? 065 000h 4kb 064fffh ? 064 000h 256 bytes 0017ffh ? 001700h 4kb 063fffh ? 063 000h 256 bytes 0016ffh ? 001600h 4kb 062fffh ? 062 000h 256 bytes 0015ffh ? 001500h 4kb 061fffh ? 061 000h 256 bytes 0014ffh ? 001400h 4kb 060fffh ? 060 000h 256 bytes 0013ffh ? 001300h 256 bytes 0012ffh ? 001200h 256 bytes 0011ffh ? 001100h 256 bytes 0010ffh ? 001000h 4kb 00ffffh ? 00f000h 256 bytes 000fffh ? 000f00h 4kb 00efffh ? 00e000h 256 bytes 000effh ? 000e00h 4kb 00dfffh ? 00d000h 256 bytes 000dffh ? 000d00h 4kb 00cfffh ? 00c000h 256 bytes 000cffh ? 000c00h 4kb 00bfffh ? 00b000h 256 bytes 000bffh ? 000b00h 4kb 00afffh ? 00a000h 256 bytes 000affh ? 000a00h 4kb 009fffh ? 009 000h 256 bytes 0009ffh ? 000900h 4kb 008fffh ? 008 000h 256 bytes 0008ffh ? 000800h 4kb 007fffh ? 007 000h 256 bytes 0007ffh ? 000700h 4kb 006fffh ? 006 000h 256 bytes 0006ffh ? 000600h 4kb 005fffh ? 005 000h 256 bytes 0005ffh ? 000500h 4kb 004fffh ? 004 000h 256 bytes 0004ffh ? 000400h 4kb 003fffh ? 003 000h 256 bytes 0003ffh ? 000300h 4kb 002fffh ? 002 000h 256 bytes 0002ffh ? 000200h 4kb 001fffh ? 001 000h 256 bytes 0001ffh ? 000100h 4kb 000fffh ? 000 000h 256 bytes 0000ffh ? 000000h 32kb 32kb 64kb 32kb 32kb ? ? ? ? ? ? ? ? ? 64kb 32kb 32kb ? ? ? 64kb 64kb 32kb 4kb 1-256 byte (d8h command) (52h command) (20h command) (02h command) block erase detail page address block address range range block erase block erase block erase page program detail page program 6 AT25SF041 ds-25sf041?044c?7/2014 4. device operation the AT25SF041 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the spi master. the spi master communicates with the AT25SF041 via th e spi bus which is comprised of four signal lines: chip select ( cs ), serial clock (sck), serial input (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the AT25SF041 supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 4-1. spi mode 0 and 3 4.1 dual output read the AT25SF041 features a dual-output read mode that allow two bits of data to be clocked out of the device every clock cycle to improve throughput. to accomplish this, both the si and so pins are utilized as outputs for the transfer of data bytes. with the dual-output read array command, the si pin becomes an output along with the so pin. 4.2 quad output read the AT25SF041 features a quad-output read mode that allow four bits of data to be clocked out of the device every clock cycle to improve throughput. to accomplish this, the si, so, wp , hold pins are utilized as outputs for the transfer of data bytes. with the quad-output read array command, the si, wp , hold pins become outputs along with the so pin. 5. commands and addressing a valid instruction or operation must always be started by first asserting the cs pin. after the cs pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. all opcode, address, and data bytes are transferred with the most-significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not supported by the AT25SF041 will be ignored by the device and no operation will be started. the device will continue to ignore any data presented on the si pin until the start of the next operation ( cs pin being deasserted and then reasserted). in addition, if the cs pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of three bytes of information to be sent, representing address bits a23-a0. since the upper address limit of the AT25SF041 memory arra y is 07ffffh, address bits a 23-a19 are always ignored by the device. sck cs si so msb lsb msb lsb 7 AT25SF041 ds-25sf041?044c?7/2014 table 5-1. command listing command opcode clock frequency address bytes dummy bytes data bytes section link read commands read array 0bh 0000 1011 up to 85 mhz 3 1 1+ 6.1 03h 0000 0011 up to 50 mhz 3 0 1+ dual output read 3bh 0011 1011 up to 85 mhz 3 1 1+ 6.2 dual i/o read bbh 1011 1011 up to 85 mhz 3 0 1+ 6.3 quad output read 6bh 0110 1011 up to 85 mhz 3 1 1+ 6.4 quad i/o read ebh 1110 1011 up to 85 mhz 3 1 1+ 6.5 continuous read mode reset - dual ffffh 1111 1111 1111 1111 up to 104 mhz 0 0 0 6.6 continuous read mode reset - quad ffh 1111 1111 up to 104 mhz 0 0 0 6.6 program and erase commands block erase (4 kbytes) 20h 0010 0000 up to 104 mhz 3 0 0 7.2 block erase (32 kbytes) 52h 0101 0010 up to 104 mhz 3 0 0 block erase (64 kbytes) d8h 1101 1000 up to 104mhz 3 0 0 chip erase 60h 0110 0000 up to 104 mhz 0 0 0 7.3 c7h 1100 0111 up to 104 mhz 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 up to 104 mhz 3 0 1+ 7.1 protection commands write enable 06h 0000 0110 up to 104 mhz 0 0 0 8.1 write disable 04h 0000 0100 up to 104 mhz 0 0 0 8.2 security commands erase security register page 44h 0100 0100 up to 104 mhz 3 0 0 9.1 program security register page 42h 0100 0010 up to 104 mhz 3 0 1+ 9.2 read security register page 48h 0100 1000 up to 85mhz 3 1 1+ 9.3 status register commands read status register byte 1 05h 0000 0101 up to 104 mhz 0 0 1 10.1 read status register byte 2 35h 0011 0101 up to 104 mhz 0 0 1 write status register 01h 0000 0001 up to 104 mhz 0 0 1 or 2 10.2 write enable for volatile status register 50h 0101 0000 up to 104mhz 0 0 0 10.3 miscellaneous commands read manufacturer and device id 9fh 1001 1111 up to 104mhz 0 0 3 11.1 8 AT25SF041 ds-25sf041?044c?7/2014 6. read commands 6.1 read array (0bh and 03h) the read array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address is specified. the device incorporates an internal address counter that automatically increments every clock cycle. two opcodes (0bh and 03h) can be used for the read array command. the use of each opcode depends on the maximum clock frequency that will be used to read data from the device. the 0bh opcode can be used at any clock frequency up to the maximum specified by f rdhf , and the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (0bh or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, an additional dummy byte needs to be clocked into the device if the 0bh opcode is used for the read array operation. after the three address bytes (and the dummy byte if us ing opcode 0bh) have been clocked in, additional clock cycles will result in data being output on the so pin. the data is always output with the msb of a byte first. when the last byte (07ffffh) of the memory array has been read, the devic e will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the so pin into high-impedance state. the cs pin can be deasserted at any time and does not require a full byte of data be read. figure 6-1. read array - 03h opcode read id 90h 1001 0000 up to 104 mhz 3 0 2 11.2 deep power-down b9h 1011 1001 up to 104 mhz 0 0 0 11.3 resume from deep power-down abh 1010 1011 up to 104 mhz 0 0 0 11.4 resume from deep power-down and read id abh 1010 1011 up to 104 mhz 0 3 1 11.4 table 5-1. command listing command opcode clock frequency address bytes dummy bytes data bytes section link 6 & . & 6 6 , 6 2 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 9 AT25SF041 ds-25sf041?044c?7/2014 figure 6-2. read array - 0bh opcode 6.2 dual-output r ead array (3bh) the dual-output read array command is similar to the standard read array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. unlike the standard read array command, however, the dual-output read array command allows two bits of data to be clocked out of the device on every clock cycle, rather than just one. the dual-output read array command can be used at any clock frequency, up to the maximum specified by f rddo . to perform the dual-output read array operation, the cs pin must first be asserted and then the opcode 3bh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. following the three address bytes, a single dummy byte must also be clocked into the device. after the three address bytes and the dummy byte have been cl ocked in, additional clock cycles will result in data being output on both the so and si pins. the data is always output with the msb of a byte first and the msb is always output on the so pin. during the first clock cycle, bit seven of the first data byte is output on the so pin, while bit six of the sam e data byte is output on the si pin. during the next clock cycle, bits five and four of the first data byte are output on the so and si pins, respectively. the sequence continues with each byte of data being output after every four clock cycles. when the last byte (07ffffh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array.deasserting the cs pin will terminate the read operation and put the so and si pins into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 6-3. dual-output read array 6 & . & 6 6 , 6 2 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % ; ; ; ; ; ; ; ; 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' 2 1 7 & $ 5 ( ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( sck cs 6 , 6 , 2 so ms b ms b 23 1 0 00111011 67 5 41 01 1 9 81 23 94 24 3 4 1 4 0 3 73 8 3 33 6 3 5 3 4 3 13 2 2 93 04 44 74 8 4 6 4 5 2 3 & 2 ' ( aaaa aaa aa ms b xxxxxxxx ms b ms b ms b d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 $ ' ' 5 ( 6 6 % , 7 6 $ $ d on ' t & $ 5 ( ou t p u t d a t $ % < 7 ( ou t p u t d a t $ % < 7 ( h i gh - i mp e d a n ce 10 AT25SF041 ds-25sf041?044c?7/2014 6.3 dual-i/o read array (bbh) the dual-i/o read array command is similar to the dual-output read array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address with two bits of address on each clock and two bits of data on every clock cycle. the dual-i/o read array command can be used at any clock frequency, up to the maximum specified by f rddo . to perform the dual-i/o read array operation, the cs pin must first be asserted and then the opcode bbh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. following the three address bytes, a single mode byte must also be clocked into the device. after the three address bytes and the mode byte have been clocked in, additional clock cycles will result in data being output on both the so and si pins. the data is always output with the msb of a byte first and the msb is always output on the so pin. during the first clock cycle, bit seven of the first data byte is output on the so pin, while bit six of the sam e data byte is output on the si pin. during the next clock cycle, bits five and four of the first data byte are output on the so and si pins, respectively. the sequence continues with each byte of data being output after every four clock cycles. when the last byte (07ffffh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array.deasserting the cs pin will terminate the read operation and put the so and si pins into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 6-4. dual i/o read array (initial command or previous m5, m4 ? 1,0) 6.3.1 dual-i/o read array (bbh) with continuous read mode the fast read dual i/o command can further reduce instruction overhead through setting the continuous read mode bits (m7-0) after the input address bits (a23-0), as show n in figure 6-5. the upper nibble of the (m7-4) controls the length of the next fast read dual i/o command through the inclus ion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0) are don't care ("x"). howe ver, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the "continuous read mode" bits m5-4 = (1,0), then the next fast read dual i/o command (after cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 15. this reduces the command sequence by eight clocks and allows the read address to be immediately entered after cs is asserted low. if the "continuous read mode" bits m5-4 do not equal to (1,0), the next command (after cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset command can also be used to reset (m7-0) before issuing normal commands. i/o 0 (si) sck i/o 1 (so) cs msb msb 23 1 0 10111011 67 5 41011 9 812 23 21 22 19 20 opcode a 22 a 20 a 18 a 16 a 0 m 6 m 4 a 14 a address bits a23-a16 m 3 m 2 m 1 m 0 address bits a15-a8 a7-a0 m7-m0 msb a 23 a 21 a 19 a 17 a 1 m 7 m 5 a 15 a 27 25 26 24 d 6 d 4 d 3 d 2 d 1 d 0 byte 1 d 7 d 5 d 6 d 7 byte 2 11 AT25SF041 ds-25sf041?044c?7/2014 figure 6-5. dual-i/o read array (previous command set m5, m4 = 1,0) 6.4 quad-output read array (6bh) the quad-output read array command is similar to the dual-output read array command. the quad-output read array command allows four bits of data to be clocked out of the device on every clock cycle, rather than just one or two. the quad enable bit (qe) of the status register must be set to enable for the quad-output read array instruction. the quad-output read array command can be used at any clock frequency, up to the maximum specified by f rdqo . to perform the quad-output read array operation, the cs pin must first be asserted and then the opcode 6bh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. following the three address bytes, a single dummy byte must also be clocked into the device. after the three address bytes and the dummy byte have been cl ocked in, additional clock cycles will result in data being output on the i/o 3-0 pins. the data is always output with the msb of a byte first and the msb is always output on the i/o 3 pin. during the first clock cycle, bit 7 of the first data byte will be output on the i/o 3 pin while bits 6, 5, and 4 of the same data byte will be output on the i/o 2 , i/o 1 , and i/o 0 pins, respectively. during the next clock cycle, bits 3, 2, 1, and 0 of the first data byte will be output on the i/o 3 , i/o 2 , i/o 1 and i/o 0 pins, respectively. the sequence continues with each byte of data being output afte r every two clock cycles. when the last byte (07ffffh) of the memory array has been read, the device will cont inue reading from the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array.deasserting the cs pin will terminate the read operation and put the wp , hold , so, si pins into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. ? i/o 0 (si) sck i/o 1 (so) cs msb 23 1 067 5 41011 9 812 17 15 16 13 14 a 22 a 20 a 18 a 16 a 0 m 6 m 4 a 14 a address bits a23-a16 m 3 m 2 m 1 m 0 address bits a15-a8 a7-a0 m7-m0 msb a 23 a 21 a 19 a 17 a 1 m 7 m 5 a 15 a 21 19 20 18 d 6 d 4 d 3 d 2 d 1 d 0 byte 1 d 7 d 5 d 6 d 7 byte 2 12 AT25SF041 ds-25sf041?044c?7/2014 figure 6-6. quad-output read array 6.5 quad-i/o read array(ebh) the quad-i/o read array command is similar to the q uad-output read array command. the quad-i/o read array command allows four bits of address to be clocked into the device on every clock cycle, rather than just one. the quad-i/o read array command can be used at any clock frequency, up to the maximum specified by f rdqo . to perform the quad-i/o read array operation, the cs pin must first be asserted and then the opcode ebh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. following the three address bytes, a single mode byte must also be clocked into the device. after the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles will result in data being output on the i/o 3-0 pins. the data is always output with the msb of a byte first and the msb is always output on the i/o 3 pin. during the first clock cycle, bit 7 of the first data byte will be output on the i/o 3 pin while bits 6, 5, and 4 of the same data byte will be output on the i/o 2 , i/o 1 and i/o 0 pins, respectively. during the next clock cycle, bits 3, 2, 1, and 0 of the first data byte will be output on the i/o 3 , i/o 2 , i/o 1 and i/o 0 pins, respectively. the sequence continues with each byte of data being output after every two clock cycles. when the last byte (07ffffh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array.deasserting the cs pin will terminate the read operation and put the i/o 3 , i/o 2 , i/o 1 and i/o 0 pins into a high- impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read.the quad enable bit (qe) of the status register must be set to enable for the quad-i/o read array instruction. i/o 0 (si) sck 0 6 % 0 6 % 23 1 0 01101011 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa aa 0 6 % xxxxxxxx address bits a23-a0 don't care byte 1 out byte 2 out byte 3 out byte 4 out byte 5 out i/o 1 (so) high-impedance d 5 d 1 d 5 d 1 d 5 d 1 d 5 d 1 d 5 d 1 i/o 2 (wp) high-impedance d 6 d 2 d 6 d 2 d 6 d 2 d 6 d 2 d 6 d 2 i/o 3 (hold) msb msb msb msb msb high-impedance d 7 d 3 d 7 d 3 d 7 d 3 d 7 d 3 d 7 d 3 d 4 d 0 d 4 d 0 d 4 d 0 d 4 d 0 d 4 d 0 cs 13 AT25SF041 ds-25sf041?044c?7/2014 figure 6-7. quad-i/o read array (initial command or previous m5, m4 ??? 1,0) 6.5.1 quad-i/o read array (ebh) with continuous read mode the fast read quad i/o command can further reduce instruction overhead through setting the continuous read mode bits (m7-0) after the input address bits (a23-0), as shown in figure 6-6. the upper nibble (m7-4) of the continuous read mode bits controls the length of the next fast read quad i/o command through the inclusion or exclusion of the first byte instruction code. the lower nibble bits (m3-0) of the conti nuous read mode bits are don't care. however, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5-4 = (1,0), then the next quad-i/o read array command (after cs is raised and then lowered) does not require the ebh instruction code, as shown in fig 6-8. this reduces the command sequence by eight clocks and allows the read address to be immediately entered after cs is asserted low. if the "continuous read mode" bits m5-4 do not equal to (1,0), the next command (after cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset command can al so be used to reset (m7-0) before issuing normal commands. figure 6-8. quad i/o read array with continuous read mode (previous command set m5-4 =1,0) 6.6 continuous read mode reset (ffh or ffffh) the continuous read mode bits are used in conjunction with the dual i/o read array and the quad i/o read array commands to provide the highest random flash memory access rate with minimum spi instruction overhead, thus allowing more efficient xip (execute in place) with this device family. i/o 0 (si) sck i/o 1 (so) cs msb 23 1 0 11101011 67 5 41011 9 819 17 18 16 opcode a 20 a 16 a 12 a 8 a23-a16 a15-a8 a 21 a 17 a 13 a 9 23 21 22 20 d 4 d 1 d 0 d 5 d 4 byte 1 d 5 d 0 d 1 byte 2 i/o 2 (wp) a 22 a 18 a 14 a 10 d 2 d 6 d 6 d 2 i/o 3 (hold) a 23 a 19 a 15 a 11 d 3 d 7 d 7 d 3 14 15 13 12 a 4 a 0 m 4 m 0 a7-a0 m7-m0 a 6 a 2 m 6 m 2 a 7 a 3 m 7 m 3 a 5 a 1 m 5 m 1 dummy i/o 0 (si) sck i/o 1 (so) cs 23 1 067 5 41011 9 8 a 20 a 16 a 12 a 8 a23-a16 a15-a8 a 21 a 17 a 13 a 9 d 4 d 1 d 0 d 5 d 4 byte 1 d 5 d 0 d 1 byte 2 i/o 2 (wp) a 22 a 18 a 14 a 10 d 2 d 6 d 6 d 2 i/o 3 (hold) a 23 a 19 a 15 a 11 d 3 d 7 d 7 d 3 14 15 13 12 a 4 a 0 m 4 m 0 a7-a0 m7-m0 a 6 a 2 m 6 m 2 a 7 a 3 m 7 m 3 a 5 a 1 m 5 m 1 dummy 14 AT25SF041 ds-25sf041?044c?7/2014 the "continuous read mode" bits m7-0 are set by the d ual/quad i/o read array commands. m5-4 are used to control whether the 8-bit spi instruction code (bbh or ebh) is needed or not for the next instruction. when m5-4 = (1,0), the next instruction will be treated the same as the current dual/quad i/o read array command without needing the 8-bit instruction code. when m5-4 do not equal (1,0), the device returns to normal spi instruction mode, in which all instructions can be accepted. m7-6 and m3-0 are reserved bits for future use; either 0 or 1 values can be used. see figure 6-9, the continuous read mode reset instruction ( ffh or ffffh) can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation. to reset continuous read mode during quad i/o operation, only eight clocks are needed to shift in instruction ffh. to reset continuous read mode during dual i/o operation, sixteen clocks are needed to shift in instruction ffffh. figure 6-9. continuous read mode reset (quad) figure 6-10. continuous read mode reset (dual) 7. program and erase commands 7.1 byte/page program (02h) the byte/page program command allows anywhere from a singl e byte of data to 256 bytes of data to be programmed into previously erased memory locations. an erased memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable (06h)? on page 17 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte/page program command, an opcode of 02h mu st be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on an even 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situation, any data sck cs si so ms b 23 1 0 11111111 67 5 4 op cod e don?t care 10 11 9 81415 13 12 11111111 s ck cs si so ms b 23 1 0 11111111 67 5 4 op cod e don?t care 15 AT25SF041 ds-25sf041?044c?7/2014 that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting addr ess specified by a23-a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. in addition, if the memory is in the protected state (see ?non-volatile protection? on page 18 ), then the byte/page program command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected. while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. figure 7-1. byte program figure 7-2. page program 6 & . & 6 6 , 6 2 0 6 % 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( $ $ $ $ $ $ $ $ $ 0 6 % ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ , 1 6 & . & 6 6 , 6 2 0 6 % 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( $ $ $ $ $ $ 0 6 % ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' $ 7 $ , 1 % < 7 ( 0 6 % ' ' ' ' ' ' ' ' ' $ 7 $ , 1 % < 7 ( q 16 AT25SF041 ds-25sf041?044c?7/2014 7.2 block erase (20h, 52h, or d8h) a block of 4, 32, or 64 kbytes can be erased (all bits set to the logical ?1? state) in a single operation by using one of thre e different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is used for a 32-kbyte erase, or d8h is used for a 64-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. to perform a block erase, the cs pin must first be asserted and the appropriate opcode (20h, 52h, or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4- or 32- or 64-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the device will erase the appropriate block. the erasing of the block is internally self- timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. therefore, for a 4-kbyte erase, address bits a11-a0 will be ignored by the device and their values can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14- a0 will be ignored by the device. for a 64-kbyte erase, address bits a15-a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. if the memory is in the protected state, then the block erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent, the cs pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t blke time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. figure 7-3. block erase 7.3 chip erase (60h or c7h) the entire memory array can be erased in a single operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. two opcodes (60h and c7h) can be used for the chip erase command. there is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. to perform a chip erase, one of the two opcodes must be clocked into the device. since the entire memory ar ray is to be erased, no address bytes need to be clocked into 6 & . & 6 6 , 6 2 0 6 % 0 6 % & & & & & & & & 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ $ $ $ $ ' ' 5 ( 6 6 % , 7 6 $ $ + , * + , 0 3 ( ' $ 1 & ( 17 AT25SF041 ds-25sf041?044c?7/2014 the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of the device is internally self-timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, no erase will be performed. in addition, if the memory array is in the protected state, then the chip erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the cs pin is deasserted on uneven byte boundaries or if the memory is in the protected state. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t chpe time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. figure 7-4. chip erase 8. protection commands and features 8.1 write enable (06h) the write enable command is used to set the write enable latch (wel) bit in the status register to a logical ?1? state. the wel bit must be set before a byte/page program, erase, pr ogram security register pages , erase security register pages or write status register command can be executed. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. if the wel bit in the status register is not set prior to the issuance of one of these commands, then the command will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device wil l abort the operation and the wel bit state will not change. figure 8-1. write enable 6 & . & 6 6 , 6 2 0 6 % & & & & & & & & 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 6 & . & 6 6 , 6 2 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 18 AT25SF041 ds-25sf041?044c?7/2014 8.2 write disable (04h) the write disable command is used to reset the write enable lat ch (wel) bit in the status register to the logical ?0? state. with the wel bit reset, all byte/page program, erase, program security register page, and write status register commands will not be executed. other conditions can also caus e the wel bit to be reset; for more details, refer to the wel bit section of the status register description. to issue the write disable command, the cs pin must first be asserted and the opcode of 04h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the wel bit state will not change. figure 8-2. write disable 8.3 non-volatile protection the device can be software protected against erroneous or ma licious program or erase operations by utilizing the non- volatile protection feature of the device. non-volatile pr otection can be enabled or disabled by using the write status register command to change the value of the protection (cmp, se c, tb, bp2, bp1, bp0) bits in the status register. the following table outlines the states of the protection bits and the associated protection area. ? 6 & . & 6 6 , 6 2 0 6 % 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( table 8-1. memory array with cmp=0 protection bits memory content sec tb bp2 bp1 bp0 address range portion x x 0 0 0 none none 0 0 0 0 1 070000h-07ffffh upper 1/8 0 0 0 1 0 060000h-07ffffh upper 1/4 0 0 0 1 1 040000h-07ffffh upper 1/2 0 1 0 0 1 000000h-00ffffh lower 1/8 0 1 0 1 0 000000h-01ffffh lower 1/4 0 1 0 1 1 000000h-03ffffh lower 1/2 0 x 1 x x 000000h-07ffffh all 1 0 0 0 1 07f000h-07ffffh upper 1/128 1 0 0 1 0 07e000h-07ffffh upper 1/64 1 0 0 1 1 07c000h-07ffffh upper 1/32 19 AT25SF041 ds-25sf041?044c?7/2014 table 8-2. memory array protection with cmp=1 1 0 1 0 x 078000h-07ffffh upper 1/16 1 0 1 1 0 078000h-07ffffh upper 1/16 1 1 0 0 1 000000h-000fffh lower 1/128 1 1 0 1 0 000000h-001fffh lower 1/64 1 1 0 1 1 000000h-003fffh lower 1/32 1 1 1 0 x 000000h-007fffh lower 1/16 1 1 1 1 0 000000h-007fffh lower 1/16 1 x 1 1 1 000000h-07ffffh all protection bits memory content sec tb bp2 bp1 bp0 address range portion x x 0 0 0 000000h-07ffffh all 0 0 0 0 1 000000h-06ffffh lower 7/8 0 0 0 1 0 000000h-05ffffh lower 3/4 0 0 0 1 1 000000h-03ffffh lower 1/2 0 1 0 0 1 010000h-07ffffh upper 7/8 0 1 0 1 0 020000h-07ffffh upper 3/4 0 1 0 1 1 040000h-07ffffh upper 1/2 0 x 1 x x none none 1 0 0 0 1 000000h-07efffh lower 127/128 1 0 0 1 0 000000h-07dfffh lower 63/64 1 0 0 1 1 000000h-07bfffh lower 31/32 1 0 1 0 x 000000h-077fffh lower 15/16 1 0 1 1 0 000000h-077fffh lower 15/16 1 1 0 0 1 001000h-07ffffh upper 127/128 1 1 0 1 0 002000h-07ffffh upper 63/64 1 1 0 1 1 004000h-07ffffh upper 31/32 1 1 1 0 x 008000h-07ffffh upper 15/16 1 1 1 1 0 008000h-07ffffh upper 15/16 1 x 1 1 1 none none table 8-1. memory array with cmp=0 protection bits memory content 20 AT25SF041 ds-25sf041?044c?7/2014 as a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the protection can be locked from updates by using the wp pin (see ?protected states and the write protect pin? on page 20 for more details). 8.4 protected states and the write protect pin the wp pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. instead, the wp pin, is used to control the hardware locking mechanism of the device. if the wp pin is permanently connected to gnd, then the protection bits cannot be changed. 9. security register commands the device contains three extra pages called security registers that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. the security registers are independent of the main flash memory. each page of the security register can be erased and programmed independently. each page can also be independently locked to prevent further changes. 9.1 erase security registers (44h) before an erase security register page command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical "1" state. to perform an erase security register page command, the cs pin must first be asserted and the opcode 44h must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying the security register page to be erased must be clocked in. when the cs pin is deasserted, the device will erase the appropriate block. the erasing of the block is internally self-timed and should take place in a time of t be . since the erase security register page command erases a r egion of bytes, the lower order address bits do not need to be decoded by the device. therefore address bits a7-a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted right after the last address bit (a0); otherwise, the device will abort the operation and no erase operation will be performed. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t be time to determine if the device has finished erasing. at some point before the erase cycle completes, the rdy /bsy bit in the status register will be reset back to the logical "0" state. the wel bit in the status register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete address being sent, the cs pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. the security registers lock bits (lb3-lb1) in the status r egister can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked. the erase security register page instruction will be ignored for security registers which have their lock bit set. table 9-1. security register addresses for program security registers command address a23-a16 a15-a8 a7-a0 security register 1 00h 01h byte address security register 2 00h 02h byte address security register 3 00h 03h byte address 21 AT25SF041 ds-25sf041?044c?7/2014 figure 9-1. erase security register page 9.2 program security registers (42h) the program security registers command utilizes the internal 256-byte buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. the security registers can be programmed in a similar fash ion to the program array operation up to the maximum clock frequency specified by f clk . before a program security registers command can be started, the write enable command must have been previously issued to the device (see ?write enable (06h)? on page 17 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to program the security registers, the cs pin must first be asserted and the opcode of 42h must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to program within the security register. figure 9-2. program security registers 9.3 read security registers (48h) the security register can be sequentially read in a similar fa shion to the read array operation up to the maximum clock frequency specified by f clk . to read the security register, the cs pin must first be asserted and the opcode of 48h must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the security register. following the three address bytes, one dummy byte must be clocked into the device before data can be output. after the three address bytes and the dummy byte have been clo cked in, additional clock cycles will result in security register data being output on the so pin. when the last byte (0003ffh) of the security register has been read, the device will continue reading back at the beginning of the r egister (000000h). no delays will be incurred when wrapping around from the end of the register to the beginning of the register. 6 & . & 6 6 , msb 23 1 0 67 5 4 op c od e $ $ $ $ $ % , 7 $ ' ' 5 ( 6 6 6 & . & 6 6 , 6 2 ms b ms b 23 1 0 0 01 67 5 49 83 9 3 73 8 3 33 6 3 5 3 4 3 13 2 2 93 0 op cod e h i gh - i mp e d a n ce aa aaa a ms b dddddddd a d d r e ss b i t s a 2 3 - a 0 d a t a i n b y t e 1 ms b dddddddd d a t a i n b y t e n 22 AT25SF041 ds-25sf041?044c?7/2014 deasserting the cs pin will terminate the read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. ? figure 9-3. read security registers 10. status register commands 10.1 read status regi ster (05h and 35h) the status register can be read to determine the device's r eady/busy status, as well as the status of many other functions such as block protection. the status register c an be read at any time, including during an internally self-timed program or erase operation. to read status register byte 1, the cs pin must first be asserted and the opcode of 05h must be clocked into the device. after the opcode has been clocked in, the device will begin outpu tting status register byte 1 data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of status register byte 1 has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence will output new data. deasserting the cs pin will terminate the read status register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. to read status register byte 2, the cs pin must first be asserted and the opcode of 35h must be clocked into the device. after the opcode has been clocked in, the device will begin outpu tting status register byte 2 data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of status register byte 2 has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence will output new data. deasserting the cs pin will terminate the read status register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 9-2. security register addresses for read security registers command address a23-a16 a15-a8 a7-a0 security register 1 00h 01h byte address security register 2 00h 02h byte address security register 3 00h 03h byte address 6 & . & 6 6 , 6 2 ms b ms b 23 1 0 01 67 5 41 01 1 9 81 23 33 6 3 5 3 4 3 13 2 2 93 0 op cod e aaaa aaa aa xxx ms b ms b dddddddd d d a d d r e ss b i t s a 2 3 - a 0 ms b xxxxxx d on ' t ca r e d a t a b y t e 1 h i gh - i mp e d a n ce 23 AT25SF041 ds-25sf041?044c?7/2014 notes: 1. only bits 7 through 2 of the status register c an be modified when using the write status register command. 2. r/w = readable and writable ? r = readable only figure 10-1. read status register byte 1 table 10-1. status register format - byte 1 bit (1) name type (2) description 7 srp0 status register protection bit-0 r/w see table 10-3 on status register protection 6 sec block protection r/w see table 8-1 and 8-2 on non-volatile protection 5 tb top or bottom protection r/w see table 8-1 and 8-2 on non-volatile protection 4 bp2 block protection bit-2 r/w see table 8-1 and 8-2 on non-volatile protection 3 bp1 block protection bit-1 r/w see table 8-1 and 8-2 on non-volatile protection 2 bp0 block protection bit-0 r/w see table 8-1 and 8-2 on non-volatile protection 1 wel write enable latch status r 0 device is not write enabled (default) 1 device is write enabled 0 rdy /bsy ready/busy status r 0 device is ready 1 device is busy with an internal operation sck cs si so ms b 23 1 0 00000101 67 5 41 01 1 9 81 22 12 2 1 72 0 1 9 1 8 1 51 6 1 31 42 32 42 82 9 2 7 2 6 2 53 0 2 3 & 2 ' ( ms b ms b dddddd dd d d ms b dddddd d d d dd d d d 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 byte 1 h i gh - i mp e d a n ce 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 byte 1 byte 1 table 10-2. status register format ? byte 2 bit (1) name type (2) description 7 res reserved for future use r 0 reserved for future use 6 cmp complement block protection r/w 0 see table on block protection 5 lb3 lock security register 3 r/w 0 security register page-3 is not locked (default) 1 security register page-3 cannot be erased/programmed 4 lb2 lock security register 2 r/w 0 security register page-2 is not locked (default) 1 security register page-2 cannot be erased/programmed 3 lb1 lock security register 1 r/w 0 security register page-1 is not locked (default) 1 security register page-1 cannot be erased/programmed 2 res reserved for future use r 0 reserved for future use 1 qe quad enable r/w 0 hold and wp function normally (default) 1 hold and wp are i/o pins 0 srp1 status register protect bit-1 r/w see table on status register protection 24 AT25SF041 ds-25sf041?044c?7/2014 notes: 1. only bits 6 through 3, 1, and 0 of the status regist er can be modified when using the write status register command 2. r/w = readable and writable ? r = readable only. ? figure 10-2. read status register byte 2 10.1.1 srp1, srp0 bits the srp1 and srp0 bits control whether the status register can be modified. the state of the wp pin along with the values of the srp1 and srp0 determine if the device is software protected, hardware protected, or permanently protected (see table 10-3 ). 10.1.2 cmp, sec, tb, bp2, bp1, bp0 bits the cmp, sec, tb, bp2, bp1, and bp0 bits control which portions of the array are protected from erase and program operations (see tables 8-1 and 8-2). the cmp bit complements the effect of the other bits. the sec bit selects between large and small block size protection. the tb bit selects between top of the array or bottom of the array protection. the bp2, bp1, and bp0 bits determine ho w much of the array is protected. sck cs si so ms b 23 1 0 00 0101 67 5 41 01 1 9 81 22 12 2 1 72 0 1 9 1 8 1 51 6 1 31 42 32 42 82 9 2 7 2 6 2 53 0 2 3 & 2 ' ( ms b ms b dddddd dd d d ms b dddddd d d d dd d d d 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 byte 2 h i gh - i mp e d a n ce 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 6 7 $ 7 8 6 5 ( * , 6 7 ( 5 byte 2 byte 2 table 10-3. status regist er protection table srp1 srp0 wp status register description 0 0 x software protected the status register can be written to after a write enable instruction, wel=1.(factory default) 0 1 0 hardware protected wp =0, the status register is locked and cannot be written. 0 1 1 hardware unprotected wp =1, the status register is unlocked and can be written to after a write enable instruction, wel=1. 1 0 x power supply lock- down (1) 1. when srp1, srp0 = (1, 0), a power-down, power-up cycle will change srp1, srp0 to the (0, 0) state. status register is protected and cannot be written to again until the next power-down, power-up cycle. 1 1 x one time program status register is permanently protected and cannot be written to. 25 AT25SF041 ds-25sf041?044c?7/2014 10.1.3 wel bit the wel bit indicates the current status of the internal writ e enable latch. when the wel bit is in the logical ?0? state, the device will not accept any byte/page pr ogram, erase, program security register , erase security register, or write status register commands. the wel bit defaults to the logica l ?0? state after a device power-up or reset operation. in addition, the wel bit will be reset to the logical ?0? state automatically under the following conditions: ? write disable operation completes successfully ? write status register operation completes successfully or aborts ? program security register operation completes successfully or aborts ? erase security register operation completes successfully or aborts ? byte/page program operation completes successfully or aborts ? block erase operation completes successfully or aborts ? chip erase operation completes successfully or aborts if the wel bit is in the logical ?1? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete o r unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode for a byte/page program, erase, program security register, erase security register, or write status register command must have been clocked into the device. 10.1.4 rdy /bsy bit the rdy /bsy bit is used to determine whether or not an internal oper ation, such as a program or erase, is in progress. to poll the rdy /bsy bit to detect the completion of a program or erase cycle, new status register data must be continually clocked out of the device until the state of the rdy /bsy bit changes from a logical ?1? to a logical ?0?. 10.1.5 lb3, lb2, lb1 bits the lb3, lb2, and lb1 bits are used to determine if any of the three security register pages are locked. ? the lb3 bit is in the logical ?1? state if security register page-2 is locked and cannot be erased or programmed. ? the lb2 bit is in the logical ?1? state if security register page-1 is locked and cannot be erased or programmed ? the lb1 bit is in the logical ?1? state if security register page-0 is locked and cannot be erased or programmed. 10.1.6 qe bit the qe bit is used to determine if the device is in the quad enabled mode. if the qe bit is in the logical ?1? state, then the hold and wp pins functions as input/output pins similar to the si and so. if the qe bit is in the logical ?0? state, then the hold pin functions as an input only and the wp pin functions as an input only. 10.2 write status register (01h) the write status register command is used to modify the block protection, security register lock-down, quad enable, and status register protection. before the write status register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device followed by one or two bytes of data. the first byte of data consists of the srp0, sec, tb, bp2, bp1, bp0 bit values and 2 dummy bits. the second byte is optional and consists of 1 dummy bit, the cmp, lb3, lb2, lb1, 1 dummy bit, the qe, and 1 dummy bit. when the cs pin is deasserted, the bit values in the status register will be modified, and the wel bit in the status register will be reset back to a logical ?0?. the complete one byte or two bytes of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the status register bits will not change, memory protection status will not change, and the wel bit in the status register will be reset back to the logical ?0? state 26 AT25SF041 ds-25sf041?044c?7/2014 table 10-4. write status register format. figure 10-3. write status register 10.3 write enable for volati le status register (50h) the non-volatile status register bits de scribed in table 10-1 and table 10-2 can also be written to as volatile bits. during power up reset, the non-volatile status register bits are copied to a volatile version of the status register that is used during device operation. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the status register non- volatile bits. to write the volatile version of the status register bits, th e write enable for volatile status register (50h) instruction must be issued prior to each write status registers (01h) instruction. write enable for volatile status register instruction will not set the write enable latch bit. it is only valid for the next following write status registers instruction, to change the volatile status register bit values. figure 10-4. write enable for volatile status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srp0 sec tb bp2 bp1 bp0 wel rdy /bsy si sck so cs msb 23 1 0 00000001 67 5 41011 9 819 17 18 16 opcode dddd status register in - byte 1 msb 23 21 22 20 14 15 13 12 dddd dddd status register in - byte 2 dddd high-impedance table 10-5. write status register byte 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved cmp lb3 lb2 lb1 reserved qe srp1 6 & . & 6 6 , 6 2 ms b 23 1 0 67 5 4 op cod e h i gh - i mp e d a n ce 27 AT25SF041 ds-25sf041?044c?7/2014 11. other commands and functions the AT25SF041 supports three different commands to access device identification that indicates the manufacturer, device type, and memory density. the returned data bytes provide information as shown in table 11-1. 11.1 read manufacturer and device id (9fh) identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. since not all flash devices are capable of operating at ve ry high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure all devices used in the application can be identified properly. once the identification process is complete, the application can increase the clock frequency to accommodate specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 11-2. manufacturer and device id information table 11-1. manufacturer and device id information instruction opcode manufacturer id device id (part 1) device id (part 2) read manufacturer and device id 9fh 1fh 84h 01h read id (legacy command) 90h 1fh 12h resume from deep power-down and read device id abh 12h byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 84h 3 device id (part 2) 01h table 11-3. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for adesto) 0 0 0 1 1 1 1 1 device id (part 1) family code density code 84h family code:100 (at25sfxxx series) ? density code: 00100 (4-mbit) 1 0 0 0 0 1 0 0 device id (part 2) sub code product version code 01h sub code: 000 (standard series) ? product version: 00001 0 0 0 0 0 0 0 1 28 AT25SF041 ds-25sf041?044c?7/2014 figure 11-1. read manufacturer and device id 11.2 read id (legacy command) (90h) identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the preferred method for doing so is the jedec standard ?the AT25SF041 supports three different commands to access device identification that indicates the manufacturer, device type, and memory density. the returned data bytes provide information as shown in table 11-1.? method described in section on page 27 ; however, the legacy read id command is supported on the AT25SF041 to enable backwards compatibility to previous generation devices. to read the identification information, the cs pin must first be asserted and the opcode of 90h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id of 1fh followed by a single byte of data representing a device code of 12h. after the device code is output, the sequence of bytes will repeat. deasserting the cs pin will terminate the read id operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data read. figure 11-2. read id (legacy command) 11.3 deep power-down (b9h) during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consumption state called the deep power-down mode. sck cs si so 6 0 9fh 8 7 opcode 1fh 84h 01h manufacturer id device id byte1 device i d byte2 high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits) sck cs si so ms b 23 1 0 0010 0 67 5 41 01 1 9 81 22 12 2 1 72 0 1 9 1 8 1 51 6 1 31 4 op cod e ms b 011111 0 0 ms b 0 0 ma n u f a ct u r e r i d d e v i ce cod e h i gh - i mp e d a n ce 29 AT25SF041 ds-25sf041?044c?7/2014 when the device is in the deep power-down mode, all co mmands including the read status register command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection me chanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an byte boundary (multiples of eight bits); otherwise, the device w ill abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power-cycle. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. figure 11-3. deep power-down 11.4 resume from deep power-down (abh) in order to exit the deep power-down mode and resume nor mal device operation, the resume from deep power-down command must be issued. the resume from deep power-down command is the only command that the device will recognize while in the deep power-down mode. to resume from the deep power-down mode, the cs pin must first be asserted and the opcode of abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power-down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, or if the cs pin is not deasserted on an byte boundary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. 6 & . & 6 6 , 6 2 0 6 % , & & 2 3 & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( 6 w d q g e \ 0 r g h & x u u h q w $ f w l y h & x u u h q w ' h h s 3 r z h u ' r z q 0 r g h & x u u h q w w ( ' 3 ' 30 AT25SF041 ds-25sf041?044c?7/2014 figure 11-4. resume from deep power-down 11.4.1 resume from deep power-down and read device id (abh) the resume from deep power-down command can also be used to read the device id. when used to release the device from the power-down state and obtain the device id, the cs pin must first be asserted and opcode of abh must be clocked into the device, followed by 3 dummy bytes. the device id bits are then shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure 11-4. this command only outputs a single byte device id. the device id value for the AT25SF041 is listed in table 11-1. after the last bit (bit 0) of the device id has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the cs pin remains asserted and the sck pin is being pulsed. after cs is deasserted it must remain high for a time duration of t rdpo before new commands can be received. the same instruction may be used to read device id when not in power down. in that case, /cs does not have to remain high remain after it is deasserted. figure 11-5. resume from deep power-down and read device id 6 & . & 6 6 , 6 2 ms b , & & 23 1 0 10101011 67 5 4 op cod e h i gh - i mp e d a n ce d e e p p o w e r - d o w n mo d e cu r r e n t a c t i v e cu r r e n t st a n d b y mo d e cu r r e n t t r d p d 6 & . & 6 6 , 6 2 ms b , & & 23 1 0 10101011 67 5 4 op cod e h i gh - i mp e d a n ce ' h h s 3 r z h u ' r z q 0 r g h & x u u h q w a c t i v e cu r r e n t 31 32 30 29 38 39 37 35 36 34 33 xx xxx ' 8 0 0 < % < 7 ( 6 w 5 ' 3 2 msb dddd dddd ' ( 9 , & ( , ' 6 w d q g e \ 0 r g h & x u u h q w 31 AT25SF041 ds-25sf041?044c?7/2014 11.5 hold function the hold pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. therefore, if an erase cycle is in progress, asserting the hold pin will not pause the operation, and the erase cycle will continue until it is finished. if the qe bit value in the status register has been set to logical ?1?, then the hold pin does not function as a control pin. the hold pin will function as an output for quad-output read and input/output for quad-i/o read. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won?t be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pin will be in a high-impedance state. in addition, both the si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the hold pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, then the ho ld mode won?t end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the wel bit in t he status register back to the logical ?0? state. figure 11-6. hold mode sck cs hold hold hold hold 32 AT25SF041 ds-25sf041?044c?7/2014 12. electrical specifications 12.3 dc characteristics 12.1 absolute maximum ratings* temperature under bias. . . . . . . . . . . . . -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability. storage temperature . . . . . . . . . . . . . . . -65 ? c to +150 ? c all input voltages (including nc pins) ? with respect to ground . . . . . . . . . . . . . . -0.6v to +4.1v all output voltages ? with respect to ground . . . . . . . . . . -0.6v to v cc + 0.5v 12.2 dc and ac operating range AT25SF041 operating temperature (case) industrial -40 ? c to 85 ? c v cc power supply 2.5v to 3.6v symbol parameter condition 2.5v to 3.6v units min typ max i dpd deep power-down current cs , hold , wp = v ih ? all inputs at cmos levels 2 5 a i sb standby current cs , hold , wp = v ih ? all inputs at cmos levels 13 25 a i cc1 (1) active current, read (03h, 0bh) operation f = 20mhz; i out = 0ma 3 6 ma f = 50mhz; i out = 0ma 4 7 ma f = 85mhz; i out = 0ma 5 8 ma i cc2 (1) active current,(3bh, bbh ? read operation (dual) f = 50mhz; i out = 0ma 5 8 ma f = 85mhz; i out = 0ma 6 10 ma i cc3 (1) active current,(6bh, ebh ? read operation (quad) f = 50mhz; i out = 0ma 6 10 ma f = 85mhz; i out = 0ma 8 12 ma i cc4 (1) active current, ? program operation cs = v cc 10 16 ma i cc5 (1) active current, ? erase operation cs = v cc 10 16 ma 33 AT25SF041 ds-25sf041?044c?7/2014 i li input load current all inputs at cmos levels 1 1 a i lo output leakage current all inputs at cmos levels 1 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6ma; v cc = 2.5v 0.4 v v oh output high voltage i oh = -100a v cc - 0.2v v 1. typical values measured at 3.0v @ 25c for the 2.5v to 3.6v range 12.4 ac characteristics - m aximum clock frequencies symbol parameter 2.5v to 3.6v 2.7v to 3.6v units min typ max min typ max f clk maximum clock frequency for all operations ? (excluding 0bh opcode) 104 104 mhz f rdlf maximum clock frequency for 03h opcode 50 50 mhz f rdhf maximum clock frequency for 0bh opcode 70 85 mhz f rddo maximum clock frequency for 3b, bbh opcode 70 85 mhz f rdqo maximum clock frequency for 6b, ebh opcode 70 85 mhz 12.5 ac characteristics - all other parameters symbol parameter 2.5v to 3.6v 2.7v to 3.6v units min typ max min typ max t clkh clock high time 5 5 ns t clkl clock low time 5 5 ns t clkr (1) clock rise time, peak-to-peak (slew rate) 0.1 0.1 v/ns t clkf (1) clock fall time, peak-to-peak (slew rate) 0.1 0.1 v/ns t csh chip select high time 10 10 ns t csls chip select low setup time (relative to clock) 5 5 ns t cslh chip select low hold time (relative to clock) 5 5 ns t cshs chip select high setup time (relative to clock) 5 5 ns symbol parameter condition 2.5v to 3.6v units min typ max 34 AT25SF041 ds-25sf041?044c?7/2014 t cshh chip select high hold time (relative to clock) 5 5 ns t ds data in setup time 2 2 ns t dh data in hold time 2 2 ns t dis (1) output disable time 7 6 ns t v output valid time (03h, 0bh) 7 6 ns output valid time (3bh, bbh - dual) 7 7 output valid time (6bh, ebh - quad) 8 8 t oh output hold time 0 0 ns t hls hold low setup time (relative to clock) 5 5 ns t hlh hold low hold time (re lative to clock) 5 5 ns t hhs hold high setup time (relative to clock) 5 5 ns t hhh hold high hold time (relative to clock) 5 5 ns t hlqz (1) hold low to output high-z 6 6 ns t hhqz (1) hold high to output high-z 6 6 ns t wps (1) (2) write protect setup time 20 20 ns t wph (1)(2) write protect hold time 100 100 ns t edpd (1) chip select high to deep power-down 1 1 s t rdpd (1) chip select high to standby mode 5 5 s t rdpo (1) resume deep power-down, cs high to id 5 5 s 1. not 100% tested (value guaranteed by design and characterization). 2. only applicable as a constraint for the write status register command when bpl = 1. 12.6 program and er ase characteristics symbol parameter 2.5v to 3.6v min typ max units t pp (1) page program time (256 bytes) 0.7 2.5 ms t bp byte program time 5 s t blke (1) block erase time 4 kbytes 60 300 ms 32 kbytes 300 1300 64 k bytes 500 2200 t chpe (1) (2) chip erase time 4 10 sec 12.5 ac characteristics - all other parameters symbol parameter 2.5v to 3.6v 2.7v to 3.6v units min typ max min typ max 35 AT25SF041 ds-25sf041?044c?7/2014 t srp (1) security register program time 2.5 ms t srp (1) security register erase time 15 ms t wrsr (2) write status register time 15 ms 1. maximum values indicate worst-case per formance after 100,000 erase/program cycles. 2. not 100% tested (value guaranteed by design and characterization). 12.7 power-up conditions symbol parameter min max units t vcsl minimum v cc to chip select low time 20 s t puw power-up device delay before program or erase allowed 10 ms v por power-on reset voltage 2.3 v 12.6 program and er ase characteristics symbol parameter 2.5v to 3.6v min typ max units 36 AT25SF041 ds-25sf041?044c?7/2014 12.8 input test waveforms and measurement levels 12.9 output test load 13. ac waveforms figure 13-1. serial input timing figure 13-2. serial output timing ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2 ns (10% to 90%) device under test 30pf & 6 6 , 6 & . 6 2 0 6 % + , * + , 0 3 ( ' $ 1 & ( 0 6 % / 6 % w & 6 / 6 w & / . + w & / . / w & 6 + 6 w & 6 + + w ' 6 w ' + w & 6 / + w & 6 + & 6 6 , 6 & . 6 2 w 9 w & / . + w & / . / w ' , 6 w 9 w 2 + 37 AT25SF041 ds-25sf041?044c?7/2014 figure 13-3. wp timing for write status register command when bpl = 1 ? figure 13-4. hold timing ? serial input figure 13-5. hold timing ? serial output ? wp si sck so 000 high-impedance msb x t wps t wph cs lsb of write status register data byte msb of write status register opcode msb of next opcode cs si sck so t hhh t hls t hlh t hhs hold high-impedance cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx 38 AT25SF041 ds-25sf041?044c?7/2014 14. ordering information 14.1 ordering code detail ordering code (1) (2) 1. the shipping carrier option code is not marked on the devices. 2. dfn and tssop packages not currently in production. dfn and tsso p package part numbers, lead fi nish materials and package out line drawings are subject to change. package operating voltage max. freq. (mhz) operation range AT25SF041-sshd-b 8s1 2.5v to 3.6v 85mhz industrial (-40c to +85c) AT25SF041-sshd-t AT25SF041-shd-b 8s2 AT25SF041-shd-t AT25SF041-mhd-t 8ma1 AT25SF041-mahd-t 8ma3 AT25SF041-xmhd-t 8x package type 8s1 8-lead, 0.150" wide, plastic gull wi ng small outline package (jedec soic) 8s2 8-lead, 0.208" wide, plastic gull wi ng small outline package (eiaj soic) 8ma1 8-pad (5 x 6 x 0.6mm body), thermally enhanced plastic ultra thin dual flat no-lead (udfn) 8ma3 8-pad (2 x 3 x 0.6mm body), thermally enhanced plastic ultra thin dual flat no-lead (udfn) 8x 8-lead (4 x 4 mm body), thin shrink small outline package (tssop) at2 5s 0 4 ss d hb 1? ? f designator product family device density 04 = 4-megabit interface 1 = serial package option m = 8-pad, 5 x 6 x 0.6 mm udfn ma = 8-pad, 2 x 3 x 0.6 mm udfn ss = 8-lead, 0.150" wide soic s = 8-lead, 0.208" wide soic xm = 8-lead tssop device grade h = green, nipdau lead finish, industrial temperature range (?40c to +85c) shipping carrier option b = bulk (tubes) t = tape and reel operating voltage d = 2.5v to 3.6v 39 AT25SF041 ds-25sf041?044c?7/2014 15. packaging information 15.1 8s1 ? 8-lead, .150? jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? ? e e 1 1 n n top view t o p v i e w c c e1 e 1 end view a a b b l l a1 a 1 e e d d side view s i d e v i e w package drawing contact: contact@adestotech.com ? 8s1 f 5/19/10 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb 40 AT25SF041 ds-25sf041?044c?7/2014 15.2 8s2 ? 8-lead, .208? eiaj soic title drawing no. gpc rev. package drawing contact: contact@adestotech.com ? 8s2 stn f 8s2, 8-lead, 0.208? body, plastic small outline package (eiaj) 4/15/08 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs aren't included. 3. determines the true geometric position. 4. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 4 c 0.15 0.35 4 d 5.13 5.35 e1 5.18 5.40 2 e 7.70 8.26 l 0.51 0.85 0 8 e 1.27 bsc 3 1 1 n n e e top view t o p v i e w c c e1 e 1 end view e n d v i e w a a b b l l a1 a 1 e e d d side view s i d e v i e w 41 AT25SF041 ds-25sf041?044c?7/2014 15.3 8ma1 ? udfn note: subject to change. title drawing no. gpc rev. package drawing contact: contact@adestotech.com ? 8ma1 yfg d 8ma1, 8-pad (5 x 6 x 0.6 mm body), thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max note a 0.45 0.55 0.60 a1 0.00 0.02 0.05 b 0.35 0.40 0.48 c 0.152 ref d 4.90 5.00 5.10 d2 3.80 4.00 4.20 e 5.90 6.00 6.10 e2 3.20 3.40 3.60 e 1.27 l 0.50 0.60 0.75 y 0.00 ? 0.08 k 0.20 ? ? 4/15/08 pin 1 id top view e d a1 a side view y c bottom view e2 d2 l b e 1 2 3 4 8 7 6 5 pin #1 notch (0.20 r) 0.45 k pin #1 chamfer (c 0.35) option a (option b) 42 AT25SF041 ds-25sf041?044c?7/2014 15.4 8ma3 ? udfn title drawing no. gpc rev. package drawing contact: contact@adestotech.com ? 8ma3 ycq a 8ma3, 8-pad, 2 x 3 x 0.6 mm body, 0.5 mm pitch, 1.6 x 0.2 mm exposed pad, saw singulated thermally enhanced plastic ultra thin dual flat no lead package (udfn/uson) common dimensions (unit of measure = mm) symbol min nom max note a 0.45 ? 0.60 a1 0.00 ? 0.05 b 0.20 ? 0.30 d 1.95 2.00 2.05 d2 1.50 1.60 1.70 e 2.95 3.00 3.05 e2 0.10 0.20 0.30 e ? 0.50 ? l 0.40 0.45 0.50 l3 0.30 ? 0.40 ccc ? ? 0.05 eee ? ? 0.05 8/8/08 notes: 1. all dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.05 mm. 3. warpage shall not exceed 0.05 mm. 4. package length/package width are considered as special characteristic. 5. refer to jede mo-236/mo-252 1 4 8 5 b e2 d2 8x c 0.10 mm b a r0.10 l3 0.10 ref. e 1.50 ref. r0.125 d 1 4 pin 1 id e 5 b a a1 a 0.127 ref. c c eee ccc 8x c 23 6 7 8 l // 43 AT25SF041 ds-25sf041?044c?7/2014 15.5 8x ? tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. h 8x e 12/8/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1 package drawing contact: contact@adestotech.com ? 44 AT25SF041 ds-25sf041?044c?7/2014 16. revision history revision level ? release date history a ? april 2014 initial release. document posted to public website. b ? may 2014 updated memory array protection bits: address range 07e000h- 07ffffh. removed tray shipping ca rrier option from dfn packages (-y). removed erase suspend and resume feature. c ? july 2014 removed quad input references on pin descriptions. corrected opcode reference for read array; obh uses f rdhf . corrected document control number (ds-25sf041). removed tssop bulk shipping option. removed preliminary status. 45 AT25SF041 ds-25sf041?044c?7/2014 corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2014 adesto technologies. all rights reserved. / rev.: ds-25sf041?044c?7/2014 disclaimer: adesto technologies corporation makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty which is detailed in adesto's terms and conditions located on the company's web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no lic enses to patents or other intellectual property of adesto are granted by the company in connection with the sale of adesto products, expressly or by implication. adesto's products are not authorized for u se as critical components in life support devices or systems. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners. |
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