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eu a2112 ds21 12 v er0.1 apr. 2010 1 25-w mono class-d a udio p o w er amplifier with speaker protection descript ion the eua21 12 is a hi gh efficiency, one channel bridged-tied load (btl), class-d audio power amplifier. operating from a 24v power supply, eua2112 is capable of delivering 25w of continuous output power to a 8 ? load with 10% thd+n. the eua2112 features a differential input architecture offering improved noise immunity over a single-ended (se) input amplifier. amplifier gain is internally configured and can be selected to 20, 26, 32 or 36db utilizing the go and g1 gain select pins. advanced emi suppression technology enables the use of inexpensive ferrite bead at the outputs while meeting emc requirements. the speaker protection circuitry is integrated into eua2112 to limit the amount of current through the speaker. the eua2112 also features short-circuit and thermal protection preventing the device from being damaged during a fault condition. the eua2112 is available in thermally efficient 28-pin tssop package. fea tures z w ide su pp ly voltage: 8v to 26v z unique modulation scheme reduces emi emission z 25w into an 8- ? load from a 24-v supply z 20w into a 4- ? load from a 12-v supply z 94% efficient class-d operation eliminates need for heat sinks z four selectable, gain settings z differential inputs z speaker protection circuitry z thermal and short-circuit protection z 28-pin tssop package with thermal pad z rohs compliant and 100% lead(pb)-free halogen-free applica tions z t elevisi ons t ypical application cir cuit figur e1. simplified application schematic v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 2 pin configurations package type pin configurations tssop-28 pin description pin tssop-28 i/o/p description sd 1 i shutdown logic input for audio amp (low = outputs hi-z, high = outputs enabled). ttl logic levels with compliance to avcc. fault 2 o open drain output used to display short circuit or dc detect fault status. voltage compliant to avcc. short circuit faults can be set to auto-recovery by connecting fault pin to sd pin. otherwise, both short circuit faults and dc detect faults must be reset by cycling pvcc. gnd 3,4 i connect to local ground. gain0 5 i gain select least significa nt bit. ttl logic levels with compliance to avcc. gain1 6 i gain select most significant bit. ttl logic levels with compliance to avcc. avcc 7,14 p analog supply agnd 8 p analog signal ground. connect to the thermal pad. gvdd 9 o high-side fet gate drive supply. nominal voltage is 4.5v. also should be used as supply for plimit function. plimit 10 i power limit level adjust. connect a resistor divider from gvdd to gnd to set power limit. connect directly to gvdd for no power limit. inn 11 i negative audio input. biased at 2.25v. inp 12 i positive audio input. biased at 2.25v. nc 13 p not connected pvcc 15,16,27,28 p power supply h-bridge. pvcc pins are connect internally. bsp 17,21 i bootstrap i/o for positive high-side fet. outp 18,20 o class-d h-bridge positive output. pgnd 19,24 power ground for the h-bridges. bsn 22,26 i bootstrap i/o for negative high-side fet. outn 23,25 o class-d h-bridge negative output. n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 3 ordering information order number package type marking operating temperature range EUA2112QIR1 tssop-28 xxxxx eua2112 -40 c to +85c eua2112 ?? ?? ?? ?? lead free code 1: lead free, halogen free 0: lead packing r: tape & reel operating temperature range i: industry standard package type q:tssop n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 4 absolute maximum ratings t supply voltage, avcc,pvcc, ----------------------------- -------------------------------------------- -0.3 v to 30v t input voltage, sd ,gain0,gain1,pbtl, fault ----------------------------------------- -0.3 v to v cc +0.3v t input voltage, plimit ------------------------------------ ---------------------------------- -0.3 v to gvdd +0.3v t input voltage, rinn,rinp,linn,linp ---------------- --------------------------------------------- -0.3 v to 6.3v t thermal resistance ja (tssop-28) -------------------------------------------------------------------- 34 ??/w t free-air temperature range, t a --------------------------------------------------------------------- -40c to +85c t junction temperature range, t j -------------------------------------------------------------------- -40c to +150c t storage temperature rang, t stg ------------------------------------------------------------------- -65c to +150c t lead temperature ------------------------------------------------------------------------------------------ 260c t load resistance, r load ---------------------------------------------------------------------------------- 3.2 ? minimum t esd susceptibility (hbm) ------------ ---------------------- --------------------------------------- ------------ 2kv recommended operating conditions min max unit supply voltage, v cc pvcc,avcc 8 26 v high-level input voltage, v ih sd ,gain0,gain1,pbtl 2 v low-level input voltage, v il sd ,gain0,gain1,pbtl 0.8 v high-level input current, i ih sd ,gain0,gain1,pbtl,v i =2v,v cc =18v 50 a low-level input current, i il sd ,gain0,gain1,pbtl,v i =0.8v,v cc =18v 5 a low-level output voltage, v ol fault , r pull-up =100k, v cc =26v 0.8 v oscillator frequency, f osc 230 330 khz operating free-air temperature, t a -40 85 c dc characteristics t a = +25c ,v cc =24v, r l =8? (unless otherwise noted) eua2112 symbol parameter conditions min t yp max. unit os v class-d output offset voltage (measured differentially) v i = 0v, gain = 36db 5 50 mv i cc quiescent supply current sd =2v, no load, pv cc =24v 32 50 ma i cc(sd) quiescent supply current in shutdown mode sd =0.8v, no load, pv cc =24v 250 400 a high side 240 r ds (on) drain-source on-state resistance v cc =12v, i o =500ma, t j =25c low side 240 m ? gain0=0.8v 19 20 21 gain1=0.8v gain0=2v 25 26 27 db gain0=0.8v 31 32 33 g gain gain1=2v gain0=2v 35 36 37 db t on turn-on time sd =2v 28 ms t off turn-off time sd =0.8v 28 ms gvdd gate drive supply i gvdd =100a 4.2 4.5 4.8 v t dcdet dc detect time v (rinn) =5v, vrinp=0v 420 ms n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 5 dc characteristics t a = +25c ,v cc =12v, r l =8? (unless otherwise noted) eua2112 symbol parameter conditions min t yp max. unit os v class-d output offset voltage (measured differentially) v i = 0v,gain =36db 5 50 mv i cc quiescent supply current sd =2v, no load, pv cc =12v 20 35 ma i cc(sd) quiescent supply current in shutdown mode sd =0.8v, no load, pv cc =12v 200 1000 a high side 240 r ds (on) drain-source on-state resistance v cc =12v, i o =500ma, t j =25c low side 240 m ? gain0=0.8v 19 20 21 gain1=0.8v gain0=2v 25 26 27 db gain0=0.8v 31 32 33 g gain gain1=2v gain0=2v 35 36 37 db t on turn-on time sd =2v 28 ms t off turn-off time sd =0.8v 28 ms gvdd gate drive supply i gvdd =2ma 4.2 4.5 4.8 v v o output voltage maximum under plimit control v (plimit) =1.3v, v i =1vrms 6.75 7.90 8.75 v ac characteristics t a = +25c ,v cc =24v, r l =8 ? (unless otherwise noted) eua2112 symbol parameter conditions min t yp max. unit k svr power supply ripple rejection 200mv pp ripple at 1khz, gain= 20db, inputs ac-coupled to agnd -60 db p o continuous output power thd+n=10%, f=1khz, v cc =24v 25 w thd+n total harmonic distortion +noise v cc =24v, f=1khz, po=12.5w( half-power) 0.25 % 255 v vn output integrated noise 20hz to 22khz, a-weighted filter, gain=20db -71 dbv snr signal-to-noise ratio p o =12.5w, f=1khz,gain=20db, a-weighted 91 db f osc oscillator frequency 230 280 330 khz thermal trip point 150 c thermal hysteresis 30 c n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 6 ac characteristics t a = +25c ,v cc =12v, r l =8 ? (unless otherwise noted) eua2112 symbol parameter conditions min t yp max. unit k svr power supply ripple rejection 200mv pp ripple from 20hz ~1khz, gain= 20db, inputs ac-coupled to agnd -60 db thd+n=10%, f=1khz, v cc =12v, r l =4 ? 20 p o continuous output power thd+n=10%, f=1khz, v cc =12v, r l =8 ? 10 w thd+n total harmonic distortion +noise r l =8 ? , f=1khz, po=5w( half-power) 0.25 % 255 v vn output integrated noise 20hz to 22khz, a-weighted filter, gain=20db -71 dbv snr signal-to-noise ratio maximum output at thd+n< 1%, f=1khz,gain=20db, a-weighted 90 db f osc oscillator frequency 230 280 330 khz thermal trip point 150 c thermal hysteresis 30 c block diagram figure2. n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 7 typical characteristics figure3. figure4. figure5. figure6. figure7. figure8. n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 8 figure9. figure10. figure11. figure12. figure13. figure14. n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 9 figure15. figure16. n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 10 application information differential input the differential input stage of the amplifier cancels any comm on-mode noise that appears on both input lines of the audio channel. to use the eua2112 with a differential source, connec t the positive signal of the audio source to the inp pin and the negative signal from the audio source to the inn pin (figure 17). figure 17. differential input single-ended input when using an audio source with a sing le-ended ?out?, it is important to connect the rinn and linn pins to the gnd of the audio source with coup ling capacitors. (figure 18). figure 18. single ended input n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 11 gain selection the gain of the eua2112 is set by two input terminals, gain0 and gain1. the gains listed in table 1 are realized by changing the taps on the input resistors a nd feedback resistors inside the amplifier. this causes the input impedance (z i ) to be dependent on the gain setting. the actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. however, the input impedance from part-to-part at the same gain may shift by 20% due to shifts in the actual resist ance of the input resistors. for design purposes, the input network should be designed assuming an input impedance of 40 k ? , which is the absolute minimum input impedance of the eua2112. at the lower gain settings, the input impedance could increase as high as 120 k ? . table.1 gain setting amplifier gain (db) input impedance (k ? ) gain1 gain0 typ typ 0 0 20 100 0 1 26 50 1 0 32 50 1 1 36 50 sd operation connect sd to a logic high for normal operation. pulling sd low causes the outputs to mute and the amplifier to enter a low-current state. never leave sd unconnected, because amplifier operation would be unpredictable. for the best power-off pop performance, place the amplifier in the shutdown prior to removing the power supply voltage. plimit the voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail. add a resistor divider from gvdd to ground to set the voltage at the plimit pin. an exte rnal reference may also be used if tighter tolerance is required. also add a 1f capacitor from pin 10 to ground. the plimit circuit sets a limit on the output peak-to-peak voltage. the limiting is done by limiting the duty cycle to fixed maximum value. this limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to pvcc. this "virtual" rail is 6 times the voltage at the plimit pin. this output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. ---------------- (1) for unclipped power where: r s is the total series resistance including r ds(on) , and any resistance in the output filter. r l is the load resistance. v p is the peak amplitude of the output possible within the supply rail. v p = 6.6 plimit voltage if plimit < 6.6 v p p out (10%thd) = 1.25 p out (unclipped) table.2 plimit typical operation test conditions() plimit voltage output power (w) output voltage amplitude (v p-p ) pvcc=24v, vin=1vrms, r l =4 ? , gain=20db 4.5 25.87 28.8 pvcc=24v, vin=1vrms, r l =4 ? , gain=20db 1.24 13.48 20.7 pvcc=24v, vin=1vrms, r l =4 ? , gain=20db 0.8 6.46 18.2 pvcc=12v, vin=1vrms, r l =4 ? , gain=20db 4.5 18.72 24.4 pvcc=12v, vin=1vrms, r l =4 ? , gain=20db 1.13 11.7 19.3 pvcc=12v, vin=1vrms, r l =4 ? , gain=20db 0.77 6.08 13.9 gvdd supply the gvdd supply is used to power the gates of the output full bridge transistors. it can also be used to supply the plimit voltage divider circuit. add a 1f capacitor to ground at this pin. dc detect eua2112 has circuitry which will protect the speakers from dc current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. a dc detect fault will be reported on the fault pin as a low state. the dc detect fault will also cause the amplifier to shutdown by changing the state of the outputs to hi-z. to clear the dc detect it is necessary to cycle the pvcc supply. cycling sd will not clear a dc detect fault. a dc detect fault is issued when the output differential duty-cycle of either channel exceeds 20% (for example, +60%, -40%) for more than 420 msec at the same polarity. this feature protects the speaker from large dc currents or ac currents less than 2hz. to avoid nuisance faults due to the dc detect circuit, hold the sd pin low at l r2 2 p v s r2 l r l r out p + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 12 power-up until the signals at the inputs are stable. also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance dc detect faults. short-circuit protection and automatic recovery feature the eua2112 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-gnd shorts, and output-to-vcc shorts. when a short circuit is detected on the outputs, the part immediately disables the output drive. this is a latched fault and must be reset by cycling the voltage on the shutdown pin or mute pin. this clears the short-circuit flag and allows for normal operation if the short was removed. if the short was not removed, the protection circuitry again activates. thermal protection thermal protection on the eua2112 prevents damage to the device when the intern al die temperature exceeds 150 o c. there is a 10 o c tolerance on this trip point from device to device. once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. this is not a latched fault. the thermal fault is cleared once the temperature of the die is reduced by 30 o c. the device begins normal operation at this point with no external system interaction. input resistance changing the gain setting can vary the input resistance of the amplifier from its smallest value, 50 k ? 20%, to the largest value, 100 k ? 20%. as a result, if a single capacitor is used in the input high-pass filter, the -3 db or cutoff frequency may change when changing gain steps. the -3db frequency can be calculated using equation 2. use the z i values given in table 1. ---------------- (2) input capacitor, c i in the typical application, an input capacitor (c i ) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. in this case, c i and the input impedance of the amplifier (z i ) form a high-pass filter with the corner frequency determined in equation 3. ----------------- (3) the value of c i is important, as it directly affects the bass (low-frequency) performance of the circuit. consider the example where z i is 50 k ? and the specification calls for a flat bass response down to 20 hz. equation 3 is reconfigured as equation 4. ----------------- (4) in this example, c i is 0.16 f; so, one would likely choose a value of 0.22 f as this value is commonly used. if the gain is known and is constant, use z i from table 1 to calculate c i . power supply decoupling, c s the eua2112 is a high-performance cmos audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (thd) is as low as possible. power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. the optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. for higher frequency transients, spikes, or digital hash on the line, a good low equivale nt-series-resistance (esr) ceramic capacitor, typically 0.1 f to 1 f placed as close as possible to the device vcc lead works best. for filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 f or greater placed near the audio power amplifier is recommended. the 220 f capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. the pvcc terminals provide the power to the output transistors, so a 220 f or larger capacitor should be placed on each pvcc terminal. a 10 f capacitor on the avcc terminal is adequate. bsn and bsp capacitors the full h-bridge output stages use only nmos transistors, that require bootstrap capacitors for the high side of each output to turn on correctly. a 220nf~2.2uf ceramic capacitor, rated for at least 25v, must be connected from each output to its corresponding bootstrap input. (see application circuit diagram in figure 17,18.) the bootstrap capacitors connected between the bsx pins i c i z2 1 f = i c i z2 1 c f = c f i z2 1 i c = n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 13 and corresponding output function as a floating power supply for the high-side n-channel power mosfet gate drive circuitry. during each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side mosfets turned on. using low-esr capacitors use capacitors with an esr less than 100m ? for optimum performance. low-esr ceramic capacitors minimize the output resistance. for best performance over the extended temperature range, select x7r capacitors. output filter most applications require a ferrite bead filter. the ferrite filter reduces emi around 1 mhz and higher (fcc and ce only test radiated emissions greater than 30 mhz). when selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. use an lc output filter if there are low frequency (<1 mhz) emi-sensitive circuits and/or there are long wires from the amplifier to the speaker. when both an lc filter and a ferrite bead filter are used, the lc filter should be placed as close as possible to the ic followed by the ferrite bead filter. figure19. figure20. figure21. n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com
eua2112 ds2112 ver0.1 apr. 2010 14 package information tssop-28 millimeters inches symbols min. max. min. max. a - 1.20 - 0.047 a1 0.00 0.15 0.000 0.006 b 0.19 0.30 0.007 0.012 e1 4.40 0.173 d 9.60 9.80 0.378 0.386 d1 3.05 3.55 0.120 0.139 e 6.20 6.60 0.244 0.260 e2 2.62 3.12 0.103 0.122 e 0.65 0.026 l 0.45 0.75 0.018 0.030 n~n?t?m?w3^v?mw`r?y?b?g ?pqls? tel: 0755-8398 3377 / 135 9011 2223 http://www.gofotech.com v?mw`r?y?b? www.gofotech.com

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