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| MX29VS128F multiplexed, burst mode read while write flash memory MX29VS128F p/n: pm1679 rev. 1.2, feb. 13, 2014 http://
2 contents 1. features ........................................................................................................................................ 5 2. general information .............................................................................................................. 7 2-1. operating speeds .................................................................................................................. 7 2-2. ordering information ............................................................................................................ 7 2-3. part name description .......................................................................................................... 8 3. pin configuration / symbol description .......................................................................... 9 3-1. logic symbol ......................................................................................................................... 9 3-2. pin descriptions .................................................................................................................. 10 4. block diagram .......................................................................................................................... 11 4-1. block address structure ................................................................................................. 12 table 1-1. sector address table (top boot) ......................................................................................... 13 table 1-2. sector address table (bottom boot) ................................................................................... 15 5. bus operations ......................................................................................................................... 17 table 2. bus operations ....................................................................................................................... 17 5-1. status register .................................................................................................................... 18 table 3-1. status register .................................................................................................................... 18 table 3-2. status register - erase suspend ........................................................................................ 18 table 3-3. status register - erase status ............................................................................................ 19 table 3-4. status register - program status ........................................................................................ 19 table 3-5. status register - program suspend .................................................................................... 19 table 3-6. status register - protect status .......................................................................................... 20 5-2. blank check ......................................................................................................................... 20 5-3. non-burst (asynchronous) read operation ..................................................................... 20 5-4. burst (synchronous) read operation .............................................................................. 20 5-4-1. burst mode - continuous linear ................................................................................................ 21 table 4-1. address latency for 10-13 dummy cycles ......................................................................... 21 table 4-2. address latency for 9 dummy cycles ................................................................................ 21 table 4-3. address latency for 8 dummy cycles ................................................................................ 22 table 4-4. address latency for 7 dummy cycles ................................................................................ 22 table 4-5. address latency for 6 dummy cycles ................................................................................ 22 table 4-6. address latency for 5 dummy cycles ................................................................................ 22 table 4-7. address latency for 4 dummy cycles ................................................................................ 23 table 4-8. address latency for 3 dummy cycles ................................................................................ 23 5-4-2. linear burst mode - 8/16 word with wrap around .................................................................... 23 table 5. burst address groups ............................................................................................................ 23 5-4-3. reading memory array .............................................................................................................. 24 figure 1. back-to-back read/write cycle timings .............................................................................. 24 p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 3 5-5. program operation .............................................................................................................. 25 5-5-1. write buffer programming operation ......................................................................................... 26 5-5-2. accelerated program operations ............................................................................................... 26 table 6. write buffer programming command sequence ................................................................... 27 figure 2. write buffer programming operation .................................................................................... 27 5-6. erase operation .................................................................................................................. 28 5-6-1. sector erase ............................................................................................................................. 28 5-6-2. chip erase ................................................................................................................................ 28 5-6-3. accelerated sector erase .......................................................................................................... 28 figure 3. erase operation .................................................................................................................... 29 5-7. program/erase suspend/resume ...................................................................................... 29 5-7-1. program suspend/program resume ......................................................................................... 29 5-7-2. erase suspend/erase resume ................................................................................................. 30 5-8. confguration register table 7. confguration register ............................................................................................................ 31 5-8-1. set confguration register command sequence ...................................................................... 32 5-8-2. confgurable dummy cycle ....................................................................................................... 32 5-8-3. burst length confguration ........................................................................................................ 32 table 8. confguration dummy cycles vs frequency .......................................................................... 33 5-8-4. output drive strength ................................................................................................................ 33 figure 4. example of programmable dummy cycles .......................................................................... 33 5-9. enter/exit secured silicon sector command sequence ................................................. 34 5-9-1. program secured silicon sector command sequence ............................................................. 34 5-10. handshaking feature .......................................................................................................... 34 6. security features .................................................................................................................. 35 6-1. sector protect/un-protect ................................................................................................... 35 6-2. sector protect range .......................................................................................................... 35 6-3. hardware protect ................................................................................................................. 35 6-4. sss lock bits ...................................................................................................................... 36 6-5. secured silicon sector flash memory region .............................................................. 36 6-5-1. factory locked region: secured silicon sector programmed and protected at the factory ... 36 6-5-2. customer lockable region: secured silicon sector not programmed or protected at the factory ....... 37 7. command definitions ............................................................................................................. 38 8. energy saing mode .............................................................................................................. 41 8-1. standby mode ...................................................................................................................... 41 8-2. automatic sleep mode ........................................................................................................ 41 8-3. output disable ..................................................................................................................... 41 table 9. dc characteristics .................................................................................................................. 42 8-3-1. hardware reset ......................................................................................................................... 43 p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 4 table 10. hardware reset .................................................................................................................... 43 figure 5. reset timings ....................................................................................................................... 43 8-3-2. software reset .......................................................................................................................... 43 9. deice id and common flash memory interface (cfi) mode ....................................... 44 table 11-1. id/cfi mode: device id ..................................................................................................... 44 table 11-2. id/cfi mode: identifcation data values ............................................................................ 45 table 11-3. id/cfi mode: system interface data values ..................................................................... 45 table 11-4. cfi mode: device geometry data values ......................................................................... 46 table 11-5. cfi mode: primary vendor-specifc extended query data values ................................... 47 table 11-6. cfi mode: id/cfi data ..................................................................................................... 48 10. electrical characteristics ............................................................................................... 49 10-1. absolute maximum stress ratings ................................................................................... 49 10-2. operating temperatures and oltages .............................................................................. 49 10-3. test conditions .................................................................................................................... 50 figure 6. test setup ............................................................................................................................. 50 figure 7. input waveforms and measurement levels .......................................................................... 50 10-4. ac characteristics .............................................................................................................. 51 figure 8. vcc power-up diagram ....................................................................................................... 51 figure 9. deep power down mode waveform .................................................................................... 52 figure 10. clk characterization .......................................................................................................... 52 table 12. synchronous / burst read .................................................................................................... 53 figure 11. burst mode read ................................................................................................................ 53 table 13. asynchronous read ............................................................................................................. 54 figure 12. asynchronous mode read .................................................................................................. 54 table 14. erase/program operations ................................................................................................... 55 figure 13. program operation timings ................................................................................................ 56 figure 14. chip/sector erase operations ............................................................................................ 57 figure 15. 8-, 16-word linear burst address wrap around ................................................................. 58 figure 16. latency with boundary crossing ........................................................................................ 58 10-5. erase and programming performance .............................................................................. 59 10-5-1. bga ball capacitance ............................................................................................................. 60 10-6. low cc write prohibit ...................................................................................................... 60 10-6-1. write pulse "glitch" protection ................................................................................................ 60 10-6-2. logical prohibit ........................................................................................................................ 60 10-6-3. power-up sequence ................................................................................................................ 60 10-6-4. power-up write prohibit ........................................................................................................... 60 10-6-5. power supply decoupling ........................................................................................................ 60 11. package information ............................................................................................................. 61 12. reision history ...................................................................................................................... 62 p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 5 128m-bit [8m x16-bit] cmos 1.8 volt, multiplexed, burst mode flash memory performance high performance v:rugsurudpplqwlph v(iihfwlyhzrugsurudpplqwlph xwlol]lqdzrug:ulwhxiihudw9&& ohyho v(iihfwlyhzrugsurudpplqwlph of utilizing a 32 word write buffer at acc ohyho sector erase time pviru.zrugvhfwruv pviru.zrugvhfwruv read access time xuvwdffhvvwlphqvdwlqgxvwuldo temperature range) fkurrxudgrpdffhwlph 6fkurrxudgrpdffhwlph secure silicon sector region zrugviruwkhidfwrufxvwrphu secure silicon sector power dissipation 7slfdoydoxhvelwvvzlwfklq cl = 10 pf at 108 mhz, cin excluded pirurwlxrxexuwuhdgprgh piru3urjudp(udh2shudwlrpd[ xiru6wdgeprgh program/erase cycles ffohvwslfdo data retention hduv 1. features characteristics burst length xuvw0rgh&rqwlqxrxvolqhdu /lqhduexuvwohqwkzrugzlwkzuds around sector architecture 0xowledqnufklwhfwxuhedqnv 5hdgzklohzulwhrshudwlrq )rxu.zrugvhfwruvrqwrserwwrpri address range hfwruduh.:rughfwru power supply operations 9iruuhdgsurudpdqghudvh rshudwlrqv9wr9 hhssrzhugrzqprgh p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 6 hardware features ? supports multiplexing data and address for reduced i/o count. ? a15Ca0 multiplexed as q15Cq0 sector architecture hardware sector protection - all sectors locked when wp#/acc = vil package ? 56-ball thin fbga (fine-pitch ball grid array) ? all packaged devices are rohs compliant and halogen-free. handshaking feature ? allows system to determine the read operation of burst data with minimum possible latency by monitoring rdy. software features advanced security features ? volatile sector protection ? a command sector protection method that protects individual sectors from being programmed or erased. ? secured silicon sectors can be locked or in-system at vcc level. electronic identifcation ? software command set compatible with jedec 42.4 standards ? common flash interface (cfi) supported erase suspend/erase resume ? erase operation will be halted when the bank receives an erase suspend command. and will be restarted when the bank receives the erase resume command. program suspend/program resume ? program operation will be halted when the bank receives a program suspend command. it will be restarted when the bank receives the program resume command. write condition bits ? provides a software method of providing write condition bits to indicate the status of program and erase operations. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 7 2. general information 2-1. operating speeds clock speed burst access (ns) synch. initial access (ns) asynch. initial access (ns) output loading 108 mhz 7 75 80 10 pf the operating temperature range is from -40c to +85c. 2-2. ordering information part number access t ime (ns) package remark MX29VS128Ftxji-80g (t op boot) 80 56 tfbga vi/o=vcc MX29VS128Fbxji-80g (bottom boot) 80 56 tfbga vi/o=vcc : MX29VS128F is for the validation of mcp products. please contact macronix local sales for product support . p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 8 2-3. part name description g: rohs compliant & halogen-free speed: 80: 80ns t emperature range: i: indsustrial -40c ~ +85c package: xj: tfbga revision: f mx 29 vs 128 f t xj i - 80 g density & mode: 128: 128mb vs: 1.8v burst mode (with read while write) device: 29: flash brand: mx product t ype t : t op boot b: bottom boot p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 9 3. pin configuration / symbol description 56-ball thin fbga 16 i/o a/q0-15 rdy a16-amax ce# oe# we# reset# a vd# vi/o clk wp#/acc vssq 3-1. logic symbol a1 rdy d4 a21 d5 v ss d6 clk d7 v cc d8 we# d9 wp#/acc d10 a19 d11 a17 d12 a22 e3 v i/o e4 a16 e5 a20 e6 avd# e7 nc e8 reset# e9 dnu e10 a18 e11 ce# e12 v ss v ss f4 a/q7 f5 a/q6 f6 a/q1 3 f7 a/q1 2 f8 a/q3 f9 a/q2 f10 a/q9 f11 a/q8 f12 oe# g3 a/q15 g4 a/q14 g5 v ssq g6 a/q5 g7 a/q4 g8 a/q11 g9 a/q10 g10 v i/o g11 a/q1 g12 a/q0 f3 nc nc nc nc nc nc nc nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k c3 c4 d3 c7 c8 c11 c12 h3 h4 h7 h8 h11 h12 a14 k1 k14 nc nc nc nc p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 10 3-2. pin descriptions symbol descriptions a22-a16 input pins for address a/q15~ a/q0 input pins for address and multiplex input/output pins for data wp#/acc write protect/input pin for programming acceleration avd# an input pin for address valid, to indicate the following input are address information or data information. (a/q15~a/q0 are multiplex pins and a22~a16 are address pins only) vil asynchronous mode to indicate valid address burst mode to latch starting address on rising edge of clk vih data will be inputted from a/q15~a/q0, a22~a16 will be ignored by device. ce# input pin for chip enable clk the frst rising edge of clk pin will start when both avd# low latches address input and activates burst mode operation. nc no connection oe# input pin for output enable reset# input pin for hardware reset, reset operation starts when voltage goes low . rdy output pin for ready signal. for further information please refer to confguration register table. vcc power supply pin (1.70v~1.95v) for device vi/o power supply pin (1.70v~1.95v) for input/output we# input pin for write enable vss ground pin for device vssq ground pin for input/output dnu do not use (dnu pin can be connected to vcc, ground, floating, but cannot connect to voltage > 1.5vcc) notes : 1. wp#/acc=vhv enters into the acc programming mode. wp#/acc=vil, erase/program function disabled. wp#/acc should keep vih for all other cases. it must not be left foated or unconnected; inconsistent behavior of the device may result. 2. vi/o voltage must tight up with vcc. vi/o = vcc = 1.70v~1.95v p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 11 4. block diagram control input logic program/erase high voltage write s tat e machine (wsm) stat e register flash arra y x-decoder address la tch and buffer y -p ass ga te y -decoder arra y source hv command data decoder command da t a la tch i/o buffer pgm data hv program da t a la tch sense amplifier aq[15:0] am-a16 am: msb address ce# oe# we# reset# clk a vd# acc rdy p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 12 4-1. block & address structure the main fash memory array is organized as word mode (x16). the details of the address ranges and the corresponding sector addresses are shown in table 1. the device is consisted of fve memory address areas as below: ? main flash array area ? secured silicon sector area ? device id & cfi area ? confguration register area ? sss (secured silicon sector) lock bit to facilitate the data read fexibility, this device enables the "address mapping" feature that could have user to defne the non-main array areas to be read as the main array area by mapping the address into the intended main array. for address range being marked as mapping area but not defned will output invalid data. each bank can be operated in the following three modes: - normal read mode - program/erase (pe) mode - address mapping (am) mode first two modes can be operated in any bank, but am mode can only be operated in bank0. in addition, at any time, only one bank is available to use the pe or am mode. ? normal read mode: the device will be in normal read mode in following status: hardware reset, power on, command reset, exit from pe mode. ? pe mode: the program & erase operation can be conducted in the bank, however, in the same bank, no read is allowed. other non-pe-mode banks are available for read operation at the same time. this is the "read-while-write" operation. ? am mode: one of the non-main-aray address is mapped in a bank. only one bank may be in am mode, all other banks may not be in am or pe mode. before entering am mode, all p/ e operation should be fnished. the attempt of entering pe mode or am mode when the other bank is in pe or am mode will be ignored. simultaneous operation of one bank in am mode, the other bank for normal read mode is allowed. the am mode can only be operated in lowest address bank. the mapping address of am mode should be within the assigned lowest address bank address area. ? the secured silicon sector, sss lock bit, and confguration register can be programmed in am mode per the mapped address. during above operation, it switches from am mode to pe mode. device id/ cfi is factory programming only. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 13 table 1-1. sector address table (top boot) bank sector size sector address range kwords 0 64 sa0 000000h-00ffffh 64 sa1 010000h-01ffffh 64 sa2 020000h-02ffffh 64 sa3 030000h-03ffffh 64 sa4 040000h-04ffffh 64 sa5 050000h-05ffffh 64 sa6 060000h-06ffffh 64 sa7 070000h-07ffffh 64 sa8 080000h-08ffffh 64 sa9 090000h-09ffffh 64 sa10 0a0000h-0affffh 64 sa11 0b0000h-0bffffh 64 sa12 0c0000h-0cffffh 64 sa13 0d0000h-0dffffh 64 sa14 0e0000h-0effffh 64 sa15 0f0000h-0fffffh 1 64 sa16 100000h-10ffffh 64 sa17 110000h-11ffffh 64 sa18 120000h-12ffffh 64 sa19 130000h-13ffffh 64 sa20 140000h-14ffffh 64 sa21 150000h-15ffffh 64 sa22 160000h-16ffffh 64 sa23 170000h-17ffffh 64 sa24 180000h-18ffffh 64 sa25 190000h-19ffffh 64 sa26 1a0000h-1affffh 64 sa27 1b0000h-1bffffh 64 sa28 1c0000h-1cffffh 64 sa29 1d0000h-1dffffh 64 sa30 1e0000h-1effffh 64 sa31 1f0000h-1fffffh 2 64 sa32 200000h-20ffffh 64 sa33 210000h-21ffffh 64 sa34 220000h-22ffffh 64 sa35 230000h-23ffffh 64 sa36 240000h-24ffffh 64 sa37 250000h-25ffffh 64 sa38 260000h-26ffffh 64 sa39 270000h-27ffffh 64 sa40 280000h-28ffffh 64 sa41 290000h-29ffffh bank sector size sector address range kwords 2 64 sa42 2a0000h-2affffh 64 sa43 2b0000h-2bffffh 64 sa44 2c0000h-2cffffh 64 sa45 2d0000h-2dffffh 64 sa46 2e0000h-2effffh 64 sa47 2f0000h-2fffffh 3 64 sa48 300000h-30ffffh 64 sa49 310000h-31ffffh 64 sa50 320000h-32ffffh 64 sa51 330000h-33ffffh 64 sa52 340000h-34ffffh 64 sa53 350000h-35ffffh 64 sa54 360000h-36ffffh 64 sa55 370000h-37ffffh 64 sa56 380000h-38ffffh 64 sa57 390000h-39ffffh 64 sa58 3a0000h-3affffh 64 sa59 3b0000h-3bffffh 64 sa60 3c0000h-3cffffh 64 sa61 3d0000h-3dffffh 64 sa62 3e0000h-3effffh 64 sa63 3f0000h-3fffffh 4 64 sa64 400000h-40ffffh 64 sa65 410000h-41ffffh 64 sa66 420000h-42ffffh 64 sa67 430000h-43ffffh 64 sa68 440000h-44ffffh 64 sa69 450000h-45ffffh 64 sa70 460000h-46ffffh 64 sa71 470000h-47ffffh 64 sa72 480000h-48ffffh 64 sa73 490000h-49ffffh 64 sa74 4a0000h-4affffh 64 sa75 4b0000h-4bffffh 64 sa76 4c0000h-4cffffh 64 sa77 4d0000h-4dffffh 64 sa78 4e0000h-4effffh 64 sa79 4f0000h-4fffffh 5 64 sa80 500000h-50ffffh 64 sa81 510000h-51ffffh 64 sa82 520000h-52ffffh 64 sa83 530000h-53ffffh 64 sa84 540000h-54ffffh p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 14 bank sector size sector address range kwords 5 64 sa85 550000h-55ffffh 64 sa86 560000h-56ffffh 64 sa87 570000h-57ffffh 64 sa88 580000h-58ffffh 64 sa89 590000h-59ffffh 64 sa90 5a0000h-5affffh 64 sa91 5b0000h-5bffffh 64 sa92 5c0000h-5cffffh 64 sa93 5d0000h-5dffffh 64 sa94 5e0000h-5effffh 64 sa95 5f0000h-5fffffh 6 64 sa96 600000h-60ffffh 64 sa97 610000h-61ffffh 64 sa98 620000h-62ffffh 64 sa99 630000h-63ffffh 64 sa100 640000h-64ffffh 64 sa101 650000h-65ffffh 64 sa102 660000h-66ffffh 64 sa103 670000h-67ffffh 64 sa104 680000h-68ffffh 64 sa105 690000h-69ffffh 64 sa106 6a0000h-6affffh 64 sa107 6b0000h-6bffffh 64 sa108 6c0000h-6cffffh 64 sa109 6d0000h-6dffffh 64 sa110 6e0000h-6effffh 64 sa111 6f0000h-6fffffh 7 64 sa112 700000h-70ffffh 64 sa113 710000h-71ffffh 64 sa114 720000h-72ffffh 64 sa115 730000h-73ffffh 64 sa116 740000h-74ffffh 64 sa117 750000h-75ffffh 64 sa118 760000h-76ffffh 64 sa119 770000h-77ffffh 64 sa120 780000h-78ffffh 64 sa121 790000h-79ffffh 64 sa122 7a0000h-7affffh 64 sa123 7b0000h-7bffffh 64 sa124 7c0000h-7cffffh 64 sa125 7d0000h-7dffffh 64 sa126 7e0000h-7effffh 16 sa127 7f0000h-7f3fffh 16 sa128 7f4000h-7f7fffh 16 sa129 7f8000h-7fbfffh 16 sa130 7fc000h-7fffffh p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 15 table 1-2. sector address table (bottom boot) bank sector size sector address range kwords 0 16 sa0 000000h-003fffh 16 sa1 004000h-007fffh 16 sa2 008000h-00bfffh 16 sa3 00c000h-00ffffh 64 sa4 010000h-01ffffh 64 sa5 020000h-02ffffh 64 sa6 030000h-03ffffh 64 sa7 040000h-04ffffh 64 sa8 050000h-05ffffh 64 sa9 060000h-06ffffh 64 sa10 070000h-07ffffh 64 sa11 080000h-08ffffh 64 sa12 090000h-09ffffh 64 sa13 0a0000h-0affffh 64 sa14 0b0000h-0bffffh 64 sa15 0c0000h-0cffffh 64 sa16 0d0000h-0dffffh 64 sa17 0e0000h-0effffh 64 sa18 0f0000h-0fffffh 1 64 sa19 100000h-10ffffh 64 sa20 110000h-11ffffh 64 sa21 120000h-12ffffh 64 sa22 130000h-13ffffh 64 sa23 140000h-14ffffh 64 sa24 150000h-15ffffh 64 sa25 160000h-16ffffh 64 sa26 170000h-17ffffh 64 sa27 180000h-18ffffh 64 sa28 190000h-19ffffh 64 sa29 1a0000h-1affffh 64 sa30 1b0000h-1bffffh 64 sa31 1c0000h-1cffffh 64 sa32 1d0000h-1dffffh 64 sa33 1e0000h-1effffh 64 sa34 1f0000h-1fffffh 2 64 sa35 200000h-20ffffh 64 sa36 210000h-21ffffh 64 sa37 220000h-22ffffh 64 sa38 230000h-23ffffh 64 sa39 240000h-24ffffh 64 sa40 250000h-25ffffh 64 sa41 260000h-26ffffh 64 sa42 270000h-27ffffh 64 sa43 280000h-28ffffh 64 sa44 290000h-29ffffh 64 sa45 2a0000h-2affffh bank sector size sector address range kwords 2 64 sa46 2b0000h-2bffffh 64 sa47 2c0000h-2cffffh 64 sa48 2d0000h-2dffffh 64 sa49 2e0000h-2effffh 64 sa50 2f0000h-2fffffh 3 64 sa51 300000h-30ffffh 64 sa52 310000h-31ffffh 64 sa53 320000h-32ffffh 64 sa54 330000h-33ffffh 64 sa55 340000h-34ffffh 64 sa56 350000h-35ffffh 64 sa57 360000h-36ffffh 64 sa58 370000h-37ffffh 64 sa59 380000h-38ffffh 64 sa60 390000h-39ffffh 64 sa61 3a0000h-3affffh 64 sa62 3b0000h-3bffffh 64 sa63 3c0000h-3cffffh 64 sa64 3d0000h-3dffffh 64 sa65 3e0000h-3effffh 64 sa66 3f0000h-3fffffh 4 64 sa67 400000h-40ffffh 64 sa68 410000h-41ffffh 64 sa69 420000h-42ffffh 64 sa70 430000h-43ffffh 64 sa71 440000h-44ffffh 64 sa72 450000h-45ffffh 64 sa73 460000h-46ffffh 64 sa74 470000h-47ffffh 64 sa75 480000h-48ffffh 64 sa76 490000h-49ffffh 64 sa77 4a0000h-4affffh 64 sa78 4b0000h-4bffffh 64 sa79 4c0000h-4cffffh 64 sa80 4d0000h-4dffffh 64 sa81 4e0000h-4effffh 64 sa82 4f0000h-4fffffh 5 64 sa83 500000h-50ffffh 64 sa84 510000h-51ffffh 64 sa85 520000h-52ffffh 64 sa86 530000h-53ffffh 64 sa87 540000h-54ffffh 64 sa88 550000h-55ffffh p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 16 bank sector size sector address range kwords 5 64 sa89 560000h-56ffffh 64 sa90 570000h-57ffffh 64 sa91 580000h-58ffffh 64 sa92 590000h-59ffffh 64 sa93 5a0000h-5affffh 64 sa94 5b0000h-5bffffh 64 sa95 5c0000h-5cffffh 64 sa96 5d0000h-5dffffh 64 sa97 5e0000h-5effffh 64 sa98 5f0000h-5fffffh 6 64 sa99 600000h-60ffffh 64 sa100 610000h-61ffffh 64 sa101 620000h-62ffffh 64 sa102 630000h-63ffffh 64 sa103 640000h-64ffffh 64 sa104 650000h-65ffffh 64 sa105 660000h-66ffffh 64 sa106 670000h-67ffffh 64 sa107 680000h-68ffffh 64 sa108 690000h-69ffffh 64 sa109 6a0000h-6affffh 64 sa110 6b0000h-6bffffh 64 sa111 6c0000h-6cffffh 64 sa112 6d0000h-6dffffh 64 sa113 6e0000h-6effffh 64 sa114 6f0000h-6fffffh 7 64 sa115 700000h-70ffffh 64 sa116 710000h-71ffffh 64 sa117 720000h-72ffffh 64 sa118 730000h-73ffffh 64 sa119 740000h-74ffffh 64 sa120 750000h-75ffffh 64 sa121 760000h-76ffffh 64 sa122 770000h-77ffffh 64 sa123 780000h-78ffffh 64 sa124 790000h-79ffffh 64 sa125 7a0000h-7affffh 64 sa126 7b0000h-7bffffh 64 sa127 7c0000h-7cffffh 64 sa128 7d0000h-7dffffh 64 sa129 7e0000h-7effffh 64 sa130 7f0000h-7fffffh p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 17 5. bus operations this chapter indicates the functions and utilizations of bus operations. bus operations are started by the internal command register and executed by a bus interface or similar logic circuitry. the command register does not occupy any memory addresses. it is stored in the format of latches and independent to the address and data information when executing the command. the contents of the register acts as it is input to internal state machine. in addition, the state machine outputs determine the function of the device. table 2. shows all inputs, control level requirement, and resulting output for all the bus operations. please read it for further information. note : falling edge of avd# determines when to disable the current burst cycle while a new burst read cycle is started by the rising edge of clk. table 2. bus operations operation ce# oe# we# clk avd# address data reset# synchronous operations latch starting burst address by clk l h h r l addr in addr in h advance burst read to next address l l h r h x output valid h terminate current burst read cycle h x x x x x highz h terminate current burst read cycle through reset# x x x x x x highz l asynchronous operations asynchronous read - addresses latched l h h l r addr in addr in h asynchronous read - data on bus l l h l h x output data h asynchronous program (avd# latched addresses) l h x l r addr in addr in h asynchronous program (we# latched data) l h r l h x input valid h non-operations standby (ce#) h x x x x x highz h hardware reset x x x x x x highz l legend: l = 0; h = 1; x = vil or vih; r = rising edge; h-l = high to low. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 18 notes: 1. wp#/acc low protects all sectors. 2. a/q0~a/q15 are input (din) or output (dout) pins according to the requests of command sequence, sector protection. 3. in word mode, the addresses are am to a0, am: msb of address. 5-1. status register bits in status register can offer users to identify the state in device right now. for more details, please see the following tables: table 3-1. status register status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready erase suspend erase status program status rfu program suspend sector protect bank status device ready 1 0: default 0: default 0: default dc 0: default 0: default 0: default device busy 0 dc dc dc dc dc dc 0: busy in this bank device busy 0 dc dc dc dc dc dc 1: busy in other bank invalid 1 dc dc dc dc dc dc 1 notes: 1. dc=dont care 2. bit 0 will show which bank is busy if and only if bit 7 is 0. otherwise, bit 0 can only become 0. 3. bit 3 is rfu table 3-2. status register - erase suspend status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready erase suspend erase status program status rfu program suspend sector protect bank status no sector in erase suspend 1 0 dc dc dc dc dc dc one sector in erase suspend 1 1 dc dc dc dc dc dc notes: 1. dc=dont care 2. after issuing erase suspend command, user should check bit 7 to make sure the value is 1 before accessing other sectors in the same bank. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 19 3. bit 3 is rfu table 3-3. status register - erase status status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready erase suspend erase status program status rfu program suspend sector protect bank status erase success 1 dc 0 dc dc dc dc dc erase fail 1 dc 1 dc dc dc dc dc notes: 1. dc=dont care 2. bit 5 will show the erase status of last erase operation. user may input clear status register or hardware reset to return to the default value. 3. bit 3 is rfu table 3-4. status register - program status status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready erase suspend erase status program status rfu program suspend sector protect bank status program success 1 dc dc 0 dc dc dc dc program fail 1 dc dc 1 dc dc dc dc notes: 1. dc=dont care 2. bit 4 will show the program status of last program operation. user may input clear status register or hardware reset to return to the default value. 3. bit 3 is rfu table 3-5. status register - program suspend status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready erase suspend erase status program status rfu program suspend sector protect bank status no sector in program suspend 1 dc dc dc dc 0 dc dc one sector in program suspend 1 dc dc dc dc 1 dc dc notes: 1. dc=dont care 2. after issuing program suspend command, user should check bit 7 to make sure the value is 1 before accessing other sectors in the same bank. 3. bit 3 is rfu p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 20 table 3-6. status register - protect status status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device ready erase suspend erase status program status rfu program suspend sector protect bank status unprotected sector during operation 1 dc dc dc dc dc 0 dc protected sector during operation 1 dc dc dc dc dc 1 dc notes: 1. dc=dont care 2. if last operation is failed due to the sector is protected bit 1 will become 1. user may input clear status register or hardware reset to return to the default value. 3. bit 3 is rfu. 5-2. blank check users can use blank check command to confrm the selected sector is erased. it is not allowed for users to read the array while the blank check command is being executed in the same array. this will return unknown data. blank check command is only valid in asynchronous read mode, which means the confguration register bit 15(cr [15]) is 1. this command may not conduct if the device is in operations. the operation process of blank check command is as follows: command will be issued (address 555h and data 33h) on sector x, while the device is in the idle state (neither during program suspend nor erase suspend operations.) after the operation is completed, the device will return to the idle state. user may use the read status register to confrm if the device is still busy and when compete if the sector is blank or not. bit 5 in the status register will be zero if the sector is erased and will become one if it is not erased. in addition, bit 7 & bit 0 in the status register will show if the device is performing a blank check. the device will halt the operation and report the results immediately, if any bit is found has not been erased. 5-3. non-burst (asynchronous) read operation upon device's power-up, non-burst mode read is as the default state. to perform a read operation, the system addresses the desired memory array or status register location by providing its address on the address pins and simultaneously enabling the chip by driving avd# & ce# low, and we# high. the clk keeps low during asynchronous read operation. the address is latched on the rising edge of avd#; oe# will be driven low afterwards. a/q15-a/q0 output the data after previous operations is complete. 5-4. burst (synchronous) read operation the device supports the following burst read modes: - burst mode - continuous linear - linear burst mode - 8/16 word with wrap around p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 21 5-4-1. burst mode - continuous linear burst read mode is enabled when confguration register bit 15 is set to 0. the number of dummy cycles should be set (for tiacc for each burst session) before the clock signal is being activated. before the burst read mode is activated, the number of dummy cycle will be determined by the setting confguration register command. see confguration register chapter for details. the process of the continuous burst read operation is as follows: the rising edge of a clk cycle while avd# = vil--> initial word output tiacc --> wait for dummy cycle --> rising edge of each consecutive clock, following words output (tbacc) (automatically increase the internal address counter) 1. for address boundary every 128 words, the frst boundary starts with 00007fh, next with 0000ffh by adding 128 words address; and etc. 2. additional dummy cycles are needed if the start address for the output cannot be divided by 8. rdy status indicates the condition of the device by de-asserting. there is a permanent internal address boundary in the device that occurs every 128 words. 1 or 2 dummy cycles are required while crossing boundary. additional dummy cycles needed when starting burst address cannot be divided by 8. table 4-1. address latency for 10-13 dummy cycles (+2dc only occures when crossing 128 words boundary) dummy cycles word subsequent clock cycles after initial dummy cycles 10-13 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 +2dc d8 1 d1 d2 d3 d4 d5 d6 d7 1dc +2dc d8 2 d2 d3 d4 d5 d6 d7 1dc 1dc +2dc d8 3 d3 d4 d5 d6 d7 1dc 1dc 1dc +2dc d8 4 d4 d5 d6 d7 1dc 1dc 1dc 1dc +2dc d8 5 d5 d6 d7 1dc 1dc 1dc 1dc 1dc +2dc d8 6 d6 d7 1dc 1dc 1dc 1dc 1dc 1dc +2dc d8 7 d7 1dc 1dc 1dc 1dc 1dc 1dc 1dc +2dc d8 table 4-2. address latency for 9 dummy cycles (+1dc only occures when crossing 128 words boundary) dummy cycles word subsequent clock cycles after initial dummy cycles 9 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 +1dc d8 1 d1 d2 d3 d4 d5 d6 d7 1dc +1dc d8 2 d2 d3 d4 d5 d6 d7 1dc 1dc +1dc d8 3 d3 d4 d5 d6 d7 1dc 1dc 1dc +1dc d8 4 d4 d5 d6 d7 1dc 1dc 1dc 1dc +1dc d8 5 d5 d6 d7 1dc 1dc 1dc 1dc 1dc +1dc d8 6 d6 d7 1dc 1dc 1dc 1dc 1dc 1dc +1dc d8 7 d7 1dc 1dc 1dc 1dc 1dc 1dc 1dc +1dc d8 p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 22 table 4-3. address latency for 8 dummy cycles dummy cycles word subsequent clock cycles after initial dummy cycles 8 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 d4 d5 d6 d7 1dc d8 2 d2 d3 d4 d5 d6 d7 1dc 1dc d8 3 d3 d4 d5 d6 d7 1dc 1dc 1dc d8 4 d4 d5 d6 d7 1dc 1dc 1dc 1dc d8 5 d5 d6 d7 1dc 1dc 1dc 1dc 1dc d8 6 d6 d7 1dc 1dc 1dc 1dc 1dc 1dc d8 7 d7 1dc 1dc 1dc 1dc 1dc 1dc 1dc d8 table 4-4. address latency for 7 dummy cycles dummy cycles word subsequent clock cycles after initial dummy cycles 7 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 d4 d5 d6 d7 d8 d9 2 d2 d3 d4 d5 d6 d7 1dc d8 d9 3 d3 d4 d5 d6 d7 1dc 1dc d8 d9 4 d4 d5 d6 d7 1dc 1dc 1dc d8 d9 5 d5 d6 d7 1dc 1dc 1dc 1dc d8 d9 6 d6 d7 1dc 1dc 1dc 1dc 1dc d8 d9 7 d7 1dc 1dc 1dc 1dc 1dc 1dc d8 d9 table 4-5. address latency for 6 dummy cycles dummy cycles word subsequent clock cycles after initial dummy cycles 6 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 d4 d5 d6 d7 d8 d9 2 d2 d3 d4 d5 d6 d7 d8 d9 d10 3 d3 d4 d5 d6 d7 1dc d8 d9 d10 4 d4 d5 d6 d7 1dc 1dc d8 d9 d10 5 d5 d6 d7 1dc 1dc 1dc d8 d9 d10 6 d6 d7 1dc 1dc 1dc 1dc d8 d9 d10 7 d7 1dc 1dc 1dc 1dc 1dc d8 d9 d10 table 4-6. address latency for 5 dummy cycles dummy cycles word subsequent clock cycles after initial dummy cycles 5 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 d4 d5 d6 d7 d8 d9 2 d2 d3 d4 d5 d6 d7 d8 d9 d10 3 d3 d4 d5 d6 d7 d8 d9 d10 d11 4 d4 d5 d6 d7 1dc d8 d9 d10 d11 5 d5 d6 d7 1dc 1dc d8 d9 d10 d11 6 d6 d7 1dc 1dc 1dc d8 d9 d10 d11 7 d7 1dc 1dc 1dc 1dc d8 d9 d10 d11 p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 23 table 4-7. address latency for 4 dummy cycles dummy cycles word subsequent clock cycles after initial dummy cycles 4 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 d4 d5 d6 d7 d8 d9 2 d2 d3 d4 d5 d6 d7 d8 d9 d10 3 d3 d4 d5 d6 d7 d8 d9 d10 d11 4 d4 d5 d6 d7 d8 d9 d10 d11 d12 5 d5 d6 d7 1dc d8 d9 d10 d11 d12 6 d6 d7 1dc 1dc d8 d9 d10 d11 d12 7 d7 1dc 1dc 1dc d8 d9 d10 d11 d12 table 4-8. address latency for 3 dummy cycles dummy cycles word subsequent clock cycles after initial dummy cycles 3 dummy cycles 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1 d2 d3 d4 d5 d6 d7 d8 d9 2 d2 d3 d4 d5 d6 d7 d8 d9 d10 3 d3 d4 d5 d6 d7 d8 d9 d10 d11 4 d4 d5 d6 d7 d8 d9 d10 d11 d12 5 d5 d6 d7 d8 d9 d10 d11 d12 d13 6 d6 d7 1dc d8 d9 d10 d11 d12 d13 7 d7 1dc 1dc d8 d9 d10 d11 d12 d13 5-4-2. linear burst mode - 8/16 word with wrap around fixed amount of data (8 or 16 words) is output from continuous address for the linear wrap around mode. (in the unit of words). the origin burst read address is decided by the group where the origin address falls. the defnition of groups is as illustrated in table 5 below. if the system is in 16-word mode, the subsequent clock cycles are needed. the detailed number of subsequent clock cycles please see the table above. there is no need to have subsequent clock cycles in 8-word mode. 8-, 16-word modes will be determined by the setting confguration register command. see confguration register chapter for details. table 5. burst address groups mode word group size word group address ranges 8-word mode 8 words per group 0-7h, 8-fh, 10-17, 16-word mode 16 words per group 0-fh, 10-1fh, 20-2fh, p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 24 5-4-3. reading memory array read mode is the default state after a power-up or a reset operation. an erase operation will be paused (after a time delay less than tesl) and the bank will enter erase- suspended read mode if the bank receives an erase suspend command while in the sector erase state. while in the erase-suspended read mode, data can be programmed or read from any sector which is not being erased. reading from addresses within sector (s) being erased is invalid. if a program command is issued to any inactive (not currently being erased) sector during erase- suspended read mode, the bank will perform the program operation and automatically return to erase-suspended read mode after the program operation completes successfully. while in erase-suspended read mode, an erase resume command must be issued by the system to reactivate the erase operation. the erase operation will resume from where it was suspended and will continue the operation until it completely fnishes or another erase suspend command is received. after the memory bank completes an embedded operation (chip erase, sector erase, or program) successfully, it will automatically return to idle state. if the embedded operation fails to complete, bit 5 (erase fail) or bit 4(program fail) in status register will become 1. the system may perform a "clear status register" operation before the next operation. oe# ce# we# t oez data addresse s a vd# wd 25h ra w a t wc t ds t dh t rc t rc t oe t aa vd s t aa vdh t a cc t oeh t wp t ghwl t wc t sr/w last cycle in prog r am or sector er ase command sequence read status (at least tw o cycle s) in same bank and/or arr a y data from other bank begin another wr ite or prog r am command sequence rd ra s a(555h) rd t wph figure 1. back-to-back read/write cycle timings note: breakpoints in waveforms indicate that system may alternately read array data from the non- busy bank while checking the status of the program or erase operation in the busy bank. the system should read status twice to ensure valid information. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 25 5-5. program operation the program operation is combined by two parts,"program to buffer" and "program buffer to flash". for further operation detail, please refer to 5-5-1. write buffer programming operation. after the program command sequence has been executed, the internal write state machine (wsm) automatically executes the algorithms and timings necessary for programming and verifcation, which includes generating suitable program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass verifcation or have low margins. the internal controller protects cells that do pass verifcation and margin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells continue to be programmed. with the internal wsm automatically controlling the programming process, users only need to enter the program command and data once. programming will only change the bit status from "1" to "0". it is not possible to change the bit status from "0" to "1" by programming. this can only be done with an erase operation. furthermore, the internal write verifcation only checks and detects errors in cases where a "1" is not successfully programmed to "0". any commands written to the bank during programming will be ignored except, read status register, hardware reset or program suspend. hardware reset will terminate the program operation after a period of time not more than tpsl. when the program is complete or the program operation is terminated by a hardware reset, the bank will return to idle state. when program suspend is ready, the bank will enter program suspend read mode. after the embedded program operation has begun, users can check for completion by reading the following bits in the status register table ( please refer to section 5-1. status register, tables: 3-1 and 3-4) . p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 26 5-5-1. write buffer programming operation the system is able to program up to 32 words in one programing operation. to trigger the write buffer programming, start with the program to buffer command at sector address+555h. the second cycle writes the "word locations subtract one" number. following the operations above, system starts to write the mingling of address and data. after the programming of the frst address or data, the "write-buffer-page" is selected. the following data should be within the above mentioned page. the "write-buffer-page" is selected by choosing address a22-a5. "write-buffer-page" address has to be the same for all address/data write into the write buffer. if not, operation will be aborted and the system will return to initial state. at the same time, bit 4 in status register will become 1. users may input a "clear status register" to clear this value before next operation. conditions which will lead to abort condition 1 condition 2 condition 3 condition 4 after inputting number of locations" to program, the value loaded is higher than the page buffer size. during program to buffer period, address written in a sector is not assigned. during program to buffer period, address/data written to buffer-write- page is not assigned by the starting address. input any other command except program to buffer after assigning the number of data load. if the system has been aborted, bit 4 in the status register will become 1. user may input command "clear status register" to clear bit 4 before next operation. to program the content of the write buffer page to flash memory needs a program buffer to flash command. the write buffer programming operation can be suspended or resumed by the standard commands. once the write buffer programming operation is fnished, it will return to idle state. see table 6 and figure 2 below for the write buffer programming command sequence write buffer programming can be conducted in any sequence. however the id/cfi, confguration mode, sss lock bit, and secured silicon sector region are not functional when program operation is in progress. multiple write buffer programming operations on the same write buffer address range without intervening erases is available. any bit in a write buffer address range can not be programmed from 0 back to 1. 5-5-2. accelerated program operations by applying high voltage (vhv) to the wp#/acc pin, the bank will enter the accelerated programming mode. during accelerated programming, the current drawn from the wp#/acc pin is no more than icp1. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 27 table 6. write buffer programming command sequence sequence command address data remarks 1 program to buffer sa+555h 0025h 2 indicate # of program locations sa+2aah word count (# of locations) - 1 3 load 1st word sa+write buffer location write addresses need to be within write- buffer-page boundaries, but no need to be loaded in any order. 4-x load next word sa+write buffer location write same as above x+1 load last word sa+write buffer location write same as above x+2 program buffer to flash sa+555h 0029h this command must come after the last write buffer location loaded, or the operation will abort. x+3 bank goes busy last status monitoring through read status register note: sa=sector address figure 2. write buffer programming operation wr ite ?wr ite to buff er? command and sector address wr ite n umber of addresses to pro gr am mi n us 1(dc) and sector address w r ite pro gr am b uff er to flash sector address wr ite first address/data wr ite n e xt address/data pair dc = dc - 1 dc = 0 ? p a r t of ?wr ite to buff er? command sequence y es y es no no abor t wr ite to buff er oper ation? wr ite to a diff erent sector address buffer operation is aborted, bit 4 in status register will become 1. the system will be back to initial state. a "clear status register" command is needed before next operation. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 28 5-6. erase operation there are two types of erase operations performed on the memory array -- sector erase and chip erase. sector erase operation erases one selected sector. sector erase will not be conducted if the selected sector is protected. chip erase will not be conducted if any of the sectors is in locked range sector or sa0 is locked protected. it can be done after the those sectors are being un-protected. 5-6-1. sector erase the sector erase operation is used to clear data within a sector by returning all the memory location to the 1 state. it requires two cycles to initiate the erase operation. the frst cycle is inputting sa (note)+address 555h and data 80h. the second cycle is sa+address 2aah and data 30. if the selected sector is protected, sector erase will not start and bit 1 will become 1. user may input a "clear status register" command to return bit 1 to default value before next operation. sector erase command sequence is as follows: sa+set-up command -->sa+sector erase command. note: sa=sector address after the embedded sector erase operation begins, all commands except erase suspend and read status register will be ignored. the only way to interrupt the operation is with an erase suspend command or with a hardware reset. the hardware reset will completely abort the operation and return the bank to initial state. please refer to section 5-1. status register, tables 3-1 and 3-3 . 5-6-2. chip erase the chip erase operation is used to erase all the data within the memory array. all memory cells containing a "0" will be returned to the erased state of "1". this operation requires 2 cycles to initiate the action. the frst cycle is inputting sa (note)+address 555h and data 80h. the second cycle is sa+2aah and data 10h. during the chip erase operation, no other software commands except read status register will be accepted, but if a hardware reset is received or the working voltage is too low , that chip erase will be terminated. after chip erase operation completes, the chip will automatically return to initial state. if any of the sectors is in locked range sector or sa0 is locked, chip erase will not start. the system is able to determine the status of the embedded chip erase operation. 5-6-3. accelerated sector erase an accelerated erase function is provided to erase no more than 100 times per sector erase. accelerated (acc) erase operation should be conducted in the range of 30 c+/-10 c. the acc erase provides much faster erase operation compare with standard erase operations. operations below are needed prior to acc sector erase operation: 1. if the selected sector is protected, sector erase will not start and bit 5 & bit 1 will become 1. users may input a "clear status register" command to return the bits to default value before next operation. 2. vhv must be applied to acc input at least 1 s before executing step 3. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 29 3. sector erase command is issued. 4. bit 7, bit 5 and bit 1 in status register should be monitored so to verify when erase operation is complete. this part is the same as in the standard erase operation. 5. acc is lowered from vhv to vcc. figure 3. erase operation st ar t erase command sequence y e s erase completion 5-7. program/erase suspend/resume 5-7-1. program suspend/program resume after a program operation begins, program suspend and read status register are the only valid command that can be issued. the system will determine if the bank has entered the program- suspended read mode through bit 2 in status register. after the bank has entered program-suspended mode, the system can read any sector (s) except that being programmed by the suspended program operation. reading the array being program suspended is invalid. whenever a suspend command is issued, user must issue a program resume command and check bit 2 in status register, before issue another program command. the system can use the status register bits shown in table 3-1 and table 3-5 to determine the current state of the bank. when the bank is program/erase suspended, user is not allowed to enter am mode. the program suspend operation is as follows: issuing programming suspend command --> bank's programming operation suspended paused within tpsl; status bits updated; address defned --> data to be read from non-suspended sectors. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 30 note that when an erase suspend is in operation, program suspend can also be conducted, data can then be read from non-suspended sectors. the program resume command is valid only when the bank is in program-suspended mode. for program resume, it operates as thus: issuing program resume command --> bank resumes programming (status to be checked by bit 2 in status register). please refer to table 3-5. status register - program suspend it must exit the suspend by issuing resume command. after programming being resumed, another program suspend can be issued after 25us. note: while a program operation is suspended and resumed more than once, a minimum delay of tprs (program resume to program suspend) is required between next resume and suspend command. 5-7-2. erase suspend/erase resume after a sector erase operation begins, erase suspend, read status register, and hardware reset are t he only valid commands t hat can be issued. i f t he syst em issues an erase suspend command after the sector erase operation has already begun, the bank will not enter erase-suspended read mode until tesl has elapsed. the system is able to determine if the bank has entered the erase- suspended read mode through bit 6 in status register. after the bank has entered erase-suspended read mode, the system can read or program any sector (s) except that being erased by the suspended erase operation. reading any sector being erased or programmed will cause unknown state. whenever a suspend command is issued, users must issue a resume command and check bit 6 in status register before issue another erase command. when the bank reads from a erase suspended sector during burst read mode, the burst read operation will soutput undefned value when crossing the boundary to the suspended sector . user may restart the burst operation by issuing new address and avd# pulse. the system is able to use the status register bits shown in table 3-1 and 3-2 to determine the current state of the bank. the sector erase resume command is valid only when the bank is in erase-suspended read mode. after erase operation resumes, users can issue another erase suspend command, but there should be a 400us interval between erase resume and the next erase suspend command. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 31 5-8. confguration register a confguration register is used to set the various burst parameters: number of dummy cycles, burst length, rdy confguration, and synchronous mode active. the confguration register table displays the address bits of confguration register settings represent various device functions. table 7. confguration register function cr bit settings (binary) enable sync read mode cr15 1 = default async read mode 0= sync read mode programmable dummy cycles cr14 0000 = reserved 0001 = data is valid on the 3rd active clk rising edge after addresses are latched 0010 = data is valid on the 4th active clk rising edge after addresses are latched 0011 = data is valid on the 5th active clk rising edge after addresses are latched 0100 = data is valid on the 6th active clk rising edge after addresses are latched 0101 = data is valid on the 7th active clk rising edge after addresses are latched 0110 = data is valid on the 8th active clk rising edge after addresses are latched 0111 = data is valid on the 9th active clk rising edge after addresses are latched 1000 = data is valid on the 10th active clk rising edge after addresses are latched 1001 = data is valid on the 11th active clk rising edge after addresses are latched 1010 = data is valid on the 12th active clk rising edge after addresses are latched 1011 = data is valid on the 13th active clk rising edge after addresses are latched (default) 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved cr13 cr12 cr11 rdy polarity cr10 0 = rdy signal is active low 1 = rdy signal is active high (default) reserved cr9 1 = default rdy cr8 0 = rdy active one clock cycle before data 1 = rdy active with data (default) driver strength cr7 0 = full driver strength (default) 1 = half driver strength reserved cr6 1 = default reserved cr5 0 = default reserved cr4 0 = default reserved cr3 1 = default burst length cr2 000 = continuous (default) 010 = linear burst length - 8-word with wrap around 011 = linear burst length - 16-word with wrap around (all other bit settings are reserved) cr1 cr0 p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 32 notes : 1. rdy confguration - the device is able to set rdy to output voh with valid data by default. rdy goes active one data cycle ahead of the active data. cr8 sets to "1" for rdy being active; "0" for rdy being active one cycle ahead of the valid data to be output. 2. rdy polarity - both devices have this default setting to indicate if the system is ready for cr10 to set to "1" when rdy is high. set to "0" will set rdy to low. when rdy is low, rdy shows the device is ready. 5-8-1. set confguration register command sequence the burst mode parameter is set by the confguration register. the following modes are confgured: burst length, rdy confguration, synchronous mode active, and number of dummy cycles. before entering burst mode, the confguration register needs to be set. user should issue enter confguration register command frst and then set confguration register by following 4 cycles. ? cycle 1: sa+address 555h & data 25h. ? cycle 2: sa+address 2aah & data 00h. ? cycle 3: sa+address x00h & pd. ? cycle 4: sa+ address 555h & data 29h. to reset the bank to read mode, a software reset command needs to be issued. the bank's default state after power up or hardware reset is asynchronous read mode. before entering synchronous mode, the register needs to be set. during bus operation, the register can not be modifed. note: sa=sector address 5-8-2. confgurable dummy cycle the confgurable dummy cycle settings can be decided by the input frequency of the bank - the confguration bit (cr14Ccr11) determines the setting. refer to table 8. confguration dummy cycles vs frequency as below. the certain number of cycles for original burst read is set by confguration register command sequence in 5-8-1. the clock frequency determines the number of dummy cycles confgured. note: after a power-up or hardware reset, the default setting of dummy cycle will be set to 13. in order to ensure the bank is set as expected, it is recommended that confguration register command sequence should be written even if the default dummy cycle value is desired. default state can also be obtained by hardware reset. other setting not listed in the table above will be reserved as invalid. if the setting cr[14:11] is not in legal setting as table listed, the bank will output cr[14:11] to 1011 and rdy will be disasserted. 5-8-3. burst length confguration three different burst read modes are supported: 8 & 16 word linear burst read with wrap around; continuous burst read. the bank's default burst read is burst mode - continuous linear. it launches with starting address till the burst read ends. when reaches the highest address, it wraps around to the lowest address. in 8 or 16 word liner burst read with wrap around, the wrap around occurs in the 8 or 16 word boundary. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 33 table 8. confguration dummy cycles vs frequency cr [14:11] dummy cycles freq max (mhz) 0001 3 27 0010 4 40 0011 5 54 0100 6 66 0101 7 80 0110 8 95 0111 9 104 1000 10 108 5-8-4. output drive strength user may tune the strength of output driver from full strength to half strength depends on the confguration bit cr7. the default setting is cr7=1; with full strength. if cr7=0, the strength of output buffer will be reduced to half strength. figure 4. example of programmable dummy cycles data a vd# oe# clk 1 2 3 4 5 d0 d1 0 6 1 7 3 t otal n umber of cloc k cycles f ollo wing addresses being latched rising edge of ne xt cloc k cycle f ollo wing last w ait state tr iggers ne xt b urst data t otal n umber of cloc k edges f ollo wing addresses being latched 2 4 5 6 7 p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 34 5-9. enter/exit secured silicon sector command sequence a 8-word, random esn (electronic serial number) is in the secured silicon sector region. the operation of secured silicon sector region is thus: 1-cycle command to enter the region --> access of the region --> 1-cycle command to exit the region --> return to normal operation the "enter secured silicon region" enables user to conduct the following: - read the region - program the user region - read non re-mapped area - issuing "exit secured silicon region" command the secured silicon sector region cannot be accessed when program/erase is in operation. in the secured silicon sector region, 128-word region is factory locked, while the other 128-word region is customer locked. 5-9-1. program secured silicon sector command sequence programming secured silicon sector starts by entering secured silicon sector region. after entering the region the sequence is as the table 6. write buffer programming command sequence . the system can monitor bit 7, bit 4 and bit 0 in status register to check the status of the embedded operation as the system does when programming the normal array. programming the secured silicon sector will only change the bit status from 1 to 0. it is not possible to change the bit status from 0 to 1 by programming. furthermore, the internal write verifcation only checks and detects errors in case where a 1 is not successfully programmed to 0. when program is complete, the device then returns to read secured silicon sector mode. if embedded program exceeds max. time limit (a failure occurs), bit 4 in status register changes to 1. under this condition, users may input a "clear status register" command. also, hardware reset can return to idle state. 5-10. handshaking feature by conducting the host to detect the ready (rdy) signal, the handshaking feature enables the system to decide when the initial burst data is ready, which controls by ce#. rdy is active when ce# is low. rdy is foating when both ce# are high. a/q15 ~ a/q0 are active when ce# & oe# are low. a/q15~a/q0 are foating when both ce# high and oe# are high. the synchronous mode operation is as thus: confgure the number of dummy cycle by confguration register(cr14~cr11) --> avd# and oe# goes low --> rising edge of rdy indicates the initial burst word data indicated. the burst read may be optimized by confguring the setting the number of dummy cycle per clock frequency. in asynchronous mode, ce# is low and rdy is high. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 35 6. security features 6-1. sector protect/un-protect the device is capable of protect all sectors from program/erase operation. upon power-up, all sectors are unprotected by default. protected/un-protected sector operation is as thus: issue frst two cycles sector protected/un- protected command (x555h & x2aah) address & data 60h. 3rd cycle address (sla) & command (60h) to unlock and indicate address a6 for the sector to be protected (vil) or un-protected (vih). when a6= vil, all sectors protected. one sector at a time can then be un-protected. prior to program/erase operation, un-protected sector address needs to be checked. un-protection status of a sector can be altered after program/ erase operations are suspended. during program suspend/resume and erase suspend/resume, the sector protection status is not checked. when sector protect/un-protect command issued to a "sector protect range" area, all sectors in it will not be un-protected. if a program/erase operation occurs in a protected sector, the operation will not start and bit 1 in status register will become 1. users may input a "clear status register" command or "hardware reset" command to return it to default value. 6-2. sector protect range a range of sectors can be protected from write operation with the sector protect range command till power off or hardware reset. the sector protect range command overrides the sector protect/ un-protect command. the sequence is as follows: 2 cycles of addresses (x555h & x2aah) & data (60h)--> 1 cycle (3rd) load sector address & issue sector address command (61h) (setting lower sector of range) --> 1 cycle (4th), write sector address & load sector address command (61h) (setting upper sector of the range). the range is 128kb. if the sector address meets the locations of the 4 boot sectors in range, all sectors will be protected. before power cycle or hardware reset, the selected sectors are protected. address input need to start from lower address to higher address, otherwise the sector lock range command will be invalid. in addition, the sector lock range command would only be valid when a6=vil. the sector lock range command is only valid once after a power cycle or hardware reset. sector lock range command is superior to the sector protect command. 6-3. hardware protect when wp#/acc = vil, no program/erase operation then allowed for all sectors. no program / erase operation is allowed until vcc > vlko. if vcc > vlko, user needs to avoid unintended write to the device. for oe#, we# or ce#'s glitch less than 3ns, the program/erase cycle will not be triggered. power-up write inhibit is supported, thus during power up, ce#=reset#=vil and oe#=vih, no program/erase operation is allowed. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 36 6-4. sss lock bits there are two bits in sss lock bits: secured silicon sector protection bit in customer region is bit 0. secured silicon sector protection bit in factory region is bit 1. all other bits in this register are 1 in default. if bit 0 is 1, the secured silicon sector in customer region is programmable. if bit 0 is 0, that region will be un-programmable. as soon as secured silicon sector region has been programmed, sss lock bits should be 0. 6-5. secured silicon sector flash memory region the secured silicon sector region is an extra otp memory space of 256 words in length. there are two regions in this memory space: factory locked region(0~7fh) and customer lockable region(80~ffh). customer can issue sss lock entry command and then sss lock read command to query the lock status of the device. in factory-locked device, secured silicon sector region is protected when shipped from factory and the sss lock bit (bit 1) is set to "1". in customer lockable device, security sector region is unprotected when shipped from factory and the sss lock bit (bit 0) is set to "0". following attributes applies for this region: - the region is not available during pe mode or other region in am mode - sector address will be supplied when the sss entry command choose memory array sector which is overlaid by the sss region address map - continuous burst read in this region wraps from ffh to 00h - read to be performed in async & sync mode 6-5-1. factory locked region: secured silicon sector programmed and protected at the factory in the factory-locked region, the secured silicon sector is permanently locked before shipping from the factory. this region will have a 8-word esn in the security region. the esn occupies 00000h to 00007h in word mode. the following attributes applie for this region: secured silicon sector address range standard factory locked express flash factory locked 000000h-00007fh esn factory lock 000080h-0000ffh unavailable determined by customer p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 37 6-5-2. customer lockable region: secured silicon sector not programmed or protected at the factory when the security feature is not required, the customer lockable region in secured silicon sector can act as an extra memory space. secured silicon sector is protected by sss lock bit (bit1 and bit0). note that once the secured silicon sector is protected, there is no way to unprotect the secured silicon sector and the content of it can no longer be altered. after the secured silicon is locked and verifed, system must write exit security sector region, go through a power cycle, or issue a hardware reset to return the device to read normal array mode. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 38 7. command definitions command defnitions table shows the address and data requirements for both command sequences. command asyn. read program to buffer program buffer to flash sector erase chip erase cycles 1 3-34(note1) 1 2 2 1st bus cycle addr ra sa+555 sa+555 sa+555 sa+555 data rd 25 29 80 80 2nd bus cycle addr sa+2aa sa+2aa sa+2aa data wc 30 10 3rd bus cycle addr sa+pa data pd 4th bus cycle addr sa+pa data pd command reset read status register clear status register program suspend program resume cycles 1 1 1 1 1 1st bus cycle addr x sa+555 sa+555 xxx sa+000 data f0 70 71 51 50 2nd bus cycle addr sa data rr 3rd bus cycle addr data 4th bus cycle addr data command erase suspend erase resume blank check sector protected /un-protected sector lock range cycles 1 1 1 3 4 1st bus cycle addr xxx sa+000 sa+555 555 555 data b0 30 33 60 60 2nd bus cycle addr 2aa 2aa data 60 60 3rd bus cycle addr sla sla data 60 61 4th bus cycle addr sla data 61 p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 39 command id/cfi mode deep power down enter read exit enter exit cycles 1 1 1 3 1 1st bus cycle addr sa+x55 sa+ra xxx 555 xxx data 90 (1) / 98 (2) data f0 aa ab 2nd bus cycle addr 2aa data 55 3rd bus cycle addr xxx data b9 4th bus cycle addr data command confguration register enter program to buffer program buffer to flash read exit cycles 1 3 1 1 1 1st bus cycle addr sa+555 sa+555 sa+555 sa+x00 xxx data d0 25 29 rr f0 2nd bus cycle addr sa+2aa data 0 3rd bus cycle addr sa+x00 data pd 4th bus cycle addr data command sss lock enter program to buffer program buffer to flash read exit cycles 1 3 1 1 1 1st bus cycle addr sa+555 sa+555 sa+555 sa+xxx xxx data 40 25 29 rr f0 2nd bus cycle addr sa+2aa data 0 3rd bus cycle addr sa+00 data pd 4th bus cycle addr data note 1 = id note 2 = cfi p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 40 command secured silicon sector region enter program to buffer program buffer to flash read exit cycles 1 3-34 (note1) 1 1 1 1st bus cycle addr sa+555 sa+555 sa+555 sa+ra xxx data 88 25 29 rd f0 2nd bus cycle addr sa+2aa data wc 3rd bus cycle addr sa+pa data pd 4th bus cycle addr sa+pa data pd x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens frst. sa = address of the sector to be verifed or erased. address bits amax - a13 uniquely select any sector. wc = word count. number of write buffer locations to load minus 1 sla= sector lock address rr= read register value note 1: the minimum cycles are 3 and the maximum cycles are 34. the number depends on the data which need to be programmed at location pa. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 41 8. energy saving mode 8-1. standby mode the device enters standby mode whenever the reset# and ce# pins are both held high except in the embedded mode. while in this mode, we# and oe# will be ignored, all data output pins will be in a high impedance state, and the device will draw minimal (icc3) current. 8-2. automatic sleep mode automatic sleep mode is able to minimize power consumption of flash device. the device automatically enters this mode when the addresses and clock stays stable. the automatic sleep mode will not be infuenced by the ce#, we#, and oe# control signals. standard address access timings are responsible for offering new data when addresses are changed. output data will be always available to the system and latched in sleep mode. icc6 in the table 9. dc characteristics indicates the current specifcations for automatic sleep mode. automatic sleep mode is not allowed while in sync read mode. 8-3. output disable output (a/q15-a/q0) is disabled and in tri-state when oe#=vih. oe# doesn't control the rdy . p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 42 parameter description test conditions min typ max unit iccb vcc active burst read current ce# = vil, oe# = vih, we#=vih, burst length = 8 108 mhz 15 33 ma ce# = vil, oe# = vih, we#=vih, burst length = 16 108 mhz 15 35 ma ce# = vil, oe# = vih, we#=vih, burst length = continuous 108 mhz 20 39 ma icc1 vcc active asynchronous read current ce# = vil, oe# = vih, we#=vih, 5 mhz 10 18 ma 1 mhz 3 4 ma icc2 vcc active write current ce# = vil, oe# = vih, wp#/acc = vih 20 60 ma icc3 vcc standby current ce# = vcc+/-0.2v, reset# = vcc+/-0.2v 30 115 ua icc4 vcc reset current reset# = vil, clk = vil 30 150 ua icc5 vcc read while write current ce#=vil, oe#=vih, wp#/acc=vih 71 76 ma icc6 vcc sleep current ce# = vil, oe# = vih 30 115 ua idpd vcc deep power down current ce# = vcc+/-0.2v, reset# = vcc+/-0.2v 5 50 ua ilo output leakage current vout = vss to vcc, vcc = vcc max 1 ua ilhv high voltage pin leakage current vin=vhv, vcc=vcc max 35 ua ili input leakage current vin = vss to vcc, vcc = vcc max 1 ua ippe accelerated erase current wp#/acc = vhv 10 30 ma ippw accelerated program current wp#/acc = vhv 5 30 ma vhv very high voltage for accelerated program 8.5 9.5 v vih input high voltage vi/o-0.4 vi/o+0.4 v vil input low voltage -0.2 0.4 v vlko low vcc lock-out voltage 1.0 1.4 v voh output high voltage ioh = C100 ua, vcc = vcc min 0.85x vi/o v vol output low voltage iol = 100 ua, vcc = vcc min 0.45 v table 9. dc characteristics p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 43 8-3-1. hardware reset driving the reset# pin low for a period of trp or more will return the device to read mode. if the device is in the process of a program or erase operation, the reset operation will take at most a period of trh before the device returns to read mode. when the reset# pin is held at gnd0.3v, the device only consumes standby (isbr) current. however, the device draws larger current if the reset# pin is held at a voltage greater than gnd+0.3v and less than or equal to vil. it is recommended to tie the system reset signal to the reset# pin of the fash memory . this allows the device to be reset with the system and puts it in a state where the system can immediately begin reading boot code from it. table 10. hardware reset parameter description speed unit trp reset# waveform width reset at embedded program / erase operation 25 us reset at read operation 5 us trh reset high time before read 200 ns 8-3-2. software reset software reset is one of reset commands in the command set (see chapter 7. command defnitions ) that is able to return the device to read array memory after reset. it must be used under the following conditions: 1. exit sss lock. 2. exit secured silicon sector region. 3. exit confguration register region. 4. exit id/cfi mode. figure 5. reset timings reset# t rp ce#, oe# t rh t rph p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 44 9. device id and common flash memory interface (cfi) mode the device features cfi mode. host system can retrieve the operating characteristics, structure and vendor-specifed information such as identifying information, memory size, byte/word confguration, operating voltages and timing information of this device by cfi mode. if the system writes the cfi query command "98h", to address "55h", the device will enter the cfi query mode. the system can read cfi information at the addresses given in table 13. once user enters cfi query mode, users are allowed to issue reset command to exit cfi mode and return to read array mode. table 11-1. id/cfi mode: device id description address (h) (word mode) data (h) macronix manufacture id 00 c2h device id 01 007e revision id 03 00h id version 06 10h security silicon 07 q5-q0=reserved q6 - customer lock bit 0 = un-locked, 1 = locked, q7 - factory lock bit 0 = un-locked, 1 = locked q8 - q15 = reserved lower software bites 0c 05h bit 0 - status register support 1 = status register supported 0 = status register not supported bit 1 - dq polling support 1 = dq bits polling supported 0 = dq bits polling not supported bit 3-2 - command set support 11 = reserved 10 = reserved 01 = reduced command set 0 = old command set bit 4- f - reserved high order device id, word 2 0e 0063h/top; 0065h/bottom low order device id, word 3 0f 0001h (top/bottom) p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 45 table 11-2. id/cfi mode: identifcation data values description address (h) (word mode) data (h) query-unique ascii string "qry" 10 0051h 11 0052h 12 0059h primary vendor command set and control interface id code 13 0002h 14 0000h address for primary algorithm extended query table 15 0040h 16 0000h alternate vendor command set and control interface id code 17 0000h 18 0000h address for alternate algorithm extended query table 19 0000h 1a 0000h table 11-3. id/cfi mode: system interface data values description address (h) (word mode) data (h) vcc min. (program/erase) d7Cd4: volt, d3Cd0: 100 millivolt 1bh 0017h vcc max. (program/erase) d7Cd4: volt, d3Cd0: 100 millivolt 1ch 0019h acc min. voltage (00h = no acc pin present) refer to 4dh 1dh 0000h acc max. voltage (00h = no acc pin present) refer to 4eh 1eh 0000h typical timeout per single word write 2 n us 1fh 0004h typical timeout for min. size buffer write 2 n us (00h = not supported) 20h 0009h typical timeout per individual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms (00h = not supported) 22h 0011h max. timeout for word write 2 n times typical 23h 0004h max. timeout for buffer write 2 n times typical 24h 0002h max. timeout for sector erase 2 n times typical 25h 0003h max. timeout for full chip erase 2 n times typical (00h = not supported) 26h 0002h p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 46 table 11-4. cfi mode: device geometry data values description address data 128e device size = 2 n byte 27h 0018h flash device interface description (refer to cfi publication 100) 28h 0001h 29h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ah 0006h 2bh 0000h number of erase block regions within device 2ch 0002h erase block region 1 information (refer to the cfi specifcation or cfi publication 100) 2dh 007eh (top boot) 0003h (bottom boot) 2eh 0000h 2fh 0000h (top boot) 0080h (bottom boot) 30h 0002h (top boot) 0000h (bottom boot) erase block region 2 information 31h 0003h (top boot) 007eh (bottm boot) 32h 0000h 33h 0080h (top boot) 0000h (bottom boot) 34h 0000h (top boot) 0002h (bottom boot) p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 47 table 11-5. cfi mode: primary vendor-specifc extended query data values description address (h) (word mode) data (h) query - primary extended table, unique ascii string, pri 40h 0050h 41h 0052h 42h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0033h unlock recognizes address (bits 1-0) 0= recognize, 1= don't recognize 45h 0000h erase suspend (2= to both read and program) 46h 0002h sector protect (n= # of sectors/group) 47h 0001h temporary sector unprotect (1=supported) 48h 0000h sector protect/chip unprotect scheme 49h 0008h simultaneous r/w operation (0=not supported) 4ah 0000h burst mode (0=not supported) 4bh 0001h page mode (0=not supported, 01 = 4 word page, 02 = 8 word page) 4ch 0000h minimum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4dh 0085h maximum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4eh 0095h top/bottom sector flags 00h: uniform 02h: bottom boot 03h: top boot 4fh 02h (bottom boot) 03h (top boot) program suspend (0=not supported, 1=supported) 50h 0001h p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 48 table 11-6. cfi mode: id/cfi data description address (h) (word mode) data (h) unlock bypass 00h = not supported 01h = supported 51h 0000h secure silicon region (customer lockable region) size 2n bytes 52h 0008h hardware reset low time-out until reset is completed during an embedded algorithm - maximum 2 n ns (e.g. 10 s => n = e) 53h 000eh hardware reset low time-out until reset is completed not during an embedded algorithm - maximum 2 n ns (e.g. 10 s => n = e) 54h 0008h erase suspend time-out maximum 2 n us 55h 0005h program suspend time-out maximum 2 n us 56h 0005h bank organization: x= number of banks 57h 0008h bank 0 region information x= number of sectors in bank 58h 0010h (top boot) 0013h (bottom boot) bank 1 region information x= number of sectors in bank 59h 0010h bank 2 region information x= number of sectors in bank 5ah 0010h bank 3 region information x= number of sectors in bank 5bh 0010h bank 4 region information x= number of sectors in bank 5ch 0010h bank 5 region information. x= number of sectors in bank 5dh 0010h bank 6 region information x= number of sectors in bank 5eh 0010h bank 7 region information x= number of sectors in bank 5fh 0010h (bottom boot) 0013h (top boot) p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 49 10. electrical characteristics 10-1. absolute maximum stress ratings surrounding temperature with bias -65c to +125c storage temperature -65c to +150c voltage range vcc -0.5v to vcc+0.5v vi/o -0.5v to vcc+0.5v acc -0.5v to +10.5v the other pins. -0.5v to vcc +0.5v output short circuit current (less than one second) 200 ma commercial (c) grade surrounding temperature (t a ) 0c to +70c industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages full vcc range 1.7~1.95v vi/o range = vcc notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -1.0v for period up to 20ns. maximum negative overshoot waveform maximum positive overshoot waveform 10-2. operating temperatures and voltages 0v -1.0v 20ns vcc+1.0v 1.95v 20ns p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 50 10-3. test conditions testing conditions: ? output load capacitance, cl : 1ttl gate, 10pf ? rise/fall times : 2ns ? input pulse levels :0.0 ~ vi/o ? in/out reference levels :0.5v i/o figure 6. test setup figure 7. input waveforms and measurement levels device under test cl 1.8v 6.2k 2.7k 0.0 v output measurement l e v el input v i/o /2 v i/o /2 v i/o p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 51 10-4. ac characteristics vcc power-up and power-down sequencing once vcc attains its operating voltage, de-assertion of reset# to vih is permitted. vcc power- up and power-down sequencing are not restricted. during the entire vcc power sequence, reset# needs to be asserted to vil until the respective supplies reach their operating voltages. once vcc operating voltage has been achieved, reset# to vih is allowed to be de-asserted. output disable mode once oe# is input is at vih, output from the device is disabled and placed in the state of high impedance. vcc power-up parameter description test setup speed unit tvcs vcc setup time min 1 ms notes: 1. vcc >+ vi/o - 100 mv 2. vcc ramp rate is > 100 us/v figure 8. vcc power-up diagram v cc reset# t vc s v i/o clk characteristics parameter description frequency unit 66 83 108 tclk clk cycle min 15 12 9.26 ns tclkr clk rise time max 3 2.5 1.9 ns tclkf clk fall time tclkh/l clk high or low time min 7 5.5 4.2 ns notes: 1. clock jitter of +/- 5% permitted. 2. not 100% tested. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 52 figure 10. clk characterization t clk t cl t ch t cr t cf clk figure 9. deep power down mode waveform item typ max web high to release from deep power down mode trdp 100us 200us web high to deep power down mode tdp 10us 20us oe# ce# a vd# we clk v cc v ih v il aah xx a/q15? a/q0 amax ? a16 abh 555h 55h xx 2aah b9h xx xx xx xx tdp trdp ac characteristics p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 53 figure 11. burst mode read note: chip enters burst mode once 1st clk rises and avd# equals to vil. parameter description speed unit tiacc initial access time max 75 ns tbacc burst access time valid clock to output delay max 7 ns tavds avd# setup time to clk min 4 ns tavdh avd# hold time from clk min 5 ns tavdo avd# high to oe# low min 4 ns tacs address setup time to clk min 4 ns tach address hold time from clk min 5 ns tbdh data hold time from next clock cycle min 0 ns tcez chip enable to high z (note) max 10 ns toez output enable to high z (note) max 10 ns tces ce# setup time to clk min 4 ns tracc ready access time from clk max 7 ns tclks clk low to avd# low min 5 ns toecs oe# enable to first output clk setup time min 8 ns toe output enable to valid data max 15 ns tcas ce# setup time to falling edged of avd# min 0 ns table 12. synchronous / burst read notes: 1. not 100% tested. 2. avd# cannot be vil for 2 subsequent clock cycles. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 54 table 13. asynchronous read parameter description speed unit tce access time from ce# low max 80 ns tacc asynchronous access time max 80 ns tavdp avd# low time min 7 ns taavds address setup time to rising edge of avd# min 3.5 ns taavdh address hold time from rising edge of avd# min 3.2 ns toe output enable to output valid max 15 ns toeh we# disable to oe# enable min 4 ns toez output enable to high z (see note) max 10 ns toavd avd# disable to oeb enable min 10 ns tavdo oe# disable to avd# enable min 10 ns toeqx output enable to data low z min 0 ns tcr ce# enable to rdy ready max 10 ns tcez ce# disable to rdy hiz max 10 ns tcas ce# setup time to falling edged of avd# min 0 ns note: not 100% tested. figure 12. asynchronous mode read p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 55 table 14. erase/program operations parameter description speed unit twc write cycle time (note 1) min 45 ns tas address setup time min 4 ns tah address hold time min 6 ns tavdp avd# low time min 7 ns tds data setup time min 25 ns tdh data hold time min 0 ns tghwl read recovery time before write typ 0 ns tcs ce# setup time to we# typ 8 ns tch ce# hold time typ 0 ns twp/twrl write pulse width typ 30 ns twph write pulse width high typ 20 ns tsr/w latency between read and write operations min 0 ns tacc acc rise and fall time min 500 ns tvps acc setup time (during accelerated programming) min 1 us tvcs vcc setup time min 1 ms tesl erase suspend latency max 25 us tpsl program suspend latency max 25 us ters erase resume to erase suspend min 400 us tprs program resume to program suspend min 25 us twea web disable to avd# enable min 9.2 ns tvlwh avd# disable to web# disable min 23.5 ns tcas ce# setup time to falling edged of avd# min 0 ns tweh oe# disable to we# enable time min 4 ns notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. 3. preprogramming time is not included. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 56 figure 13. program operation timings oe# ce# a vd# we clk v cc t a s t wp t ah t wc t wph s a(555h) t vcs t t cs cas t dh t ch 70h ba(555h) status b a program command sequence (last two cycles) read status data t ds v ih v il t a vd p pd pa 29h a/q15? a/q0 amax ? a16 b a ba(555h) sa(555h) pa wea t tvl wh notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. ba = address bits are suffcient to select a bank. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 57 figure 14. chip/sector erase operations note: sa is the sector address for sector erase. p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 58 figure 15. 8-, 16-word linear burst address wrap around a/q15 ? a/q0 clk address (he x) d 0 d1 d2 oe# address wr aps bac k to beginning of address g roup . 3 9 3 9 3 a 3b 3c 3d 3e 3f 38 initial access v il v ih a vd# v il v ih d 3 d 4 d5 d6 d7 (st a ys lo w) ce# v il (st a ys l o w) note: 8-word linear burst mode shown. 16-word linear burst read modes behave similarly . d0 represents the frst word of the linear burs t. figure 16. latency with boundary crossing clk address (h e x) c12 4 c12 5 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (sta ys high) a vd# rd y(1) data oe#, ce# (sta ys lo w) address boundar y occurs e v e r y 128 w ords , beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a bounda r y crossing. 7c 7 d 7 e 7f 7f 8 0 81 82 83 latency rd y(2) latency t ra cc t r a cc t ra cc t ra cc notes: 1. cxx indicates the clock that triggers data dxx on the outputs; for example, c60 triggers d60. 2. please reference burst read related tables for deta ils. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 59 10-5. erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 1.8v vcc. programming specifcations assume checkboard data pattern. 2. maximum values are measured at vcc = 1.8 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. erase/program cycles comply with jedec jesd-47e & a117a standard. 4. exclude 00h program before erase operation. parameter limits units min. typ. (1) max. (2) chip programming time (128mb) 70 sec chip erase time (128mb) 80 300 sec sector erase time (16kw) 0.5 5 sec sector erase time (64kw) 1 7 sec word program time 30 360 us total write buffer time 240 us acc total write buffer time 80 us erase/program cycles 100,000 cycles effective word programming time 7.5 us blank check time 10 ms latch-up characteristics pin capacitance parameter symbol parameter description test setup typ max unit cin2 control pin capacitance vin=0 7.5 9 pf cout output capacitance vout=0 8.5 12 pf cin input capacitance vin=0 6 7.5 pf min. max. input voltage voltage difference with gnd on wp#/acc pins -1.0v 10.5v input voltage voltage difference with gnd on all normal pins input -1.0v 1.5vcc vcc current -100ma +100ma all pins included except vcc. test conditions: vcc = 1.8v, one pin per testing data retention parameter condition min. max. unit data retention 55?c 20 years p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 60 10-6. low vcc write prohibit the device refuses to accept any write command when vcc is less than vlko. this prevents data from spuriously being altered during power-up, power-down, or temporary power interruptions. the device automatically resets itself when vcc is lower than vlko and write cycles are ignored until vcc is greater than vlko. the system must provide proper signals on control pins after vcc rises above vlko to avoid unintentional program or erase operations. 10-6-1. write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. on we#, noise pulses of less than 5ns do not initiate a write cycle. 10-6-2. logical prohibit a valid write cycle requires both ce# and we# at vil with oe# at vih. while initiating a write cycle, ce# and we# must be a logical "0" while oe# is a logical "1". write cycle is ignored when either ce# at vih, we# at vih, or oe# at vil. 10-6-3. power-up sequence upon power-up, the device is placed in read mode. furthermore, program or erase operation will begin only after successful completion of specifed command sequences. 10-6-4. power-up write prohibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. 10-6-5. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect. 10-5-1. bga ball capacitance parameter symbol parameter description test setup typ max unit cin input capacitance vin = 0 4.2 5.0 pf cout output capacitance vout = 0 5.4 6.5 pf cin2 control pin capacitance vin = 0 3.9 4.7 pf notes: 1. sampled, not 100% tested. 2. test conditions ta = 25c, f = 1.0 mhz. p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 61 11. package information p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F 62 12. revision history rev. no. description page date 1.0 1. removed "advanced information" from features page p5 feb/22/2012 1.1 1. modifed table 10-1. voltage range (for vcc & vi/o) p49 aug/05/2013 to vcc+0.5v 1.2 1. updated d9 and dnu pin descriptions p9,10 feb/13/2014 2. modifed the address and cycles of program to buffer command. p38,40 3. added notes for id/cfi mode enter data p39 4. modifed vcc ramp up rate unit p51 5. updated pin descriptions for write protection p6,10,18,26, 27,35,42,59 6. modifed set confguration register command sequence p32 p/n: pm1679 rev. 1.2, feb. 13, 2014 multi-bank, read while write flash memory 63 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as it s suppliers and/ or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2011~2014. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider , nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich audio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at http://www.macronix.com p/n: pm1679 rev. 1.2, feb. 13, 2014 MX29VS128F |
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