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3.3v differential ecl/pecl pll clock generator semiconductor technical data order number: mpc9991/d rev 0, 12/2001 1 ? motorola, inc. 2001

the mpc9991 is a 3.3 v compatible, pll based ecl/pecl clock driver. using sige technology and a fully differential design ensures optimum skew and pll jitter performance. the performance of the mpc9991 makes the device ideal for workstation, mainframe computer and telecommunication applications. with output frequencies up to 400 mhz and output skews less than 150 ps 1 the device meets the needs of the most demanding clock applications. the mpc9991 offers a differential ecl/pecl input for applications which need to lock to an existing clock signal. it also offers a secondary singleended ecl/pecl clock for system test capabilities. features ? 13 differential outputs, pll based clock generator ? sige technology supports minimum output skew (max. 150 ps 1 ) ? supports up to three individual generated output clock frequencies with a maximum clock frequency up to 400 mhz ? external pll feedback supports zero-delay capability ? selectable sync pulse generation ? ecl/pecl compatible differential clock inputs and outputs ? single 3.3v (pecl) or -3.3v (ecl) supply ? ambient temperature range 0 c to +70 c ? standard 52 lead lqfp package ? pin and function compatible to the mpc991 functional description the mpc9991 utilizes pll technology to frequency lock its outputs onto an input reference clock. normal operation of the mpc9991 requires the connection of the differential pll feedback output qfb to the differential feedback input fb_in to close the pll feedback path. the reference clock frequency and the divider for the feedback path determine the vco frequency. both must be selected to match the vco frequency range. the mpc9991 features frequency programmability between the three output banks outputs as well as the output to input relationships. output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3 :1 and 4:3:2 can be realized. the three banks of outputs can each be programmed by the fsel[3:0] pins of the device. there are 16 different output frequency configurations available in the device. additionally, the device supports a separate configurable feedback output. this allows for the feedback frequency to be programmed independently of the other outputs, providing six inpu t to output frequency ratios that can be configured by the fsel_fb[2:0] inputs. the external feedback feature enables the use of the mpc9991 as a zero-delay buffer. the vco_sel pin provides an extended pll input reference frequency range. the sync pulse generator monitors the phase relationship between the qa[3:] and qc[2:0] output banks. the sync generator output signals the coincident edges of the two output banks. this feature is useful for non binary relationships betw een output frequencies (i.e., 3:2 or 4:3 relationships). the sync_sel input switches the qd[1:0] outputs between the sync signals and an extensions to the qc bank of outputs. the ref_sel pin selects the differential ecl/pecl compatible input pair or a single-ended ecl/pecl compatible input as the reference clock signal. the pll_en control selects the pll bypass configuration for test and diagnosis. in this configuration, the selected input reference clock is routed directly to the outpu t dividers bypassing the pll. the pll bypass is fully static and the minimum clock frequency specification and all other pll characteristi cs do not apply. the mpc9991 requires an external reset signal for start-up and for pll recovery in the case the external feedback is interrupted. the mpc9991 is fully 3.3v (pecl) or -3.3v (ecl) compatible and requires no external loop filter components. all inputs accept pecl/ecl compatible differential signals while the outputs provide pecl/ecl compatible levels with the capability to drive terminated 50 transmission lines. the device is pin and function compatible to the mpc991 and is packaged in a 52-lead lqfp package. 1. final specification of this parameter is pending characterization. this document contains information on a product under development. motorola reserves the right to change or discontinue this pr oduct without notice. fa suffix 52 lead lqfp package case 848d 3.3v differential ecl/pecl pll clock generator idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 1 data sheet mpc9991
idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 2 mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 motorola timing solutions 2 figure 1. mpc9991 logic diagram 0 1 0 1 0 1 4 all input resistors have a value of 50k w 0 1 v cc v cc 3 pll 2, 4, 6, 8 qfb eclk eclk tclk fsel[3:0] qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 bank a bank b bank c vco ref fb sync pulse 2, 4, 6, 8 16, 24, 32 2, 4, 6, 8 qc2 qd0 fsel_fb[2:0] sync_sel mr ref_sel fb_in vco_sel pll_en 8001600 mhz 2 4 bank d 2, 4, 6, 8 fb_in qfb qd0 qd1 qd1 qc0 qc1 qc2 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 function table control default 0 1 ref_sel 0 selects eclk, eclk as pll refererence signal input selects tckl as pll reference signal input vco_sel 0 selects vco 2. (high input frequency range) selects vco 4. the vco frequency is scaled by a factor of 4 (low input frequency range). pll_en 0 normal operation mode with pll enabled. test mode with the pll bypassed. the reference clock is substituted for the internal vco output. mpc9991 is fully static and no minimum frequency limit applies. all pll related ac characteristics are not applicable. mr 0 normal operation reset of the device. during reset the pll feedback loop is open and the internal vco is tied to its lowest frequency. the mpc9991 requires reset at power-up and after any loss of pll lock. loss of pll lock may occur when the external feedback path is interrupted. the length of the reset pulse should be greater than one reference clock cycle (cclkx) sync_sel 0 qd[1:0] outputs generate a sync signal qd[1:0] outputs generate clock signals that match the qc[2:0] outputs vco_sel, fsel[3:0] and fsel_fb[2:0] control the operating pll frequency range and input/output frequency ratios. see table 2 and table 3 for the device frequency configuration.
idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 3 mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 timing solutions 3 motorola figure 2. mpc9991 52lead package pinout (top view) qb3 qb3 vcc qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 sync_sel vco_sel qc1 qc1 qco qc0 vcc qd1 qd1 qd0 qd0 vcc qfb qfb vcc_pll fsel0 qb2 qb2 fsel1 qb1 qb1 fsel2 qb0 qb0 vcc qc2 qc2 fsel3 vee mr pll_en ref_sel fsel_fb2 fsel_fb1 fsel_fb0 tclk eclk eclk vcc fb_in fb_in 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 12345678910111213 39 38 37 36 35 34 33 32 31 30 29 28 27 26 mpc9991 table 1: pin configuration pin i/o type function eclk, eclk input pecl/ecl differential reference clock signal input tclk input pecl/ecl single-ended test clock input fb_in, fb_in input pecl/ecl differential pll feedback clock signal input, connect to qfb, qfb vco_sel input pecl/ecl vco operating frequency select pll_en input pecl/ecl pll enable/bypass mode select ref_sel input pecl/ecl pll reference signal input select mr input pecl/ecl device reset fsel[3:0] input pecl/ecl output frequency divider select fsel_fb[2:0] input pecl/ecl frequency divider select for the qfb output sync_sel input pecl/ecl qd output mode select qa[0-3], qa[0-3] output pecl/ecl differential clock outputs (bank a) qb[0-3], qb[0-3] output pecl/ecl differential clock outputs (bank b) qc[0-2], qc[0-2] output pecl/ecl differential clock outputs (bank c) qd[0-1], qd[0-1] output pecl/ecl differential clock/sync signal outputs (bank d) qfb, qfb output pecl/ecl differential pll feedback clock output (connect to fb_in, fb_in ) vee a supply vee negative power supply v cc supply vcc positive power supply. all v cc pins must be connected to the positive power supply for correct dc and ac operation vcc_pll supply vcc pll positive power supply (analog power supply). it is recommended to use an external rc filter for the analog power supply pin vcc_pll. please see applications section for details a. in ecl mode (negative power supply mode), vee is -3.3v and vcc is connected to gnd (0v). in pecl mode (positive power supply mode), vee is connected to gnd (0v) and vcc is +3.3v. in both modes, the input and output levels are referenced to the most positive supply (vcc).
idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 4 mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 motorola timing solutions 4 table 2: output divider pll feedback m (qfb) vco_sel fsel_b2 fsel_fb1 fsel_fb0 qfb 0 0 0 0 vco 4 0 0 0 1 vco 8 0 0 1 0 vco 12 0 0 1 1 vco 16 0 1 0 0 vco 16 0 1 0 1 vco 32 0 1 1 0 vco 48 0 1 1 1 vco 64 1 0 0 0 vco 8 1 0 0 1 vco 16 1 0 1 0 vco 24 1 0 1 1 vco 32 1 1 0 0 vco 32 1 1 0 1 vco 64 1 1 1 0 vco 96 1 1 1 1 vco 128 table 3: output divider n (bank a to bank c) vco_sel fsel3 fsel2 fsel1 fsel0 qa[3:0] qb[3:0] qc[2:0] 0 0 0 0 0 vco 4 vco 4 vco 4 0 0 0 0 1 vco 4 vco 4 vco 8 0 0 0 1 0 vco 4 vco 8 vco 8 0 0 0 1 1 vco 4 vco 4 vco 12 0 0 1 0 0 vco 4 vco 12 vco 12 0 0 1 0 1 vco 4 vco 8 vco 12 0 0 1 1 0 vco 4 vco 8 vco 16 0 0 1 1 1 vco 4 vco 12 vco 16 0 1 0 0 0 vco 4 vco 4 vco 16 0 1 0 0 1 vco 4 vco 16 vco 16 0 1 0 1 0 vco 8 vco 8 vco 12 0 1 0 1 1 vco 8 vco 12 vco 12 0 1 1 0 0 vco 8 vco 12 vco 16 0 1 1 0 1 vco 12 vco 12 vco 16 0 1 1 1 0 vco 12 vco 16 vco 16 0 1 1 1 1 vco 16 vco 16 vco 16 1 0 0 0 0 vco 8 vco 8 vco 8 1 0 0 0 1 vco 8 vco 8 vco 16 1 0 0 1 0 vco 8 vco 16 vco 16 1 0 0 1 1 vco 8 vco 8 vco 24 1 0 1 0 0 vco 8 vco 24 vco 24 1 0 1 0 1 vco 8 vco 16 vco 24 1 0 1 1 0 vco 8 vco 16 vco 32 1 0 1 1 1 vco 8 vco 24 vco 32 1 1 0 0 0 vco 8 vco 8 vco 32 1 1 0 0 1 vco 32 vco 32 vco 32 1 1 0 1 0 vco 16 vco 16 vco 24 1 1 0 1 1 vco 16 vco 24 vco 24 1 1 1 0 0 vco 16 vco 24 vco 32 1 1 1 0 1 vco 24 vco 24 vco 32
mpc9991 timing solutions 5 motorola table 4: absolute maximum ratings a symbol characteristics min max unit condition v cc supply voltage -0.3 3.6 v v in dc input voltage -0.3 v cc +0.3 v v out dc output voltage -0.3 v cc +0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature -65 125 c a. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these c onditions or conditions beyond those indicated may adversely affect device reliability. functional operation at absolute-maximum-rated co nditions is not implied. table 5: general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc 2 v mm esd protection (machine model) tbd v hbm esd protection (human body model) tbd v cdm esd protection (charged device model) tbd v lu latchup immunity 200 ma c in input capacitance 4.0 pf inputs q jc thermal resistance (junction-to-ambient, junction-to-board, junction-to-case) tbd c/w t j operating junction temperature a (continuous operation) mtbf = 9.1 years 0 110 c a. operating junction temperature impacts device life time. maximum continuous operating junction temperature should be selected according to the application life time requirements (see application note an1545 for more information). the device ac and dc parameters a re specified up to 110 c junction temperature allowing the mpc9991 to be used in applications requiring industrial temperature range. it is recommended that users of the mpc9991 employ thermal modeling analysis to assist in applying the junction temperature specifica tions to their particular application. idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 5 mpc9991 3.3v differential ecl/pecl pll clock generator netcom
idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 6 mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 motorola timing solutions 6 table 6: pecl dc characteristics (v cc = 3.3v 5%, v ee = gnd, t a = 0 c to 70 c) a symbol characteristics min typ max unit condition differential pecl clock inputs (eclk, eclk and fb_in, fb_in ) b v pp ac differential input voltage c 0.1 1.3 v differential operation v cmr differential cross point voltage d 1.0 v cc -0.3 v differential operation single-ended pecl clock inputs (tclk, vco_sel, pll_en , mr, ref_sel, sync_sel, fsel_fb[2:0], fsel[3:0]) v ih input high voltage tbd tbd v il input low voltage tbd tbd i in input current tbd m a v in = tbd or v in = tbd pecl clock outputs (qa[3:0], qa[3:0] , qb[3:0], qb[3:0] , qc[2:0], qc[2:0] , qd[1:0], qd[1:0] ) v oh output high voltage tbd v cc -1.005 tbd v termination 50 to v tt v ol output low voltage tdb v cc -1.705 tbd v termination 50 to v tt supply current i ee maximum quiescent supply current without output termination current tbd tbd ma v ee pin i cce maximum quiescent supply current, outputs terminated 50 to v tt tbd tbd ma v cc pins a. ac characteristics are design targets and pending characterization. b. clock inputs driven by pecl compatible signals. c. v pp is the minimum differential input voltage swing required to maintain ac characteristics. d. v cmr (dc) is the crosspoint of the differential input signal. functional operation is obtained when the crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. e. i cc includes current through the output resistors (all outputs terminated to v tt ). table 7: ecl dc characteristics (v ee = 3.3v 5%, v cc = gnd, t a = 0 c to 70 c) a symbol characteristics min typ max unit condition differential ecl clock inputs (eclk, eclk and fb_in, fb_in ) b v pp differential input voltage c 0.1 1.3 v differential operation v cmr differential cross point voltage d v ee +1.0 -0.3 v differential operation i in input current a 150 m a v in = v il or v in = v ih single-ended ecl clock inputs (tclk, vco_sel, pll_en , mr, ref_sel, sync_sel, fsel_fb[2:0], fsel[3:0]) v il input voltage low -1.46 v v ih input voltage high -1.14 v i in input current e 150 m a v in = v il or v in = v ih ecl clock outputs (qa[3:0], qa[3:0] , qb[3:0], qb[3:0] , qc[2:0], qc[2:0] , qd[1:0], qd[1:0] ) v oh output high voltage tbd -1.005 tbd v termination 50 to v tt v ol output low voltage tbd -1.705 tbd v termination 50 to v tt supply current and v i ee maximum quiescent supply current without output termination current tbd tbd ma v ee pin i ccf maximum quiescent supply current, outputs terminated 50 to v tt tbd tbd ma v cc pins a. dc characteristics are design targets and pending characterization. b. clock inputs driven by pecl compatible signals. c. v pp (dc) is the minimum differential input voltage swing required to maintain device functionality. d. v cmr (dc) is the crosspoint of the differential input signal. functional operation is obtained when the crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. e. input have internal pullup/pulldown resistors which affect the input current. f. i cc includes current through the output resistors (all outputs terminated to v tt ).
mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 timing solutions 7 motorola table 8: ac characteristics (ecl: v ee = 3.3v 5%, v cc = gnd, or pecl: v cc = 3.3v 5%, v ee = gnd, t a = 0 c to 70 c) a b symbol characteristics min typ max unit condition f ref input reference frequency 4 feedback 8 feedback 12 feedback 16 feedback 24 feedback 32 feedback 48 feedback 64 feedback 96 feedback 128 feedback input reference frequency in pll bypass mode c 200.0 100.0 66.6 50.0 33.3 25.0 16.6 12.5 8.3 6.25 400.0 200.0 133.3 100.0 66.6 50.0 33.3 25.0 16.6 12.5 tbd mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz pll locked pll bypass f vco vco frequency range d 800 1600 mhz f max output frequency 4 output 8 output 12 output 16 output 24 output 32 output 200.0 100.0 66.6 50.0 33.3 25.0 400.0 200.0 133.3 100.0 66.6 50.0 mhz mhz mhz mhz mhz mhz pll locked v pp differential input voltage e (peak-to-peak) 0.3 1.3 v v cmr differential input crosspoint voltage f pecl ecl v cc -0.3 -0.3 v v o(p-p) differential output voltage (peak-to-peak) 0.8 tbd v f refdc reference input duty cycle 40 60 % t ( ? ) propagation delay (static phase offset) eclk, eclk to fb_in, fb_in tclk to fb_in, fb_in 150 150 ps ps pll locked t sk(o) output-to-output skew g 150 ps dc output duty cycle 45 50 55 % t jit(cc) cycle-to-cycle jitter rms (1 s ) h tbd ps t jit(per) period jitter rms (1 s ) tbd ps t jit( ? ) i/o phase jitter rms (1 s ) tbd ps bw pll closed loop bandwidth i khz t lock maximum pll lock time 10 ms t r , t f output rise/fall time 0.05 tbd ns 20% to 80% a. ac characteristics are design targets and pending characterization. b. ac characteristics apply for parallel output termination of 50 w to v tt . c. in bypass mode, the mpc9991 divides the input reference clock. d. the input reference frequency must match the vco lock range divided by the total feedback divider ratio: f ref = f vco (m ? vco_sel). e. v pp is the minimum differential input voltage swing required to maintain ac characteristics including tpd and device-to-device ske w. f. v cmr (ac) is the crosspoint of the differential input signal. normal ac operation is obtained when the crosspoint is within the v cmr (ac) range and the input swing lies within the v pp (ac) specification. violation of v cmr (ac) or v pp (ac) impacts the device propagation delay, device and part-to-part skew. g. see application section for part-to-part skew calculation. h. see application section for a jitter calculation for other confidence factors than 1 . i. -3 db point of pll transfer characteristics. idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 7
idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 8 mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 motorola timing solutions 8 applications information mpc9991 configurations configuring the mpc9991 amounts to properly configuring the internal dividers to produce the desired output frequencies. the output frequency can be represented by this formula: vco_sel m n f ref f out f out = f ref ? m n pll where f ref is the reference frequency of the selected input clock source (eclk or tclk), m is the pll feedback divider and n is a output divider. m is configured by the fsel_fb[2:0] and n is configured for all output banks by the fsel[3:0] inputs. the reference frequency f ref and the selection of the feedback-divider m is limited by the specified vco frequency range. f ref and m must be configured to match the vco frequency range of 800 to 1600 mhz in order to achieve stable pll operation: f vco,min (f ref ? vco_sel ? m) f vco,max the pll post-divider vco_sel is either a divide-by-two or a divide-by-four and can be used to situate the vco into the specified frequency range. this divider is controlled by the vco_sel pin. vco_sel effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. the output frequency for each bank can be derived from the vco frequency and output divider: f qa[4:0] = f vco (vco_sel ? n a ) f qb[4:0] = f vco (vco_sel ? n b ) f qc[3:0] = f vco (vco_sel ? n c ) table 9: mpc9991 divider divider function vco_sel values m pll feedback fsel fb[2 0] 2 4, 8, 12, 16, 32, 48, 64 fsel_fb[2:0] 4 8, 16, 24, 32, 64, 96, 128 n a bank a output di id fsel a 2 4, 8, 12, 16 divider fsel_a 4 8, 16, 24, 32 n b bank b output di id fsel b 2 4, 8, 12, 16 divider fsel_b 4 8, 16, 24, 32 n c bank c output di id fsel c 2 4, 8, 12, 16 divider fsel_c 4 8, 16, 24, 32 table 9 shows the various pll feedback and output dividers. the output dividers for the three output banks allow the user to configure the outputs into 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and 4:3:2 frequency ratios. figure 3. and figure 4. display example configurations for the mpc9991: figure 3. example configuration figure 4. example configuration mpc9991 fref = 66.6 mhz 200 mhz 66.6 mhz 66.6 mhz (feedback) 66.6 mhz mpc9991 example configuration (feedback of qfb = 66.6 mhz, vco_sel= 4, m=6, n a =2, n b =6, n c =6, f vco =1600 mhz). frequency range min max input 33.3 mhz 66.6 mhz qa outputs 100 mhz 200 mhz qb outputs 33.3 mhz 66.6 mhz qc outputs 33.3 mhz 66.6 mhz eclk vco_sel sync_sel fsel[3:0] fsel_fb[2:0] qa[3:0] qb[3:0] qc[2:0] qfb tclk ref_sel fb_in 1 0 0100 010 mpc9991 fref = 77.76 mhz 311.04 mhz 155.52 mhz 77.76 mhz (feedback) 77.76 mhz mpc9991 example configuration (feedback of qfb = 77.76 mhz, vco_sel= 2, m=8, n a =2, n b =4, n c =8, f vco =1244.16 mhz). frequency range min max input 50 mhz 100 mhz qa outputs 200 mhz 400 mhz qb outputs 100 mhz 200 mhz qc outputs 50 mhz 100 mhz eclk vco_sel sync_sel fsel[3:0] fsel_fb[2:0] qa[4:0] qb[4:0] qc[3:0] qfb tclk ref_sel fb_in 1 1 0110 001 sync qd[1:0] 77.76 mhz qd[1:0] qd outputs 50 mhz 100 mhz
idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 9 mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 timing solutions 9 motorola sync output description the mpc9991 has a system synchronization pulse generator. in configurations with the output frequency relationships are not integer multiples of each other sync provides a signal for system synchronization purposes. the mpc9991 monitors the relationship between the a bank and the c bank of outputs. the sync output is asserted (logic high) depending on the placement of the clock edges of the qa and qc outputs. the qsync pulse width is equal to the period of the higher of the qa and qc output frequencies. figure 5. shows various waveforms for the sync pulse. the sync signal is defined for all possible combinations of the bank a and bank c outputs. the sync signal is routed to the qd bank of outputs if the sync_sel input is set to logic 0, otherwise the sync signal generation is disabled and the qd outputs match the qc output bank signals. figure 5. qsync timing diagram qa 1:1 mode qc qd (sync) v cc qa 2:1 mode qc qd (sync) qa 3:1 mode qc qd (sync) qa 3:2 mode qc qd (sync) qa 4:3 mode qc qd (sync)
mpc9991 motorola timing solutions 10 power supply filtering the mpc9991 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cc_pll power supply impacts the device characteristics, for instance i/o jitter. the mpc9991 provides separate power supplies for the output buffers (v cc ) and the phase-locked loop (v cc_pll ) of the device. the purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simple but effective form of isolation is a power supply filter on the v cca_pll pin for the mpc9991. figure 6. illustrates a typical power supply filter scheme. the mpc9991 frequency and phase stability is most susceptible to noise with spectral content in the 100khz to 20mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop across the series filter resistor r f . from the data sheet the i cc_pll current (the current sourced through the v cc_pll pin) is typically 3 ma (5 ma maximum), assuming that a minimum of 2.325v (v cc =3.3v or v cc =2.5v) must be maintained on the v cc_pll pin. the resistor r f shown in figure 6. av cc_pll power supply filtero must have a resistance of 9-10 (v cc =2.5v) to meet the voltage drop criteria. figure 6. v cc_pll power supply filter vcc_pll vcc mpc9991 10 nf r f = 910 w c f 33...100 nf r f vcc c f = 22 m f the minimum values for r f and the filter capacitor c f are defined by the required filter characteristics: the rc filter should provide an attenuation greater than 40 db for noise whose spectral content is above 100 khz. in the example rc filter shown in figure 6. av cc_pll power supply filtero, the filter cut-off frequency is around 3-5 khz and the noise attenuation at 100 khz is better than 42 db. as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. although the mpc9991 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. using the mpc9991 in zerodelay applications nested clock trees are typical applications for the mpc9991. designs using the mpc9991 as lvcmos pll fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from cmos fanout buffers. the external feedback option of the mpc9991 clock driver allows for its use as a zero delay buffer. one example configuration is to use a 4 output as a feedback to the pll and configuring all other outputs to a divide-by-4 mode. the propagation delay through the device is virtually eliminated. the pll aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. the maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. this effective delay consists of the static phase offset, i/o jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. calculation of part-to-part skew the mpc9991 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. if the reference clock inputs of two or more mpc9991 are connected together, the maximum overall timing uncertainty from the common cclkx input to any output is: t sk(pp) = t ( ? ) + t sk(o) + t pd, line(fb) + t jit( ? ) cf this maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and i/o (phase) jitter: figure 7. mpc9991 max. device-to-device skew t pd,line(fb) t jit( ? ) + t sk(o) t ( ? ) +t ( ? ) t jit( ? ) + t sk(o) t sk(pp) max. skew eclk common qfb device 1 any q device 1 qfb device2 any q device 2 due to the statistical nature of i/o jitter a rms value (1 ) is specified. i/o jitter numbers for other confidence factors (cf) can be derived from table 10. idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 10 mpc9991 3.3v differential ecl/pecl pll clock generator netcom
idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 11 mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc9991 timing solutions 11 motorola table 10: confidence facter cf cf probability of clock edge within the distribution 1 0.68268948 2 0.95449988 3 0.99730007 4 0.99993663 5 0.99999943 6 0.99999999 the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation a i/o jitter confidence factor of 99.7% ( 3 ) is assumed, resulting in a worst case timing uncertainty from input to any output of -345 ps to 345 ps 1 relative to cclk: t sk(pp) = [150ps...150ps] + [150ps...150ps] + [(15ps 3)...(15ps 3)] + t pd, line(fb) t sk(pp) = [345ps...345ps] + t pd, line(fb) due to the frequency dependence of the i/o jitter, figure 8. amax. i/o jitter versus frequencyo can be used for a more precise timing performance analysis. figure 8. max. i/o jitter versus frequency tbd see mpc961c application section for an example i/o jitter characteristics figure 9. mpc9991 ac test reference differential pulse generator z = 50 r t = 50 w z o = 50 w dut mpc9991 v tt r t = 50 w z o = 50 w v tt
mpc9991 motorola timing solutions 12 outline dimensions fa suffix 52 lead lqfp package case 848d-03 issue d f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums l, m and n to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane t. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). ???? ???? view aa ab ab view y section abab rotated 90 clockwise dim a min max min max inches 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c 1.70 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref c l x x=l, m, n 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h lm n 0.20 (0.008) t lm seating plane c 0.10 (0.004) t 4x 3 4x 2 s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s lm m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 l n m h t 1 g q 1 q q 3 q 2 0 7 12 0 7 0 0 ref 12 ref 3x view y view aa 2x r r1 12 ref 12 ref idt? 3.3v differential ecl/pecl pll clock generator freescale timing solutions organization has been acquired by integrated device technology, inc mpc9991 12 mpc9991 3.3v differential ecl/pecl pll clock generator netcom
mpc9991 3.3v differential ecl/pecl pll clock generator netcom mpc92459 900 mhz low voltage lvds clock synthesizer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom

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