 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| loginid=chunping.miao@nbbsw.com,time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=mt6589_technical_brief_v0.2.docx,company=bird_wcx mt 6589 hspa + smartphone application processor technical brief version: 0 . 2 release date: 2012 - 09 - 26 ? 2011 - 2012 mediatek inc. this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. specifications are subject to change without notice. mediatek confidential for chunping.miao@ nbbsw.com use only free datasheet http:///
o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 2 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. document revision history revision date author description 0. 1 2012 - 0 9 - 14 yc lai first created by yc lai 0.2 2012 - 09 - 2 6 yc lai document revised. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 3 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. table of contents document revision history ................................ ................................ ................................ .................. 2 table of contents ................................ ................................ ................................ ................................ ... 3 1 system overvie w ................................ ................................ ................................ .......................... 6 1.1 platform features ................................ ................................ ................................ ................. 7 1.2 modem features ................................ ................................ ................................ ................. 8 1.3 multimedia features ................................ ................................ ................................ ............. 9 1.4 general descriptions ................................ ................................ ................................ .......... 10 2 produc t description ................................ ................................ ................................ ................... 12 2.1 pin description ................................ ................................ ................................ .................... 12 2.1.1 ball map view ................................ ................................ ................................ ..... 12 2.1.2 pin coordinate ................................ ................................ ................................ .... 13 2.1.3 detail ed pin description ................................ ................................ ..................... 17 2.2 electrical characteristic ................................ ................................ ................................ ...... 29 2.2.1 absolute maximum ratings ................................ ................................ ............... 29 2.2.2 recommended operating conditions ................................ ................................ 30 2.2.3 storage condition ................................ ................................ ............................... 31 2.2.4 ac electrical characteristics and timing diagram ................................ ............ 31 2.3 system configuration ................................ ................................ ................................ ......... 34 2.3.1 mode selection ................................ ................................ ................................ ... 34 2.3.1 constant tie pins ................................ ................................ ............................... 34 2.4 power - on sequence ................................ ................................ ................................ ........... 35 2.5 analog baseband ................................ ................................ ................................ ............... 36 2.5.1 bbrx ................................ ................................ ................................ .................. 37 2.5.2 bbtx ................................ ................................ ................................ .................. 39 2.5.3 2gbbtx ................................ ................................ ................................ ............. 41 2.5.4 apc - dac ................................ ................................ ................................ ........... 42 2.5.5 vbias - dac ................................ ................................ ................................ ........ 43 2.5.6 auxadc ................................ ................................ ................................ ............ 44 2.5.7 clock squarer ................................ ................................ ................................ ..... 46 2.5.8 phase locked loop ................................ ................................ ............................ 46 2.5.9 temperature sensor ................................ ................................ .......................... 51 2.6 pack age information ................................ ................................ ................................ ........... 52 2.6.1 package outlines ................................ ................................ ............................... 52 2.6.2 thermal operating specifications ................................ ................................ ...... 52 2.6.3 lead - free packaging ................................ ................................ .......................... 52 2.7 ordering information ................................ ................................ ................................ ........... 53 2. 7.1 top marking definition ................................ ................................ ....................... 53 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 4 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. list of figures figure 1 - 1: block diagram of mt6589 ................................ ................................ ................................ ... 11 figure 2 - 1 : ball map view of mt6589 ................................ ................................ ................................ .. 12 figure 2 - 2: basic timing parameter for lpddr2 commands ................................ ................................ 32 figure 2 - 3: basic timing parameter for lpddr2 write ................................ ................................ .......... 32 figure 2 - 4: basic timing parameter for lpddr2 read ................................ ................................ .......... 33 figure 2 - 8: power on/off sequence with xtal ................................ ................................ ...................... 35 figure 2 - 9: power on/off sequence without xtal ................................ ................................ ................. 36 figure 2 - 10: block diagram of bbrx - adc ................................ ................................ ........................... 38 figure 2 - 11: block diagram of 2gbbtx ................................ ................................ ................................ 41 figure 2 - 12: block diagram of apc - dac ................................ ................................ .............................. 42 figure 2 - 13: block diagram of vbias - dac ................................ ................................ .......................... 43 figure 2 - 14: block diagram of auxadc ................................ ................................ ............................... 44 figure 2 - 15: block diagram of pll ................................ ................................ ................................ ....... 47 figure 2 - 16: outlines and dimensions of fccsp 11.8mm*11.8mm, 515 - ball, 0.4mm pitch package .. 52 figu re 2 - 17: top mark of mt6589 ................................ ................................ ................................ ......... 53 list of tables table 2 - 1: pin coordinate ................................ ................................ ................................ ...................... 13 table 2 - 2: acronym for pin type ................................ ................................ ................................ ............ 17 table 2 - 3: detailed pin description ................................ ................................ ................................ ........ 17 table 2 - 4: absolute maximum ratings for power supply ................................ ................................ ....... 29 table 2 - 5: recommended operating conditions for power supply ................................ ........................ 30 table 2 - 6: lpddr2 ac timing parameter table of external memory interfaces ................................ .... 33 table 2 - 8: mode selection of chip (pmu 6320 pin) ................................ ................................ ............... 34 table 2 - 9: constant tied pins of mt6589 ................................ ................................ .............................. 34 table 2 - 10: baseband downlink specifications ................................ ................................ ..................... 38 table 2 - 11: baseband uplink transmitter specifications ................................ ................................ ........ 40 table 2 - 12: baseband uplink transmitter specifications ................................ ................................ ........ 41 table 2 - 13: apc - dac specifications ................................ ................................ ................................ ..... 42 table 2 - 14: vbias - dac specifications ................................ ................................ ................................ . 43 table 2 - 15: definitions of auxadc channels ................................ ................................ ....................... 44 table 2 - 16: auxadc specifications ................................ ................................ ................................ ...... 45 table 2 - 17: clock squarer 1 & 2 specifications ................................ ................................ ..................... 46 table 2 - 18: armpll specifications ................................ ................................ ................................ ....... 47 tabl e 2 - 19: mainpll specifications ................................ ................................ ................................ ..... 48 table 2 - 20: mmpll specifications ................................ ................................ ................................ ........ 48 table 2 - 21: isppll specifications ................................ ................................ ................................ ......... 48 table 2 - 22: univpll specifications ................................ ................................ ................................ ...... 49 table 2 - 23: msdcpll specifications ................................ ................................ ................................ .... 49 table 2 - 24: tvdpll specifi cations ................................ ................................ ................................ ....... 49 table 2 - 25: lvdspll specifications ................................ ................................ ................................ ..... 50 table 2 - 26: mdpll1 & mdpll2 specifications ................................ ................................ .................... 50 table 2 - 27: wpll specifications ................................ ................................ ................................ ........... 50 table 2 - 28: whpll specifications ................................ ................................ ................................ ........ 50 table 2 - 29: mcupll1 & mcupll2 specifications ................................ ................................ ............... 51 table 2 - 30 : temperature sensor specifications ................................ ................................ ..................... 51 table 2 - 31: thermal operating specifications ................................ ................................ ....................... 52 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 5 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 6 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 1 s ystem overview mt 6589 is a highly integrated baseband platform incorporat ing both modem and application processing subsystems to enable 3g s mart phone applications. the chip integrates a quad - core arm? cortex - a7 mpcore tm operating up to 1 .2 ghz , an arm ? cortex - r4 mcu and a powerful multi - standard video accelerator . the mt 6589 interfaces to na nd flash memory , 32 - bit lpddr2 for optimal performanc e and also supports booting from slc nand or emmc to mini mize the overall bom cost. in addition, an extensive set of interfaces and connectivity peripherals are included to interface to cameras, touch - screen displays, mmc/sd cards and external bluetooth, wilan and gps modules. the a pplication processor , a quad - core arm? cortex - a7 mpcore tm which include s a neon m ultimedia p rocessing e ngine , offers processing power necessary to support the latest openos along with its demanding applications such as w eb b rowsing , e mail , gps n avigation and g ames. all are viewed on a high resolution touch screen display with graphics enhanced by the 2d and 3d g raphics acceleration. the multi - standard video accelerator and an advanced audio subsystem are also included to provide advanced multimedia applications and services such as s treaming audio and video, a multitude of decoders and encoders such as h.264 and mpeg - 4. a udio support s include fr, hr, efr, amr fr, amr hr and wide - band amr vo code rs , polyphonic ringtones and advanced audio functions such as echo cancellation, h ands - free speakerphone operation and noise cancellation. an arm? cortex - r4 , dsp, and 2g and 3g coprocessors provide a powerful modem subsystem capable of supporting category 24 ( 42.2 mbps) hsdpa downlink and category 7 ( 11.5 mbps) hsupa uplink data rates, as well as class 12 gprs and edge. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 7 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 1.1 platform f eatures ? general ? smartphone two mcu subsystems architecture ? slc nand flash and emmc bootloader ? ap mcu subsystem ? quad - core arm? cortex - a7 mpcore tm operatin g at 1 .2 ghz ? neon multimedia processing engine with simdv2/vfpv4 isa support ? 32kb l1 i - cache and 32kb l1 d - cache ? 1mb unified l2 cache ? dvfs technology with adaptive operating voltage fro m 0.9 5 v to 1.2 6 v ? md mcu subsystem ? arm ? cortex - r4 processor with maximum 480 mhz operation frequency ? 64kb i - cache, 32kb d - cache ? 256kb tcm (tightly - coupled memory) ? dsp for running modem/voice tasks, with maximum 240mhz operation frequency ? high - performance axi and ahb bus ? general dma engine and dedicated dma channels for peripheral data transfer ? watchdog timer for system error recovery ? po wer management for clock gating control ? md e xternal interfaces ? supports d ual sim / usim interface ? interface pins with rf and radio - related peripherals (antenna tuner, pa, ) ? uart for modem logging/debugging purpose ? external m emory i nterface ? supports lpddr 2 up to 2g b ? 32 - bit data bus width ? memory clock up to 533 mhz ? supports s elf - r efresh /partial self - refresh mode ? low - power operation ? programmable slew rate for memory controllers io pads ? supports dual rank memory device ? advanced bandwidth arbitration control ? security ? arm ? trustzone? security ? connectivity ? usb2.0 high - speed otg supporting 15 tx and 15 rx endpoints ? usb 2.0 full - speed host ? nand flash controller supporting nand bootable, inand2? and movinand? ? 4 uart for gps, bt, fm - rds, modem and debugging interfaces ? irda fir/mir/sir ? spi for external device ? 7 i2c to control periphera l devices, e.g. cmos imag e sensor, lcm or fm receiver module ? i2s for connection with optional external hi - end audio codec ? gpios ? 4 sets of memory card controller s supporting sd/sdhc/ms/mspro/mmc and sdio2.0/3.0 protocols ? operating conditions ? core voltage: 1.05v ? processor dvfs voltage: 0.95v ~ 1.26v (typ. 1.05v; s leep mode 0.85v) ? processor sram voltage: 1.05v ~ 1.26v (typ. 1.05v; s leep mode 0.85v) 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 8 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. ? gpu voltage: 1.05v ? i/o voltage: 1.8v/2.8v/3.3v ? memory: 1.2v/1.8v/1.35v/1.5v/1.25v ? nand: 1.8v/2.8v ? lcm interface: 1.8v ? clock source: 26mhz, 32.768khz ? package ? type: fccsp ? 11.8mm x 11.8mm ? height: 1.0mm maximu m ? ball count: 515 balls c ? ball pitch: 0.4mm 1.2 modem f eatures ? 3g umts fdd supported features ( w ith mt6167) ? 3g modem support s most main features in 3gpp release 7 and release 8 ? cpc (dtx in cell_dch, ul drx dl drx) , hs - scch - less , hs - dsch ? dual c ell operation ? mac - ehs ? two drx (receiver diversity) schemes in ura_pch and cell_pch ? uplin k cat. 7 (16 qam), throughput up to 11.5mbps ? downlink cat. 24 (64qam, dual - cell hs dpa), throughput up to 42.2mbps ? fast dormancy ? etws ? network selection enhancements ? 3g t dd supported features ( w ith mt616 8 ) ? td - scdma/hsdpa/hsupa baseband ? supports td - scdma bands 34, 39 & 40 and quad band gsm/edge ? circuit - switched voice and data, and packet - switched data ? 384/384kbps class in ul/dl for td - scdma ? td - hsdpa: 2.8mbps dl (cat.14) ? td - hsupa: 2.2mbps ul (cat.6) ? f8/f9 ciphering/integrity protection ? radio interface and baseband front - end ? high dynamic range delta - sigma adc converts the downlink analog i an d q signals to digital baseband ? 10 - bit d/a c onverter for automatic power control (apc) ? programmable r adio r x filter with adaptive gain control ? dedicated r x filter for f b acquisition ? baseband parallel interface (bpi) with programmable driving strength (shared by 2g & 3g modem) ? supports m ulti - band ? gsm modem and voice codec ? dial tone generation ? noise reduction ? echo suppression ? advanced sidetone o scillation r eduction ? digita l sidetone generator with programmable gain ? two programmable acoustic compensation filters ? gsm quad vocoders for adaptive multirate (amr), enhanced full rate (efr), full rate (fr) and half rate (hr) ? gsm channel coding, equalization and a5/1, a5/2 and a5/3 ciphering ? gprs gea1, gea2 and gea3 ciphering ? programmable gsm/gprs /edge modem ? packet s witched d ata with cs1/cs2/cs3/cs4 coding schemes 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 9 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. ? gsm c ircuit s witch d ata ? gprs /edge class 12 ? support s saic (single antenna interference cancellation) technology ? support s vamos (voice services over adaptive multi - user channels on one slot) technology in r9 spec 1.3 multimedia f eatures ? display ? supports landscape or portrait panel resolution up to wxga (1280x800) ? supports 8/9/16/18/24 - bit host interface (mipi dbi) ? supports 8/9/16/24/32 - bit serial interfaces ? supports 16/18/24 - bit rgb interfaces (mipi dpi) ? mipi dsi interface (4 data lanes) ? embedded lcd gamma correction ? support s true colors ? 4 overlay layers with per - pixel alpha channel and gamma table ? supports spatial and temporal dithering ? supports side - by - side format output to stereo 3d panel in both portrait and landscape modes ? supports external hdmi/mhl tx bridge with 720p vi deo output ? supports color enhancement ? supports adaptive contrast enhancement ? supports image/video/graphic s harpness enhancement ? supports dynamic backlight scaling ? graphics ? opengl es 1.1/2.0 3d graphic accelerator capable of processing 50 m tri/sec and 572 m pixel/sec @ 286 mhz ( effective pixel rate: 1 , 430 m pixel/sec . ) ? openvg1.1 vector graphics accelerator ? 2d graphics hardware accelerator ? image ? integrated image signal processor support s 1 3 mp up to 15fps ? supports electronic image stabilization ? supports video stabilization ? supports local contrast enhancement ? supports preference color adjustment ? supports noise reduction ? supports multiple frame noise reduction for video recording ? supports lens shading correction ? supports auto sensor defect pixel correction ? suppor ts ae/awb/af ? supports edge enhancement (sharpness) ? supports face detection and visual tracking ? supports multiple frame blending for multi - motion special effect ? supports zero shutter delay image capture ? supports capturing full size image when recording vide o (up to 8m sensor) ? supports capturing stereo image without bridge ic ? supports stereo video recording without bridge ic ? supports mipi csi - 2 high - speed camera serial interface with 4 data lane (for main) + 2 data lane (for stereo) + 2 data lane (for sub) ? su pports xenon flash 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 10 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. ? hardware jpeg decoder: b aseline decoding with 42m pixel/sec, progressive format decoding support ? hardware jpeg encoder: b aseli ne encoding with 90m pixel/sec ? supports yuv422/yuv420 color format and exif/jfif format ? hardware webp decoder ? video ? h.264 decoder: b aseline 1080p @ 30fps/40mbps ? h.264 decoder: m ain/high profile 1080p@30fps/40mbps ? sorenson h.263/h.263 decoder: 1080p @ 30fps/40mbps ? mpeg - 4 sp/asp decoder: 1080p @ 30fps/40mbps ? divx3/divx4/divx5/divx6/divx hd/xvid decoder: 1080p @ 30fps/40mbps ? vp8 decoder: 1080p @ 30fps/40mbps ? vc - 1 decoder: 1080p @ 30fps/40mbps ? mpeg - 4 encoder: s imple profile 1080p @ 30fps ? h.263 encoder: 1080p @ 30fps ? h.264 encoder: h igh profile 720p @ 30fps ? vp8 encoder: 720p@ 30fps ? audio ? sampling rates supported: 6 khz to 96khz ? samp le formats supported: 8 - bit/16 - bit, mono/stereo ? interfaces supported: dai, i2s, pcm ? 4 - band iir compensation filter to enhance loudspeaker responses ? proprietary audio post - processing technologies: besloudness, android built - in post processi ng ? audio encode: amr - nb, amr - wb, aac, ogg ? audio decode: wav, mp3, mp2, aac, amr - nb, amr - wb, midi, vorbis, ape, aac - plus v1, aac - plus v2, flac, wma ? speech ? s peech c odec (fr, hr, efr, amr fr, amr hr and wide - band amr) ? ctm ? noise r eduction ? noise suppression ? noise cancellation ? dual - mic noise cancellation ? echo cancellation ? echo suppression ? dual - mic input ? digital mic input 1.4 general d escription s mediatek mt 6589 is a highly integrated 3g s ystem - on - chip (s o c) which incorporates advanced features e.g. hspa r 8 modem, quad - core arm? cortex - a7 mpcore tm operating a t 1 .2 ghz , 3 d graphics (opengl|e s 2.0), 1 3 m camera isp, lpddr2 533 mhz and h igh - d efinition 1080 p video decoder. mt 6589 helps phone manufacturers build high - performance 3g smart phone s with pc - like browser, 3d gaming and cinema class home entertainment experience s . world - l eading t echnology 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 11 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. based on mediateks world - leading mob ile chip s o c architecture with advanced 28 nm p rocess, mt 6589 is the b rand - new generation smart phone s o c integrat ing mediatek hspa r 8 modem, 1 .2 g hz quad - core arm? cortex - a7 mpcore tm , 3d graphics and h igh - d efinition 1080 p video decoder. rich in f eature s, h igh - v alued p roduct to enrich the camera feature s , mt 6589 equips a 13 m camera isp with advanced features e.g. auto focus, anti - handshake, auto sensor defect pixel correction , continuous video af, face detection, burst shot, optical zoom and panorama view. incredible b rowser experience the 1 .2 ghz q uad - core arm? cortex - a7 mpcore tm with neon m ultimedia p rocessing e ngine brings pc - like browser experience s and help s accelerate opengl|es 2.0 3d adobe flash 10 rendering performance to an unbeatable level. figure 1 - 1 : blo c k d iag ram of mt 6589 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < m t 6 3 2 0 a r m ? t r u s t z o n e ? p o w e r v r ? s g x 5 4 4 g r a p h i c s a c c e l e r a t o r s i m s i m m m c / s d / s d i o q w e r t y k e y p a d l p d d r 2 u s b 2 . 0 o t g u s b 2 . 0 h o s t i 2 c c a m e r a i s p l c d c o n t r o l i m a g e p o s t - p r o c e s s j p e g c o d e c v i d e o c o d e c m u l t i m e d i a i n t e r n a l m e m o r y d m a a r m ? c o r t e x - r 4 c a c h e t c m j t a g g p t i m e r m o d e m m c u e x t e r n a l m e m o r y i n t e r f a c e p o w e r m a n a g e m e n t p l l d a c a n a l o g d s p u a r t 1 3 m p c a m e r a l c d b a t t e r y s p e a k e r m i c 2 m i c 1 m t 6 6 2 8 t o u c h p a n e l g p i o n a n d f l a s h h s p a + g s m / g p r s / e d g e m o d e m r x a d c t x a d c a f c a p c m o d e m a n a l o g b t / f m w i f i / g p s j t a g h e a d s e t a d c m t 6 5 8 9 m t 6 1 6 7 f o r w c d m a e d g e r f w c d m a r f a r m ? c o r t e x - a 7 m p c o r e t m a r m ? c o r t e x - a 7 m p c o r e t m a r m ? c o r t e x - a 7 m p c o r e t m a r m ? c o r t e x - a 7 m p c o r e t m n e o n l 2 c a c h e a p m c u m t 6 1 6 8 f o r t d s c d m a t d s c d m a r f e d g e r f free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 12 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2 product d escription 2.1 pin description 2.1.1 ball m ap v iew figure 2 - 1 : b all map vie w of mt 6589 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 13 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.1.2 pin coordinate table 2 - 1 : pin c oordinate ball loc. ball n ame ball loc. ball n ame ball loc. ball n ame a1 nc k12 gnd w19 gnd a2 scl2 k13 dvdd18_emi w20 dvdd a4 msdc3_dat0 k15 dvdd18_emi w24 gnd a5 rdq9 k16 gnd w25 urxd4 a8 rdqm0 k17 gnd w26 urxd2 a9 rdq5 k18 gnd w27 pwm1 a12 rdq15 k20 dvdd18_emi w28 urts2 a13 ra6 k25 adc_clk y1 dvdd33_mc2 a15 ra4 k26 adc_ws y2 msdc1_insi a17 rdq30 k28 adc_dat_in y3 msdc2_insi a20 rdq21 l1 rdp0 y4 msdc2_dat1 a21 rdqm2 l2 rdn1_a y5 dpib4 a24 rdq26 l3 rdp0_a y24 dvdd28_nml2 a25 msdc0_dat4 l4 rcp_a y25 urts1 a27 msdc0_dat5 l7 dvdd18_mipirx y26 urxd1 a28 msdc0_cmd l24 gnd y27 utxd1 a29 nc l25 testmode y28 utxd4 b1 sda2 l26 dac_ws y29 ucts1 b2 mrg_i2s_pcm_clk l27 dac_dat_out aa1 dpib7 b3 urxd3 l28 pwrap_event aa2 dpig7 b4 msdc3_dat1 l29 pwrap_spi0_csn aa5 dpig5 b5 rdq8 m1 rdn0 aa6 gnd b7 rdq0 m2 rdp2 aa25 chd_dm_p0 b8 rdq3 m3 rdn1 aa26 pwm3 b9 rdq4 m4 rcp aa28 pwm4 b11 rdq12 m6 dvss18_mipirx aa29 pwm2 b12 rdq14 m15 avss18_mempll ab2 dpir2 b13 ra12 m16 avdd18_mempll ab4 dpib3 b14 rba0 m24 sim2_sclk ab5 dpig1 b15 rcas_ m25 sim1_sio ab11 vproc_fb b17 rdq31 m26 pwrap_spi0_mi ab25 chd_dp_p0 b18 rdq28 m27 dac_clk ab26 avss33_usb_p0 b20 rdq20 m28 pwrap_spi0_mo ab27 usb_dm_p0 b21 rdq18 m29 pwrap_spi0_clk ab28 avdd33_usb_p0 b22 rdq16 n2 rdn2 ac1 dpig0 b24 rdq25 n3 rdp1 ac2 dpihsync b25 msdc0_dat2 n4 rcn ac3 dpib0 b26 msdc0_dat0 n10 dvdd ac4 dpir6 b27 msdc0_dat6 n11 dvdd ac5 dpib1 b28 nld4 n12 dvdd ac26 avdd18_usb_p1 b29 nrnb n13 dvdd ac27 usb_dp_p0 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 14 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. ball loc. ball n ame ball loc. ball n ame ball loc. ball n ame c1 sda1 n14 dvdd ad1 dpivsync c2 mrg_i2s_pcm_rx n15 dvdd ad2 dpir5 c3 mrg_i2s_pcm_sync n16 dvdd ad3 dpig3 c4 msdc3_clk n17 dvdd ad4 dpib6 c5 gnd n18 tn_mempll ad5 dpir3 c6 rdq11 n19 tp_mempll ad6 dpig4 c7 rdq10 n24 sim2_sio ad8 i2s_data_out c8 gnd n25 sim1_sclk ad10 eint10_auxin2 c9 rdqm1 n28 sim2_srst ad11 gnd_vproc_fb c10 rdq6 p1 rdn3 ad12 avss18_ap c11 rdq13 p2 rdp3 ad16 avss18_md c12 rba1 p3 tdn0 ad20 gnd c14 rras_ p4 tdp1 ad24 gnd c15 rodt p6 tdn3 ad27 avdd18_usb_p0 c16 ra3 p7 tdp3 ad28 usb_vrt c17 ra5 p8 tcp ad29 usb_dm_p1 c18 rdqm3 p10 dvdd ae2 dpib5 c19 rdq22 p11 gnd ae5 dpir0 c20 rdq23 p12 gnd ae6 lsa0 c21 gnd p13 gnd ae7 disp_pwm c22 rdq24 p14 gnd ae8 eint5 c23 rdq27 p15 gnd ae9 sda0 c24 gnd p16 gnd ae10 eint11_auxin3 c26 msdc0_dat1 p17 dvdd ae11 aux_xm c27 msdc0_clk p18 dvdd ae12 aux_yp c28 nld0 p19 dvdd ae13 avss18_ap c29 nld7 p20 dvdd ae17 avss18_md d2 scl1 p25 rtc32k_ck ae20 bsi1a_cs0 d3 msdc3_dat3 p26 srclkena ae21 bsi1a_data1 d4 msdc3_dat2 p28 sim1_srst ae22 bsi1b_data d5 msdc3_cmd p29 srcvolten ae23 bsi1b_cs0 d6 rdq1 r1 tdp2 ae24 bpi1_bus18 d7 gnd r2 tdn2 ae25 dvdd28_bpi d8 rdq2 r3 tdp0 ae26 bpi1_bus16 d9 gnd r4 tdn1 ae27 usb_vbus d10 rdq7 r6 vrt ae28 avss33_usb_p1 d11 gnd r7 tcn ae29 usb_dp_p1 d12 ra14 r10 gnd af1 dvdd18_nml3 d13 ra1 r11 gnd af2 dpir4 d14 ra10 r12 dvdd_dvfs af4 dpide d17 ra13 r13 gnd af5 spi1_mo d18 gnd r14 gnd af6 lpce1b d19 rdq29 r15 dvdd_dvfs af8 eint9 d20 gnd r16 gnd af9 scl0 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 15 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. ball loc. ball n ame ball loc. ball n ame ball loc. ball n ame d21 rdq19 r17 dvdd af10 eint16_auxin4 d22 gnd r18 gnd af12 aux_xp d23 rdq17 r19 dvdd af13 ul_q_n2 d24 fsource_p r20 gnd af14 ul_q_p2 d25 msdc0_dat3 r24 dvdd18_mc0 af15 dl_q_p2 d26 msdc0_dat7 r25 eint4 af16 dl_q_n2 d27 ncle r26 iddig af17 ul_i_n1 d28 nld14 r27 eint3 af18 ul_i_p1 e1 dai_rstb r28 watchdog af19 ul_q_p1 e2 mrg_i2s_pcm_tx r29 sysrstb af20 ul_q_n1 e5 srclkenai t2 dvss18_mipitx af21 bsi1c_clk e6 rdqs0 t3 dvdd18_mipitx af22 srclkena2 e9 rdqs1_ t4 msdc1_dat1 af23 bsi1b_clk e11 ra8 t5 msdc1_dat3 af24 bpi1_bus11 e12 ra11 t8 gnd af26 bpi1_bus6 e13 rcke t9 gnd af27 bpi1_bus4 e14 rcs_ t10 dvdd_gpu af28 vm0 e15 rextdn t11 gnd af29 avdd33_usb_p1 e16 rwe_ t12 dvdd_dvfs ag1 dpib2 e17 ddr3rstb t13 gnd ag2 dpir7 e18 ra0 t14 gnd ag3 dpir1 e20 rdqs3 t15 dvdd_dvfs ag4 lsck e23 rdqs2_ t16 gnd ag5 spi1_clk e25 msdc0_rstb t17 dvdd ag8 eint7 e26 nld11 t18 gnd ag9 i2s_clk e28 nld8 t19 dvdd ag12 aux_ym e29 nceb0 t20 gnd ag13 ul_i_p2 f1 dvdd18_nml4 t25 jtrst_b ag14 ul_i_n2 f2 cmpdn t26 eint2 ag15 dl_i_p2 f4 utxd3 t27 eint1 ag16 dl_i_n2 f6 rdqs0_ t28 eint0 ag17 dvdd18_md f9 rdqs1 u1 dvdd33_mc1 ag18 vbias f12 rcs1_ u2 msdc1_clk ag19 apc2 f16 ra2 u5 msdc1_cmd ag20 apc1 f17 ra7 u6 msdc1_sdwpi ag22 bsi1a_data2 f18 ra9 u8 gnd ag23 dvdd28_bsi f20 rdqs3_ u9 dvdd_gpu ag26 bpi1_bus1 f23 rdqs2 u10 dvdd_gpu ag27 bpi1_bus8 f25 nld12 u11 gnd ag28 bpi1_bus5 f28 nld13 u12 dvdd_dvfs ah1 dpig2 f29 nweb u13 dvdd_dvfs ah2 dpig6 g2 cmflash u14 dvdd_dvfs ah3 lsda g3 cmmclk u15 dvdd_dvfs ah4 lpce0b g4 cmpclk u16 gnd ah5 spi1_mi 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 16 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. ball loc. ball n ame ball loc. ball n ame ball loc. ball n ame g25 nld15 u17 dvdd ah6 lrstb g26 nld1 u18 gnd ah7 lpte g27 nld3 u19 dvdd ah8 eint6 g28 nld6 u20 dvdd ah9 i2s_ws h1 dvdd18_mipiio u24 jtck ah10 auxin1 h2 cmrst u25 jrtck ah11 auxin0 h3 rdn0_b u28 jtdo ah12 refp h4 rcn_b u29 jtdi ah13 refn h10 dvdd18_emi v1 msdc1_dat0 ah14 avdd18_md h12 rclk1 v2 msdc1_dat2 ah16 dl_i_n1 h13 rclk1_ v4 msdc2_dat0 ah17 dl_q_n1 h14 vref v5 msdc2_sdwpi ah18 dl_q_p1 h15 rclk0_ v6 gnd ah19 avdd28_dac h16 rclk0 v7 gnd ah20 txbpi1 h18 vref v8 gnd ah21 bsi1a_data0 h19 dvdd18_emi v9 dvdd_gpu ah22 bsi1a_clk h20 dvdd18_emi v10 dvdd_gpu ah23 bsi1c_data h25 nld10 v11 gnd ah24 bpi1_bus10 h26 nale v12 dvdd_dvfs ah25 bpi1_bus13 h27 nld2 v13 dvdd_dvfs ah26 bpi1_bus9 h28 nld5 v14 dvdd_dvfs ah27 bpi1_bus17 h29 nceb1 v15 dvdd_dvfs ah28 bpi1_bus3 j1 rdn1_b v16 gnd ah29 vm1 j2 rdp1_b v17 dvdd aj1 nc j3 rdp0_b v18 gnd aj2 dpick j4 rcp_b v19 gnd aj3 lsce0b j6 gnd v20 dvdd aj5 lsce1b j10 dvdd18_emi v24 utxd2 aj6 spi1_csn j11 dvdd18_emi v25 ucts2 aj8 eint8 j14 gnd v26 jtms aj9 i2s_data_in j17 dvdd18_emi v28 sda3 aj11 dvdd18_pllgp j18 dvdd18_emi v29 scl3 aj12 avdd18_ap j19 dvdd18_emi w2 msdc2_dat2 aj14 clk26m2 j20 dvdd18_emi w3 msdc2_clk aj16 dl_i_p1 j25 nreb w4 msdc2_cmd aj19 clk26m1 j28 nld9 w5 msdc2_dat3 aj21 ext_clk_en j29 dvdd18_nml1 w8 dvdd18_mc12 aj22 dvdd18_bsi k2 rdp1_a w11 gnd aj24 bpi1_bus0 k3 rdn0_a w12 dvdd_dvfs aj25 bpi1_bus7 k4 rcn_a w13 dvdd_sram aj27 bpi1_bus2 k6 dvss18_mipiio w14 dvdd_sram aj28 bpi1_bus12 k10 gnd w15 dvdd_dvfs aj29 nc k11 gnd w16 gnd 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 17 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.1.3 detailed pin description table 2 - 2 : acronym for pin type abbreviation description ai analog input ao analog output aio analog bi - direction di digital input do digital output dio digital bi - direction p power g ground table 2 - 3 : detail ed pin description pin n ame type description power d omain system sysrstb dio system reset input dvdd18_nml1 watchdog do watchdog reset output dvdd18_nml1 srcvolten dio wakeup signal to external pmic dvdd18_nml1 testmode dio test mode dvdd18_nml1 rtc32k_ck dio 32k clock intput dvdd18_nml1 srclkenai dio 26mhz co - clock enable input dvdd18_nml4 srclkena dio 26mhz co - clock enable output dvdd18_nml1 pmic pwrap_spi0_mo dio pmic spi control interface dvdd18_nml1 pwrap_spi0_mi dio pmic spi control interface dvdd18_nml1 pwrap_spi0_csn dio pmic spi control interface dvdd18_nml1 pwrap_spi0_clk dio pmic spi control interface dvdd18_nml1 pwrap_event dio pmic spi control interface dvdd18_nml1 adc_clk dio pmic a udio input interface dvdd18_nml1 adc_ws dio pmic a udio input interface dvdd18_nml1 adc_dat_in dio pmic a udio input interface dvdd18_nml1 dac_clk dio pmic a udio output interface dvdd18_nml1 dac_ws dio pmic a udio output interface dvdd18_nml1 dac_dat_out dio pmic a udio output interface dvdd18_nml1 sim sim1_sio dio sim1 data, pmic interface dvdd18_nml1 sim1_srst dio sim1 reset, pmic interface dvdd18_nml1 sim1_sclk dio sim1 clock, pmic interface dvdd18_nml1 sim2_sio dio sim2 data, pmic interface dvdd18_nml1 sim2_srst dio sim2 reset, pmic interface dvdd18_nml1 sim2_sclk dio sim2 clock, pmic interface dvdd18_nml1 jtag jtck dio jtck dvdd18_nml1 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 18 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain jtdo dio jtdo dvdd18_nml1 jtrst_b dio jtrst_b dvdd18_nml1 jtdi dio jtdi dvdd18_nml1 jrtck dio jrtck dvdd18_nml1 jtms dio jtms dvdd18_nml1 lcd disp_pwm dio display pwm output dvdd18_nml3 lpce1b dio parallel display interface chip select 1 output dvdd18_nml3 lpce0b dio parallel display interface chip select 0 output dvdd18_nml3 lpte dio parallel display interface tearing effect dvdd18_nml3 lrstb dio parallel display interface reset signal dvdd18_nml3 dpi dpide dio data enable signal of dpi dvdd18_nml3 dpick dio clock pin of dpi dvdd18_nml3 dpivsync dio vertical synchronization signal of dpi dvdd18_nml3 dpihsync dio horizontal synchronization signal of dpi dvdd18_nml3 dpir7 dio data pin 7 of dpi r - channel/data 23 for dbi parallel lcd interface dvdd18_nml3 dpir6 dio data pin 6 of dpi r - channel/data 22 for dbi parallel lcd interface dvdd18_nml3 dpir5 dio data pin 5 of dpi r - channel/data 21 for dbi parallel lcd interface dvdd18_nml3 dpir4 dio data pin 4 of dpi r - channel/data 20 for dbi parallel lcd interface dvdd18_nml3 dpir3 dio data pin 3 of dpi r - channel/data 19 for dbi parallel lcd interface dvdd18_nml3 dpir2 dio data pin 2 of dpi r - channel/data 18 for dbi parallel lcd interface dvdd18_nml3 dpir1 dio data pin 1 of dpi r - channel/data 17 for dbi parallel lcd interface dvdd18_nml3 dpir0 dio data pin 0 of dpi r - channel/data 16 for dbi parallel lcd interface dvdd18_nml3 dpig7 dio data pin 7 of dpi g - channel/data 15 for dbi parallel lcd interface dvdd18_nml3 dpig6 dio data pin 6 of dpi g - channel/data 14 for dbi parallel dvdd18_nml3 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 19 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain lcd interface dpig5 dio data pin 5 of dpi g - channel/data 13 for dbi parallel lcd interface dvdd18_nml3 dpig4 dio data pin 4 of dpi g - channel/data 12 for dbi parallel lcd interface dvdd18_nml3 dpig3 dio data pin 3 of dpi g - channel/data 11 for dbi parallel lcd interface dvdd18_nml3 dpig2 dio data pin 2 of dpi g - channel/data 10 for dbi parallel lcd interface dvdd18_nml3 dpig1 dio data pin 1 of dpi g - channel/data 9 for dbi parallel lcd interface dvdd18_nml3 dpig0 dio data pin 0 of dpi g - channel/data 8 for dbi parallel lcd interface dvdd18_nml3 dpib7 dio data pin 7 of dpi b - channel/data 7 for dbi parallel lcd interface dvdd18_nml3 dpib6 dio data pin 6 of dpi b - channel/data 6 for dbi parallel lcd interface dvdd18_nml3 dpib5 dio data pin 5 of dpi b - channel/data 5 for dbi parallel lcd interface dvdd18_nml3 dpib4 dio data pin 4 of dpi b - channel/data 4 for dbi parallel lcd interface dvdd18_nml3 dpib3 dio data pin 3 of dpi b - channel/data 3 for dbi parallel lcd interface dvdd18_nml3 dpib2 dio data pin 2 of dpi b - channel/data 2 for dbi parallel lcd interface dvdd18_nml3 dpib1 dio data pin 1 of dpi b - channel/data 1 for dbi parallel lcd interface dvdd18_nml3 dpib0 dio data pin 0 of dpi b - channel/data 0 for dbi parallel lcd interface dvdd18_nml3 slcd lsce0b dio serial display interface chip select 0 output dvdd18_nml3 lsck dio serial display interface clock output dvdd18_nml3 lsce1b dio serial display interface chip select 1 output dvdd18_nml3 lsda dio serial display interface data dvdd18_nml3 lsa0 dio serial display interface address dvdd18_nml3 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 20 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain output i2s i2s_data_in dio i2s data input pin dvdd18_nml3 i2s_data_out dio i2s data output pin dvdd18_nml3 i2s_ws dio i2s word select dvdd18_nml3 i2s_ck dio i2s clock dvdd18_nml3 pcm/i2s m erge i nterface mrg_i2s_pcm_tx dio pcm/i2s/ m erge a udio i nterface to mt6628 dvdd18_nml4 mrg_i2s_pcm_clk dio pcm/i2s/ m erge a udio i nterface to mt6628 dvdd18_nml4 mrg_i2s_pcm_rx dio pcm/i2s/ m erge a udio i nterface to mt6628 dvdd18_nml4 mrg_i2s_pcm_syn c dio pcm/i2s/ m erge a udio i nterface to mt6628 dvdd18_nml4 dai_rstb dio pcm/i2s/ m erge a udio i nterface to mt6628 dvdd18_nml4 eint eint0 dio external interrupt 0 dvdd18_nml1 eint1 dio external interrupt 1 dvdd18_nml1 eint2 dio external interrupt 2 dvdd18_nml1 eint3 dio external interrupt 3 dvdd18_nml1 eint4 dio external interrupt 4 dvdd18_nml1 eint5 dio external interrupt 5 dvdd18_nml3 eint6 dio external interrupt 6 dvdd18_nml3 eint7 dio external interrupt 7 dvdd18_nml3 eint8 dio external interrupt 8 dvdd18_nml3 eint9 dio external interrupt 9 dvdd18_nml3 eint10_aux_in2 dio/aio external interrupt 10/ aux adc external channel 2 dvdd18_nml3 eint11_aux_in3 dio/aio external interrupt 11/ aux adc external channel 3 dvdd18_nml3 eint16_aux_in4 dio/aio external interrupt 16/ aux adc external channel 4 dvdd18_nml3 pwm pwm1 dio pwm1 dvdd28_nml2 pwm2 dio pwm2 dvdd28_nml2 pwm3 dio pwm3 dvdd28_nml2 pwm4 dio pwm4 dvdd28_nml2 uart1 urxd1 dio uart1 rx dvdd28_nml2 urts1 dio uart1 rts dvdd28_nml2 ucts1 dio uart1 cts dvdd28_nml2 utxd1 dio uart1 tx dvdd28_nml2 uart2 utxd2 dio uart2 tx dvdd18_nml1 urxd2 dio uart2 rx dvdd18_nml1 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 21 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain ucts2 dio uart2 cts dvdd18_nml1 urts2 dio uart2 rts dvdd18_nml1 uart3 utxd3 dio uart3 tx dvdd18_nml4 urxd3 dio uart3 rx dvdd18_nml4 uart4 utxd4 dio uart4 tx dvdd28_nml2 urxd4 dio uart4 rx dvdd28_nml2 spi spi1_csn dio spi1 chip select dvdd18_nml3 spi1_mi dio spi1 data in dvdd18_nml3 spi1_mo dio spi1 data out dvdd18_nml3 spi1_clk dio spi1 clock dvdd18_nml3 bpi bpi_bus0 dio bpi bus0 dvdd28_bpi bpi_bus1 dio bpi bus1 dvdd28_bpi bpi_bus2 dio bpi bus2 dvdd28_bpi bpi_bus3 dio bpi bus3 dvdd28_bpi bpi_bus4 dio bpi bus4 dvdd28_bpi bpi_bus5 dio bpi bus5 dvdd28_bpi bpi_bus6 dio bpi bus6 dvdd28_bpi bpi_bus7 dio bpi bus7 dvdd28_bpi bpi_bus8 dio bpi bus8 dvdd28_bpi bpi_bus9 dio bpi bus9 dvdd28_bpi bpi_bus10 dio bpi bus10 dvdd28_bpi bpi_bus11 dio bpi bus11 dvdd28_bpi bpi_bus12 dio bpi bus12 dvdd28_bpi bpi_bus13 dio bpi bus13 dvdd28_bpi bpi_bus16 dio bpi bus16 dvdd28_bpi bpi_bus17 dio bpi bus17 dvdd28_bpi bpi_bus18 dio bpi bus18 dvdd28_bpi vm vm1 dio pa mode selection dvdd28_bpi vm0 dio pa mode selection dvdd28_bpi bsi bsi1a_cs0 dio bsi1a cs0 dvdd18_bsi bsi1a_clk dio bsi1a clk dvdd18_bsi bsi1a_data0 dio bsi1a data0 dvdd18_bsi bsi1a_data1 dio bsi1a data1 dvdd18_bsi bsi1a_data2 dio bsi1a data2 dvdd18_bsi bsi1b_cs0 dio bsi1b cs0 dvdd28_bsi bsi1b_clk dio bsi1b clk dvdd28_bsi bsi1b_data dio bsi1b data dvdd28_bsi bsi1c_clk dio bsi1c clk dvdd18_bsi bsi1c_data dio bsi1c data dvdd18_bsi 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 22 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain txbpi1 dio rf mt6167 txbpi1 dvdd18_bsi ext_clk_en dio co - c lock control pin dvdd18_bsi srclkena2 dio co - c lock control pin dvdd18_bsi msdc0 msdc0_dat6 dio msdc0 data6 pin dvdd18_mc0 msdc0_dat7 dio msdc0 data7 pin dvdd18_mc0 msdc0_dat5 dio msdc0 data5 pin dvdd18_mc0 msdc0_rstb dio msdc0 reset output dvdd18_mc0 msdc0_dat4 dio msdc0 data4 pin dvdd18_mc0 msdc0_dat2 dio msdc0 data2 pin dvdd18_mc0 msdc0_dat3 dio msdc0 data3 pin dvdd18_mc0 msdc0_cmd dio msdc0 command pin dvdd18_mc0 msdc0_clk dio msdc0 clock output dvdd18_mc0 msdc0_dat1 dio msdc0 data1 pin dvdd18_mc0 msdc0_dat0 dio msdc0 data0 pin dvdd18_mc0 msdc1 msdc1_clk dio msdc1 clock output dvdd33_mc1/dvdd18_mc12 msdc1_cmd dio msdc1 command pin dvdd33_mc1/dvdd18_mc12 msdc1_dat0 dio msdc1 data0 pin dvdd33_mc1/dvdd18_mc12 msdc1_dat1 dio msdc1 data1 pin dvdd33_mc1/dvdd18_mc12 msdc1_dat2 dio msdc1 data2 pin dvdd33_mc1/dvdd18_mc12 msdc1_dat3 dio msdc1 data3 pin dvdd33_mc1/dvdd18_mc12 msdc1_sdwpi dio msdc1 wp pin dvdd33_mc1/dvdd18_mc12 msdc1_insi dio msdc1 card insertion dvdd18_nml3 msdc2 msdc2_clk dio msdc2 clock output dvdd33_mc2/dvdd18_mc12 msdc2_cmd dio msdc2 command pin dvdd33_mc2/dvdd18_mc12 msdc2_dat0 dio msdc2 data0 pin dvdd33_mc2/dvdd18_mc12 msdc2_dat1 dio msdc2 data1 pin dvdd33_mc2/dvdd18_mc12 msdc2_dat2 dio msdc2 data2 pin dvdd33_mc2/dvdd18_mc12 msdc2_dat3 dio msdc2 data3 pin dvdd33_mc2/dvdd18_mc12 msdc2_sdwpi dio msdc2 wp pin dvdd33_mc2/dvdd18_mc12 msdc2_insi dio msdc2 card insertion dvdd33_mc2/dvdd18_mc12 msdc3 msdc3_clk dio msdc3 clock output dvdd18_nml4 msdc3_cmd dio msdc3 command pin dvdd18_nml4 msdc3_dat0 dio msdc3 data0 pin dvdd18_nml4 msdc3_dat1 dio msdc3 data1 pin dvdd18_nml4 msdc3_dat2 dio msdc3 data2 pin dvdd18_nml4 msdc3_dat3 dio msdc3 data3 pin dvdd18_nml4 nfi nceb0 dio parallel nand interface chip select 0 output dvdd18_nml1 nceb1 dio parallel nand interface chip select 1 output dvdd18_nml1 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 23 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain nrnb dio parallel nand interface chip ready input dvdd18_nml1 ncle dio parallel nand interface command latch enable output dvdd18_nml1 nale dio parallel nand interface address latch enable output dvdd18_nml1 nreb dio parallel nand interface read strobe output dvdd18_nml1 nweb dio parallel nand interface write strobe output dvdd18_nml1 nld0 dio nand - flash data 0 dvdd18_nml1 nld1 dio nand - flash data 1 dvdd18_nml1 nld2 dio nand - flash data 2 dvdd18_nml1 nld3 dio nand - flash data 3 dvdd18_nml1 nld4 dio nand - flash data 4 dvdd18_nml1 nld5 dio nand - flash data 5 dvdd18_nml1 nld6 dio nand - flash data 6 dvdd18_nml1 nld7 dio nand - flash data 7 dvdd18_nml1 nld8 dio nand - flash data 8 dvdd18_nml1 nld9 dio nand - flash data 9 dvdd18_nml1 nld10 dio nand - flash data 10 dvdd18_nml1 nld11 dio nand - flash data 11 dvdd18_nml1 nld12 dio nand - flash data 12 dvdd18_nml1 nld13 dio nand - flash data 13 dvdd18_nml1 nld14 dio nand - flash data 14 dvdd18_nml1 nld15 dio nand - flash data 15 dvdd18_nml1 efuse fsource_p dio e - fuse b lowing p ower c ontrol fsource_p emi ddr3rstb dio ddr3 reset output # dvdd18_emi rclk0 dio dram clock 0 output dvdd18_emi rclk0_ dio dram clock 0 output # dvdd18_emi rclk1 dio dram clock 1 output dvdd18_emi rclk1_ dio dram clock 1 output # dvdd18_emi rcke dio dram command output cke dvdd18_emi rcs_ dio dram chip select 0 # dvdd18_emi rcs1_ dio dram chip select 1 # dvdd18_emi rcas_ dio dram command output cas# dvdd18_emi rras_ dio dram command output ras# dvdd18_emi rwe_ dio dram command output wr# dvdd18_emi rba0 dio dram bank address output 0 dvdd18_emi rba1 dio dram bank address output 1 dvdd18_emi ra0 dio dram address output 0 dvdd18_emi ra1 dio dram address output 1 dvdd18_emi ra2 dio dram address output 2 dvdd18_emi ra3 dio dram address output 3 dvdd18_emi 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 24 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain ra4 dio dram address output 4 dvdd18_emi ra5 dio dram address output 5 dvdd18_emi ra6 dio dram address output 6 dvdd18_emi ra7 dio dram address output 7 dvdd18_emi ra8 dio dram address output 8 dvdd18_emi ra9 dio dram address output 9 dvdd18_emi ra10 dio dram address output 10 dvdd18_emi ra11 dio dram address output 11 dvdd18_emi ra12 dio dram address output 12 dvdd18_emi ra13 dio dram address output 13 dvdd18_emi ra14 dio dram address output 14 dvdd18_emi rdqm0 dio dram dqm 0 dvdd18_emi rdqm1 dio dram dqm 1 dvdd18_emi rdqm2 dio dram dqm 2 dvdd18_emi rdqm3 dio dram dqm 3 dvdd18_emi rdqs0 dio dram dqs 0 dvdd18_emi rdqs0_ dio dram dqs 0 # dvdd18_emi rdqs1 dio dram dqs 1 dvdd18_emi rdqs1_ dio dram dqs 1 # dvdd18_emi rdqs2 dio dram dqs 2 dvdd18_emi rdqs2_ dio dram dqs 2 # dvdd18_emi rdqs3 dio dram dqs 3 dvdd18_emi rdqs3_ dio dram dqs 3 # dvdd18_emi rdq0 dio dram data pin 0 dvdd18_emi rdq1 dio dram data pin 1 dvdd18_emi rdq2 dio dram data pin 2 dvdd18_emi rdq3 dio dram data pin 3 dvdd18_emi rdq4 dio dram data pin 4 dvdd18_emi rdq5 dio dram data pin 5 dvdd18_emi rdq6 dio dram data pin 6 dvdd18_emi rdq7 dio dram data pin 7 dvdd18_emi rdq8 dio dram data pin 8 dvdd18_emi rdq9 dio dram data pin 9 dvdd18_emi rdq10 dio dram data pin 10 dvdd18_emi rdq11 dio dram data pin 11 dvdd18_emi rdq12 dio dram data pin 12 dvdd18_emi rdq13 dio dram data pin 13 dvdd18_emi rdq14 dio dram data pin 14 dvdd18_emi rdq15 dio dram data pin 15 dvdd18_emi rdq16 dio dram data pin 16 dvdd18_emi rdq17 dio dram data pin 17 dvdd18_emi rdq18 dio dram data pin 18 dvdd18_emi rdq19 dio dram data pin 19 dvdd18_emi rdq20 dio dram data pin 20 dvdd18_emi rdq21 dio dram data pin 21 dvdd18_emi 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 25 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain rdq22 dio dram data pin 22 dvdd18_emi rdq23 dio dram data pin 23 dvdd18_emi rdq24 dio dram data pin 24 dvdd18_emi rdq25 dio dram data pin 25 dvdd18_emi rdq26 dio dram data pin 26 dvdd18_emi rdq27 dio dram data pin 27 dvdd18_emi rdq28 dio dram data pin 28 dvdd18_emi rdq29 dio dram data pin 29 dvdd18_emi rdq30 dio dram data pin 30 dvdd18_emi rdq31 dio dram data pin 31 dvdd18_emi rodt(/rba2) dio dram odt p in(/dram bank address output 2) dvdd18_emi rextdn dio dram rextdn p in dvdd18_emi cam cmpclk dio pixel clock from sensor dvdd18_nml4 cmmclk dio master clock to sensor dvdd18_nml4 cmrst dio reset control to sensor dvdd18_nml4 cmpdn dio power down to sensor dvdd18_nml4 cmflash dio camera flash control signal dvdd18_nml4 i2c0 scl0 dio i2c0 clock dvdd18_nml3 sda0 dio i2c0 data dvdd18_nml3 i2c1 scl1 dio i2c1 clock dvdd18_nml4 sda1 dio i2c1 data dvdd18_nml4 i2c2 scl2 dio i2c2 clock dvdd18_nml4 sda2 dio i2c2 data dvdd18_nml4 i2c3 scl3 dio i2c3 clock dvdd18_nml1 sda3 dio i2c3 data dvdd18_nml1 abb ul_q_n1 aio umts uplink for umtstx_qn dvdd18_md ul_q_p1 aio umts uplink for umtstx_qp dvdd18_md ul_i_p1 aio umts uplink for umtstx_ip dvdd18_md ul_i_n1 aio umts uplink for umtstx_in dvdd18_md vbias aio 3g pa analog control avdd28_dac apc1 aio automatic power control for 1 st modem avdd28_dac apc2 aio automatic power control for 2 nd modem avdd28_dac clk26m1 aio 26mhz clock input for ap & 1 st modem avdd18_md dl_q_p1 aio umts uplink for umtsrx_qp dvdd18_md dl_q_n1 aio umts uplink for umtsrx_qn dvdd18_md dl_i_n1 aio umts uplink for umtsrx_in dvdd18_md 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 26 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain dl_i_p1 aio umts uplink for umtsrx_ip dvdd18_md dl_q_p2 aio umts uplink for 2 nd umtsrx_qp or wcdma diversity path dvdd18_md dl_q_n2 aio umts uplink for 2 nd umtsrx_qn or wcdma diversity path dvdd18_md dl_i_n2 aio umts uplink for 2 nd umtsrx_in or wcdma diversity path dvdd18_md dl_i_p2 aio umts uplink for 2 nd umtsrx_ip or wcdma diversity path dvdd18_md clk26m2 aio 26mhz clock input for ap & 2 nd modem avdd18_md ul_q_n2 aio umts uplink for 2 nd umtstx_qn avdd18_md ul_q_p2 aio umts uplink for 2 nd umtstx_qp avdd18_md ul_i_p2 aio umts uplink for 2 nd umtstx_ip avdd18_md ul_i_n2 aio umts uplink for 2 nd umtstx_in avdd18_md refn aio negative reference port for internal circuit avdd18_ap refp aio positive reference port for internal circuit avdd18_ap aux_in0 aio auxadc external input channel 0 avdd18_ap aux_in1 aio auxadc external input channel 1 avdd18_ap aux_xp aio auxadc channel for touch screen tp_x+ avdd18_ap aux_yp aio auxadc channel for touch screen tp_y+ avdd18_ap aux_xm aio auxadc channel for touch screen tp_x - avdd18_ap aux_ym aio auxadc channel for touch screen tp_y - avdd18_ap mipi tdn3 aio dsi0 lane3 n dvdd18_mipitx tdp3 aio dsi0 lane3 p dvdd18_mipitx tdn2 aio dsi0 lane2 n dvdd18_mipitx tdp2 aio dsi0 lane2 p dvdd18_mipitx tcn aio dsi0 ck lane n dvdd18_mipitx tcp aio dsi0 ck lane p dvdd18_mipitx tdn1 aio dsi0 lane1 n dvdd18_mipitx tdp1 aio dsi0 lane1 p dvdd18_mipitx tdn0 aio dsi0 lane0 n dvdd18_mipitx tdp0 aio dsi0 lane0 p dvdd18_mipitx 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 27 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain vrt ao external resistor for dsi bias connect 1.5k ohm 1% resistor to ground. dvdd18_mipitx rdn3 aio csi0 lane3 n dvdd18_mipirx rdp3 aio csi0 lane3 p dvdd18_mipirx rdn2 aio csi0 lane2 n dvdd18_mipirx rdp2 aio csi0 lane2 p dvdd18_mipirx rcn aio csi0 ck lane n dvdd18_mipirx rcp aio csi0 ck lane p dvdd18_mipirx rdn1 aio csi0 lane1 n dvdd18_mipirx rdp1 aio csi0 lane1 p dvdd18_mipirx rdn0 aio csi0 lane0 n dvdd18_mipirx rdp0 aio csi0 lane0 p dvdd18_mipirx rdn1_a aio csi1 lane1 n/ pixel data [6] from sensor dvdd18_mipiio rdp1_a aio csi1 lane1 p /pixel data [7] from sensor dvdd18_mipiio rcn_a aio csi1 ck lane n /pixel data [8] from sensor dvdd18_mipiio rcp_a aio csi1 ck lane p /pixel data [9] from sensor dvdd18_mipiio rdn0_a aio csi1 lane0 n/ vref from sensor dvdd18_mipiio rdp0_a aio csi1 lane0 p/ href from sensor dvdd18_mipiio rdn1_b aio csi1 sub - cam lane1 n /pixel data [2] from sensor dvdd18_mipiio rdp1_b aio csi1 sub - cam lane1 p /pixel data [3] from sensor dvdd18_mipiio rcn_b aio csi1 sub - cam ck lane n /pixel data [4] from sensor dvdd18_mipiio rcp_b aio csi1 sub - cam ck lane p /pixel data [5] from sensor dvdd18_mipiio rdn0_b aio csi1 sub - cam lane0 n /pixel data [0] from sensor dvdd18_mipiio rdp0_b aio csi1 sub - cam lane0 p /pixel data [1] from sensor dvdd18_mipiio usb usb_dp_p0 aio usb port0 d+ differential data line avdd33_usb_p0 usb_dm_p0 aio usb port0 d - differential data line avdd33_usb_p0 chd_dp_p0 aio bc1.1 charger dp avdd33_usb_p0 chd_dm_p0 aio bc1.1 charger dm avdd33_usb_p0 usb_vrt ao usb output for bias current ; connect with 5.11k 1% ohm to gnd avdd18_usb_p0 usb_vbus ai power for connected device +3.3v avdd18_usb_p0 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 28 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain usb_dp_p1 aio usb port1 d+ differential data line avdd33_usb_p1 usb_dm_p1 aio usb port1 d - differential data line avdd33_usb_p1 iddig dio usb otg id pin dvdd18_nml1 mempll tp_mempll aio mempll differential output p for debug avdd18_mempll tn_mempll aio mempll differential output n for debug avdd18_mempll analog p ower dvdd18_pllgp p analog power input 1.8v for pll avdd18_ap p analog power input 1.8v for auxadc, tsense avdd18_md p analog power input 1.8v for bbtx, bbrx, 2gbbtx dvdd18_md p alternative analog power input 1.8v for bbtx, bbrx, 2gbbtx avdd28_dac p analog power input 2.8v for apc dvdd18_mipitx p analog power for mipi dsi dvdd18_mipirx p analog power for mipi csi0 dvdd18_mipiio p analog power for mipi csi1 & gpi avdd33_usb_p0 p analog power 3.3v for usb port 0 avdd33_usb_p1 p analog power 3.3v for usb port 1 avdd18_usb_p0 p analog power 1.8v for usb port 0 avdd18_usb_p1 p analog power 1.8v for usb port 1 avdd18_mempll p analog power for mempll digital p ower dvdd 18 _ nml1 p digital power input for nml1 - dvdd 28 _nml2 p digital power input for nml2 - dvdd 18 _nml3 p digital power input for nml3 - dvdd 18 _nml4 p digital power input for nml4 - dvdd 28 _bpi p digital power input for 2.8v bpi io - dvdd 28 _bsi p digital power input for 2.8v bsi io - dvdd 18 _bsi p digital power input for 1.8v bsi io - dvdd 18 _emi p digital power input for emi - dvdd 18 _mc0 p digital power input for msdc0 - dvdd 33 _mc1 p digital power input for msdc1 t ransmitter - 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 29 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin n ame type description power d omain dvdd 33 _mc2 p digital power input for msdc2 t ransmitter - dvdd 18 _mc 12 p digital power input for msdc 1/msdc2 r eceiver - dvdd_ gpu p digital power input for g raphic p rocessor - d vdd p digital power input for core - d vdd_dvfs p digital power input for processor - d vdd_sram p digital power input for processor memory - analog g round avss18_ap g avss18_md g dvss18_mipitx g dvss18_mipirx g dvss18_mipiio g avss33_usb_p0 g avss33_usb_p1 g avss18_mempll g digital g round gnd g - 2.2 electrical c haracteristic 2.2.1 absolute m aximum r atings table 2 - 4 : absolute maximum ratings for power supply symbol or p in n ame description min. max. unit dvdd18_pllgp analog power input 1.8v for pll 1.7 1.9 v avdd18_ap analog power input 1.8v for auxadc, tsense 1.7 1.9 v avdd18_md analog power input 1.8v for bbtx, bbrx, 2gbbtx 1.7 1.9 v dvdd18_md alternative analog power input 1.8v for bbtx, bbrx, 2gbbtx 1.7 1.9 v avdd28_dac analog power input 2.8v for apc 2.66 2.94 v dvdd18_mipitx analog power for mipi dsi 1.7 1.9 v dvdd18_mipirx analog power for mipi csi0 1.7 1.9 v dvdd18_mipiio analog power for mipi csi1 & gpi 1.7 1.9 v avdd33_usb_p0 analog power 3.3v for usb port 0 3.135 3.465 v avdd33_usb_p1 analog power 3.3v for usb port 1 3.135 3.465 v avdd18_usb_p0 analog power 1.8v for usb port 0 1.7 1.9 v avdd18_usb_p1 analog power 1.8v for usb port 1 1.7 1.9 v avdd18_mempll analog power for mempll 1.7 1.9 v dvdd 18 _n ml1 digital power input for n ml1 1.62 1.98 v 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 30 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol or p in n ame description min. max. unit dvdd 28 _n ml2 digital power input for n ml2 1 . 7 3. 6 v dvdd 18 _n ml3 digital power input for n ml3 1.62 1.98 v dvdd 18 _n ml4 digital power input for n ml4 1.62 1.98 v dvdd 28 _bpi digital power input for bpi 1 . 7 3. 6 v dvdd 28 _b s i digital power input for b s i 1 . 7 3. 6 v dvdd 18 _bsi digital power input for bsi 1.62 1.98 v dvdd 18 _mc0 digital power input for msdc0 1.62 1.98 v dvdd 18 _mc 12 digital power input for msdc 1/msdc2 1.62 1.98 v dvdd 33 _mc1 digital power input for msdc1 1 . 7 3. 6 v dvdd 33 _mc2 digital power input for msdc2 1 . 7 3. 6 v dvdd 18 _ emi digital power input for emi 1.08 1.98 v d vdd digital power input for core 0.95 1.15 v d vdd _gpu digital power input for gpu 0.95 1.26 v dv dd_dvfs digital power input for processor 0.77 1.26 v d vdd_sram digital power input for processor memory 0.95 1.26 v warning: stressing the device beyond the a bsolute m aximum r atings may cause permanent damage. these are stress ratings only. 2.2.2 recommended o perating c onditions table 2 - 5 : recommended operating conditions for power supply symbol or p in n ame description min. typ. max. unit dvdd18_pllgp analog power input 1.8v for pll 1.7 1.8 1.89 v avdd18_ap analog power input 1.8v for auxadc, tsense 1.71 1.8 1.89 v avdd18_md analog power input 1.8v for bbtx, bbrx, 2gbbtx 1.71 1.8 1.89 v dvdd18_md alternative analog power input 1.8v for bbtx, bbrx, 2gbbtx 1.71 1.8 1.89 v avdd28_dac analog power input 2.8v for apc 2.66 2.8 2.94 v dvdd18_mipitx analog power for mipi dsi 1.71 1.8 1.89 v dvdd18_mipirx analog power for mipi csi0 1.71 1.8 1.89 v dvdd18_mipiio analog power for mipi csi1 & gpi 1.71 1.8 1.89 v avdd33_usb_p0 analog power 3.3v for usb port 0 3.135 3.3 3.465 v avdd33_usb_p1 analog power 3.3v for usb port 1 3.135 3.3 3.465 v avdd18_usb_p0 analog power 1.8v for usb port 0 1.71 1.8 1.89 v avdd18_usb_p1 analog power 1.8v for usb port 1 1.71 1.8 1.89 v avdd18_mempll analog power for mempll 1.71 1.8 1.89 v dvdd 18 _n ml1 digital power input for n ml1 1.62 1.8 1.98 v dvdd 28 _n ml2 digital power input for n ml2 1.7 1.8 1.95 v 2.7 3.3 3.6 dvdd 18 _n ml3 digital power input for n ml3 1.62 1.8 1.98 v 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 31 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol or p in n ame description min. typ. max. unit dvdd 18 _n ml4 digital power input for n ml4 1.62 1.8 1.98 v dvdd 28 _bpi digital power input for bpi 1.7 1.8 1.95 v 2.7 3.3 3.6 dvdd 28 _b s i digital power input for b s i 1.7 1.8 1.95 v 2.7 3.3 3.6 dvdd 18 _bsi digital power input for bsi 1.62 1.8 1.98 v dvdd 18 _mc0 digital power input for msdc0 1.62 1.8 1.98 v dvdd 18 _mc 12 digital power input for msdc 1/msdc2 1.62 1.8 1.98 v dvdd 33 _mc1 digital power input for msdc1 1.7 1.8 1.95 v 2.7 3.3 3.6 dvdd 33 _mc2 digital power input for msdc2 1.7 1.8 1.95 v 2.7 3.3 3.6 dvdd 18 _ emi digital power input for emi (lpddr2) 1. 08 1. 2 1. 32 v digital power input for emi (uvddr3) 1.125 1.25 1.375 digital power input for emi (lvddr3) 1.215 1.35 1.485 digital power input for emi (ddr3) 1.35 1.5 1.65 d vdd digital power input for core 1.00 1.05 1.10 v d vdd _gpu digital power input for gpu 1.00 1.05 1.20 v dv dd_dvfs digital power input for processor 0.81 1.15 1.20 v d vdd_sram digital power input for processor memory 1.00 1.15 1.20 v 2.2.3 storage c ondition 1. shelf life in sealed bag: 12 months at < 40 c and < 90% relative humidity (rh). 2. after bag opened, devices subjected to infrared reflow, vapor - phase reflow, or equivalent processing must be: ? mounted within 168 hours at factory conditions of 30 c/60% rh, or ? stored at 20% rh. 3. devices require baking before mounting, if: ? 192 hours at 40 c +5 c/ - 0 c and < 5% rh for low temperature device containers, or ? 24 hours at 125 c +5 c/ - 0 c for high temperature device containers. 2.2.4 ac e lectrical c haracteristics and t iming d iagram 2.2.4.1 external memory interface for lpddr 2 the e xternal memory interface, shown in figure 2 - 4, figure 2 - 5 and figure 2 - 6, is used to connect lpddr2 device for mt65 8 9 . it includes pins ed_clk, ed_clk_b, ecke, ecs#, eba[2:0], edqs[3:0], edqs#[3:0], ea[9:0] and ed[31:0]. table 2 - 5 summarizes the symbol definition and the related timing specification s. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 32 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. figure 2 - 2 : basic timing parameter for lpddr2 commands figure 2 - 3 : basic timing parameter for lpddr2 write 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < e d _ c l k e d _ c l k _ b e c s _ b e c a 0 - 9 [ c m d ] e d _ c l k e d _ c l k _ b e c a 0 - 9 [ c m d ] e d q s / e d q s _ b e d q s e d q s / e d q s _ b e d q s free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 33 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. figure 2 - 4 : basic timing parameter for lpddr2 read table 2 - 6 : lpddr2 ac timing parameter table of external memory interfaces symbol description min. typ. max. unit tck clock c ycle t ime 3.75 8 ns tdqsck dqs output access time from ck/ck 2.5 5.5 ns tch clock high level width 0.45 0.55 tck tcl clock low level width 0.45 0.55 tck thp clock half period 0.45 0.55 tck tds dq & dm input setup time 0.43 ns tdh dq & dm input hold time 0.43 ns tdqss write command to 1 st dqs latching transition 0.75 1.25 tck tdss dqs falling edge to ck setup time 0.2 tck tdsh dqs falling edge hold time from ck 0.2 tck tis address & control input setup time 0.46 ns tih address & control input hold time 0.46 ns tlz(dqs) dqs low - impedance time from ck/ck tdqsck (m in. ) C 300 ns thz(dqs) dqs high - impedance time from ck/ck tdqsck (m ax. ) C 100 ns tlz(dq) dq low - impedance time from ck/ck tdqsck (m in. ) C (1.4tqhs (m ax. ) ) ns thz(dq) dq high - impedance time from ck/ck tdqsck (m ax. ) + ns 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 34 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol description min. typ. max. unit (1.4tdqsq (m ax. ) ) tdqsq dqs - dq skew 0.34 ns tqhp data half period m in. (tqsh, tqsl) tck tqhs data hold skew factor 0.4 ns tqh dq/dqs output hold time from dqs tqhp C ns tdqsh dqs input high - level width 0.4 tck tdqsl dqs input low - level width 0.4 tck tqsh dqs output high pulse width tch C tck tqsl dqs output low pulse width tcl C tck tmrw mode register write command period 5 tck tmrr mode register read command period 2 tck trpre read preamble 0.9 1.1 tck trpst read postamble tcl C tck tras active to precharge command period 3 tck trc active to active command period 6 tck trfc auto refresh to active/auto refresh command period 56 tck trcd active to read or write delay 3 tck trp precharge command period 3 tck trrd active bank a to active bank b delay 2 tck twr write recovery time 3 tck twtr internal write to read command time 2 tck txsr self refresh exit to the next valid command 40 tck txp exit power - down to the next valid command delay 2 tck tcke cke min. pulse width (high & low pulse width) 2 tck 2.3 system configuration 2.3.1 m ode s elec tion table 2 - 7 : mode s election of c hip (pmu 6320 pin) pin n ame description kp_col0 0: trigger usb download without battery 1: na kp_row0 0: trigger usb download without battery 1: na 2.3.1 constant t ie p ins table 2 - 8 : constant tied pins of mt 6589 pin name description 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 35 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. pin name description testmode test mode (tie to gnd) fsource_p efuse burning (tie to gnd) 2.4 power - on sequence the power - on/off sequence with xtal is shown in the follow ing figure: figure 2 - 5 : power on/off sequence with xtal note that the above figure onl y shows one power - on/off condition with xtal. the e xternal pmic mt6320 for application processor mt 6589 handles the power on and off of the handset. the following three different method s switch on the handset ( w hen vbat 3.2v): 1. pulling pwrkey low ( the u ser presses pwrkey . ) 2. pulling bbwakeup high 3. valid charger plug - in pulling pwrkey low is a normal way to turn on the handset , which turn s on regulators as long as the pwrkey is kept low. mt632 0 output s reset signal resetb to mt 6589 sysrstb input. after sysr stb is de - asserted, the microprocessor starts and pulls bbwakeup high. after that pwrkey can be released , p ulling bbwakeup high will also turn on the handset. this is the case when the alarm in the rtc expires. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < v b a t d d l o u v l o p w r k e y b b w a k e u p v c o r e v i o 1 8 v a / v a 2 8 / v i o 2 8 v a s t v p r o c v s r a m v m v u s b / v e m c 3 v 3 / v e m c 1 v 8 v m c / v m c h v t c x o r e s e t b d e - b o u n c e t i m e = 5 0 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 0 m s 2 m s 8 m s 2 m s free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 36 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. besides, applying a valid external supply on chrin will also turn on the handset. however, i f the battery is in the uv state (vbat < 3.2v), the handset can no t be turned on in any way. the uvlo function in mt632 0 prevents system startup when initial voltage of the main battery is below the 3.2v thre shold. when the battery voltage is bigger than 3.2v, the uvlo comparator switches and threshold are reduced to 2.9v , which allows the handset to start smoothly unless the battery decays to 2.9v and below. once mt632 0 enters the uvlo state, it draws very l ow quiescent current. the vrtc ldo will still be active until the ddlo disables it. figure 2 - 6 : power on/off sequence without xtal the figure above shows the power - on/off sequence without xtal. vtcxo is always turned on when vbat is above the ddlo threshold. 2.5 analog b aseband to communicate with analog blocks, a common control interface for all analog blocks is implemented. in addition, there are some dedicated interfaces for data transfer. the common control interface translates the apb bus write and read cycle for specific addresses related to analog front - end control. during the writing or reading of any of these control registers, there is a latency associated with the transfer of data to or from the analog front - end. dedicated data interface of each analog block is implemented in the corresponding digital block. an a nalog b lock includes the following analog function s for the complete gsm/gprs/wcdma base - band signal processing: 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < v b a t d d l o u v l o p w r k e y b b w a k e u p v c o r e v i o 1 8 v a / v a 2 8 / v i o 2 8 v a s t v p r o c v s r a m v m v u s b / v e m c 3 v 3 / v e m c 1 v 8 v m c / v m c h v t c x o r e s e t b d e - b o u n c e t i m e = 5 0 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 m s 2 2 m s 2 m s 8 m s 2 m s free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 37 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. ? base - band r x : for i/q channels base - band a/d conversion ? base - band t x : for i/q channels base - band d/a conversion and smoothing filtering . ? 2g b ase - band tx: for the 2 nd i/q channels base - band d/a conversion and smoothing filtering. ? rf c ontrol: two dac s for automatic power control (apc) are included . their outputs are provided to the external rf power amplifier respectively, according to the system dual - talk configuration . on e more dac for voltage bias control (vbias) is included for wcdma system , and t he output is provided to the external rf power amplifier. ? auxiliary adc: provid es an adc for the battery and other auxiliary analog function s monitoring . ? clock g eneration: inclu des two clock - squarer s for shaping the dual - talk system clock and 14 plls provid ing clock signals to base - band trx, dsp, mcuusb , msdc, lvds and hdmi units. the a nalog b locks include the following analog function s for complete gsm/gprs/wcdma base - band sign al processing: ? bbrx ? bbtx ? 2gbbtx ? apc - dac ? vbias - dac ? auxadc ? pha se l ocked l oop 2.5.1 bbrx 2.5.1.1 block descriptions the receiver (r x ) performs baseband i/q channels downlink analog - to - digital conversion: 1. analog input multiplexer: for each channel, a 2 - input multiplexer is included. 2. a/d converter: 4 high performance sigma - delta adcs perform i/q digitization for further digital signal processing. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 38 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. figure 2 - 7 : block diagram of bbrx - adc 2.5.1.2 function specifications see the table below for t he function specifications of the base - band downlink receiver. table 2 - 9 : baseband d ownlink s pecifications symbol parameter min. typ. max. unit vin differential analog input voltage (peak - to - peak) 2.4 v icm common mode input current magnitude 1 ua vcm common mode input voltage 0.65 0.7 0.75 v fc input clock frequency ? clock rate (dc mode) ? clock rate (sc mode & gsm mode) 416 208 mhz mhz input clock duty cycle 49.5 50 50.5 % input clock period jitter, dc mode 0.14 % (rms) input clock period jitter, sc mode & gsm mode 0.61 % (rms) rin differential input resistance ? dc mode ? sc mode & gsm mode 5.6 11.2 8 16 10.4 20.8 k k fs output sampling rate 416/208 msps vos differential input referred offset 10 mv sin signal to in - band noise ? dc mode, 2.4vpp (5.2mhz ) sinewave, 400khz ~ 4.6mhz band 72 75 db 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < d l _ i _ p 1 d l _ i _ n 1 v c m 1 v c m 1 m u x m o d u l a t o r e n c o d e r 8 t h e r m o m e t e r ( f s ) d o u t _ i 1 [ 3 : 0 ] 2 ' s c o m p l e m e n t ( f s ) d l _ q _ p 1 d l _ q _ n 1 v c m 1 v c m 1 m u x m o d u l a t o r e n c o d e r 8 d o u t _ q 1 [ 3 : 0 ] c k o u t _ 4 1 6 m _ i q 1 i n t _ s e l _ v i n _ i q 1 d l _ i _ p 2 d l _ i _ n 2 v c m 2 v c m 2 m u x m o d u l a t o r e n c o d e r 8 d o u t _ i 2 [ 3 : 0 ] d l _ q _ p 2 d l _ q _ n 2 v c m 2 v c m 2 m u x m o d u l a t o r e n c o d e r 8 d o u t _ q 2 [ 3 : 0 ] c k o u t _ 4 1 6 m _ i q 2 i n t _ s e l _ v i n _ i q 2 m a i n p a t h d i v e r s i t y p a t h ( o r 2 n d m o d e m ) free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 39 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol parameter min. typ. max. unit ? sc mode, 2.4vpp (2.7mhz ) sinewave, 1khz ~ 2.1mhz band ? gsm mode: 2.4vpp(570khz) sinewave, 70khz ~ 270khz band 72 84 75 87 db db dvdd18 digital power supply 1.7 1.8 1.9 v avdd18 analog power supply 1.7 1.8 1.9 v t operating temperature ? ? power - up ? power - down 3 1 ma ua 2.5.2 bbtx 2.5.2.1 block descriptions bbtx includes two channel dacs with the 1 st order low pass filter. the dacs are pmos current - steering topology with nmos constant sinking current and the active rc filter performs current to voltage buffer. the bitwidth of dacs is 10 - bit which is encoded into 7 bits of thermometer code and 7 binary code by mixedsys hardware. the encoded bits are timing synchronized by d - type flip - flop which is toggled by the analog local clock. the md - pll deliver s 832mhz diff erential clock to bbtx. a clock divider translates the 832mhz to 416mhz for dacs and afifo inside mixedsys. the io power, dvdd18_md is regula t ed to a voltage around 1.55v to supply analog component. t he required bias currents are generated by bbrx. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 40 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.5.2.2 function specifications table 2 - 10 : baseband u plink t ransmitter s pecifications symbol parameter min . typ . max . unit v ocm dc output common mode voltage 0.6 1 5 0.65 0. 68 5 v i k hf l eakage current @ supply, irms @ 416*2 = 832 mhz 3.5 ua v fs dac output swing 2 1 00 mv n dac r esolution 10.0 bit f s sampling clock 416 mhz i mis 1 - sgma dac unit cell mismatch 1 % g mis 3 - sigma i/q g ain m ismatch - 0.2 0.2 db v os_t 3 - sigma o utput differential dc offset over temp. 4 mv v os 3 - sigma o utput differential dc offset 10 mv f 3db 3db corner freq. 20 25 30 mhz s lpf lpf selectivity @832mhz 28 db n oob output n oise level @45mhz 15.1 30.1. nvrms/sqrt(hz) cn signal to noise ratio @45mhz - 146 - 140 dbc/hz im3 in - band two - tone test swing v1=v2=290/sqrt(2) mv - 60 - 56 dbc t operating t emperature - 20 80 c current consumption ? power - up ? power - d own 4 . 1 1 0 ma u a 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 41 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.5.3 2gbbtx 2.5.3.1 block descriptions the 2g transmitter ( 2g t x ) performs 2g baseband i/q channels up - link digital - to - analog conversion for dual - talk application . each channel includes: 1. 11 - b it d/a c onverter: c onverts digital modulated signals to analog domain. the input to the dac is sampled at 26 mhz rate with the 11 - bit resolution. 2. smoothin g f ilter: the low - pass filter performs smoothing function for dac output signals with a 1.8mhz 2 nd - order butterworth frequency response. figure 2 - 8 : block diagram of 2gbbtx 2.5.3.2 function specifications see the table below for t he function specifications of the 2g base - band uplink transmitter. table 2 - 11 : baseband u plink t ransmitter s pecifications symbol parameter min . typ . max . unit n resolution 11 bit fs sampling r ate 26 msps sinad signal to noise and distortion ratio (in - band) 80 db thd total h armonic d istortion - 60 db output s wing ( f ull swing) 0.9 1.0 1.1 vppd vocm output cm v oltage 1. 0 5 1. 1 1. 15 v output c apacitance (single - ended) 20 pf output r esistance (differential) 1.5 k dnl differential n onlinearity - 0.5 +0.5 lsb inl integral n onlinearity - 1.0 +1.0 lsb 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < d a c d a c l p f l p f u l i p u l i n u l q p u l q n u l _ a n a l o g _ c k u l _ i _ d a t a [ 1 0 : 0 ] u l _ q _ d a t a [ 1 0 : 0 ] r g _ u l _ a n a l o g _ p w d b r g _ u l _ l p f _ v c m [ 1 : 0 ] r g _ u l _ l p f _ b i a s a d j [ 1 : 0 ] r g _ u l _ l p f _ f c a d j [ 7 : 0 ] l p f b w c a l b i a s g e n free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 42 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol parameter min . typ . max . unit oe offset e rror (after calibration) +/ - 1 lsb fcut filter - 3db cutoff frequency (calibrated) 1.8 mhz i/q g ain m ismatch +/ - 0. 2 db dvdd digital p ower s upply 0.95 1. 05 1. 15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current consumption ? power - up ? power - d own 3.6 1 0 ma u a 2.5.4 apc - dac 2.5.4.1 block descriptions see the figure below. a p c - dac is designed to produce a single - ended output signal at a p c pin. figure 2 - 9 : block diagram of apc - dac 2.5.4.2 function specifications see the table below for t he function specifications of the apc - dac . table 2 - 12 : apc - dac s pecifications symbol parameter min . typ . max . unit n resolution 10 bit f s clock rate 1.0833 2.1666 ms/s sndr signal - to - noise - and - distortion ratio (10khz sine wave with 1.0v swing) 50 db t s settling time (99% full - swing settling) 5 us v o,max maximum output avdd ? 0.2 v c l output loading capacitance 1 , 000 2 , 200 pf dnl differential nonlinearity (code 30 ~ 970) ? 1.0 lsb inl integral nonlinearity (code 30 ~ 970) ? 2.0 lsb dvdd digital power supply 0.9 1.0 1.1 v avdd analog power supply 2.6 2.8 3.0 v 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < r e f e r e n c e b u f f e r & b i a s g e n . r - s t r i n g d a c c o r e 1 0 - b i t d f f a p c - d a c a p c _ e n o u t p u t b u f f e r p a d _ a p c a p c _ b u s [ 9 : 0 ] a p c _ r s t b r g _ a p c _ t g s e l a p c _ t g v b g ( f r o m b a n d g a p ) r g _ a p c b u f _ t r i m [ 3 : 0 ] p a free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 43 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol parameter min . typ . max . unit t operating temperature ? ? on current consumption (power - on state) 300 ua i off current consumption (power - down state) 1 ua 2.5.5 vbias - dac 2.5.5.1 block descriptions figure 2 - 10 : block diagram of vbias - dac 2.5.5.2 function specifications the functional specifications of the vbias - dac are listed in the following table. table 2 - 13 : vbias - dac s pecifications symbol parameter min . typ . max . unit n resolution 10 bit f s clock rate 1.0833 2.1666 ms/s sndr signal - to - noise - and - distortion ratio (10khz sine wave with 1.0v swing) 50 db t s settling time (99% full - swing settling) 5 us v o,max maximum output avdd ? 0.2 v c l output loading capacitance 1000 pf dnl differential nonlinearity (code 20 ~ 970) ? 1.0 lsb inl integral nonlinearity (code 20 ~ 970) ? 2.0 lsb dvdd digital power supply 0.9 1.0 1.1 v avdd analog power supply 2.6 2.8 3.0 v t operating temperature ? 20 85 ? c i on current consumption (power - on state) 300 ua i off current consumption (power - down state) 1 ua 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < r e f e r e n c e b u f f e r & b i a s g e n . r - s t r i n g d a c c o r e 1 0 - b i t d f f v b i a s - d a c v b i a s _ e n o u t p u t b u f f e r p a d _ v b i a s v b i a s _ b u s [ 9 : 0 ] v b i a s _ r s t b r g _ v b i a s _ t g s e l v b i a s _ t g v b g ( f r o m b a n d g a p ) r g _ v b i a s b u f _ t r i m [ 3 : 0 ] p a free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 44 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.5.6 auxadc 2.5.6.1 block descriptions auxiliary adc measur es adc and is the resistive touch panel controller. the auxiliary adc includes the following functional blocks: 1. analog m ultiplexer: s elects signal from one of the auxiliary input channels. there are 16 input channels of a ux adc. some are for internal voltage measuring and some for external voltage measuring. enviro n mental message s to be monitored, e.g. temperature, should be transferred to the voltage domain. 2. 12 - bit a/d c onverter: c onverts the multiplexed input signal to 12 - bit digital data. the t ouch s creen controller drive s the external touch panel via pads xp, xm, yp and ym , and a ux adc as a voltage meter , obtain s the x/y - position of the touched point on the external touch screen. the t ouch s creen i nter face contains 3 main blocks , which are touch screen pads control logic, adc interface logic and interrupt generation logic. the t ouch s creen i nterface supports 2 conversion modes , separate x/y position conversion mode and auto (sequential) x/y position con version mode. see table 2 - 14 : definitions of auxadc c hannel s f or brief descriptions of auxadc input channels. figure 2 - 11 : block diagram of auxadc table 2 - 14 : definitions of auxadc c hannel s a ux adc c hannel id description channel 0 external use (aux_in0) channel 1 external use (aux_in1) channel 2 optional e xternal use (aux_in2) 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < v r t v r b p a d _ a u x i n < 4 : 0 > 5 m u x a d c a v d d a v d d p a d _ x p p a d _ y p p a d _ y m p a d _ x m s / h p e n i n t e r r u p t d i g i t a l c o n t r o l l e r d o < 1 1 : 0 > free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 45 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. a ux adc c hannel id description channel 3 optional e xternal use (aux_in3) channel 4 optional e xternal use (aux_in4) channel 5 na channel 6 na channel 7 na channel 8 na channel 9 na channel 1 0 na channel 11 na channel 12 xm (t ouch p anel ) channel 13 xp ( t ouch p anel) channel 14 yp ( t ouch p anel) channel 15 ym ( t ouch p anel) 2.5.6.2 function specifications see the table below for t he function specifications of auxiliary adc. table 2 - 15 : auxadc specifications symbol parameter min . typ . max . unit n resolution 12 bit fc clock r ate 4 mhz fs sampling r ate @ n - bit 4/(n+4) msps input s wing 0 avdd v cin input c apacitance unselected c hannel selected c hannel 50 4 ff pf rin input r esistance unselected c hannel 400 m clock l atency n+4 1/fc dnl differential n onlinearity +1.0/ - 1.0 lsb inl integral n onlinearity +1.0/ - 1.0 lsb oe offset e rror +/ - 5 mv fse full s wing e rror +/ - 5 mv sinad signal to n oise and d istortion r atio (10 k hz f ull s wing i nput & 1.0833mhz c lock r ate) 62 68 db dvdd digital p ower s upply 1.0 1.1 1.2 v avdd analog p ower s upply 1.75 1.8 1.85 v t operating t emperature - 20 80 c current consumption ? power - up ? power - d own 250 1 ua u a ztp support s touch panel impedance 200 2k 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 46 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.5.7 clock squarer 2.5.7.1 block descriptions for most vcxo, the output clock waveform is sinusoidal with too small amplitude (about several hundred mv) to make mt 6589 digital circuits function well. clock squarer is designed to convert such a small signal to a rail - to - rail clock signal with excellent duty - cycle. 2.5.7.2 function specifications see the table below for t he function specifications of clock squarer. table 2 - 16 : clock squarer 1 & 2 s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 13 26 mhz fout output c lock f requency 13 26 mhz vin input s ignal a mplitude 350 500 1 , 000 mvpp dcycin input s ignal d uty c ycle 50 % dcycout output s ignal d uty c ycle dcycin - 5 dcycin+5 % tr rise t ime on p in clksqout 5 ns/pf tf fall t ime on p in clksqout 5 ns/pf dvdd digital p ower s upply 1.0 1.1 1.2 v avdd analog power supply 1.7 1.8 1.9 v t operating t emperature - 20 80 current c onsumption 5 00 ua 2.5.8 phase locked loop 2.5.8.1 block descriptions there are total 14 plls in pll macro, providing several clocks for cpu, bus, m odem, a nalog modem, msdc, lvds, hdmi and image - sensor. armpll provides around 1 .2 ghz clock for arm cortex - a15. mainpll provides around 806mhz clock for bus and most of the functi on modules. mmpll provides around 286mhz clock for venc and mfg. isppll is the clock source of image sense processing, which ranges from 104 to 208mhz for supporting various image sensor s . univpll provides 48mhz for usbphy. msdcpll provides around 208mhz a s the clock source of msdc module. tvdpll provides 27/54/148.5mhz clock for the tv encoder and hdmi bri d ge. lvdspll provides 20 ~ 75mhz clock for lvds bridge and dpi interface. mdpll1 and mdpll2 are the main clock source of dual - talk modem, providing a fix ed 416mhz from different clock squarer s for further clock division. wpll is a fractional pll which multipl ies clock 26mhz to 245.76mhz for hspa. whpll provides a fixed 250.25mhz for 3g hspa. mcupll1 and mcupll2 provide around 481mhz for arm cortex - r4, fd21 6 and bus. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 47 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. figure 2 - 12 : block diagram of pll 2.5.8.2 function specifications see the table below for t he function specifications of pll. table 2 - 17 : armpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 7 54 1 ,508 mhz settling t ime 20 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 30 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < c l k s q c l k s q 1 b i a s / l d o 2 6 m h z p a d _ c l k 2 6 m _ 1 a d _ m e m _ 2 6 m _ c k a d _ m i p i _ 2 6 m _ c k a d _ m d s y s 1 _ 2 6 m _ c k m d p l l 1 m d _ p l l ( 8 3 2 m h z ) a d _ m d p l l 1 _ 4 1 6 m _ c k / 2 m t 6 5 8 9 m d p l l 1 r g _ c l k s q 1 _ e n t o b b t r x n s _ m d 8 3 2 m _ c k p n s _ m d 8 3 2 m _ c k n q s _ m d 8 3 2 m _ v s s w p l l a d _ w p l l _ 2 4 5 p 7 6 m _ c k m c u p l l 1 a d _ m c u 1 _ h 4 8 1 m _ c k w h p l l a d _ w h p l l _ 2 5 0 p 2 5 m _ c k s d m _ p l l ( 1 9 6 6 . 0 8 m h z ) l c _ i n t _ p l l ( 1 0 0 1 m h z ) s d m _ p l l ( h o p 1 9 2 4 m h z ) / m / m e x t e r n a l o f p l l i n t e r n a l o f p l l / m a n a l o g s p e c i a l d i v i d e r / 4 / 2 / 4 / 4 u n i v p l l / 2 6 / 2 / 3 / 5 / 7 a d _ u n i v _ 6 2 4 m _ c k a d _ u n i v _ 4 1 6 m _ c k a d _ u n i v _ 2 4 9 p 6 m _ c k a d _ u n i v _ 1 7 8 p 3 m _ c k a d _ u n i v _ 4 8 m _ c k a d _ u s b _ 4 8 m _ c k l c _ i n t _ p l l ( 1 2 4 8 m h z ) m a i n p l l a r m p l l a d _ a r m _ h 1 3 0 0 m _ c k a d _ m a i n _ h 8 0 6 m _ c k a d _ m a i n _ h 3 2 2 p 4 m _ c k a d _ m a i n _ h 2 3 0 p 3 m _ c k a d _ m a i n _ h 5 3 7 p 3 m _ c k s d m _ p l l ( h o p 1 6 1 2 m h z ) s d m _ p l l ( h o p 1 3 0 0 m h z ) l c _ i n t _ p l l ( 1 4 3 0 m h z ) m m p l l t v d p l l l v d s p l l m s d c p l l s d m _ p l l ( h o p 1 6 6 4 m h z ) / 4 a d _ m s d c _ h 2 0 8 m _ c k / 2 / 4 a d _ l v d s _ h 1 8 0 m _ c k / 2 s d m _ p l l ( h o p 1 4 4 0 m h z ) / 4 a d _ t v d _ h 1 4 8 p 5 m _ c k / 2 / 4 / 8 / 1 6 s d m _ p l l ( h o p 2 3 7 6 m h z ) / 4 m o d e m t e s t c k t + - b i a s / l d o m t 6 5 8 9 p l l g p 1 2 5 m h z ~ 3 1 2 . 5 m h z a d _ i s p _ 2 0 8 m _ c k l c _ i n t _ p l l ( 1 6 6 4 m h z ) i s p p l l / 4 b a c k - u p f o r s p e c i a l s e n s o r / 2 / 3 / 5 / 7 / 1 c l k s q c l k s q 2 b i a s / l d o 2 6 m h z p a d _ c l k 2 6 m _ 2 m d p l l 2 m d _ p l l ( 8 3 2 m h z ) a d _ m d p l l 2 _ 4 1 6 m _ c k / 2 m t 6 5 8 9 m d p l l 2 r g _ c l k s q 2 _ e n t o b b t r x n s _ m d 8 3 2 m _ c k p n s _ m d 8 3 2 m _ c k n q s _ m d 8 3 2 m _ v s s m c u p l l 2 a d _ m c u 2 _ h 4 8 1 m _ c k s d m _ p l l ( h o p 1 9 2 4 m h z ) / 4 / 2 m o d e m / 2 / 3 / 5 / 7 a d _ m m _ d i v 2 _ c k a d _ m m _ d i v 3 _ c k a d _ m m _ d i v 5 _ c k a d _ m m _ d i v 7 _ c k a d _ m d s y s 2 _ 2 6 m _ c k a d _ s y s _ 2 6 m _ c k / 2 d a _ c p u _ c k _ m o n / 1 free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 48 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol parameter min . typ . max . unit avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 1 .2 ma power - d own c urrent c onsumption 1 ua table 2 - 18 : mainpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 500 806 884 mhz settling t ime 20 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 19 : mmpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 286 338 mhz settling t ime 20 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 20 : isppll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 104 208 mhz settling t ime 20 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 49 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol parameter min . typ . max . unit current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 21 : univpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency n/a 624 n/a mhz settling t ime 20 us output c lock d uty c ycle 45 50 55 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1.05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 22 : msdcpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 208 mhz settling t ime 20 us output c lock d uty c ycle 45 50 55 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 23 : tvdpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 148.5 mhz settling t ime 20 us output c lock d uty c ycle 45 50 55 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 50 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. table 2 - 24 : lvdspll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 75 mhz settling t ime 20 us output c lock d uty c ycle 45 50 55 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 25 : mdpll1 & mdpll2 specifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency n/a 416 n/a mhz settling t ime 100 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 30 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 2 .5 ma power - d own c urrent c onsumption 1 ua table 2 - 26 : wpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency n/a 245.76 n/a mhz settling t ime 20 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1. 05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 27 : whpll s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 51 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. symbol parameter min . typ . max . unit fout output c lock f requency n/a 250.25 n/a mhz settling t ime 20 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1.05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 0.8 ma power - d own c urrent c onsumption 1 ua table 2 - 28 : mcupll1 & mcupll2 s pecifications symbol parameter min . typ . max . unit fin input c lock f requency 26 mhz fout output c lock f requency 481 mhz settling t ime 20 us output c lock d uty c ycle 47 50 53 % output c lock j itter ( p eriod j itter) 60 ps dvdd digital p ower s upply 0.95 1.05 1.15 v avdd analog p ower s upply 1.7 1.8 1.9 v t operating t emperature - 20 80 c current c onsumption 2 ma power - d own c urrent c onsumption 1 ua 2.5.9 temperature sensor 2.5.9.1 block descriptions in order to monitor the temperature of cpu s , several temperature sensor s are provided . the temperature sensor is made of substrate bjt in the cmos process. the voltage output of temperature sensor is measured by auxadc. 2.5.9.2 function specifications see the table below for t he function specifications of t emperature s ensor . table 2 - 29 : temperature s ensor s pecifications symbol parameter min . typ . max . unit resolution 0.1 5 c temperature r ange 0 85 c accuracy - 5 5 c active c urrent 300 ua quiescent c urrent 3 ua 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 52 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.6 package information 2.6.1 package outlines figure 2 - 1 3 : outlines and dimensions of fccsp 1 1 . 8 mm*1 1 . 8 mm, 5 15 - ball, 0.4mm pitch package 2.6.2 thermal operating specification s table 2 - 30 : thermal operating specification s symbol description value unit notes maximum operating junction temperature 125 c package thermal resistances in nature convection 29.55 c/watt 2.6.3 lead - free packaging mt 6589 is provided in a lead - free package and meet s rohs requirements. 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < free datasheet http:/// o r j l q l g f k x q s l q j p l d r # q e e v z f r p w l p h l s g r f w l w o h 0 7 b 7 h f k q l f d o b % u l h i b y g r f [ f r p s d q \ % l u g b : & ; mt 6589 hspa + smartphone application processor technical brief confidential a mediatek confidential ? 2012 mediatek inc. page 53 of 53 this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. 2.7 ordering i nformation 2.7.1 top m arking d efinition figure 2 - 14 : top mark of mt 6589 0 ( ' , $ 7 ( . & 2 1 ) , ' ( 1 7 , $ / ) 2 5 f k x q s l q j p l d r # q e e v z f r p 8 6 ( 2 1 / < m t 6 5 8 9 % k d d d d - # # # # l l l l l m t x x x x x x p a r t n o . % : w : w c d m a t : t d - s c d m a e : e d g e d d d d : d a t e c o d e # # # # : s u b c o n t r a c t o r c o d e l l l l l : d i e l o t n o . s : s p e c i a l c o d e free datasheet http:/// |
Price & Availability of MTK6589
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |