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2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 1 of 31 product description the kxt j2 is a tri - axis +/ - 2g, +/ - 4g or +/ - 8g silicon micromachined accelerometer. the sense element is fabricated using kionixs proprietary plasma micromachining process technology. acceleration sensing is based on the principle of a differential capacitance arising from acceleration - induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stress. the sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. a separate asic device packaged with the sense eleme nt provides signal conditioning and digital communications . the accelerometer is delivered in a 2 x 2 x 0.9 mm lga plastic package operating from a 1.8 C 3.6v dc supply. voltage regulators are used to maintain constant internal operating voltages over th e range of input supply voltages. this results in stable operating characteristics over the range of input supply voltages and virtually undetectable ratiometric error. the i 2 c digital protocol is used to communicate with the chip to configure the part a nd monitor outputs .
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 2 of 31 functional diagram
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 3 of 31 product specifications table 1 . mechanical (specifications are for operation at 2.6v and t = 25c unless stated otherwise) parameters units min typical max operating temperature range o c - 40 - 85 zero - g offset mg - 25 200 zero - g offset variation from rt over temp. mg/ o c 0.2 sensitivity (14 - bit) 1,2 gsel1=1, gsel0=1 ( 8g) counts/g 1024 sensitivity (12 - bit) 1 gsel1=0, gsel0=0 ( 2g) counts/g 1024 gsel1=0, gsel0=1 ( 4g) 512 gsel1=1, gsel0=0 ( 8g) 256 sensitivity (8 - bit) 1 gsel1=0, gsel0=0 ( 2g) counts/g 64 gsel1=0, gsel0=1 ( 4g) 32 gsel1=1, gsel0=0 ( 8g) 16 sensitivity variation from rt over temp. %/ o c 0.01 self test output change on activation g 1.25 (x) 0.8 (y) 0.6 (z) mechanical resonance ( - 3db) 3 hz 3500 (xy) 1800 (z) non - linearity % of fs 0.6 cross axis sensitivity % 2 notes: 1. resolution and acceleration ranges are user selectable via i 2 c. 2. 14 - bit resolution is only available for registers 0x06h C 0x0bh in the 8g full power mode 3. resonance as defined by the dampened mechanical sensor.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 4 of 31 table 2 . electrical (specifications are for operation at 2.6v and t = 25c unless stated otherwise) parameters units min typical max supply voltage (v dd ) operating v 1.71 2.6 3.6 i/o pads supply voltage (v io ) v 1.7 v dd current consumption full power mode (res = 1) ? a 135 low power mode 1 (res = 0) 10 disabled 0.9 output low voltage (v io < 2v) 2 v - - 0.2 * v io output low voltage (v io > 2v) 2 v - - 0.4 output high voltage v 0.8 * v io - - input low voltage v - - 0.2 * v io input high voltage v 0.8 * v io - - input pull - down current ? a 0 start up time 3 ms ~1/odr power up time 4 ms 10 i 2 c communication rate mhz 3.4 output data rate (odr) 5 hz 0.781 50 1600 bandwidth ( - 3db) 6 res = 0 hz 800 res = 1 hz odr/2 notes: 1. current varies with output data rate (odr) see table below. 2. for i 2 c communication, this assumes a minimum 1.5k ? pull - up resistor on scl and sda pins. 3. start up time is from pc1 set to valid outputs. time varies with output data rate (odr); see chart below 4. power up time is from vdd and io_vdd valid to device boot completion. 5. user selectable through i 2 c. 6. user selectable and dependent on odr and res.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 5 of 31 table 3 current profile odr (hz) res current ( a) 0 disabled 0.9 0.781 0 1.7 1.563 0 2 3.125 0 2.2 6.25 0 3.3 12.5 0 5 25 0 9 50 0 16 100 0 29 200 0 57 400 0 120 800 0 120 1600 0 120 all rates 1 120 kxtj2 representative current profile 1.7 2 2.2 3.3 5 9 16 29 57 120 120 120 1 10 100 1000 0.1 1 10 100 1000 10000 current ( a) odr (hz ) kxtj2 representative current (a) res = 0 full power mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 6 of 31 table 4 start up time kxtj2 representative start up time odr (hz) start up time (ms) 0.781 124 0 1.563 621 3.125 309 6.25 151 12.5 80 25 41 50 21 100 11 200 6 400 4 800 3 1600 2 1240 621 309 151 80 41 21 11 6 4 3 2 1 10 100 1000 10000 0.1 1 10 100 1000 10000 start up time (ms) odr (hz) kxtj2 start up time (ms)
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 7 of 31 table 5 environmental parameters units min typical max supply voltage (v dd ) absolute limits v - 0.5 - 3. 63 operating temperature range o c - 40 - 85 storage temperature range o c - 55 - 150 mech. shock (powered and unpowered) g - - 5000 for 0.5ms 10000 for 0.2ms esd hbm v - - 2000 caution: esd sensitive and mechanical shock sensitive component, improper handling can cause permanent damage to the device. this product conforms to directive 2002/95/ec of the european parliament and of the council of the european union (rohs). specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (pbb), or polybrominated diphenyl ethers (pbde) above the maximum concentration values (mcv) by weight in any of its homogenous materials. homogenous materials are "of uniform composition throughout." this product is halogen - free per iec 61249 - 2 - 21. specifically, the materials used in this product contain a maximum total halogen content of 150 0 ppm with less than 900 - ppm bromine and less than 900 - ppm chlorine. soldering soldering recommendations are available upon request or from www.kionix.com . floor life factory floor life exposure of the kx cj9 reels removed from the moisture barrier bag should not exceed a maximum of 168 hours at 30c/6 0%rh. if this floor life is exceeded, the parts should be dried per the ipc/jedec j - std - 033a standard. hf
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 8 of 31 application schematic table 6 . kxtj2 pin descriptions pin name description 1 addr i 2 c programmable address bit C connect to io_vdd or gnd 2 sda i 2 c serial data 3 io vdd the power supply input for the digital communication bus. optionally decouple this pin to ground with a 0.1uf ceramic capacitor. 4 r s vd reserved C connect to vdd, io vdd, or gnd 5 int physical interrupt 6 gnd ground 7 vdd the power supply input. decouple this pin to ground with a 0.1uf ceramic capacitor. 8 gnd ground 9 gnd ground 10 vdd the power supply input. decouple this pin to ground with a 0.1uf ceramic capacitor. 11 io vdd the power supply input for the digital communication bus. optionally decouple this pin to ground with a 0.1uf ceramic capacitor. 12 scl i 2 c serial clock addr 1 2 3 4 5 7 8 9 10 90 12 vdd scl sda kxtj2 res io vdd c 1 11 6 int c 2
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 9 of 31 test specifications ! special characteristics : these characteristics have been identified as being critical to the customer. every part is tested to verify its conformance to specification prior to shipment. table 7 . test specifications parameter specification test conditions zero - g offset @ rt 0 +/ - 205 counts 25c, vdd = 2.6 v
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 10 of 31 package dimensions and orientation 2 x 2 x 0.9 mm lga all dimensions and tolerances conform to asme y14.5m - 1994
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 11 of 31 orientation when device is accelerated in +x, +y or +z direction, the corresponding output will increase. static x/y/z output response versus orientation to earths surface (1g): gsel1=0, gsel0=0 ( 2g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 1024 64 0 0 - 1024 - 64 0 0 0 0 0 0 y (counts) 0 0 - 1024 0 - 64 0 0 1024 64 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 1024 64 - 1 024 - 64 x - polarity + 0 - 0 0 0 y - polarity 0 - 0 + 0 0 z - polarity 0 0 0 0 + - (1g) earths surface pin 1 +x +y +z
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 12 of 31 static x/y/z output response versus orientation to earths surface (1g): gsel1=0, gsel0=1 ( 4g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 512 32 0 0 - 512 - 32 0 0 0 0 0 0 y (counts) 0 0 - 512 - 32 0 0 512 32 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 512 32 - 512 - 32 x - polarity + 0 - 0 0 0 y - polarity 0 - 0 + 0 0 z - polarity 0 0 0 0 + - (1g) earths surface static x/y/z output response versus orientation to earths surface (1g): gsel1=1, gsel0=0 ( 8g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 256 16 0 0 - 256 - 16 0 0 0 0 0 0 y (counts) 0 0 - 256 - 16 0 0 256 16 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 256 16 - 256 - 16 x - polarity + 0 - 0 0 0 y - polarity 0 - 0 + 0 0 z - polarity 0 0 0 0 + - (1g) earths surface
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 13 of 31 kxt j2 digital interface the kionix kxt j2 digital accelerometer has the ability to communicate on the i 2 c digital serial interface bus . this a llows for easy system integration by eliminating analog - to - digital converter requirements and by providing direct communication with system micro - controllers . the serial interface terms and descriptions as indicated in table 8 . serial interface terminologies below will be observed throughout this document. term description transmitter the device that transmits data to the bus. receiver the device that receives data from the bus. master the device that initiates a transfer, generates clock signals, and terminates a transfer. slave the device addressed by the master. table 8 . serial interface terminologies i 2 c serial interface as previously mentioned, the kxt j2 has the ability to communicate on an i 2 c bus. i 2 c is primarily used for synchronous serial communication between a master device and one or more slave devices. the master, typically a micro controller, provides the seri al clock signal and addresses slave devices on the bus. the kxt j2 always operates as a slave device during standard master - slave i 2 c operation. i 2 c is a two - wire serial interface that contains a serial clock (scl) line and a serial data (sda) line. scl is a serial clock that is provided by the master, but can be held low by any slave device, putting the master into a wait condition. sda is a bi - directional line used to transmit and receive data to and from the interface. data is transmitted msb (most s ignificant bit) first in 8 - bit per byte format, and the number of bytes transmitted per transfer is unlimited. the i 2 c bus is considered free when both lines are high. the i 2 c interface is compliant with high - speed mode, fast mode and standard mode i 2 c st andards.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 14 of 31 figure 1 . multiple kxt j2 i 2 c connection i 2 c operation transactions on the i 2 c bus begin after the master transmits a start condition (s), which is defined as a high - to - low transition on the data line while the scl line is held high. the bus is considered busy after this condition. the next byte of data tran smitted after the start condition contains the slave address (sad) in the seven msbs (most significant bits), and the lsb (least significant bit) tells whether the master will be receiving data 1 from the slave or transmitting data 0 to the slave. whe n a slave address is sent, each device on the bus compares the seven msbs with its internally stored address. if they match, the device considers itself addressed by the master. the kxt j2 s slave address is comprised of a programmable part and a fixed pa rt, which allows for connection of multiple kxt j2 's to the same i 2 c bus. the slave address associated with the kxt j2 is 000111x, where the programmable bit, x, is determined by the assignment of addr (pin 1 ) to gnd or io_ vdd. figure 1 above shows how two kxt j2 's would be implemented on an i 2 c bus. it is mandatory that receiving devices acknowledge (ack) each transaction. therefore, the transmitter must release the sda line during this ack pulse. the receiver then pulls the data line low so that it remains stable low during the high period of the ack clock pulse. a receiver that has been addressed, whether it is master or slave, is obliged to gener ate an ack after each byte of data has been received. to conclude a transaction, the master must transmit a stop condition (p) by transitioning the sda line from low to high while scl is high. the i 2 c bus is now free. mcu kxtj2 sda scl io_vdd addr scl scl sda sda scl s da addr kxtj2
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 15 of 31 writing to a kxt j2 8 - bit register upon power up, the master must write to the kxt j2 s control registers to set its operational mode. therefore, when writing to a control register on the i 2 c bus, as shown sequence 1 on the following page, the following protocol must be observed: after a start condition, sad+w transmission, and the kxt j2 ack has been returned, an 8 - bit register address (ra) command is transmitted by the master. this command is telling the kxt j2 to which 8 - bit register the master will be writing the data. since this is i 2 c mode, the msb of the ra command should always be zero (0). the kxt j2 acknowledges the ra and the master transmits the data to be stored in the 8 - bit regi ster. the kxt j2 acknowledges that it has received the data and the master transmits a stop condition (p) to end the data transfer. the data sent to the kxt j2 is now stored in the appropriate register. the kxt j2 automatically increments the received ra c ommands and, therefore, multiple bytes of data can be written to sequential registers after each slave ack as shown in sequence 2 on the following page. reading from a kxt j2 8 - bit register when reading data from a kxt j2 8 - bit register on the i 2 c bus, as shown in sequence 3 on the next page, the following protocol must be observed: the master first transmits a start condition (s) and the appropriate slave address (sad) with the lsb set at 0 to write. the kxt j2 acknowledges and the master transmits the 8 - bit ra of the register it wants to read. the kxt j2 again acknowledges, and the master transmits a repeated start condition (sr). after the repeated start condition, the master addresses the kxt j2 with a 1 in the lsb (sad+r) to read from the previousl y selected register. the slave then acknowledges and transmits the data from the requested register. the master does not acknowledge (nack) it received the transmitted data, but transmits a stop condition to end the data transfer. note that the kxt j2 au tomatically increments through its sequential registers, allowing data to be read from multiple registers following a single sad+r command as shown below in sequence 4 on the following page. the 8 - bit register data is transmitted using a left - most format, first bit shifted/clocked out being the msb bit. if a receiver cannot transmit or receive another complete byte of data until it has performed some other function, it can hold scl low to force the transmitter into a wait state. data transfer only contin ues when the receiver is ready for another byte and releases scl.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 16 of 31 data transfer sequences the following information clearly illustrates the variety of data transfers that can occur on the i 2 c bus and how the master and slave interact during these transfers. table 9 defines the i 2 c terms used during the data transfers. term definition s start condition sr repeated start condition sad slave address w write bit r read bit ack acknowledge nack not acknowledge ra register address data transmitted/received data p stop condition table 9 . i 2 c terms sequence 1. the master is writing one byte to the slave. master s sad + w ra data p slave ack ack ack sequence 2. the master is writing multiple bytes to the slave. master s sad + w ra data data p slave ack ack ack ack sequence 3. the master is receiving one byte of data from the slave. master s sad + w ra sr sad + r nack p slave ack ack ack data sequence 4. the master is receiving multiple bytes of data from the slave. master s sad + w ra sr sad + r ack nack p slave ack ack ack data data
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 17 of 31 kxt j2 embedded registers the kxt j2 has 20 embedded 8 - bit registers that are accessible by the user. this section contains the addresses for all embedded registers and also describes bit functions of each register. table 8 below provides a listing of the accessible 8 - bit registers and the ir addresses. register name type i2c address read/write hex binary kionix reserved - 0x00 C 0x05 - xout_l r 0x06 0000 0110 xout_h r 0x07 0000 0111 yout_l r 0x08 0000 1000 yout_h r 0x09 0000 1001 zout_l r 0x0a 000 0 1010 zout_h r 0x0b 000 0 1011 dcst _resp r 0x0c 0000 1100 kionix reserved - 0x 0 d C 0x0e - who_am_i r 0x0f 0000 1111 kionix reserved - 0x10 C 0x15 - int_source1 r 0x16 0001 0110 int_source2 r 0x17 0001 0111 status_reg r 0x18 0001 1000 kionix reserved - 0x19 - int_rel r 0x1a 0001 1010 ctrl_reg1 * r/w 0x1b 0001 1011 kionix reserved - 0x1c 0001 1100 ctrl_reg2* r/w 0x1d 0001 1101 int_ctrl_reg1 * r/w 0x1e 0001 1110 int_ctrl_reg2* r/w 0x1f 0001 1111 kionix reserved - 0x20 0010 0000 data_ctrl_reg * r/w 0x21 0010 0001 kionix reserved - 0x22 C 0x 28 - wakeup_timer* r/w 0x29 0010 1001 kionix reserved - 0x2a C 0x 39 - self_test r/w 0x3a 0011 1010 kionix reserved - 0x 3b C 0x 69 - wakup_threshold* r/w 0x6a 0110 1010 * note: when changing the contents of these registers, the pc1 bit in ctrl_reg1 must first be set to 0. table 10 . kxt j2 register map
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 18 of 31 kxt j2 register descriptions accelerometer outputs these registers contain up to 12 - bits of valid acceleration data for each axis depending on the setting of the res bit in ctrl_reg1, where the acceleration outputs are represented in 12 - bit valid data when res = 1 and 8 - bit valid data when res = 0. th e data is updated every user - defined odr period, is protected from overwrite during each read, and can be converted from digital counts to acceleration (g) per table 11 below. the register acceleration output binary data is represented in 2s complement format. for example, if n = 12 bits, then the counts range is from - 2048 to 2047, and if n = 8 bits, then the counts range is from - 128 to 127. 12 - bit register data (2s complement) equivalent counts in decimal range = +/ - 2g range = +/ - 4g range = +/ - 8g 0111 1111 1111 2047 +1.999g +3.998g +7.996g 0111 1111 1110 2046 +1.998g +3.996g +7.992g 0000 0000 0001 1 +0.001g +0.002g +0.004g 0000 0000 0000 0 0.000g 0.000g 0.000g 1111 1111 1111 - 1 - 0.001g - 0.002g - 0.004g 1000 0000 0001 - 2047 - 1.999g - 3.998g - 7.996g 1000 0000 0000 - 2048 - 2.000g - 4.000g - 8.000g 8 - bit register data (2s complement) equivalent counts in decimal range = +/ - 2g range = +/ - 4g range = +/ - 8g 0111 1111 127 +1.984g +3.968g +7.936g 0111 1110 126 +1.968g +3.936g +7.872g 0000 0001 1 +0.016g +0.032g +0.064g 0000 0000 0 0.000g 0.000g 0.000g 1111 1111 - 1 - 0.016g - 0.032g - 0.064g 1000 0001 - 127 - 1.984g - 3.968g - 7.936g 1000 0000 - 128 - 2.000g - 4.000g - 8.000g table 11 . acceleration (g) calculation
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 19 of 31 xout_l x - axis accelerometer output least significant byte r r r r r r r r xoutd3 xoutd2 xoutd1 xoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x06h xout_h x - axis accelerometer output most significant byte r r r r r r r r xoutd11 xoutd10 xoutd9 xoutd8 xoutd7 xoutd6 xoutd5 xoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x07h yout_l y - axis accelerometer output least significant byte r r r r r r r r youtd3 youtd2 youtd1 youtd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x08h yout_h y - axis accelerometer output most significant byte r r r r r r r r youtd11 youtd10 youtd9 youtd8 youtd7 youtd6 youtd5 youtd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x09h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 20 of 31 zout_l z - axis accelerometer output least significant byte r r r r r r r r zoutd3 zoutd2 zoutd1 zoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x0ah zout_h z - axis accelerometer output most significant byte r r r r r r r r zoutd11 zoutd10 zoutd9 zoutd8 zoutd7 zoutd6 zoutd5 zoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x0bh dcst_resp this register can be used to verify proper integrated circuit functionality. it always has a byte value of 0x55h unless the dcst bit in ctrl_reg3 is set. at that point this value is set to 0xaah. the byte value is returned to 0x55h after reading this register. r r r r r r r r dcstr7 dcstr6 dcstr5 dcstr4 dcstr3 dcstr2 dcstr1 dcstr0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01010101 i 2 c address: 0x0ch who_am_i this register can be used for supplier recognition, as it can be factory written to a known byte value. the default value is 0x 09 h . r r r r r r r r wia7 wia6 wia5 wia4 wia3 wia2 wia1 wia0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00001001 i 2 c address: 0x0fh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 21 of 31 interrupt source registers these two registers report interrupt state changes. this data is updated when a new interrupt event occurs and each applications result is latched until the interrupt release register is read. the programmable interrupt engine can be configured to repor t data in an unlatched manner via the interrupt control registers. int _ source1 this register reports which function caused an interrupt. reading from the interrupt release register (int_rel, 0x1ah) will clear the entire contents of this register. r r r r r r r r 0 0 0 drdy 0 0 wufs 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x16h drdy - indicates that new acceleration data ( a t reg addr 0x 06h to 0x 0bh) is available. this bit is cleared when acceleration data is read or the interrupt release register (in t_rel , 0x 1ah) is read. 0 = new acceleration data not available 1 = new acceleration data available wufs - wake up, this bit is cleared when the interrupt source latch register (in t_re l, ox 1ah) is read. 0 = no motion 1 = motion has activated the interrupt
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 22 of 31 int _ source2 this register reports the axis and direction of detected motion per table 12 . this register is cleared when the interrupt source latch register (in t_rel, 0x 1ah) is read . r r r r r r r r 0 0 xnwu xpwu ynwu ypwu znwu zpwu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1 7 h bit description xnwu x negative (x - ) reported xpwu x positive (x+) reported ynwu y negative (y - ) reported ypwu y positive (y+) reported znwu z negative (z - ) reported zpwu z positive (z+) reported table 12 . kxt j2 motion reporting status_reg this register reports the status of the interrupt. r r r r r r r r 0 0 0 int 0 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x18h int reports the combined (or) interrupt information of drdy and wufs in the interrupt source register ( int_source1 , 0x16h) . this bit is cleared when acceleration data is read or the interrupt release register ( int_rel, 1ah) is read. 0 = no interrupt event 1 = interrupt event has oc curred
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 23 of 31 int_rel latched interrupt source information (in t_source1, 0x16h and in t_source2, 0x 17h) is cleared and physical interrupt latched pin (7) is changed to its inactive state when this register is read . r r r r r r r r x x x x x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1ah
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 24 of 31 ctrl_reg1 read/write control register that controls the main feature set. r/w r/w r/w r/w r/w r/w r/w r/w pc1 res drdye gsel1 gsel0 0 wufe 0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x1bh pc1 controls the operating mode of the kxt j2 . 0 = stand - by mode 1 = operating mode res determines the performance mode of the kxt j2 . note that to change the value of this bit, the pc1 bit must first be set to 0. 0 = low current, 8 - bit valid . only available for odr <= 200 hz. bandwidth (hz) = 800 1 = high current, 12 - bit or 14 - bit valid . bandwidth (hz) = odr/2 drdye enables the reporting of the availability of new acceleration data as an interrupt. note that to change the value of this bit, the pc1 bit must first be set to 0. 0 = availability of new acceleration data is not reflected as an interrupt 1 = availability of new acceleration data is reflected as an interrupt gsel1, gsel 0 selects the acceleration range of the ac celerometer outputs per table 13 . note that to change the value of this bit, the pc1 bit must first be set to 0 . gsel1 gsel0 range 0 0 +/ - 2g 0 1 +/ - 4g 1 0 +/ - 8g 1 1 +/ - 8g 1 table 13 . selected acceleration range wuf e enables the wake up (motion detect) function. 0= disabled, 1= enabled. note that to change the value of this bit, the pc1 bit must first be set to 0. 0 = wake up function disabled 1 = wake up function enabled 1 this is a 14 - bit mode available only in full power mode and only for registers 0x 06h - 0x 0bh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 25 of 31 ctrl_reg 2 read/write control register that provides more feature set control. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w srst reserved reserved dcst reserved owufa owufb owufc reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x1dh srst initiates software reset, which performs the ram reboot routine. this bit will remain 1 until the ram reboot routine is finished. srst = 0 C no action srst = 1 C start ram reboot routine dcst initiates the digital communication self - test function. dcst = 0 C no action dcst = 1 C sets st_resp register to 0xaah and when st_resp is read, sets this bit to 0 and sets st_resp to 0x55h owufa, owufb, owufc sets the output data rate for the wake up function (motion detection) per table 14 below owufa owufb owufc wake up function output data rate 0 0 0 0.781hz 0 0 1 1.563hz 0 1 0 3.125hz 0 1 1 6.25hz 1 0 0 12.5hz 1 0 1 25hz 1 1 0 50hz 1 1 1 100hz table 14 . output data rate for wake up function
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 26 of 31 int_ctrl_reg1 this register controls the settings for the physical interrupt pin (7). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 ien iea iel 0 0 0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00010000 i 2 c address: 0x1eh ien enables/disables the physical interrupt pin (7) ien = 0 C physical interrupt pin (7) is disabled ien = 1 C physical interrupt pin (7) is enabled iea sets the polarity of the physical interrupt pin (7) iea = 0 C polarity of the physical interrupt pin (7) is active low iea = 1 C polarity of the physical interrupt pin (7) is active high iel sets the response of the physical interrupt pin (7) iel = 0 C the physical interrupt pin (7) latches until it is cleared by reading int_rel iel = 1 C the physical interrupt pin (7) will transmit one pulse with a period of 0.03 - 0.05ms int_ctrl_reg2 this register controls which axis and direction of detected motion can cause an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 xnwue xpwue ynwue ypwue znwue zpwue reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00111111 i 2 c address: 0x1f h xnwu - x negative (x - ) : 0 = disabled, 1 = enabled xpwu - x positive (x+) : 0 = disabled, 1 = enabled ynwu - y negative (y - ) : 0 = disabled, 1 = enabled ypwu - y positive (y+) : 0 = disabled, 1 = enabled znwu - z negative (z - ) : 0 = disabled, 1 = enabled zpwu - z positive (z+) : 0 = disabled, 1 = enabled
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 27 of 31 data_ctrl_reg read/write control register that configures the acceleration outputs. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 osaa osab osac osad reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000010 i 2 c address: 0x21h osaa, osab, osac , osad sets the output data rate (odr) for the low - pass filtered a cceleration output s per table 15 . osaa osab osac osad output data rate lpf roll - off 1 0 0 0 0.781hz 0.3905hz 1 0 0 1 1.563hz 0.781hz 1 0 1 0 3.125hz 1.563hz 1 0 1 1 6.25hz 3.125hz 0 0 0 0 12.5hz 6.25hz 0 0 0 1 25hz 12.5hz 0 0 1 0 50hz 25hz 0 0 1 1 100hz 50hz 0 1 0 0 200hz 100hz 0 1 0 1 400hz 200hz 0 1 1 0 800hz 400hz 0 1 1 1 1600hz 800hz table 15 . acceleration output data rate (odr) and lpf roll - off note: output data rates >= 400hz will force device into full power mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 28 of 31 wake up_timer this register sets the time motion must be present before a wake - up interrupt is set. every count is calculated as 1/owuf delay period. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. valid entries are from 1 to 255, excluding the zero value. r/w r/w r/w r/w r/w r/w r/w r/w wufc7 wufc6 wufc5 wufc4 wufc3 wufc2 wufc1 wufc0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 000000 0 i 2 c address: 0x2 9 h self_test when 0xca is written to this register, the mems self - test function is enabled. electrostatic - actuation of the accelerometer, results in a dc shift of the x, y and z axis outputs. writing 0x00 to this register will return the accelerometer to normal operation. wakeup_threshold this register sets the threshold for wake - up (motion detect) interrupt is set. the kxt j2 will ship from the factory with this value set to correspond to a change in acceleration of 0.5g . note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w wuth7 wuth6 wuth5 wuth4 wuth3 wuth2 wuth1 wuth0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0001 000 i 2 c address: 0x6ah r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 1 0 1 0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x3ah
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 29 of 31 kxt j2 embedded wake up function the kxt j2 contains an interrupt engine that can be configured by the user to report when qualified changes in acceleration occur. the user has the option to enable or disable specific axes and specific directions, as well as to specify the delay time. an example use case for the engine would be to detect motion on any axis to signal an event and wake up the accelerometer or other devices . this can be achieved by configuring the engine to detect when the acceleration on any axis is greater than the user - defined th reshold for a user - defined amount of time. equations 1 and 2 show how to calculate the engine threshold (wakeup_thresh old ) and delay time (wakeup_timer) register values for the desired result. wakeup_thresh old (counts) = desired threshol d (g) x 16 (counts/g) equation 1. wake up threshold note that this defined threshold is differential with respect to the previous reading. t his threshold is constan t ly compared with the result of the differential acceleration (future reading(g) C previous readin g(g)). for example, if the threshold is set to 0.4g and it is previously experiencing a 1g acceleration in the axis and the future reading is still 1g, then the differential acceleration value is 0 g , and this case will not exceed the threshold of 0.4g and no interrupt can be generated . on the other hand, if it is previously experiencing a 1g acceleration in the axis and the future reading changed to 1 .6 g, then the differential acceleration value is 0.6 g and in this case it will exceed the threshold o f 0.4g and the interrupt will be generated. the wake up delay time in counts is defined as follows: wakeup_timer (counts) = desired delay time (sec) x owuf (hz) equation 2 . wake up delay time
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 30 of 31 figure 2 below shows the latched response of the wake up function with wuf timer = 10 counts. figure 2 . latched motion interrupt response the kxtj2 wake - up function is always latched. however, if the int_ctrol_reg1 is set with iel = 1, then upon a wake - up event the wuf interrupt signal will pulse and return low , but only once. t he wuf interrupt output will not reset until a read of the int_rel l atch reset register. 0g typical wake up interrupt example differential acceleration wuf threshold ex: delay counter = 10 motion 10 inactive wuf timer
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxtj 2 - 1009 rev. 4 mar - 2013 36 thornwood dr. C ithaca, ny 14850 ? 2012 kionix C all rights reserved tel : 607 - 257 - 1080 C fax: 607 - 257 - 1146 595 - 4464 - 1303111031 www.kionix.com - info@kionix.com page 31 of 31 revision history revision description date 1 initial release 27 - sep - 2012 2 update to include addr pin description connect to io_vdd or gnd 26 - nov - 2012 3 updated floor lif e spec 06 - dec - 2012 4 updated table 7 to match table 1, updated self test spec 11 - mar - 2013 "kionix" is a registered trademark of kionix, inc. products described herein are protected by patents issued or pending. no license is granted by implication or otherwise under any patent or other rights of kionix. the information contained herein is be lieved to be accurate and reliable but is not guaranteed. kionix does not assume responsibility for its use or distribution. kionix also reserves the right to change product specifications or discontinue t his product at any time without prior notice. t his publication supersedes and replaces all information previously supplied.

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