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1. general description the HEF4030B is a quad 2-input exclusive-or gate. the outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. it operates over a recommended v dd power supply range of 3 v to 15 v referenced to v ss (usually ground). unused inputs must be connected to v dd , v ss , or another input. 2. features and benefits ? fully static operation ? 5 v, 10 v, and 15 v parametric ratings ? standardized symmetrical output characteristics ? specified from ? 40 ? c to +125 ? c ? complies with jedec standard jesd 13-b ? inputs and outputs are protected against electrostatic effects 3. ordering information 4. functional diagram HEF4030B quad 2-input exclusive-or gate rev. 4 ? 13 november 2013 product data sheet table 1. ordering information all types operate from ? 40 ? c to +125 ? c type number package name description version HEF4030Bp dip14 plastic dual in-line package; 14 leads (300 mil) sot27-1 HEF4030Bt so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 fig 1. functional diagram fig 2. logic diagram (one gate) d d d % $ % $ % $ % $ < < < < mna788 y a b
HEF4030B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 4 ? 13 november 2013 2 of 12 nxp semiconductors HEF4030B quad 2-input exclusive-or gate 5. pinning information 5.1 pinning 5.2 pin description 6. functional description [1] h = high voltage level; l = low voltage level fig 3. pin configuration + ( ) % $ 9 ' ' % % < $ < < $ < % % 9 6 6 $ d d d table 2. pin description symbol pin description 1a, 2a, 3a, 4a 1, 5, 8, 12 data input 1b, 2b, 3b, 4b 2, 6, 9, 13 data input 1y, 2y, 3y, 4y 3, 4, 10, 11 data output v ss 7 ground (0 v) v dd 14 supply voltage table 3. functional table [1] input output na nb ny lll lhh hl h hhl HEF4030B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 4 ? 13 november 2013 3 of 12 nxp semiconductors HEF4030B quad 2-input exclusive-or gate 7. limiting values [1] for dip14 packages: above t amb = 70 ? c, p tot derates linearly with 12 mw/k. [2] for so14 packages: above t amb = 70 ? c, p tot derates linearly with 8 mw/k. 8. recommended operating conditions table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss = 0 v (ground). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +18 v i ik input clamping current v i < ? 0.5 v or v i >v dd + 0.5 v - ? 10 ma v i input voltage ? 0.5 v dd + 0.5 v i ok output clamping current v o < ? 0.5 v or v o >v dd + 0.5 v - ? 10 ma i i/o input/output current - ? 10 ma i dd supply current - 50 ma t stg storage temperature ? 65 +150 ?c t amb ambient temperature ? 40 +125 ?c p tot total power dissipation t amb = ? 40 ? c to + 125 ?c dip14 [1] -750mw so14 [2] -500mw p power dissipation per output - 100 mw table 5. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3 - 15 v v i input voltage 0 - v dd v t amb ambient temperature in free air ? 40 - +125 ?c ? t/ ? v input transition rise and fall rate v dd = 5 v --3.75 ? s/v v dd = 10 v --0.5 ? s/v v dd = 15 v --0.08 ? s/v HEF4030B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 4 ? 13 november 2013 4 of 12 nxp semiconductors HEF4030B quad 2-input exclusive-or gate 9. static characteristics table 6. static characteristics v ss = 0 v; v i =v ss or v dd ; unless otherwise specified. symbol parameter conditions v dd t amb = ? 40 ?c t amb = +25 ?c t amb = +85 ? c t amb = +125 ?c unit min max min max min max min max v ih high-level input voltage ?i o ? < 1 ? a 5 v 3.5 - 3.5 - 3.5 - 3.5 - v 10 v7.0-7.0-7.0- 7.0 - v 15 v 11.0 - 11.0 - 11.0 - 11.0 - v v il low-level input voltage ?i o ? < 1 ? a 5 v - 1.5 - 1.5 - 1.5 - 1.5 v 10 v - 3.0 - 3.0 - 3.0 - 3.0 v 15 v - 4.0 - 4.0 - 4.0 - 4.0 v v oh high-level output voltage ?i o ? < 1 ? a 5 v 4.95 - 4.95 - 4.95 - 4.95 - v 10 v 9.95 - 9.95 - 9.95 - 9.95 - v 15 v 14.95 - 14.95 - 14.95 - 14.95 - v v ol low-level output voltage ?i o ? < 1 ? a 5 v - 0.05 - 0.05 - 0.05 - 0.05 v 10 v - 0.05 - 0.05 - 0.05 - 0.05 v 15 v - 0.05 - 0.05 - 0.05 - 0.05 v i oh high-level output current v o = 2.5 v 5 v - ? 1.7 - ? 1.4 - ? 1.1 - ? 1.1 ma v o = 4.6 v 5 v - ? 0.64 - ? 0.5 - ? 0.36 - ? 0.36 ma v o = 9.5 v 10 v - ? 1.6 - ? 1.3 - ? 0.9 - ? 0.9 ma v o = 13.5 v 15 v - ? 4.2 - ? 3.4 - ? 2.4 - ? 2.4 ma i ol low-level output current v o = 0.4 v 5 v 0.64 - 0.5 - 0.36 - 0.36 - ma v o = 0.5 v 10 v 1.6 - 1.3 - 0.9 - 0.9 - ma v o = 1.5 v 15 v 4.2 - 3.4 - 2.4 - 2.4 - ma i i input leakage current 15 v - ? 0.1 - ? 0.1 - ? 1.0 - ? 1.0 ? a i dd supply current all valid input combinations; i o =0a 5 v - 0.25 - 0.25 - 7.5 - 7.5 ? a 10 v - 0.5 - 0.5 - 15.0 - 15.0 ? a 15 v - 1.0 - 1.0 - 30.0 - 30.0 ? a c i input capacitance ---7.5-- - -pf HEF4030B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 4 ? 13 november 2013 5 of 12 nxp semiconductors HEF4030B quad 2-input exclusive-or gate 10. dynamic characteristics [1] the typical value of the propagation delay and output transi tion time can be calculated with the extrapolation formula (c l in pf). table 7. dynamic characteristics t amb = 25 ? c; for waveforms see figure 4 ; for test circuit, see figure 5 ; unless otherwise specified. symbol parameter extrapolation formula [1] v dd min typ max unit t phl high to low propagation delay 57 + 0.55 ? c l 5 v - 85 175 ns 24 + 0.23 ? c l 10 v - 35 75 ns 22 + 0.16 ? c l 15 v - 30 55 ns t plh low to high propagation delay 47 + 0.55 ? c l 5 v - 75 150 ns 19 + 0.23 ? c l 10 v - 30 65 ns 17 + 0.16 ? c l 15 v - 25 50 ns t thl high to low output transition time 10 + 1.00 ? c l 5 v - 60 120 ns 9 + 0.42 ? c l 10 v - 30 60 ns 6 + 0.28 ? c l 15 v - 20 40 ns t tlh low to high output transition time 10 + 1.00 ? c l 5 v - 60 120 ns 9 + 0.42 ? c l 10 v - 30 60 ns 6 + 0.28 ? c l 15 v - 20 40 ns table 8. dynamic power dissipation v ss = 0 v; t r = t f ? 20 ns; t amb = 25 ? c. symbol parameter v dd typical formula where p d dynamic power dissipation 5 v p d = 1100 ? f i + ? (f o ? c l ) ? v dd 2 ( ? w) f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; ? (f o ? c l ) = sum of the outputs; v dd = supply voltage in v. 10 v p d = 4900 ? f i + ? (f o ? c l ) ? v dd 2 ( ? w) 15 v p d = 14400 ? f i + ? (f o ? c l ) ? v dd 2 ( ? w) HEF4030B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 4 ? 13 november 2013 6 of 12 nxp semiconductors HEF4030B quad 2-input exclusive-or gate 11. waveforms measurement points are given in table 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 4. input to output propagation delays and output transition times d d d q $ q % l q s x w q < |