document number: 91405 www.vishay.com s10-0998-rev. a, 26-apr-10 1 power mosfet irFD9010, sihFD9010 vishay siliconix features ? for automatic insertion ? compact, end stackable ?fast switching ? low drive current ? easy paralleled ? excellent temperature stability ? p-channel versatility ? compliant to rohs directive 2002/95/ec description the hvmdip technology is the key to vishays advanced line of power mosfet transistors. the efficient geometry and unique processing of the hvmdip design achieves very low on-state resist ance combined with high transconductance and extreme device ruggedness. the p-channel hvmdips are designed for application which require the convenience of reverse polarity operation. they retain all of the features of the more common n-channel hvmdips such as voltage control, very fast switching, ease of paralleling, and excelle nt temperature stability. p-channels hvmdips are intended for use in power stages where complementary symmetry with n-channel devices offers circuit simplification. they are also very useful in drive stages because of the circui t versatility offered by the reverse polarity connection. applications include motor control, audio amplifiers, swit ched mode converters, control circuits and pulse amplifiers. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = - 25 v, starting t j = 25 c, l = 52 mh, r g = 25 , i as = - 2.0 a (see fig. 12). c. i sd - 4.0 a, di/dt 75 a/s, v dd v ds , t j 175 c. d. 1.6 mm from case. product summary v ds (v) - 50 r ds(on) ( )v gs = - 10 v 0.50 q g (max.) (nc) 11 q gs (nc) 3.8 q gd (nc) 4.1 configuration single s g d p-channel mosfet hvmdip d s g ordering information package hvmdip lead (pb)-free irFD9010pbf sihFD9010-e3 snpb irFD9010 sihFD9010 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 50 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 c i d - 1.1 a t c = 100 c - 0.68 pulsed drain current a i dm - 8.8 linear derating factor 0.01 w/c inductive current, clamped l = 100 h see fig. 14 i lm - 8.8 a inductive current, unclamped (avalanche current) see fig. 15 i l - 1.5 maximum power dissipation t c = 25 c p d 1w operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91405 2 s10-0998-rev. a, 26-apr-10 irFD9010, sihFD9010 vishay siliconix notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja - 120 c/w specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0 v, i d = - 250 a - 50 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = - 1 ma - - 0.091 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 500 na zero gate voltage drain current i dss v ds = - 50 v, v gs = 0 v - - - 250 a v ds = - 40 v, v gs = 0 v, t j = 125 c - - - 1000 on-state drain current i d(on) v gs = 10 v v ds > i d(on) x r ds(on) max. - 1.1 - - a drain-source on-state resistance r ds(on) v gs = - 10 v i d = - 0.58 a b - 0.35 0.50 forward transconductance g fs v ds = - 20 v, i d = - 2.4 a 1.7 2.5 - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 5 - 240 - pf output capacitance c oss - 160 - reverse transfer capacitance c rss -30- total gate charge q g v gs = - 10 v i d = - 4.7 a, v ds = 0.8 v see fig. 6 and 13 b -7.211 nc gate-source charge q gs -2.53.8 gate-drain charge q gd -2.74.1 turn-on delay time t d(on) v dd = - 25 v, i d = - 4.7 a r g = 24 , r d = 5.6 , see fig. 10 b -6.19.2 ns rise time t r -4771 turn-off delay time t d(off) -1320 fall time t f -3959 internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.0- nh internal source inductance l s -6.0- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 1.1a pulsed diode forward current a i sm --- 8.8 body diode voltage v sd t j = 25 c, i s = - 0.7 a, v gs = 0 v b --- 5.5v body diode reverse recovery time t rr t j = 25 c, i f = - 4.7 a, di/dt = 100 a/s b 33 75 160 ns body diode reverse recovery charge q rr 0.090 0.22 0.52 c forward turn-on time t on intrinsic turn-on time is negligib le (turn-on is dominated by l s and l d ) d s g s d g
document number: 91405 www.vishay.com s10-0998-rev. a, 26-apr-10 3 irFD9010, sihFD9010 vishay siliconix typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage 10 8 6 4 2 0 25 20 15 10 5 0 - v gs , drain-to- s ource voltage (v) - i d , drain current (a) - 7 v - 10 v - 8 v - 4 v v gs = - 6 v - 5 v 80 s pul s e width 10 8 6 4 2 0 5 4 3 2 1 0 - v gs , drain-to- s ource voltage (v) - i d , drain current (a) - 7 v - 10 v - 8 v - 4 v v gs = - 6 v - 5 v 80 s pul s e width 10 1 0.1 0.01 0.001 10 8 6 4 3 0 - v gs , drain-to- s ource voltage (v) - i d , drain current (a) t j = 150 c 80 s pul s e width v d s = 2 x v gs t j = 25 c 3.0 2.4 1.8 1.2 0.6 0 160 - 60 t j , junction temperature (c) r d s (on) , drain-to- s ource on re s i s tance (normalized) v gs = - 10 v i d = - 4.7 v 140 120 100 80 60 40 20 0 - 20 - 40 500 400 300 200 100 0 100 10 1 - v gs , drain-to- s ource voltage (v) capacitance (pf) v gs = 0 v, f = 1 mhz c i ss = c g s + c gd , c d s s horted c r ss = c gd c o ss = c d s + c gd c r ss c i ss c o ss 20 16 12 8 4 0 15 12 9 6 3 0 q g , total g ate charge (nc) - v gs , g ate-to- s ource voltage (v) v d s = - 40 v for te s t circuit s ee figure 13 i d = - 4.7 a
www.vishay.com document number: 91405 4 s10-0998-rev. a, 26-apr-10 irFD9010, sihFD9010 vishay siliconix fig. 7 - typical source-d rain diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms 10 1 0.1 5 4 3 2 1 0 - v s d , s ource-to-drain voltage (v) - i s d , rever s e drain current (a) t j = 150 c t j = 25 c 100 10 1 0.01 100 10 1 - v d s , drain-to- s ource voltage (v) - i d , drain current (a) t c = 25 c t j = 150 c s ingle pul s e 10 s 0.1 100 operation in thi s area limited by r d s (on) 100 s 1 m s 10 m s 100 m s 1 s dc 2.0 1.6 1.2 0.8 0.4 0 150 125 100 75 50 25 t c , ca s e temperature (c) - i d , drain current (a) p u lse width 1 s d u ty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd v gs 10 % 90 % v ds t d(on) t r t d(off) t f
document number: 91405 www.vishay.com s10-0998-rev. a, 26-apr-10 5 irFD9010, sihFD9010 vishay siliconix fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 13a - basic ga te charge waveform fig. 13b - gate charge test circuit 1000 100 10 1 0.1 100 0.1 0.01 0.001 0.0001 0.00001 t 1 , rectangular pul s e duration ( s ) thermal re s pon s e (z dthjc ) 110 0.2 0.1 0.5 0.02 0.01 0.05 s ingle pul s e (thermal re s pon s e) note s : 1. duty factor, d = t 1 /t 2 2. peak t j = p dm x t thjc + t c p dm t 1 t 2 r g i as 0.01 w t p d.u.t l v ds + - v dd - 10 v var y t p to o b tain req u ired i as i as v ds v dd v ds t p q gs q gd q g v g charge - 10 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
www.vishay.com document number: 91405 6 s10-0998-rev. a, 26-apr-10 irFD9010, sihFD9010 vishay siliconix fig. 14 - for p-channel vishay siliconix maintains worldwide manufa cturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91405 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage reverse recovery c u rrent body diode forward c u rrent v gs = - 10 v* v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform ind u ctor c u rrent d = p.w. period + - - - - + + + * v gs = - 5 v for logic level and - 3 v drive devices peak diode recovery dv/dt test circuit v dd ? dv/dt controlled b y r g ? i sd controlled b y d u ty factor "d" ? d.u.t. - device u nder test d.u.t. circ u it layo u t considerations ? low stray ind u ctance ? gro u nd plane ? low leakage ind u ctance c u rrent transformer r g compliment n-channel of d.u.t. for driver
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