low-voltage/low-power copyright ? 2 009 by silicon laboratories 10.1.2009 port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0/vref p0.1/agnd p0.2/xtal1/rtcout p0.3/xtal2/wakeout p0.4/tx p0.5/rx p0.6/cnvstr p0.7/iref0 crossbar control port i/o configuration cip-51 8051 controller core 16k byte isp flash program memory 256 byte sram sfr bus 512 byte xram port 1 drivers p1.0/sck1 p1.1/miso1 p1.2/mosi1 p1.3/nss1 p1.4 p1.5 port 2 drivers spi 0,1 analog peripherals comparators + - power net vdd/dc+ gnd/dc- xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 12-bit adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator 6-bit iref vref gnd p1.6 iref0 cp0, cp0a p2.7/c2d + - cp1, cp1a smartclock oscillator xtal3 xtal4 dc/dc converter vbat gnd vreg digital power analog power crc engine dcen c8051f912 ultra-low power, hi gh-performance mcu ultra-low power - 160 a/mhz active current from 1.8?3.6 v @ 25 mhz - 10 na sleep current with data retention; bod disabled - 50 na sleep current with data retention; bod enabled - 300 na sleep current with smartclock (internal oscillator) - 600 na sleep current with smartclock (external crystal) - 2 s wake up from sleep - 1.5 s analog settling time supply voltage: 0.9 to 3.6 v - one-cell mode supports 0.9?3.6 v operation; bypass feature automatically shut s off the dc-dc converter when not needed - two-cell mode supports 1.8?3.6 v operation - built-in dc-dc converter with 1.8 ?3.3 v output (65 mw max) for use in one-cell mode; c an supply external devices 12-bit analog to digital converter - up to 75 ksps 12-bit mode or 300 ksps 10-bit mode - up to 15 external inputs - external pin or internal vref (no external capacitor required) - on-chip pga allows measuri ng voltages up to twice the ? reference voltage - autonomous burst mode with 16-bit automatic averaging ? accumulator - built-in temperature sensor two comparators - programmable hysteresis and response time - configurable as interrupt or reset source - low current (400 na typical) - up to 15 capacitive touch sense inputs internal 6-bit cu rrent reference - up to 500 a; source and sink capability - enhanced resolution via pwm interpolation development kit: c8051f912dk high-speed 8051 c core - pipe-lined instruction architecture ; executes 70% of instructions in 1 or 2 system clocks - 25 mips peak throughput with 25 mhz clock - expanded interrupt handler memory - 768 bytes internal data ram (256 + 512) - 16 kb flash; in-system programmable; full read/write/erase functio nality over the entire supply range digital peripherals - 16 port i/o; all 5 v tolerant with programmable drive strength - hardware enhanced uart, 2 spi and smbus? serial ports available concurrently - low power 32-bit smartclock operates down to 0.9 v - four general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with six capture/com - pare modules and watchdog timer clock sources - precision internal oscillators: 24.5 mhz with 2% accuracy sup - ports uart operation; spread-spectrum mode for reduced emi - low power internal oscillator: 20 mhz - external oscillator: crystal, rc, c, cmos clock - smartclock oscillator: 32.768 khz crystal or 16.4 khz lfo - can switch between clock sources on-the-fly; useful in power saving modes on-chip debug - on-chip debug circuitry facilitates full speed, non-intrusive in- system debug (no emulator required) - provides 4 breakpoints, single stepping package options - 24-pin qfn (4x4 mm), rohs compliant - 24-pin qsop (easy to hand solder), rohs compliant temperature range: ?40 to +85 c
low-voltage/low-power copyright ? 2 009 by silicon laboratories 10.1.2009 silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned her ein are trademarks or registered tr ademarks of their respective holders c8051f912 ultra-low power, hi gh-performance mcu selected electrical specifications (at 25 c) parameter conditions min typ max units supply input voltage two-cell mode one-cell mode dc-dc converter disabled 1.8 ? 3.6 v dc-dc converter enabled 0.9 ? 3.6 v supply current with cpu active vdd = 1.8?3.6 v clock = 24.5 mhz (2% internal precision oscillator) ?160?a/mhz supply current (shutdown) ? (v bat = 1.8 v) sleep mode; bod off ? .010 ? a sleep mode; bod on ? .050 ? a sleep mode; smartclock running ? .300 ? a clock frequency range dc ? 25 mhz wakeup time two-cell mode ? 2 ? s one-cell mode ? 10 ? s analog settling time ? 1.5 ? s internal oscillator frequency precision oscillator 24 24.5 25 mhz low power oscillator 182022mhz a/d converter resolution 12/10 bits throughput rate ? ? 75/300 ksps product family package information: 24-pin qfn mm min typ max a a1 b d d2 e e e2 l l1 aaa bbb ccc ddd 0.70 0.75 0.80 0.00 0.02 0.05 0.18 0.25 0.30 4.00 bsc 2.50 2.60 2.70 0.50 bsc 4.00 bsc 2.50 2.60 2.70 0.35 0.40 0.45 ? ? 0.15 ? ? 0.10 ? ? 0.10 ? ? 0.05 ? ? 0.10 part number package package size (mm) adc fla s h (kb) ram (bytes) rtc sleep (na) bod disableable c8051f912-gm 24p qfn 4x4 12-bit 16 768 300 yes C8051F912-GU 24p qsop 9x6 12-bit 16 768 300 yes c8051f911-gm 24p qfn 4x4 10-bit 16 768 600 no c8051f911-gu 24p qsop 9x6 10-bit 16 768 600 no c8051f902-gm 24p qfn 4x4 12-bit 8 768 300 yes c8051f902-gu 24p qsop 9x6 12-bit 8 768 300 yes c8051f901-gm 24p qfn 4x4 10-bit 8 768 600 no c8051f901-gu 24p qsop 9x6 10-bit 8 768 600 no
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