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kb8527b 1 chip clp subsystem ic kb8527b is a monolithic circuit which can be used in high performance 60mhz mca type clp system. the kb8527b is a subsystem ic for fm / fsk receiving syste- ms and a complete one chip fm / fsk receiver ic for 60mhz system. it`s feature includes receiving functions for fm / fsk systems, a compandor to remove external noise, and pll ( ph- ase lock loop ) of channel selection which blocks surrounding frequency interference. the kb8527b can be used with a wide range of fm / fsk vhf bandwidth systems, including cordless phone, and the narrow band voice and data sending / receiving systems. to make applications easily and simply, pheripheral parts are minimized. features 48 -qfp- 1010e ? operating voltage range : 2.0v ~ 5.5v ? typical supply current : 13.5ma at 3.6v ? built - in low battery detection function ( selectable 3.45v, 3.3v, 3.0v, 2.2v, 2.1v ) ? built - in speaker amplifier ? built - in splatter filter ? built - in dual conversion receiver, compandor and universal pll ? fm receiver - complete dual coversion circuit - excellent input sensitivity (0.7 m vrms at 20db sinad) ? compandor - easy gain control to use external component - included alc (automatic level control) circuit - included mute logic ? universal pll - rx (tx) divided counter range : 1/16 ~ 1/16383 - reference frequency divided counter range : 1/16 ~ 1/4095 - lock detector signal output - serial interface with micom for controlling each block introduction ordering information + : new product
kb8527b 1 chip clp subsystem ic block diagram limiting if amp meter driver carrier detector rectifier gain cell regulator (1v) limiter gain cell rectifier if amp (455khz) 13 14 15 16 17 18 19 21 22 23 quad detector fsk comp alc 37 38 39 40 41 42 43 44 45 46 47 48 rx vco if amp (10.7mhz) 1`st mix regulator ( 2.15 v ) programmable counter ( rx ) programmable counter ( tx ) programmable counter ( ref ) rx phase detector tx phase detector fmcu 4_25 cnt control buffer sum amp pri spk amp sum amp pri amp compandor mute spk amp x-tal osc low battery detector 2`nd mix 35 34 33 32 31 30 29 28 27 26 25 12 11 10 9 8 7 5 4 3 1 2 - + vref + - crc co sfi sfo cdo/ldt gnd (pll) clk data lbd en agic pdt epi erc sai sao1 sao2 vcc (comp) gnd (comp) cpi+ cpi - alc 24 v ref (comp) 2mo vcc (rx) li ld gnd (rx) qci rao dsci dsco mdo 2loi 6 36 2loi gnd (pll) v ref (pll) 2mi 1loi 1loi 1mi tif 1mi 1mo v cc (pll) vco rx pdr 20 eo splatter filter
kb8527b 1 chip clp subsystem ic 1 2 3 4 5 6 7 8 9 10 11 12 epi erc eo sai sao1 sao2 vcc (comp) gnd (comp) cpi+ cpi - crc 2mo vcc (rx) li ld gnd (rx) qci rao dsci dsco mdo v ref(comp) alc kb8527b 14 15 16 17 18 19 20 21 22 23 24 13 47 46 45 44 43 42 41 40 39 38 37 48 36 35 34 33 32 31 30 29 28 27 26 25 co sfi sfo cdo/ldt gnd (pll) clk data lbd en agic gnd (pll) v ref(pll) 2loi 2loi 2mi 1loi 1loi 1mi tif 1mi 1mo v cc(pll) pin configuration pdt vco rx pdr
kb8527b 1 chip clp subsystem ic pin description pin no symbol description 1 co compressor output terminal of compandor ; connected to the splatter filter amp input terminal. 2 pdt phase detector output terminal of the transmitter at pll. if f tx > f ref or f tx is leading the output is negative pulse if f tx < f ref or f tx is lagging the output is positive pulse if f tx = f ref and the same phase the output is high impedance 3 4 5 ldt/ cdo gnd pll ground. ground of logic section at pll. lbd low battery detecting output. ( selectable 3.45v, 3.3v, 3.0v, 2.2v, 2.0v ). during the normal operation, output level is low, but it is high at low battery detection. as this pin is an open collector type, it requires a pull - up resister. these pins are serial interface terminals for programming reference counter, auxiliary reference counter, tx channel counter, rx channel counter and control block that controls internal each block with test mode and power saving mode. clk 7 8 9 data en 10 this pin bypasses ac elements at the feedback loop which come from the sum amp block of compressor. a capacitor should be connected between this ter- minal and gnd. ( c = 2.2 uf ) 11 agic input terminal of splatter filter amp. sfi sfo output terminal of splatter filter amp. ldt : output terminal of transmitter lock detector in pll block. output is low if pll is in lock state and is high if pll is in unlock state. cdo : as an output terminal of the carrier detector buffer, connected to (rssi ) terminal of micom. this pin outputs the contents of meter driver buffer which is turned on / off, according to the signal level detected by meter driver. 6
kb8527b 1 chip clp subsystem ic converts waveform from the full wave rectifier to dc element at the rectifier block of compressor. ( rc = 33 msec ) 12 crc pre - amp inverting input terminal of compressor. adjusts the negative feedback loop gain. ( in application, gain is 5 ) 13 cpi - pin no symbol description pre - amp non - inverting input terminal of compressor. used as an input terminal for voice signals. 14 cpi + output terminal of speaker amp 2. this signal is the same as sao1 output, but phase difference is 180 o for sao1. dc voltage level is ( vcc - 0.7v ) / 2. sao 2 15 gnd (comp) ground. ground of compandor. vcc (comp) 16 supply voltage. power supply terminal of compandor. 17 18 sao 1 output terminal of speaker amp 1. dc voltage level is ( vcc - 0.7v ) / 2. 21 erc converts waveform from the full wave rectifier to dc element at the rectifier block of expander. ( rc = 33 msec ) 22 epi - pre - amp inverting input terminal of expander. adjusts the negative feedback loop gain. ( in application, gain is 5 ) 19 sai speaker amp 1 input terminal. between this terminal and expander output terminal, uses a ac coupled. 20 eo output terminal of expander, from which a regenerated voice signals are emitted. 23 alc reference current input terminal of automatic level control ( alc) ; adjusts thd of compressor output voltage to less than 3 % or limites the frequency deviation of tx if the input is higher than a certain level. the alc circuit may be turned off depending on the alc reference current or the magnitude of output voltage may be limited if it is higher than a certain level. ( iref = 8ua, ralc = 120 k w )
kb8527b 1 chip clp subsystem ic pin no symbol description reference voltage ( v ref = 1v ). supplies a regulator voltage to the compressor and expander of compander. 24 v ref(comp) mdo output terminal of the meter driver. amplitude of rf input signal for useful frequency is detected by meter driver circuit. the meter driver circuit has perfect linear characteristic of 60 db range for input signal level. ( 0.1 m v / db ) 25 26 dsco output terminal of data slicing comparator. seperates frequency shift keying ( fsk ) serial data and executes data shapping and limiting. 27 dsci input terminal of data slicing comparator. non - inverting type with the negative input terminal biased to 1/2 vcc. 29 qci quadrature coil input terminal. the 455 khz oscillator circuit is an lp=680uh, cp=180 pf valued lc tank circuit. voice signals are detected by mixture of 455 khz ( by phase difference ) which is converted from mixer 2. 30 gnd rx ground . ground for receiver. recovered audio output terminal. voice signals detected by the quadrature detector are amplified and then output through this terminal. 28 rao limiter input and decoupling terminal. removes amplitude modulation elements caused by fading or fm signal noise. limiting if amplifies and limits the second intermediate frequency, 455 khz. the input impedance of the limiting if amplifier is set to 1.5 k w . while fm waves are transmitted with constant magnitude, their magnitudes are slightly modulated due to reflection from obstacles, fading phenomenon, noise wave, and mixing with am wave elements before entering the receiver`s antenna. the limiter makes amplitude uniform by removing these am wave elements. 31 32 ld li
kb8527b 1 chip clp subsystem ic pin no symbol description 33 v cc(rx) 2mo 34 output terminal of mixer 2. second intermediate frequency ( 455 khz ), generated by mixing first intermediate frequency ( 10.7 mhz ) and second local oscillator is output. supply voltage. supplies power to the receiver. 37 2mi input terminal of mixer 2. output from mixer 1 is entered to mixer 2 input terminal via 10.7 mhz ceramic filter. second mixer converts frequency to second inter- mediate frequency ( 455 khz : am if ). 38 1mo output terminal of mixer 1. the signal from mixer 1 and the frequency of the first local oscillator are mixed to produce the first intermediate frequency, which is the output through this terminal. the output terminal is an emitter follower with an output impedance of 330 w to match the 330 w input / output impedance of the 10.7 mhz ceramic filter. input terminal of the first local oscillator. the local oscillator is a voltage controlled oscillator. local oscillation frequency and received frequency are mixed at mixer 1 and then conerted to the first intermediate frequency of 10.7 mhz or 10.695 mhz. 39 40 1loi 1loi vco rx the terminal which variable capacitor is included in the chip. used as an input terminal where 1`st local oscillation frequency is changed by varying the capacitor connected between 1`st local oscillator terminals. the internal variable capacitor has the value of 18.73 ~ 15.86 pf depending on the applied voltage. ( 1.0 ~ 2.0 v ) 41 input terminal of second local oscillator. generates second local oscillator frequency to convert output from mixer 1 ( 10.7 mhz ) into second intermediate frequency. it is an oscillator with crystal of 10.24 mhz and 10.245 mhz. 2loi 35 2loi 36 input terminal of mixer 1. this mixer is made of double balanced multiplier. the received signal amplied at rf amp is input to this teminal. 42 1mi 43 1mi 44 gnd (pll) ground. ground for analog at pll.
kb8527b 1 chip clp subsystem ic pin no symbol description pdr phase detector output terminal of the receiver at pll. if f rx > f ref or f rx is leading the output is negative pulse if f rx < f ref or f rx is lagging the output is positive pulse if f rx = f ref and the same phase the output is high impedance 45 v ref(pll) pll voltage reference output pin. an internal voltage regulator provides a stable power supply voltage for the rx and tx plls. 46 v cc(pll) power supply terminal of pll. 47 tif input terminal of tx channel counter. ac coupling with tx vco. minimum input level is 300 mvp-p ( at 60mhz ). 48
kb8527b 1 chip clp subsystem ic absolute maximum ratings current consumption at each mode ( vcc = 3.6v ) current consumption in each block ( vcc = 3.6v ) 600ua modes min. max. inactive mode rx mode communication mode ( active mode ) - typ. 350ua 6.6ma 13.5ma - - - - modes min. max. receiver part expander part speaker part compressor part - typ. 5.0ma 1.4ma 1.7ma 3.0ma 1.6ma 0.8ma - - pll rx part tx part - - - 7.5ma 2.1ma 2.5ma 4.5ma 2.4ma 1.2ma v mw o c o c characteristic symbol unit maximum supply voltage power dissipation operating temperature storage temperature v cc p d t opr t stg value 5.5 600 -20 ~ + 70 - 55 ~ + 150
kb8527b 1 chip clp subsystem ic electrical characteristics receiver ( v cc = 3.6v, f c = 49.7mhz, f dev = + 3khz, f mod = 1khz,ta = 25 o c , unless otherwise specified ) 2.0 5.5 operating voltage characteristic min typ max unit symbol test conditions vcc v - input for -3db sensitivity 0.7 2.0 m vrms input for 20db sensitivity 0.7 2.0 m vrms s/n ratio 48 55 db recovered audio output 145 185 225 mvrms -3db point modulation input modulation input no modulation input rfin = 1mvrms v lim v i(sen) s/n v o(ra) 130 205 noise output level v no -3.3 db mvrms recovered audio output voltage drop -8 - - v o(rad) vcc = 5v 2v rfin = 1mvrms rfin = no input detect output voltage 1.0 1.5 2.0 v v o(det) rfin = 1mvrms - - - carrier detector threshold mv 0.60 0.73 110 150 3.0 0.25 0.5 first mixer conversion voltage gain 0.49 v comparator threshold voltage difference 70 comparator output voltage 1 comparator output voltage 2 2.7 v v - - 14 18 22 17 21 25 second mixer conversion voltage gain db db d v th v oh v ol v th(det) d g v(2m) v comp = 150mvp-p r l = 180 k w rfin = no input v comp = 150mvp-p rl = 180 k w v comp = 150mvp-p r l = 180 k w v i(43) = 1mvrms r l(38) = 330 w v i(37) = 1mvrms r l(34) = 1.5 k w d g v(1m) characteristic min typ max unit symbol test conditions
kb8527b 1 chip clp subsystem ic electrical characteristics (continued) compressor ( vcc = 3.6v, fc = 1khz, ta = 25 o c, unless otherwise specified ) characteristic min typ max unit symbol test conditions detector output resistance r o(det) 1.2 - k w detector output dc voltage change ratio d v o(det) meter drive slope mds 0.15 0.23 v/khz 70 100 135 na/db first mixer input resistance first mixer input capacitance r i(1m) c i(1m) rfin = 1mvrms rfin = 1mvrms fc = 50mhz fc = 50mhz 500 690 7.2 10 pf w 100 250 limiter input sensitivity v i(lim) 10 -22 - 25 m v rms second mixer input sensitivity s v(2m) first mixer 3rd order sensitivity 3rd dbm fc = 455khz, 20db sinad fc = 10.7mhz, 20db sinad 3.45 3.3 3.0 2.2 2.1 v low battery detector lbd - - - - - - -0.15 - 0.1 lbd0 ~ lbd3 = 0 ( default ) only lbd2 = 0 only lbd1 = 0 only lbd3 = 0 lbd0 ~ lbd3 = 1 0.075 - 0.1 detector output distortion thd det 1.5 2.5 % rfin = 1mvrms - am rejection ratio amrr rfin = 1mvrms ~ 10mvrms am mod = 30% 25 35 - db characteristic min typ max unit symbol test conditions v reference voltage v ref 0.9 1.0 1.1 standard output voltage vo(com) 255 300 345 mvrms no signal vinc = 13mvrms 0db db -1.0 0 compressor gain difference d g v1 ( com) d g v2(com) -1.0 -0.5 0 -2.0 db vinc = -20db vinc = -40db m v rms
kb8527b 1 chip clp subsystem ic expander (vcc = 3.6v, fc = 1khz, ta = 25 o c, unless otherwise specified) electrical characteristics (continued) characteristic min typ max unit symbol test conditions compressor output distortion mute attenuation ratio thd com 1.0 0.5 % att mute compressor limiting voltage v lim(com) alc v alc vinc = 0db vinc = 0db vinc = variable i alc = 8ua ( r alc = 120 k w ) 80 1.41 1.65 1.83 vp-p 280 330 60 db 380 mvrms - splatter filter vo(sf) v inc = 13mvrms = 0 db 255 300 345 mvrms db standard output voltage v o(exp) vin e = 30mvrms 0db mvrms expander gain difference d g v1(exp) d g v2(exp) vin e = -10db 104 130 156 d g v3(exp) vin e = -20db vin e = -30db 0.5 1.0 1.5 0 0 0 1.0 2.0 3.0 db db expander output distortion thd exp vin e = 0db 1.0 0.5 % - characteristic min typ max unit symbol test conditions mute attenuation ratio att mute 80 60 db expander maximum output voltage vin e = variable thd = 10% mvrms vin e = 0db v oexp(max) 500 600 - - speaker amp output 1 speaker amp output 2 vo( sa1) v ine = 30mvrms = 0 db v ine = 30mvrms = 0 db 104 104 130 130 156 156 mvrms mvrms vo( sa1)
kb8527b 1 chip clp subsystem ic pll ( vcc = 3.6v, ta = 25 o c, unless otherwise specified ) characteristic min typ max unit symbol test conditions operating current i ccpll vcc = 3.6v 2.0 3.5 ma input current input voltage i ih i il v ih v il vin = vcc vin = 0v 5 -5 0.3 vcc- 0.3 m a m a v v vout = vcc vout = 0v output current i oh i ol 0.3 0.3 ma ma output voltage v oh1 v ol1 v oh2 v ol2 pdt,pdr : io = -0.3ma ( sourcing ) pdt,pdr : io = 0.3ma ( sinking ) ld,f mcu : io = -0.1ma ( sourcing ) ld,f mcu : io = 0.1ma ( sinking ) v v v v vcc- 0.4 vcc- 0.5 0.4 0.5 - - - - - - - - - - - - - - - - - - - - - pll regulator voltage v pllreg - 2.15 1.95 2.25 v
kb8527b 1 chip clp subsystem ic pll program summary ? mcu ( micom ) serial interface ( msb : 1 ? st input ) use clk (pin 7 ), data (pin 8 ) , en (pin 9 ) terminals for program. data and clk terminals are used for loading data to internal shift - register. when en terminal is ` low `, it is possible to program tx-channel counter, rx - channel counter and various control functions of pll. when en terminal is ` high` , program 1`st local oscillator capacitor selection in receiver for u.s.a - 25 ch function. - tx - register, rx-register, control register pmc0 pmc1 14 bit data msb lsb data en - reference - register - receiver -1`st local oscillator internal capacitor selection register & low battery detector voltage register [ clo _ lbd - register ] data en clk msb lsb <1> pmc lbd3 lbd2 lbd1 lbd0 clo5 clo4 clo3 clo2 clo1 clo0 clk en pmc0 pmc1 uk_s1 uk_s0 12 bit data data msb lsb clk
kb8527b 1 chip clp subsystem ic ? programmable counter - rx - counter : setting frequency for rx.vco ( 14 bits --> 1/16 ~ 1/16383 ) [ default_ch. = usa_#21 ( remote ) : 36.075mhz ( div._no = 7215 )] - tx - counter : setting frequency for tx.vco ( 14 bits --> 1/16 ~ 1/16383 ) [ default_ch. = usa_#21 ( remote ) : 49.830mhz ( div._no = 9966 )] < rx. register (16bits) > < tx. register (16 bits) > * program mode control bit name default value 7215 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 pmc0 pmc1 d13 d12 d11 d10 d9 d8 * 0 1 1 1 0 0 bit name default value 7215 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 1 1 1 0 0 bit name default value 9966 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 pmc0 pmc1 d13 d12 d11 d10 d9 d8 * 1 0 0 1 1 0 bit name default value 9966 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 1 1 0 1 1 pmc0 pmc0 pmc1 pmc1 program mode program mode 0 0 0 1 0 1 1 1 control block upll_rx. block upll_ref. block upll_tx. block
kb8527b 1 chip clp subsystem ic - ref - counter : setting reference frequency for phase detector ( 12 bits --> 1/16 ~ 1/4095 ) [ default_divider = 2048, x-tal_osc = 10.240 mhz -->fref = 5khz ] < ref. register (16bits) > -uk_selection < reference frequency selection > bit name default value 2048 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 bit name default value 2048 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 pmc0 pmc1 uk_s1 uk_s0 d11 d10 d9 d8 * 1 0 0 0 ref.freq. selection for united kingdom uk_s0 uk_s1 0 0 1 0 0 1 1 1 fr1 fr2 freftx frefrx fref (a) fref (a) fref/4 (b) fref/4 (b) fref/4 (b) fref/25 (c) fref/25 (c) fref (a) fref/4 (b) fref/4 (b) fref/25 (c) fref (a) fref/4 (b) fref/25 (c) fref/4 (b) - 12 bits reference program divider. 4 25 pd_tx pd_rx ld pdt pdr fref (a) fref 4 (b) fref 25 (c) fr1 fr2 . . . . . . . .
kb8527b 1 chip clp subsystem ic control register (16 bits) ? control program *** test mode & ldt-cdo mode ldt/cdo test1 test2 ldt / cdo remark 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 rx block cdo rx block cdo 4_25cnt block fr2 4_25cnt block fr2 pll block ldt pll block ldt test pll_rx test pll_tx default bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name description function ldt_cdo lbd-bs ldt or cdo select low battery detector battery save rx-bs rx battery save test2 test1 test mode 2 test mode 1 0:normal (cdo) 1:ldt 0:normal (lbd-on) 1:lbd-part power-off 0:normal (rx-on) 1:rx-part power-off * * * function test on each block of upll - - - don`t care don`t care don`t care - bit bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 name description function pmc0 pmc1 program mode control_0 - don`t care pll tx -bs pll_tx battery save co_m compressor mute selection compressor battery save expander mute selection expander battery save co_bs ex_m ex_bs * program latch assign don`t care 0:normal (pll_tx-on) 1:pll_tx power-off 0:normal 1:mute 0: co-on 1: normal ( co-part power-off ) 0:normal 1:mute 0: ex-on 1: normal ( ex-part power-off ) program mode control_1
kb8527b 1 chip clp subsystem ic ? operating internal circuit blocks in each mode ? clo_lbd - register program [ rx - 1`st local oscillation internal cap. for u.s.a - 25ch & low battery detect voltage ] - clo register ( 6 bits ) : receiver 1`st local oscillator internal capacitor selection ***** pmc ( program mode control ) pmc = `high` & en = `high` ---> clo_lbd register program mode operating circuit blocks mode ( state ) active state ( communication mode ) receiving mode inactive state pll regulator / micom i/f ( data, clk, en ) / 2`nd local oscillator / receiver / 1`st local oscillator / rx pll / carrier detector / fsk comparator / low battery detector / tx pll / expander & speaker amp / compressor / splatter filter amp pll regulator / micom i/f ( data, clk, en ) / 2`nd local oscillator / receiver / 1`st local oscillator / rx pll / carrier detector / fsk comparator / low battery detector. pll regulator / micom i/f ( data, clk, en ) bit bit10 (msb) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name default value 0 function pmc clo5 clo4 clo3 clo2 clo1 clo0 1 * * * * * 0 0 0 0 0 0 - 0:normal 1:internal cap. for usa 25 channel =4.4pf 0:normal 1:internal cap. for usa 25 channel =1.0pf 0:normal 1:internal cap. for usa 25 channel =3.6pf 0:normal 1:internal cap. for usa 25 channel =1.2pf 0:normal 1:internal cap. for usa 25 channel =0.6pf 0:normal 1:internal cap. for usa 25 channel =2.4pf
kb8527b 1 chip clp subsystem ic - rx - low battery detect voltage ***** pmc ( program mode control ) pmc = `high` & en = `high` ---> clo - lbd register program mode in case the 12 bits programming, insert 1 don`t care bit ( dummy bit ) between pmc and lbd3. * example 1 > low battery detector voltage : 2.1v u.s.a _ch-#1 ( remote ) ---> 1`st local osc. varicap value =15.86pf, internal cap = 7.0pf ( ext_l = 0.45uh, ext_c = 30pf ) - 12 bit data format data en clk msb lsb pmc lbd3 lbd2 lbd1 lbd0 clo5 clo4 clo3 clo2 clo1 clo0 1 1 1 1 1 0 1 1 1 0 0 1( 0 ) dummy bit bit bit 10 (msb) bit 9 bit 8 bit 7 bit 6 low battery detector voltage remark name pmc lbd3 lbd2 lbd1 lbd0 default value 1 * * * * * 0 0 0 0 - default function 1 0 1 1 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 3.45v 3.3v 3.0v 2.2v 2.1v - - - - -
kb8527b 1 chip clp subsystem ic - in case of setting 16 bit data format data en clk msb lsb pmc lbd3 lbd2 lbd1 lbd0 clo5 clo4 clo3 clo2 clo1 clo0 1 1 1 1 1 0 1 1 1 0 0 1(0) dummy bit 1(0) 1(0) 1(0) 1(0) in case of 16 bits programming, insert 5 don`t care bits between the pmc and lbd3 * example data for u.s.a 25_channel selection 1`st local osc. internal capacitor select bit5 (clo5) bit4 (clo4) bit3 (clo3) bit2 (clo2) bit1 (clo1) bit0 (clo0) base channels hand channels varicap value external c external l internal c 1 ~ 25ch. 1 ~ 25ch. 1.0v ~ 2.0v typ 1.5v 27pf ( 30pf ) 0.45uh pf 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 16 ~ 25ch. - 01 ~ 04ch. 05 ~ 10ch. 11 ~ 15ch - - - 16 ~ 25ch. - - - 01 ~ 06ch. 07 ~ 15ch. 18.73 ~ 15.86pf 18.73 ~ 15.86pf 18.73 ~ 15.86pf 18.73 ~ 15.86pf 18.73 ~ 15.86pf 18.73 ~ 15.86pf 18.73 ~ 15.86pf 27pf 30pf 27pf 27pf 27pf 30pf 30pf 0.45uh 0.45uh 0.45uh 0.45uh 0.45uh 0.45uh 0.45uh - 0.6 1.6 1.2 0.6 7.0 5.8
kb8527b 1 chip clp subsystem ic ? phase detector / lock detector output waveforms ( phase detector / lock detector output waveform ) ref.freq. tif n pdt ld . . 12 bits reference program divider. 4 25 pd_tx ld pdt fref (a) fref 4 (b) fref 25 (c) fr1 fr2 14 bits tx. program divider. 2loi tif ref.freq tif n . . . . . . . . . .

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