rev. 0.1 2/12 copyright ? 2012 by silicon laboratories AN671 AN671 p recision 32? p ort i/o c rossbar d ecoder 1. introduction precision32? devices use one or more port i/o crossbar decoders to assign internal digital signals to port i/o pins. a crossbar decoder prov ides the system desi gner with flexibility to custom ize the pinout according to the needs of the application. the port i/o crossbar decoder is particularly useful in low pin count devices where the number of internal digital signal s outnumber the available i/o pins. the crossbars are fully supported by the silicon labs precision32 sdk, in cluding hardware access layer (hal) routines and code examples showing how to configure a crossbar for a particular peripheral. additionally, the precision32 appbuilder application provides a graphical interface to easily configure pins in a crossbar. figure 1 shows an example of how internal signals are rout ed to the port banks of sim3u1xx devices through the use of two crossbar decoders. port bank 0 (pb0) and port bank 1 (pb1) are connected to crossbar 0, and port bank 2 (pb2) and port bank 3 (pb3 ) are connected to crossbar 1. figure 1. crossbar example on a sim3u167 device 2. relevant documentation precision32 application notes are listed on th e following website: www. silabs.com/32bit-mcu. ?? an664: precision32? cmsis and hal user?s guide ?? an670: getting started wit h the silicon labs pr ecision32? appbuilder sim3u167 80-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pb4.4 pb4.5 vsshd pb4.3 pb4.2 viohd pb4.0 pb4.1 pb3.0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 pb0.11 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vss vio pb1.13 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vbus vss vdd vio d+ d- reset pb0.0 pb0.1 pb0.2 pb0.3 pb0.4 pb0.5 pb0.6 pb0.7 pb0.8 pb0.9 pb0.10 pb0.13 pb0.14 pb0.15 pb1.0 pb1.1 pb1.2/trst pb1.3/tdo/swv pb1.4/tdi pb1.5/etm0 pb1.6/etm1 vio pb1.8/etm3 pb1.9/traceclk pb1.10 pb1.11 pb1.12 pb1.14 pb2.3 pb2.4 pb2.5 pb2.6 pb2.7 pb2.8 pb2.9 pb2.10 pb2.11 pb2.12 pb2.13 pb2.14 pb3.1 pb3.2 pb3.3 pb3.4 pb3.5 pb3.6 pb3.7 pb3.8 pb3.9 pb3.10 pb3.11 swclk/tck swdio/tms pb0.12 pb1.7/etm2 pb1.15 pb2.0 pb2.1 pb2.2 vregin crossbar 0 (pb0 and pb1) crossbar 1 (pb2 and pb3) pb4 independent of the crossbars
AN671 2 rev. 0.1 3. crossbar function the primary function of a crossbar decoder is to route inte rnal digital signals to port bank pins. figure 2 is a block diagram of crossbar 0 on sim3u1xx devices. the inputs to the crossbar are a number of internal digital signals inside the device. the xbar0h, xbar0l, and pbskip register s in the port configurat ion module (pbcfg) define how the internal digital signals are mapped to the i/o pins of pb0 and pb1. figure 2. example routing of internal digital signals to port banks on sim3u1xx devices crossbar 0 digital crossbar 0 priority decoder port match pm pmmsk not all port i/o pins are available on all packages. port i/o cells pb1.0 pb1.15 16 port i/o cells pb0.0 pb0.15 16 xbar0h xbar0l pbskip highest priority lowest priority flow control rx/tx clock usart0 nss sck/miso/mosi spi0 flow control rx/tx clock usart1 epca0 ?n? channels pca0 ?n? channels pca1 ?n? channels epca0 eci pca0 eci i2c0 sda/scl cmp0a cmp0s cmp0 cmp1a cmp1s cmp1 t0ex t0ct timer0 t1ex t1ct timer1 i2s0 tx pca1 eci flow control rx/tx uart0 rx/tx uart1 nss sck/miso/mosi spi1 nss sck/miso/mosi spi2 ahb clock output ( 16)
AN671 rev. 0.1 3 3.1. crossbar f unctionality on reset after a device reset, all crossbars enter a disabled default reset state. port bank pins connected to a disabled crossbar are forced into a high impedance digital input mode. firmware must enable the crossbar associated with a specific port bank pin in order to use that pin as an output. in most applications, firmware will enable all crossbars on the device to control all the available i/o pins on the device. when a crossbar is enabled with no internal signals select ed to be routed to i/o pins, the crossbar provides full general purpose input/output (gpio) access to the port banks associated with it. pins with full gpio access can be used as digital inputs, digital outputs, or may be used by various analog functions on the device. as internal signals are selected to be routed to i/o pins (or ?enabl ed in the crossbar?), the crossbar claims pins from the associated port banks. pins claimed by the crossbar canno t be used as gpio and are under the full control of the crossbar and the associated peripheral. 3.2. skipping pins in the crossbar the crossbars have a pin-skipping feature for pins that mu st be reserved gpio or analog functions. any port bank pin with its corresponding pbskipen bit set to 1 cannot be claimed by the cros sbar and will remain available for gpio or analog functions. the ability to have the crossb ar skip certain pins is usef ul when a system designer is trying to achieve a specific pinout for the device. 3.3. crossbar priority order as internal signals are enabled in a crossbar, the crossbar claims pins from the port banks to connect to the internal signal, starting with the least significant port bank pin and finishing with the most significant port bank pin. as an example, crossbar 0 of sim3u1xx devices would st art with pb0.0, then pb0.1, and continue in this fashion until reaching pb1.15. if the crossbar encounters a pin that has its pbskipe n bit set to 1, it skips over the pin and claims the next available pin. any pin not claimed by the crossbar can be used for gpio or analog functions. the crossbar uses a priority order to assign enabled intern al signals to claimed port bank pins. this priority order varies with the specific crossbar implementation. figu re 3 shows an example priority order from crossbar 0 of sim3u1xx devices. in this example, th ere are four enabled peripherals that require pin assignment: spi0, epca0, uart0, and uart1. from the enabled peripherals, spi0 has t he highest priority, so it will be assigned to the first three pins claimed by the crossbar. note that in this exam ple configuration, firmware configured the first 8 pins of pb0 (pb0.0 - pb0.7) to be skipped by the crossbar; the crossbar will assign the spi0 pins to pb0.8, pb0.9, and pb0.10. following the priority order, the epca0 pins are assigned to pb0.11, pb0.12, pb0.15, pb1.0. the pb1.2. pb0.13 and pb0.14 pins are not assigned to epca0 becaus e they are configured to be skipped by the crossbar. uart0 and uart1 are assigned to the next four avail able pins: pb1.3, pb1.4, pb.15, and pb1.6. the remaining pins (pb1.7?pb1.15) are not claimed by the crossbar. 3.4. creating a fl exible device pinout the definition of a system can sometimes change in the mi ddle of the design cycle, necessitating a pinout change. planning ahead for such changes in pinout can save cost ly pcb revisions and decrease time to market when a system definition change does occur. in the example pin out shown in figure 3, spi0 is used in 3-wire mode. if the communication protocol was changed from 3-wire to 4-wi re mode, then pb0.11 would be used for the nss signal, causing all peripherals of lower priority order to shift by one pin. using the crossbar?s skip functionality, the system designer can plan ahead for such a change by skipping pb0 .11 when the specification calls for 3-wire spi mode. the skipped pin can later be un-skipped if the specification later requires th e use of 4-wire spi without affecting the location of peripherals with a lower pr iority order. if the specification does not change, the skipped pin can be used for gpio (e.g., to control an led or as a debug signal). adding a few skipped pins when determining the original device pinout can allow future functionality to be added with minimal impact on the device pinout.
AN671 4 rev. 0.1 figure 3. example crossbar priority order on sim3u1xx devices (crossbar 0) p0 p1 5 4 6 7 1 0 2 3 13 12 14 15 9 8 10 11 5 4 6 7 1 0 2 3 13 12 14 15 9 8 10 11 signal name peripheral usart0_tx usart0 usart0_rx usart0_rts usart0_cts usart0_uclk spi0_sck spi0 spi0_miso spi0_mosi spi0_nss usart1_tx usart1 usart1_rx usart1_rts usart1_cts usart1_uclk epca0_cex0 epca0 epca0_cex1 epca0_cex2 epca0_cex3 epca0_cex4 epca0_cex5 pca0_cex0 pca0 pca0_cex1 pca1_cex0 pca1 pca1_cex1 epca0_eci epca0 eci pca0_eci pca0 eci pca1_eci pca1 eci i2s0_tx_ws i2s0 tx i2s0_tx_sck i2s0_tx_sd i2c0_sda i2c0 i2c0_scl cmp0s cmp0 cmp0a cmp1s cmp1 cmp1a timer0_ct timer0 timer0_ex timer1_ct timer1 timer1_ex uart0_tx uart0 uart0_rx uart0_rts uart0_cts uart1_tx uart1 uart1_rx spi1_sck spi1 spi1_miso spi1_mosi spi1_nss spi2_sck spi2 spi2_miso spi2_mosi spi2_nss ahb_out ahb clock / 16 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pbskipen
AN671 rev. 0.1 5 4. configuring the crossbar and port i/o in firmware the precision32 appbuilder application provides a graphical interface to easily configure pins in the crossbars. this software uses the hardware acce ss layer (hal), a part of the silicon labs sdk pa ckage that enables rapid development on sim3xxxx devices. the crossbars and po rt banks on sim3xxxx devices are part of the pbcfg and pbstd modules. the following steps show an example of how to initialize the crossbars and pins on sim3u1xx devices to achieve the pinout shown in figure 3 using the silicon labs hal: 1. enable the apb clo ck to the i/o modules: 2. configure pins to be skipped by the crossbars an d enable signals in the crossbars. a full list of signal names that may be enabled in the crossbars ca n be found in a file named si32_pbcfg_a_support.h. 3. configure the functional and output mode of each pin: 4. enable the crossbar or crossbars:
AN671 6 rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.
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