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| ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?d n b y 2 1 4 5 0 n b y 2 1 4 6 ? ?? ? r 2 5 ??( o yk t ) b e d * g , 6 w]?? ? t h i 2 2 6 l t q t ? a|k ????0 - t q j u n 0 r t q j u n 0 n j d s p x j s f u n 0? |r { > 3 / 8 w? 6 / 3 6 w; { ] ? y+ - s ??? ]? 2 / 4 n b )?o? *r] ? y+ - s?? ? ]? 2 b )?o? * n b y 2 1 4 5 9 5 )] * t 5 5 )^? j * y r?0x n b y 2 1 4 6 ?? 5 5 )] * t 3 5 )^? j * y r?0x ? y r?0x -0 -? h? a ??? 8?] r? *? ) 1? , w s f g 0 3 . w s f g 0 3? 1 1? , w s f g . w s f g ? 1 w s f g 0 5 w s f g 0 3 [ w s f g * [ 4?? jr? *? ) w s f g 0 3 w s f g [ 3 y w s f g * ? , 5 / 1 : 7 w ?e -#c # ?| b e d ? 1? n b y 2 1 4 5 0 n b y 2 1 4 6 - {j 4 / 9 1 1 w? 5 / 2 4 7 w? .|j] ?e n b y 2 1 4 5g 3 5[ m u t t p q v? n b y 2 1 4 6g 3 1[ m u t t p q v? ? r h - ?+? . 5 1 d? , 9 6 dt * ? ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `b ? <?; k ?g ; k 9? ?} c ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `v ? ? 0x|r? *? -0 -? h ?? ? ]r? *? 1? , w s f g 0 3 . w s f g 0 3? 1 1? , w s f g . w s f g ? 1 w s f g 0 5 w s f g 0 3 [ w s f g ? ? jr? *? w s f g 0 3 w s f g [ 3 ! y ! w s f g ? 9 5] t 5 5? j y r? ) n b y 2 1 4 5 * ? 5 5] t 3 5? j y r? ) n b y 2 1 4 6 * ? 7 w -1?"r? ? ] tj] ?e ? 2 2 6 l t q t" g h ? , 6 w]?? ? ? 3 1 0 3 5[ m u t t p q v? n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ________________________________________________________________ maxim integrated products 1 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `[ m|? 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 agnd1 agnd2 av dd2 agnd3 ch2 ch1 ch0 av dd1 top view ref refcap dv dd dv ddo ch6 ch5 ch4 ch3 16 15 14 13 9 10 11 12 dgnd dgndo dout sclk sstrb din cs ch7 tssop MAX1034 19-3574; rev 1; 12/06 t q j [ r t q j5 n p u p s p m b - ! j o d /|* n j d s p x j s f5 o b u j p o b m ! t f n j d p o e v d u p s ! d p s q /|* [ m|? )? *?k ?t ?|" ? ta5 n b y j nu+^at ?|ia n b y j ny !i|@?|?j t?%? |g ? ??@ia| -@?a ? t !ig??i?? \$?|eiv?l n b y j n |^at ? ?s ? e- ["d|k ?t ?? 7 n b y j n|? x x x / n b y j n . j d / d p n / d o ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `? g? part pin- package channels pkg code MAX1034 eug* 24 tssop 8 u24-1 max1035 eup 20 tssop 4 u20-2 * ? v?- g?? ?? ?? h ?+? . 5 1 d? , 9 6 dt *? n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd1 to agnd1 ....................................................-0.3v to +6v av dd2 to agnd2 ....................................................-0.3v to +6v dv dd to dgnd ........................................................-0.3v to +6v dv ddo to dgndo ..................................................-0.3v to +6v dv dd to dv ddo ......................................................-0.3v to +6v dv dd , dv ddo to av dd1 ........................................-0.3v to +6v av dd1 , dv dd , dv ddo to av dd2 ..........................-0.3v to +6v dgnd, dgndo, agnd3, agnd2 to agnd1 ......-0.3v to +0.3v cs , sclk, din, dout, sstrb to dgndo ............................................-0.3v to (dv ddo + 0.3v) ch0Cch7 to agnd1 ...................................................-6v to +6v ref, refcap to agnd1.......................-0.3v to (av dd1 + 0.3v) continuous current (any pin) ...........................................50ma continuous power dissipation (t a = +70c) 20-pin tssop (derate 11mw/c above +70c) ..........879mw 24-pin tssop (derate 12.2mw/c above +70c) .......976mw operating temperature range ...........................-40c to +85c junction temperature .....................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units dc accuracy (notes 1, 2) resolution 14 bits integral nonlinearity inl 0.25 1 lsb differential nonlinearity dnl no missing codes 1 lsb 0.5 transition noise external or internal reference 2 lsb rms unipolar 0 10 single-ended inputs bipolar -1.0 10 unipolar 0 20 offset error differential inputs (note 3) bipolar -2 20 mv channel-to-channel gain matching unipolar or bipolar 0.025 %fsr channel-to-channel offset error matching unipolar or bipolar 1.0 mv unipolar 10 offset temperature coefficient bipolar 5 ppm/c unipolar 0.5 gain error bipolar 0.3 %fsr unipolar 1.5 gain temperature coefficient bipolar 1.0 ppm/c unipolar endpoint overlap negative unipolar full scale to positive unipolar zero-scale 0 5 lsb n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units dynamic specifications f in(sine-wave) = 5khz, v in = fsr - 0.05db, f sample = 130ksps (notes 1, 2) differential inputs, fsr = 2 x v ref 84.5 single-ended inputs, fsr = v ref 84 single-ended inputs, fsr = v ref / 2 82.5 signal-to-noise plus distortion sinad single-ended inputs, fsr = v ref / 4 79 80.5 db differential inputs, fsr = 2 x v ref 84.5 single-ended inputs, fsr = v ref 84 single-ended inputs, fsr = v ref / 2 82.5 signal-to-noise ratio snr single-ended inputs, fsr = v ref / 4 80.5 db total harmonic distortion (up to the 5th harmonic) thd -98 db spurious-free dynamic range sfdr 92 99 db aperture delay t ad figure 21 15 ns aperture jitter t aj figure 21 100 ps channel-to-channel isolation 105 db conversion rate external clock mode, figure 2 114 external acquisition mode, figure 3 84 byte-wide throughput rate f sample internal clock mode, figure 4 106 ksps analog inputs (ch0Cch3 max1035, ch0Cch7 MAX1034, agnd1) small-signal bandwidth all input ranges, v in = 100mv p-p (note 2) 2 mhz full-power bandwidth all input ranges, v in = 4v p-p (note 2) 700 khz r[2:1] = 001 -v ref /4 +v ref /4 r[2:1] = 010 -v ref /2 0 r[2:1] = 011 0 +v ref /2 r[2:1] = 100 -v ref /2 +v ref /2 r[2:1] = 101 -v ref 0 r[2:1] = 110 0 +v ref input voltage range (table 6) v ch_ r[2:1] = 111 -v ref +v ref v true-differential analog common-mode voltage range v cmdr dif/ sgl = 1 (note 4) -4.75 +5.50 v common-mode rejection ratio cmrr dif/ sgl = 1, input voltage range = v ref /4 75 db input current i ch_ -v ref < v ch_ < +v ref -1500 +650 a input capacitance c ch_ 5pf input resistance r ch_ 6k electrical characteristics (continued) (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units internal reference (bypass refcap with 0.1f to agnd1 and ref with 1.0f to agnd1) reference output voltage v ref 4.056 4.096 4.136 v reference temperature coefficient tc ref 30 ppm/c ref shorted to agnd1 10 reference short-circuit current i refsc ref shorted to av dd -1 ma reference load regulation i ref = 0 to 0.5ma 0.1 10 mv external reference (refcap = av dd ) reference input voltage range v ref 3.800 4.136 v refcap buffer disable threshold v rcth (note 5) av dd1 - 0.4 av dd1 - 0.1 v v ref = +4.096v, external clock mode, external acquisition mode, internal clock mode, or partial power-down mode 90 200 reference input current i ref v ref = +4.096v, full power-down mode 0.1 10 a external clock mode, external acquisition mode, internal clock mode, or partial power-down mode 20 45 reference input resistance r ref full power-down mode 40 k digital inputs (din, sclk, cs ) input high voltage v ih 0.7 x dv ddo v input low voltage v il 0.3 x dv ddo v input hysteresis v hyst 0.2 v input leakage current i in v in = 0 to dv ddo -10 +10 a input capacitance c in 10 pf digital outputs (dout, sstrb) dv ddo = 4.75v, i sink = 10ma 0.4 output low voltage v ol dv ddo = 2.7v, i sink = 5ma 0.4 v output high voltage v oh i source = 0.5ma dv ddo - 0.4 v dout tri-state leakage current i ddo cs = dv ddo -10 +10 a power requirements (av dd1 and agnd1, av dd2 and agnd2, dv dd and dgnd, dv ddo and dgndo) analog supply voltage av dd1 4.75 5.25 v digital supply voltage dv dd 4.75 5.25 v electrical characteristics (continued) (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units preamplifier supply voltage av dd2 4.75 5.25 v digital i/o supply voltage dv ddo 2.70 5.25 v internal reference 3 3.5 av dd1 supply current i avdd1 external clock mode, external acquisition mode, or internal clock mode external reference 2.5 3 ma dv dd supply current i dvdd external clock mode, external acquisition mode, or internal clock mode 0.9 2 ma av dd2 supply current i avdd2 external clock mode, external acquisition mode, or internal clock mode 17.5 25 ma dv ddo supply current i dvddo external clock mode, external acquisition mode, or internal clock mode 0.2 1 ma partial power-down mode 1.3 ma total supply current full power-down mode 1 a power-supply rejection ratio psrr all analog input ranges 0.125 lsb timing characteristics (figures 15 and 16) external clock mode 272 62 external acquisition mode 228 62 sclk period t cp internal clock mode 100 83 s external clock mode 109 external acquisition mode 92 sclk high pulse width (note 6) t ch internal clock mode 40 ns external clock mode 109 external acquisition mode 92 sclk low pulse width (note 6) t cl internal clock mode 40 ns din to sclk setup t ds 40 ns din to sclk hold t dh 0ns sclk fall to dout valid t do 40 ns cs fall to dout enable t dv 40 ns cs rise to dout disable t tr 40 ns cs fall to sclk rise setup t css 40 ns cs high minimum pulse width t cspw 40 ns sclk fall to cs rise hold t csh 0ns sstrb rise to cs fall setup (note 4) 40 ns dout rise/fall time c l = 50pf 10 ns sstrb rise/fall time c l = 50pf 10 ns electrical characteristics (continued) (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 6 _______________________________________________________________________________________ analog supply current vs. analog supply voltage MAX1034/35 toc01 av dd1 (v) i avdd1 (ma) 5.15 5.05 4.95 4.85 2.35 2.40 2.45 2.50 2.55 2.60 2.30 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode preamplifier supply current vs. preamplifier supply voltage MAX1034/35 toc02 av dd2 (v) i avdd2 (ma) 5.15 5.05 4.85 4.95 16 17 18 19 20 21 22 23 24 15 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode digital supply current vs. digital supply voltage MAX1034/35 toc03 dv dd (v) i dvdd (ma) 5.15 5.05 4.95 4.85 0.70 0.75 0.80 0.85 0.90 0.65 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `?o ?+v (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) note 1: parameter tested at av dd1 = av dd2 = dv dd = dv ddo = 5v. note 2: see definitions in the parameter definitions section at the end of the data sheet. note 3: guaranteed by correlation with single-ended measurements. note 4: not production tested. guaranteed by design. note 5: to ensure external reference operation, v refcap must exceed (av dd1 - 0.1v). to ensure internal reference operation, v refcap must be below (av dd1 - 0.4v). bypassing refcap with a 0.1f or larger capacitor to agnd1 sets v refcap 4.096v. the tran- sition point between internal reference mode and external reference mode lies between the refcap buffer disable threshold minimum and maximum values (figures 17 and 18). note 6: the sclk duty cycle can vary between 40% and 60%, as long as the t cl and t ch timing requirements are met. electrical characteristics (continued) (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d _______________________________________________________________________________________ 7 digital i/o supply current vs. digital i/o supply voltage MAX1034/35 toc04 dv ddo (v) i dvddo (ma) 5.15 5.05 4.85 4.95 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.10 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c external clock mode analog supply current vs. analog supply voltage MAX1034/35 toc05 av dd1 (v) i avdd1 (ma) 5.15 5.05 4.95 4.85 0.47 0.49 0.51 0.53 0.55 0.45 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c partial power-down mode preamplifier supply current vs. preamplifier supply voltage MAX1034/35 toc06 av dd2 (v) i avdd2 (ma) 5.15 5.05 4.95 4.85 0.12 0.14 0.16 0.18 0.20 0.10 4.75 5.25 t a = +85 c t a = +25 c t a = -40 c partial power-down mode digital supply current vs. digital supply voltage MAX1034/35 toc07 dv dd (v) i dvdd ( m a) 5.15 4.85 5.05 4.95 0.122 0.124 0.126 0.128 0.130 0.132 0.134 0.136 0.120 4.75 5.25 partial power-down mode t a = +85 c t a = +25 c t a = -40 c ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 8 _______________________________________________________________________________________ analog supply current vs. conversion rate MAX1034/35 toc08 conversion rate (ksps) i avdd1 (ma) 200 150 100 50 0.5 1.0 1.5 2.0 2.5 3.0 0 0 external clock mode partial power-down mode full power-down mode preamplifier supply current vs. conversion rate MAX1034/35 toc09 i avdd2 (ma) 5 10 15 20 25 0 conversion rate (ksps) 200 150 100 50 0 f clk = 7.5mhz (note 6) external clock mode full power-down mode, partial power-down mode digital supply current vs. conversion rate MAX1034/35 toc10 i dvdd (ma) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0 conversion rate (ksps) 200 150 100 50 f clk = 7.5mhz (note 6) full power-down mode external clock mode, partial power-down mode digital i/o supply current vs. conversion rate MAX1034/35 toc11 conversion rate (ksps) i dvddo (ma) 200 150 100 50 0.1 0.2 0.3 0.4 0.5 0.6 0 0 f clk = 7.5mhz (note 6) external clock mode full power-down mode, partial power-down mode note 6: for partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples. partial power-down or full power-down modes were entered thereafter. by using this method, the conversion rate was found by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down or full power-down modes. ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d _______________________________________________________________________________________ 9 external reference input current vs. external reference input voltage MAX1034/35 toc12 external reference voltage (v) external reference current (ma) 4.10 4.05 4.00 3.95 3.90 3.85 0.13 0.14 0.15 0.16 0.12 3.80 4.15 all modes -0.10 -0.04 -0.06 -0.08 -0.02 0 0.02 0.04 0.06 0.08 0.10 -40 10 -15 35 60 85 gain drift vs. temperature MAX1034/35 toc13 temperature ( c) gain drift (%) +v ref /2 bipolar v ref bipolar range v ref /4 bipolar -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 -40 10 -15 35 60 85 offset drift vs. temperature MAX1034/35 toc14 temperature ( c) offset error (mv) +v ref /4 bipolar range v ref bipolar channel-to-channel isolation vs. input frequency MAX1034/35 toc15 frequency ( khz ) isolation (db) 1000 100 10 -100 -80 -60 -40 -20 0 -120 1 10,000 f sample = 115ksps v ref bipolar range ch0 to ch2 common-mode rejection ratio vs. frequency MAX1034/35 toc16 frequency (khz) cmrr (db) 1000 100 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 1 10,000 f sample = 115ksps v ref bipolar range 1.0 0.5 0 -0.5 -1.0 0 8192 4096 12,288 16,383 integral nonlinearity vs. digital output code MAX1034/35 toc17 digital output code inl (lsb) f sample = 115ksps v ref bipolar range 1.0 0.5 0 -0.5 -1.0 0 8192 4096 12,288 16,383 differential nonlinearity vs. digital output code MAX1034/35 toc18 digital output code dnl (lsb) f sample = 115ksps v ref bipolar range -140 -100 -120 -60 -80 -20 -40 0 02030 10 40 50 fft at 5khz MAX1034/35 toc19 frequency (khz) magnitude (db) f sample = 115ksps f in(sine wave) = 5khz v ref bipolar range ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 10 ______________________________________________________________________________________ snr, sinad, enob vs. analog input frequency MAX1034/35 toc20 frequency (khz) snr, sinad (db) 100 10 10 20 30 40 50 60 70 80 90 100 0 1 1000 enob (bits) 7 8 9 10 11 12 13 14 15 16 6 f sample = 115ksps v ref bipolar range snr sinad enob ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) snr, sinad, enob vs. sample rate MAX1034/35 toc21 sample rate (ksps) snr, sinad (db) 100 10 1 20 40 60 80 100 0 0.1 1000 enob snr, sinad f in(sine wave) = 5khz v ref bipolar range 10 11 12 13 14 9 enob (bits) -sfdr, thd vs. sample rate MAX1034/35 toc22 sample rate (ksps) -sfdr, thd (db) 100 10 1 -100 -80 -60 -40 -20 0 -120 0.1 1000 f in(sine wave) = 5khz v ref bipolar range thd -sfdr -sfdr, thd vs. analog input frequency MAX1034/35 toc23 frequency (khz) -sfdr, thd (db) 100 10 -100 -80 -60 -40 -20 0 -120 1 1000 f sample = 115ksps v ref bipolar range thd -sfdr analog input current vs. analog input voltage MAX1034/35 toc24 analog input voltage (v) analog input current (ma) 4 2 0 -2 -4 -0.5 -1.0 0 0.5 1.0 1.5 -1.5 -6 6 all modes n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 11 small-signal bandwidth MAX1034/35 toc25 frequency (khz) attenuation (db) 1000 100 10 -25 -20 -15 -10 -5 0 -30 1 10,000 reference voltage vs. time MAX1034/35 toc27 1v/div 0v 4ms/div ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+v )? * (av dd1 = av dd2 = dv dd = dv ddo = 5v, agnd1 = dgnd = dgndo = agnd2 = agnd3 = 0, f clk = 3.5mhz (50% duty cycle), external clock mode, v ref = 4.096v (external reference operation), refcap = av dd1 , maximum single-ended bipolar input range (v ref ), c dout = 50pf, c sstrb = 50pf, unless otherwise noted.) full-power bandwidth MAX1034/35 toc26 frequency (khz) attenuation (db) 1000 100 10 -50 -40 -30 -20 -10 0 -60 1 10,000 0 10,000 5000 20,000 15,000 35,000 30,000 25,000 40,000 8191 8190 8192 8193 8194 8195 noise histogram (code edge) MAX1034/35 toc28 code number of hits 65,534 samples 0 10,000 30,000 20,000 60,000 50,000 40,000 70,000 8191 8190 8192 8193 8194 noise histogram (code center) MAX1034/35 toc29 code number of hits 65,534 samples n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 12 ______________________________________________________________________________________ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `[ m? MAX1034 max1035 12av dd1 2 3 ch0 3 4 ch1 4 5 ch2 5 6 ch3 6 ch4 7 ch5 8 ch6 9 ch7 10 7 cs 11 8 din 12 9 sstrb 13 10 sclk 14 11 dout 15 12 dgndo 16 13 dgnd 17 14 dv ddo 18 15 dv dd 19 16 refcap 20 17 ref [ m a ? y ??1 2 s b w e e 2 , 5 / 8 6 w? , 6 / 3 6 w???1$ ' 1 / 2 g?? s b w e e 2 l 5 u b h o e 2 y r?0x 1 y r?0x 2 y r?0x 3 y r?0x 4 y r?0x 5 y r?0x 6 y r?0x 7 y r?0x 8 ??i?r?i cs ?? k ?? t d m l|? ?? e j o4[$? h4 i cs ?? k ?? t d m l| ]?- e p v u4[ri cs ? s ? r t d m l [ e j o|?$ ? e p v u ? ? rk ?r?i cs ?? k ?? t d m l|? ?4[$? hi cs ? s ? r e j o |?$ ? t ??,ig] ? t t u s c|? ?-,?- hs|k ?/ 3e? q i ?+?j] ? y+ t t u s c*????3y y cs ? \? t t u s cy ? ? rp%?' ?| j 0 p# r ?r?i cs ?? t d m l sk ?4[$? e j o [$ e p v ui cs ? s ? r t d m l ?$ ? rk ?ri cs ?? k ?? t d m l| ? ]?4[$ e p v ui cs ? e p v u ? ? k j 0 p? e h o e e h o e p b h o e 4 b h o e 3 [ b h o e 2? u? k ? e h o e e h o e p b h o e 4 b h o e 3 [ b h o e 2? ?? k j 0 p???1r? s e w e e p , 3 / 8 w? , 6 / 3 6 w???1$ ' 1 / 2 g?? s e w e e p l 5? e h o e p k ???1r? s e w e e , 5 / 8 6 w? , 6 / 3 6 w???1$ ' 1 / 2 g?? s e w e e l 5 ? e h o e r?1l 5 ??gj] ?e s s f g d b q b w e e $ g] ?e 1 / 1 2 g?? s s f g d b ql 5u b h o e 2 ) w s f g d b q 5 / 1 : 7 w * ?e |r 0 b e d ?er?gj] ?e b s f g 4 / 9 1 1 wu 5 / 2 4 7 w|j] ?e ?1g] ?e 0 - 2 g?? s s f gl 5u b h o e 2@& w s f g = 5 / 1 : 7 w 2 % ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` .? n b y 2 1 4 5 0 n b y 2 1 4 6? ?? ? r 2 5??( o b e dg , 6 w]?? ?@ ??? a|k ???? [ 3 / 8 w? 6 / 3 6 w; {z y r 2 5? b e dr?}] []? jr?|]g? ) u 0 i *? 5 ?r]g s t ?i y r??1 *?-???2| . w s f g u ???2?| , w s f g ??|"m? jr??1 *?? . 3 y w s f g u , 3 y w s f g k ?t -0 -? h #? ?0x|? [k ?g b? ) d * j?50 - t q j 0 r t q j 0 n j d s p x j s f 0?|r { > <?t n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 13 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` [ m? )? * MAX1034 max1035 21 18 agnd3 22 19 av dd2 23 20 agnd2 24 1 agnd1 4C20ma plc acceleration pressure temperature wheatestone wheatestone 1 f 0.1 f agnd2 dgndo agnd3 dgnd av dd2 dv dd av dd1 0.1 f 0.1 f 0.1 f 5.0v 5.0v 5.0v MAX1034 cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 ref agnd1 refcap 0.1 f 3.3v mc68hcxx c dv ddo sclk cs din sstrb dout v dd sck i/o mosi i/o miso v ss d 2 / ! ?ob? 5 [ m a ? y g s? 4 b h o e 45 b e d| ? ?e?? s b h o e 4 b h o e 2$ e h o e e h o e p b h o e 4 b h o e 3 [ b h o e 2? ?? y ???1 3 s b w e e 3 , 5 / 8 6 w? , 6 / 3 6 w???1$ 0 - 1 / 2 g?? s b w e e 3 l 5 u b h o e 3 y ? 3- ? y ? -|? m? b h o e 2? 6? e h o e e h o e p b h o e 4 b h o e 3 [ b h o e 2? {?? y ? 2 e h o e e h o e p b h o e 4 b h o e 3 [ b h o e 2? {?? n b y 2 1 4 5 0 n b y 2 1 4 6 n b y 2 1 4 5 ?? 9 5] y r?0x t 5 5? j0x ) e tk ?t ?" ?] j | 1 vd * n b y 2 1 4 6 ?? 5 5 ] y r?0x t 3 5? j0x ? y r?0 x ? -0 -? h? a ??? 8?]r? *? ) 1? , w s f g 0 3 . w s f g 0 3? 1 1? , w s f g . w s f g ? 1 w s f g 0 5 w s f g 0 3 [ w s f g * [ 4?? jr? *? ) w s f g 0 3 w s f g [ 3 y w s f g *%j?? y r?0x ? ?? 7 w g? " 90x| g?y l00x|t ? + ?? ?' ?+ 1?? n b y 2 1 4 5 [ n b y 2 1 4 6?? 5 | ?] j ? a|??- 2?,? 5 ? a?? g? a| b w e e 2 b w e e 3 e w e e [ e w e e p ?? ? - y{" v ?* 5? - # h|? ? s b w e e 2 b w e e 3 [ e w e e {u?2 1#?? {4 ? - # h|?? s b h o e 2 b h o e 3 b h o e 4 e h o e [ e h o e p {?? j0' 1 / 2 g ?? s ? ???l 5u b| {?? )- 2 * ? + wm|?? b 2 1 g?? 1 / 2 gl 5??@ t ?+ n b y 2 1 4 5 0 n b y 2 1 4 6 b e dg]? j?( @ ) t b s *t c@ ? u 0 i y m - s?1g st ? 2 5?k ? + h}] [? jr? ? @ - ??] ?v [w ?vg s *? g?? 5 n b y 2 1 4 5 0 n b y 2 1 4 6 ?? ?? u 0 i & ?? y r ?g s2? w|p+@?g??? ? ?+ y+ | u 0 i ? [g .?d 3d 4 [d 5?, n b y 2 1 4 5 0 n b y 2 1 4 6| y r?? 5s??|r?g s ?r ? |' y r?? [r??1?#v )d 6 * 9 0 50x w s f g ? ?r? r 2 5? b e d 14 ______________________________________________________________________________________ - 2 / ! n b y 2 1 4 5 0 n b y 2 1 4 6??l 5 power supply/ground supply voltage range (v) typical supply current (ma) circuit section bypassing dv ddo /dgndo 2.7 to 5.25 0.2 digital i/o 0.1f to dgndo av dd2 /agnd2 4.75 to 5.25 17.5 analog circuitry 0.1f to agnd2 av dd1 /agnd1 4.75 to 5.25 3.0 analog circuitry 0.1f to agnd1 dv dd /dgnd 4.75 to 5.25 0.9 digital control logic and memory 0.1f to dgnd - 3 / ! y r?|? ? bit number name description 7 start start bit. the first logic 1 after cs goes low defines the beginning of the analog input configuration byte. 6c2 5c1 4c0 channel-select bits. sel[2:0] select the analog input channel to be configured (tables 4 and 5). 3 dif/ sgl differential or single-ended configuration bit. dif/ sgl = 0 configures the selected analog input channel for single-ended operation. dif/ sgl = 1 configures the channel for differential operation. in single-ended mode, input voltages are measured between the selected input channel and agnd1, as shown in table 4. in differential mode, the input voltages are measured between two input channels, as shown in table 5. be aware that changing dif/ sgl adjusts the fsr, as shown in table 6. 2r2 1r1 0r0 input-range-select bits. r[2:0] select the input voltage range, as shown in table 6 and figure 7. y r?? 5 0 -v$b| y r?|? ? )- 3 * - s y r?]? |??? j t]t 1+ y r?g s?? ? q? b e d| 7 l r? )d 7 * d 7 ? < ?| y r?? 5 y r? ?? 7 w g ?"@0 -6 ? ? ?g [ ???1 w t k 50xr? a y?1| =k? z v?s r??1 *? y r? $ q??d 6?, ]t ]2 b h o e 2+?l ? )- 4 [- 5 *?? j y + j o , [ j o . ? ?- 4 [- 6 ?r? ??? j0x ? j ?mu0x| y |? ? v?? ?? s d i 3 [ d i 4|?? ?? w s f g |? jt r? b s d i 3| y |? ???? ?? w s f g |? jt 1+ ) 2 1 2 1 2 2 1 1 *?? d i 3 [ d i 4? j t ? ? 2 1 2 1 1 1 1 1 y r?r q n b y 2 1 4 5 0 n b y 2 1 4 6r?g? 5 ?? 2 / 6 n i {cg sr q 2 / 6 n i {r?r q' ? e h ?k ? ~$ g s? ?o ?+v || . t g e s - ! u i e ! w t / ! b o b m p h ! j o q v u g s f r v f o d zn#?,i?k ?|g s? h - 2 6 l i { uf^ s y r? *? [ g?" ?d 8?, -0 -? h? ?? ?ik r|] y r??1 *? e j g 0 sgl = 1 ? y r? 0x ? -0 -?? s \ 3 ; 1 ^ <??? a ? 8?]r? *?? v r rr v r rr v sj cm . = + ? ? ? ? ? ? ++ + ? ? ? ? ? ? ? ? ? ? ? ? 1 12 2 375 1 1 12 n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d cs sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 din s c2 c1 c0 0 0 0 0 analog input track and hold* dout b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 x x byte 1 byte 2 byte 3 byte 4 sstrb hold track hold high impedance t acq *track and hold timing is controlled by sclk. f sample f sclk / 32 sampling instant high impedance d 3 / ! j] ? y+ ) y+ 1 * ______________________________________________________________________________________ 15 n b y 2 1 4 5 0 n b y 2 1 4 6 d 9? ? -? h? |? j y r??1 *?@ ? ? ?ik r? e j g 0 sgl = 2 ? y r? ? j ?0 -?? s \ 3 ; 1 ^ <??? a ? 4?? j r? *?? ? y???|r??1 *?5?2 0x5 e?? ? y r? ?? 7 w g?" &? y h 5 e?? y r? g? ? ??i ? g t s|? \?1?? 7 w g?" *?? u y r?0x ? s? x ?r?1 ? + e? ? | ??1 ?" - 7 w -? f t e [~ ? ?= z? ? n b y 2 1 4 5 0 n b y 2 1 4 6| y r? )d 7 * hu? ?+ e? ? y t0y ?~? ?"?? i ?+ 1 ???| ??1 [ 0 t? ~$ ?-j] n b y 2 1 4 5 0 n b y 2 1 4 6 ? ? 9 0 50x w s f g ? ?r? r 2 5? b e d 16 ______________________________________________________________________________________ cs sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 din sc2c1c00000 analog input track and hold* hold dout b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 x x byte 1 byte 2 byte 3 byte 4 sstrb intclk** 1 2 3 14 15 16 17 track hold t acq 100ns to 400ns f intclk 4.5mhz f sample f sclk / 32 + f intclk / 17 *track and hold timing is controlled by sclk. **intclk is an internal signal and is not accessible to the user. sampling instant high impedance d 4 / ! j]g y+ ) y+ 2 * d 7 / ! < ?| y r?? 5 MAX1034 max1035 r2 r1 v sj *r source analog signal source r2 r1 v sj *r source analog signal source in_+ in_+ *minimize r source to avoid gain error and distortion. n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 17 cs sclk 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 din s c2 c1 c0 0 0 0 0 analog input track and hold* track dout b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 x x byte 1 byte 2 byte 3 sstrb intclk** 1 2 3 25 26 27 28 9 10 11 12 13 14 15 16 10 11 12 13 14 hold hold t acq 100ns to 400ns f intclk 4.5mhz f sample f sclk / 24 + f intclk / 28 *track and hold timing is controlled by intclk, and is not accessible to the user. **intclk is an internal signal and is not accessible to the user. sampling instant high impedance d 5 / ! ] ? y+ ) y+ 3 * analog input voltage (v) analog input current (ma) 4 2 0 -2 -4 -0.5 -1.0 0 0.5 1.0 1.5 -1.5 -6 6 d 6 / ! y r?? r??1| n b y 2 1 4 5 0 n b y 2 1 4 6 ? j a y *? n b y 2 1 4 5 0 n b y 2 1 4 6|? j a y *? ) w d n e s *??? . 5 / 8 6 w? , 6 / 6 w22{u?i|t ? +? j a y *??c?? ? a yr??1 *?|"?j ? ? a| y r? $? b h o e 2 ?"?? 7 w? y r?|? ?|| ? *?? ? s \ 3 ; 1 ^ ? ?$b 0x| x ? *? )- 3 [- 7? d :d 2 1 [d 2 2 ? n b y 2 1 4 5 0 n b y 2 1 4 6 ?+? g t s = w s f g 0 3 g t s = w s f g [ g t s = 3 y w s f g j0b|?i y r??1 *?s l] j ? ? ?}s g t s|?i a y?1 *? v ch ch cmdr _ _ = + () + () ? 2 9 0 50x w s f g ? ?r? r 2 5? b e d 18 ______________________________________________________________________________________ - 4 / ! r?k ? ?+ data bit operation d7 (start) d6 d5 d4 d3 d2 d1 d0 conversion-start byte (tables 4 and 5) 1c2c1c00000 analog-input configuration byte (table 2) 1 c2 c1 c0 dif/ sgl r2 r1 r0 mode-control byte (table 7) 1m2m1m01000 - 5 / ! ] y+ ) e j g 0 sgl = 1 *|0x? channel-select bit channel c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 000+ - 001 + - 010 + - 011 + - 100 + - 101 + - 110 +- 111 +- - 6 / ! ^? j y+ ) e j g 0 t h m ! = 2 *|0x? channel-select bit channel c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 000+- 0 0 1 reserved 010 +- 0 1 1 reserved 100 +- 1 0 1 reserved 110 +- 1 1 1 reserved k { > n b y 2 1 4 5 0 n b y 2 1 4 6 ?? t q j 0 r t q j [ n j d s p x j s f 0?| r { > n b y 2 1 4 5 0 n b y 2 1 4 60 - e j o e p v u t d m l cs [ t t u s c - 1#? ? ?r0g t d m l h - i 2 1 n i { )] ? y+ y+ 3 * 4 / 7 8 n i { )j] ? y+ y+ 1 * t 5 / 4 : n i { )j] ? y+ y+ 2 * ? )0?g ? <? *b ?g d q p m = 1 d q i b = 1| t q jr ? + ?d?d 3d 4 [d 5?, k { >?r?2 ?? ? ? ] t^? jr?0x|? ? ? ] ?v tw ?vr? *? ? ? ?+ y+? j] ? ) y+ 1 * j]g ) y+ 2 * ] ? ) y+ 3 * ?? ) y+ 5 * ] ? y+ ) y+ 7 * r] ? y+ ) y+ 8 * ? ?t [s ? + ? ) cs * ?0 - cs ' n b y 2 1 4 5 0 n b y 2 1 4 6? .|0gi cs ?? k ?? t d m l|? ?? e j o4[$? h @&k ?? t d m l| ]?- e p v u4[$ hi cs ? s ? r t d m l [ e j o|?$ ?% e p v u? ??2??j??? a1 e p v u#?? t t u s c|ey 5 ?p%??y a1 ? g s# t ??, ) t t u s c * ?d 4 [d 5?, t t u s c$ -, b e d/ 3r? ? (t @& ? -2s/e? q| ? + t t u s c? j] ? y+ )d 3 **????3p% -2y { t t u s c ?q?? ?3 t??3 cs |?? p%j]??y a1 t t u s c n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 19 001 010 011 100 101 110 111 0 -v ref /2 -3/4 v ref -v ref +v ref +3/4 v ref +v ref /2 +v ref /4 -v ref /4 each input is fault tolerant to 6v. (ch_) - agnd1 (v) input range selection bits, r[2:0] fsr = v ref / 2 fsr = v ref / 2 fsr = v ref / 2 fsr = v ref fsr = v ref fsr = v ref fsr = 2 x v ref d 8 / ! ]r??1 *? 001 010 011 100 101 110 111 -v ref -3/2 v ref -2 x v ref +v ref +3/2 v ref +v ref +v ref /2 -v ref /2 each input is fault tolerant to 6v. (ch_+) - (ch_-) (v) input range selection bits, r[2:0] 0 fsr = v ref fsr = 2 x v ref fsr = 4 x v ref d 9 / ! ? jr??1 *? n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 20 ______________________________________________________________________________________ - 7 / ! ? *?? ? dif/ sgl r2 r1 r0 mode transfer function 0 0 0 0 no range change* 0001 single-ended bipolar - v ref /4 to +v ref /4 full-scale range (fsr) = v ref / 2 figure 12 0010 single-ended unipolar -v ref /2 to 0 fsr = v ref / 2 figure 13 0011 single-ended unipolar 0 to +v ref /2 fsr = v ref / 2 figure 14 0100 single-ended bipolar -v ref /2 to +v ref /2 fsr = v ref figure 12 0101 single-ended unipolar -v ref to 0 fsr = v ref figure 13 0110 single-ended unipolar 0 to +v ref fsr = v ref figure 14 0111 default setting single-ended bipolar -v ref to +v ref fsr = 2 x v ref figure 12 1 0 0 0 no range change** 1001 differential bipolar -v ref /2 to +v ref /2 fsr = v ref figure 12 1 0 1 0 reserved 1 0 1 1 reserved 1100 differential bipolar -v ref to +v ref fsr = 2 x v ref figure 12 1 1 0 1 reserved 1 1 1 0 reserved 1111 differential bipolar -2 x v ref to +2 x v ref fsr = 4 x v ref figure 12 * t ? ? ) e- 4 * ** y+ <? ? ) e- 4 * ?*? ?- 4?,' 4?r?k ? ?+ n b y 2 1 4 5 0 n b y 2 1 4 6 ?r0g ? r?k ? ?? ?*? * ? ?*??c?? cs ?? 4[$? e j o|? ] ?3?4 ? o ] e h?? ? h? ?rk ?t & t |??k ? ?/- e p v u$ ? h|??j] ? y+ ) y+ 1 *& |t ? + ? c 2 4 C c 2/ 3- e p v u$ ? h|??j]g y+ ) y+ 2 *& |t ? + ? c 2 4 C c 6/ 3- e p v u$ ? h|??] ? y+ ) y+ 3 *& |t ? + ? c 2 4 C c 3/ 3- e p v u$ rk ? ?+ ? t d m l| ]?rk ?2?$ ?? i| ?+- e p v u4[r@& n t c? ) c 2 4 * ?r ?? i|g??l e r =k ] j2 d 2 3d 2 4 [d 2 5 |? y r? ? y r? y |?lk? ? ] t^? jr? ? r??1 *? zklk -- 3?,| y r?|? ? v ?r|? ? y r?? ? @?@r?| ?g?d 2 6?,| ?d? ?? \v y r?|? @d 2 7 ? e p v u [ t t u s c| ? r =k b e d|r =k?c ? y r??1 [k rt i? .| d 2 3d 2 4 [d 2 5 ? n b y 2 1 4 5 0 n b y 2 1 4 6 |r =k ?r =ks ? ep? ? y r??1 *? ? ] t? j|? ? ?e?1 b e dr =k,*|]?0?g"??i? ) m t c * ? n b y 2 1 4 5 0 n b y 2 1 4 6 m t cg e ?+ ?r ? | o5?k ) o = 2 5 * g t s? x ? *? ) ed 8 [d 9 * 1 2 4 096 . lsb fsr v v ref n = n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 21 input common-mode voltage range vs. output voltage (fsr = v ref ) input voltage (v) common-mode voltage (v) 6 4 2 0 -2 -4 -6 -4 -2 0 2 4 6 -6 -8 8 v ref = 4.096v d : / ! a y?1r??1| ) g t s ! = w s f g * input common-mode voltage range vs. output voltage (fsr = 2 x v ref ) input voltage (v) common-mode voltage (v) 6 4 2 0 -2 -4 -6 -4 -2 0 2 4 6 -6 -8 8 v ref = 4.096v d 2 1 / ! a y?1r??1| ) g t s ! = 3 ! y ! w s f g * input common-mode voltage range vs. output voltage (fsr = 4 x v ref ) input voltage (v) common-mode voltage (v) 6 4 2 0 -2 -4 -6 -4 -2 0 2 4 6 -6 -8 8 v ref = 4.096v d 2 2 / ! a y?1r??1| ) g t s ! = 5 ! y ! w s f g * n b y 2 1 4 5 0 n b y 2 1 4 6 y+ <? n b y 2 1 4 5 0 n b y 2 1 4 6t : 2 ? qt| y+ <? @ d 2 6 ?? \' y+ <? ? y+ <? ?| ? +?- 8?, ? y+ <? ? v? t 1+ <? n b y 2 1 4 5 0 n b y 2 1 4 6| ? h y+ ? t 1+ ? y+ <? ?? t 1+ )l e y+ <? ] j *@ 't ? ? ) e- 4d 3d 4 [d 5 * v?t n b y 2 1 4 5 0 n b y 2 1 4 6g e? 1 ? s y g st ?k g s? ? j] ? y+ y+ 1 ! )d 3 * ? " tj h ) e f m f d u s j d b m ! d i b s b d u f s j t u j d t - * ? ? <?g . ? t e . cs ???3 ? ?s b e dt e . [- e p v usk ? -| ?? ? t d m l ? j]g y+ y+ 2 ! )d 4 * ? "?tj h ) e f m f d u s j d b m ! d i b s b d u f s j t u j d t - * ? ? <?g . ? ? 3 ?| t d m lm ? s cs q?? ? 3 -? b e dt e . ?5 | ?[ ? ? t t u s c$ ? ? ? 3 ?| t d m l@ s e p v uk ? ? ] ? y+ y+ 3 ! )d 5 * ? tj h ) e f m f d u s j d b m ! d i b s b d u f s j t u j d t - * ? ] ? <?g . 9 0 50x w s f g ? ?r? r 2 5? b e d 22 ______________________________________________________________________________________ 1 lsb = fsr x v ref 16,384 x 4.096v binary output code (lsb [hex]) 3fff 3ffe 3ffd 2001 2000 1fff 0003 0002 0001 0000 fsr 0 1 2 3 8,192 16,381 16,383 input voltage (lsb [decimal]) (agnd1) fsr d 2 4 / ! /|] ?vr =k]r? . g t su 1 1 lsb = fsr x v ref 16,384 x 4.096v binary output code (lsb [hex]) 3fff 3ffe 3ffd 2001 2000 1fff 0003 0002 0001 0000 fsr 0 1 2 3 8,192 16,381 16,383 input voltage (lsb [decimal]) (agnd1) fsr d 2 5 / ! /|] ?vr =k]r? 1u , g t s 1 lsb = fsr x v ref 16,384 x 4.096v binary output code (lsb [hex]) 3fff 3ffe 3ffd 2001 2000 1fff 0003 0002 0001 0000 fsr -8,192 -8,190 0 +8,189 +8,191 input voltage (lsb [decimal]) agnd1 (dif/sgl = 0) 0v (dif/sgl = 1) fsr -1 +1 d 2 3 / ! /|w ?vr =k] t? jr? ? ? 2 ?| t d m lm ? s cs q?? ? 3 -? b e dt ?5 | ?[ ? ? t t u s c$ ? ? ? 3 ?| t d m l@ s e p v uk ? j] ? y+ ) y+ 1 * n b y 2 1 4 5 0 n b y 2 1 4 6 ?+?j] ? y+ - y{" p |tj h t d m l <? y g s|g <? y g s|t #? i <?g y g s| .? t d m l |? 2 5 ]? * y r?g )d 3 * j] ? y+??g t d m lq?t ?t ? t d m l? hb ?? q?"?| t d m l? h ? ?]g???|?1?t e . b j] ? y+ t t u s c ???3 p% ? + n b y 2 1 4 5 0 n b y 2 1 4 6? ?+?j] ? y+ t t u s c -2y { j]g y+ ) y+ 2 * gj]g y+ tj h"??j]g y+ t d m l <? y g s|g #? i <?g y g s | .] ? <? y r??1|t ? t d m l| ? 2 7 ]? ?r y r?g )d 4 * n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 23 cs sclk din dout 18 start sel2 sel1 sel0 r2 r1 r0 dif/sgl t cl t cp t ch t dv t css t ds t dh t csh t cspw t tr 18 start m2 m1 m0 1 0 0 0 analog input configuration byte mode control byte high impedance high impedance high impedance d 2 6 / ! y r?|? ? [ y+ <? ?| ? cs sclk dout t css high impedance sstrb t sscs msb t do note: sstrb and cs remain low in external clock mode (mode 0). d 2 7 / ! e p v u [ t t u s c - 8 / ! y+ <? ? bit number bit name description 7 start start bit. the first logic 1 after cs goes low defines the beginning of the mode-control byte. 6m2 5m1 4m0 mode-control bits. m[2:0] select the mode of operation as shown in table 8. 3 1 bit 3 must be a logic 1 for the mode-control byte. 2 0 bit 2 must be a logic 0 for the mode-control byte. 1 0 bit 1 must be a logic 0 for the mode-control byte. 0 0 bit 0 must be a logic 0 for the mode-control byte. n b y 2 1 4 5 0 n b y 2 1 4 6 ?j]g y+ cs ?? *| 2 6 ?2e? ??3m ??? 2 7 ?2e| ]? t? ?$? ?3?d 4?, y{" vt e . s e j o [ t d m l?? 9? ?r? 5?z 't e . e j o [ t d m l|?$ ?t ? +|l0 ?c t r? ? t t u s c$ - o? cs 2st ? + ?2 ?b?*?| t d m l? ? t t u s c ) ???3 ] ? y+ ) y+ 3 * ] ? y+] ? <? y g s|g [t ] ?? t d m l|? 9 ]? ?| 2 1 1 o tu 5 1 1 o t? . ? hm?? 5 / 6 n i {?] ?g s|? 2 2 ] ? * y r?g )d 5 * ?] ? y+ cs ? *| 8 t d m l ?2e ????3m ??? 9 t d m l ?2e| ]? t ? ?$? ?3t r? ? t t u s c$? ?3 - 2 o? cs @st ? +?2 ?b?*?| t d m l? ? t t u s c ) ???3 ?? ) y+ 5 * ?- 9?,?? n \ 3 ; 1 ^ = 2 1 1 - s n b y 2 1 4 5 0 n b y 2 1 4 6 ???c?c?5? ? 0x|?? w s f g w ?v]t 1+@&gj] ? y+ ) y+ 1 * ] ? y+ ) y+ 7 * ?- 9?,?? n \ 3 ; 1 ^ = 2 2 1 h ?? ] ? y +? ] ? y+ ? ?e?1? ? 5 [?? ??j h??| y ] j]] ? s ] ? y+ - e y+ <? ?? v ?$ y+ ) e y+ <? ] j *? ? j] ? y+ <? ? ? j]g y+ <? ? ? ] ? y+ <? ? ? ?? ? ? r] ? y+ <? ? z?+ - 4? n b y 2 1 4 5 0 n b y 2 1 4 6?r|k 1 ?? cs ?w g?- ] ? y+s r] ? y+ ) y+ 8 * i n \ 3 ; 1 ^ = 2 2 2 h ??r] ? y+??? ]u 2 b )?o? *?r] ? y+ h|?? y ] j]] ?? +g] ?e-r] ? y+ s ???t ?? 2 1 n t| a ? .2? z] ?e?1?? v sr] ? y+ - e y+ <? ?? v ?$ ? y+ )l e y+ <? ] j *? ? j] ? y+ <? ? ? j]g y+ <? ? 9 0 50x w s f g ? ?r? r 2 5? b e d 24 ______________________________________________________________________________________ m2 m1 m0 mode 0 0 0 external clock (default) 0 0 1 external acquisition 0 1 0 internal clock 0 1 1 reserved 1 0 0 reset 1 0 1 reserved 1 1 0 partial power-down 1 1 1 full power-down - 9 / ! y+ <?? n \ 3 ; 1 ^ ? ] ? y+ <? ? ? ?? ? ? ] ? y+ <? ? z? 1 - 4? n b y 2 1 4 5 0 n b y 2 1 4 6?r|k 1 ?? cs ?w g?sr] ? y+ ?? ?? n b y 2 1 4 5 0 n b y 2 1 4 6?? ? t ??gj] ? y+|u ? ?+???? 5 ? ?+? )- 8 [- 9 * ? y r?0x ) d i 1 C d i 8 * ????]t y+r? *?? w s f g )- 7 * ??2 ?b ? u???? v??????y ?t ji d s f g = 2 / 1 g [ d s f g d b q = 1 / 2 g b?] ?e 2 1 n t|?? . ?m| ?e??? ??|?? . ] [j] ?e n b y 2 1 4 5 0 n b y 2 1 4 6 -g] ?e tj] ?e ?e? 1l0 b e d| g t s )d 2 3d 2 4 [d 2 5 *? +g| ?e t] ?e ? [ 0 t? t ?$4| ?e ?1 n @'j] ?e ] ?e n b y 2 1 4 5 0 n b y 2 1 4 6 : 5 / 1 : 7 wr ?e ?r ? e0 - *a?? 6 l |? {u s f g d b q )d 2 8 * s f g d b q?|?1 3 - |? s f g?? 5 / 1 : 7 w ?e? 1ig] ?e b 1 / 2 g tw ?m|?? s s f g d b ql 5u b h o e 24 2 / 1 g tw ?m|?? s s f gl 5u b h o e 2 j] ?e 'j] ?e ? s s f g d b q {u b w e e 2 2 ] ?e [ ?e | b w e e 2 s f g d b q$ s f g$? r?@ {jj] ?e?1 n b y 2 1 4 5 0 n b y 2 1 4 6 |j] ?e? s ?? | ?e?1 [ ?+ y+ )l e ?o ?+v || f y u f s o b m ! s f g f s f o d f ! j o q v u ! d v s s f o u ! w t / f y u f s o b m ! s f g f s f o d f ! j o q v u ! w p m u b h f * ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `bg? ] ?r?( jg@gs3 ?? ) -g * -2?t ? +||t l0g(k|3 1 ? ? ?v | ??t ???@? 3 0 4 m t c s n t ) 5 m t c q . q *|t ? ?r 2 7 ) 5 3 = 2 7 *(gc s ?cu 2 m t c q . q 5 C 3 1 n bg s { > d 2 : ? n b y 2 1 4 5 0 n b y 2 1 4 6 [ 5 C 3 1 n bg s? . | <] { > 5 C 3 1 n bg s -2+ ?? ) 5 n b -, ] ?g s 3 1 n b-, ] g s * tw? i r ) 5 n bu 3 1 n b? .|? t-| . y k ? *? ?? b -0 - {?? s 5 C 3 1 n bg s n b y 2 1 4 5 0 n b y 2 1 4 6$ ??? 3 1 1 ? - s 5 C 3 1 n b g st ? 1 / 9 wu 5 w |g ss ?? ?2' ?? n b y 2 1 4 5 0 n b y 2 1 4 6? |@ ?? 3 1 1 ?z?b|b? ] 1u w s f g ? *? ) s \ 3 ; 1 ^ = 1 2 2- 7 *?? i? ? 5 n bu 3 1 n b ? y ? |bb' |2 4? n b y 2 1 4 5 0 n b y 2 1 4 6r ?- 5 C 3 1 n bg s| j n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 25 ref refcap agnd1 4.096v bandgap reference 5k 1x sar adc ref 4.096v 1.0 f 0.1 f v rcth MAX1034 max1035 d 2 8 / ! ] ?e n b y 2 1 4 5 0 n b y 2 1 4 6 ?b t 2 l i {g s n b y 2 1 4 5 0 n b y 2 1 4 6?b| - e| . t t ? n b y 2 1 4 5|r? " ? ] -l0 n b y 2 1 4 5|d? j?b| z??5 -2 {j|c? +by??z??@ ? - n b y 2 1 4 5|r? ?r | )d 3 1 *?? ? j 9m$ 9m|r {? n b y 2 1 4 5 0 n b y 2 1 4 6|^? jr? wm| ? o?1 ? ? j? ? w s f g 0 3? jr??1 *?? |r??1 *? [ 9mr?|? ]8| 9m b?@ 9m | [$? ??sr? *? 0 -? h <? ? 0x| y r? *?2 h| ] ?v? c?lk?? ??? ?$ 0x|r ? *?- ?? kb|v ?$r? *? -? ? q|r?1 *?#c| m t c[? ???? . w s f g 0 3u 1| ? *? [ 1u w s f g 0 3| ? *?? .$ m t c?? cr??1 *?|?i kt? . w s f g 0 3u , w s f g 0 3 ) g t s = w s f g * z {? [l 5 ? y{" ;v e q d c|z ;? f? 5?b ??? a| y [k ??2i?k [ y g s$ ? ? - y [k )05 ?g s *g sy %3r#y? h v??]k g s# d 2 ?n @|; {? 1+? b h o e 2 p a y {?? ? e h o e p a k {?? s?? y ?io {? y {?? s??k ?io {u k {??m ? sk ?? [ y ???]? {u ??' "?io {?????|? ? 5b ? ?? 0 5@b ? -|a b w e e 2 ??| ? ]? b e d| w|v ' 1 / 2 g|- a#??#?? s b w e e 2 l 5u b h o e 2l 5??| #b -a ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `lk?c j ;#v ) j o m * j o m5# r =k ?#|??? ??# -25 " ]?# -25? [d? ? y ?| # n b y 2 1 4 5 0 n b y 2 1 4 6| j o m5g? # 1 ? ?| vv ref ref / , . 2 16 384 4 096 9 0 50x w s f g ? ?r? r 2 5? b e d 26 ______________________________________________________________________________________ ref refcap agnd1 4.096v bandgap reference 5k 1x sar adc ref 4.096v 1.0 f v rcth MAX1034 max1035 av dd1 max6341 v+ 1.0 f out gnd in d 2 9 / ! j] ?e ?+? 5 ? j ;#v ) e o m * e o m5# [? qt [ 2 m t c /?? .|?? e o m ??*m? . 2 m t c -?zy i [r =k|]v t t 5?? b e dr =kt i"$?| | y r?? q ?t i"$? ?rt t?r t i? m t c|f? 0x . ? -t 0x . ? -t-, ? y r?0x| ? - t? ?zk h|0x . ? -t ???| y r ?0x? { x ? mt| 6 l i {uf4 ?? ???0x? $4 mty4? h|uf? ?0x|r ?r g g ui????0x |g s?? |g s mt [ ??? y r?0x| 6 l i {g s mt ? ?? t?0x . ? -t2 e c?]? n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 27 MAX1034 200 4C20ma input 200 4C20ma input ch0 ch8 c d 2 : / ! 5 C 3 1 n bb MAX1034 max1035 ch0 ref p ch1 low-offset differential amplifier bridge d 3 1 / ! ?b n b y 2 1 4 5 0 n b y 2 1 4 6 ] ?v? . g t su 1 w i ? y r??1 ut r? k r ?] 2 ) 1 y 4 g g g * /= z 1 y 4 g g gu 1 y 4 g g f|"$? ? b h o e 2 . 1 / 6 m t c|??] ?v?5?{ | ?"$? [ / ?"$?? .|???b ? ???0x ? {? 1 wu , g t s i ? y r??1 ut r? k r? ] 1 ) 1 y 1 1 1 1 * /= z 1 y 1 1 1 1u 1 y 1 1 1 2|"$? ? b h o e 2 , 1 / 6 m t c ] ?v?5?{| ? "$? [ / ?"$?|????b ??? ?0x ? {? w ?v? i ? y r??1 ut r? k r ? 2 [2 ?|] 1 ) 1 y 3 1 1 1 * /= z 1 y 2 g g gu 1 y 3 1 1 1|"$?? ) 3 o . 2 . 1 / 6 * m t c w ?v ?5??{||?"$? [ /|?"$?? .|?? ??b s??0x {? d? i u ?v x ??1 ut r? k r ?] 2 ! ) 1 y 4 g g g * /= z 1 y 4 g g fu 1 y 4 g g g|"$ ??? x ? 2 / 6 ! m t c d?5?? ? ??{| x ?"$? [ / x ?"$?? .|? ??b ????0x ? {? ] ?v? c? ] ?v? c?5?? y ?wr??1 *?? .$ |$ ? ? ?? . w s f g 0 3u 1 wr??1 *? b 1 y 4 g g gr|r??1 1u , w s f g 0 3r??1 *? b 1 y 1 1 1 1r|r??1?? 5] ?v? c ? n b y 2 1 4 5 0 n b y 2 1 4 6|] ?v? c??u?z ?$ y r??1 *?? .$ - 4?g s [ ?l cg sr q 6 b e dr? 2 1 1 n w q . q |uf ?[ r?? hk t ? + ]? m? ]? . 4 e c b|? h t?cg sr q x ? hr q 6 b e dr? m?? x ?| : 6 % |uf? m r?? h?uk ?t ? +| m? ]? . 4 e c% b|? h t? x ? hr q a y4? ) d n s s * ! d n s s5 h a y g s t u y r?|g s|4? ? a yg s -25 c t? g s -25 w| ] d n s j?-, a y4?5 ? jg sd a yg sd? d n s s ??? j y+ ??4? ) q t s s * q t s s5?? ?r??1r?1$ ? ???? 1$ ? ?|?? n b y 2 1 4 5 0 n b y 2 1 4 6 v? b w e e 2 -2? 5 / 8 6 wu 6 / 3 6 w? .$ ? q t s s j?-,@& g e ?+ ?r ? ? n b y 2 1 4 5 0 n b y 2 1 4 6 q t s s5?w ?v y+ s y r? {??{| ; ?? ; ?? u b k 5g 0$ ? ?|; jz )d 3 2 * ; ?? ; ?? u b e 5- t d m l ]?u# g 0| . ? )d 3 2 * g ) t o s * t o s5g s s n t [ s n t|? v | s n t t j ? ?f?(uf [ e d?j `?? h|???? j g s , ! ^ ) t j o b e * t j o b e?g s s n t [ ^ s n t|? v ^ s n tt j ? ?f [ e d?j `?? h|???? j sinad db signal noise rms rms ( ) log = ? ? ? ? ? ? 20 psrr db vv vvvv out out [ ] log . . (. ) (. ) = ? ? ? ? ? ? ? ? 20 525 475 525 475 9 0 50x w s f g ? ?r? r 2 5? b e d 28 ______________________________________________________________________________________ ?i? ) f o p c * f o p c-, b e d???r?? h [g h|s tr? *? [ b e d x ? *?$? f o p c -?2 ?+ ? uf^ ) u i e * ? n b y 2 1 4 5 0 n b y 2 1 4 6 u i e5r?g s?(uf j ?| s n t? [ ?fy?-i+?? | w 2 5 ?f m? w 3 u w 6 (5 3(u 6(uf j ?| m? ?2?? *? ) t g e s * t g e s5 ?f s n t ? )"mg s j ? *? m? j ? s n t?? thd vvvv v log = +++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 enob sinad . . = ? ? ? ? ? ? ? 176 602 n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d ______________________________________________________________________________________ 29 t ad t aj intclk (mode 2) analog input track and hold track hold sample instant sclk (mode 0) 13 14 15 sclk (mode 1) 15 16 10 11 12 d 3 2 / ! ; ? ?d n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d 30 ______________________________________________________________________________________ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` `g? transistor count: 28,210 process: bicmos ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` 1 vd MAX1034 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd1 analog input mux and multirange circuitry pga agnd2 av dd2 4.096v bandgap reference 1x 5k in ref refcap ref control logic and registers fifo clock out sar adc serial i/o agnd2 av dd2 agnd3 av dd1 dgnd dv dd dgndo sclk dout sstrb din cs dv ddo [m)* 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 agnd2 av dd2 agnd3 ref ch1 ch0 av dd1 agnd1 refcap dv dd dv ddo dgnd din cs ch3 ch2 12 11 9 10 dgndo dout sclk sstrb max1035 tssop top view % s f w ! 2||? ?? 2 4 C 7 4 1 4 2 n b y 2 1 4 5 0 n b y 2 1 4 6 9 0 50x w s f g ? ?r? r 2 5? b e d tssop4.40mm.eps package outline, tssop 4.40mm body 21-0066 1 1 i ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` v?g? ( tk ?t ? | v?d -y5" | ???" | v?jpg??? www.maxim-ic.com.cn/packages ) n b y j n ? ?0 ? 9 4 3 9g( ?v i 2 1 1 1 9 4 ? e? ?? 9 1 1 ! 9 2 1 ! 1 4 2 1 ? ?? 1 2 1 . 7 3 2 2 6 2 : : ^? 1 2 1 . 7 3 2 2 6 3 : : n b y j ny n b y j n?-2j|? \? 5' ? y ?? - n b y j n? ?? \ . ??? \0| ? ??- t ? [ ?|z ? maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 31 ? 2006 maxim integrated products 5 n b y j n ! j o u f h s b u f e ! q s p e v d u t - ! j o d / |?* |
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