mpc9819 rev 3, 09/2005 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. clock generator for powerquicc and powerpc microprocessors and microcontrollers the mpc9819 is a pll-based clock gen erator specifically designed for freescale microprocessor and microc ontroller applications including the powerpc and powerquicc. this device generates the microprocessor input clock and other microprocesso r system and bus clocks at any one of four output frequencies. these frequencies include t he popular 66- and 133-mhz pci/x bus frequencies. the device offers five low-skew clock outputs plus three reference outputs. the clock input reference is 25 mhz and may be derived from an external source or by the addition of a 25-mhz crystal to the on-chip crystal oscillator. the extended temperatur e range of the mpc9819 supports telecommunication and networking requirements. features ? 5 lvcmos outputs for proce ssor and other system circuitry ? 3 buffered 25-mhz reference clock outputs ? crystal oscillator or external reference input ? 25-mhz input reference frequency ? selectable output frequencies in clude: 66, 100, 125, or 133 mhz ? low cycle-to-cycle and period jitter ? package: 20-lead ssop ? 3.3-v supply ? supports computing, networking, and telecommunications applications ? ambient temperature range: ?40c to +85c functional description the mpc9819 uses a pll with a 25-mhz input reference frequen cy to generate a single bank of five configurable lvcmos output clocks. the ou tput frequency of this bank is config urable to eith er 66, 100, 125, or 133 mh z by two fsel pins. the 25- mhz reference may be either an external fr equency source or a 25-mhz crystal. the 25-m hz crystal is directly connected to the xtal_in and xtal_out pins with no additional components requir ed. an external reference may be applied to the xtal_in pin with the xtal_out pin left floating. the input reference, whether provided by a crystal or an external input, is also direc tly buffered to a second bank of three lvcmos outputs. these outputs may be used as the clock source for processor i/o applications such as an ethernet phy. the mpc9819 is packaged in a 20-lead ssop package. mpc9819 microprocessor clock generator en suffix 20 ssop package pb-free package case 1461-02 sd suffix 20 ssop package case 1461-02
advanced clock drivers devices 2 freescale semiconductor mpc9819 figure 1. mpc9819 logic diagram table 1. pin configurations pin i/o type function qa0, qa1, qa2, qa3, qa4 output lvcmos clock outputs qref0, qref1, qref2 output lvcmos reference output (25 mhz) xtal_in input lvcmos crystal oscillator input pin xtal_out output lvcmos crystal oscillator output pin fsel0, fsel1 input lvcmos configures bank a clock output frequency (pull-up) mr/oe input lvcmos enables all outputs (pull-down) v dd ? ? 3.3-v supply gnd ? ? ground table 2. function table control default 00 01 10 11 fsel0, fsel1 11 66 mhz 125 mhz 100 mhz 133 mhz ref pll 400 or 500 mhz qa0 qa1 qa2 qa4 xtal_in osc xtal_out fsel0 qref0 fsel1 qa3 qref1 qref2 data generator mr/oe 66,100,125,133 25 mhz mhz
advanced clock drivers devices freescale semiconductor 3 mpc9819 figure 2. mpc9819 20-lead ssop package pinout (top view) mpc9819 operation crystal oscillator the mpc9819 features a fully integrated pierce oscillator to minimize system implementa tion costs. other than the addition of a 25-mhz crystal, no external components are required.the crystal selection should be: 25 mhz, parallel resonant type with a load specification of c l = 10 pf. crystals with a load specification of c l = 20 pf may be used, however, the reference frequency may be higher than the specified 25 mhz. externally supplied capacitors on both the xtal_in and xtal_out pins may be used to trim the frequency as desired. the crystal should be located as close to the mpc9819 xtal_in and xtal_out pins as possible to avoid any board level parasitic. power supply bypassing the mpc9819 should have all v dd pins bypassed with 0.01 capacitors and a minimum of one 1.0 capacitor for the overall package. all capacitors should be located as close to the ssop pins as possible. external clock source an external reference source of 25 mhz may be applied to the xtal_in pin. in this mode of operation, the xtal_out pin should be left floating. xtal_in xtal_out fsel0 v dd fsel1 qref2 gnd qref1 qref0 v dd v dd qa4 qa3 gnd qa2 qa1 v dd qa0 mr/oe gnd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 table 3. crystal specifications parameter value crystal cut fundamental at cut resonance parallel resonance shunt capacitance (c o ) 5?7 pf load capacitance (c l ) 10 pf equivalent series resistance (esr) 20?60 ?
advanced clock drivers devices 4 freescale semiconductor mpc9819 table 4. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum val ues beyond which damage to the device may occur. exposure to these conditions or conditions beyond t hose indicated may adversely affect device reliabi lity. functional operat ion at absolute-maxim um-rated conditions is not implied. symbol characteristics min max unit condition v dd supply voltage ?0.3 3.8 v i in dc input current ? 20 ma i out dc output current ? 75 ma t s storage temperature ?65 125 c table 5. general specifications symbol characteristics min typ max unit condition v tt output termination voltage ? v dd 2 ?v mm esd protection (machine model) 200 ? ? v hbm esd protection (human body model) 2000 ? ? v lu latch-up immunity 200 ? ? ma c in input capacitance ? 4 ? pf inputs c pd power dissipation capacitance ? 8.5 ? pf ja thermal resistance (junction-to-ambient) ? 80.8 ? c/w t c ambient temperature ?40 85 c table 6. dc characteristics (v dd = 3.3 v 5%, t a = ?40 to +85c) symbol characteristics min typ max unit condition v ih input high voltage (xtal_in) 2.4 ? v dd + 0.3 v input threshold = v dd /2 v ih input high voltage 2.0 ? v dd + 0.3 v v il input low voltage ? ? 0.8 v lvcmos i in input current (1) 1. inputs have pull-down resistors affecting the input current. ? ? 150 av in = v ddl or gnd v oh output high voltage 2.4 ? ? v i oh = ?12 ma v ol output low voltage ? ? 0.4 v i ol = 12 ma z out output impedance ? 14 ? ? i dd maximum supply current f a = 66 mhz f a = 133 mhz ? ? 23 32 40 50 ma 25 mhz reference frequency i ddbase base supply current (2) (for dynamic power dissipation calculation) 2. p d = (v dd * i ddbase ) + 5 (v dd 2 ) * c pd * f a . ?14?ma
advanced clock drivers devices freescale semiconductor 5 mpc9819 figure 3. mpc9819 ac test reference (lvcmos outputs) table 7. ac characteristics (1) (2) (v dd = 3.3 v 5%, t a = ?40 to +85c) 1. ac characteristics are design targets and pending characterization. 2. ac characteristics apply for par allel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition input and output timing specification f ref input reference frequency 25 mhz input xtal input 25 25 mhz mhz f vco vco frequency range fsel0, fsel1 = 00,01,11 fsel0, fsel1 = 10 400 500 mhz mhz f mcx output frequency (qax) fsel0, fsel1 = 00 fsel0, fsel1 = 10 fsel0, fsel1 = 01 fsel0, fsel1 = 11 output frequency (qrefx) 66.66 100 125 133.33 25 ? ? ? ? ? mhz mhz mhz mhz mhz pll locked f refpw reference input pulse width 10 ? ? ns @ 25 mhz dc output duty cycle 45 50 55 % f out output frequency accuracy crystal (3) external reference 3. based upon recommended crystal specificat ions as outlined in operation section. ? ? 100 0 ppm ppm with recommended crystal see table 3 pll specifications bw pll closed loop bandwidth (4) 4. ?3 db point of pll transfer characteristics. 500 khz t lock maximum pll lock time 10 ms skew and jitter specifications t sk(o) output-to-output skew (within a bank) 75 ps t jit(cc) cycle-to-cycle jitter 150 ps @ 25 mhz input reference q a output t jit(per) period jitter 100 ps @ 25 mhz input reference q a output t r , t f output rise/fall time 1 ns 20% to 80% z = 50 ? r t = 50 ? v tt z = 50 ? v tt dut mpc9819 pulse generator z = 50 ? r t = 50 ?
advanced clock drivers devices 6 freescale semiconductor mpc9819 table 8. mpc9819 pin list pin description pin description 1 xtal_in 11 gnd 2 xtal_out 12 mr/oe 3 fsel0 13 qa0 4v dd 14 v dd 5 fsel1 15 qa1 6qref2 16qa2 7gnd 17gnd 8qref1 18qa3 9qref0 19qa4 10 v dd 20 v dd
advanced clock drivers devices freescale semiconductor 7 mpc9819 package dimensions case 1461-02 issue a 20 ssop package page 1 of 3
advanced clock drivers devices 8 freescale semiconductor mpc9819 package dimensions case 1461-02 issue a 20 ssop package page 2 of 3
advanced clock drivers devices freescale semiconductor 9 mpc9819 package dimensions case 1461-02 issue a 20 ssop package page 3 of 3
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