1 S1C33L05 32-bit single chip microcomputer 32-bit s1c33000 risc core low power multiply accumulation built-in 16k-byte ram 10-bit adc built-in lcd controller built-in usb1.1 function controller built-in sdram controller description the S1C33L05 is a seiko epson original 32-bit microcomputer that features high speed, low power consump- tion, and low-voltage operation. the S1C33L05 consists of an s1c33000 32-bit risc type cpu as its core, peripheral circuits including a bus control unit, dma controller, interrupt controller, timers, serial interface with fifo, a/d converter, a color stn lcd controller that supports 64k color display, sdram controller, usb1.1 function controller, sequential rom interface, mmc (spi mode) interface and nand flash interface, and also an embedded ram. two oscillation circuits and a pll are also included, supporting advanced operation, power- saving operation, and high-performance realtime clock functions. the S1C33L05 is ideal for portable products that require high-speed data processing. especially it is suitable for the application processor embedded in pdas, electronic dictionary and e-book readers. features core cpu seiko epson original 32-bit risc cpu s1c33000 built-in ?basic instruction set: 105 instructions (16-bit fixed size) ?sixteen 32-bit general-purpose register ?32-bit alu and 8-bit shifter ?multiplication/division instructions and mac (multiplication and accumulation) instruction are available ?20.83 ns of minimum instruction execution time at 48 mhz operation internal memory general-purpose ram .............................. 16k bytes (1-cycle-access) video-ram ............................................... 40k bytes (usable for general-purpose ram, 2-cycle-access) internal peripheral circuits osc3 oscillation circui t/pll ..................... when pll is disabled crystal oscillator 5 mhz min. to 48 mhz max. ceramic oscillator 48 mhz (fixed) external clock input 2 mhz min. to 48 mhz max. when pll is enabled crystal oscillator 20 mhz min. to 48 mhz max. ceramic oscillator 48 mhz (fixed) external clock input 20 mhz min. to 48 mhz max. generates the main clock for the bus and the cpu. the software controllable pll multiplies the high-speed (osc3) oscillation clock frequency. pll input clock 10 mhz min. to 24 mhz max. pll output clock 10 mhz min. to 48 mhz max. osc1 oscillation circuit ............................. cr ystal oscillator or external clock input 32.768 khz typ. generates the source clock for the realtime clock function, etc.
2 S1C33L05 timers ....................................................... 8-bit timer 6 channels 16-bit timer 6 channels watchdog timer 1 channel (16-bit timer 0's function) clock timer 1 channel (with alarm function) serial interface .......................................... 4 channels clock-synchronous system, asynchronous system and irda 1.0 interface are selectable. ch.0 is selectable between a built-in buffer type (a 4-byte receive- data buffer and a 2-byte transmit-data buffer) and no buffer type. a/d converter ............................................ 10 b its 5 channels lcd controller ........................................... 4 or 8-bit monochrome/color lcd interface panels supported - single-panel, single drive passive display - 4/8-bit monochrome lcd interface - 4/8-bit color lcd interface display modes - 16-bpp mode: 64k colors or 64-level gray scale display - 12-bpp mode: 4096 colors or 16-level gray scale display - 8-bpp mode: 256 colors or 64-level gray scale display - 4-bpp mode: 16 colors or 16-level gray scale display - 2-bpp mode: 4 colors or 4-level gray scale display - 1-bpp mode: 2 colors or 2-level gray scale display ? a 256 3 6-bit look-up table (256k-color palette) is pro- vided for displaying 256 colors simultaneously. the lut can be bypassed to send display data from vram directly to the lcd. ? gray scale display uses frm (frame rate modulation) and dithering. resolution (programmable) typical resolutions when only the internal vram is used: - 320 240 pixels in 4-bpp mode - 160 240 pixels in 8-bpp mode - 160 160 pixels in 12-bpp mode typical resolutions when an external vram is used via the uma: - 320 240 pixels in 8-bpp mode - 320 240 pixels in 16-bpp mode sdram controller ..................................... 48 mhz synchronous clock max. supports up to 256m-bit (32mb) sdram with 16-bit data width. 16-stage iqb (32-byte instruction queue buffer) and 2-stage dqb (4-byte data queue buffer) are provided. allows lcdc dma controller to access sdram directly as an external vram. mmc (spi m ode) interface ....................... 1 channel supports 1 to 16-bit serial data transfer in master mode. compatible with mmc.
3 S1C33L05 nand flash interface ................................ generates the #smwe and #smre signals using the bcu sig- nals to interface directly with smartmedia cards or nand flash memories. supports 8/16-bit nand flash devices. also the nand flash booting function and the ecc function when a nand flash is read/written are supported. sequential rom interface ........................ supports mx23l12813 (manufactured by macronix international co., ltd.). generates the squale, sqlale and #sqrd signals using the bcu signals to interface directly with the sequential mask rom. usb1.1 function controller ........................ endpoint: ep0, epa, epb, epc, epd (4 channels); fifo: 1,024 bytes dma controlle r .......................................... high-speed dma 4 channels high-speed dma ch. 3 has been reserved for the internal usb1.1 function controller. intelligent dma 128 channels interrupt controller .................................... possible to invoke dma input interrupt 10 types (programmable) dma controller interrupt 5 types 16-bit programmable timer interrupt 12 types 8-bit programmable timer interrupt 6 types serial interface interrupt 15 types a/d converter interrupt 1 type clock timer interrupt 1 type lcd controller interrupt 1 type spi interrupt 1 type usb function controller interrupt 1 type general-purpose input and output ports ... shar ed with the i/o pins for internal peripheral circuits input port 9 bits (max.) i/o port 69 bits (max.) ? the k54 and k65?67 pins are not available in the S1C33L05. ? two led direct output (8 ma) ports (p27 and p26) are avail- able. ? the number of the ports varies depending on the peripheral functions used. external bus interface bcu (bus control unit) built-in ?26-bit address bus (internal 28-bit processing) ?16-bit data bus (data size is selectable from 8 bits and 16 bits in each area.) ?little/big-endian memory access; endian type may be set in each area. ?memory mapped i/o ?chip enable and wait control circuits built-in ?supports burst rom.
4 S1C33L05 operating conditions and power consumption operating voltage ..................................... c ore (v dd )1. 65 v to 1.95 v (1.8 v ?.15 v) (when crystal oscillator is used) 1.70 v to 1.90 v (1.8 v ?.10 v) (when ceramic oscillator is used) i/o (v dde , av dde )2. 70 v to 3.60 v (when usb is not used) 3.00 v to 3.60 v (when usb is used) operating clock frequency ........................ cpu 48 mhz max. note 1 bus (bcu) 40 mhz max. lcd controller 48 mhz max. usb function controller 48 mhz sdram 48 mhz operating temperature ............................. -40 to 85? (when crystal oscillator is used) 0 to 70? (when ceramic oscillator is used) power consumption .................................. during sleep 12 ? typ. during halt 18 mw typ. (48 mhz, lcdc and usb not included) during execution 42 mw typ. note 2 (48 mhz, lcdc and usb not included) lcd controller - during display 1.8 mw typ. (lcdc clock = 8 mhz, 16 bpp, ivram mode, v dd , lcdc block only) usb controller - idle state 14 mw typ. (v dd , usb block only) supply form plastic package ......................................... qfp21-176pin (24 mm 24 mm 1.4 mm, 0.5-mm pitch) die form .................................................... 167-pad (5.25 mm 4.85 mm, 100 ? pitch) notes: 1. set the #x2spd pin to "0" when running the cpu with a 40 mhz or more system clock. also make sure that the internal bus operating clock frequency does not exceed 40 mhz. 2. the values of power consumption during execution were measured when a test program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed.
5 S1C33L05 block diagram v dd v ss v dde osc3 osc4 plls0 pllc osc1 osc2 fosc1(p14/p60) sdclk(p60) sdcke(p20) sda10(p61) udqm(p63) ldqm(p62) #sdce(p53) #sdras(pa1) #sdcas(pa0) #sdwe(p21) fpdat[7:0](pb7?0) fpframe(pc0) fpline(pc1) fpshift(pc2) drdy(pc3) #dmareqx(k50, k51, k53) #dmaackx(p32, p33, p04, p06) #dmaendx(p15, p16, p05, p07) ad0?(k60?4) #adtrg(k52) av dde k50?3 k60?4 #reset #nmi #x2spd ea10md[1:0] #busreq(p34) #busack(p35) #busget(p31) dsio dst[2:0](p10?2) dpco(p13) dclk(p14) tst boot test[1:0] burnin scanen t8ufx(p10?3) sinx(p00, p04, p27, p33) soutx(p01, p05, p26, p16) #sclkx(p02, p06, p25, p15) #srdyx(p03, p07, p24, p32) fsin0(p00) fsout0(p01) #fsclk0(p02) #fsrdy0(p03) p00?7, p10?6 p20?7, p30?5 p40?7, p50?5 p60?3 #smwe(p34) #smre(p35) sdi(p33) sdo(p31) spiclk(p32) S1C33L05 exclx(p10?3, p15, p16) tmx(p22?7) 16-bit programmable timer (6 ch.) a[25:18](p40?47), a[17:1], a0/#bsl d[15:0] #rd #wrl/#wr #wrh/#bsh #ce10ex #ce[9:4](p55?50) #wait(p30) #gaas(p21) #gard(p31) bclk(p60) usbdp usbdm usbvbus s1c33000 interrupt controller prescaler/pll/ selector a/d converter (5 ch.) osc3 osc1 lcdc sdram controller clock timer ram 16kb intelligent dma (128 ch.) high-speed dma (4 ch.) usb 1.1 interface 8-bit programmable timer (6 ch.) serial interface standard (4 ch.) serial interface built-in fifo (1 ch.) input port input port input port pull-up control i/o port pa0?2 pb0?7 pc0?3 pd0?7 extended i/o port nand flash interface sequential rom interface uma vram 40kb squale(pd2) sqlale(pd1) #sqrd(pd0) mmc (spi mode) interface bus control unit cpu core fig. 1 S1C33L05 functional block diagram
6 S1C33L05 89 132 45 88 index 44 1 176 133 S1C33L05 no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 pin name d9 d8 v dde d7 d6 d5 d4 d3 d2 d1 d0 v ss p30 /#wait/#ce4&5/pa2 pd0 /#sqrd pd1 /sqlale pd2 /squale pd3 pd4 pd5 pd6 pd7 v dde p22 /tm0 p23 /tm1 p24 /tm2/#srdy2 p25 /tm3/#sclk2 p26 /tm4/sout2 p27 /tm5/sin2 v ss pb7 /fpdat7 pb6 /fpdat6 pb5 /fpdat5 pb4 /fpdat4 v dd pb3 /fpdat3 pb2 /fpdat2 pb1 /fpdat1 pb0 /fpdat0 pc3 /drdy pc2 /fpshift pc1 /fpline pc0 /fpframe v ss p16 /excl5/#dmaend1/sout3 no. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 pin name p15 /excl4/#dmaend0/#sclk3 n.c. dsio v dde dclk /p14/fosc1 dpco /p13/excl3/t8uf3 dst2 /p12/excl2/t8uf2 dst1 /p11/excl1/t8uf1 dst0 /p10/excl0/t8uf0 v dd #nmi #reset n.c. v ss k60 /ad0 k61 /ad1 k62 /ad2 k63 /ad3 k64 /ad4 test0 av dde k53 /#dmareq2 k52 /#adtrg k51 /#dmareq1 k50 /#dmareq0 v ss osc1 osc2 v dde b urnin scanen test1 n.c. v dd osc3 osc4 v ss p07 /#srdy1/#dmaend3 p06 /#sclk1/#dmaack3 p05 /#sout1/#dmaend2 p04 /#sin1/#dmaack2 p03 /#srdy0/#fsrdy0 p02 /#sclk0/#fsclk0 n.c. no. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 pin name p01 /sout0/fsout0 p00 /sin0/fsin0 usbdp usbdm n.c. usbvbus v dde p31 /#busget/#gard/sdo p32 /#dmaack0/#srdy3/spiclk v ss p33 /#dmaack1/sin3/sdi p34 /#busreq/#ce6/#smwe p35 /#busack/#smre v dd #x2spd ea10md0 ea10md1 v dde pllc v ss plls0 tst boot #ce4 /#ce11/#ce11&12/p50 v ss #ce5 /#ce15/#ce15&16/p51 #ce6 /#ce7&8/p52 # ce7 /#ras0/#ce13/#ras2/p53/#sdce #ce8 /#ras1/#ce14/#ras3/p54 #ce9 /#ce17/#ce17&18/p55 #ce10ex /#ce9&10ex p61 /sda10 p62 /ldqm p63 /udqm p21 /#dwe/#gaas/#sdwe #lcas /pa0/#sdcas v dd #hcas /pa1/#sdras p20 /#drd/sdcke v dde bclk /p60/fosc1/sdclk a25 /p40 v ss a24 /p41 no. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 pin name a23 /p42 n.c. a22 /p43 a21 /p44 a20 /p45 a19 /p46 a18 /p47 a17 a16 v dde a15 a14 n.c. a13 a12 v ss a11 a10 v dd a9 a8 a7 a6 a5 v ss a4 a3 v dde a2 a1 a0 /#bsl #wrh /#bsh n.c. #wrl /#wr/#we #rd v ss d15 d14 d13 d12 d11 v dd d10 n.c. bold : the pin (signal) name of a default setup. pin layout qfp21-176pin fig. 2 pin layout diagram (qfp21-176pin)
7 S1C33L05 basic external connection diagram fig. 3 basic external connection diagram x'tal1 c g1 c d1 rf 1 rd 1 r 1 c 1 c 2 r 2 c 3 crystal resonator gate capacitor drain capacitor feedback resistor drain resistor resistor capacitor capacitor resistor capacitor 32.768 khz 12 pf 12 pf 10 m ? 0 ? 4.7 k ? 100 pf 3 pf 10 ? 1 f x'tal2 or ce c g2 c d2 rf 2 rd 2 resonator gate capacitor drain capacitor feedback resistor drain resistor crystal 3 pf 4 pf 1 m ? 0 ? ceramic (cstcw48m0x11 ???) (6 pf) (6 pf) 22 k ? 47 ? note : ? 1o scillation characteristics vary depending on conditions (components used, board pattern, etc.). the values in the above table are shown only for reference and not guaranteed. in particular, ceramic oscillation is extremely sensitive to influence of external components and printed- circuit boards. before using a ceramic resonator, please be sure to contact murata manufacturing co., ltd. for further information on conditions of use for ceramic resonators. furthermore, this chip supports only 48-mhz ceramic resonators. do not use ceramic resonators with any other frequency. ? 2 capacitance built into the ceramic resonator S1C33L05 [the potential of the substrate (back of the chip) is v ss .] external bus hsdma serial i/o a/d input input i/o timer input/output ? 1: when the pll is not used, leave the pllc pin open. fpframe fpline fpdat[7:0]([7:4]) fpshift drdy sdclk sdcke a[15:14] a12 sda10 a[10:1] d[15:0] udqm ldqm #sdce #sdras #sdcas #sdwe usbdp usbdm usbvbus sdi sdo spiclk #smwe #smre sqlale squale #sqrd a[25:1], a0/#bsl d[15:0] #rd #gard #gaas #wrl/#wr #wrh/#bsh #cexx #ce10ex #wait bclk #busreq #busack #busget #nmi #dmareqx #dmaackx #dmaendx sinx/fsin0 soutx/fsout0 #sclkx/#fsclk0 #srdyx/#fsrdy0 #adtrg adx exclx tmx t8ufx kxx pxx lcd usb (host) nand flash mmc debug interface v dd v dde av dde ea10md0 ea10md1 #x2spd boot pllc plls0 osc3 osc4 osc1 osc2 #reset tst test1 test2 scanen burnin v ss fosc1 dst[2:0] dpco dclk dsio 1.8 v 3.3 v rd 2 rd 1 c d2 x'tal2 or ce rf 2 c g2 c d1 x'tal1 rf 1 c g1 c 2 c 1 r 1 ? 1 + + dp dm vbus di do clk, cs #we #re sq rom alel aleh #rd yd lp xd[7:0]([7:4]) xscl fr sdram (4m x 16) clk cke ba[1:0] a11 a10 a[9:0] dq[15:0] dqmh dqml #cs #ras #cas #we c 3 r 2 ? 1, ? 2 ? 1, ? 2 ? 1 ? 1
S1C33L05 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2004, all right reserved. seiko epson corporation electronic devices marketing & sales div. ed international sales dept. 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 epson electronic devices website document code: 405123500 issue june, 2004 printed in japan l http://www.epsondevice.com
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