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intel ? 810/810e chipsets: gmch electrical and thermal specifications datasheet addendum january 31, 2000 r
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 2 datasheet addendum order number: 298180 - 001
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 3 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? 810 chipset and intel ? 810e chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. i 2 c is a 2-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american philips corporation. alert on lan is a result of the intel-ibm advanced manageability alliance and a trademark of ibm copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation www.intel.com or call 1-800-548-4725 *third-party brands and names are the property of their respective owners. copyright ? intel corporation 2000
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 4 datasheet addendum contents 1. overview ................................ ................................ ................................ ............................. 7 1.1. rel ated documents and references ................................ ................................ .......... 7 2. electrical characteristics ................................ ................................ ................................ ...... 8 2.1. absolute maximum dc ratings ................................ ................................ ................. 8 2.2. thermal characteristics ................................ ................................ ............................ 8 2.3. p ower characteristics ................................ ................................ ............................... 8 2.4. signal groups ................................ ................................ ................................ .......... 9 2.5. dc characteristics ................................ ................................ ................................ . 10 2.6. ac characteristics ................................ ................................ ................................ . 12 2.7. gmch timing diagrams ................................ ................................ ......................... 19 3. gmch dac ................................ ................................ ................................ ...................... 22 3.1. dac dc characteristics ................................ ................................ ......................... 22 3.2. dac reference and output specifications ................................ ................................ 22 3.3. dac ac characteristics ................................ ................................ ......................... 23 4. signal quality specifications ................................ ................................ .............................. 24 4.1. 3.3v signal overshoot/undershoot specification ................................ ....................... 24 4.2. gtl+ signal overshoot/undershoot specification ................................ ...................... 24 4.3. 1.8v s ignal overshoot/undershoot specification ................................ ....................... 24
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 5 figures figure 1. 2.5v clocking interface ................................ ................................ ...................... 19 figure 2. 3.3v clocking interface ................................ ................................ ...................... 19 figure 3. 3.3v clock duty cycle ................................ ................................ ....................... 19 figure 4. valid delay from rising clock edge ................................ ................................ ... 20 figure 5. setup and hold time to clock ................................ ................................ ............ 20 figure 6. float delay ................................ ................................ ................................ ....... 20 figure 7. pulse width ................................ ................................ ................................ ..... 21 figure 9. source synchronous digital video out timings ................................ ..................... 21 tables table 1. power characteristics ................................ ................................ ........................... 8 table 2. gmch signal groups ................................ ................................ ........................... 9 table 3. dc characteristics ................................ ................................ ............................. 10 table 4. clock timings (66/100 mhz) ................................ ................................ ............... 12 table 5. display interface clock timing ................................ ................................ ............. 13 table 6. cpu interface timings for 370-pin socket ................................ ............................. 13 table 7. cpu interface timings for sc242 connector ................................ .......................... 14 table 8. system memory timings (100mhz) ................................ ................................ ...... 15 table 9. display cache memory timings (100 mhz) ................................ ........................... 16 table 11. digital video out: flat panel timings ................................ ................................ .. 17 table 12. flat panel data setup and hold times from clkout ................................ ........... 17 table 13. digital video out: tv out timings ................................ ................................ ....... 18 table 14. tv out data setup and hold times from clkout ................................ ................ 18 table 15. dac dc characteristics ................................ ................................ .................... 22 table 16. dac reference and output specifications ................................ ............................ 22 table 17. dac ac characteristics ................................ ................................ .................... 23 table 18. 3.3v signal quality specification ................................ ................................ ........ 24 table 19. gtl+ signal quality specification ................................ ................................ ....... 24 table 20. 1.8v signal quality specification ................................ ................................ ........ 24
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 6 datasheet addendum revision history rev. description date -001 initial release january 31, 2000
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 7 1. overview this document covers the electrical and thermal specifications (ets) for the graphics and memory controller hub (gmch) components for the intel ? 810 chipset and intel ? 810e chipset. the components covered are: intel ? 810 chipset: intel ? 82810/82810-dc100 graphics and memory controller hub (gmch) intel ? 810e chipset: intel ? 82810e graphics and memory controller hub (gmch) information in this document that is not shaded applies to both devices. information that is shaded, as is shown here, indicates differences between the two devices. 1.1. related documents and references intel ? 810 chipset: intel ? 82810/82810-dc100 graphics and memory controller hub (gmch) datasheet intel ? 810e chipset: intel ? 82810e graphics and memory controller hub (gmch) datasheet intel ? celeron? processor ? datasheets intel ? pentium ? ii processor developer?s manual intel ? pentium ? iii processor datasheets intel ? 810 chipset design guide ck whitney clock synthesizer / driver specification intel ? celeron? processor i/o buffer models whitney i/o buffer models rev 1.3 (ibis format)
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 8 datasheet addendum 2. electrical characteristics unused active low 3.3v tolerant inputs should be connected to 3.3v. unused active high inputs should be connected to ground (vss). 2.1. absolute maximum dc ratings case temperature under bias ................................ ................................ ............................ 0 o c to +105 o c storage temperature ................................ ................................ ................................ ........... -55 o c to +150 o c 3.3v supply voltage with respect to vss (vcc) ................................ ............................ -0.3 to + 4.3 v 1.8v supply voltage with respect to vss ................................ ................................ ...... -0.3 to + 2.5v warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operating beyond the "operating conditions" is not recommended and extended exposure beyond "operating conditions" may affect reliability. 2.2. thermal characteristics the gmch is designed for operation at case temperatures between 0 o c and 105 o c. for thermal considerations and guidelines, refer to the intel a 810 chipset application note #1, thermal design and considerations . 2.3. power characteristics table 1 . power characteristics symbol parameter min max unit notes p gmch total chip power dissipation 4.0 w v cc_1.8 1.8v supply voltage 1.71 1.89 v v cc_3.3 3.3v supply voltage 3.14 3.46 v v sus_3.3 3.3v standby supply voltage 3.14 3.46 v i cc_1.8 1.8v power supply current 1.40 a i cc_3.3_sm 3.3v power supply current for system memory 950 ma i cc_3.3_dc 3.3v power supply current for display cache 250 ma i cc_3.3_dac 3.3v power supply current for ramdac 200 ma i sus_3.3 3.3v standby supply current 110 ma notes: 1. the maximum values of the currents should not be used to calculate the maximum power consumption, since they may not occur at the same time. the p gmch listed above is the maximum power consumption.
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 9 2.4. signal groups to ease discussion of the ac and dc characteristics, the signals on the gmch have been combined into groups with similar characteristics. these signal groups are referenced throughout this document. table 2 . gmch signal groups signal group signal type signals (a) gtl+ i/o ha[31:3]#, hd[63:0]#, ads#, bnr#, dbsy#, drdy#, hit#, hitm#, hreq[4:0]#, htrdy#, rs[2:0]# (b) gtl+ input hlock# (c) gtl+ output cpurst#, bpri#, defer# (d) gtl+ termination voltage gtlref[b:a] (e) cmos (2.5v) input hclk (f) cmos i/o sdqm[7:0], smd[63:0], lmd[31:0], ldqm[3:0] (g) cmos input sclk, reset#, dclkref, lrclk (h) cmos output scs[3:0]#, sras#, scas#, smaa[11:0], sbs[1:0], smab[7:4]#, swe#, scke[1:0], lcs#, lsras#, lscas#, lma [11:0], lwe#, loclk, ltclk (k) cmos (1.8v) input tvclkin/int# (l) cmos (1.8v) output clkout[1:0], blank#, ltvdata[11:0], tvvsync, tvhsync (m) cmos i/od ddcscl*, ddcsda*, ltvcl, ltvda (n) ramdac output red, green, blue (o) display sync output vsync, hsync (p) display reference iref, iwaste notes: 1. ddc inputs are not 5v tolerant.
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 10 datasheet addendum 2.5. dc characteristics table 3 . dc characteristics functional operating range (v c c_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) symbol signal group parameter min max unit notes gtl+ i/o dc characteristics vil_gtl (a,b) gtl+ input low voltage -0.3 gtlref ?0.2 v vih_gtl (a,b) gtl+ input high voltage gtlref +0.2 1.835 v vol_gtl (a,c) gtl+ output low voltage 0.6 v iol_gtl (a,c) gtl+ output low current 36 48 ma gtl_ref (d) gtl+ reference voltage 2/3(1.5v)-2% 2/3(1.5v)+2% v i leak_gtl (a,b) leakage current 10 m a 3.3v cmos i/o signal dc characteristics vil_3.3 (f,g) cmos input low voltage -0.3 0.8 v vih_3.3 (f,g) cmos input high voltage 2.0 vcc_3.3 +0.3 v vol_3.3 (f,h) cmos output low voltage 0.4 v voh_3.3 (f,h) cmos output high voltage 2.4 v iol_3.3 (f,h) cmos output low current 3 ma ioh_3.3 (f,h) cmos output high current -2.0 ma i leak_3.3 (f,g) leakage current 100 m a 1.8v cmos i/o dc characteristics vil_1.8 (j,k) cmos input low voltage -0.3 0.4(vcc1.8max) v vih_1.8 (j,k) cmos input high voltage 0.6(vcc1.8min) 0.3 + (vcc1.8max) v vol_1.8 (j,l) cmos output low voltage 0.1(vcc1.8max) v voh_1.8 (j,l) cmos output high voltage 0.9(vcc1.8min) v iol_1.8 (j,l) cmos output low current 1.0 ma ioh_1.8 (j,l) cmos output high current -1.0 ma i leak_1.8 (j,k) leakage current 10 m a
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 11 functional operating range (v c c_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) symbol signal group parameter min max unit notes cmos i/od signal dc characteristics vil_i/od (m) cmos i/od input low voltage 0.1 0.8 v vih_i/od (m) cmos i/od input high voltage 2.0 v cc_3.3 + 0.1 v vol_i/od (m) cmos i/od output low voltage 0.4 v voh_i/od (m) cmos i/od output high voltage 2.4 v iol_i/od (m) cmos i/od output low current 4 ma i leak_i/od (m) leakage current 100 m a display sync output dc characteristics vol_dis (o) display sync output low voltage 0.4 v voh_dis (o) display sync output high voltage 2.4 v iol_dis (o) display sync output low current 4 ma input/output capacitance cin1 (g) input capacitance 7.5 11.3 pf f c = 1 mhz cin2 (k) input capacitance 6.4 9.8 pf f c = 1 mhz cout1 (h) output capacitance 3.54 6.6 pf f c = 1 mhz cout2 (i) output capacitance 6.4 9.8 pf f c = 1 mhz ci/o1 (f) i/o capacitance 3.54 6.6 pf f c = 1 mhz ci/o2 (j) i/o capacitance 6.4 9.8 pf f c = 1 mhz
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 12 datasheet addendum 2.6. ac characteristics all timings are in nanoseconds (ns), unless otherwise specified. in addition, all the clock-to-output values are specified into 0 pf load, unless otherwise specified. table 4 . clock timings (66/100 mhz) functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) 66 mhz 100 mhz 133 mhz (810e only) sym parameter min max min max min max fig unit notes hclk (host clock) t1a hclk period 15 15.5 10.0 10.5 7.5 8.0 1 ns t1b hclk jitter 250 250 250 1 ps t1c hclk high time 5.2 3.0 1.87 1 ns t1d hclk low time 5.0 2.8 1.87 1 ns t1e hclk slew rate 1.0 4.0 1.0 4.0 1.0 4.0 1 v/ns sclk (system memory clock) t2a sclk period n/a n/a 10 10.5 n/a n/a 1 ns t2b sclk jitter n/a n/a 250 n/a n/a 1 ps t2c sclk high time n/a n/a 3.0 n/a n/a 1 ns t2d sclk low time n/a n/a 3.0 n/a n/a 1 ns t2e sclk slew rate n/a n/a 1.0 4.0 n/a n/a 1 v/ns t2f sclk duty cycle n/a n/a 45% 55% n/a n/a 1 lrclk (display cache receive clock) t3a lrclk period n/a n/a 10 10.5 7.5 8.0 1 ns t3b lrclk jitter n/a n/a 250 250 1 ps t3c lrclk high time n/a n/a 3.0 2.0 1 ns t3d lrclk low time n/a n/a 3.0 2.0 1 ns t3e lrclk slew rate n/a n/a 1.0 4.0 1.0 4.0 1 v/ns t3f lrclk duty cycle n/a n/a 45% 55% 45% 55% 1 ltclk (display cache transmit clock) t4 ltclk period n/a n/a 10 10.5 7.5 8.0 1 ns t5 loclk period n/a n/a 10 10.5 7.5 8.0 1 ns notes: 1. ac specifications are measured at the gmch.
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 13 table 5 . display interface clock timing functional operating range (v cc_1.8 = 1.8v 5%, v c c_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) 48 mhz fig unit notes symbol parameter min max dclkref (display interface clock) (must be non-spread spectrum modulated) t6a dclkref period 20.83 24.31 2 ns t6b dclkref jitter 500 2 ps t6c dclkref high time 9.2 2 ns t6d dclkref low time 9.2 2 ns t6e dclkref slew rate 1.0 4.0 2 v/ns t6f dclkref duty cycle 45% 55% 2 table 6 . cpu interface timings for 370-pin socket (intel ? 810 chipset) functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) 66 mhz 100 mhz symbol parameter min max min max fig unit notes t7 valid delay from hclk rising (tco) 1.27 7.0 1.27 5.35 4 ns t8 input setup time to hclk rising (tsu) 2.72 2.72 5 ns t9 input hold time from hclk rising (thld) 0.10 0.10 5 ns table 7 . cpu interface timings for 370-pin socket (intel ? 810e chipset) functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) 66 mhz 100mhz 133mhz sym parameter min max min max min max fig unit notes t7 valid delay from hclk rising (tco) 1.05 4.10 1.05 4.10 1.05 4.10 4 ns t8 input setup time to hclk rising (tsu) 2.65 2.65 2.65 5 ns t9 input hold time from hclk rising (thld) 0.10 0.10 0.10 5 ns
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 14 datasheet addendum table 8 . cpu interface timings for sc242 connector (intel ? 810 chipset) functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) 66 mhz 100 mhz sym parameter min max min max fig unit notes t7_s valid delay from hclk rising (tco) n/a n/a 0.50 4.50 4 ns t8_s input setup time to hclk rising (tsu) n/a n/a 2.27 5 ns t9_s input hold time from hclk rising (thld) n/a n/a 0.28 5 ns table 9 . cpu interface timings for sc242 (intel ? 810e chipset) functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) 66 mhz 100mhz 133mhz sym parameter min max min max min max fig unit note s t7_s valid delay from hclk rising (tco) 0.50 3.63 0.50 3.63 0.50 3.63 4 ns t8_s input setup time to hclk rising (tsu) 2.27 2.27 2.27 5 ns t9_s input hold time from hclk rising (thld) 0.28 0.28 0.28 5 ns
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 15 table 10 . system memory timings (100mhz) functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) 1x buffer 2x buffer 3x buffer 4x buffer sym parameter min max min max min max min max units notes t10 we# valid delay from sclk rising 1.15 4.70 1.05 4.30 1.05 4.30 n/a n/a ns 0pf t11 sras# valid delay from sclk rising 1.15 4.70 1.05 4.30 1.05 4.30 n/a n/a ns 0pf t12 scas# valid delay from sclk rising 1.15 4.70 1.05 4.30 1.05 4.30 n/a n/a ns 0pf t13 cs[3:0]# valid delay from sclk rising n/a n/a 1.05 4.30 1.05 4.30 n/a n/a ns 0pf t14 maa[11:8, 3:0], bs[1:0], valid delay from sclk rising 1.15 4.70 1.05 4.30 1.05 4.30 n/a n/a ns 0pf t15 cke[1:0] valid delay from sclk rising n/a n/a 0.95 3.60 0.96 3.55 0.91 3.52 ns 0pf t16 maa/b[7:4]# valid delay from sclk rising 1.15 4.00 0.95 3.55 0.96 3.55 0.91 3.51 ns 0pf 1.0x buffer 1.5x buffer 2.5x buffer sym parameter min max min max min max units notes t17 dqm[7:0] valid delay from sclk rising 1.24 4.60 1.38 4.95 1.17 4.40 ns 0pf t18 md[63:0] valid delay from sclk rising 1.24 4.60 1.38 4.95 1.17 4.40 ns 0pf sym parameter min max units notes t19 md[63:0] setup time to sclk rising 0.50 ns 0pf t20 md[63:0] hold time from sclk rising 1.10 ns 0pf
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 16 datasheet addendum table 11 . display cache memory timings (100 mhz) functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) symbol parameter 100 mhz 133 mhz (810e only) units figure notes min max min max t21 lcs[1:0]# valid delay from ltclk rising 3.10 4.60 1.90 3.30 ns 4 0pf t22 ldqm valid delay from ltclk rising 3.10 4.60 1.90 3.30 ns 4 0pf t23 lsras# valid delay from ltclk rising 3.10 4.60 1.90 3.30 ns 4 0pf t24 lscas# valid delay from ltclk rising 3.10 4.60 1.90 3.30 ns 4 0pf t25 lma[11:0] valid delay from ltclk rising 3.10 4.60 1.90 3.30 ns 4 0pf t26 lwe# valid delay from ltclk rising 3.10 4.60 1.9 3.30 ns 4 0pf t27 lmd[31:0] valid delay from ltclk rising 3.10 4.60 1.9 3.30 ns 4 0pf t28 lmd[31:0] setup time to lrclk rising 0.5 0.5 ns 5 0pf t29 lmd[31:0] hold time to lrclk rising 1.0 1.0 ns 5 0pf
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 17 table 12 . digital video out: flat panel timings functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) symbol parameter min max units figure notes t42 ltvdata[11:0], blank#, tvvsync, tvhsync valid before clkout[1:0], ttdvb see table 11 ns 9 1 t43 ltvdata[11:0], blank#, tvvsync, tvhsync valid after clkout[1:0], ttdva see table 11 ns 9 1 receiver timing n/a int# asynchronous n/a ns notes: 1. the output valid delay is measured into a 60 ohm transmission line load and is frequency dependent. table 13 . flat panel data setup and hold times from clkout clkout (mhz) ttdvb (min) (ns) ttdva (min) (ns) 20 10.75 10.95 25 8.40 8.60 30 6.85 7.05 35 5.74 5.94 40 4.90 5.10 45 4.25 4.45 50 3.73 3.93 55 3.30 3.50 60 2.95 3.15 65 2.65 2.85 70 2.39 2.59 75 2.16 2.36 80 2.01 2.21 85 1.80 2.00
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 18 datasheet addendum table 14 . digital video out: tv out timings functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) symbol parameter min max units figur e notes t44 ltvdata[11:0], blank#, tvvsync, tvhsync valid before clkout[1:0], ttdvb see table 15 ns 9 1 t45 ltvdata[11:0], blank#, tvvsync, tvhsync valid after clkout[1:0], ttdva see table 15 ns 9 1 receiver timing tvclkin @ 20-40 mhz t46a tvclkin period 11.75 50 ns t46b tvclkin jitter 300 ps t46c tvclkin high time 3.0 ns t46d tvclkin low time 3.0 ns t46e tvclkin rise time 0.4 2.0 ns t46f tvclkin fall time 0.4 2.0 ns notes: 1. the output valid delay is measured into a 60 ohm transmission line load and frequency dependent. table 15 . tv out data setup and hold times from clkout clkout (mhz) ttdvb (min) (ns) ttdva (min) (ns) 20 10.75 10.95 25 8.40 8.60 30 6.85 7.05 35 5.74 5.94 40 4.90 5.10
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 19 2.7. gmch timing diagrams figure 1 . 2.5v clocking interface hclk 1.7v 0.7v period high time low time slew rate slew rate 1.25v 1.7v 0.7v 1.7v 0.7v 1.25v figure 2 . 3.3v clocking interface sclk dclkref 2.0v 0.8v period high time low time slew rate slew rate 1.5v 2.0v 0.8v 2.0v 0.8v 1.5v figure 3 . 3.3v clock duty cycle clock (3.3v) 1.5v 1.5v duty cycle max duty cycle min note: applies to all 3.3v clocks.
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 20 datasheet addendum figure 4 . valid delay from rising clock edge clock vtclock valid delay vtsignal output figure 5 . setup and hold time to clock clock input hold time setup time vtclock vtsignal figure 6 . float delay clock output float delay vtsignal vtclock
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 21 figure 7 . pulse width pulse width vtsignal vtsignal figure 8 . source synchronous digital video out timings tdvb tdva clkout1 clkout0 ltvdata
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 22 datasheet addendum 3. gmch dac the gmch dac (digital-to-analog converter) consists of three identical 8-bit dacs to provide red, green and blue color components. each dac can output a current from 0 to 255 units of current, where one unit of current (lsb) is defined based on the vesa video signal standard. 3.1. dac dc characteristics table 16 . dac dc characteristics functional operating range (v cc_1 .8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) parameter min typical max unit notes dac resolution 8 bits ile (integral linearity error) -1.0 +1.0 lsb dle (differential linearity error) -1.0 +1.0 lsb 1 full scale (gain) error -5.0 +10.0 % of full scale dac full scale voltage 665 700 770 mv vesa video level lsb current 73.2 ua monotonicity guaranteed notes: 1. guaranteed by design characterization 3.2. dac reference and output specifications table 17 . dac reference and output specifications functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) parameter description note reference resistor (connected to iref pad) 174 w for vesa standard output load double termination required with 75 w (effective resistance 37.5 w ) video filter pi filter: ferrite bead (75 w @ 100 mhz) and two 3.3 pf capacitors apply to each ramdac output
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r datasheet addendum 23 3.3. dac ac characteristics table 18 . dac ac characteristics functional operating range (v cc_1.8 = 1.8v 5%, v cc_3.3 / v sus_3.3 = 3.3v 5%; t case = 0 o c to + 105 o c) parameter min typical max unit notes pixel clock rate 250 mhz rgb video output rise time (10-90% of full-scale) no load 0.23 0.52 ns rgb video output rise time (10-90% of full-scale) 0.8 3.0 ns 1 rgb video output fall time (10-90% of full-scale) no load 0.57 1.55 ns rgb video output fall time (10-90% of full-scale) 1.35 2.5 ns 1 glitch energy/clock feed through 200 pv-s 2 notes: 1. as measured at the vga connector 2. black to white level transition with 37.5 w load. spec guaranteed by design characterization
intel ? 810/810e chipsets: gmch electrical and thermal characteristics r 24 datasheet addendum 4. signal quality specifications 4.1. 3.3v signal overshoot/undershoot specification table 19 . 3.3v signal quality specification symbol parameter max time duration note vos_max absolute maximum overshoot vcc_3.3 + 1.5v n/a 1 vus_max absolute maximum undershoot ? 1.5v n/a 1 vos overshoot voltage magnitude vcc_3.3 + 1v 2ns vus undershoot voltage magnitude ?1v 2ns notes: 1. the signal voltage must not exceed the absolute maximum overshoot/undershoot voltag e 4.2. gtl+ signal overshoot/undershoot specification table 20 . gtl+ signal quality specification symbol parameter max time duration note vos_max absolute maximum overshoot vcc_1.8 + 1v n/a 1 vus_max absolute maximum undershoot ? 1v n/a 1 notes: 1. the signal voltage must not exceed the absolute maximum overshoot/undershoot voltage 4.3. 1.8v signal overshoot/undershoot specification table 21 . 1.8v signal quality specification symbol parameter max time duration note vos_max absolute maximum overshoot vcc_1.8 + 1v n/a 1 vus_max absolute maximum undershoot ? 1v n/a 1 notes: 1. the signal voltage must not exceed the absolute maximum overshoot/undershoot voltage

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