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mp44010 boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 1 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the mp44010 is a boundary conduction mode pfc controller which can provide simple and high performance active power factor correction using minimum external components. the output voltage is accurately regulated by a high performance voltage mode amplifier with an accurate internal voltage reference. the precise adjustable output over-voltage protection greatly enhances the system reliability. the on-chip r/c filter on the current sense pin can eliminate the external r/c filter. the extremely low start-up current, quiescent current and the disable function can reduce the power consumption and result in excellent efficiency performance. the mp44010 is available in soic8 and dip packages. features ? boundary conduction mode pfc controller for pre-regulator ? zero-crossing compensation to minimum thd of ac input current ? precise adjustable output over-voltage protection ? ultra-low (15 a) start-up current. ? low (0.46ma) quiescent current ? on-chip filter on current sense pin ? disable function ? -600/+800ma peak gate drive current ? available in soic8 and dip-8 packages applications ? offline adaptor ? electronic ballast ? llc front end ? other pfc pre-regulators all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc. other patents pending. typical application
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 2 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number package top marking junction temperature (t j ) mp44010hs * soic8 mp44010 -40 c to +125 c MP44010HP ** dip8 mp44010 -40 c to +125 c * for tape & reel, add suffix ?z (e.g. mp44010hs?z). for rohs compliant packaging, add suffix ?lf (e.g. mp44010hs?lf?z) ** for rohs compliant packaging, add suffix ?lf (e.g. MP44010HP?lf) package reference fb comp mult cs vin gate gnd zcs 1 2 3 4 8 7 6 5 top view absolute maxi mum ratings (1) supply voltage v in ..........................-0.5v to 22v analog inputs and outputs ...............-0.3v to 8v zcs max. current.......................-50ma to 10ma continuous power dissipation (t a = +25c) (2) soic8 ........................................................ 1.4w dip8????????????????..1.2w junction temperature??????? ?..150 c lead temperature (solder).......................260 c storage temperature............... -55 c to +150 c recommended operating conditions (3) supply voltage v in .........................13.4v to 22v analog inputs and outputs .............-0.3v to 6.5v maximum junction temp. (t j ). ...............+125 c thermal resistance (4) ja jc soic8 .....................................90 ...... 45 ... c/w dip8 .......................................105 ..... 45 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by d(max)=(t j (max)-t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circui try protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 3 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v in = 15v, t a = t j = +25 c, unless otherwise noted parameter symbol condition min typ max units supply voltage operating range v in after turn on 10.7 22 v turn on threshold v in_on 11 12.4 13.4 v turn off threshold v in_off 8.7 9.8 10.7 v hysteresis v in_hys 2.2 3 v zener voltage v z i in =20ma 22 25 28 v supply current start-up current i startup v in =11v 15 40 a quiescent current i q no switch 0.46 0.65 ma operating current i cc f s =70khz, c load =1nf 1.6 2.5 ma multiplier input bias current i mult -1 a linear operation range v mult 0 to 3 v output max. slope v cs / v mult 1.62 1.85 v/v gain (5)(6) k 0.64 0.82 1/v error amplifier feedback voltage v fb 2.465 2.5 2.535 v feedback voltage line regulation v fb_lr vin=10.7v to 22v 2 5 mv feedback bias current i fb 0.2 a open loop voltage gain g v 60 80 db gain-bandwidth product gb 1 mhz source current i comp_source -2 -4 -5 ma sink current i comp_sink 2.5 5.5 ma upper clamp voltage v comp_h 5.3 6 6.6 v lower clamp voltage v comp_l 2. 2.2 2.4 v current sense comparator input bias current i cs -1 a delay t dt 300 450 ns current sense clamp voltage v cs_clamp 1.6 1.72 1.83 v v mult =0v 30 mv current sense offset v cs_offset v mult =2.5v 5 mv zero current sensor upper clamp voltage v zcsclamp_h i zcs =2.5ma 7.2 7.8 8.3 v
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 4 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics (continued) v in = 15v, t a = t j = +25 c, unless otherwise noted. parameter symbol condition min typ max units lower clamp voltage v zcsclamp_l i zcs =-2.5ma 0.3 0.55 0.8 v v zcs_h v zcs rising 2.1 2.3 v zero current sensing threshold v zcs_l v zcs falling 1.15 1.35 v zcs_en threshold v zcs_en_r v zcs rising 310 mv zcs_en hysteresis v zcs_en_hys 120 mv source current capability i zcs_source 3 ma restart current after disable i zcs_res 60 85 a re-starter re-start time t start 80 175 280 s over-voltage dynamic ovp current i ovp 30 40 50 a hysteresis i ovp_hys 30 a static ovp threshold v ovp 2 2.2 2.4 v gate driver i gdsource =20ma 2.4 2.7 v v oh i gdsource =200ma 3.9 5.1 v dropout voltage v ol i gdsink =200ma 0.5 1.5 v voltage fall time t f 30 70 ns voltage rise time t r 40 80 ns max output drive voltage v d_max 12 13.5 15 v source current capability i gate_source -600 ma sink current capability i gate_sink 800 ma uvlo saturation voltage v saturation v in =0 to v in_on , i gate_sink =10ma 0.3 v note: 5) the multiplier output is given by: v cs =kv mutl (v comp -2.5) 6) guaranteed by design.
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 5 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 6 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performance characteristics ( continued )
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 7 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performance characteristics ( continued ) performance waveforms are generated using the evaluation board built with design example on page 11. v ac =220v, v out =400v, p out =100w, t a =25 o c, unless otherwise noted. v out ac coupled 10v/div. i l 1a/div. steady state p out =100w v rec 200v/div. v out ac coupled 10v/div. i l 1a/div. v rec 200v/div. v out ac coupled 10v/div. i l 1a/div. v rec 200v/div. steady state p out =50w steady state p out =0w v out 200v/div. v rec 100v/div. i ac 10a/div. v out 200v/div. v rec 100v/div. i ac 2a/div. startup shutdown v gate 20v/div. v zcs 50v/div. i l 1a/div. zero-current sensing v rec 10v/div. v gate 20v/div. i l 1a/div. zero-crossing compensation v ac =85v harmonics 0 5 10 15 20 25 30 35 311 192735 harmonic order harmonic ratio mp44010 design example iec1000-3-2 class c
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 8 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions pin # name description 1 fb feedback pin. the output voltage is fed in to this pin through a resistor divider. 2 comp output of the error amplifier. a compensati on network is connected between this pin and fb pin. 3 mult input of the multiplier. connect this pin to the rectified main voltage via a resistor divider to provide the sinusoidal reference for the current control loop. 4 cs current sense pin. the current through mosfet is fed into this pin via a resistor. the resulting voltage on this pin is compared with th e output of internal multiplier to get an internal sinusoidal-shaped reference, to determine mosfet ?s turn-off. on-chip r/c filter can reduce high frequency noise on this pin. 5 zcs inductor?s zero-crossing current sensing inpu t. a negative-transition edge triggers mosfet?s turn-on. 6 gnd ground. 7 gate gate driver output. the high output current of t he gate driver is able to drive low-cost power mosfet. the high-level voltage of this pin is clamped to 12v in case this pin is supplied with a high vcc. 8 vin supply voltage of both the signal path of the ic and the gate driver. a bypass capacitor from this pin to ground is needed to reduce noise. block diagram 2.5v + - fb comp mult cs + - uvlo vref zcs gate vin gnd multiplier + - overvoltage detection r sq + - 2.1v 1.35v disable starter driver voltage regulator 150k 2pf figure 1?functional block diagram
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 9 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation the mp44010 is a boundary conduction mode pfc controller which is optimized for the pfc pre-regulator up to 300w and fully complies with the iec1000-3-2 specification. output voltage regulation the output voltage is sensed at the fb pin through a resistor divider from output voltage to ground. the accurate on-chip reference voltage and the high performance error amplifier regulate the output voltage accurately. over-voltage protection (ovp) the mp44010 offers two stages of over-voltage protection: dynamic over-voltage protection and static over-voltage protection. with two-stage protection, the circuit can operate reliably. the mp44010 achieves ovp by monitoring the current flow through the comp pin. at steady-state operation, the current flow through high-side feedback resistor r9 and low- side feedback resistor r10 is: ofb fb r9 r10 vv v ii r9 r10 ? === if there is an abrupt rise on the output ( v o ), and the compensation network connected between fb pin and comp pin takes time to achieve high power factor (pf) due to the long rc time constant. the voltage on fb pin will still be kept at the reference value. the current through r10 remains equal to v fb /r10, but the current through r9 will become: ' oofb r9 vvv i r9 + ? = this current has to flow into the comp pin. at the same time, this current is monitored inside the chip. if it rises to 35a, the output voltage of the multiplier will be forced to decrease and the energy delivering to output will be reduced. if this current continues to rise to about 40a, the dynamic ovp could be triggered. consequently, the gate driver is blocked to turn off the external power mosfet and the device enters an idle state. this state is maintained until the current falls below 10a, the point at which, the internal starter will be re-enabled and allows the switching to restart. when the load is very light, the output voltage tends to stay steadily above the nominal value. in this condition, the error amplifier output will saturate low. when the error amplifier output is lower than 2.2v, static ovp will be triggered. consequently, the gate driver will be blocked to turn off the external power mosfet and the device enters an idle state. normal operation is resumed once the error amplifier output goes back into the regulated region. 2.5v + - fb comp mult uvlo gate multiplier overvoltage detection driver vo r9 r10 i r9 i r10 figure 2?ovp detector block disable function the mp44010 can be disabled by pulling the zero current sensing (zcs) pin lower than 190mv. this can help to further reduce quiescent current when the pfc pre-regulator needs to be shutdown. after releasing the zcs pin, it will stay at lower clamp voltage when there is no external voltage from auxiliary winding. boundary conduction mode zcs gate r sq + - 2.1v 1.35v disable starter driver v aux figure 3?zcs, triggering and disable block
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 10 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. when the current of the boost inductor reaches zero, the voltage on the inductor will be reversed. then zcs generates the turn-on signal of the mosfet by sensing the falling edge of the voltage on the auxiliary winding coupled with the inductor. if the voltage of the zcs pin rises above 2.1v, the comparator waits until the voltage falls below 1.35v. once the voltage falls below 1.35v, the mp44010 turns on the mosfet. the 7.8v high clamp and 0.55v low clamp protect the zcs pin. the internal 175s timer generates a signal to turn on the mosfet if the driver signal has been low for more than 175s. this also allows the mosfet to turn on during start-up period since no signal is generated from zcd then. zero-crossing compensation the mp44010 offers 30mv voltage offset for multiplier output near the zero-crossing of the line voltage which can force the circuit to process more energy at the bottom of the line voltage. with this function, the thd of the current could be evidently reduced. to prevent redundant energy, this offset is reduced as the instantaneous line voltage increases. therefore the offset will be negligible near the top of the line voltage. power factor correction the mp44010 senses the inductor current through the current sense pin and compares to the sinusoidal-shaped signal which is generated from the output of the multiplier. when the external power mosfet turns on, the inductor current rises linearly. when the peak current hits the sinusoidal-shaped signal, the external power mosfet begins to turn off and the diode turns on. the inductor current also begins to fall. when the inductor current reaches zero, the power mosfet begins to turn on again, which causes the inductor current to start rising again. the power circuit works in boundary conduction mode, and the envelope of the inductor current is sinusoidal-shaped. the average input current is half of the peak current, so the average input current is also sinusoidal-shaped. a high power factor can be achieved through this control method. multiplier output inductor current input average current figure 4?inductor current waveform the control flow chart of the mp44010 is shown in figure 5. turn on latch off ic very low consumption vcc > 12.4v y n comp clamp to 2.2v monitor vcc monitor v comp monitor ?i comp vcc< 9.5 v y n v comp <2.2v burst operation ea output goes back to linear region? n y 2.5v< v comp <5.7v ?i comp <37ua continuous operation 37ua< ?i comp <40ua ?i comp >40ua ovp step 1: the mult output is forced to decrease ovp step 2: gate driver is off ?i comp <10ua y n ic is disabled. very low consumption v zcd <190mv? y n figure 5?control flow chart
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 11 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. layout guide for boundary mode pfc operation, the output is fed back to fb pin and is compared with the reference voltage. so a constant reference voltage is very important for output voltage accuracy. therefore, the wire from fb pin to the feedback resistors should be as short as possible. the envelope of the inductor current is from the multiplier output which is generated by rectified ac voltage. therefore a good layout should keep mult pin immune to noise. it is recommended that placing a small ceramic cap from mult pin to gnd. for zero current sensing, r5 should be placed close to zcs and a long connection wire should be avoided. if the long wire is necessary, a small bypass cap is needed to avoid noise. for inductor current sensing, although there is on-chip filter on cs pin, it is still recommended that the wire from current sensing resistor to cs pin should be as short as possible to prevent falsely turning off mosfet. if it is difficult to achieve using short wire, an external filter from sensing resistor to cs pin is recommended. to keep the chip operating with a stable vin voltage, a big e-cap and a small ceramic cap are good combination as vin caps. in addition, the vin caps should be close to vin pin to prevent vin voltage fluctuation. please see the mp44010 demo board for recommended layout. design example case 1: below is a design example following the application guideline for the specifications: v ac 85~265v v out 400v p out 100w the detailed application schematic is shown in figure 6. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more possible applications of this device, please refer to related evaluation board datasheets. figure 6?100w mp44010 design example
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 12 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. case 2: at light load, the power loss can be saved by inserting ln60a01 to disconnect the resistor of voltage divider. the implement circuit is shown in the figure 7. at light load, the pin 9 of hr1000 is asserted low when it operates at burst mode, and the signal generated from pin 9 is applied to synchronize the on/off of mp44010; it also can drive ln60a1 to connect or disconnect resistor of voltage divider at the same time. and the control signal of ln60a01 also can be external signal from mcu system. for more details, please refer to an of mp44010. vcc mp44010 hr1000 ac input gnd vbus ln60a01 control signal 7 7 3 1 5 1 8 5 6 7 4 3 1 2 9 figure 7?power consumption reduction with ln60a01
mp44010 ? boundary mode pfc controller mp44010 rev. 1.11 www.monolithicpower.com 13 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation aa. 6) drawing is not to scale. 0.010(0.25) bsc gauge plane
mp44010 ? boundary mode pfc controller notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp44010 rev. 1.11 www.monolithicpower.com 14 10/17/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. dip8 note: 1) control dimension is in inches . dimension in bracket is in millimeters . 2) package length and width do not include mold flash , or protrusions. 3) drawing conforms to jedec ms- 001, variation ba. 4) drawing is not to scale. 0.008(0.20) 0.014(0.36) 0.240(6.10) 0.260(6.60) pin 1 id 0.050(1.27) 0.065(1.65) 0.367(9.32) 0.387(9.83) top view front view side view 1 4 85 0.300(7.62) 0.325(8.26) 0.320( 8.13) 0.400(10.16) 0.125(3.18) 0.145(3.68) 0.120(3.05) 0.140(3.56) 0.015(0.38) 0.021(0.53) 0.100(2.54) bsc 0.015(0.38) 0.035(0.89)

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