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features: controls bipolar and unipolar stepper motors step modes: full, 1/2, 1/4, 1/8, 1/16 and 1/32 pwm outputs for external h-bridge drivers precision dac reference for pwm sense comparators fast, slow and mixed decay modes power saving holding torque for idling motor automatic switching to holding torque with programmable delay when motor idles programmable delay for sense input blanking programmable delay for mixed decay cycles input for step command input for direction control input for reset to home input for disabling pwm outputs input/output for external clock or built -in oscillator supply current < 400ua supply voltage 4.5v to 5.5v LS8292 (dip), LS8292-s (soic), LS8292- ts (tssop) ls8293 (dip), ls8293-s (soic), ls8293- ts (tssop) description: LS8292 and ls8293 are stepper motor controllers with selectable resolutions from full to 1/32 step. there are four phase drive outputs and two inhibit outputs for controlling 2- phase bipolar or 4-phase unipolar motors. these outputs are designed to drive two external h-bridge drivers for bipolar motor windings or four external transistors for center-tapped unipolar motor windings. these outputs can also be configured to drive discrete external transistors for bipolar motor windings. a lookup table sources the pwm duty cycle digital data for the two motor windings corresponding to the step sequence. two internal dacs convert the pwm data to analog voltages as percentages of the reference voltage applied at the vref input. currents through the motor windings are monitored at the sense inputs as voltage drops across fractional-ohm resistors in series with the h -bridge drivers. upon turning on a pwm drive, when the voltage at the sense input reaches the dac reference level, the pwm output is switched off for remainder of the cycle. the pwm cycle is fixed at tpwm = 256/fc, where fc is the clock frequency at the xtli input. the pwm cycles for the two drives are started simultaneously but terminated separately per individual dac references. an input is provided for the holding torque state at lower winding current in the motor idle state. the holding-torque current level is adjusted with a separate reference voltage applied at the vrefh input. the vrefh is automatically switched in if the motor idles for a programmable specified delay following a micro-step. pwm chopping can be applied either to the phase or to the inhibit outputs. the chopping mode affects the manner in which the winding current decays during a pwm cycle. there are four selectable decay modes: fast-decay, slow- decay, single-mixed-decay and dual-mixed-decay. in the fast -decay mode the diagonal high side and low side transistors of the h-bridge are both turned off during the pwm off period. this causes the inductive current to be dissi pated through the bypass diodes in a direction opposing the motor supply voltage resulting in fast decay. in the slow -decay mode the low side transistor of the h-bridge is turned off keeping the high side transistor on during the pwm off period. this causes the inductive current to re-circulate through the high side transistor and diode loop. the current decays slowly because of the low loop voltage. the slow-decay can be useful for motors that do not store enough energy in the windings leading to an average current too low for any useful torque. in the single -mixed-decay mode, slow and fast decays are combined in the following way: ? when the motor is idle, slow decay is applied to both windings to guarantee lowest current ripple in a holding stat e. ? when the motor is stepping, if the step requires the current in a winding to decrease, fast decay is applied to the winding for a programmable duration followed by slow decay. if the step requires the current in a winding to increase, slow decay is applied to the winding. in dual -mixed-decay mode, mixed decay is applied to both windings for every step with fast decay being followed by slow decay. lsi/csi lsi computer systems, inc. 1235 walt whitman road, melville, ny 11747 (631) 271 - 0400 fax (631) 271 - 0405 LS8292 ls8293 preliminary micro-stepping motor controller june 201 3 8292 -0614 13 -1
one of six stepping modes can be selected by two input pins: full, 1/2, 1/4, 1/8, 1/16 and 1/32. an internal oscillator generates the system clock and sets the pwm period. the oscillator pin can also be driven by an external clock. other available inputs are for step command, direction control, resetting to home position, disabling the h-bridge drives, sense input blanking delay control and fast to slow switching delay control in the mixed decay modes. input/output description: xtli, xtlo a crystal connected between these two pins sets the system clock frequency. alternatively, xtli pin can be driven by an external clock for providing the system clock. the pwm period tpwm, is related to the system clock frequency as follows: tpwm = 256/fc, where, fc is the system clock frequency applied at the xtli input. m0, m1 m0 is a 3-state input amd m1 is a 2 -state input; together they select the step mode as follows: table 1 m1 m0 step mode 0 0 full step 1 0 1/2 step 0 float 1/4 step 1 float 1/8 step 0 1 1/16 step 1 1 1/32 step reset / when low, reset/ input clears the step pointer to home position per table 4. this input has an internal pull-up resistor. step/ a low pulse at the step/ input causes the motor to advance one step forward or reverse. the step size is selected per table 1. fw d when high, the fw d input causes the motor to step in the forward direction per incremental step sequence of table 4. when low, the motor steps in the reverse direction per decremental step sequence of table 4. en / when high, en/ input causes all motor drive outputs to be disabled bringing inh1/, inh2/, pha, phb, phc and phd low. when enable/ is low, all motor drive outputs are enabled. home/ home/ is an open drain output to indicate step0 per table 4 with an active low. vref input for the chopper circuit dac reference voltage. it regulates the peak motor winding current by regulating the pwm duty cycle. the dac modifies the vref input voltage for the current sensing comparators at every sequential motor step which can be estimated with the following equations: vsens1 = | (vref/7) x cos((90/32) x (n + 16))o | vsens2 = | (vref/7) x sin((90/32) x (n + 16))o | where, n is the 1/32 column step number in table 6. the sense resistors should satisfy the relation: rs1 = rs2 = vref/( 7 x imax) where, imax is the maximum motor winding current and rs1 and rs2 are the fractional-ohm sense resistors in series with each phase of the h-bridge driver transistors. vrefh input for the holding torque reference voltage when the holding torque mode is enabled. the holding torque reference voltage should satisfy the relation: vrefh = 7 x rs1 x imaxh = 7 x rs2 x imax h, where, imaxh is the maximum winding current intended in the holding state and rs1 and rs2 are the fractional ohm sense resistors in series with each phase of the h-bridge driver transistors. sense1, sense2 inputs for motor winding current sense. a fractional-ohm resistor connected in series with each of the h-bridge drivers produce sense1 and sense2 voltages. these voltages are compared with the dac modulated reference voltages for generating the pwm phase or inhibit outputs. pha, phb, phc, phd phase drive outputs for power stages. in a bipolar motor, pha and phb are used for one h-bridge while phc and phd are used for the other. in the slow-decay mode the phase outputs are chopped by means of the current sense comparators. in the fast-decay mode the phase outputs are kept enabled while the inhibit outputs are chopped. inh1/, inh2/ these outputs are active low inhibit controls for motor drive outputs. inh1/ controls driver stage using pha and phb outputs while inh2/ controls driver stage using phc and phd outputs. in the f ast-decay mode inhibit outputs are chopped by means of the current sense comparators. in the slow-decay mode the inhibit outputs are enabled while the phase outputs are chopped. sync/ this open drain output produces a negative-going pulse occurring at the beginning of every pwm cycle which can be use to drive an external slope compensation circuit. slope compensation may be useful at pwm duty cycle exceeding 50%, particularly in the fast-decay mode. tblnk a resistor-capacitor pair connected to the tblnk input controls the delay for which the sense input sampling is inhibited at the beginning of each pwm cycle. the delay is given by: tblnk = 1.2 x rbcb where, rb and cb are the resistor and the capacitor connected to the tblnk pin. thld a resistor-capacitor pair connected to this pin produces the holding torque initiation delay following a step command. upon delay timeout the normal torque reference voltage vref is switched out from the sense comparators, being replaced with the holding torque reference voltage vrefh. the holding torque at lower dissipation prevails as long as the motor remains idle. the delay is given by: thld = 1.4 x rhch 8292 - 021811 - 2
where, rh and ch are the resistor and the capacitor connected to the thld pin. if the pin is tied low, holding torque mode is disabled and normal torque prevails in both dynamic and idle motor states. dcym, tdcyd, tdcyu dcym and tdcyd inputs control the pwm decay modes for the LS8292 as follows: dcym, tdcyd and tdcyu inputs control the pwm decay modes for the ls8293 as follows: table3 dcym tdcyd tdcyu decay mode 1 0 x fast 1 1 x slow 0 rdcd 0 single - mixed 0 rdcd rucu dual - mixed fast-decay. phase output are enabled while inhibit outputs are chopped in both dynamic and idle motor states. slow-decay . inhibit output are enabled while phase outputs are chopped in both dynamic and idle motor states. single-mixed-decay . following a stepping event, if the step requires the current in a winding to decrease, fast decay is applied to the winding for a programmable duration followed by slow decay. the duration is given by: tdcyd = 1.2 x rdcd, where rd and cd are the resistor and the capacitor connected to the tdcyd pin. if the step requires the current in a winding to increase, slow decay is applied to the winding. if motor is idle, slow decay is applied to both winding s. dual-mixed-deacy. following a stepping event fast decay is applied to both windings for programmable durations followed by slow decay. the duration of the fast decay for the winding requiring lower current following a stepping event is given by: tdcyd = 1.2 x rdcd and the duration of the fast decay for the winding requiring higher current following a stepping event is given by: tdcyu = 1.2 x rucu. ru and cu are the resistor and the capacitor connected to the tdcyu pin. if motor is idle, slow decay is applied to both winding s. vdd supply voltage positive terminal. dgnd supply negative terminal for digital ground. agnd analog ground; must be connected together with dgnd on the pcb. table 2 dcym tdcyd decay mode 1 0 fast 1 1 slow 0 rdcd single - mixed pin assignment top view 24 1 2 3 4 5 6 7 8 9 10 11 12 m0 m1 dcym reset/ vref dgnd xtli xtlo home/ en/ fwd step/ ls8293 13 14 15 16 17 18 19 20 21 22 23 24 agnd sense2 sense1 tdcyd tblnk phd phc phb pha inh2/ inh1/ vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LS8292 m0 m1 dcym step/ reset/ fwd en/ home/ xtlo xtli dgnd sync/ tdcyu thld 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vrefh vref agnd sense2 sense1 tdcyd tblnk phd phc phb pha inh2/ inh1/ vdd 8292 - 021811 - 3 24 phd
mode select m0 m1 step control & look - up table vdd reset/ step/ fwd home/ xtli xtlo mux vr vref vrefh vr vr dac dac output control tdcyu + + - - sense1 sense2 dgnd agnd dcym en/ tdcyd tblnk thld vdd phd phc phb pha inh2/ inh1/ fig 2. LS8292/ls8293 block diagram 8292 - 021811 - 4
table 4 absolute maximum ratings parameter symbol value unit dc supply voltage vdd +7 v input voltage (all inputs) vin gnd ? 0.3 to vdd + 0.3 v operating temperature t a -25 to +85 oc storage temperature t stg -65 to +125 oc table 5 electrical and transient characteristics ( vdd = 5v, t a = -25 oc to +85 oc ) parameter symbol min typ max unit condition supply voltage vdd 4.5 5.0 5.5 v - supply current idd - - 500 ua outputs floating, inputs high m0 input logic high v mh 4.0 - - v - m0 input logic low v ml - - 0.6 v input voltage logic high (all other inputs) v ih 2.0 - - v - input voltage logic low (all other inputs) v il - - 0.8 v - input current: reset/ logic high i irh - - 30 ua v ih = 2v input current: reset/ logic low i irl - - 40 ua v il = 0.8v input current: m0 logic high i mh - 5 - ua v ih = 5v input current: m0 logic low i ml - 5 - ua v il = 0v input current: logic high (all other inputs) i ih - - 50 na leakage current input current: logic low (all other inputs) i il - - 50 na leakege current output current: sink (phase & inhibit outputs) i opil 10 - - ma v out = 0.4v output current: source (phase & inhibit outputs) i opih -5 - - ma v out = 4.6v output current: sink (sync/ output) i osl 10 - - ma v out = 0.4v output current: sink (home/ output) i ohl 10 - - ma v out = 0.4v output current: source (home/ output) i ohh -5 - - ma v out = 4.6v input reference voltage (vref & vrefh) vrf 2.5 - 4.5 v - sense comparators offset voltage vos - 50 200 uv vrf = 2v tdcyd input timing resistpr r d 2 - - k ? - tdcyu input timing resistor r u 2 - - k ? - thld input timing resistor r h 4 - - k ? - tblnk input timing resistor r b 6 - - k ? - xtli input frequency fc - 5.0 8.0 mhz - fwd input set-up time for step/ tfd 0 0 0 ns - step/ input pulse width tspw - 8/fc - us - reset/ input pulse width trpw - 8/fc - us - sync/ output pulse width tsypw - 16/fc - us - pwm period tpwm - 255/fc - us - 8292-021811-5
fig 3. single and dual mixed-decay modes fig 4. LS8292 driving two-phase bipolar motor time icoil tdcyu tdcyd slow decay dual or single mixed decay dual mixed decay slow decay slow decay step up step down tpwm uc m0 m1 dcym reset/ step/ fwd en/ inh1/ inh2/ pha phb phc phd rb cb rd cd tblnk tdcyd +5v +5v 5mhz 10 m? cm cm xtlo xtli LS8292 1 2 3 4 5 6 7 9 10 16 17 inh1/ inh2/ a b c d rs rs dgnd agnd sense1 sense2 11 13 15 14 sns1 sns2 1 15 l298 +5v vdd 24 23 22 21 20 19 18 9 vss +vm vs 4 8 gnd note. cm is chosen according to following relation: cm = 2(cl C cp) C 10pf, where cl = crystal load capacitance and cp = parasitic capacitance 6 11 5 7 10 12 o1 o2 o3 o4 2 3 13 14 8292-0 61413 -6 vref vr 12
fig.5. ls8293 application for two phase motor using two separate drivers uc m0 m1 dcym reset/ step/ fwd en/ inh1/ pha phb rb cb rd cd tblnk tdcyd +5v +5v 5mhz 10m? cm cm xtlo xtli ls8293 1 2 3 4 5 6 7 9 10 20 21 en in1 in2 dgnd l6201 l6202 l6203 vdd 28 27 25 24 +vm vs o1 o2 +5v ru cu tdcyu 13 +5v rh ch +5v 14 thld boot1 15 nf 15 nf boot2 220 nf vref l6201 l6202 l6203 +vm vs o1 o2 boot1 15 nf 15 nf boot2 220 nf vref en in1 in2 inh2/ phc phd 26 23 22 gnd gnd agnd sense2 sense1 19 18 11 17 vr vrh 17 18 vref vrefh 8292-021811-7 note2. cm is chosen according to following relation: cm = 2(cl C cp) C 10pf, where cl = crystal load capacitance and cp = parasitic capacitance note1. all functional options have been implemented in this application. if all options are not used, following components can be deleted: ~rd, ru, cd and cu: if no mixed-decay mode id selected. ~rh and ch: if holding torque is not selected. in this case vrefh pin is tied to gnd.
fig 6. typical application for four phase unipolar motor using discrete mosfets uc m0 m1 reset/ step/ fwd en/ rb cb tblnk +5v 5mhz 10 m? cm cm xtlo xtli LS8292 1 2 4 5 6 7 9 10 17 dgnd vdd 24 21 23 20 +vm +5v r agnd 11 13 vr 12 vref note 4. cm is chosen according to following relation: cm = 2(cl C cp) C 10pf, where cl = crystal load capacitance and cp = parasitic capacitance note 1. this design can operate in the slow-decay mode only. pha inh1/ phb q 1 q 2 sense1 15 22 18 q 3 q 4 14 phc inh2/ phd sense2 19 r 74hc08 74hc08 d d d d +vm dcym +5v 3 tdcyd 16 8292-021811-8 note 2. q1, q2, q3 and q4 are power mosfets suitable for 5v gate drive. typical part numbers: irlz44n and irf3708 note 3. for higher pre-drive capability, 74hc08 can be replaced with mic4468
fig.7. discrete component driver pha 2n 5551 1 n 4148 bd679 6a 10 2k? bd679 6 a10 6 a10 r 6a 10 6a 10 6a 10 bd679 bd679 2n 5551 1n 4148 2k? vm phc 2n 5551 1 n 4148 bd679 6a 10 2k? bd679 6 a10 6 a10 r 6a 10 6a 10 6a 10 bd679 bd679 2n 5551 1n 4148 2k? vm inh1/ sense1 phb inh2/ sense2 phd LS8292 note. all inverters are 74hc04, all nand gates are 74hc00 and all and gates are 74hc08 8292-021811-9
fig.8. bipolar driver using n-channel mosfets r vm ho vs lo com vcc vb 0.1uf +20v ho vs lo com vcc vb 0.1uf +20v ir2104 ir2104 r vm ho vs lo com vcc vb 0.1uf + 20v ho vs lo com vcc vb 0.1uf +20v ir2104 ir2104 pha inh1/ sense1 in sd/ phb in sd/ phc inh2/ sense2 phd LS8292 ls8293 notes: vm 100v. all mosfets are irf540n, all diodes are 1n4002 8292-061512-10
table 6 step number pwm duty cycle (%) full 1/2 1/4 1/8 1/16 1/32 inh1/ inh2/ pha phb phc phd step angle (o ) 0 0 0 0 0 0 70.7 70.7 1 0 1 0 home 1 67.2 74.1 1 0 1 0 2.81 1 2 63.4 77.3 1 0 1 0 5.63 3 59.6 80.3 1 0 1 0 8.44 1 2 4 55.6 83.1 1 0 1 0 11.25 5 51.4 85.8 1 0 1 0 14.06 3 6 47.1 88.2 1 0 1 0 16.88 7 42.8 90.4 1 0 1 0 19.69 1 2 4 8 38.3 92.4 1 0 1 0 22.50 9 33.7 94.2 1 0 1 0 25.31 5 10 29.0 95.7 1 0 1 0 28.13 11 24.3 97.0 1 0 1 0 30.94 3 6 12 19.5 98.1 1 0 1 0 33.75 13 14.7 98.9 1 0 1 0 36.56 7 14 9.8 99.5 1 0 1 0 39.38 15 4.9 99.9 1 0 1 0 42.19 1 2 4 8 16 0.0 100 0 1 1 0 45.00 17 4.9 99.9 0 1 1 0 47.81 9 18 9.8 99.5 0 1 1 0 50.63 19 14.7 98.9 0 1 1 0 53.44 5 10 20 19.5 98.1 0 1 1 0 56.25 21 24.3 97.0 0 1 1 0 59.06 11 22 29.0 95.7 0 1 1 0 61.88 23 33.7 94.2 0 1 1 0 64.69 3 6 12 24 38.3 92.4 0 1 1 0 67.50 25 42.8 90.4 0 1 1 0 70.31 13 26 47.1 88.2 0 1 1 0 73.13 27 51.4 85.8 0 1 1 0 75.94 7 14 28 55.6 83.1 0 1 1 0 78.75 29 59.6 80.3 0 1 1 0 81.56 15 30 63.4 77.3 0 1 1 0 84.38 31 67.2 74.1 0 1 1 0 87.19 1 2 4 8 16 32 70.7 70.7 0 1 1 0 90.00 33 74.1 67.2 0 1 1 0 92.81 17 34 77.3 63.4 0 1 1 0 95.63 35 80.3 59.6 0 1 1 0 98.44 9 18 36 83.1 55.6 0 1 1 0 101.25 37 85.8 51.4 0 1 1 0 104.06 19 38 88.2 47.1 0 1 1 0 106.88 39 90.4 42.8 0 1 1 0 109.69 5 10 20 40 92.4 38.3 0 1 1 0 112.50 41 94.2 33.7 0 1 1 0 115.31 21 42 95.7 29.0 0 1 1 0 118.13 43 97.0 24. 3 0 1 1 0 120.94 11 22 44 98.1 19.5 0 1 1 0 123.75 45 98.9 14.7 0 1 1 0 126.56 23 46 99.5 9.8 0 1 1 0 129.38 47 99.9 4.9 0 1 1 0 132.19 3 6 12 24 48 100 0.0 0 1 0 1 135.00 49 99.9 4.9 0 1 0 1 137.81 25 50 99.5 9.8 0 1 0 1 140.63 51 98.9 14.7 0 1 0 1 143.44 13 26 52 98.1 19.5 0 1 0 1 146.25 53 97.0 24.4 0 1 0 1 149.06 27 54 95.7 29.0 0 1 0 1 151.88 55 94.2 33.7 0 1 0 1 154.69 7 14 28 56 92.4 38.3 0 1 0 1 157.50 57 90.4 42.8 0 1 0 1 160.31 29 58 88.2 47.1 0 1 0 1 163.13 continued on next page 8292 - 021811 - 1 1
step number pwm duty cycle (%) full 1/2 1/4 1/8 1/16 1/32 inh1/ inh2/ pha phb phc phd step angle (o ) 59 85.8 51.4 0 1 0 1 165.94 15 30 60 83.1 55.6 0 1 0 1 168.75 61 80.3 59.6 0 1 0 1 171.56 31 62 77.3 63.4 0 1 0 1 174.38 63 74.1 67.2 0 1 0 1 177.19 2 4 8 16 32 64 70.7 70.7 0 1 0 1 180.00 65 67.2 74.1 0 1 0 1 182.81 33 66 63.4 77.3 0 1 0 1 185.63 67 59.6 80.3 0 1 0 1 188.44 17 34 68 55.6 83.1 0 1 0 1 191.25 69 51.4 85.8 0 1 0 1 194.06 35 70 47.1 88.2 0 1 0 1 196.88 71 42.8 90.4 0 1 0 1 199.69 9 18 36 72 38.3 92.4 0 1 0 1 202.50 73 33.7 94.2 0 1 0 1 205.31 37 74 29.0 95.7 0 1 0 1 208.13 75 24.3 97.0 0 1 0 1 210.94 19 38 76 19.5 98.1 0 1 0 1 213.75 77 14.7 98.9 0 1 0 1 216.56 39 78 9.8 99.5 0 1 0 1 219.38 79 4.9 99.9 0 1 0 1 222.19 5 10 20 40 80 0.0 100 1 0 0 1 225.00 81 4.9 99.9 1 0 0 1 227.81 41 82 9.8 99.5 1 0 0 1 230.63 83 14.7 98.9 1 0 0 1 233.44 21 42 84 19.5 98.1 1 0 0 1 236.25 85 24.4 97.0 1 0 0 1 239.06 43 86 29.0 95.7 1 0 0 1 241.88 87 33.7 94.2 1 0 0 1 244.69 11 22 44 88 38.3 92.4 1 0 0 1 247.50 89 42.8 90.4 1 0 0 1 250.31 45 90 47.1 88.2 1 0 0 1 253.13 91 51.4 85.8 1 0 0 1 255.94 23 46 92 55.6 83.1 1 0 0 1 258.75 93 59.6 80.3 1 0 0 1 261.56 47 94 63.4 77.3 1 0 0 1 264.38 95 67.2 74.1 1 0 0 1 267.19 3 6 12 24 48 96 70.7 70.7 1 0 0 1 270.00 97 74.1 67.2 1 0 0 1 272.81 49 98 77.3 63.4 1 0 0 1 275.63 99 80.3 59.6 1 0 0 1 278.44 25 50 100 83.1 55.6 1 0 0 1 281.25 101 85.8 51.4 1 0 0 1 284.06 51 102 88.2 47.1 1 0 0 1 286.88 103 90.4 42.8 1 0 0 1 289.69 13 26 52 104 92.4 38.3 1 0 0 1 292.50 105 94.2 33.7 1 0 0 1 295.31 53 106 95.7 29.0 1 0 0 1 298.13 107 97.0 24.3 1 0 0 1 300.95 27 54 108 98.1 19.5 1 0 0 1 303.75 109 98.9 14.7 1 0 0 1 306.56 55 110 99.5 9.8 1 0 0 1 309.38 111 99.9 4.9 1 0 0 1 312.19 7 14 28 56 112 100 0.0 1 0 1 0 315.00 113 99.9 4.9 1 0 1 0 317.81 57 114 99.5 9.8 1 0 1 0 320.63 115 98.9 14.7 1 0 1 0 323.44 29 58 116 98.1 19.5 1 0 1 0 326.25 continued on next page 8292 - 021811 - 1 2
step number pwm duty cycle (%) full 1/2 1/4 1/8 1/16 1/32 inh1/ inh2/ pha phb phc phd step angle (o ) 117 97.0 24.4 1 0 1 0 329.06 59 118 95.7 29.0 1 0 1 0 331.88 119 94.2 33.7 1 0 1 0 334.69 15 30 60 120 92.4 38.3 1 0 1 0 337.50 121 90.4 42.8 0 1 0 1 340.31 61 122 88.2 47.1 0 1 0 1 343.13 123 85.8 51.4 0 1 0 1 345.95 31 62 124 83.1 55.6 0 1 0 1 348.75 125 80.3 59.6 0 1 0 1 351.56 63 126 77.3 63.4 0 1 0 1 354.38 127 74.1 67.2 0 1 0 1 357.19 0 0 0 0 0 0 70.7 70.7 0 1 0 1 home note: in table4 the pwm duty cycles are ind icated for fast decay mode which causes inh1/ and inh2/ outputs to be chopped. in slow decay mode inh1/ and inh2/ outputs remain high while pha, phb, phc and phd outputs are chopped. 8292 - 021811 - 1 3

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