stepper motor controller features: ?controls bipolar and unipolar motors ?cost-effective, low current , pin compatible replacement for l297 ?torque ripple compensated half-steps - LS8297CT ?half and full step modes ?normal/wave drive ?direction control ?reset input ?step control input ?enable input ?pwm chopper circuit for current control ?two over current sensor comparators with external references input ?all inputs and outputs ttl/cmos compatible (ttl for 5v operation) ? supply current < 400ua ?4.75 to 7v operation (v dd ?v ss ). ? ls8297 (dip), ls8297-s (soic), ls8297-ts (tssop) LS8297CT (dip), LS8297CT-s (soic), LS8297CT-ts (tssop) ?see figure 1 april 2009 8297-042009-1 lsi/csi l si c o m p u t e r sy s t e m s , i n c . 1 2 3 5 w a l t w h i t m a n r o a d , m e l v i l l e , n y 1 1 7 4 7 ( 6 3 1 ) 2 7 1 - 0 4 0 0 f a x ( 6 3 1 ) 2 7 1 - 0 4 0 5 ls8297 LS8297CT description: the ls8297 stepper motor controller generates four phase drive signal outputs for controlling two phase bipolar and four phase unipolar mo- tors. the outputs are used to drive two h-bridges for the two motor windings in the bipolar motor or the four driver transistors for the two center- tapped windings in the unipolar motor. the motor can be driven in full step mode either in normal drive (two-phase-on) or wave drive (one-phase-on) and half step mode. the ls8297 provides two inhibit outputs which are used to control the driver stages of each of the motor phases. the circuit uses step, frd/rev and half/full inputs in a translator to generate controls for the output stages. a dual pwm chopper circuit using an on-chip oscillator, latches and volt- age comparators are used to regulate the current in the motor windings. for each pair of phase driver outputs (pha, phb, and phc, phd) each pulse of the common internal oscillator sets the latch and enables the output. if the current in the motor winding causes the voltage across a sense resistor to exceed the reference voltage, v ref , at the comparator inputs, the latch is reset disabling the output until the next oscillator pulse. the control input determines whether the chopper acts on the phase driver outputs or the inhibit outputs. when the phase lines are chopped, the non-active phase line of each pair (pha, phb or phc, phd) is activated rather than de-activating the active line to reduce dis- sipation in the load sensing resistors. refer to figure 5b for bipolar mo- tors. if pha is high and phb is low, current flows through q1, motor winding, q4 and sense resistor rs. when chopping occurs, phb is brought high and circulating current flows through q1 and d3 and not through rs resulting in less power dissipation in rs. current decay is slow using this method. when the control input is brought low, chopping occurs by bringing inh1 low. in this case circulating current flows through d2, motor winding and d3 and through the power supply to ground causing the current to decay rapidly. for unipolar motors, only inhibit chopping is used. refer to figure 6. when inh1 is brought low current in either half of the center tapped motor winding recir- culates through the diode across it. LS8297CT is the torque ripple compensated version of the ls8297. torque imbalance resulting from alternating ?ne- phase on? ?wo-phase on?sequence of the half-step mode (see figure 4) is eliminated in the LS8297CT by switching the sense reference voltage between 100% and 70.7% in alter- nate steps. input/output description: osc input an rc input with the resistor connected to v dd and the ca- pacitor connected to ground determines the oscillator chopper rate. when connected as an oscillator, the oscillator output appears as a negative-going pulse at the sync pin. if the os- cillator pin is tied to ground, the sync pin becomes an input. osc frequency, fosc = 1/0.69rc sync as an output the sync can be used to drive sync pins of other ls8297 s. this eliminates the need for rc components for any other ls8297 controllers used in the system. as an input the sync can be driven by the ls8297 that has the rc oscilla- tor components or by any other system external clock. u l a3800 lsi 1 ls8297 LS8297CT figure 1 2 3 4 5 6 20 19 18 17 16 15 7 8 9 10 14 13 12 11 sync v ss home phd enable reset fwd/rev osc vref sense1 sense2 v dd control pha phc half/full step inh2 phb inh1 pin assignment top view
pha/phb/phc/phd phase drive output signals for power stages. in a bipolar motor pha and phb are used for one h-bridge while phc and phd are used for the other. inh1/inh2 outputs these outputs are active low inhibit controls for motor drive outputs. inh1 controls driver stage using pha and phb sig- nals while inh2 control driver stage using phc and phd sig- nals. when the control input is low, these outputs are chopped using the internal oscillator for current regulating. control input when high, the phase outputs, pha, phb, phc and phd are chopped. when low, inh1 and inh2 are chopped. normally, inhibit outputs are chopped. phase chopping might be used with a bipolar motor that does not store much energy to pre- vent fast current decay and a low useful torque. enable input when enable input is low, inh1, inh2, pha, phb, phc and phd are brought low. home output an open drain output that indicates when the ls8297 is in its initial state with pha, phb, phc, phd = logic states 0101 re- spectively. refer to figure 4. in the active state the open drain device is off. step input an active low pulse on this input causes the motor to ad- vance one step. the step occurs on the rising edge of the step signal. frd/rev input a logic 1 on this input causes the motor to advance through the stepping sequence of fig. 4. a logic 0 on this input cause the motor to reverse the sequence. reset input an active low on this input cause the motor to be restored to the home position (0101). half/full input when high, half-step operation is selected. when low, full- step operation is selected. one-phase on full step is selected by selecting full when stepping sequence is at an even state. two-phase on full step operation is selected when stepping sequence is at an odd state. refer to figure 4. sense1/ sense2 inputs inputs for load current sense voltages from power stages us- ing pha and phb drive signals or phc and phd drive sig- nals, respectively. v ref reference voltage for chopper circuit which determines the peak load current. 8297-091608-2 figure 2. ls8297/LS8297CT block diagram output logic translator + - 14 13 16 sense1 sense2 v ref osc 3 17 20 19 12 4 9 5 6 7 8 pha inh1 phb phc phdinh2 v dd half/full reset fwd/rev step home 18 osc sq r ff1 r s q ff2 1 10 + - sync control 11 enable mux x0.707 15 v ss 2 +v
absolute maximum ratings symbol parameter value unit v s supply voltage 10 v v i input signals 7 v t stg , t j storage and junction temperatures -40 to +150 ? electrical characteristics: (refer to block diagram, figure 2, and timing diagram, figure 3) t a = +25?, v dd = +5v unless otherwise specified. parameter symbol minimum typical maximum unit condition ( pin 12 ) supply voltage v dd 4.75 - 7 v - quiscent supply current i dd - 300 400 ua outputs floating ( pins 11, 17, 18, 19, 20 ) input voltage low v il 0 - 0.75 v - input voltage high v ih 2 - v dd v - input current i i - - 50 na v i = v il input current i i - - 50 na v i = v ih ( pin 10 ) enable input voltage low v enl 0 - 1.3 v - enable input voltage high v enh 2 - v dd v - enable input current i en - - 50 na v en = v enl enable input current i en - - 50 na v en = v enh ( pins 4, 6, 7, 9 ) phase output voltage low v ol - - 0.5 v i o = -10ma phase output voltage high v oh 4.0 - - v i o = 5ma ( pins 5, 8 ) inhibit output voltage low v inhl - - 0.5 v i o = -10ma inhibit output voltage high v inhh 4.0 - - v i o = 5ma ( pin 3 ) leakage current i leak - - 1 ua v o = v do = 7v saturation voltage v sat - - 0.4 v i = 5ma ( pins 13, 14, 15 ) comparators offset voltage v off - 5 - mv v ref = 1v comparator bias current i o 100 - 10 ua - ( pin 15 ) input reference voltage v ref 0 - 3 v - input current i ref - - 8 ua v ref = 3v clock time step t stp 0.5 - - us - pulse width set up time t s 1 - - us - hold time t h 4 - - us - reset time t r 1 - - us - reset to step delay t rstp 1 - - us - ( pin 16 ) oscillator: sawtooth low v sol - 2.1 - v - sawtooth high v soh - 3.65 - v - frequency f osc - 30 - khz r = 22k w , c = 3.3nf 8297-040109-3
figure 3. input timing diagram 8297-040109-4
1 2 3 4 5 6 7 8 0101 1001 0001 1000 1010 0010 0110 0100 home 1 2 3 4 5 6 7 8 1000 0010 0100 0001 step 1 3 5 7 1 3 5 7 1 3 5 7 a b c
figure 5a. typical application schematic for a two - phase bipolar motor using a single motor driver ic figure 5b. one half of l298 drive stage 8297-040309-6 v m pha phb inh1 q1 q2 q3 q4 d1 d3 d4d2 r sense1 13 14 2 16 10 17 18 20 11 19 7 4 8 5 12 11 7 10 9 4 2 3 13 14 1 15 8 mcu ls8297 LS8297CT l298 5v v m reset enable stepper motor windings pha phb phc phd sense1 vref inh1 inh2 step frd/rev v dd v ss sense2 15 9 12 6 inh1 inh2 pha phb phc phd 5 6 r r out1 out2 out3 out4 v dd vs v dd half/full control sensea v ss senseb see note note: the sense resistors on l298 should be chosen so that i max = v re f /r, where i max is the maximum motor winding current. 22k 3.3nf osc
7297-090908-7 figure 6. typical application schematic for a four-phase unipolar motor using discrete mosfet transistors note: q1, q2, q3, q4 are mosfet power transistors suitable for 5v gate drive typical p/ns = irlz44n and irf3708 16 10 17 11 19 12 mcu ls8297 LS8297CT 5v enable step frd/rev v dd 2 v ss reset osc 13 14 vref sense2 15 4 5 pha phb inh1 6 r sense1 r 8 9 7 phc phd inh2 v m v m 1 2 3 74hc08 74hc08 4 5 6 9 10 12 13 8 q1 q2 q3 q4 11 v dd half/full control 20 18 22k 3.3nf
figure 7. synchronizing multiple ls8297s 7297-041309-8 r c +v osc sync sync sync osc osc ls8297 LS8297CT 16 16 16 1 1 1 ls8297 LS8297CT ls8297 LS8297CT the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
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