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s-25c010a/020a/040a www.sii-ic.com cmos spi serial e 2 prom ? seiko instruments inc., 2007-2010 rev.3.0 _00_c seiko instruments inc. 1 the s-25c010a/020a/040a is spi serial e 2 prom which operate at high speed, with low current consumption and the wide range operation. the s-25c010a /020a/040a respectively has t he capacity of 1k-bit, 2k-bit, 4k-bit and the organization of 128 words 8-bit, 256 words 8-bit, 512 words 8-bit. these ics are able to page write and sequential read. ? features ? wide range operation read 1.6 to 5.5 v (at ? 40 to + 85c) write 1.7 to 5.5 v (at ? 40 to + 85c) ? operation frequency 5.0 mhz (2.5 to 5.5 v), 2.0 mhz (1.6 to 5.5 v) ? spi mode (0, 0) and (1, 1) ? page write: 16 bytes / page ? sequential read ? write protect: software, hardware protect area: 25%, 50%, 100% ? monitors write to the memory by a status register ? write protect function dur ing the low power supply ? cmos schmitt input cs , sck, si, wp , hold ? endurance: 10 6 cycles/word *1 (at + 25c), ? data retention: 100 years (at + 25c) ? memory capacitance: s-25c010a 1k-bit s-25c020a 2k-bit s-25c040a 4k-bit ? data before shipment: memory array ffh, bp1 = 0, bp0 = 0 ? lead-free, sn 100%, halogen-free *2 *1. for each address (word: 8-bit) *2. refer to ? ? product name structure ? for details. ? packages ? 8-pin sop (jedec) ? 8-pin tssop ? snt-8a ? tmsop-8 caution this product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to sii is indispensable.
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 2 ? pin configurations 8-pin sop (jedec) top view table 1 pin no. symbol description 1 cs *1 chip select input 2 so serial data output 3 wp *1 write protect input 4 gnd ground 5 si *1 serial data input 6 sck *1 serial clock input 7 hold *1 hold input 8 vcc power supply *1. all input pins have the cmos structur e. do not set the input pins in high impedance during operation. so cs 1 2 3 4 8 7 6 5 sck wp gnd si hold vcc figure 1 s-25c010a0i-j8t1x s-25c020a0i-j8t1x s-25c040a0i-j8t1x 8-pin tssop top view table 2 pin no. symbol description 1 cs *1 chip select input 2 so serial data output 3 wp *1 write protect input 4 gnd ground 5 si *1 serial data input 6 sck *1 serial clock input 7 hold *1 hold input 8 vcc power supply *1. all input pins have the cmos structur e. do not set the input pins in high impedance during operation. so cs wp gnd sck si hold vcc 1 2 3 4 8 7 6 5 figure 2 s-25c010a0i-t8t1x s-25c020a0i-t8t1x s-25c040a0i-t8t1x snt-8a top view table 3 pin no. symbol description 1 cs *1 chip select input 2 so serial data output 3 wp *1 write protect input 4 gnd ground 5 si *1 serial data input 6 sck *1 serial clock input 7 hold *1 hold input 8 vcc power supply *1. all input pins have the cmos structur e. do not set the input pins in high impedance during operation. so cs 1 2 3 4 8 7 6 5 sck wp gnd si hold vcc figure 3 s-25c010a0i-i8t1x s-25c020a0i-i8t1x s-25c040a0i-i8t1x
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 3 remark 1. see dimensions for details of the package drawings. 2. x: g or u 3. please select products of environmental code = u for sn 100%, halogen-free products. tmsop-8 top view table 4 pin no. symbol description 1 cs *1 chip select input 2 so serial data output 3 wp *1 write protect input 4 gnd ground 5 si *1 serial data input 6 sck *1 serial clock input 7 hold *1 hold input 8 vcc power supply *1. all input pins have the cmos structur e. do not set the input pins in high impedance during operation. 3 2 4 1 8 6 7 5 vcc hold sck si cs so gnd wp figure 4 s-25c010a0i-k8t3u s-25c020a0i-k8t3u s-25c040a0i-k8t3u
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 4 ? block diagram mode decoder status register address register data register wp cs hold si sck so vcc gnd memory cell array status memory cell array voltage detector read circuit clock counter y decoder x decoder input control circuit output control circuit step-up circuit page latch figure 5
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 5 ? absolute maximum ratings table 5 item symbol absolute maximum rating unit power supply voltage v cc ? 0.3 to + 7.0 v input voltage v in ? 0.3 to + 7.0 v output voltage v out ? 0.3 to v cc + 0.3 v operation ambient temperature t opr ? 40 to + 85 c storage temperature t stg ? 65 to + 150 c caution the absolute maximum ra tings are rated values exceeding whic h the product could suffer physical damage. these values must therefore not be exceeded under any conditions. ? recommended operating conditions table 6 item symbol condition min. max. unit read operation 1.6 5.5 v power supply voltage v cc write operation 1.7 5.5 v high level input voltage v ih v cc = 1.6 to 5.5 v 0.7 v cc v cc + 1.0 v low level input voltage v il v cc = 1.6 to 5.5 v ? 0.3 0.3 v cc v ? pin capacitance table 7 (ta = 25 c, f = 1.0 mhz, v cc = 5 v) item symbol condition min. max. unit input capacitance c in v in = 0 v ( cs , sck, si, wp , hold ) ? 8 pf output capacitance c out v out = 0 v (so) ? 10 pf ? endurance table 8 item symbol operation ambient temperature min. max. unit endurance n w + 25c 10 6 ? cycles / word *1 *1. for each address (word: 8 bits) ? data retention table 9 item symbol operation ambient temperature min. max. unit data retention ? + 25c 100 ? year
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 6 ? dc electrical characteristics table 10 v cc = 1.6 to 2.5 v f sck = 2.0 mhz v cc = 2.5 to 4.5 v f sck = 5.0 mhz v cc = 4.5 to 5.5 v f sck = 5.0 mhz item symbol condition min. max. min. max. min. max. unit current consumption (read) i cc1 no load at so pin ? 1.5 ? 2.0 ? 2.5 ma table 11 v cc = 1.7 to 2.5 v f sck = 2.0 mhz v cc = 2.5 to 4.5 v f sck = 5.0 mhz v cc = 4.5 to 5.5 v f sck = 5.0 mhz item symbol condition min. max. min. max. min. max. unit current consumption (write) i cc2 no load at so pin ? 2.0 ? 2.5 ? 3.0 ma table 12 v cc =1.6 to 2.5 v v cc =2.5 to 4.5 v v cc =4.5 to 5.5 v item symbol condition min. max. min. max. min. max. unit standby current consumption i sb cs = vcc, so = open other inputs are v cc or gnd ? 1.5 ? 1.5 ? 1.5 a input leakage current i li v in = gnd to v cc ? 1.0 ? 1.0 ? 1.0 a output leakage current i lo v out = gnd to v cc ? 1.0 ? 1.0 ? 1.0 a v ol1 i ol = 2.0 ma ? ? ? 0.4 ? 0.4 v low level output voltage v ol2 i ol = 1.5 ma ? 0.4 ? 0.4 ? 0.4 v v oh1 i oh = ? 2.0 ma ? ? 0.8 v cc ? 0.8 v cc ? v high level output voltage v oh2 i oh = ? 0.4 ma 0.8 v cc ? 0.8 v cc ? 0.8 v cc ? v
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 7 ? ac electrical characteristics table 13 measurement conditions input pulse voltage 0.2 v cc to 0.8 v cc output reference voltage 0.5 v cc output load 100 pf table 14 v cc = 1.6 to 2.5 v v cc = 2.5 to 4.5 v v cc = 4.5 to 5.5 v item symbol min. max. min. max. min. max. unit sck clock frequency f sck ? 2.0 ? 5.0 ? 5.0 mhz cs setup time during cs falling t css.cl 150 ? 90 ? 90 ? ns cs setup time during cs rising t css.ch 150 ? 90 ? 90 ? ns cs deselect time t cds 200 ? 90 ? 90 ? ns cs hold time during cs falling t csh.cl 200 ? 90 ? 90 ? ns cs hold time during cs rising t csh.ch 150 ? 90 ? 90 ? ns sck clock time ?h? *1 t high 200 ? 90 ? 90 ? ns sck clock time ?l? *1 t low 200 ? 90 ? 90 ? ns rising time of sck clock *2 t rsk ? 1 ? 1 ? 1 s falling time of sck clock *2 t fsk ? 1 ? 1 ? 1 s si data input setup time t ds 50 ? 20 ? 20 ? ns si data input hold time t dh 60 ? 30 ? 30 ? ns sck ?l? hold time during hold rising t skh.hh 150 ? 70 ? 70 ? ns sck ?l? hold time during hold fa lling t skh.hl 100 ? 40 ? 40 ? ns sck ?h? setup time during hold fa lling t sks.hl 150 ? 60 ? 60 ? ns sck ?h? setup time during hold rising t sks.hh 150 ? 60 ? 60 ? ns disable time of so output *2 t oz ? 200 ? 100 ? 100 ns delay time of so output t od ? 150 ? 70 ? 70 ns hold time of so output t oh 0 ? 0 ? 0 ? ns rising time of so output *2 t ro ? 100 ? 40 ? 40 ns falling time of so output *2 t fo ? 100 ? 40 ? 40 ns disable time of so output during hold fa lling *2 t oz.hl ? 200 ? 100 ? 100 ns delay time of so output during hold rising *2 t od.hh ? 150 ? 50 ? 50 ns wp setup time t ws1 0 ? 0 ? 0 ? ns wp hold time t wh1 0 ? 0 ? 0 ? ns wp release / setup time t ws2 0 ? 0 ? 0 ? ns wp release / hold time t wh2 60 ? 30 ? 30 ? ns * 1. the clock cycle of the sck clock (frequency f sck ) is 1/f sck s. this clock cycle is determined by a combination of several ac characteristics. note that t he clock cycle cannot be set as (1/f sck ) = t low (min.) + t high (min.) by minimizing the sck clock cycle time. * 2. these are values of sample and not 100% tested.
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 8 table 15 v cc = 1.7 to 5.5 v item symbol min. max. unit write time t pr ? 4.0 ms so t csh.cl sck cs si t css.cl t ds t dh msb in lsb in t csh.ch t css.ch t cds t fsk t rsk high-z figure 6 serial input timing so sck hold cs si t skh.hl t oz.hl t od.hh t skh.hh t sks.hl t sks.hh figure 7 hold timing
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 9 so sck cs si t high t oh t ro t oz t low t sck t od t fo t od t oh addr lsb in lsb out figure 8 serial output timing wp cs t wh1 t ws1 figure 9 valid timing in write protect wp cs t wh2 t ws2 figure 10 invalid timing in write protect
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 10 ? pin functions 1. cs (chip select input ) pin this is an input pin to set a chip in the select status. in t he ?h? input level, the device is in the non-select status and its output is high impedance. the devic e is in standby as long as it is not in write inside. the device goes in active by setting the chip select to ?l?. input any instruction code after pow er-on and a falling of chip select. 2. si (serial data input ) pin this pin is to input serial data. this pin receives an inst ruction code, an address and write dat a. this pin latches data at rising edge of serial clock. 3. so (serial data output ) pin this pin is to output serial data. the data output changes at falling edge of serial clock. 4. sck (serial clock input ) pin this is a clock input pin to set the timing of serial data. an instruction code, an address and write data are received at a rising edge of clock. data is output at falling edge of clock. 5. wp (write protect input ) pin this is an input pin to protect memory data when write instruction (write, wrsr) is being input. by setting this pin to ?l?, the wel bit in the status regi ster is set to ?l?. therefore s-25c 010a/020a/040a does not write to the e 2 prom, however, it accepts other instructi ons. fix this pin ?h? or ?l? not to set it in the floating state. refer to ? ? protect operation ? for details. 6. hold (hold input ) pin this pin is used to pause serial communications without setting the device in the non-select status. in the hold status, the serial output goes in high impedance, t he serial input and the serial clock go in ?don?t care?. during the hold operation, be sure to set the dev ice in active by setting the chip select ( cs pin) to ?l?. refer to ? ? hold operation ? for details.
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 11 ? instruction setting table 16 and 17 are the lists of instruction fo r the s-25c010a/020a/040a. the instruct ion is able to be input by changing the cs pin ?h? to ?l?. input the instruct ion in the msb first. each instruction code is organized with 1-byte as shown below. if the s-25c010a/020a/040a receives any invalid instruct ion code, the device goes in the non-select status. 1. s-25c010a/020a table 16 instruction code address data instruction operation sck input clock 1 to 8 sck input clock 9 to 16 sck input clock 17 to 24 wren write enable 0000 x110 ? ? wrdi write disable 0000 x100 ? ? rdsr read the status register 0000 x101 b7 to b0 output *1 ? wrsr write in the status r egister 0000 x001 b7 to b0 input ? read read memory data 0000 x011 a7 *2 to a0 d7 to d0 output *3 write write memory data 0000 x010 a7 *2 to a0 d7 to d0 input *1. sequential data reading is possible. *2. in the s-25c010a, a7 = don?t care because the address range is a6 to a0. *3. after outputting data in the specified address, data in the following address is output. remark x = don?t care. 2. s-25c040a table 17 instruction code address data instruction operation sck input clock 1 to 8 sck input clock 9 to 16 sck input clock 17 to 24 wren write enable 0000 x110 ? ? wrdi write disable 0000 x100 ? ? rdsr read the status register 0000 x101 b7 to b0 output *1 ? wrsr write in the status r egister 0000 x001 b7 to b0 input ? read read memory data 0000 [a8 *2 ] 011 a7 to a0 d7 to d0 output *3 write write memory data 0000 [a8 *2 ] 010 a7 to a0 d7 to d0 input *1. sequential data reading is possible. *2. in the s-25c040a, assign bit a8 in the addre ss into the fifth bit in an instruction code. *3. after outputting data in the specified address, data in the following address is output. remark x = don?t care.
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 12 ? operation 1. status register the status register?s organization is below. the status register can write and read by a specific instruction. 1 b7 b6 1 b5 1 b4 bp1 b3 bp0 b2 wel b1 wip b0 block protect bits write enable latch write in progress 1 figure 11 organization of status register the status/control bits of the status register are as follows. 1. 1 bp1, bp0 (b3, b2) : block protect bit bp1 and bp0 are composed of the nonvolatile bit. the area size of software protect against write instruction is defined by them. rewriting these bits is possible by the wrsr instruction. to protect the memory area against the write instruction, set either or both of bit bp1 and bp0 to ?1?. rewriting bit bp1 and bp0 is possible unless they are in hardware protect mode ( wp pin is ?l?). refer to ? ? protect operation ? for details of ?block protect?. 1. 2 wel (b1) : write enable latch bit wel shows the status of internal write enable latch. bit wel is set by the wren instruction only. if bit wel is ?1?, this is the status that write enable latch is set. if bit wel is ?0?, write enable latch is in reset, so that the s- 25c010a/020a/040a does not receive the writ e or wrsr instruction. bit wel is reset after these operations; ? the power supply voltage is dropping ? power-on ? after performing wrdi ? after the write operation by t he wrsr instruction has completed ? after the write operation by the write instruction has completed ? after setting the wp pin to ?l?
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 13 1. 3 wip (b0) : write in progress bit wip is read only and shows whether the internal memory is in the write operation or not by the write or wrsr instruction. bit wip is ?1? during the writ e operation but ?0? duri ng any other status. figure 12 shows the usage example. d2 d1 d0 rdsr rdsr rdsr cs si wel, wip wel, wip wel, wip so write or wrsr instruction rdsr instruction rdsr instruction rdsr instruction t pr b p 1 b p 0 b p 1 b p 0 b p 1 b p 0 1111 11 1111 11 1111 00 figure 12 usage example of wel, wip bits during write
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 14 2. write enable (wren) before writing data (write and wrsr), be sure to set bit writ e enable latch (wel). this instruction is to set bit wel. its operation is below. after selecting the device by the chip select ( cs ), input the instruction code from se rial data input (si). to set bit wel, set the device in the non-select status by cs at the 8th clock of the serial clock (sck). to cancel the wren instruction, input the clock different from a s pecified value (n = 8 clock) while cs is in ?l?. so sck wp cs si instruction high-z 12345678 high / low x remark x = don?t care. figure 13 wren operation
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 15 3. write disable (wrdi) the wrdi instruction is one of ways to reset bit write enable latch (wel). after selecting t he device by the chip select ( cs ), input the instruction code from serial data input (si). to reset bit wel, set the devic e in the non-select status by cs at the 8th clock of the serial clock. to cancel the wrdi instruction, input the clock different from a specified value (n = 8 clock) while cs is in ?l?. bit wel is reset after the operations shown below. ? the power supply voltage is dropping ? power on ? after performing wrdi ? after the completion of write operation by the wrsr instruction ? after the completion of write operation by the write instruction ? after setting the wp pin to ?l? so sck wp cs si instruction high-z 12345678 high / low x remark x = don?t care. figure 14 wrdi operation
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 16 4. read the status register (rdsr) reading data in the status regi ster is possible by the rdsr instruction. during the write operation, it is possible to confirm the progress by checking bit wip. set the chip select ( cs ) ?l? first. after that, input the instruction code from serial data input (si). t he status of bit in the status register is output from serial data output (so). sequent ial read is available for the status register. to stop the read cycle, set cs to ?h?. it is possible to read the status register always. the bits in it are valid and can be read by rdsr even in the write cycle. however, during the write cycle in progr ess, the nonvolatile bits bp1, bp0 are fixed in a certain value. these updated values of bit can be obtained by inputting another new rdsr inst ruction after the write cycle has completed. contrarily, two of read only bits wel and wip are being updat ed while the write cycle is in progress. b7, b6, b5, b4 are ?1? when they are read by the rdsr instruction. so sck wp cs si instruction high-z 12345678 high / low 9 10111213141516 outputs data in the status register b7 b6 b5 b7b0b1b2b3b4 x remark x = don?t care. figure 15 rdsr operation
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 17 5. write in the status register (wrsr) the values of status register (bp1, bp0 ) can be rewritten by inputting the wrsr in struction. but b7, b6, b5, b4, b1, b0 of status register cannot be rewri tten. b7 to b4 are always ?1? w hen reading the status register. before inputting the wrsr instruction, set bit wel by the wren instruction. the operati on of wrsr is shown below. set the chip select ( cs ) ?l? first. after that, input the instruction c ode and data from serial data input (si). to start wrsr write (t pr ), set the chip select ( cs ) to ?h? after inputting data or before i nputting a rising of the next serial clock. it is possible to confirm the operation st atus by reading the value of bit wip dur ing wrsr write. bit wip is ?1? during write, ?0? during any other status. bit wel is reset when write is completed. with the wrsr instruction, the values of bp1 and bp0; wh ich determine the area size t he users can handle as the read only memory; can be changed. but if the signal wp is in ?l?, s-25c010a/020a/ 040a does not send the wrsr instruction (refer to ? ? protect operation ?). bit bp1, bp0 keep the value which is the one prior to the wr sr instruction during the wrsr instruction. the newly updated value is changed when the wrsr instruction has completed. to cancel the wrsr instruction, input the clock different from a s pecified value (n = 16clock) while cs is in ?l?. so sck wp cs si instruction high-z 12345678 high / low 9 10111213141516 inputs data in the status register b7 b6 b5 b0b1b2b3b4 x remark x = don?t care. figure 16 wrsr operation
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 18 6. read memory data (read) the read operation is shown below. input the instruction code and the address from serial data input (si) after inputting ?l? to the chip select ( cs ). the input address is loaded to the internal address counter, and data in the address is output from the serial data output (so). next, by inputting the serial clo ck (sck) keeping the chip select ( cs ) in ?l?, the address is automatically incremented so that data in the following addre ss is sequentially output. the address counter rolls over to the first address by increment in the last address. to finish the read cycle, set cs to ?h?. it is possible to raise the chip se lect always during the cy cle. during write, the read instruction code is not be accepted or operated. so sck wp cs si instruction high-z 12345678 high / low 9 1011 1314151617 8-bit address a7 *1 a6 a5 a0a1a2a3 outputs the first byte d4d5d6d7 18 19 20 21 22 23 24 d0d1d2d3 d7 outputs the second a4 12 x *1 in the s-25c010a, a7 = don?t care because the address range is a6 to a0. remark x = don?t care. figure 17 read operation (s-25c010a/020a)
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 19 so sck wp cs si instruction high-z 12345678 high / low 9 1011 1314151617 8-bit address a7 a6 a5 a0a1a2a3 outputs the first byte d4d5d6d7 18 19 20 21 22 23 24 d0d1d2d3 d7 outputs the second a4 12 a8 *1 *1 in the s-25c040a, assign bit a8 in the address into the fifth bit in an instruction code. figure 18 read operation (s-25c040a)
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 20 7. write memory data (write) figure 19 and 20 show the timing chart when inputting 1-byte data. input the instruction code, the address and data from serial data input (si) after inputting ?l? to the chip select ( cs ). to start write (t pr ), set the chip select ( cs ) to ?h? after inputting data or before inputting a risi ng of the next serial clock. bit wip is reset to ?0? when write has completed. the s-25c010a/020a/040a can page wr ite of 16 bytes. its function to transmit dat a is as same as byte write basically, but it operates page write by receiving sequential 8-bit write data as much data as page size has. input the instruction code, the address and data from serial dat a input (si) after inputting ?l? in cs , as the write operation (page) shown in figure 21 and 22 . input the next data while keeping cs in ?l?. after that, repeat i nputting data of 8-bit sequentially. at the end, by setting cs to ?h?, the write operation starts (t pr ). 4 of the lower bits in the address are automatically incremented ev ery time when receiving write data of 8-bit. thus, even if write data exceeds 16 by tes, the higher bits in the address do not c hange. and 4 of lower bits in the address roll over so that write data which is previously input is overwritten. these are cases when the write instru ction is not acc epted or operated. ? bit wel is not set to ?1? (not set to ?1? beforehand immediately before the write instruction) ? during write ? the address to be written is in the protect area by bp1 and bp0. ? the signal wp is in ?l?. to cancel the write instruction, input the cl ock different from a specified value (n = 16+m 8clock) while cs is in ?l?.
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 21 so wp cs high-z high sck 12345678 91011 1314151617 18 19 20 21 22 23 24 12 si instruction 8-bit address a7 *1 a6 a5 a0a1a2a3 a4 a7 a6 a5 a0a1a2a3 a4 data byte 1 x *1 in the s-25c010a, a7 = don?t care because the address range is a6 to a0. remark x = don?t care. figure 19 write operation (1-byte) (s-25c010a/020a) so wp cs high-z high sck 12345678 91011 1314151617 18 19 20 21 22 23 24 12 si instruction 8-bit address a7 a6 a5 a0a1a2a3 a4 a7 a6 a5 a0a1a2a3 a4 data byte 1 a8 *1 *1 in the s-25c040a, assign bit a8 in the address into the fifth bit in an instruction code. figure 20 write operation (1-byte ) (s-25c040a)
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 22 so sck wp cs si instruction high-z 12345678 high 91011 14151617 8-bit address a7 *1 a6 a5 a0a1a2 data byte (n) data byte (n + x) d4d5d6d7 18 19 20 21 22 23 24 d0d1d2d3 d0d1d2d3 d4 a3a4 12 13 x *1 in the s-25c010a, a7 = don?t care because the address range is a6 to a0. remark x = don?t care. figure21 write operation (page) (s-25c010a/020a) so sck wp cs si instruction high-z 12345678 high 91011 14151617 8-bit address a7 a6 a5 a0a1a2 data byte (n) data byte (n + x) d4d5d6d7 18 19 20 21 22 23 24 d0d1d2d3 d0d1d2d3 d4 a3a4 12 13 a8 *1 *1 in the s-25c040a, assign bit a8 in the address into the fifth bit in an instruction code. figure22 write operation (page) (s-25c040a)
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 23 ? protect operation table 18 shows the block settings of write protect. setting value in protect bit (bp1, bp0) in the status register protects data in the area of all/50%/ 25% of the memory address. setting signal wp to ?l? provides the following settings. ? write protect for the write, wrsr instructions ? reset bit wel figure 9 and 10 show the valid timing in write prot ect and invalid timing in write protect. table 18 the block settings of write protect status register address of write protect block bp1 bp0 the area of write protect s-25c040a s-25c020a s-25c010a 0 0 0 % none none none 0 1 25 % 180h to 1ffh c0h to ffh 60h to 7fh 1 0 50 % 100h to 1ffh 80h to ffh 40h to 7fh 1 1 100 % 000h to 1ffh 00h to ffh 00h to 7fh
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 24 ? hold operation the hold operation is used to pause serial communications without setting the device in the non- select status. in the hold status, the serial data output goes in high impedance, and bot h of the serial data input and the serial clock go in ?don?t care?. be sure to se t the chip select ( cs ) to ?l? to set the device in the se lect status during the hold status. generally, during the hold status, the device holds the select st atus. but if setting the device in the non-select status, the users can finish the operat ion even in progress. figure 23 shows the hold operation. set hold ( hold ) to ?l? when the serial clock (sck) is in ?l?, hold ( hold ) is switched at the same time the hol d status starts. if setting hold ( hold ) to ?h?, hold ( hold ) is switched at the same time the hold status ends. set hold ( hold ) to ?l? when the serial clock (sck) is in ?h?; the hol d status starts when the serial clock goes in ?l? after hold ( hold ) is switched. if setting hold ( hold ) to ?h?, the hold status ends when the serial clock goes in ?l? after hold ( hold ) is switched. sck hold hold status hold status figure 23 hold operation
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 25 ? write protect function during the low power supply voltage the s-25c010a/020a/040a has a built-in detection circuit which operates wi th the low power supply voltage. the s- 25c010a/020a/040a cancels the write operation (write, wrsr) when the power supply voltage drops and power-on, at the same time, goes in the write pr otect status (wrdi) automatically to reset bit wel. its detection and release voltages are 1.20 v typ. (refer to figure 24 ). to operate write, after the power suppl y voltage dropped once but rose to the volt age level which allows write again, be sure to set the write enable latch bit (w el) before operating write (write, wrsr). in the write operation, data in the address written during the low power supply voltage is not assured . cancel the write instruction set in write protect (wrdi) automatically release voltage ( +v det ) 1.20 v typ. detection voltage ( ?v det ) 1.20 v typ. power supply voltage figure 24 operation during low power supply voltage ? i/o pin 1. connection of input pin all input pins in s-25c010a/020a/040a have the cmos structure. do not se t these pins in high impedance during operation when you design. especially, set the cs input in the non-select status ?h? during power-on/off and standby. the error write does not occur as long as the cs pin is in the non-select status ?h?. set the cs pin to v cc via a resistor (the pull-up resistor of 10 to 100 k ). to prevent the error for sure, it is re commended to set other input pins than the cs pin via a pull-up resistor. 2. equivalent circuit of i/o pin figure 25 and 26 show the equivalent circuits of input pins in s-25c010a/020a/ 040a. a pull-up and pull-down elements are not included in each input pin, pay attention not to set it in the floating state when you design. figure 27 shows the equivalent circuit of the out put pin. this pin has the tri-state output of ?h? level/?l? level/high-z.
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 26 2. 1 input pin cs, sck figure 25 cs , sck pin si, wp, hold figure 26 si, wp , hold pin 2. 2 output pin so v cc figure 27 so pin 3. precaution for use absolute maximum ratings: do not operate these ics in excess of the absolute maximum ratings (as listed on the data sheet). exceeding the supply vo ltage rating can cause latch-up. operations with moisture on the e 2 prom pins may occur malfunction by short-circuit between pins. especially, in occasions like picking the e 2 prom up from low temperature t ank during the evaluation. be su re that not remain frost on the e 2 prom pin to prevent malfunction by short-circuit. also attention should be paid in using on environmen t, which is easy to dew for the same reason.
cmos spi serial e 2 prom rev.3.0 _00_c s-25c010a/020a/040a seiko instruments inc. 27 ? precautions do not apply an electrostatic discharge to this ic that ex ceeds the performance ratings of the built-in electrostatic protection circuit. sii claims no responsibility for any and all disputes arising out of or in connection with any in fringement of the products including this ic upon patents owned by a third party.
cmos spi serial e 2 prom s-25c010a/020a/040a rev.3.0 _00_c seiko instruments inc. 28 ? product name structure 1. product name (1) 8-pin sop (jedec), 8-pin tssop, snt-8a s-25cxxxx 0i ? xxxx x fixed product name s-25c010a : 1k-bit s-25c020a : 2k-bit s-25c040a : 4k-bit package name (abbreviation) and ic packing specification j8t1: 8-pin sop (jedec) , tape t8t1: 8-pin tssop, tape i8t1: snt-8a, tape environmental code u: lead-free (sn 100%), halogen-free g: lead-free (for details, please contact our sales office) (2) tmsop-8 s-25cxxxx 0i ? k8t3 u fixed product name s-25c010a : 1k-bit s-25c020a : 2k-bit s-25c040a : 4k-bit package name (abbreviation) and ic packing specification k8t3: tmsop-8, tape environmental code u: lead-free (sn 100%), halogen-free 2. package drawing code package name package tape reel land environmental code = g fj008-a-p-sd fj008-d-c-sd fj008-d-r-sd ? 8-pin sop (jedec) environmental code = u fj008-z-p-sd fj008-z-c-sd fj008-z-r-sd ? environmental code = g ft008-a-p-sd ft008-e-c-sd ft008-e-r-sd ? 8-pin tssop environmental code = u ft008-z-p-sd ft008-z-c-sd ft008-z-r-sd ? snt-8a ph008-a-p-sd ph008-a-c-sd ph008-a-r-sd ph008-a-l-sd tmsop-8 fm008-a-p-sd fm008-a-c-sd fm008-a-r-sd ?

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www.sii-ic.com ? the information described herein is subject to change without notice. ? seiko instruments inc. is not responsible for any pr oblems caused by circuits or diagrams described herein whose related industrial properties, patents, or ot her rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarant ee the success of any specific mass-production design. ? when the products described herein are regulated produ cts subject to the wassenaar arrangement or other agreements, they may not be exported without authoriz ation from the appropriate governmental authority. ? use of the information described he rein for other purposes and/or repr oduction or copying without the express permission of seiko instrum ents inc. is strictly prohibited. ? the products described herein cannot be used as par t of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of seiko instruments inc. ? although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may oc cur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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