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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? xrt82d20 single channel e1 line interface unit october 2000 rev. 1.0.6 general description the xrt82d20 is a fully integrated, single channel, line interface transceiver for 75 w or 120 w e1 (2.048 mbps) applications. the liu ic consists of a receiver with adaptive data slicer for accurate data and clock recoveries and a transmitter which accepts either sin- gle or dual-rail digital input for signal transmission to the line using a low- impedance differential line driver. the device also includes a crystal-less jitter attenua- tor for clock and data smoothing which, depending on system requirements, can be selected in either the transmit or receive path. coupling the xrt82d20 to the line requires trans- formers on both the receiver and transmitter sides, and supports both balanced and unbalanced interfac- es. features ? complete e1 (cept) line interface unit ? pin compatible with the xrt7288 ? generates transmit output pulses that are compli- ant with the itu-t g.703 pulse template for 2.048mbps (e1) rates ? on-chip pulse shaping for both 75 w and 120 w line drivers ? clock recovery and selectable crystal-less jitter attenuator ? compliant with ets300166 return loss ? compliant with the itu-t g.823 jitter tolerance requirements ? supports remote, local and digital loop back operations ? declares and clears the los per itu-t g.775 ? logic inputs accept either 3.3v or 5.0v levels ? operates over -40 0 c to 85 0 c temperature range ? ultra low power dissipation ? +3.3v or +5v supply operation applications ? pdh multiplexers ? sdh multiplexers ? digital cross-connect systems ? dect (digital european cordless telephone) base stations ? csu/dsu equipment. ? test equipment f igure 1. b lock d iagram of the xrt82d20 hdb3 encoder peak detector local loopback los detect data slicer data & timing recovery remote loopback hdb3 decoder digital loopback tx pulse shaper mux mux line driver tclk tpos tneg rclk rpos rneg ttip tring rlos rtip rring mclk timing generator jitter attenuator
? ? ? ? single channel e1 line interface unit xrt82d20 rev. 1.0.6 2 ordering information f igure 2. p inout of the xrt82d20 rtip rring muterx agnd avdd txlev ttip tvdd tring tgnd jaen digi jatx/rx mclk rlos clklos tneg/code rneg/lcv rclk rpos/rdata tclk tpos/tdata lloop rloop dloop atm raos taos 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 p art #p ackage o perating t emperature r ange xrt82d20iw 28 lead 300 mil jedec soj -40 o c to + 85 o c
xrt82d20 single channel e1 line interface unit ? ? ? ? rev. 1.0.6 i table of contents general description ................................................................................................. 1 features ...................................................................................................................... .......................... 1 applications .................................................................................................................. ....................... 1 figure 1. block diagram of the xrt82d20 ...................................................................................... ............ 1 figure 2. pinout of the xrt82d20 ............................................................................................. ................... 2 o rdering i nformation .............................................................................................................................. 2 pin descriptions .......................................................................................................... 3 figure 3. interface timing diagram in both single-rail and dual-rail mode, with digi (pin 17) = 0 . 5 figure 4. interface timing diagram in dual-rail mode only, with digi (pin 17) = 1 ............................. 6 electrical characteristics .................................................................................. 7 t able 1: r eceiver c haracteristics (ta = 25c, vdd = 3.3v 5% or 5v 5% u nless otherwise specified ) ............................................................................................................................... ............................................. 7 t able 2: t ransmitter c haracteristics : (ta = 25c, vdd = 3.3v 5% or 5v 5% u nless otherwise spec - ified ) ............................................................................................................................. ..................................... 7 t able 3: p ower c onsumption including the l ine p ower d issipation , t ransmission and receive p aths all a ctive (ta = -40 to 85c, vdd = 3.3v 5% u nless otherwise specified ) ................................................. 7 t able 4: p ower c onsumption including the l ine p ower d issipation , t ransmission and receive p aths all a ctive (ta = -40 to 85c, vdd = 5v 5% u nless otherwise specified ) ................................................... 8 t able 5: ac e lectrical c haracteristics ................................................................................................... 8 t able 6: dc e lectrical c haracteristics ; (t a = 25c, v dd =3.3v 5% or 5v 5% unless otherwise spec - ified ) ............................................................................................................................. ..................................... 9 a bsolute maximum r atings .......................................................................................................... 9 figure 5. receiver maximum jitter tolerance, test conditions: test patterrn 2^15-1, (-6db) cable loss 10 figure 6. receiver jitter transfer function (jitter attenuator disabled, test conditions: test pattern 2^15-1, input jitter 0.5uip-p ................................................................................................. ........................ 11 figure 7. receiver jitter transfer function (jitter attenuator enabled) test conditions: test pattern 2^15-1, input jitter 75% of maximum jitter tolerance .......................................................................... .... 11 system description .................................................................................................. 12 1.0 the receive section ....................................................................................................... ................. 12 1.1 jitter attenuator ......................................................................................................... ......................... 12 1.2 the transmit section ...................................................................................................... ...................... 12 figure 8. illustration on how the xrt82d20 samples the data on the tpos and tneg input pins .... 12 1.3 t he p ulse s haping c ircuit ........................................................................................................................... 12 figure 9. illustration of the itu-t g.703 pulse template for e1 application .......................................... 13 1.4 i nterfacing the t ransmit s ection of the xrt82d20 to the l ine ............................................................. 13 figure 10. illustration of how to interface the xrt82d20 to the line for 75 w applications and 3.3v op- eration only .................................................................................................................. .................................. 14 figure 11. illustration of how to interface the xrt82d20 to the line for 120 w applications and 3.3v op- eration only .................................................................................................................. .................................. 15 1.5 i nterfacing the r eceive s ection to the l ine ............................................................................................. 15 figure 12. recommended schematic for transformer-coupling the xrt82d20 to the line for 75 w ap- plications and 5 v operation only ............................................................................................. ................... 16 figure 13. recommended schematic for transformer-coupling the xrt82d20 to the line for 120 w ap- plications and 5 v operation only ............................................................................................. ................... 17 2.0 diagnostic features ....................................................................................................... .................. 17 2.1 t he l ocal l oop -b ack m ode ......................................................................................................................... 17 figure 14. illustration of the analog local loop-back within the xrt82d20 ........................................ 18 2.2 t he r emote l oop b ack m ode ....................................................................................................................... 18 figure 15. illustration of the remote loop-back path, within the xrt82d20 ........................................ 19 package outline drawing ..................................................................................... 20 .r evision h istory .............................................................................................................................. ...... 21
? ? ? ? single channel e1 line interface unit xrt82d20 rev. 1.0.6 3 pin descriptions p in #s ymbol t ype d escription 1 rlos o receiver loss of signal: this pin toggles low to indicate the loss of signal at the receive inputs. 2clklos o receiver loss of clock : with muterx=1, this pin will toggle low to indi- cate a loss of clock has occurred when the receive signal is lost (rlos=0). when rlos=0, no transitions occur on rclk, rpos/rdata and rneg outputs. 3 tneg/code i transmitter negative data input/coding select .with jitter attenuator enabled (pin 18=1), input activity on this pin determines whether the device is configured to operate in single-rail or dual-rail mode. with n-rail transmit data applied to this pin, the device is automatically configured to operate in dual-rail mode for both transmit input and receive output. if this pin is tied high for more than 16 clock cycles, the device is config- ured to operate in single-rail mode with hdb3 encoding and decoding functions enabled. if this pin is tied low for more than 16 clock cycles, the device is config- ured to operate in single-rail mode with ami encoding and decoding functions enabled. (internal pull-down). 4 rneg/lcv o receive negative data/line code violation output. if the device is configured in dual-rail mode with n-rail data applied to pin 3, then the receive negative data will be output through this pin. if the device is configured in single-rail mode and operate with hdb3 coding enabled, hdb3 code violation will be detected and cause this pin to go high. if the device is configured in single-rail mode and with ami coding selected, every bipolar violation will be reported at this pin. 5 rclk o receive clock: output receive clock signal to the terminal equipment. 6 rpos/rdata o receive positive/ data output: in dual-rail mode, this signal is the p-rail receive output data. in single- rail mode, this signal is the receive output data. 7tclk i transmitter clock input: input clock signal (2.048 mhz 50ppm) 8 tpos/tdata i transmit positive / data input. in dual-rail mode, this signal is the p-rail transmit input data. in single-rail mode, this signal is the transmit input data. 9 lloop i local loop back enable (active low): tie this pin low to enable analog local loop-back.in local loop-back mode, transmit output data is looped back to the input of the receiver.input signal at rtip and rring are ignored. local loop-back has priority over remote and digital loop-back mode. see section 2.2 for more details. (internal pull-down). 10 rloop i remote loop back enable (active low): connect this pin to ground to enable remote loop-back. in remote loop-back mode, transmit data at tpos/tdata and tneg are ignored. see section 2.2 for more details. (internal pull-down). 11 dloop i digital loop back enable (active low): connect this pin to ground to enable digital local loop-back.in digital loop-back mode, transmit input data after the encoder is looped back to the jitter attenuator (if selected) and to the receive decoder. input data at rtip and rring are ignored in this mode. (internal pull-up). in this mode, the xrt82d20 can operate only as a jitter attenuator.
xrt82d20 single channel e1 line interface unit ? ? ? ? rev. 1.0.6 4 12 atm i alarm test mode (active-low): connect this pin to ground to force clklos, rlos = 0 and lcv = 1 for testing without affecting data transmission. (internal pull-up) 13 raos i receive all ones: with this pin tied to high, an all 1s signal is inserted to the receiver out- put at rpos and rneg/rdata using mclk as timing reference. this control has priority over digital loop-back if both are enabled. (internal pull-down). 14 taos i transmit all ones: with this pin tied high, an ami encoded all 1s signal is sent to the transmit output using mclk as timing reference. this control has priority over remote loop-back if both are enabled. (internal pull-down). 15 mclk i master clock input: this signal is an independent 2.048 mhz clock with accuracy better than + 50 ppm and duty cycle within 40% to 60%. the function of mclk is to provide timing source for the pll clock recovery circuit, reference clock to insert all 1s data in the transmit as well as receive paths. this signal must be available for the device to operate. 16 jatx/rx (dr/sr) i jitter attenuator path select. with the jitter attenuator enabled, (pin 18 =1), tie this pin high to select the jitter attenuator in the transmit path and tie it low to select in the receive path. data input/output format is then controlled automati- cally by the status of the tneg input. if tneg data is present the device operates in dual-rail data mode. dual-rail/single-rail select: with the jitter attenuator disabled, (pin 18 =0), tie this pin high to select dual-rail data format and tie it low to select single-rail data for- mat. (internal pull-down) 17 digi i digital interface: with this pin tied low, input data at tpos/tdata and tneg/code is active-high and will be sampled by tclk on the falling edge, while active- high rpos/rdata and rneg output data are updated on the falling edge of rclk. see figure 3 and 4 for details. with his pin tied high and in dual-rail mode, transmit input accepts active-low tpos/tdata and tneg/code data and will be sampled by tclk on the falling edge, while rpos/rdata and rneg/lcv are active- low, data is updated on the rising edge of rclk. (internal pull-down). 18 jaen i jitter attenuator enable (active high): connect this pin high to enable the jitter attenuation function.jitter atten- uator path select is determined by the pin 16 setting. (internal pull-down) 19 tgnd - transmitter supply ground 20 tring o transmitter ring output. negative bipolar data output to the line. 21 tvdd - transmit positive supply. 5.0 v + 5% or 3.3 v + 5% 22 ttip o transmitter tip output. positive bipolar data output to the line. 23 txlev i transmit level. tie this pin high for 120 w twisted pair cable operation and tie it low for 75 w coaxial cable operation (internal pull-down). this pin is only active for 5.0v operation. p in #s ymbol t ype d escription
? ? ? ? single channel e1 line interface unit xrt82d20 rev. 1.0.6 5 24 avdd - analog positive supply. 5.0 v + 5% or 3.3 v+ 5% 25 agnd - analog supply ground 26 muterx i mute receive output. with this pin tied high, a loss of receive input signal (rlos=0) will cause clklos to go low and generate the following. dual-rail mode operation: with digi = 0, rclk = 1, rpos and rneg/rdata = 0 fwith digi = 1, rclk =0, rpos and rneg/rdata = 1 single-rail mode: rclk = 1 and rdata=0 (internal pull-down) 27 rring i receive bipolar negative input. bipolar line signal input to the receiver. 28 rtip i receiver bipolar positive input. bipolar line signal input to the receiver. f igure 3. i nterface t iming d iagram in b oth s ingle -r ail and d ual -r ail m ode , with digi (p in 17) = 0 p in #s ymbol t ype d escription tclk tpos/tdata or tneg/code active high active high rclk rpos/rdata or rneg/lcv tclk t r t f t r t f t rcd t rsu t rho
xrt82d20 single channel e1 line interface unit ? ? ? ? rev. 1.0.6 6 f igure 4. i nterface t iming d iagram in d ual -r ail m ode only , with digi (p in 17) = 1 tclk tpos/tdata active low active low rclk rpos/rdata t r t f tclk t tsu t tho t r t f t rsu t rho t rcd
? ? ? ? single channel e1 line interface unit xrt82d20 rev. 1.0.6 7 electrical characteristics t able 1: r eceiver c haracteristics (t a = 25 c, v dd = 3.3v 5% or 5v 5% u nless otherwise specified ) p arameter m in .t yp .m ax u nit receiver sensitivity 8 10 - db interference margin with -6db cable loss -18 -14 - db input impedance measured between rtip or rring to ground 0.9 2.0 - k w recovered clock jitter transfer corner frequency peaking amplitude - - 18 0.1 36 0.5 khz db jitter attenuator corner frequency (-3db curve) - 20 40 hz return loss 51khz-102khz 102khz-2048khz 2048khz-3072khz 12 18 14 25 35 25 - - - db db db t able 2: t ransmitter c haracteristics : (t a = 25 c, v dd = 3.3v 5% or 5v 5% u nless otherwise specified ) p arameter m in .t yp .m ax u nit ami output pulse amplitude 75 w application 120 w application 2.14 2.70 2.37 3.00 2.60 3.30 v v output pulse width 224 244 264 ns output pulse amplitude ratio 0.9 1.0 1.1 jitter added by the transmitter output - 0.025 0.050 uipp output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 20 25 20 - - - db db db t able 3: p ower c onsumption including the l ine p ower d issipation , t ransmission and receive p aths all a ctive (t a = -40 to 85 c, v dd = 3.3v 5% u nless otherwise specified ) s ymbol p arameter m in .t yp .m ax u nit c onditions pc power consumption - 100 140 mw 75 w load, operating at 50% mark density pc power consumption - 92 130 mw 120 w load, operating at 50% mark density pc power consumption - 150 190 mw 75 w load, operating at 100% mark density pc power consumption - 125 160 mw 120 w load, operating at 100% mark density
xrt82d20 single channel e1 line interface unit ? ? ? ? rev. 1.0.6 8 t able 4: p ower c onsumption including the l ine p ower d issipation , t ransmission and receive p aths all a ctive (t a = -40 to 85 c, v dd = 5v 5% u nless otherwise specified ) s ymbol p arameter m in .t yp .m ax u nit c onditions pc power consumption - 160 210 mw 75 w load, operating at 50% mark density pc power consumption - 145 195 mw 120 w load, operating at 50% mark density pc power consumption - 200 260 mw 75 w load, operating at 100% mark density pc power consumption - 180 240 mw 120 w load, operating at 100% mark density t able 5: ac e lectrical c haracteristics (t a = -40 to +85 c, v dd = 3.3v 5% or 5v 5% u nless otherwise specified ) p arameter s ymbol m in .t yp m ax u nits clock frequency mclk -50 ppm 2.048 +50ppm mhz clock duty cycle mclk 40 50 60 % clock period tclk - 244 - ns tclk duty cycle tcdu 30 50 70 % transmit data setup time t tsu 40 - - ns transmit data hold time ttho 40 - - ns tclk rise time (10% /90%) tr - - 40 ns tclk fall time (90% / 10%) tf - - 40 ns rclk duty cycle rcdu 45 50 55 % receive data setup time t rsu 150 244 - ns receive data hold time t rho 150 244 - ns rclk to data delay t rcd - - 40 ns rclk rise time (10%/90%) t r - - 40 ns rclk fall time (90%/10%) t f - - 40 ns
? ? ? ? single channel e1 line interface unit xrt82d20 rev. 1.0.6 9 n ote : all digital output pins except pin 1 and pin 2, which typically source 20a at voh and sink -4ma at vol t able 6: dc e lectrical c haracteristics ; (t a = 25 c, v dd =3.3v 5% or 5v 5% unless otherwise specified ) p arameter s ymbol m in t yp m ax u nit input high voltage 2.0 3.3 or 5.0 5.5 v input low voltage 0.5 0 0.8 v output high voltage @ioh=5ma (see note) vdd=3.3v vdd=5.0v 2.4 2.4 - vdd vdd v output low voltage @ iol=5ma (see note) vdd=3.3v vdd=5.0v 0 0 - 0.4 0.4 v input leakage current (except input pins with pull-up resistors) - 0 10 ua input capacitance - 5 20 pf output load capacitance - - 20 pf absolute maximum ratings storage temperature -65 to 150c operating temperature -40 to 85c supply voltage -0.5v to +6.0v
xrt82d20 single channel e1 line interface unit ? ? ? ? rev. 1.0.6 10 f igure 5. r eceiver m aximum j itter t olerance , t est c onditions : t est p atterrn 2^ 15 -1, (-6 d b) c able l oss 10 0 10 1 10 2 10 3 10 4 10 5 10 ?1 10 0 10 1 10 2 10 3 (freq.(mhz)) input jitter (uip?p) jat disabled itu-t g .823 m ask jat enabled
? ? ? ? single channel e1 line interface unit xrt82d20 rev. 1.0.6 11 f igure 6. r eceiver j itter t ransfer f unction (j itter a ttenuator d isabled , t est c onditions : t est p at - tern 2^ 15 -1, i nput j itter 0.5ui p - p 10 2 10 3 10 4 10 5 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 (freq.(mhz)) 20log(jout/jin) (db) t82d20 performance g.735-g739 specification f igure 7. r eceiver j itter t ransfer f unction (j itter a ttenuator enabled ) t est c onditions : t est p at - tern 2^ 15 -1, i nput j itter 75% of m aximum j itter t olerance 10 0 10 1 10 2 10 3 10 4 10 5 ?60 ?50 ?40 ?30 ?20 ?10 0 10 (freq.(mhz)) jitter attenuation (db) t82d20 performance itu.g.736 mask
xrt82d20 single channel line interface unit ? ? ? ? rev. 1.0.6 12 system description the xrt82d20 is a single channel e1 transceiver that provides an electrical interface for 2.048mbps ap- plications. xrt82d20 includes a receive circuit that converts an itu-t g.703 compliant bipolar signal into a ttl compatible logic levels. the receiver also in- cludes an los (loss of signal) detection circuit. similarly, in the transmit direction, the transmitter converts ttl compatible logic levels into a g.703 compatible bipolar signal. the xrt82d20 consists of both a receive section, jitter attenuator and transmit section; each of these sections will be discussed below. 1.0 the receive section at the receiver input, cable attenuated ami signal can be coupled to the receiver using a capacitor or trans- former. the receive data first goes through the peak detector and data slicer for accurate data recov- ery.the digital representation of the ami signals go to the clock recovery circuit for timing recovery and sub- sequently to the decoder (if selected) for hdb3 de- coding before being output to the rpos/rdata and rneg/lcv pins. the digital data output can be in nrz or rz format depending the mode of operation selected and with the option to be in dual-rail or single rail mode.clock timing recovery of the line interface is accomplished by means of a digital pll scheme which has high input jitter tolerance. the purpose of the receive output interface block is to interface directly with the receiving terminal equipment. the receive output interface block out- puts the data (which has been recovered from the in- coming line signal) to the receive terminal equip- ment via the rpos and rneg output pins. if the receive section of the xrt82d20 has received a positive-polarity pulse, via the rtip and rring input pins, then the receive output interface will output a pulse at the rpos output pin. similarly, if the receive section of the xrt82d20 has received a negative-polarity pulse, via the rtip and rring input pins, then the receive output interface will output a pulse at the rneg output pin. 1.1 jitter attenuator to reduce frequency jitter in the transmit clock or re- ceive clock, a crystal-less jitter attenuator is provid- ed.the jitter attenuator can be selected either in the transmit or receive path or it can be disabled. 1.2 the transmit section in general, the purpose of the transmit section (with- in the xrt82d20) is to accept ttl/cmos level digital data (from the terminal equipment), and to encode it into a format such that it can: 1. be efficiently transmitted over coaxial- or twisted pair cable at the e1 data rate; and 2. be reliably received by the remote terminal equipment at the other end of the e1 data link. 3. comply with the itu-t g.703 pulse template requirements, for e1 applications a 2.048 mhz clock is applied to the tclk input pin and nrz data at the tpos and tneg input pins. the transmit input interface circuit will sample the data, at the tpos and tneg input pins, upon the fall- ing edge of tclk, as illustrated in figure 8below. in general, if the xrt82d20 samples a 1 on the tpos input pin, then the transmit section will ulti- mately generate a positive polarity pulse via the ttip and tring output pins (across a 1:2 transformer). conversely, if the xrt82d20 samples a 1 on the tneg input pin, then the transmit section of the de- vice will ultimately generate a negative polarity pulse via the ttip and tring output pins (across a 1:2 transformer). 1.3 t he p ulse s haping c ircuit the purpose of the transmit pulse shaping circuit is to generate transmit output pulses that comply with f igure 8. i llustration on how the xrt82d20 s amples the data on the tpos and tneg input pins tclk tpos tneg tsu tho
? ? ? ? single channel line interface unit xrt82d20 rev. 1.0.6 13 the itu-t g.703 pulse template requirements for e1 applications. an illustration of the itu-t g.703 pulse template re- quirements is presented below in figure 9. with input signal as described above, the xrt82d20 will take each mark (which is provided to it via the transmit input interface block, and will generate a pulse that complies with the pulse template, present- ed in figure 9 (when measured on the secondary side of the transmit output transformer). 1.4 i nterfacing the t ransmit s ection of the xrt82d20 to the l ine itu-t g.703 specifies that the e1 line signal can be transmitted over coaxial cable and terminated with 75 w or transmitted over twisted-pair and terminated with 120 w . in both applications (e.g., 75 w or 120 w , the user is ad- vised to interface the transmitter to the line, in the manner as depicted in figure 10and figure 11, re- spectively. f igure 9. i llustration of the itu-t g.703 p ulse t emplate for e1 a pplication 0% 50% v = 100% 244ns nominal pulse 219ns (244 - 25) 269ns (244 + 25) 194ns 10% 10% 20%
xrt82d20 single channel line interface unit ? ? ? ? rev. 1.0.6 14 f igure 10. i llustration of how to interface the xrt82d20 to the l ine for 75 w w w w a pplications and 3.3v operation only 200 w 270 w 270 w 75 w 9.1 w 9.1 w 1 : 2 2 : 1 rtip rring ttip tring +3.3 v 0.1 uf tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 uf
? ? ? ? single channel line interface unit xrt82d20 rev. 1.0.6 15 n otes : 1. figure 10 and figure 11indicate that for 3.3 v oper- ation, both 75 w and 120 w applications, the user should connect a 9.1 w resistor in series between the ttip/tring outputs and the transformer. 2. figure 10 and figure 11indicate that the user should use a 2 : 1 step-up transformer. 1.5 i nterfacing the r eceive s ection to the l ine the design of the xrt82d20 permits the user to transformer-couple the receive section to the line. additionally, as mentioned earlier, the specification documents for e1 specify 75 w termination loads, when transmitting over coaxial cable, and 120 w loads, when transmitting over twisted-pair. figure 12 and figure 13 present the various methods that the user can employ to interface the receiver of the xrt82d20 to the line. f igure 11. i llustration of how to interface the xrt82d20 to the l ine for 120 w w w w a pplications and 3.3v operation only 200 w 866 w 866 w 120 w 9.1 w 9.1 w 1 : 2 2 : 1 rtip rring ttip tring +3.3 v 0.1 uf tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 uf
xrt82d20 single channel line interface unit ? ? ? ? rev. 1.0.6 16 f igure 12. r ecommended s chematic for t ransformer -c oupling the xrt82d20 to the l ine for 75 w w w w a pplications and 5 v operation only 200 w 270 w 270 w 75 w 15.4 w 15.4 w 1 : 2 1.36 : 1 rtip rring ttip tring +5 v 0.11 uf tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 uf
? ? ? ? single channel line interface unit xrt82d20 rev. 1.0.6 17 n ote : figure 12 and figure 13indicate that the user should use a 1.36 :1 step-up transformer, when interfacing the receiver to the line. 2.0 diagnostic features in order to support diagnostic operations, the xrt82d20 supports the following loop-back modes: ? local loopback ? remote loopback ? digital loopback each of these loop-back modes will be discussed be- low. 2.1 t he l ocal l oop -b ack m ode when the xrt82d20 is configured to operate in the local loop-back mode, the xrt82d20 will ignore any signals that are input to the rtip and rring input pins. the transmitting terminal equipment will trans- mit data into the xrt82d20 via the tpos, tneg and tclk input pins. this data will be processed through the transmit terminal input interface and the pulse shaping circuit. finally, this data will be output to the line via the ttip and tring output pins. additionally, this data (which is being output via the ttip and tring output pins) will be looped back into the re- ceiver block. as a consequence, this data will also be processed through the entire receive section of the xrt82d20. after this post-loop-back data has been processed through the receive section it will output, to the near-end receiving terminal equipment via the rpos and rneg output pins. figure 14, illustrates the path that the data takes (within the xrt82d20), when the chip is configured to operate in the local loop-back mode. f igure 13. r ecommended s chematic for t ransformer -c oupling the xrt82d20 to the l ine for 120 w w w w a pplications and 5 v operation only 200 w 866 w 866 w 120 w 26.1 w 26.1 w 1 : 2 1.36 : 1 rtip rring ttip tring +5 v 0.1 uf tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 uf
xrt82d20 single channel line interface unit ? ? ? ? rev. 1.0.6 18 the user can configure the xrt82d20 to operate in the local loop-back mode, by pulling the lloop input pin (pin 9) to gnd. 2.2 t he r emote l oop b ack m ode when the xrt82d20 is configured to operate in the remote loop-back mode, the xrt82d20 will ignore any signals that are input to the tpos and tneg in- put pins. the xrt82d20 will receive the incoming line signals, via the rtip and rring input pins. this data will be processed through the entire receive section (within the xrt82d20) and will output to the receive terminal equipment via the rpos and rneg output pins. additionally, this data will also be internally looped back to the transmit input interface block within the transmit section. at this point, this data will be routed through the remainder of the transmit section of the xrt82d20 and will be trans- mitted out onto the line via the ttip and tring output pins. figure 15, illustrates the path that the data takes (within the xrt82d20) when the chip is configured to operate in the remote loop-back mode. f igure 14. i llustration of the a nalog l ocal l oop -b ack within the xrt82d20 hdb3 encoder peak detector local loopback los detect data slicer data & timing recovery hdb3 decoder tx pulse shaper mux mux line driver tclk tpos tneg rclk rpos rneg ttip tring rlos rtip rring mclk timing generator jitter attenuator
? ? ? ? single channel line interface unit xrt82d20 rev. 1.0.6 19 it should be noted that during remote loop-back op- eration, any data which is input via the rtip and rring input pins, will also be output to the terminal equipment, via the rpos and rneg output pins. f igure 15. i llustration of the r emote l oop -b ack path , within the xrt82d20 hdb3 encoder peak detector los detect data slicer data & timing recovery remote loopback hdb3 decoder tx pulse shaper mux mux line driver tclk tpos tneg rclk rpos rneg ttip tring rlos rtip rring mclk timing generator jitter attenuator
xrt82d20 single channel line interface unit ? ? ? ? rev. 1.0.6 20 package outline drawing
? ? ? ? xrt82d20 single channel line interface unit rev. 1.0.6 21 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2000 exar corporation datasheet october 2000 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history rev. 1.0.6 corrections to figures, remove values from pull-up/down resistors, correct formating of .

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