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revision date: ma y 15 , 2007 16 hardware manual renesas 16-bit single-chip microcomputer h8 family / h8/300h super low power series h8/38602r hd64f38602r hd64338602r h8/38600r hd64338600r rev.3.00 rej09b0152-0300 h8/38602r group
rev. 3.00 may 15, 2007 page ii of xxxii
rev. 3.00 may 15, 2007 page iii of xxxii 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials
rev. 3.00 may 15, 2007 page iv of xxxii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed.
rev. 3.00 may 15, 2007 page v of xxxii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index
rev. 3.00 may 15, 2007 page vi of xxxii preface the h8/38602r group consists of single-chip microcomputers made up of the high-speed h8/300h cpu employing renesas technology orig inal architecture as their cores, and the peripheral functions required to configure a system. the h8/300h cpu has an instruction set that is compatible with the h8/300 cpu. target users: this manual was written for users who will be using the h8/38602r group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of th e h8/38602r group to the target users. refer to the h8/300h series software ma nual for a detailed description of the instruction set. notes on reading this manual: in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions, and elect rical characteristics. in order to understand the details of the cpu's functions read the h8/300h series software manual. in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 20, list of registers. example: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right.
rev. 3.00 may 15, 2007 page vii of xxxii notes: when using an on-chip emulator (e7) for h8/38602r program development and debugging, the following restrictions must be noted. 1. the nmi pin is reserved for the e7, and cannot be used. 2. area h'4000 to h'4fff should not be accessed. 3. area h'f780 to h'fb7f should not be accessed. 4. when the e7 is used, nmi is an input/output pin (open-drain in output mode). 5. when on-board programming/erasing is performed in boot mode, the sci3 (p31/rxd3 and p32/txd3) is used. 6. when the on-chip emulator is used, even though the on-chip oscillator is selected, connect a resonator to osc1 and osc2 or i nput an external clock to osc1. 7. when using the e7, set the fromckstp bit in clock halt register 1 to 1. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ h8/38602r group manuals: document title document no. h8/38602r group hardware manual this manual h8/300h series software manual rej09b0213 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0058 microcomputer development environment system h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series high-performance embedded workshop 3 tutorial rej10b0024 h8s, h8/300 series high-performance embe dded workshop 3 user's manual rej10b0026
rev. 3.00 may 15, 2007 page viii of xxxii application notes: document title document no. f-ztat microcomputer on-board programming rej05b0523 all trademarks and registered trademarks ar e the property of th eir respective owners.
rev. 3.00 may 15, 2007 page ix of xxxii contents section 1 overview................................................................................................1 1.1 features....................................................................................................................... ........... 1 1.2 internal bloc k diagram......................................................................................................... .2 1.3 pin assi gnment ................................................................................................................. ..... 3 1.4 pin functions .................................................................................................................. ....... 4 section 2 cpu........................................................................................................7 2.1 address space and memory map .......................................................................................... 8 2.2 register conf igura tion......................................................................................................... .. 9 2.2.1 general registers.................................................................................................... 10 2.2.2 program counter (pc) ............................................................................................ 11 2.2.3 condition-code re gister (ccr)............................................................................. 11 2.3 data formats................................................................................................................... ..... 13 2.3.1 general register data formats ............................................................................... 13 2.3.2 memory data formats ............................................................................................ 15 2.4 instruction set ................................................................................................................ ...... 16 2.4.1 table of instructions cl assified by function .......................................................... 16 2.4.2 basic instructio n formats ....................................................................................... 26 2.5 addressing modes and effec tive address ca lculation........................................................ 27 2.5.1 addressing modes .................................................................................................. 27 2.5.2 effective address calculation ................................................................................ 30 2.6 basic bus cycle ................................................................................................................ ... 32 2.6.1 access to on-chip me mory (ram, rom)............................................................ 32 2.6.2 on-chip peripheral modules .................................................................................. 33 2.7 cpu states ..................................................................................................................... ...... 34 2.8 usage notes .................................................................................................................... ..... 35 2.8.1 notes on data acce ss to empty areas ................................................................... 35 2.8.2 eepmov instru ction.............................................................................................. 35 2.8.3 bit-manipulation instruction .................................................................................. 36 section 3 exception handling .............................................................................41 3.1 exception sources and vector address ............................................................................... 42 3.2 reset .......................................................................................................................... .......... 44 3.2.1 reset exceptio n handling....................................................................................... 44 3.2.2 interrupt immediatel y after reset ........................................................................... 45 3.3 input/output pins .............................................................................................................. ... 46
rev. 3.00 may 15, 2007 page x of xxxii 3.4 register de scriptions.......................................................................................................... .46 3.4.1 interrupt edge select register (iegr) ................................................................... 47 3.4.2 interrupt enable regi ster 1 (ienr1) ...................................................................... 48 3.4.3 interrupt enable regi ster 2 (ienr2) ...................................................................... 49 3.4.4 interrupt flag register 1 (irr1)............................................................................. 50 3.4.5 interrupt flag register 2 (irr2)............................................................................. 51 3.5 interrupt sources.............................................................................................................. .... 52 3.5.1 external interrupts .................................................................................................. 52 3.5.2 internal interrupts ................................................................................................... 53 3.6 operation ...................................................................................................................... ....... 53 3.6.1 interrupt exception handling sequence ................................................................. 56 3.7 stack status after ex ception ha ndling................................................................................. 57 3.7.1 interrupt response time......................................................................................... 57 3.8 usage notes .................................................................................................................... ..... 58 3.8.1 notes on stack area use ........................................................................................ 58 3.8.2 notes on switching functions of external interrupt pins....................................... 59 3.8.3 method for clearing inte rrupt request flags ......................................................... 60 3.8.4 conflict between interrupt ge neration and disabling ............................................ 60 3.8.5 instructions that di sable interrupts......................................................................... 61 3.8.6 interrupts during execution of eepmov inst ruction ............................................ 61 3.8.7 ienr clearing ........................................................................................................ 61 section 4 clock pulse generators ....................................................................... 63 4.1 register de scription ........................................................................................................... .64 4.1.1 oscillator control re gister (o sccr) .................................................................... 64 4.2 system clock oscillator ...................................................................................................... 66 4.2.1 connecting crysta l resona tor ................................................................................ 66 4.2.2 connecting cerami c resonator .............................................................................. 66 4.2.3 external clock input method ................................................................................. 67 4.2.4 on-chip oscillator se lection me thod .................................................................... 67 4.3 subclock os cillato r............................................................................................................ .. 68 4.3.1 connecting 32.768-khz/38.4-k hz crystal re sonator ............................................ 68 4.3.2 pin connection when no t using s ubclock.............................................................. 69 4.3.3 external clock input method ................................................................................. 70 4.3.4 on-chip oscillator se lection me thod .................................................................... 70 4.4 prescalers ..................................................................................................................... ........ 71 4.4.1 prescaler s .............................................................................................................. 71 4.4.2 prescaler w............................................................................................................. 71 4.5 usage notes .................................................................................................................... ..... 72 4.5.1 note on resonators an d resonator circuits ........................................................... 72
rev. 3.00 may 15, 2007 page xi of xxxii 4.5.2 notes on board design ........................................................................................... 74 4.5.3 definition of oscillation st abilization wa it time .................................................. 74 4.5.4 note on subclock stop state................................................................................... 76 4.5.5 note on the oscillation stab ilization of re sonators ............................................... 76 4.5.6 note on using po wer-on reset .............................................................................. 76 4.5.7 note on using on-chip emulator .......................................................................... 76 section 5 power-down modes ............................................................................77 5.1 register de scriptions .......................................................................................................... .78 5.1.1 system control regi ster 1 (syscr1) .................................................................... 78 5.1.2 system control regi ster 2 (syscr2) .................................................................... 80 5.1.3 clock halt registers 1 and 2 (ckstpr1 and ckstpr2) ..................................... 81 5.2 mode transitions and states of lsi..................................................................................... 83 5.2.1 sleep mode ............................................................................................................. 87 5.2.2 standby mode......................................................................................................... 88 5.2.3 watch mode............................................................................................................ 88 5.2.4 subsleep mode........................................................................................................ 89 5.2.5 subactive mode ...................................................................................................... 89 5.2.6 active (medium-sp eed) mode ............................................................................... 90 5.3 direct tr ansition .............................................................................................................. .... 91 5.3.1 direct transition from active (high-speed) mode to active (medium-speed) mode ................................................................. 91 5.3.2 direct transition from active (high- speed) mode to subactive mode................. 92 5.3.3 direct transition from active (medium-speed) mode to active (hig h-speed) mode ...................................................................... 92 5.3.4 direct transition from active (mediu m-speed) mode to subactive mode ........... 93 5.3.5 direct transition from subactive mo de to active (high-speed) mode................. 93 5.3.6 direct transition from subactive mo de to active (medium-speed) mode ........... 94 5.3.7 notes on external input signal change s before/after dir ect transition................. 95 5.4 module standby function.................................................................................................... 96 5.5 on-chip oscillator an d operation mode............................................................................. 96 5.6 usage notes .................................................................................................................... ..... 97 5.6.1 standby mode transiti on and pin states ................................................................ 97 5.6.2 notes on external input signal ch anges before/after standby mode..................... 97 section 6 rom ....................................................................................................99 6.1 block confi guratio n........................................................................................................... 1 00 6.2 register desc riptions ......................................................................................................... 1 01 6.2.1 flash memory control re gister 1 (f lmcr1)...................................................... 101 6.2.2 flash memory control re gister 2 (f lmcr2)...................................................... 102
rev. 3.00 may 15, 2007 page xii of xxxii 6.2.3 erase block regist er 1 (ebr1) ............................................................................ 103 6.2.4 flash memory power contro l register (f lpwcr)............................................. 103 6.2.5 flash memory enable register (fenr)............................................................... 104 6.3 on-board programmi ng modes......................................................................................... 104 6.3.1 boot mode ............................................................................................................ 105 6.3.2 programming/erasure in user program mode...................................................... 108 6.4 flash memory progra mming/erasure................................................................................ 109 6.4.1 programming/programmi ng-verifyi ng................................................................. 109 6.4.2 erasing/erasing-verifying .................................................................................... 112 6.4.3 interrupt handling when progra mming/erasing flash memory........................... 112 6.5 programming/erasing protection....................................................................................... 114 6.5.1 hardware protection ............................................................................................. 114 6.5.2 software protection .............................................................................................. 114 6.5.3 error protection .................................................................................................... 114 6.6 power-down states fo r flash memory.............................................................................. 115 6.7 notes on setting module standby mode ........................................................................... 116 section 7 ram .................................................................................................. 117 section 8 i/o ports............................................................................................. 119 8.1 port 1......................................................................................................................... ......... 119 8.1.1 port data regist er 1 (pdr1) ................................................................................ 120 8.1.2 port control regist er 1 (pcr1) ............................................................................ 120 8.1.3 port pull-up control re gister 1 (pucr1)............................................................ 121 8.1.4 port mode regist er 1 (pmr1) .............................................................................. 121 8.1.5 pin functio ns ........................................................................................................ 122 8.1.6 input pull-up mos............................................................................................... 124 8.2 port 3......................................................................................................................... ......... 124 8.2.1 port data regist er 3 (pdr3) ................................................................................ 125 8.2.2 port control regist er 3 (pcr3) ............................................................................ 125 8.2.3 port pull-up control re gister 3 (pucr3)............................................................ 126 8.2.4 port mode regist er 3 (pmr3) .............................................................................. 126 8.2.5 pin functio ns ........................................................................................................ 127 8.2.6 input pull-up mos............................................................................................... 128 8.3 port 8......................................................................................................................... ......... 128 8.3.1 port data regist er 8 (pdr8) ................................................................................ 129 8.3.2 port control regist er 8 (pcr8) ............................................................................ 129 8.3.3 port pull-up control re gister 8 (pucr8)............................................................ 130 8.3.4 pin functio ns ........................................................................................................ 130 8.3.5 input pull-up mos............................................................................................... 132
rev. 3.00 may 15, 2007 page xiii of xxxii 8.4 port 9......................................................................................................................... ......... 132 8.4.1 port data regist er 9 (pdr9)................................................................................. 133 8.4.2 port control regist er 9 (pcr9) ............................................................................ 133 8.4.3 port open-drain control register 9 (p odr9) ..................................................... 134 8.4.4 port pull-up control re gister 9 (pucr9)............................................................ 134 8.4.5 pin functions ........................................................................................................ 135 8.4.6 input pull-up mos............................................................................................... 137 8.5 port b ......................................................................................................................... ........ 138 8.5.1 port data regist er b (pdrb) ............................................................................... 138 8.5.2 port mode regist er b (pmrb)............................................................................. 139 8.5.3 pin functions ........................................................................................................ 140 8.6 input/output data inversion .............................................................................................. 142 8.6.1 serial port control register ( spcr)..................................................................... 142 8.6.2 port function control register ( pfcr)................................................................ 143 8.7 usage notes .................................................................................................................... ... 144 8.7.1 how to handle un used pin................................................................................... 144 8.7.2 input characteristics differen ce due to pin function ........................................... 144 section 9 timer b1 ............................................................................................145 9.1 features....................................................................................................................... ....... 145 9.2 register desc riptions ......................................................................................................... 1 46 9.2.1 timer mode register b1 (tmb1) ........................................................................ 146 9.2.2 timer counter b1 (tcb1).................................................................................... 147 9.2.3 timer load register b1 (tlb1) .......................................................................... 147 9.3 usage method ................................................................................................................... .148 9.4 operation ...................................................................................................................... ..... 150 9.4.1 interval timer operation ...................................................................................... 150 9.4.2 auto-reload timer operation .............................................................................. 150 9.5 timer b1 operating modes ............................................................................................... 151 section 10 timer w ...........................................................................................153 10.1 features....................................................................................................................... ....... 153 10.2 input/output pins .............................................................................................................. .156 10.3 register desc riptions ......................................................................................................... 1 56 10.3.1 timer mode regist er w (tmrw) ....................................................................... 157 10.3.2 timer control regist er w (tcrw) ..................................................................... 158 10.3.3 timer interrupt enable re gister w (tierw) ...................................................... 159 10.3.4 timer status regist er w (tsrw) ........................................................................ 160 10.3.5 timer i/o control regi ster 0 (tio r0) ................................................................. 161 10.3.6 timer i/o control regi ster 1 (tio r1) ................................................................. 163
rev. 3.00 may 15, 2007 page xiv of xxxii 10.3.7 timer counter (tcnt)......................................................................................... 164 10.3.8 general registers a to d (gra to grd)............................................................. 165 10.4 operation ...................................................................................................................... ..... 166 10.4.1 normal operation ................................................................................................. 166 10.4.2 pwm opera tion.................................................................................................... 170 10.5 operation timing............................................................................................................... 175 10.5.1 tcnt count timing ............................................................................................ 175 10.5.2 output compare output timing........................................................................... 176 10.5.3 input capture timing ........................................................................................... 177 10.5.4 timing of counter clearin g by compare match .................................................. 177 10.5.5 buffer operatio n timing ...................................................................................... 178 10.5.6 timing of imfa to imfd flag setting at comp are match ................................. 179 10.5.7 timing of imfa to imfd se tting at input capture ............................................. 180 10.5.8 timing of status flag clearing............................................................................. 180 10.6 timer w operating modes ................................................................................................ 181 10.7 usage notes .................................................................................................................... ... 181 section 11 realtime clock (rtc)..................................................................... 185 11.1 features....................................................................................................................... ....... 185 11.2 input/output pin ............................................................................................................... .186 11.3 register desc riptions......................................................................................................... 1 87 11.3.1 second data register/free running c ounter data register (rsecdr) ............. 187 11.3.2 minute data regist er (rmind r) ........................................................................ 188 11.3.3 hour data regist er (rhrdr) .............................................................................. 189 11.3.4 day-of-week data regi ster (rwkdr) ............................................................... 190 11.3.5 rtc control register 1 (rtccr1) ..................................................................... 191 11.3.6 rtc control register 2 (rtccr2) ..................................................................... 192 11.3.7 clock source select re gister (rt ccsr)............................................................. 193 11.3.8 rtc interrupt flag re gister (rtc flg) .............................................................. 194 11.4 operation ...................................................................................................................... ..... 196 11.4.1 initial settings of regist ers after po wer-on ......................................................... 196 11.4.2 initial setting pr ocedure ....................................................................................... 196 11.4.3 data reading pr ocedure ....................................................................................... 197 11.5 interrupt sources.............................................................................................................. .. 198 11.6 usage notes .................................................................................................................... ... 199 11.6.1 note on clock count ............................................................................................ 199 11.6.2 note when using rt c interrupts ......................................................................... 199 section 12 watchdog timer.............................................................................. 201 12.1 features....................................................................................................................... ....... 201
rev. 3.00 may 15, 2007 page xv of xxxii 12.2 register desc riptions ......................................................................................................... 2 02 12.2.1 timer control/status regist er wd1 (tcs rwd1)............................................... 203 12.2.2 timer control/status regist er wd2 (tcs rwd2)............................................... 205 12.2.3 timer counter wd (tcwd)................................................................................ 206 12.2.4 timer mode register wd (tmwd) .................................................................... 207 12.3 operation ...................................................................................................................... ..... 208 12.3.1 watchdog time r mode ......................................................................................... 208 12.3.2 interval timer mode............................................................................................. 209 12.3.3 timing of overflow fl ag (ovf) se tting .............................................................. 209 12.4 interrupt ...................................................................................................................... ....... 210 12.5 usage notes .................................................................................................................... ... 210 12.5.1 switching between watchdog timer m ode and interval timer mode................. 210 12.5.2 module standby m ode control............................................................................. 210 12.5.3 clearing the wt/ it or ieovf bit in tcsrwd2 to 0 ......................................... 210 section 13 asynchronous event counter (aec) ..............................................213 13.1 features....................................................................................................................... ....... 213 13.2 input/output pins .............................................................................................................. .215 13.3 register desc riptions ......................................................................................................... 2 15 13.3.1 event counter pwm compare register (e cpwcr) ........................................... 216 13.3.2 event counter pwm data register (e cpwdr).................................................. 217 13.3.3 input pin edge select register (aegsr)............................................................. 218 13.3.4 event counter control register (eccr).............................................................. 219 13.3.5 event counter control/statu s register (eccsr)................................................. 220 13.3.6 event counter h (ech)........................................................................................ 222 13.3.7 event counter l (ecl)......................................................................................... 222 13.4 operation ...................................................................................................................... ..... 223 13.4.1 16-bit counter op eration ..................................................................................... 223 13.4.2 8-bit counter op eration ....................................................................................... 224 13.4.3 irqaec operation............................................................................................... 225 13.4.4 event counter pwm operatio n............................................................................ 225 13.4.5 operation of clock input en able/disable function.............................................. 227 13.5 operating states of async hronous event counter............................................................. 228 13.6 usage notes .................................................................................................................... ... 229 section 14 serial communica tion interface 3 (sci3, irda).............................231 14.1 features....................................................................................................................... ....... 231 14.2 input/output pins .............................................................................................................. .233 14.3 register desc riptions ......................................................................................................... 2 33 14.3.1 receive shift regi ster (rsr) ............................................................................... 234
rev. 3.00 may 15, 2007 page xvi of xxxii 14.3.2 receive data regi ster (rdr)............................................................................... 234 14.3.3 transmit shift regi ster (tsr) .............................................................................. 234 14.3.4 transmit data regi ster (tdr).............................................................................. 234 14.3.5 serial mode regi ster (smr) ................................................................................ 235 14.3.6 serial control re gister (s cr) .............................................................................. 237 14.3.7 serial status regi ster (ssr) ................................................................................. 240 14.3.8 bit rate regist er (brr) ....................................................................................... 243 14.3.9 serial port control register ( spcr)..................................................................... 251 14.3.10 irda control regi ster (ircr)............................................................................... 252 14.3.11 serial extended mode register (s emr) .............................................................. 253 14.4 operation in asynch ronous mode ..................................................................................... 253 14.4.1 clock..................................................................................................................... 254 14.4.2 sci3 initiali zation................................................................................................. 258 14.4.3 data transmission ................................................................................................ 259 14.4.4 serial data reception ........................................................................................... 261 14.5 operation in clock sy nchronous mode............................................................................. 265 14.5.1 clock..................................................................................................................... 265 14.5.2 sci3 initiali zation................................................................................................. 265 14.5.3 serial data tr ansmission ...................................................................................... 266 14.5.4 serial data reception (clock synchronous mode) .............................................. 268 14.5.5 simultaneous serial data tr ansmission and reception........................................ 270 14.6 irda oper ation ................................................................................................................. .271 14.6.1 transmissi on......................................................................................................... 272 14.6.2 reception .............................................................................................................. 273 14.6.3 high-level pulse wi dth selection........................................................................ 273 14.7 interrupt reques ts ............................................................................................................. .274 14.8 usage notes .................................................................................................................... ... 277 14.8.1 break detection an d processing ........................................................................... 277 14.8.2 mark state and br eak sending ............................................................................. 277 14.8.3 receive error flags and transmit operations (clock synchronous mode only) ......................................................................... 277 14.8.4 receive data sampling timing and reception margin in asynchronous mode............................................................................................. 278 14.8.5 note on switching sc k3 pin func tion ................................................................ 279 14.8.6 relation between writing to tdr and b it tdre ................................................ 279 14.8.7 relation between rdr read ing and bit rdrf.................................................... 280 14.8.8 transmit and receive operations wh en making state transition........................ 281 14.8.9 setting in subactive or subsleep mode ................................................................ 281 14.8.10 oscillator when serial communi cation interface 3 is used ................................. 281
rev. 3.00 may 15, 2007 page xvii of xxxii section 15 synchronous seria l communication unit (ssu) ............................283 15.1 features....................................................................................................................... ....... 283 15.2 input/output pins .............................................................................................................. .284 15.3 register desc riptions ......................................................................................................... 2 85 15.3.1 ss control register h (sscrh) .......................................................................... 285 15.3.2 ss control register l (sscrl) ........................................................................... 287 15.3.3 ss mode register (ssmr) ................................................................................... 289 15.3.4 ss enable regist er (sser) .................................................................................. 290 15.3.5 ss status regist er (sssr) .................................................................................... 291 15.3.6 ss receive data regi ster (ssrdr) ..................................................................... 293 15.3.7 ss transmit data regi ster (sstdr).................................................................... 293 15.3.8 ss shift register (sstrsr)................................................................................. 293 15.4 operation ...................................................................................................................... ..... 293 15.4.1 transfer clock ...................................................................................................... 293 15.4.2 relationship between clock polari ty and phase, and data................................... 294 15.4.3 relationship between data input/o utput and shift register ................................ 295 15.4.4 communication modes an d pin functions ........................................................... 296 15.4.5 operation in clocked synchro nous communication mode.................................. 297 15.4.6 operation in four-line bu s communication mode ............................................. 303 15.4.7 initialization in four-line bu s communicatio n mode......................................... 304 15.4.8 serial data tr ansmission ...................................................................................... 305 15.4.9 serial data reception ........................................................................................... 307 15.4.10 scs pin control and arbitration .......................................................................... 309 15.4.11 interrupt re quests ................................................................................................. 310 15.5 usage note..................................................................................................................... .... 310 section 16 i 2 c bus interface 2 (iic2) ................................................................311 16.1 features....................................................................................................................... ....... 311 16.2 input/output pins .............................................................................................................. .313 16.3 register desc riptions ......................................................................................................... 3 14 16.3.1 i 2 c bus control regist er 1 (iccr1 )..................................................................... 314 16.3.2 i 2 c bus control regist er 2 (iccr2 )..................................................................... 317 16.3.3 i 2 c bus mode regist er (icmr)............................................................................ 319 16.3.4 i 2 c bus interrupt enable register (i cier) ........................................................... 321 16.3.5 i 2 c bus status regi ster (icsr)............................................................................. 323 16.3.6 slave address regi ster (sar).............................................................................. 326 16.3.7 i 2 c bus transmit data re gister (icdrt)............................................................. 326 16.3.8 i 2 c bus receive data re gister (icd rr).............................................................. 327 16.3.9 i 2 c bus shift regist er (icdrs)............................................................................ 327
rev. 3.00 may 15, 2007 page xviii of xxxii 16.4 operation ...................................................................................................................... ..... 328 16.4.1 i 2 c bus format...................................................................................................... 328 16.4.2 master transmit operation................................................................................... 329 16.4.3 master receive operation .................................................................................... 331 16.4.4 slave transmit op eration ..................................................................................... 333 16.4.5 slave receive op eration....................................................................................... 336 16.4.6 clock synchronous se rial format ........................................................................ 337 16.4.7 noise can celer...................................................................................................... 340 16.4.8 example of use..................................................................................................... 340 16.5 interrupt request.............................................................................................................. .. 345 16.6 bit synchronous circuit..................................................................................................... 346 16.7 usage notes .................................................................................................................... ... 347 16.7.1 note on issuing stop condition and start (re-transmit) condition .................... 347 16.7.2 note on setting wait bit in i2c bus mode regist er (icmr)............................ 347 16.7.3 restriction on transfer rate setti ng in multimaster operation ........................... 347 16.7.4 restriction on the use of bit manipulation instructions for mst and trs setting in multimas ter opera tion................................................................. 348 16.7.5 usage note on master receive mode................................................................... 348 section 17 a/d converter ................................................................................. 349 17.1 features....................................................................................................................... ....... 349 17.2 input/output pins.............................................................................................................. .350 17.3 register desc riptions......................................................................................................... 3 50 17.3.1 a/d result regist er (adrr) ............................................................................... 350 17.3.2 a/d mode regist er (amr) .................................................................................. 351 17.3.3 a/d start regist er (adsr) .................................................................................. 352 17.4 operation ...................................................................................................................... ..... 353 17.4.1 a/d conversion .................................................................................................... 353 17.4.2 external trigger input timi ng.............................................................................. 353 17.4.3 operating states of a/d converter....................................................................... 354 17.5 example of use................................................................................................................. .354 17.6 a/d conversion accura cy definitions .............................................................................. 357 17.7 usage notes .................................................................................................................... ... 359 17.7.1 permissible signal s ource impedance .................................................................. 359 17.7.2 influences on abso lute accuracy ......................................................................... 359 17.7.3 usage notes .......................................................................................................... 360 section 18 comparators .................................................................................... 361 18.1 features....................................................................................................................... ....... 361 18.2 input/output pins.............................................................................................................. .362
rev. 3.00 may 15, 2007 page xix of xxxii 18.3 register desc riptions ......................................................................................................... 3 62 18.3.1 compare control registers 0, 1 (cmcr0, cmcr1) ........................................... 362 18.3.2 compare data regi ster (cmdr).......................................................................... 364 18.4 operation ...................................................................................................................... ..... 365 18.4.1 operation sequence .............................................................................................. 365 18.4.2 hysteresis characteristic s of compar ator............................................................. 366 18.4.3 interrupt se tting .................................................................................................... 366 18.5 usage notes .................................................................................................................... ... 368 section 19 power-on reset circuit ...................................................................369 19.1 feature ........................................................................................................................ ....... 369 19.2 operation ...................................................................................................................... ..... 370 19.2.1 power-on reset circuit ........................................................................................ 370 section 20 list of registers ...............................................................................371 20.1 register addresses (a ddress order).................................................................................. 372 20.2 register bits.................................................................................................................. ..... 376 20.3 register states in ea ch operating mode ........................................................................... 380 section 21 electrica l characteristics .................................................................385 21.1 absolute maximum ratings for f-ztat ve rsion............................................................. 385 21.2 electrical characteristics fo r f-ztat version.................................................................. 386 21.2.1 power supply voltage an d operating range........................................................ 386 21.2.2 dc character istics ................................................................................................ 393 21.2.3 ac character istics ................................................................................................ 399 21.2.4 a/d converter char acteristic s .............................................................................. 405 21.2.5 comparator char acteristic s................................................................................... 407 21.2.6 watchdog timer ch aracteristic s........................................................................... 407 21.2.7 power-on reset circu it characteris tics ............................................................... 408 21.2.8 flash memory char acteristi cs .............................................................................. 409 21.3 absolute maximum ratings fo r masked rom version.................................................... 411 21.4 electrical characteristics for masked rom ve rsion......................................................... 412 21.4.1 power supply voltage an d operating range........................................................ 412 21.4.2 dc character istics ................................................................................................ 419 21.4.3 ac character istics ................................................................................................ 425 21.4.4 a/d converter char acteristic s .............................................................................. 431 21.4.5 comparator char acteristic s................................................................................... 433 21.4.6 watchdog timer ch aracteristic s........................................................................... 433 21.4.7 power-on reset circu it characteris tics ............................................................... 434 21.5 operation timing............................................................................................................... 435
rev. 3.00 may 15, 2007 page xx of xxxii 21.6 output load circuit ........................................................................................................... 4 40 21.7 recommended re sonators................................................................................................. 440 21.8 usage note..................................................................................................................... .... 441 appendix ......................................................................................................... 443 a. instruction set ................................................................................................................ .... 443 a.1 instruction list...................................................................................................... 443 a.2 operation code map............................................................................................. 458 a.3 number of execu tion stat es ................................................................................. 461 a.4 combinations of instructions and addressing modes .......................................... 472 b. i/o ports...................................................................................................................... ....... 473 b.1 i/o port block diagrams ...................................................................................... 473 b.2 port states in each operating st ate ...................................................................... 486 b.3 port 9 related register se ttings and pin functions.............................................. 487 c. product part no. lineup .................................................................................................... 491 d. package dime nsions .......................................................................................................... 492 main revisions and additions in this edition..................................................... 495 index ......................................................................................................... 513
rev. 3.00 may 15, 2007 page xxi of xxxii figures section 1 overview figure 1.1 internal block diagram of h8/38602r group .............................................................. 2 figure 1.2 pin assignment of h8/38602r group (tnp-32) .......................................................... 3 figure 1.3 pin assignment of h8/38602r grou p (32p6u-a)........................................................ 3 section 2 cpu figure 2.1 memory map........................................................................................................ ......... 8 figure 2.2 cpu regi sters ..................................................................................................... .......... 9 figure 2.3 usage of general registers ........................................................................................ .10 figure 2.4 relationship between stack pointer an d stack area ................................................... 11 figure 2.5 general regi ster data formats (1).............................................................................. 13 figure 2.5 general regi ster data formats (2).............................................................................. 14 figure 2.6 memo ry data formats............................................................................................... .. 15 figure 2.7 inst ruction formats............................................................................................... ....... 26 figure 2.8 branch address specifi cation in memory indirect mode ........................................... 30 figure 2.9 on-chip memory acces s cycle.................................................................................. 32 figure 2.10 on-chip peripheral mo dule access cycle (3 -state access)..................................... 33 figure 2.11 cp u operating states............................................................................................. ... 34 figure 2.12 state tran siti ons ................................................................................................ ........ 35 figure 2.13 example of timer configuration with two registers allocated to same address ............................................................................................................ 36 section 3 exception handling figure 3.1 reset exce ption handling sequence........................................................................... 45 figure 3.2 block diagram of interrupt controller........................................................................ 54 figure 3.3 flow up to interrupt acceptance ................................................................................. 55 figure 3.4 interrupt ex ception handlin g sequence...................................................................... 56 figure 3.5 stack status after exceptio n handling ........................................................................ 57 figure 3.6 operation when odd address is set in sp .................................................................. 58 figure 3.7 pfcr and pmrb (or aegsr) setting and interrupt request flag clearing procedure .............................................................................................. 59 section 4 clock pulse generators figure 4.1 block diagram of clock pulse generators.................................................................. 63 figure 4.2 typical connect ion to crystal resonator.................................................................... 66 figure 4.3 typical connect ion to ceramic resonator.................................................................. 66 figure 4.4 example of external clock input ................................................................................ 67 figure 4.5 typical connection to 32 .768-khz/38.4-khz cr ystal resonator................................ 68 figure 4.6 equivalent circuit of 32 .768-khz/38.4-khz cr ystal res onator.................................. 69
rev. 3.00 may 15, 2007 page xxii of xxxii figure 4.7 pin connection when not using subclock .................................................................. 69 figure 4.8 pin connection wh en inputting exte rnal clock .......................................................... 70 figure 4.9 example of crystal and ceramic resonator assignment............................................ 72 figure 4.10 negative resistance measurem ent and circuit modifi cation suggestions ............... 73 figure 4.11 example of incorrect board design .......................................................................... 74 figure 4.12 oscillation stabilization wait time .......................................................................... 75 section 5 power-down modes figure 5.1 mode transition diagram ........................................................................................... 84 figure 5.2 standby mode transition and pin states..................................................................... 97 figure 5.3 external input signal capture when signal changes before/after standby m ode or watch mode ............................................................... 98 section 6 rom figure 6.1 flash memory block config uration.......................................................................... 100 figure 6.2 programming/erasing flowch art example in user program mode.......................... 108 figure 6.3 program/prog ram-verify fl owchart ......................................................................... 110 figure 6.4 erase/eras e-verify flowchart ................................................................................... 113 figure 6.5 module st andby mode setting.................................................................................. 116 section 8 i/o ports figure 8.1 port 1 pin config uration.......................................................................................... .. 119 figure 8.2 port 3 pin config uration.......................................................................................... .. 124 figure 8.3 port 8 pin config uration.......................................................................................... .. 128 figure 8.4 port 9 pin config uration.......................................................................................... .. 132 figure 8.5 port b pin config uration.......................................................................................... .138 figure 8.6 input/output da ta inversion function....................................................................... 142 section 9 timer b1 figure 9.1 block di agram of timer b1...................................................................................... 145 figure 9.2 timer b1 initial setti ng flow ................................................................................... 14 8 figure 9.3 processing flow when cha nging setting during counter operation ....................... 149 section 10 timer w figure 10.1 timer w block diagram......................................................................................... 155 figure 10.2 free-runnin g counter operation ............................................................................ 166 figure 10.3 periodic counter operation..................................................................................... 16 7 figure 10.4 0 and 1 output example (toa = 0, tob = 1)........................................................ 167 figure 10.5 toggle output example (toa = 0, tob = 1) ........................................................ 168 figure 10.6 toggle output example (toa = 0, tob = 1) ........................................................ 168 figure 10.7 input capt ure operating example........................................................................... 169 figure 10.8 buffer operatio n example (input capture)............................................................. 170 figure 10.9 pwm mo de example (1) ........................................................................................ 171
rev. 3.00 may 15, 2007 page xxiii of xxxii figure 10.10 pwm m ode example (2) ...................................................................................... 171 figure 10.11 buffer operatio n example (outpu t compare) ...................................................... 172 figure 10.12 pwm mode example (tob, toc, and tod = 0: initial out put values are set to 0)............................... 173 figure 10.13 pwm mode example (tob, toc, and tod = 1: initial out put values are set to 1)............................... 174 figure 10.14 count timing fo r internal cloc k source ............................................................... 175 figure 10.15 count timing fo r external cloc k source.............................................................. 175 figure 10.16 output co mpare output timing ........................................................................... 176 figure 10.17 input capt ure input signa l timing........................................................................ 177 figure 10.18 timing of counte r clearing by comp are matc h................................................... 177 figure 10.19 buffer operat ion timing (compa re match).......................................................... 178 figure 10.20 buffer operat ion timing (input capture) ............................................................. 178 figure 10.21 timing of imfa to im fd flag setting at compare match .................................. 179 figure 10.22 timing of imfa to im fd flag setting at input capture...................................... 180 figure 10.23 timing of stat us flag clearing by cpu................................................................ 180 figure 10.24 contention betw een tcnt write and clear ......................................................... 183 figure 10.25 internal clock sw itching and tcnt operation.................................................... 183 section 11 realtime clock (rtc) figure 11.1 bloc k diagram of rtc ........................................................................................... 18 6 figure 11.2 definition of time expr ession ................................................................................ 191 figure 11.3 initia l setting procedure ........................................................................................ .. 196 figure 11.4 example: readin g of inaccurate time data............................................................ 197 section 12 watchdog timer figure 12.1 block diagra m of watchdog timer ........................................................................ 202 figure 12.2 example of wa tchdog timer op eration.................................................................. 208 figure 12.3 interval timer mode operation............................................................................... 209 figure 12.4 timing of ovf flag setting.................................................................................... 209 section 13 asynchrono us event counter (aec) figure 13.1 block diagram of asynchronous ev ent count er .................................................... 214 figure 13.2 software procedure when us ing ech and ecl as 16-b it event coun ter.............. 223 figure 13.3 software procedure when us ing ech and ecl as 8-bit event counters .............. 224 figure 13.4 event count er operation waveform....................................................................... 226 figure 13.5 example of clock control op eration...................................................................... 227 section 14 serial communica tion interface 3 (sci3, irda) figure 14.1 bloc k diagram of sci3 ........................................................................................... 2 32 figure 14.2 data format in asynchronous co mmunication ...................................................... 254
rev. 3.00 may 15, 2007 page xxiv of xxxii figure 14.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-b it data, parity, two stop bits) ............ 254 figure 14.4 sample sci3 initialization fl owchart ..................................................................... 258 figure 14.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit)........................................................................... 259 figure 14.6 sample serial transmi ssion flowchart (async hronous mode) .............................. 260 figure 14.7 example sci3 operatio n in reception in asynchronous mode (8-bit data, parity, one stop bit)........................................................................... 262 figure 14.8 sample serial data recep tion flowchart (asynchronous mode) (1) ..................... 263 figure 14.8 sample serial data recep tion flowchart (asynchronous mode) (2) ..................... 264 figure 14.9 data format in clock synchronous communication.............................................. 265 figure 14.10 example of sci3 operation in transmission in clock synchronous mode ..................................................................................... 266 figure 14.11 sample serial transmissi on flowchart (clock sy nchronous mode) .................... 267 figure 14.12 example of sci3 reception operation in clock sy nchronous mode................... 268 figure 14.13 sample serial reception flowchart (clock sync hronous mode) ......................... 269 figure 14.14 sample flowchart of simultaneous serial transmit and receive operations (clock synchronous mode) .................................................. 270 figure 14.15 irda block diagram............................................................................................. 2 71 figure 14.16 irda transm ission and r eception ........................................................................ 272 figure 14.17 (a) rdrf setting and rxi interrupt ..................................................................... 276 figure 14.17 (b) tdre setting and txi interrupt ..................................................................... 276 figure 14.17 (c) tend setting and tei interrupt...................................................................... 276 figure 14.18 receive data sampli ng timing in asynchronous mode ...................................... 278 figure 14.19 relation betwee n rdr read timing and data..................................................... 280 section 15 synchronous seri al communication unit (ssu) figure 15.1 bloc k diagram of ssu............................................................................................ 2 84 figure 15.2 relationship between cl ock polarity and phase, and data ..................................... 294 figure 15.3 relationship between data input/output pin and shift register ............................ 295 figure 15.4 initialization in cloc ked synchronous comm unication mode................................ 297 figure 15.5 example of oper ation in data tr ansmission .......................................................... 298 figure 15.6 sample serial transmission flowchart ................................................................... 299 figure 15.7 example of operatio n in data receptio n (mss = 1) .............................................. 300 figure 15.8 sample serial reception flowchart (mss = 1)....................................................... 301 figure 15.9 sample flowchart for se rial transmit and recei ve operations.............................. 302 figure 15.10 initialization in fo ur-line bus communi cation mode ......................................... 304 figure 15.11 example of operatio n in data transmi ssion (mss = 1)....................................... 306 figure 15.12 example of opera tion in data recep tion (mss = 1) ............................................ 308 figure 15.13 arbitr ation check timing ..................................................................................... 309
rev. 3.00 may 15, 2007 page xxv of xxxii section 16 i 2 c bus interface 2 (iic2) figure 16.1 block diagram of i 2 c bus interf ace 2..................................................................... 312 figure 16.2 external circu it connections of i/o pins ................................................................ 313 figure 16.3 i 2 c bus form ats ...................................................................................................... 328 figure 16.4 i 2 c bus timi ng........................................................................................................ 328 figure 16.5 master transmit mode operation timing (1) ......................................................... 330 figure 16.6 master transmit mode operation timing (2) ......................................................... 330 figure 16.7 master receive mode operation timing (1)........................................................... 332 figure 16.8 master receive mode operation timing (2)........................................................... 333 figure 16.9 slave transmit mode operation timing (1) ........................................................... 334 figure 16.10 slave transmit mode operation timing (2) ......................................................... 335 figure 16.11 slave receive mode operation timing (1)........................................................... 336 figure 16.12 slave receive mode operation timing (2)........................................................... 337 figure 16.13 clock synchronou s serial transfer format .......................................................... 337 figure 16.14 transmit mode operatio n timing......................................................................... 338 figure 16.15 receive mo de operation timing .......................................................................... 339 figure 16.16 block diag ram of noise conceler......................................................................... 340 figure 16.17 sample flowchar t for master tr ansmit mode....................................................... 341 figure 16.18 sample flowchar t for master r eceive mode ........................................................ 342 figure 16.19 sample flowchar t for slave tran smit mode......................................................... 343 figure 16.20 sample flowch art for slave r eceive mode .......................................................... 344 figure 16.21 timing of b it synchronous circuit ....................................................................... 346 section 17 a/d converter figure 17.1 block diag ram of a/d c onverter ........................................................................... 349 figure 17.2 external trigger input timing ................................................................................ 353 figure 17.3 example of a/d conversion op eration .................................................................. 355 figure 17.4 flowchart of procedure for us ing a/d converter (polli ng by software) ............... 356 figure 17.5 flowchart of procedure for using a/d converter (i nterrupts used) ...................... 356 figure 17.6 a/d conversion accuracy definitions (1) .............................................................. 358 figure 17.7 a/d conversion accuracy definitions (2) .............................................................. 358 figure 17.8 example of analog input circuit ............................................................................ 359 section 18 comparators figure 18.1 block diag ram of comparators............................................................................... 361 figure 18.2 hysteresis/non-h ysteresis selecti on by cdr......................................................... 366 figure 18.3 procedure fo r setting interrupt (1) .......................................................................... 367 figure 18.4 procedure fo r setting interrupt (2) .......................................................................... 368 section 19 power-on reset circuit figure 19.1 powe r-on reset circuit........................................................................................... 369 figure 19.2 power-on rese t circuit opera tion timing ............................................................. 370
rev. 3.00 may 15, 2007 page xxvi of xxxii section 21 electrical characteristics figure 21.1 power supply voltage an d oscillation frequenc y range (1) ................................. 386 figure 21.2 power supply voltage an d oscillation frequenc y range (2) ................................. 387 figure 21.3 power supply voltage an d operating frequenc y range (1)................................... 388 figure 21.4 power supply voltage an d operating frequenc y range (2)................................... 389 figure 21.5 power supply voltage an d operating frequenc y range (3)................................... 390 figure 21.6 analog power supply voltage and operating frequency range of a/d converter (1) ................................................................................................... 391 figure 21.7 analog power supply voltage and operating frequency range of a/d converter (2) ................................................................................................... 392 figure 21.8 power supply voltage an d oscillation frequenc y range (1) ................................. 412 figure 21.9 power supply voltage an d oscillation frequenc y range (2) ................................. 413 figure 21.10 power supply voltage and operating freque ncy range (1)................................. 414 figure 21.11 power supply voltage and operating freque ncy range (2)................................. 415 figure 21.12 power supply voltage and operating freque ncy range (3)................................. 416 figure 21.13 analog power supply voltage and operating frequency range of a/d converter (1).................................................................................................. 417 figure 21.14 analog power supply voltage and operating frequency range of a/d converter (2).................................................................................................. 418 figure 21.15 cl ock input timing .............................................................................................. .435 figure 21.16 res low width timing........................................................................................ 435 figure 21.17 input timing.................................................................................................... ...... 435 figure 21.18 sck3 input clock timing .................................................................................... 435 figure 21.19 sci3 input/output ti ming in clock synchronous mode...................................... 436 figure 21.20 ssu input/output ti ming in clock synchronous mode....................................... 436 figure 21.21 ssu input/output timing (four-line bus communication mo de, master, cphs = 1) ................................. 437 figure 21.22 ssu input/output timing (four-line bus communication mo de, master, cphs = 0) ................................. 437 figure 21.23 ssu input/output timing (four-line bus communication mo de, slave, cp hs = 1) ................................... 438 figure 21.24 ssu input/output timing (four-line bus communication mo de, slave, cp hs = 0) ................................... 438 figure 21.25 i 2 c bus interface input/o utput timing ................................................................. 439 figure 21.26 power-on re set circuit rese t timing .................................................................. 439 figure 21.27 out put load condition.......................................................................................... 4 40 figure 21.28 reco mmended resona tors .................................................................................... 440 appendix figure b.1 (a) port 1 block diagram (p12)................................................................................ 473 figure b.1 (b) port 1 block diagram (p11)................................................................................ 474
rev. 3.00 may 15, 2007 page xxvii of xxxii figure b.1 (c) port 1 block diagram (p10)................................................................................ 475 figure b.2 (a) port 3 block diagram (p32)................................................................................ 476 figure b.2 (b) port 3 block diagram (p31)................................................................................ 477 figure b.2 (c) port 3 block diagram (p30)................................................................................ 478 figure b.3 (a) port 8 bloc k diagram (p84 to p82)..................................................................... 479 figure b.4 (a) port 9 block diagram (p93)................................................................................ 480 figure b.4 (b) port 9 block diagram (p92)................................................................................ 481 figure b.4 (c) port 9 block diagram (p91)................................................................................ 482 figure b.4 (d) port 9 block diagram (p90)................................................................................ 483 figure b.5 (a) port b bloc k diagram (pb5 or pb4) .................................................................. 484 figure b.5 (b) port b bloc k diagram (pb3 or pb2) .................................................................. 484 figure b.5 (c) port b bloc k diagram (pb1 or pb0) .................................................................. 485 figure d.1 package di mensions (tnp-32) ................................................................................ 492 figure d.2 package di mensions (32p6u-a).............................................................................. 493
rev. 3.00 may 15, 2007 page xxviii of xxxii
rev. 3.00 may 15, 2007 page xxix of xxxii tables section 1 overview table 1.1 pin functions ............................................................................................................ 4 section 2 cpu table 2.1 operation notation ................................................................................................. 16 table 2.2 data transfer instructions....................................................................................... 17 table 2.3 arithmetic operations instructions (1) ................................................................... 18 table 2.3 arithmetic operations instructions (2) ................................................................... 19 table 2.4 logic operations instructions................................................................................. 20 table 2.5 shift instru ctions..................................................................................................... 20 table 2.6 bit manipulation inst ructions (1)............................................................................ 21 table 2.6 bit manipulation inst ructions (2)............................................................................ 22 table 2.7 branch instructions ................................................................................................. 23 table 2.8 system control instructions.................................................................................... 24 table 2.9 block data transfer instructions ............................................................................ 25 table 2.10 addressing modes .................................................................................................. 27 table 2.11 absolute address access ranges ........................................................................... 29 table 2.12 effective address ca lculation (1)........................................................................... 30 table 2.12 effective address ca lculation (2)........................................................................... 31 section 3 exception handling table 3.1 exception sources and vector address .................................................................. 42 table 3.2 reset so urces.......................................................................................................... 44 table 3.3 pin configuration.................................................................................................... 46 table 3.4 interrupt wa it states ............................................................................................... 57 section 4 clock pulse generators table 4.1 methods for selecting system clock oscillator and on-chip oscillator............... 67 section 5 power-down modes table 5.1 operating frequency and waiting time................................................................. 79 table 5.2 transition mode after sleep instructio n execution and interrupt handling ........ 85 table 5.3 internal state in ea ch operating mode................................................................... 86 section 6 rom table 6.1 setting programmi ng modes ................................................................................ 104 table 6.2 boot mode operation ........................................................................................... 107 table 6.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible......................................................................................... 108 table 6.4 reprogramming data com putation table ............................................................ 111
rev. 3.00 may 15, 2007 page xxx of xxxii table 6.5 additional-program data computation table ...................................................... 111 table 6.6 programming time ............................................................................................... 111 table 6.7 flash memory oper ating states............................................................................ 115 section 9 timer b1 table 9.1 timer b1 operating modes .................................................................................. 151 section 10 timer w table 10.1 timer w functions ............................................................................................... 154 table 10.2 pin configuration.................................................................................................. 156 table 10.3 timer w operating modes ................................................................................... 181 section 11 realtime clock (rtc) table 11.1 pin configuration.................................................................................................. 186 table 11.2 interrupt sources................................................................................................... 198 section 12 watchdog timer table 12.1 assembly program for clearing wt/ it or ieovf bit to 0 ................................. 211 table 12.2 the value of "xx" ................................................................................................. 211 section 13 asynchrono us event counter (aec) table 13.1 pin configuration.................................................................................................. 215 table 13.2 examples of event count er pwm oper ation....................................................... 226 table 13.3 operating states of asynch ronous event counter................................................ 228 table 13.4 maximum clock frequency ................................................................................. 229 section 14 serial communica tion interface 3 (sci3, irda) table 14.1 pin configuration.................................................................................................. 233 table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (1) ..................................................... 244 table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (2) ..................................................... 244 table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (3) ..................................................... 245 table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (4) ..................................................... 245 table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (1) ..................................................... 246 table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (2) ..................................................... 246 table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (3) ..................................................... 247
rev. 3.00 may 15, 2007 page xxxi of xxxii table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (4)...................................................... 247 table 14.4 relation between n and clock .............................................................................. 248 table 14.5 maximum bit rate for each fre quency (asynchronous mode) .......................... 248 table 14.6 brr settings for various bit rates (c lock synchronous mode) (1) ................... 249 table 14.6 brr settings for various bit rates (c lock synchronous mode) (2) ................... 250 table 14.7 relation between n and clock .............................................................................. 250 table 14.8 data transfer formats (a synchronous mode)...................................................... 255 table 14.9 smr settings and corresponding data transfer formats.................................... 256 table 14.10 smr and scr settings and cl ock source sel ection............................................ 257 table 14.11 ssr status flags and recei ve data ha ndling...................................................... 262 table 14.12 ircks2 to ircks0 bit settin gs............................................................................. 273 table 14.13 sci3 interrupt requests........................................................................................ 274 table 14.14 transmit/receive interrupts ................................................................................. 275 section 15 synchronous seri al communication unit (ssu) table 15.1 pin configuration.................................................................................................. 284 table 15.2 relationship between communication modes and input/o utput pins.................. 296 table 15.3 interrupt re quests ................................................................................................. 310 section 16 i 2 c bus interface 2 (iic2) table 16.1 pin configuration.................................................................................................. 313 table 16.2 transfer rate ........................................................................................................ 316 table 16.3 interrupt re quests ................................................................................................. 345 table 16.4 time for monitoring scl..................................................................................... 346 section 17 a/d converter table 17.1 pin configuration.................................................................................................. 350 table 17.2 operating states of a/d converter....................................................................... 354 section 18 comparators table 18.1 pin configuration.................................................................................................. 362 table 18.2 combination of cmr and cmls bits ................................................................. 364 section 21 electrical characteristics table 21.1 absolute maximum ratings ................................................................................. 385 table 21.2 dc character istics ................................................................................................ 393 table 21.3 control signal timing .......................................................................................... 399 table 21.4 serial interface timing ......................................................................................... 402 table 21.5 synchronous serial communica tion unit (ssu) timing ..................................... 403 table 21.6 i 2 c bus interface timing ...................................................................................... 404 table 21.7 a/d converter char acteristic s .............................................................................. 405 table 21.8 comparator char acteristic s................................................................................... 407
rev. 3.00 may 15, 2007 page xxxii of xxxii table 21.9 watchdog timer ch aracteristic s........................................................................... 407 table 21.10 power-on reset circuit charact eristics ............................................................... 408 table 21.11 flash memory characteris tics .............................................................................. 409 table 21.12 absolute maximum ratings ................................................................................. 411 table 21.13 dc character istics ................................................................................................ 419 table 21.14 control signal timing .......................................................................................... 425 table 21.15 serial interface timing ......................................................................................... 428 table 21.16 synchronous serial communica tion unit (ssu) timing ..................................... 429 table 21.17 i 2 c bus interface timing...................................................................................... 430 table 21.18 a/d converter char acteristic s.............................................................................. 431 table 21.19 comparator char acteristic s................................................................................... 433 table 21.20 watchdog timer ch aracteristic s........................................................................... 433 table 21.21 power-on reset circu it characteris tics ............................................................... 434 appendix table a.1 instruction set....................................................................................................... 445 table a.2 operation code map (1) ....................................................................................... 458 table a.2 operation code map (2) ....................................................................................... 459 table a.2 operation code map (3) ....................................................................................... 460 table a.3 number of cycles in each instruction.................................................................. 462 table a.4 number of cycles in each instruction.................................................................. 463 table a.5 combinations of instructions and addressing modes .......................................... 472 table b.1 port 9 related register se ttings and pin functions.............................................. 487
section 1 overview rev. 3.00 may 15, 2007 page 1 of 516 rej09b0152-0300 section 1 overview 1.1 features ? high-speed h8/300h central processing un it with an internal 16-bit architecture ? upward-compatible with h8/300 cpu on an object level ? sixteen 16-bit general registers ? 62 basic instructions ? various peripheral functions ? rtc (can be used as a free-running counter) ? asynchronous event counter (aec) ? timer b1 ? timer w ? watchdog timer ? sci (asynchronous or clock synchronous serial communication interface) ? ssu (synchronous serial communication unit)* ? i 2 c bus interface (conforms to the i 2 c bus interface format that is advocated by philips electronics)* ? 10-bit a/d converter ? comparators note: * ssu and iic2 are shared. ? on-chip memory product classification model rom ram flash memory version (f-ztat tm version) h8/38602rf hd64f38602r 16 kbytes 1 kbyte h8/38602r hd64338602r 16 kbytes 1 kbyte masked rom version h8/38600r hd64338600r 8 kbytes 512 bytes note: f-ztat tm is a trademark of renesas technology corp. ? general i/o ports ? i/o pins: 13 i/o pins, including three large current ports (i ol = 15 ma, @v ol = 1.0 v) ? input-only pins: 6 input pins (also used as analog input pins) ? supports various power-down states
section 1 overview rev. 3.00 may 15, 2007 page 2 of 516 rej09b0152-0300 ? compact package package code body si ze pin pitch remarks p-vqfn-32 tnp-32 5 6 mm 0.5 mm p-lqfp-32 32p6u-a 7 7 mm 0.8 mm 1.2 internal block diagram subclock oscillator h8/300h cpu system clock oscillator p10/aevh/ftioa/tmow/clkout p11/aevl/ftci (/ irq1 ) p12/irqaec/aecpwm vcc avcc vss res test/ adtrg nmi * 1 p90/ scs /scl p91/ssck/sda p92/sso (/ irq0 ) p93/ssi (/ irq1 ) x1 x2 osc1 osc2 pb0/an0/ irq0 pb1/an1/ irq1 pb2/an2 pb3/an3 pb4/an4/comp0 pb5/an5/comp1 p82/ftiob p83/ftioc p84/ftiod p30/sck3/vc ref (/ irq0 ) p31/rxd3/irrxd p32/txd3/irtxd rom port 1 port 8 port 9 port b port 3 watchdog timer timer b1 10-bit a/d converter asynchronous event counter i 2 c bus interface 2 * 2 sci3/irda notes: 1. the nmi pin is not available when the e7 or on-chip emulator debugger is used. 2. ssu and iic2 are shared. ram power-on reset circuit realtime clock timer w comparators ssu * 2 e7_0 e7_1 e7_2 figure 1.1 internal block diagram of h8/38602r group
section 1 overview rev. 3.00 may 15, 2007 page 3 of 516 rej09b0152-0300 1.3 pin assignment avcc x1 x2 res osc2 v ss osc1 vcc test/ adtrg 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 25 24 23 22 21 20 19 18 17 p31/rxd3/irrxd p32/txd3/irtxd p93/ssi (/ irq1 ) p92/sso (/ irq0 ) p91/ssck/sda p90/ scs /scl e7_0 e7_1 e7_2 16 15 14 13 12 11 10 p30/sck3/vc ref (/ irq0 ) pb5/an5/comp1 pb4/an4/comp0 pb3/an3 pb2/an2 pb1/an1/ irq1 pb0/an0/ irq0 nmi p12/irqaec/aecpwm p11/aevl/ftci (/ irq1 ) p10/aevh/ftioa/tmow/clkout p82/ftiob p83/ftioc p84/ftiod tnp-32 (top view) figure 1.2 pin assignment of h8/38602r group (tnp-32) avcc x1 x2 res osc2 v ss osc1 vcc 1 2 3 4 5 6 7 8 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 p32/txd3/irtxd p93/ssi (/ irq1 ) p92/sso (/ irq0 ) p91/ssck/sda p90/ scs /scl e7_0 e7_1 e7_2 16 15 14 13 12 11 10 p31/rxd3/irrxd p30/sck3/vc ref (/ irq0 ) pb5/an5/comp1 pb4/an4/comp0 pb3/an3 pb2/an2 pb1/an1/ irq1 pb0/an0/ irq0 nmi p12/irqaec/aecpwm p11/aevl/ftci (/ irq1 ) p10/aevh/ftioa/tmow/clkout p82/ftiob p83/ftioc p84/ftiod test/ adtrg 32p6u-a (top view) figure 1.3 pin assignment of h8/38602r group (32p6u-a)
section 1 overview rev. 3.00 may 15, 2007 page 4 of 516 rej09b0152-0300 1.4 pin functions table 1.1 pin functions type symbol pin no. i/o functions vcc 8 input power supply pin. connect this pin to the system power supply. vss 6 input ground pin. connect th is pin to the system power supply (0 v). power supply pins avcc 1 input analog power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. clock pins osc1 7 input osc2 5 output these pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. see section 4, clock pulse generators, for a typical connection. x1 2 input x2 3 output these pins connect with a 32.768- or 38.4-khz crystal resonator for the subclock. see section 4, clock pulse generators, for a typical connection. clkout 13 output clock output pin. system control res 4 input reset pins. the power-on reset circuit is incorporated. when externally driven low, the chip is reset. test 9 input test pins. also used as the adtrg pin. when this pin is not used as the adtrg pin, users cannot use this pin. connect this pin to vss. when this pin is used as the adtrg pin, see section 17.4.2, external trigger input timing.
section 1 overview rev. 3.00 may 15, 2007 page 5 of 516 rej09b0152-0300 type symbol pin no. i/o functions nmi 16 input nmi interrupt request pin. non-maskable interrupt request input pin. in the f-ztat version, the level on this pin determines whether to enter the user or boot mode when the reset state is released. to enter the user mode, pull up this pin to the vcc level. irq0 32 (22, 26) input irq1 31 (14, 23) input external interrupt request input pins. can select the rising or falling edge. interrupt pins irqaec 15 input interrupt input pin for the asynchronous event counter. this pin enables the asynchronous event input. ftci 14 input external event input pin. timer w ftioa to ftiod 13 to 10 i/o output compare output/input capture input/pwm output pins. aevl 14 input aevh 13 input event input pins for input to the asynchronous event counter. asynchro- nous event counter (aec) aecpwm 15 output pwm output pin for the aec. rtc tmow 13 output divided clo ck output pin for the rtc. sck3 26 i/o sci3 clock i/o pin. rxd3/ irrxd 25 input sci3 data input pins or data input pins for the irda format. serial communi- cation interface 3 (sci3) txd3/ irtxd 24 output sci3 data output pins or data output pins for the irda format. scs 20 i/o ssu chip select i/o pin. ssck 21 i/o ssu clock i/o pin. ssi 23 i/o synchro- nous serial communi- cation unit (ssu) sso 22 i/o ssu transmit/receive data i/o pins. sda 21 i/o iic data i/o pin. i 2 c bus interface 2 (iic2) scl 20 i/o iic clock i/o pin.
section 1 overview rev. 3.00 may 15, 2007 page 6 of 516 rej09b0152-0300 type symbol pin no. i/o functions an0 to an5 32 to 27 input analog data input pins for the a/d converter. a/d converter adtrg 9 input external trigger input pin for the a/d converter. comp0 comp1 28 27 input analog data input pins for the comparator. comparators vcref 26 input reference voltage pin for external input of threshold voltage of the comparator analog input pins. p10 to p12 13 to 15 i/o 3-bit i/o pins. input or output can be designated for each bit by means of the port control register 1 (pcr1). p30 to p32 26 to 24 i/o 3-bit i/o pins. input or output can be designated for each bit by means of the port control register 3 (pcr3). p82 to p84 12 to 10 i/o 3-bit i/o pins. input or output can be designated for each bit by means of the port control register 8 (pcr8). p90 to p93 20 to 23 i/o 4-bit i/o pins. input or output can be designated for each bit by means of the port control register 9 (pcr9). i/o ports pb0 to pb5 32 to 27 input 6-bit input-only pins. e7 e7_0 e7_1 e7_2 19 to 17 ? e7 emulator interface pins. e7_2 selects whether the on-chip oscillator is used. e7_2 is pulled up or down by a 100-k ? resistance. for details, see section 4, clock pulse generators.
section 2 cpu cpu30h2c_000120030300 rev. 3.00 may 15, 2007 page 7 of 516 rej09b0152-0300 section 2 cpu this lsi has an h8/300h cpu with an internal 32- bit architecture that is upward compatible with the h8/300 cpu, and supports only normal mode, which has a 64-kbyte address space. ? ? ? ? ? ?
section 2 cpu rev. 3.00 may 15, 2007 page 8 of 516 rej09b0152-0300 ? h'0000 h'3fff h'f020 h'f100 h'fb80 h'ff80 h'ffff h'0050 hd64f38602r (flash memory version) interrupt vector not used on-chip rom (16 kbytes) not used internal i/o registers internal i/o registers on-chip ram (1 kbyte) h'0000 h'3fff h'f020 h'f100 h'fb80 h'ff80 h'ffff h'0050 hd64338602r (masked rom version) interrupt vector not used on-chip rom (16 kbytes) not used internal i/o registers internal i/o registers on-chip ram (1 kbyte) h'0000 h'1fff h'f020 h'f100 h'fd80 h'ff80 h'ffff h'0050 hd64338600r (masked rom version) interrupt vector not used on-chip rom (8 kbytes) not used internal i/o registers internal i/o registers on-chip ram (512 bytes) figure 2.1 memory map
section 2 cpu rev. 3.00 may 15, 2007 page 9 of 516 rej09b0152-0300 2.2 register configuration the h8/300h cpu has the internal registers shown in figure 2.2. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), and an 8-bit condition-code register (ccr). pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: ccr: i: ui: stack pointer program counter condition-code register interrupt mask bit user bit half-carry flag user bit negative flag zero flag overflow flag carry flag er0 er1 er2 er3 er4 er5 er6 er7 iuihunzvc ccr 76543210 h: u: n: z: v: c: general registers (ern) control registers (cr) [legend] (sp) figure 2.2 cpu registers
section 2 cpu rev. 3.00 may 15, 2007 page 10 of 516 rej09b0152-0300 2.2.1 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address register s and data registers. when a general register is used as a data register, it can be accessed as a 32-b it, 16-bit, or 8-bit regist er. figure 2.3 illustrates the usage of the general registers. when the genera l registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. the usage of each register can be selected independently. address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.3 usage of general registers
section 2 cpu rev. 3.00 may 15, 2007 page 11 of 516 rej09b0152-0300 general register er7 has the function of the stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.4 shows the relationship between the stack pointer and the stack area. sp (er7) empty area stack area figure 2.4 relationship between stack pointer and stack area 2.2.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). the pc is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v ), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. some instructions leave flag bits unchanged. op erations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a. 1, instruction list.
section 2 cpu rev. 3.00 may 15, 2007 page 12 of 516 rej09b0152-0300 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an e xception-handling sequence. 6 ui undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is execut ed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h fl ag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructi ons, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions.
section 2 cpu rev. 3.00 may 15, 2007 page 13 of 516 rej09b0152-0300 2.3 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.3.1 general register data formats figure 2.5 shows the data formats in general registers. 7 0 7 0 msb lsb msb lsb 70 4 3 don't care don't care don't care 7 0 4 3 70 don't care 65432 71 0 7 0 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type general register data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.5 general register data formats (1)
section 2 cpu rev. 3.00 may 15, 2007 page 14 of 516 rej09b0152-0300 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb ern: en: rn: rnh: rnl: msb: lsb: general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format general register word data word data rn en longword data [legend] ern figure 2.5 general register data formats (2)
section 2 cpu rev. 3.00 may 15, 2007 page 15 of 516 rej09b0152-0300 2.3.2 memory data formats figure 2.6 shows the data formats in memory. the h8/300h cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd addr ess, an address error does not occur, however the least significant bit of the address is re garded as 0, so access begins the preceding address. this also applies to instruction fetches. when er7 (sp) is used as an address register to access the stack area, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.6 memory data formats
section 2 cpu rev. 3.00 may 15, 2007 page 16 of 516 rej09b0152-0300 2.4 instruction set 2.4.1 table of instructions classified by function the h8/300h cpu has 62 instructions. tables 2.2 to 2.9 summarize the instructions in each functional category. the notation used in tables 2.2 to 2.9 is defined below. table 2.1 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers/address register (er0 to er7).
section 2 cpu rev. 3.00 may 15, 2007 page 17 of 516 rej09b0152-0300 table 2.2 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is id entical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 may 15, 2007 page 18 of 516 rej09b0152-0300 table 2.3 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on da ta in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte dat a in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general re gister by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 may 15, 2007 page 19 of 516 rej09b0152-0300 table 2.3 arithmetic operations instructions (2) instruction size * function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general regist er with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arith metic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 may 15, 2007 page 20 of 516 rej09b0152-0300 table 2.4 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement (logical complement) of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.5 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl rotr b/w/l rd (rotate) rd rotates general register contents. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 may 15, 2007 page 21 of 516 rej09b0152-0300 table 2.6 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immedi ate data or the lower three bits of a general register. bnot b ? ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. btst b ? ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. t he bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 3.00 may 15, 2007 page 22 of 516 rej09b0152-0300 table 2.6 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( of ) c xors the carry flag with a specified bi t in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c xors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ? ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ? c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 3.00 may 15, 2007 page 23 of 516 rej09b0152-0300 table 2.7 branch instructions instruction size function bcc * ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine note: * bcc is the general name for conditional branch instructions.
section 2 cpu rev. 3.00 may 15, 2007 page 24 of 516 rej09b0152-0300 table 2.8 system control instructions instruction size * function trapa ? starts trap-instruction exception handling rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr moves the source operand contents to the ccr. the ccr size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ccr logically ands the ccr with immediate data. orc b ccr #imm ccr logically ors the ccr with immediate data. xorc b ccr #imm ccr logically xors the ccr with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word
section 2 cpu rev. 3.00 may 15, 2007 page 25 of 516 rej09b0152-0300 table 2.9 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l?1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction be gins as soon as the transfer is completed.
section 2 cpu rev. 3.00 may 15, 2007 page 26 of 516 rej09b0152-0300 2.4.2 basic instruction formats h8/300h cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op), a register field (r), an eff ective address extension (e a), and a condition field (cc). figure 2.7 shows examples of instruction formats. ? ? ? ? op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm rn rm op ea(disp) op cc ea(disp) bra d:8 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.7 instruction formats
section 2 cpu rev. 3.00 may 15, 2007 page 27 of 516 rej09b0152-0300 2.5 addressing modes and effective address calculation the following describes the h8/300h cpu. in this lsi, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.10. each instruction uses a subset of these addressing modes. addressing modes that can be used differ depending on the instruction. for details, refer to appendix a.4, combinations of instructions and addressing modes. arithmetic and logic instructions can use the regist er direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.10 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displa cement @(d:16,ern)/@(d:24,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx: 8/#xx:16/#xx:32 7 program-counter relati ve @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8
section 2 cpu rev. 3.00 may 15, 2007 page 28 of 516 rej09b0152-0300 register direct?rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. register indirect? @ ern the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand on memory. register indirect with displacement ?@(d:16, ern) or @(d:24, ern) a 16-bit or 24-bit displacement cont ained in the instruction is adde d to an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. a 16-bit displacemen t is sign-extended when added. register indirect with post-incremen t or pre-decrement?@ern+ or @-ern ? ? ?
section 2 cpu rev. 3.00 may 15, 2007 page 29 of 516 rej09b0152-0300 the access ranges of absolute addr esses for this lsi are those s hown in table 2. 11, because the upper 8 bits are ignored. table 2.11 absolute address access ranges absolute address access range 8 bits (@aa:8) h'ff00 to h'ffff 16 bits (@aa:16) h'0000 to h'ffff 24 bits (@aa:24) h'0000 to h'ffff immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bsr instruction. an 8-b it or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memo ry operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byt e of the memory operand is ignored, generating a 24-bit branch address. figure 2.8 shows how to specify branch address for in memory indirect mode. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff). note that the first part of the address range is also the exception vector area.
section 2 cpu rev. 3.00 may 15, 2007 page 30 of 516 rej09b0152-0300 specified by @aa:8 branch address dummy figure 2.8 branch a ddress specification in memory indirect mode 2.5.2 effective address calculation table 2.12 indicates how effectiv e addresses are calculated in each addressing mode. in this lsi the upper 8 bits of the ef fective address are ignored in order to generate a 16-bit effective address. table 2.12 effective ad dress calculation (1) no 1 r o p 31 0 23 2 3 registe r indirect with dis placement @(d: 16,ern) or @(d: 24,ern) 4 r o p disp r op rm op rn 3 1 0 0 r o p 2 3 0 31 0 dis p 31 0 31 0 23 0 23 0 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand is general register contents. the value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
section 2 cpu rev. 3.00 may 15, 2007 page 31 of 516 rej09b0152-0300 table 2.12 effective ad dress calculation (2) no 5 op 23 0 abs @aa:8 7 h'ffff op 23 0 @aa:16 @aa:24 abs 15 16 23 0 op abs 6 op imm #xx:8/#xx:16/#xx:32 8 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 7 p rogr am- counter re lativ e @(d:8 ,pc ) @( d:16 ,pc) mem or y indirect @@ aa:8 23 0 di s p 0 23 0 disp op 23 op 8 abs 23 0 abs h' 0000 7 8 0 15 23 0 1 5 h'00 16 [legend] r, rm,rn : op : disp : imm : abs : register field operation field displacement immediate data absolute address pc contents sign extension memory contents
section 2 cpu rev. 3.00 may 15, 2007 page 32 of 516 rej09b0152-0300 2.6 basic bus cycle cpu operation is synchronized by a system clock ( t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub or figure 2.9 on-chip memory access cycle
section 2 cpu rev. 3.00 may 15, 2007 page 33 of 516 rej09b0152-0300 2.6.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits or 16 bits depending on the register. for description on the data bus width and number of accessing states of each register, refer to sect ion 20.1, register addresses (address order). registers with 16-bit data bus width can be accessed by word size only. registers with 8-bit data bus width can be accessed by byte or word size. wh en a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. in two-state access, the operation timing is the same as that for on-chip memory. figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub or figure 2.10 on-chip peripheral mo dule access cycle (3-state access)
section 2 cpu rev. 3.00 may 15, 2007 page 34 of 516 rej09b0152-0300 2.7 cpu states there are four cpu states: the re set state, program execution st ate, program halt state, and exception-handling state. the program execution state includes active (h igh-speed or medium- speed) mode and subactive mode. for the progra m halt state, there are sleep (high-speed or medium-speed) mode, standby mode, watch mode, and subsleep mode. these states are shown in figure 2.11. figure 2.12 shows the state trans itions. for details on pr ogram execution state and program halt state, refer to section 5, power-down modes. for details on exception handling, refer to section 3, exception handling. cpu state reset state program execution state active (high-speed) mode active (medium-speed) mode power-down modes subactive mode sleep (high-speed) mode sleep (medium-speed) mode standby mode watch mode subsleep mode program halt state a state in which the cpu operation is stopped to reduce power consumption a transient state in which the cpu changes the processing flow due to a reset or an interrupt exception-handling state the cpu is initialized the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock figure 2.11 cpu operating states
section 2 cpu rev. 3.00 may 15, 2007 page 35 of 516 rej09b0152-0300 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs interrupt source exception- handling complete reset occurs figure 2.12 state transitions 2.8 usage notes 2.8.1 notes on data access to empty areas the address space of this lsi includes empty areas in additio n to the rom, ram, and on-chip i/o registers areas available to the user. when da ta is transferred from cpu to empty areas, the transferred data will be lost. this action may al so cause the cpu to malfunction. when data is transferred from an empty ar ea to cpu, the contents of the data cannot be guaranteed. 2.8.2 eepmov instruction eepmov is a block-transfer instru ction and transfers th e byte size of data indicated by r4 or r4l, which starts from the addres s indicated by r5, to the addres s indicated by r6. set r4, r4l, and r6 so that the end address of th e destination address (value of r6 + +
section 2 cpu rev. 3.00 may 15, 2007 page 36 of 516 rej09b0152-0300 2.8.3 bit-manipulation instruction the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. special care is required wh en using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, becau se this may rewrite data of a bit other than the bit to be manipulated. bit manipulation for two registers assigned to the same address example 1: bit manipulation for the timer load register and timer counter figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. when a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. data is read in byte units. 2. the cpu sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal data bus figure 2.13 example of timer configuration with two registers allo cated to same address
section 2 cpu rev. 3.00 may 15, 2007 page 37 of 516 rej09b0152-0300 example 2: when the bset instruction is executed for port 5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins and output low-level signals. an example to output a high-level signal at p50 with a bset instruction is shown below. ? p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bset #0, @pdr5 the bset instruction is executed for port 5. ? p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 0 1 0 0 0 0 0 1 ?
section 2 cpu rev. 3.00 may 15, 2007 page 38 of 516 rej09b0152-0300 as a result of the bset instruction, bit 0 in pdr5 becomes 1, and p50 outputs a high-level signal. however, bits 7 and 6 of pdr5 end up with different values. to prevent this problem, store a copy of the pdr5 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr5. prior to executing bset instruction mov.b #h'80, r0l mov.b r0l, @ram0 mov.b r0l, @pdr5 the pdr5 value (h'80) is written to a work area in memory (ram0) as well as to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 1 0 0 0 0 0 0 0 ? ? p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 1 ram0 1 0 0 0 0 0 0 1
section 2 cpu rev. 3.00 may 15, 2007 page 39 of 516 rej09b0152-0300 bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 5 control register pcr5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins that output low-level signals. an example of setting the p50 pin as an input pin by the bclr instruction is shown below. it is assumed that a high-level signal will be input to this input pin. ? p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bclr #0, @pcr5 the bclr instruction is executed for pcr5. ? p57 p56 p55 p54 p53 p52 p51 p50 input/output output output output output output ou tput output input pin state low level high level low level low level low level low level low level high level pcr5 1 1 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ?
section 2 cpu rev. 3.00 may 15, 2007 page 40 of 516 rej09b0152-0300 ? p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 1 ? ? p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output out put output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 0
section 3 exception handling rev. 3.00 may 15, 2007 page 41 of 516 rej09b0152-0300 section 3 exception handling exception handling is caused by a reset, a trap instruction (trapa), or interrupts. ? reset a reset has the highest exception priority. excep tion handling starts after the reset state is cleared by a negation of the res signal. exception handling is also started when the watchdog timer overflows. the exception hand ling executed at this time is the same as that for a reset by the res pin. ? trap instruction exception handling starts when a trap instruction (trapa) is executed. a vector address corresponding to a vector number from 0 to 3 wh ich are specified in the instruction code is generated. exception handling can be executed at all times in the pr ogram execution state, regardless of the setting of the i bit in ccr. ? interrupts external interrupts other than the nmi and intern al interrupts are masked by the i bit in ccr, and kept pending while the i bit is set to 1. exception handling starts when the current instruction or exception handling ends, if an interrupt is requested.
section 3 exception handling rev. 3.00 may 15, 2007 page 42 of 516 rej09b0152-0300 3.1 exception sources and vector address table 3.1 shows the vector addresses and priority of each exception handling. when more than one interrupt is requested, handling is performed from the interrupt with the highest priority. table 3.1 exception sou rces and vector address source origin exception sources vector number vector address priority reset pin/ watchdog timer reset 0 h'0000 to h'0001 high ? reserved for system use 1 to 6 h'0002 to h'000d external interrupt nmi 7 h'000e to h'000f trap instruction trapa #0 trap instruction #0 8 h'0010 to h'0011 trap instruction trapa #1 trap instruction #1 9 h'0012 to h'0013 trap instruction trapa #2 trap instruction #2 10 h'0014 to h'0015 trap instruction trapa #3 trap instruction #3 11 h'0016 to h'0017 ? reserved for system us e 12 h'0018 to h'0019 cpu direct transition by executing the sleep instruction 13 h'001a to h'001b ? reserved for system use 14, 15 h'001c to h'001f external interrupts irq0 16 h'0020 to h'0021 irq1 17 h'0022 to h'0023 irqaec 18 h'0024 to h'0025 ? reserved for system use 19, 20 h'0026 to h'0029 comparators comp0 21 h'002a to h'002b comp1 22 h'002c to h'002d rtc 0.25-second overflow 23 h'002e to h'002f 0.5-second overflow 24 h'0030 to h'0031 second periodic overflow 25 h'0032 to h'0033 minute periodic overflow 26 h'0034 to h'0035 hour periodic overflow 27 h'0036 to h'0037 day-of-week periodic overflow 28 h'0038 to h'0039 week periodic overflow 29 h'003a to h'003b free-running overflow 30 h'003c to h'003d low
section 3 exception handling rev. 3.00 may 15, 2007 page 43 of 516 rej09b0152-0300 source origin exception sources vector number vector address priority wdt wdt overflow (interval timer) 31 h'003e to h'003f high asynchronous event counter asynchronous event counter overflow 32 h'0040 to h'0041 timer b1 overflow 33 h'0042 to h'0043 synchronous serial communication unit (ssu)/ iic2 * overrun error (ssu) transmit data empty (ssu) transmit end (ssu) receive data full (ssu) conflict error (ssu)/ transmit data empty (iic2) transmit end (iic2) receive data full (iic2) nack detection (iic2) arbitration (iic2) overrun error (iic2) 34 h'0044 to h'0045 timer w input capture a/compare match a input capture b/compare match b input capture c/compare match c input capture d/compare match d overflow 35 h'0046 to h'0047 ? reserved for system us e 36 h'0048 to h'0049 sci3 transmit end transmit data empty receive data full overrun error framing error parity error 37 h'004a to h'004b a/d converter a/d conversi on end 38 h'004c to h'004d ? reserved for system use 39 h'004e to h'004f low note: * the ssu and iic share the same vector addr ess. when using the iic, shift the ssu to standby mode using ckstpr2.
section 3 exception handling rev. 3.00 may 15, 2007 page 44 of 516 rej09b0152-0300 3.2 reset a reset has the highest exception priority. there are three sources to generate a re set. table 3.2 lists the reset sources. table 3.2 reset sources reset source description res pin low level input power-on reset circuit when the power supply voltage (vcc) rises for details, see section 19, power-on reset circuit. watchdog timer when the counter overflows for details, see section 12, watchdog timer. 3.2.1 reset exception handling when a reset source is generated, all the processing in execution is terminated and this lsi enters the reset state. the internal state of the cpu an d the registers of the on-chip peripheral modules are initialized by a reset. to ensure that this lsi is reset, handle the res pin as shown below. ? when power is supplied, or the system clock oscillator is stopped hold the res pin low until oscillation of the system clock oscillator has stabilized. ? when the system clock oscillator is operating hold the res pin low for the t rel state, which is specified as the electrical characteristics. after a reset source is generated, this lsi starts reset exception handling as follows. 1. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized, and the i bit in ccr is set to 1. 2. the reset exception handling vector address (h'0000 and h'0001) is read and transferred to the pc, and then program execution starts from the address indicated by the pc. the reset exception handling sequence by the res pin is shown in figure 3.1.
section 3 exception handling rev. 3.00 may 15, 2007 page 45 of 516 rej09b0152-0300 vector fetch internal address bus internal read signal internal write signal internal data bus (16 bits) res internal processing initial program instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) initial program instruction (2) (3) (2) (1) reset cleared figure 3.1 reset exception handling sequence 3.2.2 interrupt imme diately after reset immediately after a reset, if an interrupt is accepted before the st ack pointer (sp) is initialized, pc and ccr will not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling al l interrupts are masked . for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.l #xx: 32, sp).
section 3 exception handling rev. 3.00 may 15, 2007 page 46 of 516 rej09b0152-0300 3.3 input/output pins table 3.3 shows the pin configuration of the interrupt controller. table 3.3 pin configuration name i/o function nmi input nonmaskable external interrupt pin rising or falling edge can be selected irqaec input maskable external interrupt pin rising, falling, or both edges can be selected irq1 irq0 input input maskable external interrupt pins rising or falling edge can be selected 3.4 register descriptions the interrupt controller has the following registers. ? interrupt edge select register (iegr) ? interrupt enable register 1 (ienr1) ? interrupt enable register 2 (ienr2) ? interrupt flag register 1 (irr1) ? interrupt flag register 2 (irr2)
section 3 exception handling rev. 3.00 may 15, 2007 page 47 of 516 rej09b0152-0300 3.4.1 interrupt edge se lect register (iegr) iegr selects whether interrupt requests of the nmi , adtrg , irq1 , and irq0 pins are generated at the rising edge or falling edge. bit bit name initial value r/w descriptions 7 nmieg 0 r/w nmi edge select 0: detects a falling edge of the nmi pin input 1: detects a rising edge of the nmi pin input 6 ? 0 ? reserved this bit is always read as 0. 5 adtrgneg 0 r/w adtrg edge select 0: detects a falling edge of the adtrg pin input 1: detects a rising edge of the adtrg pin input 4 to 2 ? all 0 ? reserved the write value should always be 0. 1 ieg1 0 r/w irq1 edge select 0: detects a falling edge of the irq1 pin input 1: detects a rising edge of the irq1 pin input 0 ieg0 0 r/w irq0 edge select 0: detects a falling edge of the irq0 pin input 1: detects a rising edge of the irq0 pin input
section 3 exception handling rev. 3.00 may 15, 2007 page 48 of 516 rej09b0152-0300 3.4.2 interrupt enable register 1 (ienr1) ienr1 enables the rtc, irqaec, irq1, and irq0 interrupts. bit bit name initial value r/w description 7 ienrtc 0 r/w rtc interrupt request enable the rtc interrupt request is enabled when this bit is set to 1. 6 to 3 ? all 0 ? reserved the write value should always be 0. 2 ienec2 0 r/w irqaec interrupt request enable the irqaec interrupt request is enabled when this bit is set to 1. 1 ien1 0 r/w irq1 interrupt request enable the irq1 interrupt request is enabled when this bit is set to 1. 0 ien0 0 r/w irq0 interrupt request enable the irq0 interrupt request is enabled when this bit is set to 1.
section 3 exception handling rev. 3.00 may 15, 2007 page 49 of 516 rej09b0152-0300 3.4.3 interrupt enable register 2 (ienr2) ienr2 enables the a/d converter, timer b1, and asynchronous event counter interrupts. bit bit name initial value r/w description 7 ? 0 ? reserved the write value should always be 0. 6 ienad 0 r/w a/d converter interrupt request enable the a/d converter interrupt request is enabled when this bit is set to 1. 5 to 3 ? all 0 ? reserved the write value should always be 0. 2 ientb1 0 r/w timer b1 interrupt request enable the timer b1 interrupt request is enabled when this bit is set to 1. 1 ? 0 ? reserved the write value should always be 0. 0 ienec 0 r/w asynchronous event counter interrupt request enable the asynchronous event counter interrupt request is enabled when this bit is set to 1.
section 3 exception handling rev. 3.00 may 15, 2007 page 50 of 516 rej09b0152-0300 3.4.4 interrupt flag register 1 (irr1) irr1 indicates the irqaec, irq1, an d irq0 interrupt request status. bit bit name initial value r/w description 7 to 3 ? all 0 ? reserved the write value should always be 0. 2 irrec2 0 r/(w) * irqaec interrupt request flag [setting condition] when the p12 pin is set to the irqaec/aecpwm pin and the specified edge is de tected as the pin state [clearing condition] when 0 is written to this bit 1 irri1 0 r/(w) * irq1 interrupt request flag [setting condition] when the irq1 pin is set as the interrupt input pin and the specified edge is detected [clearing condition] when 0 is written to this bit 0 irri0 0 r/(w) * irq0 interrupt request flag [setting condition] when the irq0 pin is set as the interrupt input pin and the specified edge is detected [clearing condition] when 0 is written to this bit note: * only 0 can be written to clear the flag.
section 3 exception handling rev. 3.00 may 15, 2007 page 51 of 516 rej09b0152-0300 3.4.5 interrupt flag register 2 (irr2) irr2 indicates the interrupt request status of th e a/d converter, timer b1, and asynchronous event counter. bit bit name initial value r/w description 7 ? 0 ? reserved the write value should always be 0. 6 irrad 0 r/(w) * a/d converter interrupt request flag [setting condition] when a/d conversion ends [clearing condition] when 0 is written to this bit 5 to 3 ? all 0 ? reserved the write value should always be 0. 2 irrtb1 0 r/(w) * timer b1 interrupt request flag [setting condition] when the timer b1 compare match or overflow occurs [clearing condition] when 0 is written to this bit 1 ? 0 ? reserved the write value should always be 0. 0 irrec 0 r/(w) * asynchronous event counter interrupt request flag [setting condition] when the asynchronous event counter overflows [clearing condition] when 0 is written to this bit note: * only 0 can be written to clear the flag.
section 3 exception handling rev. 3.00 may 15, 2007 page 52 of 516 rej09b0152-0300 3.5 interrupt sources 3.5.1 external interrupts there are four ex ternal interrupts: nmi, irqaec, irq1, and irq0. (1) nmi interrupt nmi is the highest-priority inte rrupt, and is always accepted by th e cpu regardless of the state of the i bit in ccr. the nmieg bit in iegr can be us ed to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. (2) irq1 and irq0 interrupts irq1 and irq0 interrupts are requested by input signals at irq1 and irq0 pins. using the ieg1 and ieg0 bits in iegr, it is possibl e to select whether an interrupt is generated by a rising or falling edge at irq1 and irq0 pins. when the specified edge is input while the irq1 and irq0 pin functions are selected by pfcr and pmrb, the corresponding bit in irr1 is set to 1 and an interrupt request is generated. clearing the ien1 and ien0 bits in ienr1 to 0 disables the in terrupt request to be accepted. setting the i bit in ccr to 1 masks all interrupts. (3) irqaec interrupts an irqaec interrupt is requested by an input signal at the irqaec pin or iecpwm (pwm output for the aec). when the irqaec pin is us ed as an external interrupt pin, clear the ecpwme bit in aegsr to 0. using the aiegs1 and aiegs0 bits in aegsr, it is possible to select whether an interrupt is generated by a rising edge, falling edge, or both edges. when the ienec2 bit in ienr1 is set to 1 and the specified edge is input, the corresponding bit in irr1 is set to 1 and an interrupt request is ge nerated. for details, see section 13, asynchronous event counter (aec).
section 3 exception handling rev. 3.00 may 15, 2007 page 53 of 516 rej09b0152-0300 3.5.2 internal interrupts internal interrupts generated from the on-chip peripheral modules have the following features: ? for each on-chip peripheral module, there are fl ags that indicate the interrupt request status, and enable bits that select enab ling or disabling of these interrupts. internal interrupts can be controlled independently. if an enable bit is set to 1, an interrupt request is sent to the interrupt controller. 3.6 operation nmi interrupts are accepted at all times except in the reset state. in the case of irq interrupts and on-chip peripheral module interr upts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlle d by the interrupt controller. figure 3.2 shows a block diagram of the interrupt controller. figure 3.3 shows the flow up to interrupt acceptance. interrupt operation is described as follows. 1. if an interrupt source whose interrupt enable regi ster bit is set to 1 occurs, an interrupt request is sent to the interrupt controller. 2. when the interrupt controller receives an interr upt request, it sets the interrupt request flag. 3. from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending (see table 3.1). 4. the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. 5. if the interrupt request is accepted, after proce ssing of the current inst ruction is completed, both pc and ccr are pushed onto the stack. the stat e of the stack at this time is shown in figure 3.5. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 6. the i bit of ccr is set to 1, masking further interrupts. 7. the vector address correspond ing to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the conten ts of the vector address is executed.
section 3 exception handling rev. 3.00 may 15, 2007 page 54 of 516 rej09b0152-0300 external or internal interrupts external interrupts or internal interrupt enable signals interrpt controller interrupt request ccr (cpu) i priority decision logic figure 3.2 block diagra m of interrupt controller
section 3 exception handling rev. 3.00 may 15, 2007 page 55 of 516 rej09b0152-0300 program execution state irri0 = 1 irri1 = 1 ien1 = 1 irrec2 = 1 ienec2 = 1 ienad = 1 irrad = 1 ien0 = 1 i = 0 pc contents saved ccr contents saved i 1 branch to interrupt handling routine no no no no no no no no no yes nmi no yes yes yes yes yes yes yes yes yes [legend] pc: ccr: i: program counter condition code register i bit of ccr figure 3.3 flow up to interrupt acceptance
section 3 exception handling rev. 3.00 may 15, 2007 page 56 of 516 rej09b0152-0300 3.6.1 interrupt exception handling sequence figure 3.4 shows the interrupt exception handlin g sequence. the example shown is for the case where the program area and stack area ar e in a 16-bit and 2-state access space. stack instruction prefetch interrupt level determination wait for end of instruction (9) (11) (7) (5) (6) (8) (10) (12) (3) (4) (1) (2) internal processing interrupt accepted internal processing instruction prefetch of interrupt handling routine vector fetch high (1): (2)(4): (3): (5): (7): (6)(8): instruction prefetch address (not executed. this is the contents of the saved pc and the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp-2 sp-4 saved pc and saved ccr (9): (10): (11): (12): vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((11) = (10)) first instruction of interrupt handling rou internal address bus interrupt request signal internal read signal internal write signal internal data bus figure 3.4 interrupt ex ception handling sequence
section 3 exception handling rev. 3.00 may 15, 2007 page 57 of 516 rej09b0152-0300 3.7 stack status after exception handling figures 3.5 shows the stack after completion of interrupt exception handling. pc and ccr saved to stack sp (r7) sp ? 1 sp ? 2 sp ? 3 sp ? 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling [legend] pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr * pch pcl 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word length, starting from an even-numbered address. * ignored when returning from the interrupt handling routine. figure 3.5 stack status after exception handling 3.7.1 interrupt response time table 3.4 shows the number of wa it states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.4 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 23 15 to 37 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * excluding eepmov instruction.
section 3 exception handling rev. 3.00 may 15, 2007 page 58 of 516 rej09b0152-0300 3.8 usage notes 3.8.1 notes on stack area use when word data is accessed in this lsi, the least significant bit of the address is regarded as 0. access to the stack always takes place in word si ze, so the stack pointer (sp: r7) should never indicate an odd address. to save register values, use push.w rn (mov.w rn, @?sp) or push.l ern (mov.l ern, @?sp). to restore register values, use pop.w rn (mov.w @sp+, rn) or pop.l ern (mov.l @sp+, ern). setting an odd address in sp may cause a program to crash. an example is shown in figure 3.6. pc pc r1l pc sp sp sp h'fefc h'fefd h'feff h l l mov. b r1l, @-r7 sp set to h'feff stack accessed beyond sp bsr instruction contents of pc are lost h [legend] pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer figure 3.6 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when an rte instruction is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, th e even address contents ar e restored to ccr while the odd address contents are ignored.
section 3 exception handling rev. 3.00 may 15, 2007 page 59 of 516 rej09b0152-0300 3.8.2 notes on switching functions of external interrupt pins when pfcr and pmrb are rewritten to switch the functions of external interrupt pins and when the value of the ecpwme bit in aegsr is re written to switch between selection and non- selection of irqaec, the following points should be observed. when a pin function is switched by rewriting pfcr or pmrb that controls an external interrupt pin (irqaec, irq1 , or irq0 ), the interrupt request flag is set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching the pin function. when the va lue of the ecpwme bit in aegsr that sets selection or non-selection of irqaec is rewritten, th e interrupt request flag may be set to 1, even if a valid edge has not arrived on the selected irqaec or iecpwm (pwm output for the aec). therefore, be sure to clear th e interrupt request flag to 0 after switching the pin function. figure 3.7 shows the procedure for setting a bit in pfcr and pmrb and clearing the interrupt request flag. this procedure also applies to aegsr setting. when switching a pin function, mask the interrupt before setting the bit in pfcr and pmrb (or aegsr). after accessing pfcr and pmrb (or aegsr) , execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag to 0 is executed immediately after pfcr and pmrb (or aegsr) access without executing an instruction, the flag will not be cleared. an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level. however, the procedure in figure 3.7 is recommended because iecpwm is an internal sign al and determining its value is complicated. i bit in ccr 1 set pfcr and pmrb (or aegsr) bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in the interrupt enable register 1.) after setting pfcr and pmrb (or aegsr) bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 i bit in ccr 0 figure 3.7 pfcr and pmrb (or aegsr) setting and interrupt request fl ag clearing procedure
section 3 exception handling rev. 3.00 may 15, 2007 page 60 of 516 rej09b0152-0300 3.8.3 method for clearing interrupt request flags use the recommended method given below when clearing the flags in interrupt request registers (irr1 and irr2). ? recommended method use a single instruction to clear flags. the bit manipulation instruction and byte-size data transfer instruction can be used. two examples of program code for clearing irri1 (bit 1 in irr1) are given below. example 1: bclr #1, @irr1:8 example 2: mov.b r1l, @irr1:8 (set the value of r1l to b'11111101) ? example of a malfunction when flags are cleared with mu ltiple instructions, other fl ags might be cleared during execution of the instruct ions, even though they are curr ently set, and this will cause a malfunction. here is an example in which irri0 is cleared and disabled in the pr ocess of clearing irri1 (bit 1 in irr1). mov.b @irr1:8,r1l ......... irri0 = 0 at this time and.b #b'11111101,r1l ..... here, irri0 = 1 mov.b r1l,@irr1:8 ......... irri0 is cleared to 0 in the above example, it is assumed that an irq0 interrupt is generated while the and.b instruction is executing. the irq0 interrupt is disabled because, alth ough the original objective is clearing irri1, irri0 is also cleared. 3.8.4 conflict between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. when an interrupt source flag is cleared to 0, the interrupt concerned will be ignored.
section 3 exception handling rev. 3.00 may 15, 2007 page 61 of 516 rej09b0152-0300 3.8.5 instructions th at disable interrupts the instructions that disable interrup ts are ldc, andc, orc, and xorc. when an interrupt request is generated, an interrupt is requested to the cpu. at that time, if the cpu is executing an instruction that disables interrupts, the cpu al ways executes the next instruction after the instruction execution is completed. 3.8.6 interrupts during execu tion of eepmov instruction interrupt operation differs between the eepmov. b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during transfer is not accepted until the transfer is completed. with the eepmov.w instruction, even if an interrupt request other than the nmi is issued during transfer, the interrupt is not accepted until the transf er is completed. if the nmi interrupt request is issued, nmi exception handling starts at a break in the transfer cy cle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an nmi interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 3.8.7 ienr clearing when an interrupt request is disabled by clearing the interrupt enable register or when the interrupt flag register is cleared, the inte rrupt request should be masked (i bit = 1). if the above operation is executed while the i bit is 0 and conflict between the instruction execution and the interrupt request generation occurs, exception handling, which corresponds to the interrupt request generated after instruction execution of the ab ove operation is completed, is executed.
section 3 exception handling rev. 3.00 may 15, 2007 page 62 of 516 rej09b0152-0300
section 4 clock pulse generators cpg0200a_000020020200 rev. 3.00 may 15, 2007 page 63 of 516 rej09b0152-0300 section 4 clock pulse generators the clock pulse generator is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator, system clock divider, and on-chip oscillator. the subclock pulse generator consists of a subclock oscillator, on-chip oscillator clock divider, and subclock divider. figure 4.1 shows a block diagram of the clock pulse generators. system clock oscillator on-chip oscillator osccr subclock oscillator subclock divider system clock divider on-chip oscillator clock divider prescaler s (13 bits) osc 1 e7_2 osc 2 x 1 x 2 system clock pulse generator subclock pulse generator [legend] osccr: oscillator control register osc (f osc ) osc (f osc ) w (f w ) w (f w ) w /2 w /4 sub /2 to /8192 w w /4 w /2 w /8 osc /8 osc osc /16 osc /32 osc /64 prescaler w (8 bits) w /8 to w /1024 rosc/32 rosc (f r osc ) rosc figure 4.1 block diagram of clock pulse generators the reference clock signals that drive the cpu and on-chip peripheral modules are and sub . the system clock is divided by prescaler s to become a clock signal from /8192 to /2. w /4, which is 1/4th of the watch clock w , is divided by prescaler w to become a clock signal from w /1024 to w /8. both the system clock and s ubclock signals are provided to the on-chip peripheral modules.
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 64 of 516 rej09b0152-0300 4.1 register description ? oscillator control register (osccr) 4.1.1 oscillator control register (osccr) osccr controls the subclock oscillator, on-chip feedback resistance, and on-chip oscillator. bit bit name initial value r/w description 7 substp 0 r/w subclock oscillator control controls start and stop of the subclock oscillator. when the subclock is not used, set this bit to 1. 0: subclock oscillator operates 1: subclock oscillator stops 6 rfcut 0 r/w on-chip feedback resistance control selects whether the on-chip feedback resistance in the system clock oscillator is us ed when an external clock is input or when the on-chip oscillator is used. after setting this bit in the state in which an external clock is input or the on-chip oscillator is used, temporarily transit to standby mode, watch mode, or subactive mode. the setting of whether the feedback resistance in the system clock oscillator is used or not takes effect when standby mode, watch mode, or subactive mode is entered. 0: on-chip feedback resistance in system clock oscillator is used 1: on-chip feedback resistance in system clock oscillator is not used 5 subsel 0 r/w subclock select selects by which oscillator the subclock pulse generator operates. 0: subclock oscillator operates 1: on-chip oscillator operates note: the subsel bit setting can be changed only when the subclock is not being used.
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 65 of 518 rej09b0152-0300 bit bit name initial value r/w description 4, 3 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 2 ? 0 ? reserved the write value should always be 0. 1 oscf ? * r osc flag indicates by which oscillator the system clock pulse generator operates. 0: system clock oscillator operates 1: on-chip oscillator operates (system clock oscillator is halted) 0 ? 0 ? reserved the write value should always be 0. note: * the value depends on the state of t he e7_2 pin. refer to table 4.1.
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 66 of 516 rej09b0152-0300 4.2 system clock oscillator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. either the system clock oscillator or on-chip oscillator can be selected, as shown in figure 4.1. for the selecting method, see section 4.2.4, on-chip oscillator selection method. 4.2.1 connecting crystal resonator figure 4.2 shows a typical method of connecting a crystal resonator. an at-cut parallel-resonance crystal resonator should be used. for notes on connecting, refer to section 4.5.2, notes on board design. c 1 c 2 osc1 osc2 frequency manufacturer 4.194304 mhz nihon dempa kogyo co.,ltd. c1, c2 recommendation value product type nr-18 12 pf 20% figure 4.2 typical connect ion to crystal resonator 4.2.2 connecting ceramic resonator figure 4.3 shows a typical method of connecting a ceramic resonator. for notes on connecting, refer to section 4.5.2, notes on board design. osc1 osc2 c 1 c 2 frequency manufacturer 4.19 mhz murata manufacturing co., ltd. c1, c2 recommendation value 15 pf (on-chip) 47 pf (on-chip) figure 4.3 typical connect ion to cerami c resonator
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 67 of 518 rej09b0152-0300 4.2.3 external clock input method connect an external clock signal to pin osc1, and leave pin osc2 open. figure 4.4 shows a typical connection. the duty cycle of the ex ternal clock signal must be 45 to 55%. osc1 external clock input osc2 open figure 4.4 example of external clock input 4.2.4 on-chip oscillator selection method the on-chip oscillator is selected by the e7_2 pin input level during a reset. the methods for selecting the system clock oscillator and on-chip os cillator are shown in table 4.1. the input level on the e7_2 pin during a reset is pulled up or down using a resistor according to the selected oscillator, and fixed on exit from the reset state. when the on-chip oscillator is selected, a resonator no longer needs to be connected to the osc1 and osc2 pins. in such a case, fix the osc1 pin to gnd or leave it open , and leave the osc2 pin open. notes: 1. when programming or erasing the flash memory, such as performing on-board programming, the system clock oscillator mu st be selected. when the on-chip emulator is used, even though the on-chip oscillator is selected, connect a resonator or input an external clock. 2. when the on-chip debugger is connected, the value of the resistor should be high. when not connected, it is specified acc ording to the selected oscillator. table 4.1 methods for selecting system clock oscillator and on-chip oscillator e7_2 pin input level (during reset) oscillator in system clock pulse generator oscf 0 on-chip oscillator 1 1 system clock oscillator 0
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 68 of 516 rej09b0152-0300 4.3 subclock oscillator a subclock can be provided by connecting a crystal resonator or inputting an external clock. either the subclock oscillator or on-chip oscillator can be selected, as shown in figure 4.1. for the selecting method, see section 4.3.4, on-chip oscillator selection method. 4.3.1 connecting 32.768-khz/38.4-khz crystal resonator figure 4.5 shows an example of connecting a 32.768-khz or 38.4-khz crystal resonator. notes described in section 4.5.2, notes on board design also apply to this connection. x1 x2 c 1 c 2 note: consult with the crystal resonator manufacturer to determine the parameters. frequency manufacturer 32.768 khz 38.4 khz epson toyocom corporation products name c-4-type c-001r c = c = 7 pf (typ.) 1 2 equivalent series resistance epson toyocom corporation 30 k ? (max.) 35 k ? (max.) figure 4.5 typical connection to 32.768-khz/38.4-khz crystal resonator 1. when the resonator other than ones listed above is used, perform matching evaluation with the crystal resonator manufacture and connect it under the optimum condition. even when the resonator listed above or the equivalent is used, as the oscillation characteristics depend on the board specification, perform matching evaluation on the mounting board. 2. perform matching evaluation in the reset state (the res pin is low) and on exit from the reset state (the res pin is driven from low to high).
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 69 of 518 rej09b0152-0300 figure 4.6 shows the equivalent circuit of the crystal resonator. c s c o l s r s x1 x2 c o = 1.5 pf (typ.) r s = 14 k ? (typ.) f w = 32.768 khz/38.4 khz figure 4.6 equivalent circuit of 32.768-khz/38.4-khz crystal resonator 4.3.2 pin connection when not using subclock when the subclock is not used, connect the x1 pin to gnd and leave the x2 pin open, as shown in figure 4.7. x1 x2 gnd open figure 4.7 pin connection when not using subclock
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 70 of 516 rej09b0152-0300 4.3.3 external clock input method connect the external clock to the x1 pin and leave the x2 pin open, as shown in figure 4.8. x1 external clock input x2 open figure 4.8 pin connection wh en inputting ex ternal clock frequency watch clock ( w ) duty 45% to 55% 4.3.4 on-chip oscillator selection method the on-chip oscillator is selected by the subsel bit in osccr. when the on-chip oscillator is selected, a resonator no longer needs to be connected to the x1 and x2 pins. in such a case, fix the x1 pin at gnd.
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 71 of 518 rej09b0152-0300 4.4 prescalers this lsi is equipped with two on-chip prescale rs (prescaler s and prescaler w), which have different input clocks. prescaler s is a 13-bit counter using the system clock ( ) as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is an 8-bit counter using w /4, which is 1/4th of the watch clock w , as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. 4.4.1 prescaler s prescaler s is a 13-bit counter using the system clock ( ) as its input clock. a divided output is used as an internal clock of an on-chip peripheral module. prescaler s is in itialized to h'0000 at a reset, and starts counting up on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, prescaler s stops and is initialized to h'0000. the cpu cannot read from or write to prescaler s. the output from prescaler s is shared by the on-chip peripheral modules. in active (medium- speed) mode and sleep (medium-speed) mode, the cl ock input to prescaler s is determined by the division ratio designated by the ma1 and ma0 bits in syscr1. 4.4.2 prescaler w prescaler w is an 8-bit counter using w /4, which is 1/4th of the watch clock w , as its input clock. a divided output is used as an internal clock of an on-chip peripheral module. prescaler w is initialized to h'00 at a reset, and starts counting up on exit from the reset state. in standby mode, prescaler w is halted. even when transiting to watch mode, subactive mode, and subsleep mode, prescaler w continues operation.
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 72 of 516 rej09b0152-0300 4.5 usage notes 4.5.1 note on resonators and resonator circuits resonator characteristics are closely related to board design. therefore, resonators should be assigned after being carefully evaluated by the user in the masked rom version and flash memory version, with referring to the examples shown in this section. resonator circuit constants will differ depending on a resonator, stray capacitance in its mounting circuit, and other factors. suitable constants should be determined in cons ultation with the resonator manufacturer. design the circuit so that the oscillator pin is never applied voltages exceeding its maximum rating. (vss) vcc osc1 vss osc2 res x2 x1 avcc figure 4.9 example of crystal and ceramic resonator assignment
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 73 of 518 rej09b0152-0300 figure 4.10 (1) shows an example measuring circuit with the negative resistance recommended by the resonator manufacturer. note that if the nega tive resistance of the circ uit is less than that recommended by the resonator manufacturer, it may be difficult to start the main oscillator. if it is determined that oscillation does not occur because the negative resistance is lower than the level recommended by the resonator manufacturer, the circuit must be modified as shown in figure 4.10 (2) through (4). which of the modification suggestions to use and the capacitor capacitance should be decided based upon evaluation results such as the negative resistance and the frequency deviation. (1) negative resistance measuring circuit (2) oscillator circuit modification suggestion 1 (3) oscillator circuit modification suggestion 2 (4) oscillator circuit modification suggestion 3 c3 osc1 osc2 c1 c2 negative resistance, addition of -r osc1 osc2 c1 c2 modification point modification point modification point osc1 osc2 c1 c2 osc1 osc2 c1 c2 figure 4.10 negative resistance measurem ent and circuit modification suggestions
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 74 of 516 rej09b0152-0300 4.5.2 notes on board design when using a crystal resonator (ceramic resonator) , place the resonator and it s load capacitors as close as possible to the osc1 and osc2 pins. othe r signal lines should be routed away from the resonator circuit to prevent induc tion from interfering with correct oscillation (see figure 4.11). osc1 osc2 c 1 c 2 signal a signal b avoid figure 4.11 example of incorrect board design note: when a crystal resonator or ceramic reso nator is connected, consult with the crystal resonator and ceramic resonator manufacturers to determine the circuit constants because the constants differ according to the resonator, stray capacitance of the mounting circuit, and so on. 4.5.3 definition of oscillation stabilization wait time figure 4.12 shows the oscillation waveform (osc2), system clock ( ), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/mediu m-speed) mode, with an resonator connected to the system clock oscillator. as shown in figure 4.12, when a transition is made to active (high-speed/medium-speed) mode, from standby mode, watch mode, or subactive mode, in which the system clock oscillator is halted, the sum of the following two times (osc illation start time and wait time) is required. (1) oscillation start time the time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the system clock starts to be generated.
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 75 of 518 rej09b0152-0300 (2) wait time after the system clock is generated, the time required for the amplitude of the oscillation waveform to increase, the oscillation frequency to stabilize, and the cpu an d peripheral functions to begin operating. oscillation waveform (osc2) system clock ( ) oscillation stabilization wait time standby mode, watch mode, or subactive mode oscillation start time active (high-speed) mode or active (medium-speed) mode wait time interrupt accepted operating mode figure 4.12 oscillation stabilization wait time as the oscillation stabilization wait time required is the same as the oscillation stabilization time (t rc ) at power-on, specified in the ac characteristics, set the sts2 to sts0 bits in syscr1 to specify the time longer than the oscillation stabilization time (t rc ). therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/mediu m-speed) mode, with an resonator connected to the system clock oscillator, careful evaluation must be carried out on the mounting circuit before deciding the oscillation stabilization wait time. for the wait time, secure the time requir ed for the amplitude of the oscillation waveform to increase and the oscillation frequency to stabilize. in addition, since the oscillation start time differs according to mounti ng circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the resonator manufacturer.
section 4 clock pulse generators rev. 3.00 may 15, 2007 page 76 of 516 rej09b0152-0300 4.5.4 note on subclock stop state to stop the subclock, a state transition should not be made except to mode in which the system clock operates. if the state transition is made to other mode, it may result in incorrect operation. 4.5.5 note on the oscillation stabilization of resonators when a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. depending on the individual resonator characteristics, the oscillation waveform amplitude may not be suffic iently large immediately after the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. in this state, the oscillation waveform may be disrupted, leading to an unstable system clock and incorrect operation of the microcomputer. if incorrect operation occurs, change the setting of the standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in the system control register 1 (syscr1)) to give a longer wait time. for example, if incorrect oper ation occurs with a wait time setting of 512 states, check the operation with a wait time setting of 1,024 states or more. if the same kind of incorrect operation occurs af ter a reset as after a state transition, hold the res pin low for a longer period. 4.5.6 note on using power-on reset the power-on reset circuit in this lsi adjusts the reset clear time by th e capacitor capacitance, which is externally connected to the res pin. the external capac itor capacitance should be adjusted to secure the oscillation stabilization ti me before reset clearing. for details, refer to section 19, power-on reset circuit. 4.5.7 note on using on-chip emulator when the on-chip emulator is used, system clock accuracy is necessary for flash memory programming/erasing. the frequency of the on-chip oscillator differs depending on the voltage and temperature conditions. therefore, when usin g the on-chip emulator, the resonator must be connected to the osc1 and osc2 pi ns or an external clock must be supplied. in this case, the on- chip oscillator is used for user program executio n, and the system clock is used for flash memory programming/erasing. this control is handled when the e7_2 pin is fixed to high level during a reset by the on-chip emulator.
section 5 power-down modes rev. 3.00 may 15, 2007 page 77 of 516 rej09b0152-0300 section 5 power-down modes this lsi has eight modes of operation after a reset. these include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. the module standby function reduces power consumption by selectively halting on-chip module functions. ? active (medium-speed) mode the cpu and all on-chip peripheral modules are operable on the system clock. the system clock frequency can be selected from osc /8, osc /16, osc /32, and osc /64. ? subactive mode the cpu and all on-chip peripheral modules are operable on the subclock. the subclock frequency can be selected from w , w /2, w /4, and w /8. ? sleep (high-speed) mode the cpu halts. on-chip peripheral module s are operable on the system clock. ? sleep (medium-speed) mode the cpu halts. on-chip peripher al modules are operable on th e system clock. the system clock frequency can be selected from osc /8, osc /16, osc /32, and osc /64. ? subsleep mode the cpu halts. the on-chip peripheral modules are operable on the subclock. the subclock frequency can be selected from w , w /2, w /4, and w /8. ? watch mode the cpu halts. the on-chip peripheral modules are operable on the subclock. ? standby mode the cpu and all on-chip peripheral modules halt. ? module standby function independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. note: in this manual, active (high-speed) mode and active (medium-speed) mode are collectively called active mode.
section 5 power-down modes rev. 3.00 may 15, 2007 page 78 of 516 rej09b0152-0300 5.1 register descriptions the registers related to power-down modes are as follows. ? system control register 1 (syscr1) ? system control register 2 (syscr2) ? clock halt registers 1 and 2 (ckstpr1 and ckstpr2) 5.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby selects the mode to transit after the execution of the sleep instruction. 0: a transition is made to sleep mode or subsleep mode. 1: a transition is made to standby mode or watch mode. for details, see table 5.2. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or watch mode to active mode or sleep mode due to an interrupt. the designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. the relationship between the specified value and the nu mber of wait states is shown in table 5.1. when an external clock is to be used, the minimum value (sts2 = 1, sts1 = 1, and sts0 = 1) is recommended. when the on-chip oscillator is to be used, the minimum value (sts2 = 1, sts1 = 1, and sts0 = 1) is recommended. if a setting other than the recommended value is made, operation may start before the end of the waiting time.
section 5 power-down modes rev. 3.00 may 15, 2007 page 79 of 516 rej09b0152-0300 bit bit name initial value r/w description 3 lson 0 r/w selects the system clock ( ) or subclock ( sub ) as the cpu operating clock when watch mode is cleared. 0: the cpu operates on the system clock ( ) 1: the cpu operates on the subclock ( sub ) 2 tma3 0 r/w selects the mode to which the transition is made after the sleep instruction is executed with bits ssby and lson in syscr1 and bits dton and mson in syscr2. for details, see table 5.2. 1 0 ma1 ma0 1 1 r/w r/w active mode clock select 1 and 0 select the operating clock frequency in active (medium- speed) mode and sleep (medium-speed) mode. the ma1 and ma0 bits should be written to in active (high- speed) mode or subactive mode. 00: osc /8 01: osc /16 10: osc /32 11: osc /64 table 5.1 operating frequency and waiting time bit operating frequency and waiting time sts2 sts1 sts0 waiting states 10 mhz 8 mhz 6 mhz 5 mhz 4.194mhz 3 mhz 2 mhz 0 0 0 8,192 states 819.2 1,024.0 * 1 1,365.3 * 1 1,638.4 1953.3 2,730.7 4,096.0 1 16,384 states 1,638.4 2,048.0 2,730.7 3,276.8 3906.5 5,461.3 * 1 8,192.0 * 1 1 0 1,024 states 102.4 128.0 170.7 204.8 244.2 341.3 512.0 1 2,048 states 204.8 256.0 341.3 409.6 488.3 682.7 1,024.0 1 0 0 4,096 states 409.6 512.0 682.7 * 1 819.2 * 1 976.6 1,365.3 2,048.0 1 256 states 25.6 32.0 42.7 * 2 51.2 * 2 61.0 85.3 * 2 128.0 * 2 1 0 512 states 51.2 64.0 * 2 85.3 * 2 102.4 122.1 170.7 256.0 1 16 states 1.6 2. 0 2.7 3.2 3.8 5.3 8.0 notes: time unit is s. : recommended value when crystal resonator is used (vcc = 2.7 v to 3.6 v) : recommended value when ceramic resonator is used (vcc = 2.2 v to 3.6 v) 1. reference value when crystal resonator is used 2. reference value when ceramic resonator is used
section 5 power-down modes rev. 3.00 may 15, 2007 page 80 of 516 rej09b0152-0300 5.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 4 nesel 1 r/w noise eliminat ion sampling frequency select the subclock pulse generat or generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of osc when w is sampled. when a system clock is used, clear this bit to 0.when the on- chip oscillator is select ed, set this bit to 1. 0: sampling rate is osc /16. 1: sampling rate is osc /4. 3 dton 0 r/w direct transfer on flag selects the mode to which the transition is made after the sleep instruction is executed with bits ssby, tma3, and lson in syscr1 and bit mson in syscr2. for details, see table 5.2. 2 mson 0 r/w medium speed on flag after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. 0: operation in active (high-speed) mode 1: operation in active (medium-speed) mode 1 0 sa1 sa0 0 0 r/w r/w subactive mode clock select 1 and 0 select the operating clock frequency in subactive and subsleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 00: w /8 01: w /4 10: w /2 11: w
section 5 power-down modes rev. 3.00 may 15, 2007 page 81 of 516 rej09b0152-0300 5.1.3 clock halt registers 1 and 2 (ckstpr1 and ckstpr2) ckstpr1 and ckstpr2 allow the on-chip peripher al modules to enter the standby state in module units. ? ckstpr1 bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 6 s3ckstp 0 r/w sci3 module standby * 1 sci3 enters standby mode when this bit is cleared to 0. 5 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 4 adckstp 0 r/w a/d converter module standby a/d converter enters standby mode when this bit is cleared to 0. 3 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 2 tb1ckstp 0 r/w timer b1 module standby timer b1 enters standby mode when this bit is cleared to 0. 1 fromckstp * 2 1 r/w flash memory module standby flash memory enters standby mode when this bit is cleared to 0. 0 rtcckstp 1 r/w rtc module standby rtc enters standby mode when this bit is cleared to 0.
section 5 power-down modes rev. 3.00 may 15, 2007 page 82 of 516 rej09b0152-0300 ? ckstpr2 bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 6 twckstp 0 r/w timer w module standby timer w enters standby mode when this bit is cleared to 0. 5 iicckstp 0 r/w iic2 module standby the iic2 enters standby mode when this bit is cleared to 0. 4 ssuckstp 0 r/w ssu module standby the ssu enters standby mode when this bit is cleared to 0. 3 aecckstp 0 r/w asynchronous event counter module standby the asynchronous event counter enters standby mode when this bit is cleared to 0. 2 wdckstp 1 r/w * 3 watchdog timer module standby the watchdog timer enters standby mode when this bit is cleared to 0. 1 compckstp 0 r/w comparator module standby the comparators enter standby mode when this bit is cleared to 0. 0 ? 0 ? reserved this bit is always read as 0 and cannot be modified. notes: 1. when the sci3 module standby is set, a ll registers in the sci3 enter the reset state. 2. when using the on-chip emulator, set this bit to 1. 3. this bit is valid when the wdon bit in tcsr w is 0. if this bit is cleared to 0 while the wdon bit is set to 1 (while the watchdog time r is operating), this bit is cleared to 0. however, the watchdog timer does not en ter module standby mode and continues operating. when the wdon bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode.
section 5 power-down modes rev. 3.00 may 15, 2007 page 83 of 516 rej09b0152-0300 5.2 mode transitions and states of lsi figure 5.1 shows the possible transitions among these operating modes. a transition is made from the program execution state to the program halt state of the program by executing a sleep instruction. interrupts allow for returning from the program halt state to the program execution state of the program. a direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. the operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. res input enables transitions from a mode to the reset state. table 5.2 shows the transition co nditions of each mode af ter the sleep instruction is executed and a mode to return by an interrupt. table 5.3 shows the internal states of the lsi in each mode.
section 5 power-down modes rev. 3.00 may 15, 2007 page 84 of 516 rej09b0152-0300 reset state standby mode watch mode active (high-speed mode) sleep (high-speed) mode active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode power-down modes : transition is made after exception handling is executed. program halt state program execution state program halt state note: a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that interrupt handling is accepted. sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruc tion sleep instruc tion slee p inst ruction b a d d 4 3 3 1 1 2 4 f g a b e e e 1 j i1 i2 c h lson mson ssby tma3 dton a b c d e f g h i1 i2 j 0 0 1 0 x 0 0 0 1 1 0 0 1 x x x 0 1 1 x 1 0 0 0 0 1 1 0 0 1 1 1 1 x x 1 0 1 x x 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 interrupt sources nmi, irq0, irq1, irqaec, comp, rtc, wdt, aec, and timer b1 all interrupts except iic2 all interrupts nmi, irq0, irq1, irqaec, comp, wdt, and aec x: don't care mode transition conditions (1) mode transition conditions (2) sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction 1 2 3 4 figure 5.1 mode transition diagram
section 5 power-down modes rev. 3.00 may 15, 2007 page 85 of 516 rej09b0152-0300 table 5.2 transition mode after sleep inst ruction execution and interrupt handling lson mson ssby tma3 dton transition mode after sleep instruction execution transition mode due to interrupt 0 0 0 x 0 sleep (high-speed) mode active (high-speed) mode 0 1 0 x 0 sleep (medium-speed) mode active (medium-speed) mode 0 0 1 0 0 standby mode active (high-speed) mode 0 1 1 0 0 standby mode acti ve (medium-speed) mode 0 0 1 1 0 watch mode active (high-speed) mode 0 1 1 1 0 watch mode acti ve (medium-speed) mode 1 x 1 1 0 watch mode subactive mode 0 0 0 x 1 active (high-speed) mode (direct transition) ? 0 1 0 x 1 active (medium-speed) mode (direct transition) ? active (high- speed) mode 1 x 1 1 1 subactive mode (direct transition) ? 0 0 0 x 0 sleep (high-speed) mode active (high-speed) mode 0 1 0 x 0 sleep (medium-speed) mode active (medium-speed) mode 0 0 1 0 0 standby mode active (high-speed) mode 0 1 1 0 0 standby mode acti ve (medium-speed) mode 0 0 1 1 0 watch mode active (high-speed) mode 0 1 1 1 0 watch mode acti ve (medium-speed) mode 1 1 1 1 0 watch mode subactive mode 0 0 0 x 1 active (high-speed) mode (direct transition) ? 0 1 0 x 1 active (medium-speed) mode (direct transition) ? active (medium- speed) mode 1 1 1 1 1 subactive mode (direct transition) ? 1 x 0 1 0 subsleep mode subactive mode 0 0 1 1 0 watch mode active (high-speed) mode 0 1 1 1 0 watch mode acti ve (medium-speed) mode 1 x 1 1 0 watch mode subactive mode 0 0 1 1 1 active (high-speed) mode (direct transition) ? 0 1 1 1 1 active (medium-speed) mode (direct transition) ? subactive mode 1 x 1 1 1 subactive mode (direct transition) ? [legend] x: don?t care.
section 5 power-down modes rev. 3.00 may 15, 2007 page 86 of 516 rej09b0152-0300 table 5.3 internal state in each operating mode active mode sleep mode function high- speed medium- speed high- speed medium- speed watch mode subactive mode subsleep mode standby mode system clock oscillator functi ons functions f unctions functions halt ed halted halted halted subclock oscillator functions/ halted functions/ halted functions/ halted functions/ halted functions functions f unctions functions/ halted instructions halted ha lted halted halted halted ram registers retained cpu i/o functions functions retained retained retained functions retained retained * 1 nmi irq0 irq1 external interrupts irqaec functions functions functions functions functions functions functions functions timer b1 functions/ retained * 2 functions/ retained * 2 functions/ retained * 2 retained timer w retained functions/ retained * 3 functions/ retained * 3 retained wdt functions/ retained * 5 functions/ retained * 5 functions/ retained * 5 functions/ retained * 4 rtc functions/ retained * 6 functions/ retained * 6 functions/ retained * 6 retained asynchro- nous event counter functions functions functions functions sci3/ irda reset functions/ retained * 7 functions/ retained * 7 reset iic2 retained retained retained retained ssu retained functions/ retained * 8 functions/ retained * 8 retained a/d retained functions/ retained * 9 functions/ retained * 9 retained peripheral modules comparator functions functions functions functions functions functions functions functions notes: 1. register contents are retai ned. output is the high-impedance state. 2. functions if w /256 or w /1024 is selected as an internal clock. halted and retained otherwise.
section 5 power-down modes rev. 3.00 may 15, 2007 page 87 of 516 rej09b0152-0300 3. functions if w , w /4, or w /16 is selected as an internal clock. halted and retained otherwise. 4. functions if the on-chip oscillator is selected. halted and retained otherwise. 5. functions if the on-chip oscillator is selected or if w /16 or w /256 is selected as an internal clock. halted and retained otherwise. 6. functions if the 32.768-khz rtc is select ed as an internal clock. halted and retained otherwise. 7. functions if w is selected as an internal clock. halted and retained otherwise. 8. functions if sub /2 is selected as an internal clock. halted and retained otherwise. 9. functions if w /2 is selected as an internal clock. halted and retained otherwise. 5.2.1 sleep mode in sleep mode, cpu operation is halted but the sy stem clock oscillator, subclock oscillator, and on-chip peripheral modules function. in sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the ma1 and ma0 bits in syscr1. cpu register contents are retained. sleep mode is cleared by an inte rrupt. when an interrupt is requ ested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enab le bit. after sleep mode is cleared, a transition is made from sleep (high-speed) mode to activ e (high-speed) mode or fr om sleep (medium-speed) mode to active (medium-speed) mode. when the res pin goes low, the cpu goes into the rese t state and sleep mode is cleared. since an interrupt request signal is synchronous with the system clock, the maximum time of 2/ (s) may be delayed from the point at which an interrupt request signal occurs until the interrupt exception handling is started.
section 5 power-down modes rev. 3.00 may 15, 2007 page 88 of 516 rej09b0152-0300 5.2.2 standby mode in standby mode, the system clock oscillator stops, and the cpu and on-chip peripheral modules stop functioning except for the wdt, asynchronous event counter, and comparators. however, as long as the rated voltage is supplied, the conten ts of cpu registers and some on-chip peripheral module registers are retained. on-chip ram contents wi ll be retained as long as the voltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an in terrupt. when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, standby mode is cleared and interrupt exception handling starts. after standby mode is cleared, a transition is made to active (high-speed) or activ e (medium-speed) mode according to the mson bit in syscr2. standby mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enable bit. when a reset source is generated in standby mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes and the t rel period has elapsed. the cpu starts reset exception handling when the res pin is driven high. 5.2.3 watch mode in watch mode, the system clock oscillator and cpu operation stop, and on-chip peripheral modules stop functioning except for the wdt, rtc, timer b1, asynchronous event counter, and comparators. however, as long as the rated voltage is supplied, the contents of cpu registers, some on-chip peripheral module registers, and on-chip ram are retained. the i/o ports retain their state before the transition. watch mode is cleared by an inte rrupt. when an interrupt is requested, watch mode is cleared and interrupt exception handling starts. when watch mode is cleared by an interrupt, a transition is made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on the settings of the lson bit in syscr1 and the mson bit in syscr2. when the transition is made to active mode, after the time set in bits sts2 to sts0 in syscr1 has elapsed, interrupt exception handling starts. watch mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enable register. when a reset source is generated in watch mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes and the t rel period has elapsed. the cpu starts reset exception handling when the res pin is driven high.
section 5 power-down modes rev. 3.00 may 15, 2007 page 89 of 516 rej09b0152-0300 5.2.4 subsleep mode in subsleep mode, the cpu operation stops but on-chip peripheral modules function except for the iic2. as long as a required voltage is applied, the contents of cpu registers, the on-chip ram, and some registers of the on-chip peripheral modul es are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an in terrupt. when an interrupt is requ ested, subsleep mode is cleared and interrupt exception handling starts. after subsl eep mode is cleared, a transition is made to subactive mode. subsleep mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enable register. when a reset source is generated in subsleep mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes and the t rel period has elapsed. the cpu starts reset exception handling when the res pin is driven high. 5.2.5 subactive mode in subactive mode, the system clock oscillator stops but on-chip peripheral modules function except for the iic2. as long as a re quired voltage is app lied, the contents of some registers of the on-chip peripheral modules are retained. subactive mode is cleared by th e sleep instruction. when subact ive mode is cleared, a transition to subsleep mode, active mode, or watch mode is made, depending on the combination of bits ssby, lson, and tma3 in syscr1 an d bits mson and dton in syscr2. when a reset source is generated in subactive mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes and the t rel period has elapsed. the cpu starts reset exception handling when the res pin is driven high. the operating frequency of subactive mode is selected from w (watch clock), w /2, w /4, and w /8 by the sa1 and sa0 bits in syscr2. after the sleep instruction is executed, the operating frequency changes to the frequency which is set before the execution.
section 5 power-down modes rev. 3.00 may 15, 2007 page 90 of 516 rej09b0152-0300 5.2.6 active (medium-speed) mode in active (medium-speed) mode, the clock set by th e ma1 and ma0 bits in syscr1 is used as the system clock, and the cpu and on-chip peripheral modules function. active (medium-speed) mode is cl eared by the sleep instructio n. when active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits ssby, lson, and tma3 in syscr1, a transition to watch mode is made depending on the combination of bits ssby and tma3 in syscr1, or a transition to sleep mode is made depending on the combination of bits ssby and lson in syscr1. moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. when the res pin goes low, the cpu goes into the reset state and active (medium-sleep) mode is cleared.
section 5 power-down modes rev. 3.00 may 15, 2007 page 91 of 516 rej09b0152-0300 5.3 direct transition the cpu can execute programs in two modes: activ e and subactive modes. a direct transition is made between these two modes without stopping program execution. a direct transition can also be made when the operating clock is changed in active and subactive modes. the transition is made via the sleep or watch mode, by setting th e dton bit in syscr2 to 1 to execute a sleep instruction. after the mode transition, direct transition interrupt exception handling starts. note that if a direct transition is attempted while the i bit in ccr is 1, the transition is made to the sleep or watch mode, though not returning from the mode. 5.3.1 direct transition from active (high-sp eed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0 and the mson and dton bits in syscr2 are set to 1, a transition is made to active (medium-speed) mode via sleep mode. the time from the start of sleep instruction execu tion to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). direct transition time = {(number of sleep inst ruction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition)????(1) example: when osc/8 is selected as the cpu op erating clock after the transition direct transition time = (2 + 1) 1tosc + 14 8tosc = 115tosc for the legend of symbols used above, refer to section 21, electrical characteristics.
section 5 power-down modes rev. 3.00 may 15, 2007 page 92 of 516 rej09b0152-0300 5.3.2 direct transition from active (h igh-speed) mode to subactive mode when a sleep instruction is executed in activ e (high-speed) mode wh ile the ssby, tma3, and lson bits in syscr1 are set to 1 and the dton bi t in syscr2 is set to 1, a transition is made to subactive mode via watch mode. the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). direct transition time = {(number of sleep inst ruction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt exception handling execution states) (tsubcyc after transition)?..?(2) example: when w/8 is selected as the subactive operating clock after the transition direct transition time = (2 + 1) 1tosc + 14 8tw = 3tosc + 112tw for the legend of symbols used above, refer to section 21, electrical characteristics. 5.3.3 direct transition from active (mediu m-speed) mode to acti ve (high-speed) mode when a sleep instruction is executed in ac tive (medium-speed) mode while the ssby and lson bits in syscr1 ar e cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is ma de to active (high-speed) mode via sleep mode. the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). direct transition time = {(number of sleep inst ruction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition)???..(3) example: when osc/8 is selected as the cpu oper ating clock before the transition direct transition time = (2 + 1) 8tosc + 14 1tosc = 38tosc for the legend of symbols used above, refe r to section 21, electrical characteristics.
section 5 power-down modes rev. 3.00 may 15, 2007 page 93 of 516 rej09b0152-0300 5.3.4 direct transition from active (m edium-speed) mode to subactive mode when a sleep instruction is executed in acti ve (medium-speed) mode while the ssby, lson, and tma3 bits in syscr1 are set to 1 and the dton bit in syscr2 is set to 1, a transition is made to subactive mode via watch mode. the time from the start of sleep instruction execu tion to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). direct transition time = {(number of sleep instru ction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt exception handling execution states) (tsubcyc after transition)??(4) example: when osc/8 and w/8 are selected as the cpu operating clock before and after the transition, respectively direct transition time = (2 + 1) 8tosc + 14 8tw = 24tosc + 112tw for the legend of symbols used above, refer to section 21, electrical characteristics. 5.3.5 direct transition fr om subactive mode to ac tive (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby and tma3 bits in syscr1 are set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made directly to active (high- speed) mode via watch mode after the waiting time set in bits sts2 to sts0 in syscr1 has elapsed. the time from the start of sleep instruction execu tion to the end of interrupt exception handling (the direct transition time) is calculated by equation (5). direct transition time = {(number of sleep instru ction execution states) + (number of internal processing states)} (tsubcyc before transition) + (wait time set in bits sts2 to sts0) + (number of interrupt exception handling execution states) (tcyc after trans ition)????????? ??????..(5) example: when w/8 is selected as the cpu operating clock after the transition and wait time = 8192 states direct transition time = (2 + 1) 8tw + (8192 + 14) 1 tosc = 24tw + 8206tosc for the legend of symbols used above, refer to section 21, electrical characteristics.
section 5 power-down modes rev. 3.00 may 15, 2007 page 94 of 516 rej09b0152-0300 5.3.6 direct transition fr om subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby and tma3 bits in syscr1 are set to 1, the lson bit in syscr1 is cleared to 0, and the mson and dton bits in syscr2 are set to 1, a transition is made direc tly to active (medium-speed) mode via watch mode after the waiting time set in bits sts2 to sts0 in syscr1 has elapsed. the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (6). direct transition time = {(number of sleep inst ruction execution states) + (number of internal processing states)} (tsubcyc before transition) + (wait time set in bits sts2 to sts0) + (number of interrupt exception handling execution states) (tcyc after transition)?????????.??????..(6) example: when w/8 and osc/8 are selected as the cpu op erating clock before and after the transition, respectively, and wait time = 8192 states direct transition time = (2 + 1) 8tw + 8192 1 tosc + 14 8tosc = 24tw + 8304tosc for the legend of symbols used above, refe r to section 21, electrical characteristics.
section 5 power-down modes rev. 3.00 may 15, 2007 page 95 of 516 rej09b0152-0300 5.3.7 notes on exte rnal input signal changes before/after direct transition ? direct transition from active (high-speed) mode to subactive mode since the mode transition is performed via watc h mode, see section 5.6.2, notes on external input signal changes before/after standby mode. ? direct transition from active (mediu m-speed) mode to subactive mode since the mode transition is performed via watc h mode, see section 5.6.2, notes on external input signal changes before/after standby mode. ? direct transition from subactive mode to active (high-speed) mode since the mode transition is performed via watc h mode, see section 5.6.2, notes on external input signal changes before/after standby mode. ? direct transition from subactive mode to active (medium-speed) mode since the mode transition is performed via watc h mode, see section 5.6.2, notes on external input signal changes before/after standby mode.
section 5 power-down modes rev. 3.00 may 15, 2007 page 96 of 516 rej09b0152-0300 5.4 module standby function the module-standby function can be set to any peripheral module. in module standby mode, the clock supply to modules stops to enter the po wer-down mode. module standby mode enables each on-chip peripheral module to enter the standby st ate by clearing a bit th at corresponds to each module in ckstpr1 and ckstpr2 to 0 and cancels the mode by setting the bit to 1. (see section 5.1.3, clock halt registers 1 and 2 (ckstpr1 and ckstpr2).) 5.5 on-chip oscillator and operation mode the on-chip oscillator can be used as the clock source for the watchdog timer (wdt), subclock generation circuit ( w = r osc /32), and system clock generation circuit ( osc = r osc ). when the on-chip oscillator is used as the clock source for the watchdog timer (wdt), it operates in any modes, such as active, sleep, subactive, subsleep, watch, and standby modes. when the on-chip oscillator is used as the clock so urce for the subclock genera tion circuit, it stops in standby mode and operates in other modes. when the on-chip oscillator is used only as the clock source for the system clock generation circuit, it operates in active and sleep modes but halts the operation in subactive, subsleep, watch, and standby modes. when the on-chip oscillator is not used as the clock source for the watchdog timer (wdt), subclock generation circuit, or system clock generation circuit, it halts the operation. the on-chip oscillator operates at a reset and af ter a reset, because the watchdog timer (wdt) selects the on-chip oscillator as the clock source for the initial value.
section 5 power-down modes rev. 3.00 may 15, 2007 page 97 of 516 rej09b0152-0300 5.6 usage notes 5.6.1 standby mode transition and pin states when a sleep instruction is executed in activ e (high-speed) mode or active (medium-speed) mode while the ssby and tma3 bits in syscr1 an d the lson bit in syscr1 are cleared to 0, a transition is made to standby mode. at the sa me time, pins go to the high-impedance state (except pins for which the pull-up mos is designated as on). figure 5.2 shows the timing in this case. sleep instruction fetch internal data bus next instruction fetch port output pins high-impedance active (high-speed) mode or active (medium-speed) mode standby mode sleep instruction execution internal processing figure 5.2 standby mode transition and pin states 5.6.2 notes on external input signal changes before/after standby mode (1) when external input signal changes before/after standby mode or watch mode when an external input signal such as nmi , irq0 , irq1 , or irqaec is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock sub (referred to together in this section as the intern al clock). as the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these oper ating modes. ensure that external input signals conform to the conditions stated in (3), recommended timing of external input signals, below.
section 5 power-down modes rev. 3.00 may 15, 2007 page 98 of 516 rej09b0152-0300 (2) when external input signals cannot be captured because in ternal clock stops the case of falling edge capture is shown in figure 5.3. as shown in the case marked "capture not possi ble," when an external input signal falls immediately after a transition to active mode or su bactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc . (3) recommended timing of external input signals to ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "capture possible: case 1." external input signal capture is also possible with the timing shown in "capture possible: case 2" and "capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured. tcyc tsubcyc tcyc tsubcyc tcyc tsubcyc tcyc tsubcyc capture possible: case 1 capture possible: case 2 capture possible: case 3 capture not possible or sub operating mode active (high-speed, medium-speed) mode or subactive mode standby mode or watch mode wait for osc- illation stabilization active (high-speed, medium-speed) mode or subactive mode external input signal interrupt by different signal figure 5.3 external input signal capture when signal changes before/after standby mode or watch mode (4) input pins to which these notes apply nmi , irq0 , irq1 , irqaec, and adtrg
section 6 rom rom3560a_000120030300 rev. 3.00 may 15, 2007 page 99 of 516 rej09b0152-0300 section 6 rom the features of the 16-kbyte flash memory bu ilt into the flash memory (f-ztat) version are summarized below. ? programming/erasing methods the flash memory is programmed 128 bytes at a time. erasure is performed in single-block units. the flash memory is configured as follows: 1 kbyte 4 blocks and 12 kbytes 1 block. to erase the entire flash memory, each block must be erased in turn. ? on-board programming on-board programming/erasure can be done in boot mode, in which the boot program built into this lsi is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? automatic bit rate adjustment for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection sets software protection against fl ash memory programming/erasure. ? power-down mode operation of the power supply circuit can be partly halted in subactive mode. as a result, flash memory can be read with low power consumption. ? module standby mode use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.) however, when using the on-chip emulator debugger, set the fromckstp bit in clock halt register 1 to 1. note: the system clock oscillator must be used when programming or erasing the flash memory.
section 6 rom rev. 3.00 may 15, 2007 page 100 of 516 rej09b0152-0300 6.1 block configuration figure 6.1 shows the block configuration of flash memory. the thick lines indicate erasing a block, the narrow lines indicate programming units, and the values are addresses. the 16-kbyte flash memory is divided into 1 kbyte 4 blocks and 12 kbytes 1 block. erasure is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0482 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'08ff h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'3fff h'3f80 h'3f81 h'3f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1 kbyte erasing unit 1 kbyte erasing unit 1 kbyte erasing unit 1 kbyte erasing unit 12 kbytes erasing unit figure 6.1 flash memory block configuration
section 6 rom rev. 3.00 may 15, 2007 page 101 of 518 rej09b0152-0300 6.2 register descriptions the flash memory has th e following registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? flash memory power control register (flpwcr) ? flash memory enable register (fenr) 6.2.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory enter the programming mode, programming- verifying mode, erasing mode, or erasing-verifying mode. for details on register setting, refer to section 6.4, flash memory programming/erasure. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasure is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory enters to the erasure setup state. when it is cleared to 0, the erasure setup state is released. set this bit to 1 before setting the e bit in flmcr1 to 1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory enters to the programming setup state. when it is cleared to 0, the programming setup state is released. set this bit to 1 before setting the p bit in flmcr1 to 1.
section 6 rom rev. 3.00 may 15, 2007 page 102 of 516 rej09b0152-0300 bit bit name initial value r/w description 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory enters to erasing-verifying mode. when it is cleared to 0, erasing- verifying mode is released. 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory enters the programming-verifying mode. when it is cleared to 0, programming-verifying mode is released. 1 e 0 r/w erase when this bit is set to 1 while swe=1 and esu=1, the flash memory enters the erasing mode. when it is cleared to 0, the erasing mode is released. 0 p 0 r/w program when this bit is set to 1 while swe=1 and psu=1, the flash memory enters the programming mode. when it is cleared to 0, the programming mode is released. 6.2.2 flash memory control register 2 (flmcr2) flmcr2 is a register that indicates the state of flash memory programming/erasure. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during programming or erasing flash memory. when this bit is set to 1, flash memory enters the error-protection state. see section 6.5.3, error protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 6 rom rev. 3.00 may 15, 2007 page 103 of 518 rej09b0152-0300 6.2.3 erase block register 1 (ebr1) ebr1 specifies the erase block of flash memory. ebr1 is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved although these bits are readable/writable, only 0 should be written to. 4 eb4 0 r/w when this bit is set to 1, a12-kbyte area of h'1000 to h'3fff will be erased. 3 eb3 0 r/w when this bit is set to 1, a 1-kbyte area of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, a 1-kbyte area of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, a 1-kbyte area of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, a 1-kbyte area of h'0000 to h'03ff will be erased. 6.2.4 flash memory power control register (flpwcr) flpwcr enables or disables a transition to the flash memory power-down mode when this lsi enters the subactive mode. there are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in pow er-down mode and flash me mory can be read, and mode in which even if a transition is made to subactive mode, operat ion of the power supply circuit of flash memory is retain ed and flash memory can be read. bit bit name initial value r/w description 7 pdwnd 0 r/w power-down disable when this bit is 0 and a transition is made to subactive mode, the flash memory ent ers the power-down mode. when this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 6 rom rev. 3.00 may 15, 2007 page 104 of 516 rej09b0152-0300 6.2.5 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memo ry control registers, flmcr1, flmcr2, ebr1, and flpwcr. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 6.3 on-board programming modes the available mode for programming/erasing of the flash memory is b oot mode, which enables on-board programming/erasure. on-board programming/erasure can also be performed in user program mode. when this lsi starts after releasing the reset state, it enters a mode depending on the signal levels on the test, nmi , and e7_0 pins, as shown in table 6.1. the input level of each pin must be stable four states before the reset ends. when entering the boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entire flash memory , the programming control program is executed. this can be used for initializin g flash memory mounted on the user board or for a forcible recovery if flash memory cannot be programmed or erased in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user programming/erasing control program prepared by the user. table 6.1 setting programming modes test nmi e7_0 lsi state after reset released 0 1 x user mode 0 0 1 boot mode [legend] x: don?t care.
section 6 rom rev. 3.00 may 15, 2007 page 105 of 518 rej09b0152-0300 6.3.1 boot mode table 6.2 shows the boot mode operations be tween a reset released and a branch to the programming control program. this lsi includes a system clock oscillator which is operated by a resonator or an external clock and on-chip oscillator. in boot mode, since the system clock oscillator is selected, connect a resonator to osc1 and osc2, or an external clock signal to osc1. 1. when the boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 6.4, flash memory programming/erasure. 2. sci3 is set to the asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. the inversion function of the txd and rxd pins by spcr is set to ?not to be inverted,? so do not put inverters between the host and this lsi. 3. when the boot program is initiated, this lsi measures the low-level period of serial communication data (h'00) continuously transmitted in asynchronous mode from the host. this lsi then calculates the bit rate of the transfer from the host, and adjusts the sci3 bit rate to match that of the host. the reset signal should be negated while the rxd pin is driven high. the rxd and txd pins should be pulled up on the board if necessary. afte r the reset signal is negated, it takes approximately 100 states before this lsi is ready to measure the low-level period. 4. after matching the bit rates, sci3 transmits one byte of h'00 to the host to indicate the completion of bit rate adjustment. the host should confirm that it has received this adjustment end code (h'00) normally and th en transmit one byte of h'55 to this lsi. if reception could not be performed normally, initiate the boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and this lsi. to operate the sci properly, set the ho st's transfer bit rate and system clock frequency of this lsi w ithin the ranges listed in table 6.3. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the programming control program transmitted from the host can be stored in the area from h'fb80 to h'ff7f. the boot program area cannot be used until control of the execution is switched from the boot program to the programming control program.
section 6 rom rev. 3.00 may 15, 2007 page 106 of 516 rej09b0152-0300 6. before branching to the programming control pr ogram, this lsi terminat es transfer operations by sci3 (by clearing the re and te bits in scr3 to 0), however the adjusted bit rate value remains set in brr. therefore, the progra mming control program can still use it for transferring program data or verify data to the host. the txd pin is driven high (pcr32 = 1, p32 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these register s must be initialized at the beginning of the programming control program because the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. the boot mode can be released by a reset. hold the reset signal low at least 20 states and then set the nmi pin before negating the reset signal. the boot mode is also released when a wdt overflow occurs. 8. do not change the test pin and nmi pin input levels in boot mode.
section 6 rom rev. 3.00 may 15, 2007 page 107 of 518 rej09b0152-0300 table 6.2 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program after releasing reset state. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (lower byte following upper byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception low-order byte and high-order byte echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host. checks flash memory data, erases all flash memory blocks when data has been written to and then transmits data h'aa to host. (if erasure fails, transmits data of h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end code. h'55 reception. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of programming control program flash memory erase
section 6 rom rev. 3.00 may 15, 2007 page 108 of 516 rej09b0152-0300 table 6.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system cloc k frequency range of lsi 9,600 bps 8 to 10 mhz 4,800 bps 4 to 10 mhz 2,400 bps 2 to 10 mhz 6.3.2 programming/erasure in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user programming/erasing control program. the user must prepare the settings for branching to the user programming/erasing control program and means to transfer programming data for on-board programming. the flash memory must contain the user programming/erasing control program or a program that transfer the user programming/erasing control program from external memory. sin ce the flash memory cannot be read during programming/erasure, transfer the user programming/erasing control program to on-chip ram, as in boot mode. figure 6.2 shows a sample procedure for programming/erasure in user program mode. prepare a user programming/erasing control program in accordance with the description in section 6.4, flash memory programming/erasure. the system clock oscillator must be used when programming or erasing the flash memory. ye s no programming or erasure? transfer user programming/erasing control program to ram starting after releasing reset state branch to user programming/erasing control program in ram execute user programming/erasing control program (flash memory programmed) branch to flash memory application program branch to flash memory application program figure 6.2 programming/erasing flowchart example in user program mode
section 6 rom rev. 3.00 may 15, 2007 page 109 of 518 rej09b0152-0300 6.4 flash memory programming/erasure a software method using the cpu is employed to program and erase fl ash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: programming mode, programming-verifying mode, erasing mode, and erasing-verifying mode. the programming control program in boot mode and the user programming/erasing control program in user program mode use these operating modes in combination to perform programming/erasure. flash memory programming and erasing should be performed in accordance with the descriptions in section 6.4.1, programming/programming- verifying and section 6.4.2, erasing/erasing-verifying, respectively. 6.4.1 programming/programming-verifying when writing data or programs to the flash memory, the programming/programming-verifying flowchart shown in figure 6.3 should be follow ed. performing programm ing operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be performed on an erased area. do not reprogram an address to which data has already been programmed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if programming fewer than 128 bytes. in this case, the remaining area must be filled with h'ff. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 6.4, and additional programming data computation according to table 6.5. 4. consecutively transfer 128 bytes of data in bytes from the reprogramming data area or additional-programming data area to the flas h memory. the programming address and 128- byte data are latched in the flash memory. the lowe r eight bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 6.6 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verifying address, write 1-byte of data h'ff to an address whose lower two bits are b'00. verifying data can be read in words or in longwords from the address to which a dummy write was performed.
section 6 rom rev. 3.00 may 15, 2007 page 110 of 516 rej09b0152-0300 8. the maximum number of repetitions of the programming/programming-verifying sequence of the same bit is 1,000. start end of programming note: * the rts instruction must not be used during the following periods. 1. a period from programming 128-byte data to flash memory until clearing the p bit 2. a period from dummy-writing of h'ff to a verifying address until reading verifying data set swe bit to 1 write pulse application subroutine wait 1 s apply write pulse * end sub set psu bit to 1 enable wdt disable wdt wait 50 s set p bit to 1 wait (wait time = programming time) clear p bit to 0 wait 5 s clear psu bit to 0 wait 5 s n = 1 m = 0 no no no yes yes yes yes wait 4 s wait 2 s wait 2 s apply write pulse set pv bit to 1 set block start address as verifying address dummy write h'ff to verifying address read verifying data verifying data = write data? reprogramming data computation additional-programming data computation clear pv bit to 0 clear swe bit to 0 m = 1 m = 0 ? increment address programming failure no clear swe bit to 0 wait 100 s no yes n 6? no yes n 6 ? wait 100 s n 1000 ? n n + 1 write 128-byte reprogramming data in ram consecutively to flash memory store 128-byte programming data in programming data area and reprogramming data area apply write pulse sub-routine-call 128-byte of data verified? write 128-byte additional-programming data in ram to flash memory * figure 6.3 program/program-verify flowchart
section 6 rom rev. 3.00 may 15, 2007 page 111 of 518 rej09b0152-0300 table 6.4 reprogramming data computation table programming data verifying data reprogramming data comments 0 0 1 programming completed 0 1 0 needs to be programmed 1 0 1 ? 1 1 1 remains in erased state table 6.5 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 needs to be programmed additionally 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 6.6 programming time n (programming count) programming time additional programming time comments 1 to 6 times 30 s 10 s 7 to 1,000 times 200 s ? note: time shown in s.
section 6 rom rev. 3.00 may 15, 2007 page 112 of 516 rej09b0152-0300 6.4.2 erasing/erasing-verifying when erasing flash memory, the erasing/erasing-verifying flowchart shown in figure 6.4 should be followed. 1. prewriting (setting erase block da ta to all 0s) is not necessary. 2. erasure is performed in block units. select a single block to be erased through erase block register 1 (ebr1). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erasing time. 4. the watchdog timer (wdt) is set to prevent the flash memory overerasing due to program crush, etc. an overflow cycle of approximately 19.8 ms is adequate. 5. for writing dummy data to a verifying address, write one byte of data h'ff to an address whose lower two bits are b'00. verifying data can be read in longwords from the address to which a dummy data is written. 6. if the read data is not erased successfu lly, set erasing mode ag ain, and repeat the erasing/erasing-verifying sequ ence as before. the maximum nu mber of repetitions of the erase/erase-verify sequence is 100. 6.4.3 interrupt handling when pr ogramming/erasing flash memory all interrupts including the nmi interrupt are di sabled while flash memory is being programmed or erased or while the boot program is executed for the follo wing three reasons. 1. an interrupt during programming/erasure may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before programming the vector address or during programming/erasure, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
section 6 rom rev. 3.00 may 15, 2007 page 113 of 518 rej09b0152-0300 erase start set ebr1 enable wdt wait 1 s wait 100 s set swe bit to 1 n = 1 set esu bit to 1 set e bit to 1 wait 10 ms clear e bit to 0 wait 10 s clear esu bit to 0 wait 10 s disable wdt read verifying data increment address verifying data = all 1s ? last address of block ? all erase block erased ? set block start address to verifying address dummy write h'ff to verifying address wait 20 s wait 2 s set ev bit to 1 wait 100 s end of erasing note: * the rts instruction must not be used during a period from dummy-writing of h'ff to a verifying address until reading verifying data clear swe bit to 0 wait 4 s clear ev bit to 0 n 100 ? wait 100 s erase failure clear swe bit to 0 wait 4 s clear ev bit to 0 n n + 1 ye s no ye s ye s ye s no no no * figure 6.4 erase/erase-verify flowchart
section 6 rom rev. 3.00 may 15, 2007 page 114 of 516 rej09b0152-0300 6.5 programming/erasing protection there are three types of flash memory programming/erasing protection; hardware protection, software protection, and error protection. 6.5.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to the reset state, subactive mode, subsleep mode, watch mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) are initialized. for a reset by the res pin, the reset state is entered when the res signal is held low until oscillation stabilizes after switching on. for a reset during operation, hold the res signal low for the res pulse width specified in the ac characteristics section. 6.5.2 software protection software protection can protect programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is enabled, setting the p or e bit in flmcr1 does not cause a transition to programming mode or erasing mode. by setting the erase block register 1 (ebr1), erasing protection can be set for individual blocks. when ebr1 is set to h'00, erasing protection is set for all blocks. 6.5.3 error protection error protection is a state in which programming/erasure is forcibly aborted when an error is detected because cpu crush occurs during flash memory programming /erasure, or operation is not performed in accordance with th e programming/erasing algorithm. aborting programming/erasure prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are de tected during programming/eras ing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory address being programmed or erased is read (including vector read and instruction fetch) ? exception handling excluding a reset is started during programming/erasure ? when the sleep instruction is ex ecuted during programming/erasure
section 6 rom rev. 3.00 may 15, 2007 page 115 of 518 rej09b0152-0300 the flmcr1, flmcr2, and ebr1 settings are retained, however programming mode or erasing mode is aborted when the error occurred. programming mode or erasing mode cannot be re- entered by re-setting the p or e bit. however, settings of the pv and ev bits are retained, and a transition can be made to the verifying mode. the error protection state can be cleared only by a reset. 6.6 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read at high speed. ? power-down operating mode the power supply circuit of flash memory can be partly halted. as a re sult, flash memory can be read with low power consumption. ? standby mode all flash memory circuits are halted. table 6.7 shows the correspondence between the operating modes of this lsi and the flash memory. in subactive mode, the fl ash memory can be set to operate in power-down mode with the pdwnd bit in flpwcr. when the flash memory re turns to its normal operating state from the power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in syscr1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. table 6.7 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode watch mode standby mode standby mode standby mode standby mode standby mode
section 6 rom rev. 3.00 may 15, 2007 page 116 of 516 rej09b0152-0300 6.7 notes on setting module standby mode when the flash memory is set to enter the module standby mode, the system clock supply is stopped to the module, the function is stopped, and the state is the same as that in standby mode. also programming is stopped in the flash memory. therefore operation program should be transferred to the ram and the program should run in the ram. then the flash memory should be set to enter the module standby mode. if an interrupt is generated in module standby mode, the vector address cannot be fetched. as a result, the program may run away. before the flash memory is se t to enter module standby mode, the corresponding bit in the interrupt enable register should be cleared to 0 and the i bit in ccr should be set to 1. then after the flash memory enters the module standby mode, the nmi interrupt request should not be generated. transfer execution program to ram (user area) clear corresponding bit in interrupt enable register to 0 set i bit in ccr to 1 jump to address of execution program in ram clear fromckstp bit in crstpr1 to 0 figure 6.5 module standby mode setting
section 7 ram ram0500a_000120030300 rev. 3.00 may 15, 2007 page 117 of 516 rej09b0152-0300 section 7 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling two-state access by the cpu to both byte data and word data. product classification ram size ram address flash memory version h8/38602 rf 1 kbyte h'fb80 to h'ff7f masked rom version h8/38602r 1 kbyte h'fb80 to h'ff7f h8/38600r 512 bytes h'fd80 to h'ff7f
section 7 ram rev. 3.00 may 15, 2007 page 118 of 516 rej09b0152-0300
section 8 i/o ports rev. 3.00 may 15, 2007 page 119 of 516 rej09b0152-0300 section 8 i/o ports the h8/38602r group has 13 general i/o ports and six general input-only ports. port 8 is a large current port, which ca n drive 15 ma (@v ol = 1.0 v) when a low level signal is output. any of these ports can become an input port immediately afte r a reset. they can also be used as i/o pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. the registers for selecting these functions can be divided into two types: those included in i/o ports and those included in each on-chip peripheral module. general i/o ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. for details on the execution of bit manipulation instructions to the port data register (pdr), see section 2.8.3, bit-manipulation instruction. for details on block diagrams for each port, see appendix b.1, i/o port block diagrams. 8.1 port 1 port 1 is an i/o port also functioning as an asynchronous event counter input pin, timer w i/o pin, rtc output pin, clkout output pin, and interrupt input pin. figure 8.1 shows its pin configuration. p12/irqaec/aecpwm p11/aevl/ftci (/ irq1 ) p10/aevh/ftioa/tmow/clkout port 1 figure 8.1 port 1 pin configuration port 1 has the following registers. ? ? ? ?
section 8 i/o ports rev. 3.00 may 15, 2007 page 120 of 516 rej09b0152-0300 8.1.1 port data register 1 (pdr1) pdr1 is a register that stores data of port 1. bit bit name initial value r/w description 7 to 3 ? ? ? reserved the read value is undefined. these bits cannot be modified. 2 1 0 p12 p11 p10 0 0 0 r/w r/w r/w if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are read, re gardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. 8.1.2 port control register 1 (pcr1) pcr1 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 1. bit bit name initial value r/w description 7 to 3 ? ? ? reserved the read value is undefined. these bits cannot be modified. 2 1 0 pcr12 pcr11 pcr10 0 0 0 w w w setting a pcr1 bit to 1 makes the corresponding pin (p12 to p10) an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr1 and in pdr1 are valid when the corresponding pin is designated as a general i/o pin. pcr3 is a write-only register. the read value is undefined.
section 8 i/o ports rev. 3.00 may 15, 2007 page 121 of 516 rej09b0152-0300 8.1.3 port pull-up control register 1 (pucr1) pucr1 controls the pull-up mos of the port 1 pins in bit units. bit bit name initial value r/w description 7 to 3 ? ? ? reserved the read value is undefined. these bits cannot be modified. 2 1 0 pucr12 pucr11 pucr10 0 0 0 r/w r/w r/w when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the pull-up mos for the corresponding pin, while clearing the bit to 0 turns off the pull-up mos. 8.1.4 port mode register 1 (pmr1) pmr1 controls the selection of functions for port 1 pins. bit bit name initial value r/w description 7, 6 ? ? ? reserved the read value is undefined. these bits cannot be modified. 5 irqaec 0 r/w p12/irqaec/ aecpwm pin function switch 0: p12 i/o pin 1: irqaec input pin or aecpwm output pin 4 3 ftci * aevl * 0 0 r/w r/w p11/aevl/ftci/ irq1 pin function switch 00: p11 i/o pin 01: aevl input pin 1x: ftci input pin
section 8 i/o ports rev. 3.00 may 15, 2007 page 122 of 516 rej09b0152-0300 bit bit name initial value r/w description 2 1 0 clkout tmow aevh 0 0 0 r/w r/w r/w p10/aevh/ftioa/tmow/clkout pin function switch 000: p10 i/o pin and ftioa i/o pin 001: aevh input pin 01x: tmow pin 100: clkout output pin ( osc ) 101: clkout output pin ( osc /2) 110: clkout output pin ( osc /4) 111: setting prohibited [legend] x: don't care. note: * when the irq1s1 and irq1s0 bits in pfcr are set to b'10, the pin function becomes the irq1 input pin regardless of the setting of these bits. 8.1.5 pin functions the relationship between the register settings and the port functions is shown below. ? register name pmr1 aegsr pcr1 bit name irqaec ecpwme pcr12 pin function 0 p12 input pin 0 x 1 p12 output pin 1 x aecpwm output pin setting 1 0 x irqaec input pin [legend] x: don't care.
section 8 i/o ports rev. 3.00 may 15, 2007 page 123 of 516 rej09b0152-0300 ? irq1 ) pin register name pfcr pmr1 pcr1 bit name irq1s1 and irq1s0 ftci aevl pcr11 pin function 0 p11 input pin 0 1 p11 output pin 0 1 x aevl input pin other than b'10 1 x x ftci input pin setting b'10 x x x irq1 input pin [legend] x: don't care. ? register name pmr1 tior0 pcr1 bit name clkout tmow aevh ioa2 ioa1 ioa0 pcr10 pin function 0 p10 input pin 0 1 p10 output pin 0 1 x ftioa output pin 0 1 0 x ftioa output pin 1 x x 0 p10 input/ftioa input pin 0 1 x x 1 p10 output/ftioa input pin 0 1 x x x x aevh input pin 0 1 x x x x x tmow pin 0 x x x x clkout output pin ( osc ) * 0 1 x x x x clkout output pin ( osc /2) * setting 1 1 0 x x x x clkout output pin ( osc /4) * [legend] x: don't care. note: * switching the clock ( osc , osc /2, or osc /4) for clkout output must be performed when clkout output is halted (clkout = 0). when making a transition to a power-down m ode wherein the system clock oscillator is halted, the output level is retained. (in standby mode, output is the high-impedance state.) when making a transition from a power-down mo de wherein the system clock oscillator is halted, to the active mode wherein the system clock oscillator operates, halt clkout output (clkout = 0) bef ore the transition.
section 8 i/o ports rev. 3.00 may 15, 2007 page 124 of 516 rej09b0152-0300 8.1.6 input pull-up mos port 1 has an on-chip input pull-up mos function that can be controlled by software. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the input pull-up mos for that pin. the input pull-up mos function is in the off state after a reset. (n = 2 to 0) pcr1n 0 1 pucr1n 0 1 x input pull-up mos off on off [legend] x: don't care. 8.2 port 3 port 3 is an i/o port also functioning as an sc i3/irda i/o pin, comparator reference voltage pin and interrupt pin. figure 8.2 shows its pin configuration. p32/txd3/irtxd p31/rxd3/irrxd p30/sck3/vcref (/ irq0 ) port 3 figure 8.2 port 3 pin configuration port 3 has the following registers. ? ? ? ?
section 8 i/o ports rev. 3.00 may 15, 2007 page 125 of 516 rej09b0152-0300 8.2.1 port data register 3 (pdr3) pdr3 is a register that stores data of port 3. bit bit name initial value r/w description 7 to 3 ? ? ? reserved the read value is undefined. these bits cannot be modified. 2 1 0 p32 p31 p30 0 0 0 r/w r/w r/w if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, re gardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. 8.2.2 port control register 3 (pcr3) pcr3 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 3. bit bit name initial value r/w description 7 to 3 ? ? ? reserved the read value is undefined. these bits cannot be modified. 2 1 0 pcr32 pcr31 pcr30 0 0 0 w w w setting a pcr3 bit to 1 makes the corresponding pin (p32 to p30) an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid when the corresponding pin is designated as a general i/o pin. pcr3 is a write-only register. the read value is undefined.
section 8 i/o ports rev. 3.00 may 15, 2007 page 126 of 516 rej09b0152-0300 8.2.3 port pull-up control register 3 (pucr3) pucr3 controls the pull-up mos of the port 3 pins in bit units. bit bit name initial value r/w description 7 to 3 ? ? ? reserved the read value is undefined. these bits cannot be modified. 2 1 0 pucr32 pucr31 pucr30 0 0 0 r/w r/w r/w when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the pull-up mos for the corresponding pin, while clearing the bit to 0 turns off the pull-up mos. 8.2.4 port mode register 3 (pmr3) pmr3 controls the selection of functions for port 3 pins. bit bit name initial value r/w description 7 to 1 ? ? ? reserved the read value is undefined. these bits cannot be modified. 0 vcref 0 r/w p30/sck3/vcref pin function switch 0: p30 and sck3 i/o pin 1: comparator reference voltage (vcref) pin
section 8 i/o ports rev. 3.00 may 15, 2007 page 127 of 516 rej09b0152-0300 8.2.5 pin functions the relationship between the register settings and the port functions is shown below. ? register name spcr ircr pcr3 bit name spc3 ire pcr32 pin function 0 p32 input pin 0 x 1 p32 output pin 0 x txd3 output pin setting 1 1 x irtxd output pin [legend] x: don't care. ? register name scr3 ircr pcr3 bit name re ire pcr31 pin function 0 p31 input pin 0 x 1 p31 output pin 0 x rxd3 input pin setting 1 1 x irrxd input pin [legend] x: don't care. ? irq0 ) pin register name pfcr pmr3 scr3 smr3 pcr3 bit name irq0s1 and irq0s0 vc ref cke1 cke0 com pcr30 pin function 0 p30 input pin 0 1 p30 output pin 0 1 x sck3 output pin 0 1 x x sck3 output pin 0 1 0 x x sck3 input pin other than b'10 1 x x x x vcref pin setting b'10 x x x x x irq0 input pin [legend] x: don't care.
section 8 i/o ports rev. 3.00 may 15, 2007 page 128 of 516 rej09b0152-0300 8.2.6 input pull-up mos port 3 has an on-chip input pull-up mos function that can be controlled by software. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the input pull-up mos for that pin. the input pull-up mos function is in the off state after a reset. (n = 2 to 0) pcr3n 0 1 pucr3n 0 1 x input pull-up mos off on off [legend] x: don't care. 8.3 port 8 port 8 is an i/o port also functioning as a timer w i/o pin. figure 8.3 shows its pin configuration. port 8 p84/ftiod p83/ftioc p82/ftiob figure 8.3 port 8 pin configuration port 8 has the following registers. ? ? ?
section 8 i/o ports rev. 3.00 may 15, 2007 page 129 of 516 rej09b0152-0300 8.3.1 port data register 8 (pdr8) pdr8 is a register that stores data of port 8. bit bit name initial value r/w description 7 to 5 ? ? ? reserved the read value is undefined. these bits cannot be modified. 4 3 2 p84 p83 p82 0 0 0 r/w r/w r/w if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, re gardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. 1, 0 ? ? ? reserved the read value is undefined. these bits cannot be modified. 8.3.2 port control register 8 (pcr8) pcr8 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 8. bit bit name initial value r/w description 7 to 5 ? ? ? reserved the read value is undefined. these bits cannot be modified. 4 3 2 pcr84 pcr83 pcr82 0 0 0 w w w setting a pcr8 bit to 1 makes the corresponding pin (p84 to p82) an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr8 and in pdr8 are valid when the corresponding pin is designated as a general i/o pin. pcr8 is a write-only register. the read value is undefined. 1, 0 ? ? ? reserved the read value is undefined. these bits cannot be modified.
section 8 i/o ports rev. 3.00 may 15, 2007 page 130 of 516 rej09b0152-0300 8.3.3 port pull-up control register 8 (pucr8) pucr8 controls the pull-up mos of the port 8 pins in bit units. bit bit name initial value r/w description 7 to 5 ? ? ? reserved the read value is undefined. these bits cannot be modified. 4 3 2 pucr84 pucr83 pucr82 0 0 0 r/w r/w r/w when a pcr8 bit is cleared to 0, setting the corresponding pucr8 bit to 1 turns on the pull-up mos for the corresponding pin, while clearing the bit to 0 turns off the pull-up mos. 1, 0 ? ? ? reserved the read value is undefined. these bits cannot be modified. 8.3.4 pin functions the relationship between the register settings and the port functions is shown below. ? register name tmrw tior1 pcr8 bit name pwmd iod2 iod1 iod0 pcr84 pin function setting 0 0 0 0 0 p84 input pin 1 p84 output pin 1 x ftiod output pin 1 x x ftiod output pin 1 x x 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin 1 x x x x ftiod output pin [legend] x: don't care.
section 8 i/o ports rev. 3.00 may 15, 2007 page 131 of 516 rej09b0152-0300 ? register name tmrw tior1 pcr8 bit name pwmc ioc2 ioc1 ioc0 pcr83 pin function setting 0 0 0 0 0 p83 input pin 1 p83 output pin 1 x ftioc output pin 1 x x ftioc output pin 1 x x 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin 1 x x x x ftioc output pin [legend] x: don't care. ? register name tmrw tior0 pcr8 bit name pwmb iob2 iob1 iob0 pcr82 pin function setting 0 0 0 0 0 p82 input pin 1 p82 output pin 1 x ftiob output pin 1 x x ftiob output pin 1 x x 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin 1 x x x x ftiob output pin [legend] x: don't care.
section 8 i/o ports rev. 3.00 may 15, 2007 page 132 of 516 rej09b0152-0300 8.3.5 input pull-up mos port 8 has an on-chip input pull-up mos function that can be controlled by software. when a pcr8 bit is cleared to 0, setting the corresponding pucr8 bit to 1 turns on the input pull-up mos for that pin. the input pull-up mos function is in the off state after a reset. (n = 4 to 2) pcr8n 0 1 pucr8n 0 1 x input pull-up mos off on off [legend] x: don't care. 8.4 port 9 port 9 is an i/o port also functioning as an ssu i/o pin, iic2 i/o pin and interrupt pin. figure 8.4 shows its pin configuration. p93/ssi ( irq1 ) (1) ssus = 0 port 9 p92/sso ( irq0 ) p91/ssck/sda p90/ scs /scl p93/ scs ( irq1 ) p92/ssck ( irq0 ) p91/sso/sda p90/ssi/scl (2) ssus = 1 port 9 figure 8.4 port 9 pin configuration port 9 has the following registers. ? ? ? ?
section 8 i/o ports rev. 3.00 may 15, 2007 page 133 of 516 rej09b0152-0300 8.4.1 port data register 9 (pdr9) pdr9 is a register that stores data of port 9. bit bit name initial value r/w description 7 to 4 ? ? ? reserved the read value is undefined. these bits cannot be modified. 3 2 1 0 p93 p92 p91 p90 0 0 0 0 r/w r/w r/w r/w if port 9 is read while pcr9 bits are set to 1, the values stored in pdr9 are read, re gardless of the actual pin states. if port 9 is read while pcr9 bits are cleared to 0, the pin states are read. 8.4.2 port control register 9 (pcr9) pcr9 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 9. bit bit name initial value r/w description 7 to 4 ? ? ? reserved the read value is undefined. these bits cannot be modified. 3 2 1 0 pcr93 pcr92 pcr91 pcr90 0 0 0 0 w w w w setting a pcr9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr9 and in pdr9 are valid when the corresponding pin is designated as a general i/o pin. pcr9 is a write-only register. the read value is undefined.
section 8 i/o ports rev. 3.00 may 15, 2007 page 134 of 516 rej09b0152-0300 8.4.3 port open-drain control register 9 (podr9) podr9 selects the output format for port 9 pins. bit bit name initial value r/w description 7 to 4 ? ? ? reserved the read value is undefined. these bits cannot be modified. 3 2 1 0 p93odr p92odr p91odr p90odr 0 0 0 0 r/w r/w r/w r/w when a bit among the p93odr to p90odr bits is set to 1, the corresponding pin among p93 to p90 functions as the nmos open-drain output. when cleared to 0, the corresponding pin functions as the cmos output. 8.4.4 port pull-up control register 9 (pucr9) pucr9 controls the pull-up mos of the port 9 pins in bit units. bit bit name initial value r/w description 7 to 4 ? ? ? reserved the read value is undefined. these bits cannot be modified. 3 2 1 0 pucr93 pucr92 pucr91 pucr90 0 0 0 0 r/w r/w r/w r/w when a pcr9 bit is cleared to 0, setting the corresponding pucr9 bit to 1 turns on the pull-up mos for the corresponding pin, while clearing the bit to 0 turns off the pull-up mos.
section 8 i/o ports rev. 3.00 may 15, 2007 page 135 of 516 rej09b0152-0300 8.4.5 pin functions the relationship between the register settings and the port functions is shown below. note on the followings when port 9 is used. 1. when iic is used, ssu should not be set. 2. when ssu is used, the ice bit in iic should be set to 0. 3. the port corresponding to the pins for ssu communication data (ssi and sso) should not be set. 4. when the pins for communication data (ssi and sso) are set to open-drain output with the soos bit in the sscrh register of ssu, they are set to open-drain output regardless of the te and re bit settings in the sser register. ? irq1 ) pin register name pfcr pcr9 bit name irq1s1 and irq1s0 ssus pcr93 pin function 0 p93 input pin x 1 p93 output pin 0 x ssi i/o pin other than b'01 1 x scs i/o pin setting b'01 x x irq1 input pin [legend] x: don't care. note: when this pin is used as the ssi/ scs pin, register settings of the ssu are required. for details, see section 15.4.4, communication modes and pin functions, and appendix b.3, port 9 related register settings and pin functions.
section 8 i/o ports rev. 3.00 may 15, 2007 page 136 of 516 rej09b0152-0300 ? irq0 ) pin register name pfcr pcr9 bit name irq0s1 and irq0s0 ssus pcr92 pin function 0 p92 input pin x 1 p92 output pin 0 x sso i/o pin other than b'01 1 x ssck i/o pin setting b'01 x x irq0 input pin [legend] x: don't care. note: when this pin is used as the sso/ssck pin, register settings of the ssu are required. for details, see section 15.4.4, communication modes and pin functions, and appendix b.3, port 9 related register settings and pin functions. ? register name pfcr pcr9 bit name ssus pcr91 pin function 0 p91 input pin x 1 p91 output pin 0 x ssck i/o pin 1 x sso i/o pin setting x x sda i/o pin [legend] x: don't care. note: when this pin is used as the sso/ssck pin, register settings of the ssu are required. for details, see section 15.4.4, communication modes and pin functions, and appendix b.3, port 9 related register settings and pin functions. when this pin is used as the sda pin, register settings of the iic2 are requir ed. for details, see section 16.3.1, i 2 c bus control register 1 (iccr1). note that the priority when pin functions conflict is ssu pin > iic2 pin > p91.
section 8 i/o ports rev. 3.00 may 15, 2007 page 137 of 516 rej09b0152-0300 ? scs /scl pin register name pfcr pcr9 bit name ssus pcr90 pin function 0 p90 input pin x 1 p90 output pin 0 x scs i/o pin 1 x ssi i/o pin setting x x scl i/o pin [legend] x: don't care. note: when this pin is used as the scs /ssi pin, register settings of the ssu are required. for details, see section 15.4.4, communication modes and pin functions, and appendix b.3, port 9 related register settings and pin functions. when this pin is used as the scl pin, register settings of the iic2 are requir ed. for details, see section 16.3.1, i 2 c bus control register 1 (iccr1). note that the priority when pin functions conflict is ssu pin > iic2 pin > p90. 8.4.6 input pull-up mos port 9 has an on-chip input pull-up mos function that can be controlled by software. when a pcr9 bit is cleared to 0, setting the corresponding pucr9 bit to 1 turns on the input pull-up mos for that pin. the input pull-up mos function is in the off state after a reset. (n = 3 to 0) pcr9n 0 1 pucr9n 0 1 x input pull-up mos off on off [legend] x: don't care.
section 8 i/o ports rev. 3.00 may 15, 2007 page 138 of 516 rej09b0152-0300 8.5 port b port b is an input-only port also functioning as an interrupt input pin, analog input pin, and comparator pin. figure 8.5 shows its pin configuration. pb4/an4/comp0 pb5/an5/comp1 pb0/an0/ irq0 pb3/an3 pb2/an2 pb1/an1/ irq1 port b figure 8.5 port b pin configuration port b has the following registers. ? ? bit bit name initial value r/w description 7, 6 ? ? ? reserved the read value is undefined. these bits cannot be modified. 5 4 3 2 1 0 pb5 pb4 pb3 pb2 pb1 pb0 undefined undefined undefined undefined undefined undefined r r r r r r reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel by the ch3 to ch0 bits in amr of the a/d converter, that pin is read as 0 regardless of the input voltage.
section 8 i/o ports rev. 3.00 may 15, 2007 page 139 of 516 rej09b0152-0300 8.5.2 port mode register b (pmrb) pmrb controls the selection of the port b pin functions. bit bit name initial value r/w description 7 to 4 ? ? ? reserved the read value is undefined. these bits cannot be modified. 3 adtstchg 0 r/w test/ adtrg pin function switch selects whether pin test/ adtrg is used as test or as adtrg . 0: test pin 1: adtrg input pin for details on the setting of the adtrg input pin, refer to section 17.4.2, external trigger input timing. 2 ? ? ? reserved the read value is undefined. this bit cannot be modified. 1 irq1 0 r/w pb1/an1/ irq1 pin function switch selects whether pin pb1/an1/ irq1 is used as pb1/an1 or as irq1 . 0: pb1/an1 input pin 1: irq1 input pin * 0 irq0 0 r/w pb0/an0/ irq0 pin function switch selects whether pin pb0/an0/ irq0 is used as pb0/an0 or as irq0 . 0: pb0/an0 input pin 1: irq0 input pin * note: * when the irqns1 and irqns0 (n = 1 or 0) bits in pfcr are set to a value other than b'00, these bits should not be set since the irqn pin is assigned to another port.
section 8 i/o ports rev. 3.00 may 15, 2007 page 140 of 516 rej09b0152-0300 8.5.3 pin functions the relationship between the register settings and the port functions is shown below. ? register name amr bit name ch3 to ch0 pin function other than b'1001 pb5/comp1 input pin setting b'1001 an5 input pin [legend] x: don't care. ? register name amr bit name ch3 to ch0 pin function other than b'1000 pb4/comp0 input pin setting b'1000 an4 input pin [legend] x: don't care. ? register name amr bit name ch3 to ch0 pin function other than b'0111 pb3 input pin setting b'0111 an3 input pin [legend] x: don't care. ? register name amr bit name ch3 to ch0 pin function other than b'0110 pb2 input pin setting b'0110 an2 input pin [legend] x: don't care.
section 8 i/o ports rev. 3.00 may 15, 2007 page 141 of 516 rej09b0152-0300 ? irq1 pin register name pmrb amr pfcr bit name irq1 ch3 to ch0 irq1s1 and irq1s0 pin function other than b'0101 b'xx pb1 input pin 0 b'0101 b'xx an1 input pin b'00 irq1 input pin setting 1 b'xxxx other than b'00 setting prohibited [legend] x: don't care. ? irq0 pin register name pmrb amr pfcr bit name irq0 ch3 to ch0 irq0s1 and irq0s0 pin function other than b'0100 b'xx pb0 input pin 0 b'0100 b'xx an0 input pin b'00 irq0 input pin setting 1 b'xxxx other than b'00 setting prohibited [legend] x: don't care.
section 8 i/o ports rev. 3.00 may 15, 2007 page 142 of 516 rej09b0152-0300 8.6 input/output data inversion 8.6.1 serial port control register (spcr) spcr switches input/output data inversion of the rxd3 (irrxd) and txd3 (irtxd) pins. scinv0 p31/rxd3/irrxd p32/txd3/irtxd rxd3/irrxd txd3/irtxd scinv1 figure 8.6 input/output data inversion function bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 4 spc3 0 r/w p32/txd3/irtxd pin function switch selects whether pin p32/txd3/irtxd is used as p32 or as txd3/irtxd. 0: p32 i/o pin 1: txd3/irtxd output pin * note: * set the te bit in scr3 a fter setting this bit to 1. 3, 2 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 1 scinv1 0 r/w txd3/irtxd pin ou tput data inversion switch specifies whether the logic le vel of output data of the txd3/irtxd pin is to be inverted or not. 0: txd3/irtxd output data is not inverted 1: txd3/irtxd output data is inverted
section 8 i/o ports rev. 3.00 may 15, 2007 page 143 of 516 rej09b0152-0300 bit bit name initial value r/w description 0 scinv0 0 r/w rxd3/irrxd pin input data inversion switch specifies whether the logic level of input data of the rxd3/irrxd pin is to be inverted or not. 0: rxd3/irrxd input data is not inverted 1: rxd3/irrxd input data is inverted note: when the serial port control register is m odified, the data being input or output up to that point is inverted immediately after the modifi cation, and an invalid data change is input or output. when modifying the serial port control r egister, modification must be made in a state in which data changes are invalidated. 8.6.2 port function co ntrol register (pfcr) pfcr changes the ssu pin assignments, and assigns the irq0 and irq1 input pins to other ports. bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved these bits are always read as 0. these bits cannot be modified. 4 ssus 0 r/w ssu pin select changes the ssu pin assignments. 0: ssi is assigned to p93 sso is assigned to p92 ssck is assigned to p91 scs is assigned to p90 1: ssi is assigned to p90 sso is assigned to p91 ssck is assigned to p92 scs is assigned to p93 3 2 irq1s1 irq1s0 0 0 r/w r/w irq1 select 1, 0 00: irq1 is input from pb1 01: irq1 is input from p93 10: irq1 is input from p11 11: setting prohibited 1 0 irq0s1 irq0s0 0 0 r/w r/w irq0 select 1, 0 00: irq0 is input from pb0 01: irq0 is input from p92 10: irq0 is input from p30 11: setting prohibited
section 8 i/o ports rev. 3.00 may 15, 2007 page 144 of 516 rej09b0152-0300 8.7 usage notes 8.7.1 how to handle unused pin if an i/o pin not used by the user system is floating, pull it up or down. ? ? ? ? ? ? ? ? ? ? ? ? ? irq0 , irq1 , irqaec, aevl, aevh, sc k3, ftioa to ftiod, ftci, ssck, scs , sda, and scl are selected, the corresponding pins have the schmitt-trigger input characteristics, which are diff erent from the ones when they ar e used as the port input pins. for example, the input high voltage an d the input low voltage of the pb0/an0/ irq0 pin differ when the pin is used as pb0 input or irq0 input. for details, refer to table 21.2 which lists the dc characteristics for f-ztat version, and table 21.1 3 which lists the dc characteristics for masked rom version.
section 9 timer b1 rev. 3.00 may 15, 2007 page 145 of 516 rej09b0152-0300 section 9 timer b1 timer b1 is an 8-bit timer that increments each time a clock pulse is input. this timer has two operating modes, interval and auto reload. figure 9.1 shows a block diagram of timer b1. 9.1 features ? selection of eight internal clock sources ( /8192, /2048, /256, /64, /16, /4, w /1024, and w /256). ? an interrupt is generated when the counter overflows. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (timer b1 is halte d as the initial value. for details, refer to section 5.4, module standby function.) [legend] tmb1: tcb1: tlb1: irrtb1: pss: psw: timer mode register b1 timer counter b1 timer load register b1 time b1 interrupt request flag prescaler s prescaler w internal data bus tcb1 tmb1 pss w psw 1/4 tlb1 irrtb1 w/4 [ w/1024, w/256] figure 9.1 block diagram of timer b1
section 9 timer b1 rev. 3.00 may 15, 2007 page 146 of 516 rej09b0152-0300 9.2 register descriptions timer b1 has the following registers. ? timer mode register b1 (tmb1) ? timer counter b1 (tcb1) ? timer load register b1 (tlb1) 9.2.1 timer mode register b1 (tmb1) tmb1 selects the auto-reload function and input clock. bit bit name initial value r/w description 7 tmb17 0 r/w auto-reload function select 0: interval timer function selected 1: auto-reload function selected 6 tmb16 0 r/w counter operation/stop select 0: counter stopped 1: counter operates 5 to 3 ? all 1 ? reserved these bits are always read as 1. 2 1 0 tmb12 tmb11 tmb10 0 0 0 r/w r/w r/w counter clock select 000: internal clock: /8192 001: internal clock: /2048 010: internal clock: /256 011: internal clock: /64 100: internal clock: /16 101: internal clock: /4 110: internal clock: w /1024 111: internal clock: w /256
section 9 timer b1 rev. 3.00 may 15, 2007 page 147 of 518 rej09b0152-0300 9.2.2 timer counter b1 (tcb1) tcb1 is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tmb12 to tmb10 in tmb1. tcb1 values can be read by the cpu. when tcb1 overflows from h'ff to h'00 or to the value set in tlb1, the irrtb1 flag in irr2 is set to 1. tcb1 is al located to the same address as tlb1. tcb1 is initialized to h'00. 9.2.3 timer load register b1 (tlb1) tlb1 is an 8-bit write-only register for setting the reload value of tcb1. setting the reload value to tlb1 must be done when bit tmb16 in tmb1 is cleared to 0. when a reload value is set in tlb1, the same value is loaded into tcb1 as well, and tcb1 starts counting up from that value. when tcb1 overflows during operation in auto-reload mode, the tlb1 value is loaded into tcb1. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. tlb1 is allocated to the same address as tcb1. tlb1 is initialized to h'00.
section 9 timer b1 rev. 3.00 may 15, 2007 page 148 of 516 rej09b0152-0300 9.3 usage method figure 9.2 shows the initial setting flow of timer b1 after a reset, and figure 9.3 shows the processing flow for changing a setting during counter operation. bit tmb16 in tmb1 must be cleared to 0 when setting timer b1, as shown in th e figures. operation is not guaranteed when a setting is made with bit tmb16 in tmb1 set to 1. cancel the module standby mode of timer b1 * 1 set counter function with bit tmb17 in tmb1 and counter clock with bits tmb12 to tmb10 in tmb1 (bit tmb16 must be cleared to 0 when writing to these bits) set reload value to tlb1 when auto-reload function is selected set bit tmb16 in tmb1 to 1 to start counter operation (bits other than tmb16 must have the same values set at * 1 ) figure 9.2 timer b1 initial setting flow
section 9 timer b1 rev. 3.00 may 15, 2007 page 149 of 518 rej09b0152-0300 clear bit tmb16 in tmb1 to 0 to stop counter operation * 2 to modify the counter clock, change the value in bits tmb12 to tmb10 in tmb1 (bit tmb16 must be cleared to 0 when writing to these bits) to change the reload value, set a new reload value in tlb1 set bit tmb16 in tmb1 to 1 to start counter operation (bits other than tmb16 must have the same values set at * 2 ) figure 9.3 processing flow when changing setting during counter operation
section 9 timer b1 rev. 3.00 may 15, 2007 page 150 of 516 rej09b0152-0300 9.4 operation 9.4.1 interval timer operation when bit tmb17 in tmb1 is cleared to 0, timer b1 functions as an 8-bit interval timer. upon reset, tcb1 is cleared to h'00 and bit tmb17 is cl eared to 0, so the interval timer function is selected immediately after a reset. the operating cl ock of timer b1 is selected from eight internal clock signals output by prescaler s or prescaler w. the selection is made by bits tmb12 to tmb10 in tmb1. after bit tmb16 in tmb1 is set to 1 to start the counter operation and the count value in tmb1 reaches h'ff, the next clock signal input causes tim er b1 to overflow, setting flag irrtb1 in irr2 to 1. if ientb1 in ienr2 is 1, an interrupt is requested to the cpu. at overflow, tcb1 returns to h'00 and starts counting up again. even though interval timer operation (tmb17 = 0) is selected, when a value is set in tlb1 with bit tmb16 in tmb1 cleared to 0, the same value is set in tcb1. 9.4.2 auto-reload timer operation setting bit tmb17 in tmb1 to 1 causes timer b1 to function as an 8-bit auto-reload timer. when a reload value is set in tlb1 with bit tmb16 in tmb1 cleared to 0, the same value is loaded into tcb1. after bit tmb16 in tmb1 is set to 1 to start the counter operation and the count value in tcb1 reaches h'ff, the next clock signal input causes timer b1 to overflow. the tlb1 value is then loaded into tcb1, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb1 value. the clock sources and interrupts in auto-reload mo de are the same as in interval mode. to set a new value in tlb1 in auto-reload mode (tmb17 = 1), clear bit tmb16 in tmb1 to 0 before making the new setting.
section 9 timer b1 rev. 3.00 may 15, 2007 page 151 of 518 rej09b0152-0300 9.5 timer b1 operating modes table 9.1 shows the timer b1 operating modes. table 9.1 timer b1 operating modes active sleep oscillati on stabilization time clock source high- speed medium- speed high- speed medium- speed watch sub- active sub- sleep standby standby to active subsleep to active watch to active w/256, w/1024 /4, /16, /64, /256, /2048, /8192 [legend] : counting enabled : counting disabled (counter value retained)
section 9 timer b1 rev. 3.00 may 15, 2007 page 152 of 516 rej09b0152-0300
section 10 timer w tim08w0a_000020020200 rev. 3.00 may 15, 2007 page 153 of 516 rej09b0152-0300 section 10 timer w the timer w has a 16-bit timer having output co mpare and input capture functions. the timer w can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. thus, it can be applied to various systems. 10.1 features ? selection of eight counter clock sources: seven internal clocks ( , /2, /4, /8, w , w /4, and w /16) and an external clock (external events can be counted) ? capability to process up to four pulse outputs or four pulse inputs ? four general registers: ? independently assignable output compare or input capture functions ? usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register ? four selectable operating modes: ? waveform output by compare match selection of 0 output, 1 output, or toggle output ? input capture function rising edge, falling edge, or both edges ? counter clearing function counters can be cleared by compare match ? pwm mode up to three-phase pwm output can be provided with desired duty ratio. ? any initial timer output value can be set ? five interrupt sources four compare match/input capture interrupts and an overflow interrupt. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the timer w is halted as the in itial value. for details, refer to section 5.4, module standby function.) table 10.1 summarizes the timer w functions, and figure 10.1 shows a block diagram of the timer w.
section 10 timer w rev. 3.00 may 15, 2007 page 154 of 516 rej09b0152-0300 table 10.1 timer w functions input/output pins item counter ftioa ftiob ftioc ftiod count clock internal clocks: , /2, /4, /8, w , w /4, and w /16 external clock: ftci general registers (output compare/input capture registers) period specified in gra gra grb grc (buffer register for gra in buffer mode) grd (buffer register for grb in buffer mode) counter clearing function gra compare match gra compare match ? ? ? initial output value setting function ? yes yes yes yes buffer function ? yes yes ? ? compare 0 ? yes yes yes yes match output 1 ? yes yes yes yes toggle ? yes yes yes yes input capture function ? yes yes yes yes pwm mode ? ? yes yes yes interrupt sources overflow compare match/input capture compare match/input capture compare match/input capture compare match/input capture
section 10 timer w rev. 3.00 may 15, 2007 page 155 of 518 rej09b0152-0300 internal clock: external clock: ftci ftioa ftiob ftioc ftiod irrtw control logic clock selector comparator tcnt internal data bus bus interface [legend] tmrw: timer mode register w (8 bits) tcrw: timer control register w (8 bits) tierw: timer interrupt enable register w (8 bits) tsrw: timer status register w (8 bits) tior: timer i/o control register (8 bits) tcnt: timer counter (16 bits) gra: general register a (input capture/output compare register: 16 bits) grb: general register b (input capture/output compare register: 16 bits) grc: general register c (input capture/output compare register: 16 bits) grd: general register d (input capture/output compare register: 16 bits) irrtw: timer w interrupt request gra grb grc grd tmrw tcrw tierw tsrw tior /2 /4 /8 w w /4 w /16 figure 10.1 timer w block diagram
section 10 timer w rev. 3.00 may 15, 2007 page 156 of 516 rej09b0152-0300 10.2 input/output pins table 10.2 shows the pin configuration of the timer w. table 10.2 pin configuration name abbreviation input/output function external clock input ftci input external clock input pin input capture/output compare a ftioa input/output output pin for gra output compare or input pin for gra input capture input capture/output compare b ftiob input/output output pi n for grb output compare, input pin for grb input capture, or pwm output pin in pwm mode input capture/output compare c ftioc input/output output pi n for grc output compare, input pin for grc input capture, or pwm output pin in pwm mode input capture/output compare d ftiod input/output output pi n for grd output compare, input pin for grd input capture, or pwm output pin in pwm mode 10.3 register descriptions the timer w has the following registers. ? timer mode register w (tmrw) ? timer control register w (tcrw) ? timer interrupt enable register w (tierw) ? timer status register w (tsrw) ? timer i/o control register 0 (tior0) ? timer i/o control register 1 (tior1) ? timer counter (tcnt) ? general register a (gra) ? general register b (grb) ? general register c (grc) ? general register d (grd)
section 10 timer w rev. 3.00 may 15, 2007 page 157 of 518 rej09b0152-0300 10.3.1 timer mode register w (tmrw) tmrw selects the general register functions and the timer output mode. bit bit name initial value r/w description 7 cts 0 r/w counter start the counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 ? 1 ? reserved this bit is always read as 1. 5 bufeb 0 r/w buffer operation b selects the grd function. 0: grd operates as an input capture/output compare register 1: grd operates as the buffer register for grb 4 bufea 0 r/w buffer operation a selects the grc function. 0: grc operates as an input capture/output compare register 1: grc operates as the buffer register for gra 3 ? 1 ? reserved this bit is always read as 1. 2 pwmd 0 r/w pwm mode d selects the output mode of the ftiod pin. 0: ftiod operates normally (output compare output) 1: pwm output 1 pwmc 0 r/w pwm mode c selects the output mode of the ftioc pin. 0: ftioc operates normally (output compare output) 1: pwm output 0 pwmb 0 r/w pwm mode b selects the output mode of the ftiob pin. 0: ftiob operates normally (output compare output) 1: pwm output
section 10 timer w rev. 3.00 may 15, 2007 page 158 of 516 rej09b0152-0300 10.3.2 timer control register w (tcrw) tcrw selects the timer counter clock source, sel ects a clearing condition, and specifies the timer output levels. bit bit name initial value r/w description 7 cclr 0 r/w counter clear the tcnt value is cleared by compare match a when this bit is 1. when it is 0, tcnt operates as a free- running counter. 6 5 4 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select the tcnt clock source. 000: internal clock: counts on 001: internal clock: counts on /2 010: internal clock: counts on /4 011: internal clock: counts on /8 100: internal clock: counts on w 101: internal clock: counts on w /4 110: internal clock: counts on w /16 111: counts on rising edges of the external event (ftci) with a setting of 0xx, the timer w can be used only in active mode or sleep mode. do not make this setting in subactive mode or subsleep mode. when 100 is set in subactive mode or subsleep mode, the timer w can be used only when w is selected as the cpu operating clock. when 101 is set in subactive mode or subsleep mode, the timer w can be used only when w or w /2 is selected as the cpu operating clock. 3 tod 0 r/w timer output level setting d sets the output value of t he ftiod pin until the first compare match d is generated. 0: output value is 0 * 1: output value is 1 * 2 toc 0 r/w timer output level setting c sets the output value of t he ftioc pin until the first compare match c is generated. 0: output value is 0 * 1: output value is 1 *
section 10 timer w rev. 3.00 may 15, 2007 page 159 of 518 rej09b0152-0300 bit bit name initial value r/w description 1 tob 0 r/w timer output level setting b sets the output value of t he ftiob pin until the first compare match b is generated. 0: output value is 0 * 1: output value is 1 * 0 toa 0 r/w timer output level setting a sets the output value of t he ftioa pin until the first compare match a is generated. 0: output value is 0 * 1: output value is 1 * [legend] x: don't care. note: * the change of the setting is immediat ely reflected in the output value. 10.3.3 timer interrupt en able register w (tierw) tierw controls the timer w interrupt request. bit bit name initial value r/w description 7 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, fovi interrupt requested by ovf flag in tsrw is enabled. 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 imied 0 r/w input capture/com pare match interrupt enable d when this bit is set to 1, imid interrupt requested by imfd flag in tsrw is enabled. 2 imiec 0 r/w input capture/com pare match interrupt enable c when this bit is set to 1, imic interrupt requested by imfc flag in tsrw is enabled. 1 imieb 0 r/w input capture/com pare match interrupt enable b when this bit is set to 1, imib interrupt requested by imfb flag in tsrw is enabled. 0 imiea 0 r/w input capture/com pare match interrupt enable a when this bit is set to 1, imia interrupt requested by imfa flag in tsrw is enabled.
section 10 timer w rev. 3.00 may 15, 2007 page 160 of 516 rej09b0152-0300 10.3.4 timer status register w (tsrw) tsrw shows the status of interrupt requests. bit bit name initial value r/w description 7 ovf 0 r/(w) * timer overflow flag [setting condition] when tcnt overflows from h'ffff to h'0000 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 imfd 0 r/(w) * input capture/compare match flag d [setting conditions] ? tcnt = grd when grd functions as an output compare register ? the tcnt value is transferred to grd by an input capture signal when grd functions as an input capture register [clearing condition] read imfd when imfd = 1, then write 0 in imfd 2 imfc 0 r/(w) * input capture/compare match flag c [setting conditions] ? tcnt = grc when grc functions as an output compare register ? the tcnt value is transferred to grc by an input capture signal when grc functions as an input capture register [clearing condition] read imfc when imfc = 1, then write 0 in imfc
section 10 timer w rev. 3.00 may 15, 2007 page 161 of 518 rej09b0152-0300 bit bit name initial value r/w description 1 imfb 0 r/(w) * input capture/compare match flag b [setting conditions] ? tcnt = grb when grb functions as an output compare register ? the tcnt value is transferred to grb by an input capture signal when grb functions as an input capture register [clearing condition] read imfb when imfb = 1, then write 0 in imfb 0 imfa 0 r/(w) * input capture/compare match flag a [setting conditions] ? tcnt = gra when gra functions as an output compare register ? the tcnt value is transferred to gra by an input capture signal when gra functions as an input capture register [clearing condition] read imfa when imfa = 1, then write 0 in imfa note: * only 0 can be written to clear the flag. 10.3.5 timer i/o control register 0 (tior0) tior0 selects the functions of gra and grb, and specifies the functions of the ftioa and ftiob pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iob2 0 r/w i/o control b2 selects the grb function. 0: grb functions as an output compare register 1: grb functions as an input capture register
section 10 timer w rev. 3.00 may 15, 2007 page 162 of 516 rej09b0152-0300 bit bit name initial value r/w description 5 4 iob1 iob0 0 0 r/w r/w i/o control b1 and b0 when iob2 = 0, 00: no output at compare match 01: 0 output to the ftiob pin at grb compare match 10: 1 output to the ftiob pin at grb compare match 11: output toggles to the ftiob pin at grb compare match when iob2 = 1, 00: input capture at risi ng edge at the ftiob pin 01: input capture at fallin g edge at the ftiob pin 1x: input capture at rising and falling edges of the ftiob pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioa2 0 r/w i/o control a2 selects the gra function. 0: gra functions as an output compare register 1: gra functions as an input capture register 1 0 ioa1 ioa0 0 0 r/w r/w i/o control a1 and a0 when ioa2 = 0, 00: no output at compare match 01: 0 output to the ftioa pin at gra compare match 10: 1 output to the ftioa pin at gra compare match 11: output toggles to the ftioa pin at gra compare match when ioa2 = 1, 00: input capture at risi ng edge of the ftioa pin 01: input capture at fallin g edge of the ftioa pin 1x: input capture at rising and falling edges of the ftioa pin [legend] x: don't care.
section 10 timer w rev. 3.00 may 15, 2007 page 163 of 518 rej09b0152-0300 10.3.6 timer i/o control register 1 (tior1) tior1 selects the functions of grc and grd, and specifies the functions of the ftioc and ftiod pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iod2 0 r/w i/o control d2 selects the grd function. 0: grd functions as an output compare register 1: grd functions as an input capture register 5 4 iod1 iod0 0 0 r/w r/w i/o control d1 and d0 when iod2 = 0, 00: no output at compare match 01: 0 output to the ftiod pin at grd compare match 10: 1 output to the ftiod pin at grd compare match 11: output toggles to the ftiod pin at grd compare match when iod2 = 1, 00: input capture at risi ng edge at the ftiod pin 01: input capture at fallin g edge at the ftiod pin 1x: input capture at rising and falling edges at the ftiod pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioc2 0 r/w i/o control c2 selects the grc function. 0: grc functions as an output compare register 1: grc functions as an input capture register
section 10 timer w rev. 3.00 may 15, 2007 page 164 of 516 rej09b0152-0300 bit bit name initial value r/w description 1 0 ioc1 ioc0 0 0 r/w r/w i/o control c1 and c0 when ioc2 = 0, 00: no output at compare match 01: 0 output to the ftioc pin at grc compare match 10: 1 output to the ftioc pin at grc compare match 11: output toggles to the ftioc pin at grc compare match when ioc2 = 1, 00: input capture to grc at rising edge of the ftioc pin 01: input capture to grc at falling edge of the ftioc pin 1x: input capture to grc at rising and falling edges of the ftioc pin [legend] x: don't care. 10.3.7 timer counter (tcnt) tcnt is a 16-bit readable/writable up-counter. th e clock source is selected by bits cks2 to cks0 in tcrw. tcnt can be cleared to h'0000 through a compare match with gra by setting the cclr in tcrw to 1. when tcnt overflows (changes from h'ffff to h'0000), the ovf flag in tsrw is set to 1. if ovie in tierw is set to 1 at this time, an interrupt request is generated. tcnt must always be read or writte n in 16-bit units; 8-bit access is not allowed. tcnt is initialized to h'0000 by a reset.
section 10 timer w rev. 3.00 may 15, 2007 page 165 of 518 rej09b0152-0300 10.3.8 general registers a to d (gra to grd) each general register is a 16-bit readable/writable register that can function as either an output- compare register or an input-capture register. the function is selected by settings in tior0 and tior1. when a general register is used as an output-compare register, its value is constantly compared with the tcnt value. when the two values match (a compare match), the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. an interrupt request is generated at this time, when imiea, imieb, imiec, or imied in tierw is set to 1. compare match output can be selected in tior. when a general register is used as an input-captu re register, an external input-capture signal is detected and the current tcnt value is stored in the general register. the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. if the corresponding interrupt-enable bit (imiea, imieb, imiec, or imied) in tierw is se t to 1 at this time, an interrupt request is generated. the edge of the input-cap ture signal is selected in tior. grc and grd can be used as buffer registers of gra and grb, respectively, by setting bufea and bufeb in tmrw. for example, when gra is set as an output-compare register and grc is set as the buffer register for gra, the value in the buffer register grc is sent to gra whenever compare match a is generated. when gra is set as an input-capture register and grc is set as the buffer register for gra, the value in tcnt is transferred to gra and the va lue in gra is transferred to grc whenever an input capture is generated. gra to grd must be written or read in 16-bit un its; 8-bit access is not a llowed. gra to grd are initialized to h'ffff by a reset.
section 10 timer w rev. 3.00 may 15, 2007 page 166 of 516 rej09b0152-0300 10.4 operation the timer w has the following operating modes. ? normal operation ? pwm operation 10.4.1 normal operation tcnt performs free-running or periodic counting operations. after a reset, tcnt is set as a free- running counter. when the cts bit in tmrw is se t to 1, tcnt starts in crementing the count. when the count overflows from h'ffff to h'0000, the ovf flag in tsrw is set to 1. if the ovie in tierw is set to 1, an interrupt request is ge nerated. figure 10.2 shows free-running counting. tcnt value h'ffff h'0000 cts bit ovf time flag cleared by software figure 10.2 free-running counter operation
section 10 timer w rev. 3.00 may 15, 2007 page 167 of 518 rej09b0152-0300 periodic counting operation can be performed when gra is set as an output compare register and cclr bit in tcrw is set to 1. when the count matches gra, tcnt is cleared to h'0000, the imfa flag in tsrw is set to 1. if the correspond ing imiea bit in tierw is set to 1, an interrupt request is generated. tcnt continues counting from h'0000. figure 10.3 shows periodic counting. tcnt value gra h'0000 cts bit imfa time flag cleared by software figure 10.3 periodic counter operation by setting a general register as an output comp are register, compare matc h a, b, c, or d can cause the output at the ftioa, ftiob, ftioc, or ftiod pin to output 0, output 1, or toggle. figure 10.4 shows an example of 0 and 1 output when tcnt operates as a free-running counter, 1 output is selected for compare match a, and 0 output is selected for compare match b. when signal is already at the selected output level, the signal level does not ch ange at compare match. tcnt value h'ffff h'0000 ftioa ftiob time gra grb no change no change no change no change figure 10.4 0 and 1 output example (toa = 0, tob = 1)
section 10 timer w rev. 3.00 may 15, 2007 page 168 of 516 rej09b0152-0300 figure 10.5 shows an example of toggle output when tcnt operates as a free-running counter, and toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output figure 10.5 toggle output example (toa = 0, tob = 1) figure 10.6 shows another example of toggle output when tcnt operates as a periodic counter, cleared by compare matc h a. toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output counter cleared by compare match with gra figure 10.6 toggle output example (toa = 0, tob = 1)
section 10 timer w rev. 3.00 may 15, 2007 page 169 of 518 rej09b0152-0300 the tcnt value can be captured into a general register (gra, grb, grc, or grd) when a signal level changes at an input-capture pin (ftioa, ftiob, ftioc, or ftiod). capture can take place on the rising edge, fal ling edge, or both edges. by usin g the input-capture function, the pulse width and periods can be measured. figure 10.7 shows an example of input capture when both edges of ftioa and the falling edge of ftiob are selected as capture edges. tcnt operates as a free-running counter. tcnt value h'ffff h'1000 h'0000 ftioa gra time h'aa55 h'55aa h'f000 h'1000 h'f000 h'55aa grb h'aa55 ftiob figure 10.7 input capture operating example
section 10 timer w rev. 3.00 may 15, 2007 page 170 of 516 rej09b0152-0300 figure 10.8 shows an example of buffer operation when the gra is set as an input-capture register and grc is set as the bu ffer register for gra. tcnt op erates as a free-running counter, and ftioa captures both rising and falling edge of the input signal. due to the buffer operation, the gra value is transferred to grc by input-cap ture a and the tcnt value is stored in gra. tcnt value h'da91 h'0245 h'0000 grc time h'0245 ftioa gra h'5480 h'0245 h'ffff h'5480 h'5480 h'da91 figure 10.8 buffer operation example (input capture) 10.4.2 pwm operation in pwm mode, pwm waveforms are generated by using gra as the period register and grb, grc, and grd as duty registers. pwm waveforms are output from the ftiob, ftioc, and ftiod pins. up to three-phase pwm waveforms can be output. in pwm mode, a general register functions as an output compare register automatically. the out put level of each pin depends on the corresponding timer output level set bit (tob, toc, and tod) in tcrw. when tob is 1, the ftiob output goes to 1 at compare match a and to 0 at compare match b. when tob is 0, the ftiob output goes to 0 at compare match a and to 1 at compare match b. thus the compare match output level settings in tior0 and tior1 are ignored for the output pin set to pwm mode. if the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. figure 10.9 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is cleared at compare match a, and the output signals go to 0 at compare match b, c, and d (tob, toc, and tod = 1: initial output values are set to 1).
section 10 timer w rev. 3.00 may 15, 2007 page 171 of 518 rej09b0152-0300 tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 10.9 pwm mode example (1) figure 10.10 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is cleared at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0: initial output values are set to 0). tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 10.10 pwm mode example (2)
section 10 timer w rev. 3.00 may 15, 2007 page 172 of 516 rej09b0152-0300 figure 10.11 shows an example of buffer opera tion when the ftiob pin is set to pwm mode and grd is set as the buffer register for grb. tc nt is cleared by compare match a, and ftiob outputs 1 at compare match b and 0 at compare match a. due to the buffer operation, the ftiob output level changes and the value of buffer register grd is transferred to grb whenever compare match b occurs. this pr ocedure is repeated every time compare match b occurs. tcnt value gra h'0000 grd time grb h'0200 h'0520 ftiob h'0200 h'0450 h'0520 h'0450 grb h'0450 h'0520 h'0200 figure 10.11 buffer operatio n example (output compare)
section 10 timer w rev. 3.00 may 15, 2007 page 173 of 518 rej09b0152-0300 figures 10.12 and 10.13 show examples of the output of pwm waveforms with duty cycles of 0% and 100%. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 0% write to grb figure 10.12 pwm mode example (tob, toc, and tod = 0: initial output values are set to 0)
section 10 timer w rev. 3.00 may 15, 2007 page 174 of 516 rej09b0152-0300 tcnt value gra h'0000 ftiob time grb duty 100% write to grb tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 100% write to grb write to grb write to grb figure 10.13 pwm mode example (tob, toc, and tod = 1: initial output values are set to 1)
section 10 timer w rev. 3.00 may 15, 2007 page 175 of 518 rej09b0152-0300 10.5 operation timing 10.5.1 tcnt count timing figure 10.14 shows the tcnt count timing when th e internal clock source is selected. figure 10.15 shows the timing when the ex ternal clock source is selected. the pulse width of the external clock signal must be at least two system clock ( ) cycles; shorter pulses will not be counted correctly. tcnt tcnt input clock internal clock n n+1 n+2 rising edge figure 10.14 count timing for internal clock source tcnt tcnt input clock external clock nn+1 n+2 rising edge rising edge figure 10.15 count timing for external clock source
section 10 timer w rev. 3.00 may 15, 2007 page 176 of 516 rej09b0152-0300 10.5.2 output comp are output timing the compare match signal is generated in the last state in which tcnt and gr match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches gr, the compare match signal is generated only after the next counter clock pulse is input. figure 10.16 shows the output compare timing. gra to grd tcnt tcnt input clock n n n+1 compare match signal ftioa to ftiod figure 10.16 output compare output timing
section 10 timer w rev. 3.00 may 15, 2007 page 177 of 518 rej09b0152-0300 10.5.3 input ca pture timing input capture on the rising edge, falling edge, or both edges can be selected through settings in tior0 and tior1. figure 10.17 shows the timing when the falling edge is selected. the pulse width of the input capture signal mu st be at least two system clock ( ) cycles; shorter pulses will not be detected correctly. tcnt input capture input n?1 n n+1 n+2 n gra to grd input capture signal figure 10.17 input capture input signal timing 10.5.4 timing of counter clearing by compare match figure 10.18 shows the timing when the counter is cleared by compare match a. when the gra value is n, the counter counts from 0 to n, and its cycle is n + 1. tcnt compare match signal gra n n h'0000 figure 10.18 timing of count er clearing by compare match
section 10 timer w rev. 3.00 may 15, 2007 page 178 of 516 rej09b0152-0300 10.5.5 buffer operation timing figures 10.19 and 10.20 show the buffer operation timing. grc, grd compare match signal tcnt gra, grb n n+1 m m figure 10.19 buffer operat ion timing (compare match) gra, grb tcnt input capture signal grc, grd n m m n+1 n n n+1 figure 10.20 buffer operat ion timing (input capture)
section 10 timer w rev. 3.00 may 15, 2007 page 179 of 518 rej09b0152-0300 10.5.6 timing of imfa to imfd flag setting at compare match if a general register (gra, grb, grc, or grd) is used as an output compare register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when tcnt matches the general register. the compare match signal is generated in the last state in which the values match (when tcnt is updated from the matching count to the next count). therefore, when tcnt matches a general register, the compare match signal is generated only after the next tcnt clock pulse is input. figure 10.21 shows the timing of the imfa to imfd flag setting at compare match. gra to grd tcnt tcnt input clock n n n+1 compare match signal imfa to imfd irrtw figure 10.21 timing of imfa to imfd flag setting at compare match
section 10 timer w rev. 3.00 may 15, 2007 page 180 of 516 rej09b0152-0300 10.5.7 timing of imfa to im fd setting at input capture if a general register (gra, grb, grc, or grd) is used as an input capture register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when an input capture occurs. figure 10.22 shows the timing of the imfa to imfd flag setting at input capture. gra to grd tcnt input capture signal n n imfa to imfd irrtw figure 10.22 timing of imfa to imfd flag setting at input capture 10.5.8 timing of st atus flag clearing when the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 10.23 shows th e status flag clearing timing. imfa to imfd write signal address tsrw address irrtw tsrw write cycle t1 t2 figure 10.23 timing of status flag clearing by cpu
section 10 timer w rev. 3.00 may 15, 2007 page 181 of 518 rej09b0152-0300 10.6 timer w operating modes table 10.3 shows the timer w operating modes. table 10.3 timer w operating modes active sleep oscillati on stabilization time clock source high- speed medium- speed high- speed medium- speed watch sub- active sub- sleep standby standby to active subsleep to active watch to active ftci w, w/4, w/16 , /2, /4, /8 [legend] : counting enabled : counting disabled (counter value retained) 10.7 usage notes the following types of contention or operation can occur in timer w operation. 1. the pulse width of the input clock signal and the input capture signal must be at least two system clock cycles; shorter pulses will not be detected correctly. the system clock described here indicates the clock set for the cpu operation. for example, in the w/8 operation, at least w x 16 clock cycles are requi red as the pulse width. 2. writing to registers is performed in the t2 state of a tcnt write cycle. if counter clear signal occurs in the t2 state of a tcnt write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 10.24. if counting-up is generated in the tcnt write cycle to contend with the tcnt counting-up, writing takes precedence. 3. depending on the timing, tcnt may be incremented by a switch between different internal clock sources. when tcnt is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is, the divided system clock ( ). therefore, as shown in figure 10.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing tcnt to increment. 4. if timer w enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. before entering mo dule standby mode, disable interrupt requests.
section 10 timer w rev. 3.00 may 15, 2007 page 182 of 516 rej09b0152-0300 5. when an input capture function is specified, inputting a valid edge to the ftioa to ftiod pins sets the status bit of the correspondin g tsrw, even if the cts bit in tmrw is 0 (counting disabled state). when the relevant interrupt is enabled, this inputting generates an interrupt. 6. when the input capture timing conflicts with the corresponding gra to grd write timing, a. the written values are reflected in gra to grd. b. the status flag of the corresponding tsrw is set. 7. when the input capture timing conflicts with the gra to grd read timing, the read values are ones before capturing. the captured values can be read one clock after the capturing. 8. when the input capture a or b conflicts with the grc or grd write timing as the input capture operation in buffer mode, a. the captured values are reflected in gra or grb. b. the written values are reflected in grc or gr d. (the values in grc or grd are not ones in gra or grb before capturing.) 9. when the compare match timing conflicts with the gra to grd write timing as the compare match operation, a. the written values are reflected in gra to grd. b. the ftioa to ftiod output changes by the compare match. 10. when the compare match a or b conflicts with the gra or grb write timing as the compare match operation in buffer mode, a. the written values are reflected in gra or g rb. (the values in gra or grb are not ones in grc or grd of th e buffer register.) b. the ftioa or ftiob output changes by the compare match. 11. when the compare match a or b conflicts with the grc or grd write timing as the compare match operation in buffer mode, a. the values in gra or grb are ones in grc or grd before writing. b. the ftioa or ftiob output changes by the compare match. 12. when grc or grd is specifi ed to the compare match output as the compare match operation in buffer mode, ftioc or ftiod output changes by the grc or grd compare match. 13. when w, w/4, w/16, or ftci input is selected as the count clock, counting is enabled even in subactive and subsleep modes. counting is di sabled during the oscill ation stabilization time in transition to the active mode. 14. when w, w/4, w/16, or ftci input is selected as the count clock, counting is enabled in active and sleep modes although counting may be misaligned by one in transition from the active to subactive mode.
section 10 timer w rev. 3.00 may 15, 2007 page 183 of 518 rej09b0152-0300 counter clear signal write signal address tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 10.24 contention between tcnt write and clear tcnt previous clock n n+1 n+2 n+3 new clock count clock the change in signal level at clock switching is assumed to be a rising edge, and tcnt increments the count. figure 10.25 internal clock switching and tcnt operation
section 10 timer w rev. 3.00 may 15, 2007 page 184 of 516 rej09b0152-0300
section 11 realtime clock (rtc) rtc3000a_000120030300 rev. 3.00 may 15, 2007 page 185 of 516 rej09b0152-0300 section 11 realtime clock (rtc) the realtime clock (rtc) is a timer used to count time ranging from a second to a week. interrupts can be generated ranging from 0.25 seconds to a week. figure 11.1 shows the block diagram of the rtc. 11.1 features ? counts seconds, minutes, hours, and day-of-week ? start/stop function ? reset function ? readable/writable counter of seconds, minutes, hours, and day-of-week with bcd codes ? periodic (0.25 seconds, 0.5 seconds, one second, minute, hour, day, and week) interrupts ? 8-bit free running counter ? selection of clock source ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the rtc is oper ating as the initial value. for details, refer to section 5.4, module standby function.)
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 186 of 516 rej09b0152-0300 pss 32-khz oscillator circuit rtccsr rsecdr rmindr rwkdr clock count control circuit interrupt control circuit interrupt rtccr1 rhrdr rtccr2 rtcflg internal data bus 1/4 tmow [legend] rtccsr: rsecdr: rmindr: rhrdr: rwkdr: rtccr1: rtccr2: rtcflg: pss: clock source select register second date register/free running counter data register minute date register hour date register day-of-week date register rtc control register 1 rtc control register 2 rtc interrupt flag register prescaler s figure 11.1 block diagram of rtc 11.2 input/output pin table 11.1 shows the pin configuration of the rtc. table 11.1 pin configuration name abbreviation i/o function clock output tmow output rtc divided clock output
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 187 of 518 rej09b0152-0300 11.3 register descriptions the rtc has the following registers. ? second data register/free running counter data register (rsecdr) ? minute data register (rmindr) ? hour data register (rhrdr) ? day-of-week data register (rwkdr) ? rtc control register 1 (rtccr1) ? rtc control register 2 (rtccr2) ? clock source select register (rtccsr) ? rtc interrupt flag register (rtcflg) 11.3.1 second data register/free runn ing counter data register (rsecdr) rsecdr counts the bcd-coded second value. the setti ng range is decimal 00 to 59. it is an 8-bit read register used as a counter, when it operates as a free running counter. for more information on reading seconds, minutes, hours, and day-of-week, see section 11.4.3, data reading procedure. bit bit name initial value r/w description 7 bsy ?/(0) * r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 sc12 sc11 sc10 ?/(0) * ?/(0) * ?/(0) * r/w r/w r/w counting ten's position of seconds counts on 0 to 5 for 60-second counting. 3 2 1 0 sc03 sc02 sc01 sc00 ?/(0) * ?/(0) * ?/(0) * ?/(0) * r/w r/w r/w r/w counting one's position of seconds counts on 0 to 9 once per second. when a carry is generated, 1 is added to the ten's position. note: * initial value after a reset caused by the rst bit in rtccr1.
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 188 of 516 rej09b0152-0300 11.3.2 minute data register (rmindr) rmindr counts the bcd-coded minute value on the carry generated once per minute by the rsecdr counting. the setting range is decimal 00 to 59. bit bit name initial value r/w description 7 bsy ?/(0) * r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 mn12 mn11 mn10 ?/(0) * ?/(0) * ?/(0) * r/w r/w r/w counting ten's position of minutes counts on 0 to 5 for 60-minute counting. 3 2 1 0 mn03 mn02 mn01 mn00 ?/(0) * ?/(0) * ?/(0) * ?/(0) * r/w r/w r/w r/w counting one's position of minutes counts on 0 to 9 once per minute. when a carry is generated, 1 is added to the ten's position. note: * initial value after a reset caused by the rst bit in rtccr1.
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 189 of 518 rej09b0152-0300 11.3.3 hour data register (rhrdr) rhrdr counts the bcd-coded hour value on the carry generated once per hour by rmindr. the setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in rtccr1. bit bit name initial value r/w description 7 bsy ?/(0) * r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 ? 0 ? reserved this bit is always read as 0. 5 4 hr11 hr10 ?/(0) * ?/(0) * r/w r/w counting ten's position of hours counts on 0 to 2 for ten's position of hours. 3 2 1 0 hr03 hr02 hr01 hr00 ?/(0) * ?/(0) * ?/(0) * ?/(0) * r/w r/w r/w r/w counting one's position of hours counts on 0 to 9 once per hour. when a carry is generated, 1 is added to the ten's position. note: * initial value after a reset caused by the rst bit in rtccr1.
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 190 of 516 rej09b0152-0300 11.3.4 day-of-week data register (rwkdr) rwkdr counts the bcd-coded day-of-week value on the carry generated once per day by rhrdr. the setting range is decimal 0 to 6 using bits wk2 to wk0. bit bit name initial value r/w description 7 bsy ?/(0) * r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 to 3 ? all 0 ? reserved these bits are always read as 0. 2 1 0 wk2 wk1 wk0 ?/(0) * ?/(0) * ?/(0) * r/w r/w r/w day-of-week counting day-of-week is indicated with a binary code 000: sunday 001: monday 010: tuesday 011: wednesday 100: thursday 101: friday 110: saturday 111: reserved (setting prohibited) note: * initial value after a reset caused by the rst bit in rtccr1.
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 191 of 518 rej09b0152-0300 11.3.5 rtc control register 1 (rtccr1) rtccr1 controls start/stop and reset of the clock timer. for the definition of time expression, see figure 11.2. bit bit name initial value r/w description 7 run ?/(0) * r/w rtc operation start 0: stops rtc operation 1: starts rtc operation 6 12/24 ?/(0) * r/w operating mode 0: rtc operates in 12-hour mode. rhrdr counts on 0 to 11. 1: rtc operates in 24-hour mode. rhrdr counts on 0 to 23. 5 pm ?/(0) * r/w a.m./p.m. 0: indicates a.m. when rtc is in the 12-hour mode. 1: indicates p.m. when rtc is in the 12-hour mode. 4 rst 0 r/w reset 0: normal operation 1: resets registers and control circuits except rtccsr and this bit. clear this bit to 0 after having been set to 1. 3 int ?/(0) * r/w interrupt occurrence timing 0: periodic interrupts of second, minute, hour, and day-of- week occur during the rtc busy period. 1: periodic interrupts of second, minute, hour, and day-of- week occur immediately after the rtc busy period finishes. 2 to 0 ? all 0 ? reserved these bits are always read as 0. note: * initial value after a reset caused by the rst bit in rtccr1. 24-hour count 0 1 2 3 4 567891011121314151617 12-hour count 0 pm 24-hour count 12-hour count pm 0 (morning) 1 (afternoon) noon 123456789101101234 5 18 19 20 21 22 23 0 6 1 (afternoon) 0 7891011 0 figure 11.2 definition of time expression
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 192 of 516 rej09b0152-0300 11.3.6 rtc control register 2 (rtccr2) rtccr2 controls rtc periodic interrupts of week , day, hour, minute, one second, 0.5 seconds, and 0.25 seconds. enabling interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds sets the corresponding flag to 1 in the rtc interrupt flag register (rtcflg) when an interrupt occurs. it also controls an overfl ow interrupt of a free running counter when rtc operates as a free running counter. bit bit name initial value r/w description 7 foie ?/(0) * r/w free running counter overflow interrupt enable 0: disables an overflow interrupt 1: enables an overflow interrupt 6 wkie ?/(0) * r/w week periodic interrupt enable 0: disables a week periodic interrupt 1: enables a week periodic interrupt 5 dyie ?/(0) * r/w day periodic interrupt enable 0: disables a day periodic interrupt 1: enables a day periodic interrupt 4 hrie ?/(0) * r/w hour periodic interrupt enable 0: disables an hour periodic interrupt 1: enables an hour periodic interrupt 3 mnie ?/(0) * r/w minute periodic interrupt enable 0: disables a minute periodic interrupt 1: enables a minute periodic interrupt 2 1seie ?/(0) * r/w one-second periodic interrupt enable 0: disables a one-second periodic interrupt 1: enables a one-second periodic interrupt 1 05seie ?/(0) * r/w 0.5-second periodic interrupt enable 0: disables a 0.5-second periodic interrupt 1: enables a 0.5-second periodic interrupt 0 025seie ?/(0) * r/w 0.25-second periodic interrupt enable 0: disables a 0.25-second periodic interrupt 1: enables a 0.25-second periodic interrupt note: * initial value after a reset caused by the rst bit in rtccr1.
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 193 of 518 rej09b0152-0300 11.3.7 clock source sel ect register (rtccsr) rtccsr selects clock source. a free running counter controls start/stop of counter operation by the run bit in rtccr1. when a clock other than w /4 is selected, the rtc is disabled and operates as an 8-bit free running counter. when th e rtc operates as an 8- bit free running counter, rsecdr enables counter values to be read. an interrupt can be generated by setting 1 to the foie bit in rtccr2 and enabling an overflow interrupt of the free running counter. a clock generated by dividing the system clock by 32, 16, 8, or 4 is output in active or sleep mode. w is output in active, sleep, subactiv e, subsleep, or watch mode. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 5 4 rcs6 rcs5 sub32k 0 0 0 r/w r/w r/w clock output selection select a clock output from the tmow pin when enabling tmow output in pmr1. 000: /4 010: /8 100: /16 110: /32 xx1: w 3 2 1 0 rcs3 rcs2 rcs1 rcs0 1 0 0 0 r/w r/w r/w r/w clock source selection 0000: /8 ?????????????????? free running counter operation 0001: /32 ???????????????? free running counter operation 0010: /128 ?????????????? free running counter operation 0011: /256 ?????????????? free running counter operation 0100: /512 ?????????????? free running counter operation 0101: /2048 ???????????? free running counter operation 0110: /4096 ???????????? free running counter operation 0111: /8192 ???????????? free running counter operation 1000: w /4 ????????????????? rtc operation 1001 to 1111: setting prohibited
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 194 of 516 rej09b0152-0300 11.3.8 rtc interrupt fl ag register (rtcflg) rtcflg sets the corresponding flag when an interrupt occurs. each flag is not cleared automatically even if the interrupt is accepted. to clear the flag , 0 should be written to the flag. bit bit name initial value r/w description 7 foifg ?/(0) * 1 r/(w) * 2 [setting condition] when a free running counter overflows [clearing condition] 0 is written to foifg when foifg = 1 6 wkifg ?/(0) * 1 r/(w) * 2 [setting condition] when a week periodic interrupt occurs [clearing condition] 0 is written to wkifg when wkifg = 1 5 dyifg ?/(0) * 1 r/(w) * 2 [setting condition] when a day periodic interrupt occurs [clearing condition] 0 is written to dyifg when dyifg = 1 4 hrifg ?/(0) * 1 r/(w) * 2 [setting condition] when an hour periodic interrupt occurs [clearing condition] 0 is written to hrifg when hrifg = 1 3 mnifg ?/(0) * 1 r/(w) * 2 [setting condition] when a minute periodic interrupt occurs [clearing condition] 0 is written to mnifg when mnifg = 1 2 1seifg ?/(0) * 1 r/(w) * 2 [setting condition] when a one-second periodic interrupt occurs [clearing condition] 0 is written to 1seifg when 1seifg = 1
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 195 of 518 rej09b0152-0300 bit bit name initial value r/w description 1 05seifg ?/(0) * 1 r/(w) * 2 [setting condition] when a 0.5-second periodic interrupt occurs [clearing condition] 0 is written to 05seifg when 05seifg = 1 0 025seifg ?/(0) * 1 r/(w) * 2 [setting condition] when a 0.25-second periodic interrupt occurs [clearing condition] 0 is written to 025seifg when 025seifg = 1 notes: 1. initial value after a rese t caused by the rst bit in rtccr1. 2. only 0 can be written to clear the flag.
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 196 of 516 rej09b0152-0300 11.4 operation 11.4.1 initial settings of registers after power-on the rtc registers that store second, minute, hour, and day-of-week data, control registers, and interrupt registers are not reset by a res input, or by a reset source caused by a watchdog timer. therefore, all registers must be set to their in itial values after power-on. once the register setting are made, the rtc provides an accurate time as long as power is supplied regardless of a res input. 11.4.2 initial setting procedure figure 11.3 shows the procedure for the initial se tting of the rtc. to set the rtc again, also follow this procedure. rtc operation is stopped. rtc registers and clock count controller are reset. clock output and clock source are selected and second, minute, hour, day-of-week, operating mode, and a.m/p.m are set. rtc operation is started. run in rtccr1 = 0 rst in rtccr1 = 1 rst in rtccr1 = 0 set rtccsr, rsecdr, rmindr, rhrdr, rwkdr, 12/24 in rtccr1, and pm run in rtccr1 = 1 figure 11.3 initia l setting procedure
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 197 of 518 rej09b0152-0300 11.4.3 data reading procedure when the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be corr ect, and so the time data must be read again. figure 11.4 shows an example in which correct data is not obtained. in this exampl e, since only rsecdr is read after data update, about 1-minute inconsistency occurs. to avoid reading in this timing, the following processing must be performed. 1. check the setting of the bsy bit, and when the bsy bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. when about 62.5 ms is passed after the bsy bit is set to 1, the registers are updated, and the bsy bit is cleared to 0. 2. when int in rtccr1 is cleared to 0 and an interrupt is used, read from the second, minute, hour, and day-of-week registers after the relevant flag in rtcflg is set to 1 and the bsy bit is confirmed to be 0. when int in rtccr1 is set to 1 and an interrupt is used, read from the second, minute, hour, and day-of-week registers after the relevant flag in rtcflg is set to 1. 3. read from the second, minute, hour, and day-of-w eek registers twice in a row, and if there is no change in the read data, the read data is used. before update rwkdr = h'03, rhddr = h'13, rmindr = h'46, rsecdr = h'59 bsy bit = 0 (1) day-of-week data register read h'03 (2) hour data register read h'13 (3) minute data register read h'46 bsy bit -> 1 (under data update) after update rwkdr = h'03, rhddr = h'13, rmindr = h'47, rsecdr = h'00 bsy bit -> 0 (4) second data register read h'00 processing flow figure 11.4 example: readin g of inaccurate time data
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 198 of 516 rej09b0152-0300 11.5 interrupt sources there are eight kinds of rtc interrupts: a free-running counter overflow, week interrupt, day interrupt, hour interrupt, minute interrupt, one-sec ond interrupt, 0.5-second interrupt, and 0.25- second interrupt. when using an interrupt, set the ienrtc (rtc interrupt request enable) bit in ienr1 to 1 last after other registers are set. when an interrupt request of the rtc occurs, the corresponding flag in rtcflg is set to 1. when clearing the flag, write 0. table 11.2 interrupt sources interrupt name interrupt s ource interrupt enable bit overflow interrupt occurs when the free running counter is overflowed. foie week periodic interrupt occurs every week when the day-of-week date register value becomes 0. wkie day periodic interrupt occurs every day when the day-of-week date register is counted. dyie hour periodic interrupt occurs ever y hour when the hour date register is counted. hrie minute periodic interrupt occurs every minute when the minute date register is counted. mnie one-second periodic interrupt occurs every second when the one-second date register is counted. 1seie 0.5-second periodic interrupt occurs every 0.5 seconds. 05seie 0.25-second periodic interrupt occurs every 0.25 seconds. 025seie
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 199 of 518 rej09b0152-0300 11.6 usage notes 11.6.1 note on clock count the subclock must be connected to the 32.768-khz resonator. when the 38.4-khz resonator etc. is connected, the correct time count is not possible. 11.6.2 note when using rtc interrupts the rtc registers are not reset by a res input, power-on, or overflow of the watchdog timer, and their values are undefined after power-on. when using rtc interrupts, make sure to initialize the values before setting the ienrtc bit in ienr1 to 1.
section 11 realtime clock (rtc) rev. 3.00 may 15, 2007 page 200 of 516 rej09b0152-0300
section 12 watchdog timer wdt0110a_000020020200 rev. 3.00 may 15, 2007 page 201 of 516 rej09b0152-0300 section 12 watchdog timer this lsi incorporates the watchdog timer (wdt). the wdt is an 8-bit timer that can generate an internal reset signal if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. when this watchdog timer function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interr upt is generated each time the counter overflows. 12.1 features the wdt features are described below. ? selectable from eleven counter input clocks ten internal clock sources ( /64, /128, /256, /512, /1024, /2048, /4096, /8192, w /16, and w /256) or the on-chip oscillator (r osc /2048) can be selected as the timer-counter clock. ? watchdog timer mode if the counter overflows, this lsi is internally reset. ? interval timer mode if the counter overflows, an interval timer interrupt is generated. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the wdt is operating as the initial value. for details, refer to section 5.4, module standby function.)
section 12 watchdog timer rev. 3.00 may 15, 2007 page 202 of 516 rej09b0152-0300 figure 12.1 shows a block diagram of the wdt. r osc internal reset signal or interrupt request signal pss tcwd tmwd internal data bus tcsrwd2 tcsrwd1 [legend] [ w /16 or w /256] tcsrwd1: tcsrwd2: tcwd: tmwd: pss: timer control/status register wd1 timer control/status register wd2 timer counter wd timer mode register wd prescaler s on-chip oscillator interrupt/reset control figure 12.1 block diagram of watchdog timer 12.2 register descriptions the watchdog timer has the following registers. ? timer control/status re gister wd1 (tcsrwd1) ? timer control/status re gister wd2 (tcsrwd2) ? timer counter wd (tcwd) ? timer mode register wd (tmwd)
section 12 watchdog timer rev. 3.00 may 15, 2007 page 203 of 518 rej09b0152-0300 12.2.1 timer control/status register wd1 (tcsrwd1) tcsrwd1 performs the tcsrwd1 and tcwd write control. tcsrwd1 also controls the watchdog timer operation and indicates the operating state. tcsrwd1 must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 b6wi 1 r/w bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6 tcwe 0 r/w timer counter wd write enable tcwd can be written when the tcwe bit is set to 1. when writing data to this bit, the write value for bit 7 must be 0. 5 b4wi 1 r/w bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/w timer control/status register wd write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the write value for bit 5 must be 0. 3 b2wi 1 r/w bit 2 write inhibit the wdon bit can be written only when the write value of the b2wi bit is 0. this bit is always read as 1.
section 12 watchdog timer rev. 3.00 may 15, 2007 page 204 of 516 rej09b0152-0300 bit bit name initial value r/w description 2 wdon 1 r/w watchdog timer on tcwd starts counting up when the wdon bit is set to 1 and halts when the wdon bit is cleared to 0. [setting condition] ? when 1 is written to the wdon bit and 0 to the b2wi bit while the tcsrwe bit is 1 ? reset by res pin [clearing conditions] ? when 0 is written to the wdon bit and 0 to the b2wi bit while the tcsrwe bit is 1 1 b0wi 1 r/w bit 0 write inhibit the wrst bit can be written only when the write value of the b0wi bit is 0. this bit is always read as 1. 0 wrst 0 r/w watchdog timer reset indicates whether a reset caused by the watchdog timer is generated. this bit is not cleared by a reset caused by the watchdog timer. [setting condition] when tcwd overflows and an internal reset signal is generated [clearing conditions] ? reset by res pin ? when 0 is written to the wrst bit and 0 to the b0wi bit while the tcsrwe bit is 1
section 12 watchdog timer rev. 3.00 may 15, 2007 page 205 of 518 rej09b0152-0300 12.2.2 timer control/status register wd2 (tcsrwd2) tcsrwd2 performs the tcsrwd2 write control, mode switching, and interrupt control. tcsrwd2 must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 ovf 0 r/(w) * 1 overflow flag indicates that tcwd has ov erflowed (changes from h'ff to h'00). [setting condition] when tcwd overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, this bit is cleared automatically by the internal reset after it has been set. [clearing condition] ? when tcsrwd2 is read when ovf = 1, then 0 is written to ovf 6 b5wi 1 r/(w) * 2 bit 5 write inhibit the wt/ it bit can be written only when the write value of the b5wi bit is 0. this bit is always read as 1. 5 wt/ it 0 r/(w) * 3 timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: watchdog timer mode 1: interval timer mode 4 b3wi 1 r/(w) * 2 bit 3 write inhibit the ieovf bit can be written only when the write value of the b3wi bit is 0. this bit is always read as 1. 3 ieovf 0 r/(w) * 3 overflow interrupt enable enables or disables an overflow interrupt request in interval timer mode. 0: disables an overflow interrupt 1: enables an overflow interrupt
section 12 watchdog timer rev. 3.00 may 15, 2007 page 206 of 516 rej09b0152-0300 bit bit name initial value r/w description 2 to 0 ? all 1 ? reserved these bits are always read as 1. notes: 1. only 0 can be wr itten to clear the flag. 2. write operation is necessary because this bit controls data writing to other bit. this bit is always read as 1. 3. writing is possible only when the write conditions are satisfied. 12.2.3 timer coun ter wd (tcwd) tcwd is an 8-bit readable/writable up-counter. when tcwd overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrwd1 is set to 1. tcwd is initialized to h'00.
section 12 watchdog timer rev. 3.00 may 15, 2007 page 207 of 518 rej09b0152-0300 12.2.4 timer mode register wd (tmwd) tmwd selects the input clock. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w clock select 3 to 0 select the clock to be input to tcwd. 00xx: on-chip oscillator: counts on r osc /2048 0100: internal clock: counts on w /16 0101: internal clock: counts on w /256 011x: reserved 1000: internal clock: counts on /64 1001: internal clock: counts on /128 1010: internal clock: counts on /256 1011: internal clock: counts on /512 1100: internal clock: counts on /1024 1101: internal clock: counts on /2048 1110: internal clock: counts on /4096 1111: internal clock: counts on 8192 for the on-chip oscillator overflow periods, see section 21, electrical characteristics. in active (medium-speed), sleep (medium-speed), subactive, and subsleep modes, the 00xx value and the interval timer mode cannot be set simultaneously. in subactive and subsleep modes, when the subclock frequency is w /8, the 010x value and the interval timer mode cannot be set simultaneously. [legend] x: don't care.
section 12 watchdog timer rev. 3.00 may 15, 2007 page 208 of 516 rej09b0152-0300 12.3 operation 12.3.1 watchdog timer mode the watchdog timer is provided with an 8-bit up-counter. to use it as the watchdog timer, clear the wt/ it bit in tcsrwd2 to 0. (to write the wt/ it bit, two write accesses are required.) if 1 is written to the wdon bit and 0 to the b2wi bit simultaneously when the tcsrwe bit in tcsrwd1 is set to 1, tcwd begins counting up. (to operate the watchdog timer, two write accesses to tcsrwd1 are required.) when a clock pu lse is input after the tcwd count value has reached h'ff, the watchdog timer overflows and an in ternal reset signal is generated. the internal reset signal is output for a period of 512 clock cycles by the on-chip oscillator (r osc ). tcwd is a writable counter, and when a value is set in tcwd, the count-up starts from that value. an overflow period in the range of 1 to 256 input cl ock cycles can therefore be set, according to the tcwd set value. figure 12.2 shows an example of watchdog timer operation. example: with 30-ms overflow period when = 4 mhz 4 10 6 30 10 ?3 = 14.6 8192 tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated start 512 clock cycles by r osc therefore, 256 ? 15 = 241 (h'f1) is set in tcwd. figure 12.2 example of watchdog timer operation
section 12 watchdog timer rev. 3.00 may 15, 2007 page 209 of 518 rej09b0152-0300 12.3.2 interval timer mode figure 12.3 shows the operation in interval timer mode. to use the wdt as an interval timer, set the wt/ it bit in tcsrwd2 to 1. when the wdt is used as an interval timer, an interval timer interrupt request is generated each time the tcwd overflows. therefore, an interval timer interrupt can be generated at intervals. tcwd count value h'00 time h'ff wt/ it = 1 interval timer interrupt request generated interval timer interrupt request generated interval timer interrupt request generated interval timer interrupt request generated interval timer interrupt request generated figure 12.3 interval timer mode operation 12.3.3 timing of overf low flag (ovf) setting figure 12.4 shows the timing of the ovf flag setting. the ovf flag in tcsrwd2 is set to 1 if tcwd overflows. at the same time, a reset signal is output in watchdog timer mode and an interval timer interrupt is generated in interval timer mode. tcwd h'ff h'00 overflow signal ovf figure 12.4 timing of ovf flag setting
section 12 watchdog timer rev. 3.00 may 15, 2007 page 210 of 516 rej09b0152-0300 12.4 interrupt during interval timer mode operation, an overflow generates an interval timer interrupt. the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsrwd2. the ovf flag must be cleared to 0 in the interrupt handling routine. 12.5 usage notes 12.5.1 switching between watchdog ti mer mode and interval timer mode if modes are switched between watchdog timer and interval timer, while the wdt is operating, an error may occur in the count value. software must stop the watchdog timer (by clearing the wdon bit to 0) before switching modes. 12.5.2 module standby mode control the wdckstp bit in ckstpr2 is valid when the wd on bit in the timer control/status register wd1 (tcsrwd1) is cleared to 0. the wdckstp b it can be cleared to 0 while the wdon bit is set to 1 (while the watchdog timer is operating). however, the watchdog timer does not enter module standby mode but continues operating. when the wdon bit is cleared to 0 by software after the watchdog timer stops operating, the wdckstp bit is valid at the same time and the watchdog timer enters module standby mode. 12.5.3 clearing the wt/ it or ieovf bit in tcsrwd2 to 0 when clearing the wt/ it or ieovf bit in the timer control/status register wd2 (tcsrwd2) to 0, the corresponding bit may not be cleared to 0 depending on the program address. in particular, if lower two bits in the address of the mov.b instruction to transfer a value to tcsrwd2 are b'10, the wt/ it or ieovf bit is successfully cleared to 0, whereas if lower two bits in the address are b'00, the wt/ it or ieovf bit may not be cleared to 0. to avoid this failure, make sure to use the assembly program shown in ta ble 12.1, when clearing the wt/ it or ieovf bit to 0. specify tcsrwd2 by the 8-bit absolute address, and la bel by the 16-bit absolute address. don't change nor add instructio ns. the value of "xx" in line 1 and line 4 must be set according to table 12.2. use an arbitrary 8-bit general register for rn and rm. in addition, address1 in table 12.1 shows an example when the wt/ it or ieovf bit is cleared to 0 successfully by the mov.b instruction in line 2. address2 in table 12.1 shows an example when the wt/ it or ieovf bit fails to be cleared to 0 by the mov.b instruction in line 2, but cleared to 0 by the mov.b instruction in line 6.
section 12 watchdog timer rev. 3.00 may 15, 2007 page 211 of 518 rej09b0152-0300 table 12.1 assembly pr ogram for clearing wt/ it or ieovf bit to 0 address1 address2 assembly program h'00a0 h'0232 mov.b #h'xx,rn h'00a2 h'0234 mov.b rn,@tcsrwd2:8 ; cl ear success in case of address1 and failure in case of address2 h'00a4 h'0236 mov.b @tcsrwd2:8,rm ; tcsrwd2 read h'00a6 h'0238 and.b #h'xx, rm ; judgment of clear h'00a8 h'023a beq label:16 ; jumps to label if it is a clear success h'00ac h'023e mov.b rn,@tcsrwd2:8 ; clear success in case of address2 h'00ae h'0240 label nop table 12.2 the value of "xx" bit(s) cleared to 0 the value of "xx" in line 1 the value of "xx" in line 4 both wt/ it and ieovf 07 28 only wt/ it 17 20 only ieovf 47 08
section 12 watchdog timer rev. 3.00 may 15, 2007 page 212 of 516 rej09b0152-0300
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 213 of 516 rej09b0152-0300 section 13 asynchronou s event counter (aec) the asynchronous event counter (a ec) is an event counter that is incremented by external event clock or internal clock input. figure 13.1 shows a block diagram of the asynchronous event counter. 13.1 features ? can count asynchronous events can count external events input asynchronously without regard to the operation of system clocks ( ) or subclocks ( sub ). ? can be used as two-channel independent 8-bit event counter or single-channel independent 16- bit event counter. ? event/clock input is enabled when irqaec goes high or event counter pwm output (iecpwm) goes high. ? both rising and falling edge sensing can be used for irqaec or event counter pwm output (iecpwm) interrupts. when the asynchronous counter is not used, they can be used as independent interrupts. ? when an event counter pwm is used, event clock input enabling/disabling can be controlled at a constant cycle. an event counter pwm can be output to the aecpwm pin. ? selection of four clock sources three internal clocks ( /2, /4, or /8) or external event can be selected. ? both rising and falling edge counting is possible for the aevl and aevh pins. ? counter resetting and halting of the count-up function can be controlled by software. ? automatic interrupt generation on detection of an event counter overflow ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the asynchronous event counter is halted as the initial value. for details, refer to section 5.4, module standby function.)
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 214 of 516 rej09b0152-0300 aevh aevl irqaec aecpwm w/16 iecpwm eccr pss eccsr internal data bus ovh ovl ecpwcr ecpwdr aegsr ech (8 bits) ck ecl (8 bits) ck irrec to cpu interrupt (irrec2) edge sensing circuit edge sensing circuit edge sensing circuit pwm waveform generator /2 /4, /8 /2, /4, /8, /16, /32, /64 [legend] ecpwcr: ecpwdr: aegsr: eccsr: event counter pwm compare register event counter pwm data register input pin edge select register event counter control/status register ecl: eccr: ech: pss: event counter l event counter control register event counter h prescaler s figure 13.1 block diagram of asynchronous event counter
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 215 of 516 rej09b0152-0300 13.2 input/output pins table 13.1 shows the pin configuration of the asynchronous event counter. table 13.1 pin configuration name abbreviation i/o function asynchronous event input h aevh input event input pin for input to event counter h asynchronous event input l aevl input event input pin for input to event counter l event input enable interrupt input irqaec input input pin for in terrupt enabling event input event counter pwm output aecpwm output event counter pwm output pin 13.3 register descriptions the asynchronous event counter has the following registers. ? event counter pwm compare register (ecpwcr) ? event counter pwm data register (ecpwdr) ? input pin edge select register (aegsr) ? event counter control register (eccr) ? event counter control/status register (eccsr) ? event counter h (ech) ? event counter l (ecl)
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 216 of 516 rej09b0152-0300 13.3.1 event counter pwm compare register (ecpwcr) ecpwcr sets the one conversion period of the event counter pwm waveform. bit bit name initial value r/w description 15 ecpwcr15 1 r/w 14 ecpwcr14 1 r/w 13 ecpwcr13 1 r/w 12 ecpwcr12 1 r/w 11 ecpwcr11 1 r/w 10 ecpwcr10 1 r/w 9 ecpwcr9 1 r/w 8 ecpwcr8 1 r/w 7 ecpwcr7 1 r/w 6 ecpwcr6 1 r/w 5 ecpwcr5 1 r/w 4 ecpwcr4 1 r/w 3 ecpwcr3 1 r/w 2 ecpwcr2 1 r/w 1 ecpwcr1 1 r/w 0 ecpwcr0 1 r/w one conversion period of event counter pwm waveform when the ecpwme bit in aegsr is 1, the event counter pwm is operati ng and therefore ecpwcr should not be modified. when changing the conversion period, the event counter pwm must be halted by clearing the ecpwme bit in aegsr to 0 before modifying ecpwcr.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 217 of 516 rej09b0152-0300 13.3.2 event counter pwm data register (ecpwdr) ecpwdr controls data of the event counter pwm waveform generator. bit bit name initial value r/w description 15 ecpwdr15 0 w 14 ecpwdr14 0 w 13 ecpwdr13 0 w 12 ecpwdr12 0 w 11 ecpwdr11 0 w 10 ecpwdr10 0 w 9 ecpwdr9 0 w 8 ecpwdr8 0 w 7 ecpwdr7 0 w 6 ecpwdr6 0 w 5 ecpwdr5 0 w 4 ecpwdr4 0 w 3 ecpwdr3 0 w 2 ecpwdr2 0 w 1 ecpwdr1 0 w 0 ecpwdr0 0 w data control of event counter pwm waveform generator when the ecpwme bit in aegsr is 1, the event counter pwm is operati ng and therefore ecpwdr should not be modified. when changing the conver sion cycle, the event counter pwm must be halted by clearing the ecpwme bit in aegsr to 0 before modifying ecpwdr. the read value is undefined.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 218 of 516 rej09b0152-0300 13.3.3 input pin edge select register (aegsr) aegsr selects rising, falling, or both edge sensing for the aevh, aevl, and irqaec pins, and controls irqaec/iecpwm. bit bit name initial value r/w description 7 6 ahegs1 ahegs0 0 0 r/w r/w aec edge select h select rising, falling, or both edge sensing for the aevh pin. 00: falling edge on aevh pin is sensed 01: rising edge on aevh pin is sensed 10: both edges on aevh pin are sensed 11: setting prohibited 5 4 alegs1 alegs0 0 0 r/w r/w aec edge select l select rising, falling, or both edge sensing for the aevl pin. 00: falling edge on aevl pin is sensed 01: rising edge on aevl pin is sensed 10: both edges on aevl pin are sensed 11: setting prohibited 3 2 aiegs1 aiegs0 0 0 r/w r/w irqaec edge select select rising, falling, or both edge sensing for the irqaec pin. 00: falling edge on irqaec pin is sensed 01: rising edge on irqaec pin is sensed 10: both edges on irqaec pin are sensed 11: setting prohibited 1 ecpwme 0 r/w event counter pwm enable controls operation of event counter pwm and selection of irqaec. 0: aec pwm halted, irqaec selected 1: aec pwm enabled, irqaec not selected 0 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 219 of 516 rej09b0152-0300 13.3.4 event counter co ntrol register (eccr) eccr controls the counter input clock and pwm clock. bit bit name initial value r/w description 7 6 ackh1 ackh0 0 0 r/w r/w aec clock select h select the clock used by ech. 00: aevh pin input 01: /2 10: /4 11: /8 5 4 ackl1 ackl0 0 0 r/w r/w aec clock select l select the clock used by ecl. 00: aevl pin input 01: /2 10: /4 11: /8 3 2 1 pwck2 pwck1 pwck0 0 0 0 r/w r/w r/w event counter pwm clock select select the event counter pwm clock. 000: /2 001: /4 010: /8 011: /16 100: /32 101: /64 110: w /16 111: setting prohibited when changing the event counter pwm clock, the ecpwme bit in aegsr must be cleared to 0 to stop the pwm before rewriting this setting. 0 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 220 of 516 rej09b0152-0300 13.3.5 event counter cont rol/status register (eccsr) eccsr controls counter overflow detection, counter resetting, and count-up function. bit bit name initial value r/w description 7 ovh 0 r/w * counter overflow h this is a status flag indicating that ech has overflowed. [setting condition] when ech overflows from h?ff to h?00 [clearing condition] when this bit is written to 0 after reading ovh = 1 6 ovl 0 r/w * counter overflow l this is a status flag indicating that ecl has overflowed. [setting condition] when ecl overflows from h'ff to h'00 while ch2 is set to 1 [clearing condition] when this bit is written to 0 after reading ovl = 1 5 ? 0 r/w reserved although this bit is readable/writable, only 0 should be written to. 4 ch2 0 r/w channel select selects how ech and ecl event counters are used 0: ech and ecl are used together as a single-channel 16-bit event counter 1: ech and ecl are used as two-channel 8-bit event counter 3 cueh 0 r/w count-up enable h enables event clock input to ech. 0: ech event clock input is disabled (ech value is retained) 1: ech event clock input is enabled
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 221 of 516 rej09b0152-0300 bit bit name initial value r/w description 2 cuel 0 r/w count-up enable l enables event clock input to ecl. 0: ecl event clock input is disabled (ecl value is retained) 1: ecl event clock input is enabled 1 crch 0 r/w counter reset control h controls resetting of ech. 0: ech is reset 1: ech reset is cleared and count-up function is enabled 0 crcl 0 r/w counter reset control l controls resetting of ecl. 0: ecl is reset 1: ecl reset is cleared and count-up function is enabled note: * only 0 can be written to clear the flag.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 222 of 516 rej09b0152-0300 13.3.6 event counter h (ech) ech is an 8-bit read-only up-counter that operat es as an independent 8-bit event counter. ech also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ecl. bit bit name initial value r/w description 7 ech7 0 r 6 ech6 0 r 5 ech5 0 r 4 ech4 0 r 3 ech3 0 r 2 ech2 0 r 1 ech1 0 r 0 ech0 0 r either the external asyn chronous event aevh pin, /2, /4, or /8, or the overflow signal from lower 8-bit counter ecl can be selected as the input clock source. ech can be cleared to h'00 when the crch bit in eccsr is cleared to 0. 13.3.7 event counter l (ecl) ecl is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ecl also operates as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ech. bit bit name initial value r/w description 7 ecl7 0 r 6 ecl6 0 r 5 ecl5 0 r 4 ecl4 0 r 3 ecl3 0 r 2 ecl2 0 r 1 ecl1 0 r 0 ecl0 0 r either the external asyn chronous event aevl pin, /2, /4, or /8 can be selected as the input clock source. ecl can be cleared to h'00 when the crcl bit in eccsr is cleared to 0.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 223 of 516 rej09b0152-0300 13.4 operation 13.4.1 16-bit counter operation when bit ch2 is cleared to 0 in eccsr, ec h and ecl operate as a 16-bit event counter. any of four input clock sources? /2, /4, /8, or aevl pin input?can be selected by means of bits ackl1 and ackl0 in eccr. when aevl pin input is selected, input sensing is selected with bits alegs1 and alegs0. note that the input clock is enabled when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 13.2 shows the software procedur e when ech and ecl are used as a 16-bit event counter. clear ch2 to 0 set ackl1, ackl0, alegs1, and alegs0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 start end figure 13.2 software proc edure when using ech and ec l as 16-bit event counter as ch2 is cleared to 0 by a reset, ech and ecl operate as a 16-bit event counter after a reset, and as ackl1 and ackl0 are cleared to b 00, the operating clock is asynchronous event input from the aevl pin (using falling edge sensing). when the next clock is input after the count value reaches h'ff in both ech and ecl, ech and ecl overflow from h'ffff to h'0000, the ovh flag is set to 1 in eccsr, the ech and ecl count values each return to h'00, and counting up is restarted. when an overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 224 of 516 rej09b0152-0300 13.4.2 8-bit counter operation when bit ch2 is set to 1 in eccsr, ech and ecl operate as independent 8-bit event counters. /2, /4, /8, or aevh pin input can be selected as the input clock source for ech by means of bits ackh1 and ackh0 in eccr, and /2, /4, /8, or aevl pin input can be selected as the input clock source for ecl by means of bits ackl1 and ackl0 in eccr. input sensing is selected with bits ahegs1 and ahegs0 when aevh pin input is selected, and with bits alegs1 and alegs0 when aevl pin input is selected. note that the input clock is enabled when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 13.3 shows the software proced ure when ech and ecl are used as 8-bit event counters. set ch2 to 1 set ackh1, ackh0, ackl1, ackl0, ahegs1, ahegs0, alegs1, and alegs0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 start end figure 13.3 software proc edure when using ech and ec l as 8-bit event counters when the next clock is input after the ech count value reaches h'ff, ech overflows, the ovh flag is set to 1 in eccsr, the ech count value returns to h'00, and counting up is restarted. similarly, when the next clock is input after the ecl count value reaches h'ff, ecl overflows, the ovl flag is set to 1 in eccsr, the ecl count value returns to h'00, and counting up is restarted. when an overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 225 of 516 rej09b0152-0300 13.4.3 irqaec operation when the ecpwme bit in aegsr is 0, the ech and ecl input clocks are enabled when irqaec goes high. when irqaec goes low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled from outside by controlling irqaec. in this case, ech and ecl cannot be controlled individually. irqaec can also operate as an interrupt source. interrupt enabling is controlled by ienec2 in ienr1. when an irqaec interrupt is generated, interrupt request flag irrec2 in irr1 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge sensing can be selected for the irqaec input pin with bits aiegs1 and aiegs0 in aegsr. 13.4.4 event counter pwm operation when the ecpwme bit in aegsr is 1, the ech and ecl input clocks are enabled when event counter pwm output (iecpwm) is high. when iecpwm is low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled cyclically by controlling event counter pwm. in this case, ech and ecl cannot be controlled individually. iecpwm can also operate as an interrupt source. interrupt enabling is controlled by ienec2 in ienr1. when an iecpwm interrupt is generated, interrupt request flag irrec2 in irr1 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge detection can be se lected for iecpwm interr upt sensing with bits aiegs1 and aiegs0 in aegsr.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 226 of 516 rej09b0152-0300 figure 13.4 and table 13.2 show exam ples of event counter pwm operation. t off = t (n dr +1) t on t cm = t (n cm +1) t on : t off : t cm : t: n dr : n cm : clock input enable time clock input disable time one conversion period ecpwm input clock cycle value of ecpwdr value of ecpwcr figure 13.4 ev ent counter operation waveform note: ndr and ncm above must be set so that ndr < ncm. if the settings do not satisfy this condition, event counter pwm output (iecpwm) is fixed low. table 13.2 examples of event counter pwm operation conditions: f osc = 4 mhz, f = 4 mhz, f w = 32.768 khz, f w = 32.768 khz, high-speed active mode, ecpwcr value (ncm) = h'7a11, ecpwdr value (ndr) = h'16e3 clock source selection clock source cycle (t) * ecpwcr value (ncm) ecpwdr value (ndr) toff = t (ndr + 1) tcm = t (ncm + 1) ton = tcm ? toff /2 0.5 s 2.93 ms 15.625 ms 12.695 ms /4 1 s 5.86 ms 31.25 ms 25.39 ms /8 2 s 11.72 ms 62.5 ms 50.78 ms /16 4 s 23.44 ms 125.0 ms 101.56 ms /32 8 s 46.88 ms 250.0 ms 203.12 ms /64 16 s 93.76 ms 500.0 ms 406.24 ms w /16 488 s h'7a11 d'31249 h'16e3 d'5859 2861.59 ms 15260.19 ms 12398.60 ms note: * toff minimum width
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 227 of 516 rej09b0152-0300 13.4.5 operation of clock input enable/disable function the clock input to the event counter can be controlled by the irqaec pin when ecpwme in aegsr is 0, and by the event counter pwm output, iecpwm when ecpwme in aegsr is 1. as this function forcibly terminates the clock i nput by each signal, a maximum error of one count will occur depending on the irqaec or iecpwm timing. figure 13.5 shows an example of the operation. clock stopped n+2 n+3 n+4 n+5 n+6 nn+1 edge generated by clock return input event irqaec or iecpwm actually counted clock source counter value figure 13.5 example of clock control operation
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 228 of 516 rej09b0152-0300 13.5 operating states of asynchronous event counter the operating states of th e asynchronous event counter are shown in table 13.3. table 13.3 operating states of asynchronous event counter active sleep oscillation stabilization time counter clock source high- speed medium -speed high- speed medium- speed watch sub- active sub- sleep standby standby to active subsleep to active watch to active remarks aevh, aevl ech, ecl /2, /4, /8 * 1 w/16 pwm /2, /4, /8, /16, /32, /64 ` * 2 [legend] : counting enabled : counting disabled (counter value retained) notes: 1. the count-up function is enabled only when irqaec/iecpwm = 1. 2. output is in the high-impedance st ate during standby mode or the oscillation stabilization time from standby mode.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 229 of 516 rej09b0152-0300 13.6 usage notes 1. when reading the values in ech and ecl, first clear bits cueh and cuel to 0 in eccsr in 8-bit mode and clear bit cuel to 0 in 16-bit mode to prevent asynchronous event input to the counter. the correct value will not be returned if the event counter increments while being read. 2. for input to the aevh and aevl pins, use a clock with a frequency of up to 4.2 mhz within the range from 1.8 to 3.6 v and up to 10 mhz within the range from 2.7 to 3.6 v. for the high and low widths of the clock, see section 21, electrical characteristics. the duty cycle is arbitrary. table 13.4 maximum clock frequency mode maximum clock frequency input to aevh/aevl pin active (high-speed), sleep (high-speed) 4 to 10 mhz (2.7 to 3.6 v) 2 to 4.2 mhz (1.8 to 3.6 v) active (medium-speed), sleep (medium-speed) ( osc /8) ( osc /16) f osc = 4 mhz to 10 mhz (2.7 to 3.6 v) ( osc /32) f osc = 2 mhz to 4.2 mhz (1.8 to 3.6 v) ( osc /64) 2 f osc f osc 1/2 f osc 1/4 f osc watch, subactive, subsleep, standby ( w ) ( w /2) ( w /4) w = 32.768 khz or 38.4 khz ( w /8) 2000 khz 1000 khz 500 khz 250 khz 3. when aec uses with 16-bit mode, set cueh in eccsr to 1 first, set crch in eccsr to 1 second, or set both cueh and crch to 1 at same time before clock input. when aec is operating on 16-bit mode, do not change cueh. otherwise, ech will be miscounted up. 4. when ecpwme in aegsr is 1, the event counter pwm is operating and therefore ecpwcr and ecpwdr should not be modified. when changing the data, clear the ecpwme bit in aegsr to 0 (halt the event counter pwm) before modifying these registers. 5. the event counter pwm data register and even t counter pwm compare register must be set so that event counter pwm data register < event counter pwm compare register. if the settings do not satisfy this condition, do not set ecpwme to 1 in aegsr.
section 13 asynchronous event counter (aec) rev. 3.00 may 15, 2007 page 230 of 516 rej09b0152-0300 6. as synchronization is established internally when an irqaec interrupt is generated, a maximum error of 1 tcyc or 1tsubcyc will occur between clock halting and interrupt acceptance. 7. when pins in port 1 are used for aec input/output, the pfcr and pmr1 registers should be set in the following order. a. set the pfcr register. b. set bits 4 to 0 after bit 5 (irqaec bit) in the pmr1 register has been cleared to 0. c. set bit 5 (irqaec bit) in the pmr1 register to 1. at this time, bits 4 to 0 should not be changed and remain the same.
section 14 serial communicati on interface 3 (sci3, irda) sci0012a_000020020900 rev. 3.00 may 15, 2007 page 231 of 516 rej09b0152-0300 section 14 serial communica tion interface 3 (sci3, irda) the serial communication interface 3 (sci3) can handle both asynchronous and clock synchronous serial communication. in the async hronous method, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitte r (uart) or an asynchro nous communication interface adapter (acia). the sci3 can transmit and receive irda communi cation waveforms based on the infrared data association (irda) standard version 1.0. 14.1 features ? choice of asynchronous or clock synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected ? on-chip baud rate generator, internal clock, or external clock can be selected as a transfer clock source. ? six interrupt sources transmit-end, transmit-data-empty , receive-data-full, ove rrun error, framing error, and parity error. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the sci3 is halted as the initial va lue. for details, refer to section 5.4, module standby function.) asynchronous mode ? data length: 7, 8, or 5 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by readin g the rxd3 pin level directly in the case of a framing error
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 232 of 516 rej09b0152-0300 clock synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected note: when using serial commun ication interface 3, the system clock oscillator or subclock oscillator must be used. figure 14.1 shows a block diagram of the sci3. clock sck 3 brr3 tsr3 spcr ircr transmit/receive control circuit internal data bus [legend] rsr3: rdr3: tsr3: tdr3: smr3: scr3: ssr3: brr3: brc3: spcr: ircr: semr: receive shift register 3 receive data register 3 transmit shift register 3 transmit data register 3 serial mode register 3 serial control register 3 serial status register 3 bit rate register 3 bit rate counter 3 serial port control register irda control register serial extended mode register interrupt request (tei3, txi3, rxi3, eri3) internal clock ( /64, /16, w, ) external clock brc3 baud rate generator txd3 rxd3 smr3 scr3 ssr3 tdr3 rdr3 rsr3 semr figure 14.1 block diagram of sci3
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 233 of 518 rej09b0152-0300 14.2 input/output pins table 14.1 shows the pin configuration of the sci3. table 14.1 pin configuration pin name abbreviation i/o function sci3 clock sck3 i/o sc i3 clock input/output sci3 receive data input rxd3 input sci3 receive data input sci3 transmit data output txd3 output sci3 transmit data output 14.3 register descriptions the sci3 has the following registers for each channel. ? receive shift register 3 (rsr3)* ? receive data register 3 (rdr3)* ? transmit shift register 3 (tsr3)* ? transmit data register 3 (tdr3)* ? serial mode register 3 (smr3)* ? serial control register 3 (scr3)* ? serial status register 3 (ssr3)* ? bit rate register 3 (brr3)* ? serial port control register (spcr) ? irda control register (ircr) ? serial extended mode register (semr) note: * these register names are abbreviated to rsr, rdr, tsr, tdr, smr, scr, ssr, and brr in the text.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 234 of 516 rej09b0152-0300 14.3.1 receive shi ft register (rsr) rsr is a shift register that receives serial data input from the rxd3 pin and converts it into parallel data. when one byte of data has been r eceived, it is transferre d to rdr automatically. rsr cannot be directly accessed by the cpu. 14.3.2 receive data register (rdr) rdr is an 8-bit register that stores receive data . when the sci3 has received one byte of serial data, it transfers the received serial data from rsr to rdr, where it is stored. after this, rsr is receive-enabled. as rsr and rdr function as a d ouble buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00. rdr is initialized to h'00 by a reset or in standby mode, watch mode, or module standby mode. 14.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data fr om tdr to tsr automatically, then sends the data that starts from the lsb to the txd3 pin . data transfer from tdr to tsr is not performed if no data has been written to tdr (if the tdre bit in ssr is set to 1). tsr cannot be directly accessed by the cpu. 14.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sc i3 detects that tsr is empty, it transfers the tr ansmit data written in tdr to tsr and starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transm ission of one-frame data, the sci3 transfers the written data to tsr to continue transmission. to achieve reliable serial transmission, write transmit data to tdr only once after confirming th at the tdre bit in ssr is set to 1. tdr is initialized to h'ff. tdr is initialized to h'ff by a reset or in standby mode, watch mode, or module standby mode.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 235 of 518 rej09b0152-0300 14.3.5 serial mode register (smr) smr sets the sci3?s serial communication format and selects the clock source for the on-chip baud rate generator. smr is initialized to h'00 by a reset or in standby mode, watch mode, or module standby mode. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clock synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 or 5 bits as the data length. 1: selects 7 or 5 bits as the data length. when 7-bit data is selected. the msb (bit 7) in tdr is not transmitted. to select 5 bits as the data length, set 1 to both the pe and mp bits. the three most significant bits (bits 7, 6, and 5) in tdr are not transmitted. in clock synchronous mode, the data length is fixed to 8 bits regardless of the chr bit setting. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. in clock synchronous mode, parity bit addition and checking is not performed regardless of the pe bit setting.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 236 of 516 rej09b0152-0300 bit bit name initial value r/w description 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. when even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number, in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. when odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number, in reception, a check is carried out to confirm that the number of 1bits in the receive data plus the parity bit is an odd number. if parity bit addition and checking is disabled in clock synchronous mode and asynchronous mode, the pm bit setting is invalid. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w 5-bit communication when this bit is set to 1, the 5-bit communication format is enabled. make sure to set bit 5 (pf) to 1 when setting this bit (mp) to 1.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 237 of 518 rej09b0152-0300 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: w clock (n = 0) 10: /16 clock (n = 2) 11: /64 clock (n = 3) when the setting value is 01 in subactive mode or subsleep mode, the sci3 can be used only when w is selected for the cpu operating clock. for the relationship between the bit rate register setting and the baud rate, see section 14.3.8, bit rate register (brr). n is the decimal repres entation of the value of n in brr (see section 14.3.8, bit rate register (brr)). 14.3.6 serial control register (scr) scr enables or disables sci3 tran sfer operations and interrupt re quests, and selects the transfer clock source. for details on interrupt requests, refer to section 14.7, interrupt requests. scr is initialized to h'00 by a reset or in standby mode, watch mode, or module standby mode. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi3 interrupt request is enabled. txi3 can be released by clearing the tdre it or ti bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, the rxi3 and eri3 interrupt requests are enabled. rxi3 and eri3 can be released by clearing the rdrf bit or the fer, per, or oer error flag to 0, or by clearing the rie bit to 0.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 238 of 516 rej09b0152-0300 bit bit name initial value r/w description 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. when this bit is 0, the tdre bit in ssr is fixed at 1. when transmit data is written to t dr while this bit is 1, bit tdre in ssr is cleared to 0 and serial data transmission is started. be sure to carry out smr settings, and setting of bit spc3 in spcr, to decide the transmission format before setting bit te to 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. in this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in clock synchronous mode. be sure to carry out the smr settings to decide the reception format before setting bit re to 1. note that the rdrf, fer, per, and oer flags in ssr are not affected when bit re is cleared to 0, and retain their previous state 3 mpie 0 r/w reserved 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, the tei3 interrupt request is enabled. tei3 can be released by clearing bit tdre to 0 and clearing bit tend to 0 in ssr, or by clearing bit teie to 0.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 239 of 518 rej09b0152-0300 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 select the clock source. asynchronous mode: 00: internal baud rate generator (sck3 pin functions as an i/o port) 01: internal baud rate generat or (outputs a clock of the same frequency as the bit rate from the sck3 pin) 10: external clock (inputs a clock with a frequency 16 times the bit rate from the sck3 pin) 11: reserved clock synchronous mode: 00: internal clock (sck3 pin functions as clock output) 01: reserved 10: external clock (sck3 pin functions as clock input) 11: reserved
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 240 of 516 rej09b0152-0300 14.3.7 serial status register (ssr) ssr consists of status flags of the sci3. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. ssr is initialized to h'84 by a reset or in standby mode, watch mode, or module standby mode. bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates that transmit data is stored in tdr. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 6 rdrf 0 r/(w) * receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 when data is read from rdr if an error is detected in reception, or if the re bit in scr has been cleared to 0, rdr and bit rdrf are not affected and retain their previous state. note that if data reception is completed while bit rdrf is still set to 1, an overrun error (oer) will occur and the receive data will be lost.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 241 of 518 rej09b0152-0300 bit bit name initial value r/w description 5 oer 0 r/(w) * overrun error [setting condition] ? when an overrun error occurs in reception [clearing condition] ? when 0 is written to oer after reading oer = 1 when bit re in scr is cleared to 0, bit oer is not affected and retains its previous state. when an overrun error occurs, rdr retains the receive data it held before the overrun error occurred, and data received after the error is lost. reception cannot be continued with bit oer set to 1, and in clock synchronous mode, transmission cannot be continued either. 4 fer 0 r/(w) * framing error [setting condition] ? when a framing error occurs in reception [clearing condition] ? when 0 is written to fer after reading fer = 1 when bit re in scr is cleared to 0, bit fer is not affected and retains its previous state. note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. when a framing error occurs, the receive data is transferred to rdr but bit rdrf is not set. reception cannot be continued with bit fer set to 1. in clock synchronous mode, neither transmission nor reception is possible when bit fer is set to 1.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 242 of 516 rej09b0152-0300 bit bit name initial value r/w description 3 per 0 r/(w) * parity error [setting condition] ? when a parity error is generated during reception [clearing condition] ? when 0 is written to per after reading per = 1 when bit re in scr is cleared to 0, bit per is not affected and retains its previous state. ? receive data in which a parity error has occurred is still transferred to rdr, but bit rdrf is not set. reception cannot be continued with bit per set to 1. in clock synchronous mode, neither transmission nor reception is possible when bit per is set to 1. 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 1 mpbr 0 r reserved this bit is always read as 0 and cannot be modified. 0 mpbt 0 r/w reserved the write value should always be 0. note: * only 0 can be written to clear the flag.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 243 of 518 rej09b0152-0300 14.3.8 bit rate register (brr) brr is an 8-bit readable/writable register that adjusts the bit rate. brr is initialized to h'ff. tables 14.2 and 14.3 show the relationship between the n setting in brr and the n setting in bits cks1 and cks0 in smr in asynchronous mode. table 14.5 shows the maximum bit rate for each frequency in asynchronous mode. the values shown in these tables are values in active (high- speed) mode. when the abcs bit in semr is set to 1 in asynchronous mode, the maximum bit rate in table 14.5 is doubled. table 14.6 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 in smr in clock synchronous mode. the values shown in table 14.6 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode and abcs bit is 0] n = 32 2 2n b ? 1 error (%) = 100 b (bit rate obtained from n, n, ) ? r (bit rate in left-hand column in table 14.2) r (bit rate in left-hand column in table 14.2) [asynchronous mode and abcs bit is 1] n = 16 2 2n b ? 1 error (%) = 100 b (bit rate obtained from n, n, ) ? r (bit rate in left-hand column in table 14.3) r (bit rate in left-hand column in table 14.3) [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 14.4)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 244 of 516 rej09b0152-0300 table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (1) 32.8 khz 38.4 khz 2 mhz 2.097152 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 ? ? ? 0 10 ? 0.83 2 35 ? 1.36 2 36 0.64 150 0 6 ? 2.38 0 7 0.00 2 25 0.16 2 26 1.14 200 0 4 2.50 0 5 0.00 2 19 ? 2.34 2 19 2.40 250 0 3 2.50 ? ? ? 0 249 0.00 2 15 2.40 300 ? ? ? 0 3 0.00 0 207 0.16 0 217 0.21 600 ? ? ? 0 1 0.00 0 103 0.16 0 108 0.21 1200 ? ? ? 0 0 0.00 0 51 0.16 0 54 ?0.70 2400 ? ? ? ? ? ? 0 25 0.16 0 26 1.14 4800 ? ? ? ? ? ? 0 12 0.16 0 13 ?2.48 9600 ? ? ? ? ? ? ? ? ? 0 6 ?2.48 19200 ? ? ? ? ? ? ? ? ? ? ? ? 31250 ? ? ? ? ? ? 0 1 0.00 ? ? ? 38400 ? ? ? ? ? ? ? ? ? ? ? ? table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (2) 2.4576 mhz 3 mhz 3.6864 mhz 4 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 43 ?0.83 2 52 0.50 2 64 0.70 2 70 0.03 150 2 31 0.00 2 38 0.16 2 47 0.00 2 51 0.16 200 2 23 0.00 2 28 1.02 2 35 0.00 2 38 0.16 250 2 18 1.05 2 22 1.90 2 28 ?0.69 2 30 0.81 300 0 255 0.00 2 19 ?2.34 2 23 0.00 2 25 0.16 600 0 127 0.00 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 63 0.00 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 31 0.00 0 38 0.16 0 47 0.00 0 51 0.16 4800 0 15 0.00 0 19 ?2.34 0 23 0.00 0 25 0.16 9600 0 7 0.00 0 9 ?2.34 0 11 0.00 0 12 0.16 19200 0 3 0.00 0 4 ?2.34 0 5 0.00 ? ? ? 31250 ? ? ? 0 2 0.00 ? ? ? 0 3 0.00 38400 0 1 0.00 ? ? ? 0 2 0.00 ? ? ?
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 245 of 518 rej09b0152-0300 table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (3) 4.194304 mhz 4.9152 mhz 5 mhz 6 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 73 0.64 2 86 0.31 2 88 ?0.25 2 106 ?0.44 150 2 54 ?0.70 2 63 0.00 2 64 0.16 2 77 0.16 200 2 40 ?0.10 2 47 0.00 2 48 ?0.35 2 58 ?0.69 250 2 32 ?0.70 2 37 1.05 2 38 0.16 2 46 -0.27 300 2 26 1.14 2 31 0.00 2 32 ?1.36 2 38 0.16 600 0 217 0.21 0 255 0.00 2 15 1.73 2 19 ?2.34 1200 0 108 0.21 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 54 ?0.70 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 26 1.14 0 31 0.00 0 32 ?1.36 0 38 0.16 9600 0 13 ?2.48 0 15 0.00 0 15 1.73 0 19 ?2.34 19200 0 6 ?2.48 0 7 0.00 0 7 1.73 0 9 ?2.34 31250 ? ? ? 0 4 ?1.70 0 4 0.00 0 5 0.00 38400 ? ? ? 0 3 0.00 0 3 1.73 0 4 ?2.34 table 14.2 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 0) (4) 6.144 mhz 7.3728 mhz 8 mhz 9.8304 mhz 10 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 108 0.08 2 130 ?0.07 2 141 0.03 2 174 ?0.26 2 177 ?0.25 150 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 200 2 59 0.00 2 71 0.00 2 77 0.16 2 95 0.00 2 97 ?0.35 250 2 47 0.00 2 57 ?0.69 2 62 -0.79 2 76 -0.26 2 77 0.16 300 2 39 0.00 2 47 0.00 2 51 0.16 2 63 0.00 2 64 0.16 600 2 19 0.00 2 23 0.00 2 25 0.16 2 31 0.00 2 32 ?1.36 1200 0 159 0.00 0 191 0.00 0 207 0.16 0 255 0.00 2 15 1.73 2400 0 79 0.00 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 4800 0 39 0.00 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 9600 0 19 0.00 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 19200 0 9 0.00 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 31250 0 5 2.40 ? ? ? 0 7 0.00 0 9 ?1.70 0 9 0.00 38400 0 4 0.00 0 5 0.00 ? ? ? 0 7 0.00 0 7 1.73
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 246 of 516 rej09b0152-0300 table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (1) 32.8 khz 38.4 khz 2 mhz 2.097152 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 0 18 ?1.91 0 21 -0.83 2 70 0.03 2 73 0.64 150 0 13 ?2.38 0 15 0.00 2 51 0.16 2 54 ?0.70 200 0 9 2.50 0 11 0.00 2 38 0.16 2 40 ?0.10 250 0 7 2.50 ? ? ? 2 30 0.81 2 32 ?0.70 300 0 6 ?2.38 0 7 0.00 2 25 0.16 2 26 1.14 600 ? ? ? 0 3 0.00 0 207 0.16 0 217 0.21 1200 ? ? ? 0 1 0.00 0 103 0.16 0 108 0.21 2400 ? ? ? 0 0 0.00 0 51 0.16 0 54 -0.70 4800 ? ? ? ? ? ? 0 25 0.16 0 26 1.14 9600 ? ? ? ? ? ? 0 12 0.16 0 13 ?2.48 19200 ? ? ? ? ? ? ? ? ? 0 6 ?2.48 31250 ? ? ? ? ? ? 0 3 0.00 ? ? ? 38400 ? ? ? ? ? ? ? ? ? ? ? ? table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (2) 2.4576 mhz 3 mhz 3.6864 mhz 4 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 86 0.31 2 106 ?0.44 2 130 -0.07 2 141 0.03 150 2 63 0.00 2 77 0.16 2 95 0.00 2 103 0.16 200 2 47 0.00 2 58 ?0.69 2 71 0.00 2 77 0.16 250 2 37 1.05 2 46 ?0.27 2 57 -0.69 2 62 ?0.79 300 2 31 0.00 2 38 0.16 2 47 0.00 2 51 0.16 600 0 255 0.00 2 19 ?2.34 2 23 0.00 2 25 0.16 1200 0 127 0.00 0 155 0.16 0 191 0.00 0 207 0.16 2400 0 63 0.00 0 77 0.16 0 95 0.00 0 103 0.16 4800 0 31 0.00 0 38 0.16 0 47 0.00 0 51 0.16 9600 0 15 0.00 0 19 ?2.34 0 23 0.00 0 25 0.16 19200 0 7 0.00 0 9 ?2.34 0 11 0.00 0 12 0.16 31250 0 4 ?1.70 0 5 0.00 ? ? ? 0 7 0.00 38400 0 3 0.00 0 4 ?2.34 0 5 0.00 ? ? ?
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 247 of 518 rej09b0152-0300 table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (3) 4.194304 mhz 4.9152 mhz 5 mhz 6 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 148 ?0.04 2 174 ?0.26 2 177 ?0.25 2 212 0.03 150 2 108 0.21 2 127 0.00 2 129 0.16 2 155 0.16 200 2 81 ?0.10 2 95 0.00 2 97 ?0.35 2 116 0.16 250 2 65 ?0.70 2 76 ?0.26 2 77 0.16 2 93 ?0.27 300 2 54 ?0.70 2 63 0.00 2 64 0.16 2 77 0.16 600 2 26 1.14 2 31 0.00 2 32 ?1.36 2 38 0.16 1200 0 217 0.21 0 255 0.00 2 15 1.73 2 19 ?2.34 2400 0 108 0.21 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 54 ?0.70 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 26 1.14 0 31 0.00 0 32 ?1.36 0 38 0.16 19200 0 13 ?2.48 0 15 0.00 0 15 1.73 0 19 ?2.34 31250 ? ? ? 0 9 ?1.70 0 9 0.00 0 11 0.00 38400 0 6 -2.48 0 7 0.00 0 7 1.73 0 9 ?2.34 table 14.3 examples of brr settings for various bit rates (asynchronous mode and abcs bit is 1) (4) 6.144 mhz 7.3728 mhz 8 mhz 9.8304 mhz 10 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?0.25 150 2 159 0.00 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 200 2 119 0.00 2 143 0.00 2 155 0.16 2 191 0.00 2 194 0.16 250 2 95 0.00 2 114 0.17 2 124 0.00 2 153 -0.26 2 155 0.16 300 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 2 39 0.00 2 47 0.00 2 51 0.16 2 63 0.00 2 64 0.16 1200 2 19 0.00 2 23 0.00 2 25 0.16 2 31 0.00 2 32 ?1.36 2400 0 159 0.00 0 191 0.00 0 207 0.16 0 255 0.00 2 15 1.73 4800 0 79 0.00 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 39 0.00 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 19 0.00 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 31250 0 11 2.40 0 14 ?1.70 0 15 0.00 0 19 ?1.70 0 19 0.00 38400 0 9 0.00 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 248 of 516 rej09b0152-0300 table 14.4 relation between n and clock smr setting n clock cks1 cks0 0 0 0 0 w * 0 1 2 /16 1 0 3 /64 1 1 note: * in subactive or subsleep mode, the sci3 can be operated only when the cpu operating clock is w . table 14.5 maximum bit rate for ea ch frequency (asynchronous mode) maximum bit rate (bit/s) setting (mhz) abcs = 0 abcs = 1 n n 0.0328 * 1025 2050 0 0 0.0384 * 1200 2400 0 0 2 62500 125000 0 0 2.097152 65536 131072 0 0 2.4576 76800 153600 0 0 3 93750 187500 0 0 3.6864 115200 230400 0 0 4 125000 250000 0 0 4.194304 131072 262144 0 0 4.9152 153600 307200 0 0 5 156250 312500 0 0 6 187500 375000 0 0 6.144 192000 384000 0 0 7.3728 230400 460800 0 0 8 250000 500000 0 0 9.8304 307200 614400 0 0 10 312500 625000 0 0 note: * when cks1 = 0 and cks0 = 1 in smr
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 249 of 518 rej09b0152-0300 table 14.6 brr settings for various bi t rates (clock synchronous mode) (1) 32.8 khz 38.4 khz 2 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 200 0 40 0.00 0 47 0.00 2 155 0.16 250 0 32 ? 0.61 0 37 1.05 2 124 0.00 300 0 26 1.23 0 31 0.00 2 103 0.16 500 0 15 2.50 0 18 1.05 2 62 ? 0.79 1k 0 7 2.50 ? ? ? 2 30 0.81 2.5k ? ? ? ? ? ? 0 199 0.00 5k ? ? ? ? ? ? 0 99 0.00 10k ? ? ? ? ? ? 0 49 0.00 25k ? ? ? ? ? ? 0 19 0.00 50k ? ? ? ? ? ? 0 9 0.00 100k ? ? ? ? ? ? 0 4 0.00 250k ? ? ? ? ? ? 0 1 0.00 500k ? ? ? ? ? ? 0 * 0 * 0.00 * 1m ? ? ? ? ? ? ? ? ? note: * continuous transmission/reception is not possible.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 250 of 516 rej09b0152-0300 table 14.6 brr settings for various bi t rates (clock synchronous mode) (2) 4 mhz 8 mhz 10 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 200 3 77 0.16 3 155 0.16 3 194 0.16 250 2 249 0.00 3 124 0.00 3 155 0.16 300 2 207 0.16 3 103 0.16 3 129 0.16 500 2 124 0.00 2 249 0.00 3 77 0.16 1k 2 62 ? 0.79 2 124 0.00 2 155 0.16 2.5k 2 24 0.00 2 49 0.00 2 62 ? 0.79 5k 0 199 0.00 2 24 0.00 2 30 0.81 10k 0 99 0.00 0 199 0.00 0 249 0.00 25k 0 39 0.00 0 79 0.00 0 99 0.00 50k 0 19 0.00 0 39 0.00 0 49 0.00 100k 0 9 0.00 0 19 0.00 0 24 0.00 250k 0 3 0.00 0 7 0.00 0 9 0.00 500k 0 1 0.00 0 3 0.00 0 4 0.00 1m 0 * 0 * 0.00 * 0 1 0.00 ? ? ? note: * continuous transmission/reception is not possible. the value set in brr is given by the following formula: n = 4 2 2n b ? 1 b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 14.7.) table 14.7 relation between n and clock smr setting n clock cks1 cks0 0 0 0 0 w * 0 1 2 /16 1 0 3 /64 1 1 note: * in subactive or subsleep mode, the sci3 can be operated only when the cpu operating clock is w .
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 251 of 518 rej09b0152-0300 14.3.9 serial port control register (spcr) spcr selects the function of the txd3 (irtxd) pin and whether to invert the input/output data of the rxd3 (irrxd) and txd3 (irtxd) pins. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 4 spc3 0 r/w p32/txd3/irtxd pin function switch selects whether pin p32/txd3/irtxd is used as p32 or as txd3/irtxd. 0: p32 i/o pin 1: txd3/irtxd output pin set the te bit in scr after setting this bit to 1. 3, 2 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 1 scinv1 0 r/w txd3/irtxd pin ou tput data inversion switch selects whether output data of the txd3/irtxd pin is inverted or not. 0: output data of txd3/irtxd pin is not inverted. 1: output data of txd3/irtxd pin is inverted. 0 scinv0 0 r/w rxd3/irrxd pin input data inversion switch selects whether input data of the rxd3/irrxd pin is inverted or not. 0: input data of rxd3/irrxd pin is not inverted. 1: input data of rxd3/irrxd pin is inverted. note: when the serial port control register is m odified, the data being input or output up to that point is inverted immediately after the modifi cation, and an invalid data change is input or output. when modifying the serial port control r egister, modification must be made in a state in which data changes are invalidated.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 252 of 516 rej09b0152-0300 14.3.10 irda control register (ircr) ircr controls the irda operation of the sci3. bit bit name initial value r/w description 7 ire 0 r/w irda enable selects whether the sci3 i/o pins function as the sci3 or irda. 0: txd3/irtxd and rxd3/irrxd pins function as txd3 and rxd3 1: txd3/irtxd and rxd3/irrxd pins function as irtxd and irrxd 6 5 4 ircks2 ircks1 ircks0 0 0 0 r/w r/w r/w irda clock select if the irda function is enabled, these bits set the high- pulse width when encoding the irtxd output pulse. 000: bit rate 3/16 001: /2 010: /4 011: /8 100: /16 101: setting prohibited 11x: setting prohibited 3 to 0 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. [legend] x: don?t care.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 253 of 518 rej09b0152-0300 14.3.11 serial extended mode register (semr) semr sets the basic clock used in asynchronous mode. bit bit name initial value r/w description 7 to 4 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 3 abcs 0 r/w asynchronous mode basic clock select selects the basic clock for the bit period in asynchronous mode. this setting is enabled only in asynchronous mode (com bit in smr3 is 0). 0: operates on a basic clock with a frequency of 16 times the transfer rate 1: operates on a basic cl ock with a frequency of eight times the transfer rate clear the abcs bit to 0, when the irda function is enabled. 2 to 0 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 14.4 operation in asynchronous mode figure 14.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous mode, synchronization is performed at the falling edge of the start bit during reception. the data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transf er data is latched at the center of each bit. when the abcs bit in semr is 1, the data is sampled on the 4th pulse of a clock with a frequency eight times the bit period. inside the sc i3, the transmitter and receiver are independent units, enabling full duplex. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during tr ansmission or reception, enabling continuous data transfer. table 14.8 show s the 16 data transfer formats that can be set in asynchronous mode. the format is selected by the settings in smr as shown in table 14.9.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 254 of 516 rej09b0152-0300 lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 5, 7, or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 14.2 data format in asynchronous communication 14.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck3 pin can be selected as the sci3?s serial clock source, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr. when an external clock is input at the sck3 pin, the clock frequency should be 16 times the bit rate used (when the abcs bit in semr is 1, the clock frequency should be eight times the bit rate used). for details on selection of the clock source, see table 14.10. when the sci3 is op erated on an internal clock, the clock can be output from the sck3 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of th e clock is in the middle of the transfer data, as shown in figure 14.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 14.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 255 of 518 rej09b0152-0300 table 14.8 data transfer formats (asynchronous mode) 1 start start start start start start start start 2345 8-bit data 8-bit data setting prohibited setting prohibited setting prohibited setting prohibited 5-bit data 5-bit data 7-bit data 7-bit data 7-bit data 7-bit data 6789 stop stop 10 stop stop 11 stop stop stop stop p stop p stop stop 12 stop smr chr pe mp stop 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 start start 8-bit data 8-bit data p stop p stop stop start start 5-bit data stop p pstop stop serial data transfer format and frame length [legend] start: start bit stop: stop bit p: parity bit 5-bit data
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 256 of 516 rej09b0152-0300 table 14.9 smr settings and corres ponding data transfer formats smr data transfer format bit 7 bit 6 bit 2 bit 5 bit 3 com chr mp pe stop mode data length parity bit stop bit length 0 1 bit 0 1 no 2 bits 0 1 bit 0 1 1 8-bit data yes 2 bits 0 1 bit 0 1 no 2 bits 0 1 bit 1 0 1 1 7-bit data yes 2 bits 0 0 1 setting prohibited 0 1 bit 0 1 1 5-bit data no 2 bits 0 0 1 setting prohibited 0 1 bit 0 1 1 1 1 asynchronous mode 5-bit data yes 2 bits 1 x 0 x x clock synchronous mode 8-bit data no no [legend] x: don?t care.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 257 of 518 rej09b0152-0300 table 14.10 smr and scr setting s and clock source selection smr scr bit 7 bit 1 bit 0 tr ansmit/receive clock com cke1 cke0 mode clock source sck pin function 0 i/o port (sck3 pin not used) 0 1 internal outputs a clock with the same frequency as the bit rate 0 1 0 asynchronous mode external inputs a clock with a frequency 16 times the bit rate * 0 0 internal outputs the serial clock 1 1 0 clock synchronous mode external inputs the serial clock 0 1 1 1 0 1 1 1 1 reserved (do not specify these combinations) note: * when the abcs bit in semr is 1, inputs a clock with a frequency eight times the bit rate.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 258 of 516 rej09b0152-0300 14.4.2 sci3 initialization follow the flowchart as shown in figure 14.4 to initialize the sci3. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied ev en during initialization. when the external clock is used in clock synchronous mode, the clock must not be supplied during initialization. wait start initialization set data transfer format in smr [1] set cke1 and cke0 bits in scr3 no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie and teie bits. set spc3 bit in spcr to 1 [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock output is selected in asynchronous mode, clock is output immediately after cke1 and cke0 settings are made. when the clock output is selected at reception in clock synchronous mode, clock is output immediately after cke1, cke0, and re are set to 1. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. setting bits te and re enables the txd3 and rxd3 pins to be used. also set the rie, tie, and teie bits, depending on whether interrupts are required. in asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. figure 14.4 sample sci3 initialization flowchart
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 259 of 518 rej09b0152-0300 14.4.3 data transmission figure 14.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if the flag is cleared to 0, th e sci3 recognizes that data has been written to tdr, and tr ansfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a txi3 interrupt request is generated. continuous transmission is possible because the txi3 interr upt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. 6. figure 14.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mar k state 1 frame 0 1d0d1d70/11 11 0d0d1 d70/1 serial data tdre tend lsi operation txi3 interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi3 interrupt request generated tei3 interrupt request generated figure 14.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 260 of 516 rej09b0152-0300 no yes start transmission read tdre flag in ssr set spc3 bit in spcr to 1 [1] write transmit data to tdr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear spc3 bit in spcr and te bit in scr to 0 * tdre = 1 all data transmitted? tend = 1 break output? [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. (after the te bit is set to 1, one frame of 1 is output, then transmission is possible.) [2] to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [3] to output a break in serial transmission, after setting pcr to 1 and pdr to 0, clear the spc3 bit in spcr and the te bit in scr to 0. note: * when the spc3 bit in spcr is cleared to 0, the pin functions as an i/o port. figure 14.6 sample serial transmission flowchart (asynchronous mode)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 261 of 518 rej09b0152-0300 14.4.4 serial data reception figure 14.7 shows an example of operation for reception in asynchronous mode. in serial reception, the sci3 operat es as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives data in rsr, and checks the parity bit and stop bit. ? parity check the sci3 checks that the number of 1 bits in the receive data co nforms to the parity (odd or even) set in bit pm in the se rial mode register (smr). ? stop bit check the sci3 checks that the stop bit is 1. if two stop bits are used, only the first is checked. ? status check the sci3 checks that bit rdrf is set to 0, i ndicating that the receive data can be transferred from rsr to rdr. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri3 interrupt request is generated. r eceive data is not transferred to rdr. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri3 interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri3 interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi3 interrupt request is generated. continuous receptio n is possible because the rxi3 interrupt routine reads the receive data transferred to rdr before reception of the next receive data has been completed.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 262 of 516 rej09b0152-0300 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1 d0 d1 d7 0/1 1 0 1 0 d0 d1 d7 0/1 serial data rdrf fer lsi operation user processing rdrf flag cleared to 0 rdr data read framing error processing rxi3 interrupt request generated 0 stop bit detected eri request in response to framing error figure 14.7 example sci3 operation in reception in asynchronous mode (8-bit data, parity, one stop bit) table 14.11 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains it s state before receiving data. reception cannot be resumed while a receive error flag is se t to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 14.8 shows a sample flowchart for serial data reception. table 14.11 ssr status flag s and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had befor e data reception. however, note that if rdr is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, the rdrf flag will be cleared to 0.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 263 of 518 rej09b0152-0300 yes no start reception [1] no yes read rdrf flag in ssr [2] [3] clear re bit in scr to 0 read oer, per, and fer flags in ssr error processing (continued on next page) [4] read receive data in rdr yes no oer+per+fer = 1 rdrf = 1 all data received? [1] read the oer, per, and fer flags in ssr to identify the error. if a receive error occurs, performs the appropriate error processing. [2] read ssr and check that rdrf = 1, then read the receive data in rdr. the rdrf flag is cleared automatically. [3] to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag and read rdr. the rdrf flag is cleared automatically. [4] if a receive error occurs, read the oer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd3 pin. (a) figure 14.8 sample seri al data reception flowchar t (asynchronous mode) (1)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 264 of 516 rej09b0152-0300 (a) error processing parity error processing yes no clear oer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing oer = 1 fer = 1 break? per = 1 [4] figure 14.8 sample seri al data reception flowchar t (asynchronous mode) (2)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 265 of 518 rej09b0152-0300 14.5 operation in clock synchronous mode figure 14.9 shows the general format for clock synchronous communication. in clock synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data co nsists of the 8-bit data star ting from the lsb. in clock synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clock synchronous mo de, the sci3 receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clock synchronous mode, no parity bit is added. inside the sci3, the transmitter and receiver are independent units, en abling full-duplex communication through the use of a common clock. both the transmitter and the receiver also ha ve a double-buffered stru cture, so data can be read or written during transmission or reception, enabling cont inuous data transfer. don?t care don?t care one unit of transfer data (character or frame) 8-bit bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 14.9 data format in clock synchronous communication 14.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck3 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr. when the sci3 is operated on an internal clock, the serial clock is output from the sck3 pin. eight serial clock pulses are output in the transfer of one character, and when no tr ansfer is performed the clock is fixed high. 14.5.2 sci3 initialization before transmitting and receiving data, the sci3 sh ould be initialized as described in a sample flowchart in figure 14.4.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 266 of 516 rej09b0152-0300 14.5.3 serial data transmission figure 14.10 shows an example of sci3 operation for transmission in clock synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sci3 recognizes that data has been written to tdr, and transf ers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts tr ansmission. if the tie bit in scr is set to 1 at this time, a txi3 interrupt request is generated. 3. 8-bit data is sent from the txd3 pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd3 pin. 4. the sci3 checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr is set to 1 at this time, a tei3 interrupt request is generated. 7. the sck3 pin is fixed high. figure 14.11 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a r eceive error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before st arting transmission. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi3 interrupt request generated data written to tdr tdre flag cleared to 0 txi3 interrupt request generated tei3 interrupt request generated figure 14.10 example of sc i3 operation in transmission in clock synchronous mode
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 267 of 518 rej09b0152-0300 no yes start transmission read tdre flag in ssr set spc3 bit in spcr to 1 [1] write transmit data to tdr no yes no yes read tend flag in ssr [2] clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when clock output is selected and data is written to tdr, clocks are output to start the data transmission. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. figure 14.11 sample serial transmission flowchart (clock synchronous mode)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 268 of 516 rej09b0152-0300 14.5.4 serial data reception (clock synchronous mode) figure 14.12 shows an example of sci3 operation for reception in clock synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. the sci3 stores the received data in rsr. 3. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri3 interrupt request is generated, r eceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi3 interrupt request is generated. bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 serial data rdrf oer lsi operation rxi3 interrupt request generated rxi3 interrupt request generated eri3 interrupt request generated by overrun error overrun error processing rdrf flag cleared to 0 rdr data read rdr data has not been read (rdrf = 1) user processing serial clock 1 frame 1 frame figure 14.12 example of sci3 reception operation in clock synchronous mode reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming r eception. figure 14.13 shows a sample flowchart for serial data reception.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 269 of 518 rej09b0152-0300 yes no start reception [1] [4] no yes read rdrf flag in ssr [2] [3] clear re bit in scr to 0 overrun error processing (continued below) read receive data in rdr yes no oer = 1? rdrf = 1? data reception continued? read oer flag in ssr start overrun error processing overrun error processing clear oer flag in ssr to 0 [4] [1] read the oer flag in ssr to determine if there is an error. if an overrun error has occurred, execute overrun error processing. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial reception, before the msb (bit 7) of the current frame is received, reading the rdrf flag and reading rdr should be finished. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. reception cannot be resumed if the oer flag is set to 1. figure 14.13 sample serial reception flowchart (clock synchronous mode)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 270 of 516 rej09b0152-0300 14.5.5 simultaneous serial da ta transmission and reception figure 14.14 shows a samp le flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous seri al data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode , after checking that the sci3 has finished reception, clear re to 0. then after checking th at the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction. yes no start transmission/reception [3] overrun error processing [4] read receive data in rdr yes no oer = 1 data transmission/reception continued? [1] read tdre flag in ssr set spc3 bit in spcr to 1 no yes tdre = 1 write transmit data to tdr no yes rdrf = 1 read oer flag in ssr [2] read rdrf flag in ssr clear te and re bits in scr to 0 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. transmission/reception cannot be resumed if the oer flag is set to 1. for overrun error processing, see figure 14.13. figure 14.14 sample flowchart of simultaneo us serial transmit and receive operations (clock synchronous mode)
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 271 of 518 rej09b0152-0300 14.6 irda operation irda operation can be used with the sci3. figure 14.15 shows an irda block diagram. if the irda function is enabled using the ire bit in ircr, the txd3 and rxd3 pins in the sci3 are allowed to encode and decode the waveform based on the irda standard version 1.0 (function as the irtxd and irrxd pins). connecting these pi ns to the infrared data transceiver/receiver achieves infrared data communication based on the system defined by the irda standard version 1.0. in the system defined by the irda standard version 1.0, communicatio n is started at a transfer rate of 9600 bps, which can be modified as required. the irda interface provided by this lsi does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming. irda sci3 ircr txd3/irtxd rxd3/irrxd txd rxd pulse encoder phase inversion phase inversion pulse decoder figure 14.15 irda block diagram
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 272 of 516 rej09b0152-0300 14.6.1 transmission during transmission, the output signals from the sci3 (uart frames) are converted to ir frames using the irda interface (see figure 14.16). for serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). the high-level pulse can be selected using the ircks2 to ircks0 bits in ircr. according to the standard, the high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) bit rate or (3/16 bit rate) +1.08 s at maximum. for example, when the frequency of system clock is 10 mhz, being equal to or greater than 1.41 s, the high-level pulse width at minimum can be specified as 1.6 s. for serial data of level 1, no pulses are output. uart frame data ir frame data 0000 0 11 11 1 0000 0 11 11 1 transmission reception bit cycle pulse width is 1.6 s to 3/16 bit cycle start bit stop bit stop bit start bit figure 14.16 irda transmission and reception
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 273 of 518 rej09b0152-0300 14.6.2 reception during reception, ir frames ar e converted to uart frames us ing the irda interface before inputting to the sci3. data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. if a pul se has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is recognized as level 0. 14.6.3 high-level pu lse width selection table 14.12 shows possible settings for bits ircks2 to ircks0 (minimum pulse width), and this lsi's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. table 14.12 ircks2 to ircks0 bit settings operating bit rate (bps) (u pper row) / bit interval 3/16 (s) (lower row) frequency 2400 9600 19200 38400 (mhz) 78.13 19.53 9.77 4.88 2 010 010 010 010 2.097152 010 010 010 010 2.4576 010 010 010 010 3 011 011 011 011 3.6864 011 011 011 011 4.9152 011 011 011 011 5 011 011 011 011 6 100 100 100 100 6.144 100 100 100 100 7.3728 100 100 100 100 8 100 100 100 100 9.8304 100 100 100 100 10 100 100 100 100
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 274 of 516 rej09b0152-0300 14.7 interrupt requests the sci3 creates the following si x interrupt requests: transmit end, transmit data empty, receive data full, and receive errors (ove rrun error, framing error, and pa rity error). tabl e 14.13 shows the interrupt sources. table 14.13 sci3 interrupt requests interrupt requests abbreviation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr each interrupt request can be enabled or disabled by means of bits tie and rie in scr. when the tdre bit in ssr is set to 1, a txi3 interrupt is requested. when the tend bit in ssr is set to 1, a tei3 interrupt is requested. thes e two interrupts are generated during transmission. the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr is set to 1 before transferring the transmit data to tdr, a txi3 interrupt request is generated even if the transmit data is not ready. the initial value of the tend fl ag in ssr is 1. thus, when the teie bit in scr is set to 1 before transferring the transmit data to tdr, a tei3 interrupt request is generated even if the transmit data has not been sent. it is possible to make use of the most of these interrupt requests efficiently by transferring the transmit da ta to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi3 an d tei3), clear the enable bits (tie and teie) that correspond to these interrupt requests to 0, after transferring the transmit data to tdr. when the rdrf bit in ssr is set to 1, an rxi3 interrupt is requested, and if any of bits oer, per, and fer is set to 1, an eri3 interrupt is requested. these two interrupt requests are generated during reception. the sci3 can carry out continuou s reception using an rxi3 and co ntinuous transmission using a txi3.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 275 of 518 rej09b0152-0300 these interrupts are shown in table 14.14. table 14.14 transmit/receive interrupts interrupt flags interrupt request conditions notes rxi3 rdrf rie when serial reception is performed normally and receive data is transferred from rsr to rdr, bit rdrf is set to 1, and if bit rie is set to 1 at this time, an rxi3 is enabled and an interrupt is requested. (see figure 14.17 (a).) the rxi3 interrupt routine reads the receive data transferred to rdr and clears bit rdrf to 0. continuous reception can be performed by repeating the above operations until reception of the next rsr data is completed. txi3 tdre tie when tsr is found to be empty (on completion of the previous transmission) and the transmit data placed in tdr is transferred to tsr, bit tdre is set to 1. if bit tie is set to 1 at this time, a txi3 is enabled and an interrupt is requested. (see figure 14.17 (b).) the txi3 interrupt routine writes the next transmit data to tdr and clears bit tdre to 0. continuous transmission can be performed by repeating the above operations until the data transferred to tsr has been transmitted. tei31 tend teie when the last bit of the character in tsr is transmitted, if bit tdre is set to 1, bit tend is set to 1. if bit teie is set to 1 at this time, a tei3 is enabled and an interrupt is requested. (see figure 14.17 (c).) a tei3 indicates that the next transmit data has not been written to tdr when the last bit of the transmit character in tsr is transmitted.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 276 of 516 rej09b0152-0300 rdr rsr (reception in progress) rdrf = 0 rxd3 pin rdr rsr (reception completed, transfer) rdrf 1 (rxi3 request when rie = 1) rxd3 pin figure 14.17 (a) rdrf setting and rxi interrupt tdr (next transmit data) tsr (transmission in progress) tdre = 0 txd3 pin tdr tsr (transmission completed, transfer) tdre 1 (txi3 request when tie = 1) txd3 pin figure 14.17 (b) tdre setting and txi interrupt tdr tsr (transmission in progress) tend = 0 txd3 pin tdr tsr (transmission completed) tend 1 (tei3 request when teie = 1) txd3 pin figure 14.17 (c) tend se tting and tei interrupt
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 277 of 518 rej09b0152-0300 14.8 usage notes 14.8.1 break detection and processing when framing error detection is performed, a br eak can be detected by reading the rxd3 pin value directly. in a break, the input from the rxd3 pin becomes all 0, setting the fer flag, and possibly the per flag. note that as the sci3 co ntinues the receive oper ation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 14.8.2 mark state and break sending when the spc3 bit in spcr is 0, the txd3 pin f unctions as an i/o port whose direction (input or output) and level are determined by pcr and pdr, regardless of the te setting. this can be used to set the txd3 pin to the mark state (high level) or send a break during data transmission. to maintain the communication line at the mark state until the spc3 bit in spcr is set to 1, set both pcr and pdr to 1. as the spc3 bit in spcr is cleared to 0 at this point, the txd3 pin functions as an i/o port, and 1 is output from the txd3 pin. to send a break during data transmission, first set pcr to 1 and pdr to 0, and then clear the spc3 and te bits to 0. wh en the te bit is cleared to 0 directly after the spc3 bit is cleared to 0, th e transmitter is initialized regardless of the current transmission state after the te b it is cleared, the txd3 pin functions as an i/o port after the spc3 bit is cleared, and 0 is output from the txd3 pin. 14.8.3 receive error flags and transmit operations (clock synchronous mode only) transmission cannot be started when a receive error flag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 278 of 516 rej09b0152-0300 14.8.4 receive data samplin g timing and reception marg in in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.18. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 ? ) ? ? (l ? 0.5) f 100(%) ? ? ? ? ? ? 1 2n d ? 0.5 n ... formula (1) where n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd3) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 14.18 receive data sampling timing in asynchronous mode
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 279 of 518 rej09b0152-0300 14.8.5 note on switching sck3 pin function if the sck3 pin is used as a clock output pin by the sci3 in clock synchronous mode and is then switched to a general input/output pin (a pin with a different function), the sck3 pin outputs a low level signal for half a system clock ( ) cycle immediately after it is switched. this can be prevented by either of the following methods according to the situation. (1) when sck3 pin function is switched from clock output to non clock-output when stopping data transfer, issue one instructi on to clear bits te and re to 0 and to set bits cke1 and cke0 in scr to 1 and 0, respectively. in this case, bit com in smr should be left 1. the above prevents the sck3 pin from being used as a general input/output pin. to avoid an intermediate level of voltage from being applied to the sck3 pin, the line connected to the sck3 pin should be pulled up to the v cc level via a resistor, or supplied with output from an external device. (2) when sck3 pin function is switched from clock output to general input/output when stopping data transfer, 1. issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr to 1 and 0, respectively. 2. clear bit com in smr to 0 3. clear bits cke1 and cke0 in scr to 0. note th at special care is also needed here to avoid an intermediate level of voltage from being applied to the sck3 pin. 14.8.6 relation between wr iting to tdr and bit tdre bit tdre in the serial status register (ssr) is a status flag that indicates that data for serial transmission has not been prepared in tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. when the sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr irrespective of the state of bit tdre, but if new data is written to tdr while bit tdre is cleared to 0, the data previously stored in tdr will be lost if it has not yet been transferred to tsr. accordingly, to ensure that serial transmission is performed dependably, you should first check that bit tdre is set to 1, then write the transmit data to tdr only once (not two or more times).
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 280 of 516 rej09b0152-0300 14.8.7 relation between rdr reading and bit rdrf in a receive operation, the sci3 continually ch ecks the rdrf flag. if bit rdrf is cleared to 0 when reception of one frame ends, no rmal data reception is completed. if bit rdrf is set to 1, this indicates that an overrun error has occurred. when the contents of rdr are read, bit rdrf is cleared to 0 automatically . therefore, if rdr is read more than once, the second and subsequent read operations will be performed while bit rdrf is cleared to 0. note that, when an rdr re ad is performed while bit rdrf is cleared to 0, if the read operation coincides w ith completion of reception of a frame, the next frame of data may be read. this is shown in figure 14.19. frame 1 frame 2 frame 3 data 1 communication line rdrf rdr data 2 data 3 data 1 data 2 rdr read rdr read (a) data 1 is read at point (a) data 2 is read at point (b) (b) figure 14.19 relation between rdr read timing and data in this case, only a single rdr read operation (not two or more) should be performed after first checking that bit rdrf is set to 1. if two or more reads are performed, the data read the first time should be transferred to ram, etc., and the ram contents used. also, ensure that there is sufficient margin in an rdr read operation before reception of the next frame is completed. to be precise in terms of timing, the rdr read should be completed before bit 7 is transferred in clock synchronous mode, or before the stop bit is transferred in asynchronous mode.
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 281 of 518 rej09b0152-0300 14.8.8 transmit and receive operatio ns when making state transition make sure that transmit and receive operations ha ve completely finished before carrying out state transition processing. 14.8.9 setting in subactive or subsleep mode in subactive or subsleep mode, the sci3 can operate only when the cpu clock is w . the sa1 and sa0 bits in syscr2 should be set to 1. 14.8.10 oscillator when serial communication interface 3 is used when serial communication interface 3 is used, the system clock oscillator or subclock oscillator must be used. do not use the on-chip oscillator. for details on selecting the system clock oscillator or on-chip oscillator, see section 4.2.4, on-chip oscillator selection method. for details on selecting the subclock oscillator or on-chip oscillator, see section 4.1.1, oscillator control register (osccr).
section 14 serial communicati on interface 3 (sci3, irda) rev. 3.00 may 15, 2007 page 282 of 516 rej09b0152-0300
section 15 synchronous serial communication unit (ssu) sciaau1a_000120030300 rev. 3.00 may 15, 2007 page 283 of 516 rej09b0152-0300 section 15 synchronous seri al communication unit (ssu) the synchronous serial communication unit (ssu) can handle clocked synchronous serial data communication. figure 15.1 shows a block diagram of the ssu. 15.1 features ? can be operated in clocked synchronous communication mode or four-line bus communication mode (including bidirectional communication mode) ? can be operated as a master or a slave device ? choice of eight internal clocks ( /256, /128, /64, /32, /16, /8, /4, and sub /2) and an external clock as a clock source ? clock polarity and phase of ssck can be selected ? choice of data transfer direction (msb-first or lsb-first) ? receive error detec tion: overrun error ? multimaster error detection: conflict error ? five interrupt sources: transmit-end, transmit-dat a-empty, receive-data-fu ll, overrun error, and conflict error ? continuous transmission and reception of serial data are enabled since both transmitter and receiver have buffer structure ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the ssu is halted as the initial va lue. for details, refer to section 5.4, module standby function.)
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 284 of 516 rej09b0152-0300 ssmr sscrl sscrh sser sssr sstdr internal data bus sso scs ssck multiplexer transmission/ reception control circuit internal clock ssi sstrsr ssrdr interrupt request (txi, tei, rxi, oei, cei) ssmr: sscrl: sscrh: sser: sssr: sstdr: sstrsr: ssrdr: ss mode register ss control register l ss control register h ss enable register ss status register ss transmit data register ss shift register ss receive data register selector [legend] figure 15.1 block diagram of ssu 15.2 input/output pins table 15.1 shows the pin configuration of the ssu. table 15.1 pin configuration pin name abbreviation i/o function ssu clock ssck i/o ssu clock input/output ssu data input/output ssi i/o ssu data input/output ssu data input/output sso i/o ssu data input/output ssu chip select input/output scs i/o ssu chip select input/output
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 285 of 518 rej09b0152-0300 15.3 register descriptions the ssu has the following registers. ? ss control register h (sscrh) ? ss control register l (sscrl) ? ss mode register (ssmr) ? ss enable register (sser) ? ss status register (sssr) ? ss receive data register (ssrdr) ? ss transmit data register (sstdr) ? ss shift register (sstrsr) 15.3.1 ss control register h (sscrh) sscrh is a register that selects a master or a slave device, enables bidirectional mode, selects open-drain output of the serial data output pin, selects an output value of the serial data output pin, selects the ssck pi n, and selects the scs pin. bit bit name initial value r/w description 7 mss 0 r/w master/slave device select selects whether this module is used as a master device or a slave device. when this module is used as a master device, transfer clock is output from the ssck pin. when the ce bit in sssr is set, this bit is automatically cleared. 0: operates as a slave device 1: operates as a master device 6 bide 0 r/w bidirectional mode enable selects whether the serial data input pin and the output pin are both used or only one pin is used. for details, refer to section 15.4.3, relationship between data input/output and shift regist er. when the ssums bit in sscrl is 0, this setting is invalid. 0: normal mode. communication is performed by using two pins. 1: bidirectional mode. communication is performed by using only one pin.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 286 of 516 rej09b0152-0300 bit bit name initial value r/w description 5 soos 0 r/w serial data open-drain output select selects whether the serial data output pin is cmos output or nmos open-drain output. the serial data output pin is changed according to the register setting value. for details, refer to section 15.4.3, relationship between data input/output and shift register. 0: cmos output 1: nmos open-drain output 4 sol 0 r/w serial data output level setting although the value in the la st bit of transmit data is retained in the serial data output after the end of transmission, the output level of serial data can be changed by manipulating this bit before or after transmission. when the output level is changed, the solp bit should be cleared to 0 and the mov instruction should be used. if this bit is written during data transfer, erroneous operation may occur. therefore this bit must not be manipulated during transmission. 0: shows serial data output level to low in reading. changes serial data output level to low in writing 1: shows serial data output level to high in reading. changes serial data output level to high in writing 3 solp 1 r/w sol write protect when output level of serial data is changed, the mov instruction is used to set the sol bit to 1 and clear this bit to 0 or to clear the sol bit and this bit to 0. 0: in writing, output level can be changed according to the value of the sol bit. 1: in reading, this bit is always read as 1. in writing, output level cannot be cha nged. (see section 15.5, usage note.)
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 287 of 518 rej09b0152-0300 bit bit name initial value r/w description 2 scks 0 r/w ssck pin select selects whether the ssck pin functions as a port or a serial clock pin. 0: functions as a port 1: functions as a serial clock pin 1 0 css1 css0 0 0 r/w r/w scs pin select selects whether the scs pin functions as a port, an scs input, or scs output. when the ssums bit in sscrl is 0, the scs pin functions as a port regardless of the setting of this bit. 00: functions as a port 01: functions as an scs input 1x: functions as an scs output (however, functions as an scs input before starting transfer) [legend] x: don't care. 15.3.2 ss control register l (sscrl) sscrl is a register that controls mode, software reset, and open-drain output of the ssck and scs pins. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 288 of 516 rej09b0152-0300 bit bit name initial value r/w description 6 ssums 0 r/w ssu mode select selects which combination of the serial data input pin and serial data output pin is used. for details, refer to section 15.4.3, relation ship between data input/output and shift register. 0: clocked synchronous communication mode data input: ssi pin, data output: sso pin 1: four-line bus communication mode when mss = 1 and bide = 0 in sscrh: data input: ssi pin, data output: sso pin when mss = 0 and bide = 0 in sscrh: data input: sso pin, data output: ssi pin when bide = 1 in sscrh: data input and output: sso pin 5 sres 0 r/w software reset when this bit is set to 1, the ssu internal sequencer is forcibly reset. then this bit is automatically cleared. the register value in the ssu is retained. 4 sckos 0 r/w ssck pin open -drain output select selects whether the ssck pin functions as cmos output or nmos open-drain output. 0: cmos output 1: nmos open-drain output 3 csos 0 r/w scs pin open-drain output select selects whether the scs pin functions as cmos output or nmos open-drain output. 0: cmos output 1: nmos open-drain output 2 to 0 ? all 0 ? reserved these bits are always read as 0.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 289 of 518 rej09b0152-0300 15.3.3 ss mode register (ssmr) ssmr is a register that selects msb-first or lsb-first, clock polarity, clock phase, and transfer clock rate. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select selects whether data transfer is performed in msb-first or lsb-first. 0: lsb-first 1: msb-first 6 cpos 0 r/w clock polarity select selects the clock polarity of ssck. 0: idle state = high 1: idle state = low 5 cphs 0 r/w clock phase select selects the clock phase of ssck. 0: data change at first edge 1: data latch at first edge 4, 3 ? all 0 ? reserved these bits are always read as 0. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w transfer clock rate select sets transfer clock rate (presc aler division ratio) when the internal clock is selected. the system clock ( ) is halted in subactive mode or subsleep mode. select sub /2 in these modes. 000: /256 001: /128 010: /64 011: /32 100: /16 101: /8 110: /4 111: sub /2
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 290 of 516 rej09b0152-0300 15.3.4 ss enable register (sser) sser is a register that sets transmit enab le, receive enable, and interrupt enable. bit bit name initial value r/w description 7 te 0 r/w transmit enable when this bit is 1, transmit operation is enabled. 6 re 0 r/w receive enable when this bit is 1, receive operation is enabled. 5 rsstp 0 r/w receive single stop when this bit is 1, receive operation is completed after receiving one byte. 4 ? 0 ? reserved this bit is always read as 0. 3 teie 0 r/w transmit end interrupt enable when this bit is set to 1, a tei interrupt request is enabled. 2 tie 0 r/w transmit interrupt enable when this bit is set to 1, a txi interrupt request is enabled. 1 rie 0 r/w receive interrupt enable when this bit is set to 1, an rxi and an oei interrupt requests are enabled. 0 ceie 0 r/w conflict error interrupt enable when this bit is set to 1, a cei interrupt request is enabled.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 291 of 518 rej09b0152-0300 15.3.5 ss status register (sssr) sssr is a register that sets interrupt flags. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 orer 0 r/(w) * overrun error flag indicates that the rdrf bit is abnormally terminated in reception because an overrun error has occurred. ssrdr retains received data before the overrun error occurs and the received data after the overrun error occurs is lost. when this bit is set to 1, subsequent serial reception cannot be continued. when the mss bit in sscrh is 1, this is also applied to serial transmission. [setting condition] ? when the next serial reception is completed while rdrf = 1 [clearing condition] ? when 0 is written to this bit after reading 1 5, 4 ? all 0 ? reserved these bits are always read as 0. 3 tend 0 r/(w) * transmit end [setting condition] ? when the last bit of data is transmitted, the tdre bit is 1 [clearing conditions] ? when 0 is written to this bit after reading 1 ? when data is written in sstdr
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 292 of 516 rej09b0152-0300 bit bit name initial value r/w description 2 tdre 1 r/(w) * transmit data empty [setting conditions] ? when the te bit in sser is 0 ? when data transfer is performed from sstdr to sstrsr and data can be written in sstdr [clearing conditions] ? when 0 is written to this bit after reading 1 ? when data is written in sstdr 1 rdrf 0 r/(w) * receive data register full [setting condition] ? when serial reception is completed normally and receive data is transferred from sstrsr to ssrdr [clearing conditions] ? when 0 is written to this bit after reading 1 ? when data is read from ssrdr 0 ce 0 r/(w) * conflict error flag [setting conditions] ? when serial communication is started while ssums = 1 and mss =1, the scs pin input is low ? when the scs pin level changes from low to high during transfer while ssums = 1 and mss = 0 [clearing condition] ? when 0 is written to this bit after reading 1 note: * only 0 can be written to clear the flag.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 293 of 518 rej09b0152-0300 15.3.6 ss receive data register (ssrdr) ssrdr is an 8-bit register that stores received serial data. when the ssu has received one byte of serial data, it transfers the received serial data from sstrsr and the data is stored. after this, sstrsr is receive-enabled. as sstrsr and ssrdr function as a double buffer in this way, continuous receive operations are possible. ssrdr is a read-only register and cannot be written to by the cpu. ssrdr is initialized to h'00. 15.3.7 ss transmit data register (sstdr) sstdr is an 8-bit register that stores serial da ta for transmission. sstdr can be read or written to by the cpu at all times. when the ssu detect s that sstrsr is empty, it transfers the transmit data written in sstdr to sstrsr and starts serial transmission. if the next transmit data has already been written to sstdr during serial tran smission, continuous serial transmission is possible. sstdr is initialized to h'00. 15.3.8 ss shift register (sstrsr) sstrsr is a shift register that transmits and receive s serial data. when transmit data is transferred from sstdr to sstrsr, bit 0 in sstdr is transf erred to bit 0 in sstrsr while the mls bit in ssmr is 0 (lsb-first transfer) and bit 7 in sstdr is transferred to bit 0 in sstrsr while the mls bit in ssmr is 1 (msb-first transfer). sst rsr cannot be directly accessed by the cpu. 15.4 operation 15.4.1 transfer clock transfer clock can be sel ected from eight internal clocks and an external clock. when this module is used, the ssck pin must be selected as a seri al clock by setting the scks bit in sscrh to 1. when the mss bit in sscrh is 1, an internal clock is selected and the ssck pin is in the output state. if transfer is started, the ssck pin outputs clocks of the transfer ra te set in the cks2 to cks0 bits in ssmr. when the mss bit is 0, an ex ternal clock is selected and the ssck pin is in the input state.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 294 of 516 rej09b0152-0300 15.4.2 relationship between clock polarity and phase, and data relationship between clock polarity and phase, and transfer data changes according to a combination of the ssums bit in sscrl and the cpos and cphs bits in ssmr. figure 15.2 shows the relationship. msb-first transfer or lsb first transfer can be selected by the setting of the mls bit in ssmr. when the mls bit is 0, transfer is started from ls b to msb. when the mls bit is 1, transfer is started from msb to lsb. ssck (1) when cphs = 0, cpos =0, and ssums = 0: (2) when cphs = 0 and ssums = 1: (3) when cphs = 1 and ssums = 1: ssck (cpos = 0) ssck (cpos = 1) sso, ssi sso, ssi ssck (cpos = 0) ssck (cpos = 1) sso, ssi bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 scs scs figure 15.2 relationship between clock polarity and phase, and data
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 295 of 518 rej09b0152-0300 15.4.3 relationship between data input/output and shift register relationship of connection between the data inpu t/output pin and sstrsr changes according to a combination of the mss bit in sscrh and the ssums bit in sscrl. it also changes by the bide bit in sscrh. figure 15.3 shows the relationship. sso shift register (sstrsr) shift register (sstrsr) shift register (sstrsr) shift register (sstrsr) (1) when ssums = 0: (3) when ssums = 1, bide = 0, and mss = 0: (2) when ssums = 1, bide = 0, and mss = 1: (4) when ssums = 1 and bide = 1: ssi sso ssi sso ssi sso ssi figure 15.3 relationship between data input/output pin and shift register
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 296 of 516 rej09b0152-0300 15.4.4 communication mo des and pin functions the ssu switches functions of the input/output pin in each communication mode according to the settings of the mss bit in sscrh and the re and te bits in sser. figure 15.2 shows the relationship between communication modes and the input/output pins. in bidirectional communication mode, neither te nor re should be set to 1. table 15.2 relationship between communi cation modes and input/output pins register state pin state communication mode ssums bide mss te re ssi sso ssck 0 x 0 0 1 in ? in 1 0 ? out in clocked synchronous communication mode 1 in out in 1 0 1 in ? out 1 0 ? out out 1 in out out 1 0 0 0 1 ? in in 1 0 out ? in four-line bus communication mode 1 out in in 1 0 1 in ? out 1 0 ? out out 1 in out out 1 1 0 0 1 ? in in 1 0 ? out in 1 0 1 ? in out four-line bus (bidirectional) communication mode 1 0 ? out out [legend] x: don't care. ? : can be used as a general i/o port.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 297 of 518 rej09b0152-0300 15.4.5 operation in clocked sy nchronous communication mode initialization in clocked sync hronous communication mode: figure 15.4 shows the initialization in clocked synchr onous communication mode. before transm itting and receiving data, the te and re bits in sser should be cleared to 0, then the ssu should be initialized. note: when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not change the contents of the rdrf and or er flags, or the contents of ssrdr. start clear te and re bits in sser to 0 clear ssums bit in sscrl to 0 set scks bit in sscrh to 1 and set mss and soos bits clear cpos and cphs bits to 0 and set mls and cks2 to cks0 bits in ssmr clear orer bit in sssr to 0 set the te and re bits in sser to 1 and set rie, tie, teie, and rsstp bits according to transmission/ reception/transmission and reception end figure 15.4 initialization in cl ocked synchronous communication mode
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 298 of 516 rej09b0152-0300 serial data transmission: figure 15.5 shows an example of the ssu operation for transmission. in serial transmission, the ssu operates as described below. when the ssu is set as a master device, it outp uts a synchronous clock and data. when the ssu is set as a slave device, it outputs data in synchronized with the input clock. when the ssu writes transmit data in sstdr afte r setting the te bit to 1, the tdre flag is automatically cleared to 0 and data is transferre d from sstdr to sstrsr. then the ssu sets the tdre flag to 1 and starts transmission. if the tie bit in sser is set to 1 at this time, a txi is generated. when the tdre flag is 0 and one frame of data has transferred, data is transferred from sstdr to sstrsr and serial transmission of the next frame is started. if the eighth bit is transmitted while the tdre flag is 1, the tend bit in sssr is set to 1 and the state is retained. if the teie bit in sser is set to 1 at this time, a tei is generated. after transmission is ended, the ssck pin is fixed high. while the orer bit in sssr is set to 1, transmission cannot be performed. therefore confirm that the orer bit is cleared to 0 before transmission. figure 15.6 shows a sample flowchart for serial data transmission. ssck sso bit 0 bit 1 bit 0 bit 7 bit 7 bit 1 tdre tend lsi operation user processing write data in sstdr write data in sstdr txi generated txi generated tei generated one frame one frame figure 15.5 example of operation in data transmission
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 299 of 518 rej09b0152-0300 ye s ye s no ye s no no start initialization read tdre bit in sssr [1] [2] [3] [1] after reading sssr and confirming that the tdre bit is 1, write transmit data in sstdr. then the tdre bit is automatically cleared to 0. [2] determine whether data transmission is continued. [3] read 1 from the tend bit in sssr to confirm that data transmission is completed. after the tend bit is set to 1, clear the tend bit and te bit in sser to 0 and transmit mode is ended. tdre = 1? write transmit data in sstdr data transmission continued? read tend bit in sssr tend = 1? clear tend bit and te bit in sser to 0 end figure 15.6 sample serial transmission flowchart
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 300 of 516 rej09b0152-0300 serial data reception: figure 15.7 shows an example of th e ssu operation for reception. in serial reception, the ssu operates as described below. when the ssu is set as a master device, it outp uts a synchronous clock and inputs data. when the ssu is set as a slave device, it inputs data in synchronized with the input clock. when the ssu is set as a master device, it outputs a receive cloc k and starts reception by performing dummy read on ssrdr. after eight bits of data is receive d, the rdrf bit in sssr is set to 1 and received data is stored in ssrdr. if the rie bit in sser is set to 1 at this time, a rxi is generated. if ssrdr is read, the rdrf bit is automatically cleared to 0. when the ssu is set as a master device and receptio n is ended, received data is read after setting the rsstp bit in sser to 1. then the ssu outputs eight bits of clocks and operation is stopped. after that, the re and rsstp bits are cleared to 0 and the last received data is read. note that if ssrdr is read while the re bit is set to 1, received clock is output again. when the eighth clock rises while the rdrf bit is 1, the orer bit in sssr is set. then an overrun error (oei) is generated and operation is stopped. when the orer bit in sssr is set to 1, reception cannot be performed. therefore confirm that the orer bit is cleared to 0 before reception. figure 15.8 shows a sample flowchart for serial data reception. ssck sso bit 0 bit 7 bit 0 bit 7 bit 0 bit 7 rdrf lsi operation rxi generated rxi generated rxi generated user processing dummy read on ssrdr read data in ssrdr read data in ssrdr set rsstp to 1 rsstp one frame one frame figure 15.7 example of operati on in data reception (mss = 1)
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 301 of 518 rej09b0152-0300 ye s start initialization dummy read on ssrdr [1] [2] [3] [4] [5] [6] [7] [1] after setting each register in the ssu, dummy read on ssrdr is performed and reception is started. [2] determine whether the last one byte of data is received. when the last one byte of data is received, set to stop reception after the data is received. [3][6] when a receive error occurs, clear the orer flag to 0 after the orer flag in sssr is read and an appropriate error processing is performed. when the orer flag is set to 1, transmission/reception cannot be started again. [4] confirm that the rdrf bit is 1. if the rdrf bit is 1, receive data in ssrdr is read. if the ssrdr bit is read, the rdrf bit is automatically cleared. [5] before the last one byte of data is received, set the rsstp bit to 1 and reception is stopped after the data is received. [7] confirm that the rdrf bit is 1. to end reception, clear the re and rsstp bits to 0 and then read the last receive data. if the ssrdr bit is read before clearing the re bit, reception is started again. last reception? read orer orer = 1? read rdrf rdrf = 1? read receive data in ssrdr ye s ye s no no ye s ye s no no no set rsstp to 1 read orer orer = 1? read rdrf rdrf = 1? re = 0, rsstp = 0 read receive data in ssrdr end overrun error processing figure 15.8 sample serial reception flowchart (mss = 1)
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 302 of 516 rej09b0152-0300 serial data transmi ssion and reception: data transmission and reception is a combined operation of data transmission and reception wh ich are described before. transmission and reception is started by writing data in sstdr. when the eighth cloc k rises or the orer bit is set to 1 while the tdre bit is set to 1, transmissi on and reception is stopped. to switch from transmit mode (te = 1) or receive mode (re = 1) to transmit and receive mode (te = re = 1), the te and re bits should be cl eared to 0. after confirming that the tend, rdrf, and orer bits are cleared to 0, set the te and re bits to 1. figure 15.9 shows a sample flowchart fo r serial transmit and receive operations. ye s ye s ye s no start initialization read tdre in sssr [1] [2] [3] [4] [1] after reading sssr and confirming that the tdre bit is 1, write transmit data in sstdr. then the tdre bit is automatically cleared to 0. [2] confirm that the rdrf bit is 1. if the rdrf bit is 1, receive data in ssrdr is read. if the ssrdr bit is read, the rdrf bit is automatically cleared. [3] determine whether data transmission is continued. [4] to end transmit and receive mode, clear the tend bit to 0 and clear the te and re bits in sser to 0. tdre = 1? write transmit data in sstdr read rdrf in sssr rdrf = 1? no no read receive data in ssrdr data transmission continued? clear tend to 0 and clear te and re in sser to 0 end figure 15.9 sample flowchart for s erial transmit and receive operations
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 303 of 518 rej09b0152-0300 15.4.6 operation in four-l ine bus communication mode four-line bus communication mode is a mode which communicates with the four-line bus; a clock line, a data input line, a data output line, and a chip select line. this mode includes bidirectional mode in which the data input line and the data output line function as a single pin. the data input line and the data output line are changed according to the settings of the mss and bide bits in sscrh. for details, refer to section 15.4.3, relationship between data input/output and shift register. in this mode, relationship between clock polarity and phase, and data can be set by the cpos and cphs bits in ssmr. for details, refer to section 15.4.2, relationship between clock polarity and phase, and data. when the ssu is set as a master device, the chip select line controls out put. when the ssu is set as a slave device, the chip select line controls in put. when the ssu is set as a master device, the chip select line cont rols output of the scs pin or controls output of a general port by setting the css1 bit in sscrh to 1. when the ssu is set as a slave device, the chip select line sets the scs pin as an input pin by setting the css1 and css0 bits in sscrh to 01. in four-line bus communication mode, the mls bit in ssmr is set to 1 and transfer is performed in msb-first order.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 304 of 516 rej09b0152-0300 15.4.7 initialization in four -line bus communication mode figure 15.10 shows the initialization in four-line bus communication mode. before transmitting and receiving data, the te and re bits in sser s hould be cleared to 0, then the ssu should be initialized. note: when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not change the contents of the rdrf and or er flags, or the contents of ssrdr. start clear te and re in sser to 0 set ssums in sscrl to 1 set scks in sscrh to 1 and set bide, mss, soos, css1, and css0 [1] [2] [2] in bidirectional mode, the bide bit is set to 1 and input/output of the scs pin is set by the css1 and css0 bits. [1] the mls bit is set to 1 for msb-first transfer. the clock polarity and phase are set in the cpos and cphs bits. set mls in ssmr to 1 and set cpos, cphs, and cks2 to cks0 clear orer in sssr to 0 set te and re in sser to 1 and set rie, tie, teie, and rsstp according to transmission/reception/ transmission and reception end figure 15.10 initialization in four-line bus communication mode
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 305 of 518 rej09b0152-0300 15.4.8 serial data transmission figure 15.11 shows an example of the ssu operatio n for transmission. in se rial transmission, the ssu operates as described below. when the ssu is set as a master device, it output s a synchronous clock and data. when the ssu is set as a slave device, the scs pin is in the low-input state and the ssu outputs data in synchronized with the input clock. when the ssu writes transmit data in sstdr afte r setting the te bit to 1, the tdre flag is automatically cleared to 0 and data is transferre d from sstdr to sstrsr. then the ssu sets the tdre flag to 1 and starts transmission. if the tie bit in sser is set to 1 at this time, a txi is generated. when the tdre flag is 0 and one frame of data has transferred, data is transferred from sstdr to sstrsr and serial transmission of the next frame is started. if the eighth bit is transmitted while the tdre flag is 1, the tend bit in sssr is set to 1 and the state is retained. if the teie bit in sser is set to 1 at this time, a tei is generated. after transmission is ended, the ssck pin is fixed high and the scs pin goes high. when continuous transmission is performed with the scs pin low, the next data should be written to sstdr before transmitting the eighth bit of the frame. while the orer bit in sssr is set to 1, transmission cannot be performed. therefore confirm that the orer bit is cleared to 0 before transmission. the difference between this mode and clocked synchronous communication mode is as follows: when the ssu is set as a master device, the sso pin is in the hi-z state if the scs pin is in the hi- z state and when the ssu is set as a slave device, the ssi pin is in the hi-z state if the scs pin is in the high-input state. the sample flowchart for se rial data transmission is the same as that in clocked synchronous communication mode.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 306 of 516 rej09b0152-0300 ssck (1) when cpos = 0 and cphs = 0: (2) when cpos = 0 and cphs = 1: scs (output) scs (output) (hi-z) sso bit 7 bit 6 bit 0 bit 7 bit 6 bit 0 bit 7 bit 6 bit 0 bit 7 bit 6 bit 0 tdre tend lsi operation user processing write data in sstdr write data in sstdr user processing write data in sstdr write data in sstdr txi generated txi generated tei generated lsi operation txi generated txi generated tei generated ssck (hi-z) sso tdre tend one frame one frame one frame one frame figure 15.11 example of operation in data transmission (mss = 1)
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 307 of 518 rej09b0152-0300 15.4.9 serial da ta reception figure 15.12 shows an example of the ssu operation for reception . in serial reception, the ssu operates as described below. when the ssu is set as a master device, it output s a synchronous clock and inputs data. when the ssu is set as a slave device, the scs pin is in the low-input state and inputs data in synchronized with the input clock. when the ssu is set as a ma ster device, it outputs a receive clock and starts reception by performing dummy read on ssrdr. after eight bits of data is receive d, the rdrf bit in sssr is set to 1 and received data is stored in ssrdr. if the rie bit in sser is set to 1 at this time, an rxi is generated. if ssrdr is read, the rdrf bit is automatically cleared to 0. when the ssu is set as a master device and receptio n is ended, received data is read after setting the rsstp bit in sser to 1. then the ssu outputs eight bits of clocks and operation is stopped. after that, the re and rsstp bits are cleared to 0 and the last received data is read. note that if ssrdr is read while the re bit is set to 1, received clock is output again. when the eighth clock rises while the rdrf bit is 1, the orer bit in sssr is set. then an overrun error (oei) is generated and operation is stopped. when the orer bit in sssr is set to 1, reception cannot be performed. therefore confirm that the orer bit is cleared to 0 before reception. the set timings of the rdrf and orer flags differ according to the cphs setting. these timings are shown in figure 15.12. when the cphs bit is set to 1, the flag is set during the frame. therefore care should be taken at the end of reception. the sample flowchart for serial data reception is the same as that in clocked synchronous communication mode.
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 308 of 516 rej09b0152-0300 ssck (1) when cpos = 0 and cphs = 0: (2) when cpos = 0 and cphs = 1: scs (output) scs (output) (hi-z) ssi bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 bit 7 bit 0 rdrf rsstp lsi operation user processing dummy read on ssrdr read data in ssrdr read data in ssrdr set rsstp to 1 user processing dummy read on ssrdr read data in ssrdr read data in ssrdr set rsstp to 1 rxi generated rxi generated rxi generated lsi operation rxi generated rxi generated rxi generated ssck (hi-z) ssi rdrf rsstp one frame one frame one frame one frame figure 15.12 example of operati on in data reception (mss = 1)
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 309 of 518 rej09b0152-0300 15.4.10 scs pin control and arbitration when the ssums bit in sscrl is set to 1 and the css1 bit in sscrh is set to 1, the mss bit in sscrh is set to 1 and then the arbitration of the scs pin is checked before st arting serial transfer. if the ssu detects that th e synchronized internal scs pin goes low in this period, the ce bit in sssr is set and the mss bit is cleared. note: when a conflict error is set, subsequent transmit operation is not possible. therefore the ce bit must be cleared to 0 before starting transmission. when the multimaster error is used, the csos bit in sscrl should be set to 1. mss transfer start write data in sstdr arbitration detection period maximum time of scs internal synchronization internal scs (synchronized) scs input scs output ce (hi-z) figure 15.13 arbitration check timing
section 15 synchronous serial communication unit (ssu) rev. 3.00 may 15, 2007 page 310 of 516 rej09b0152-0300 15.4.11 interrupt requests the ssu has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. since these interrupt requ ests are assigned to the common vector address, interrupt sources must be determined by flags. table 15.3 lists the interrupt requests. table 15.3 interrupt requests interrupt request abbreviat ion interrupt condition transmit data empty txi (tie = 1), (tdre = 1) transmit end tei (teie = 1), (tend = 1) receive data full rxi (rie = 1), (rdrf = 1) overrun error oei (rie = 1), (orer = 1) conflict error cei (ceie = 1), (ce = 1) when an interrupt condition shown in table 15.3 is 1 and the i bit in ccr is 0, the cpu executes the interrupt exception handling. each interrupt source must be cleared during the exception handling. note that the tdre and tend bits are au tomatically cleared by writing transmit data in sstdr and the rdrf bit is auto matically cleared by reading ssr dr. when transmit data is written in sstdr, the tdre bit is set again at the same time. then if the tdre bit is cleared, additional one byte of data may be transmitted. 15.5 usage note when writing 1 to the solp bit in sscrh (to enable write protect) after writing 0 to it (to disable write protect), the sol bit may be changed without being protected. to avoid this, before writing 1 to the solp bit (to enable write protect), write the current value of the sol bit to itself. with this procedure, the write protect can be performed on the sol bit.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 311 of 516 rej09b0152-0300 section 16 i 2 c bus interface 2 (iic2) the i 2 c bus interface 2 conforms to and pr ovides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the configuration of the registers that control the i 2 c bus differs partly from the philips configuration, however. figure 16.1 shows a block diagram of the i 2 c bus interface 2. figure 16.2 shows an example of i/o pin connections to external circuits. 16.1 features ? selection of i 2 c format or clock synchronous serial format ? continuous transmission/reception since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmi ssion/reception can be performed. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the iic2 is halted as the initial value. for details, refer to section 5.4, module standby function.) i 2 c bus format ? start and stop conditions generated automatically in master mode ? selection of acknowledge output levels when receiving ? automatic loading of acknowledge bit when transmitting ? bit synchronization/wait function in master mode, the state of scl is monitored per bit, and the timing is synchronized automatically. if transmission/reception is not yet possible, set the scl to low un til preparations are completed. ? six interrupt sources transmit data empty (including slave-address matc h), transmit end, receive data full (including slave-address match), arbitration lost, nack detection, and stop condition detection ? direct bus drive two pins, scl and sda pins, function as cmos outputs in normal operation (when the port/serial function is selected) and nmos outputs when the bus drive function is selected. clock synchronous format ? four interrupt sources transmit-data-empty, transmit-end, receive-data-full, and overrun error
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 312 of 516 rej09b0152-0300 scl iccr1 transfer clock generation circuit address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceler noise canceler output control output control transmission/ reception control circuit iccr2 icmr icsr icier icdrr icdrs icdrt i 2 c bus control register 1 i 2 c bus control register 2 i 2 c bus mode register i 2 c bus status register i 2 c bus interrupt enable register i 2 c bus transmit data register i 2 c bus receive data register i 2 c bus shift register slave address register [legend] iccr1 : iccr2 : icmr : icsr : icier : icdrt : icdrr : icdrs : sar : sar sda internal data bus figure 16.1 block diagram of i 2 c bus interface 2
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 313 of 516 rej09b0152-0300 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 16.2 external circu it connections of i/o pins 16.2 input/output pins table 16.1 shows the pin configuration of the i 2 c bus interface 2. table 16.1 pin configuration name abbreviation i/o function serial clock pin scl i/o iic serial clock input/output serial data pin sda i/o iic serial data input/output
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 314 of 516 rej09b0152-0300 16.3 register descriptions the i 2 c bus interface 2 has the following registers. ? i 2 c bus control register 1 (iccr1) ? i 2 c bus control register 2 (iccr2) ? i 2 c bus mode register (icmr) ? i 2 c bus interrupt enable register (icier) ? i 2 c bus status register (icsr) ? slave address register (sar) ? i 2 c bus transmit data register (icdrt) ? i 2 c bus receive data register (icdrr) ? i 2 c bus shift register (icdrs) 16.3.1 i 2 c bus control register 1 (iccr1) iccr1 enables or disables the i 2 c bus interface 2, controls transm ission or reception, and selects master or slave mode, transmission or reception , and transfer clock frequ ency in master mode. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted. (scl and sda pins are set to the port/serial function.) 1: this bit is enabled for transfer operations. (scl and sda pins are bus drive state.) 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 315 of 516 rej09b0152-0300 bit bit name initial value r/w description 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. after data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to sar and the eighth bit is 1, trs is automatically set to 1. if an overrun error occurs in master mode with the clock synchronous serial format, mst is cleared to 0 and slave receive mode is entered. operating modes are described below according to mst and trs combination. when clock synchronous serial format is selected and mst is 1, clock is output. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w transfer clock select 3 to 0 these bits are valid only in master mode and should be set according to the necessa ry transfer rate (refer to table 16.2). these bit are us ed to specify the data setup time in slave transmit mode. the data setup time is secured for 10tcyc when cks3 = 0 and for 20tcyc when cks3 = 1.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 316 of 516 rej09b0152-0300 table 16.2 transfer rate bit 3 bit 2 bit 1 bit 0 transfer rate cks3 cks2 cks1 cks0 clock = 2 mhz = 5 mhz = 10 mhz 0 /28 71.4 khz 179 khz 357 khz 0 1 /40 50.0 khz 125 khz 250 khz 0 /48 41.7 khz 104 khz 208 khz 0 1 1 /64 31.3 khz 78.1 khz 156 khz 0 /80 25.0 khz 62.5 khz 125 khz 0 1 /100 20.0 khz 50.0 khz 100 khz 0 /112 17.9 khz 44.6 khz 89.3 khz 0 1 1 1 /128 15.6 khz 39.1 khz 78.1 khz 0 /56 35.7 khz 89.3 khz 179 khz 0 1 /80 25.0 khz 62.5 khz 125 khz 0 /96 20.8 khz 52.1 khz 104 khz 0 1 1 /128 15.6 khz 39.1 khz 78.1 khz 0 /160 12.5 khz 31.3 khz 62.5 khz 0 1 /200 10.0 khz 25.0 khz 50.0 khz 0 /224 8.9 khz 22.3 khz 44.6 khz 1 1 1 1 /256 7.8 khz 19.5 khz 39.1 khz
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 317 of 516 rej09b0152-0300 16.3.2 i 2 c bus control register 2 (iccr2) iccr2 issues start/stop conditions, manipulates the sda pin, monitors the scl pin, and controls reset in the control part of the i 2 c bus interface 2. bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit enables to confirm whether the i 2 c bus is occupied or released and to issue start/stop conditions in master mode. with the clock synchronous serial format, this bit has no meaning. with the i 2 c bus format, this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assuming that the stop condition has been issued. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re-transmitting a start condition. write 0 in bbsy and 0 in scp to issue a stop condition. to issue start/stop conditions , use the mov instruction. 6 scp 1 r/w start/stop issue condition disable the scp bit controls the iss ue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a repeated start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r/w sda output value control this bit is used with sdaop when modifying output level of sda. this bit should not be manipulated during transfer. 0: when reading, sda pin outputs low. when writing, sda pin is changed to output low. 1: when reading, sda pin outputs high. when writing, sda pin is changed to output hi-z (outputs high by external pull-up resistance).
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 318 of 516 rej09b0152-0300 bit bit name initial value r/w description 4 sdaop 1 r/w sdao write protect this bit controls change of output level of the sda pin by modifying the sdao bit. to change the output level, clear sdao and sdaop to 0 or set sdao to 1 and clear sdaop to 0 by the mov instruction. this bit is always read as 1. 3 sclo 1 r this bit monitors sc l output level. when sclo is 1, scl pin outputs high. when sclo is 0, scl pin outputs low. 2 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 1 iicrst 0 r/w iic control part reset this bit resets the control part except for i 2 c registers. if this bit is set to 1 when hang-up occurs because of communication failure during i 2 c operation, i 2 c control part can be reset without setting ports and initializing registers. 0 ? 1 ? reserved this bit is always read as 1, and cannot be modified.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 319 of 516 rej09b0152-0300 16.3.3 i 2 c bus mode register (icmr) icmr selects whether the msb or lsb is transferre d first, performs master mode wait control, and selects the tran sfer bit count. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used. 6 wait 0 r/w wait insertion bit in master mode with the i 2 c bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. when wait is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the setting of this bit is invalid in slave mode with the i 2 c bus format or with the clock synchronous serial format. 5, 4 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 3 bcwp 1 r/w bc write protect this bit controls the bc2 to bc0 modifications. when modifying bc2 to bc0, this bit should be cleared to 0 and use the mov instruction. in clock synchronous serial mode, bc should not be modified. 0: when writing, values of bc2 to bc0 are set. 1: when reading, 1 is always read. when writing, settings of bc2 to bc0 are invalid.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 320 of 516 rej09b0152-0300 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. when read, the remaining number of transfer bits is indicated. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl pin is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. with the clock synchronous serial format, these bits should not be modified. i 2 c bus format clock synchronous serial format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 321 of 516 rej09b0152-0300 16.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and conf irms acknowledge bits to be received. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit data empty interrupt (txi). 0: transmit data empty interrupt request (txi) is disabled. 1: transmit data empty interrupt request (txi) is enabled. 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) at the rising of the ni nth clock while the tdre bit in icsr is 1. tei can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt request (tei) is disabled. 1: transmit end interrupt request (tei) is enabled. 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive data full interrupt request (rxi) and the overrun error interrupt request (eri) with the clock synchronous format, when a receive data is transferred from icdrs to icdrr and the rdrf bit in icsr is set to 1. rxi can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clock synchronous format are disabled. 1: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clock synchronous format are enabled.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 322 of 516 rej09b0152-0300 bit bit name initial value r/w description 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt request (naki) and the overrun error (setting of the ove bit in icsr) interrupt request (eri) with the clock synchronous format, when the nackf and al bits in icsr are set to 1. naki can be canceled by clearing the nackf, ove, or nakie bit to 0. 0: nack receive interrupt request (naki) is disabled. 1: nack receive interrupt request (naki) is enabled. 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt request (stpi) is disabled. 1: stop condition detection interrupt request (stpi) is enabled. 2 acke 0 r/w acknowledge bit judgment select 0: the value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: if the receive acknowledge bit is 1, continuous transfer is halted. 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit spec ifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 323 of 516 rej09b0152-0300 16.3.5 i 2 c bus status register (icsr) icsr performs confirmation of interrupt request flags and status. bit bit name initial value r/w description 7 tdre 0 r/(w) * transmit data register empty [setting conditions] ? when data is transferred from icdrt to icdrs and icdrt becomes empty ? when trs is set ? when a start condition (including re-transfer) has been issued ? when transmit mode is entered from receive mode in slave mode [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when data is written to icdrt with an instruction 6 tend 0 r/(w) * transmit end [setting conditions] ? when the ninth clock of scl rises with the i 2 c bus format while the tdre flag is 1 ? when the final bit of transmit frame is sent with the clock synchronous serial format [clearing conditions] ? when 0 is written in tend after reading tend = 1 ? when data is written to icdrt with an instruction 5 rdrf 0 r/(w) * receive data register full [setting condition] ? when a receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written in rdrf after reading rdrf = 1 ? when icdrr is read with an instruction
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 324 of 516 rej09b0152-0300 bit bit name initial value r/w description 4 nackf 0 r/(w) * no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is 1 [clearing condition] ? when 0 is written in nackf after reading nackf = 1 3 stop 0 r/(w) * stop condition detection flag [setting conditions] ? in master mode, when a stop condition is detected after the completion of frame transfer ? in slave mode, when a stop condition is detected, after the slave address of the first byte, following the general call and the detection of the start condition, matches the address set in sar [clearing condition] ? when 0 is written in stop after reading stop = 1
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 325 of 516 rej09b0152-0300 bit bit name initial value r/w description 2 al/ove 0 r/(w) * arbitration lost flag/overrun error flag this flag indicates that arbitration was lost in master mode with the i 2 c bus format and that the final bit has been received while rdrf = 1 with the clock synchronous format. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? when the sda pin outputs high in master mode while a start condition is detected ? when the final bit is received with the clock synchronous format while rdrf = 1 [clearing condition] ? when 0 is written in al/ove after reading al/ove = 1 1 aas 0 r/(w) * slave address recognition flag in slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode. [clearing condition] ? when 0 is written in aas after reading aas = 1
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 326 of 516 rej09b0152-0300 bit bit name initial value r/w description 0 adz 0 r/(w) * general call address recognition flag this bit is valid in i 2 c bus format slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written in adz after reading adz = 1 note: * only 0 can be written to clear the flag. 16.3.6 slave address register (sar) sar selects the communica tion format and sets the slave address. when the chip is in slave mode with the i 2 c bus format, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the ch ip operates as the slave device. bit bit name initial value r/w description 7 to 1 sva6 to sva0 all 0 r/w slave address 6 to 0 these bits set a unique address in bits sva6 to sva0, differing form the addresses of other slave devices connected to the i 2 c bus. 0 fs 0 r/w format select 0: i 2 c bus format is selected. 1: clock synchronous seri al format is selected. 16.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects the space in the shift register (icdrs), it transfers th e transmit data which is written in icdrt to icdrs and starts transferring data. if the next transfer data is written to icdrt during transferring data of icdrs, conti nuous transfer is possible. if the mls bit of icmr is set to 1 and when the data is written to icdrt, the msb/lsb inverted data is read. the initial value of icdrt is h'ff. the initial value of icdrt is h'ff.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 327 of 516 rej09b0152-0300 16.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit register that stores the receiv e data. when data of one byte is received, icdrr transfers the receive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only register, therefore the cpu cannot write to this regist er. the initial value of icdrr is h'ff. 16.3.9 i 2 c bus shift register (icdrs) icdrs is a register that is used to transfer/receive data. in transm ission, data is transferred from icdrt to icdrs and the data is sent from the sda pin. in reception, data is transferred from icdrs to icdrr after data of one byte is received. this register cannot be read directly from the cpu.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 328 of 516 rej09b0152-0300 16.4 operation the i 2 c bus interface 2 can communicate either in i 2 c bus mode or clock synchronous serial mode by setting fs in sar. 16.4.1 i 2 c bus format figure 16.3 shows the i 2 c bus formats. figure 16.4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (fs = 0) (b) i 2 c bus format (repeated start condition, fs = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 16.3 i 2 c bus formats sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a figure 16.4 i 2 c bus timing [legend] s: start condition. the master device drives sda from high to low while scl is high. sla: slave address r/ w : indicates the direction of da ta transfer: from the slave devi ce to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receive device drives sda to low. data: transfer data p: stop condition. the master device drives sda from low to high while scl is high.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 329 of 516 rej09b0152-0300 16.4.2 master transmit operation in master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for ma ster transmit mode operation timing, refer to figures 16.5 and 16.6. the transmission procedure and operations in master transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. read the bbsy flag in iccr2 to confirm that the bus is free. set the mst and trs bits in iccr1 to select master transmit mode. then , write 1 to bbsy and 0 to scp using mov instruction. (start condition issued) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte data show the slave address and r/ w ) to icdrt. at this time, tdre is automatically cleared to 0, and data is transferred from icdr t to icdrs. tdre is set again. 4. when transmission of one byte data is completed while tdre is 1, tend in icsr is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in icier, and confirm that the slave device has been selected. then, write second byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue the stop condition. to issue the stop condition, write 0 to bbsy and scp using mov instruction. scl is fixed low until the transmit data is prepared or the stop condition is issued. 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wait for nack (nackf in icsr = 1) from the receive device while acke in icier is 1. then , issue the stop condition to clear tend or nackf. 7. when the stop bit in icsr is set to 1, the operation returns to the slave receive mode.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 330 of 516 rej09b0152-0300 tdre scl (master output) sda (master output) sda (slave output) tend [5] write data to icdrt (third byte) icdrt icdrs [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) user processing 1 bit 7 slave address address + r/ w data 1 data 1 data 2 address + r/ w bit 6 bit 7 bit 6 bit 5bit 4bit 3bit 2bit 1bit 0 212 3456789 a r/ w figure 16.5 master transmit mode operation timing (1) tdre [6] issue stop condition. clear tend. [7] set slave receive mode tend icdrt icdrs 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 data n data n bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [5] write data to icdrt user processing figure 16.6 master transmit mode operation timing (2)
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 331 of 516 rej09b0152-0300 16.4.3 master receive operation in master receive mode, the master device outputs th e receive clock, receives data from the slave device, and returns an acknowledge signal. for master receive mode operation timing, refer to figures 16.7 and 16.8. the reception procedure and operations in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccr1 to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icdrr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. the master device outputs the level specified by ackbt in icier to sda, at the 9th receive clock pulse. 3. after the reception of first frame data is complete d, the rdrf bit in icst is set to 1 at the rise of 9th receive clock pulse. at this time, the r eceive data is read by reading icdrr, and rdrf is cleared to 0. 4. the continuous reception is performed by reading icdrr every time rdrf is set. if 8th receive clock pulse falls after reading icdrr by the other processing while rdrf is 1, scl is fixed low until icdrr is read. 5. if next frame is the last receive data, set th e rcvd bit in iccr1 to 1 before reading icdrr. this enables the issuance of the stop condition after the next reception. 6. when the rdrf bit is set to 1 at rise of th e 9th receive clock pulse, issue the stage condition. 7. when the stop bit in icsr is set to 1, read icdrr. then clear the rcvd bit to 0. 8. the operation returns to the slave receive mode.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 332 of 516 rej09b0152-0300 tdre tend icdrs icdrr [1] clear tdre after clearing tend and trs [2] read icdrr (dummy read) [3] read icdrr 1 a 21 3456789 9 a trs rdrf scl (master output) sda (master output) sda (slave output) bit 7 master transmit mode master receive mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing data 1 data 1 figure 16.7 master receive mode operation timing (1)
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 333 of 516 rej09b0152-0300 rdrf rcvd icdrs icdrr data n-1 data n data n data n-1 [5] read icdrr after setting rcvd [6] issue stop condition [7] read icdrr, and clear rcvd [8] set slave receive mode 1 9 23456789 aa/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing figure 16.8 master receive mode operation timing (2) 16.4.4 slave transmit operation in slave transmit mode, the slave device outputs th e transmit data, while the master device outputs the receive clock and returns an acknowledge sign al. for slave transmit mode operation timing, refer to figures 16.9 and 16.10. the transmission procedure and operations in slave transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the leve l specified by ackbt in icier to sda, at the rise of the 9th clock pulse. at this time, if the 8th bit data (r/ w ) is 1, the trs and icsr bits in iccr1 are set to 1, and the mode changes to slave transmit mode automatically. the continuous transmission is performed by writing transmit data to icdrt every time tdre is set. 3. if tdre is set after writing last transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when te nd is set, clear tend. 4. clear trs for the end processing, and read icdrr (dummy read). scl is free. 5. clear tdre.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 334 of 516 rej09b0152-0300 tdre tend icdrs icdrr 1 a 21 3456789 9 a trs icdrt scl (master output) slave receive mode slave transmit mode sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 data 1 data 1 data 2 data 3 data 2 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] write data to icdrt (data 1) [2] write data to icdrt (data 2) [2] write data to icdrt (data 3) user processing figure 16.9 slave transmit mode operation timing (1)
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 335 of 516 rej09b0152-0300 tdre data n tend icdrs icdrr 1 9 23456789 a trs icdrt a scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 slave transmit mode slave receive mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [3] clear tend [5] clear tdre [4] read icdrr (dummy read) after clearing trs user processing figure 16.10 slave transmit mode operation timing (2)
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 336 of 516 rej09b0152-0300 16.4.5 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. fo r slave receive mode ope ration timing, refer to figures 16.11 and 16.12. the reception procedure and operations in slave receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ac kbt in icier to sda, at the rise of the 9th clock pulse. at the same time, rdrf in icsr is set to read icdrr (d ummy read). (since the read data show the slave address and r/ w , it is not used.) 3. read icdrr every time rdrf is set. if 8th r eceive clock pulse falls while rdrf is 1, scl is fixed low until icdrr is read. the change of the acknowledge before reading icdrr, to be returned to the master device, is reflected to the next transmit frame. 4. the last byte data is read by reading icdrr. icdrs icdrr 12 1 345678 9 9 a a rdrf data 1 data 2 data 1 scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] read icdrr (dummy read) [2] read icdrr user processing figure 16.11 slave receive mode operation timing (1)
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 337 of 516 rej09b0152-0300 icdrs icdrr 12345678 9 9 a a rdrf scl (master output) sda (master output) sda (slave output) scl (slave output) user processing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data 1 [3] set ackbt [3] read icdrr [4] read icdrr data 2 data 1 figure 16.12 slave receive mode operation timing (2) 16.4.6 clock synchronous serial format this module can be operated with the clock synchronous serial format, by setting the fs bit in sar to 1. when the mst bit in iccr1 is 1, the transfer clock output from scl is selected. when mst is 0, the external clock input is selected. (1) data transfer format figure 16.13 shows the clock sync hronous serial tr ansfer format. the transfer data is output from the rise to the fa ll of the scl clock, and the data at the rising edge of the scl clock is guaranteed. the mls bit in icmr sets the order of data transfer, in either the msb first or lsb first. the output level of sda can be changed during the transfer wait, by the sdao bit in iccr2. sda bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 scl figure 16.13 clock synchronous serial transfer format
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 338 of 516 rej09b0152-0300 (2) transmit operation in transmit mode, transmit data is output from sda, in synchronization with the fall of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for transmit mode operation timing, refer to figure 16.14. the transmission procedure and operations in transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. set the trs bit in iccr1 to select the transmit mode. then, tdre in icsr is set. 3. confirm that tdre has been set. then, writ e the transmit data to icdrt. the data is transferred from icdrt to icdrs, and td re is set automatically. the continuous transmission is performed by writing data to icdrt every time tdre is set. when changing from transmit mode to receive mode, clear trs while tdre is 1. 12 781 78 1 scl trs bit 0 data 1 data 1 data 2 data 3 data 2 data 3 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 sda (output) tdre icdrt icdrs user processing [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [2] set trs figure 16.14 transmit mode operation timing
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 339 of 516 rej09b0152-0300 (3) receive operation in receive mode, data is latched at the rise of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for receive mode operation timing, refer to figure 16.15. the reception pro cedure and operations in receiv e mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. when the transfer clock is output, set mst to 1 to start outputting the receive clock. 3. when the receive operation is completed, da ta is transferred from icdrs to icdrr and rdrf in icsr is set. when mst = 1, the ne xt byte can be received, so the clock is continually output. the continuous reception is performed by reading icdrr every time rdrf is set. when the 8th clock is risen wh ile rdrf is 1, the overrun is detected and al/ove in icsr is set. at this time, the pr evious reception data is retained in icdrr. 4. to stop receiving when mst = 1, set rcvd in iccr1 to 1, then read icdrr. then, scl is fixed high after receiving the next byte data. 12 781 7812 scl mst trs rdrf icdrs icdrr sda (input) bit 0 bit 6 bit 7 bit 0 bit 6 bit 7 bit 1 bit 0 bit 1 user processing data 1 data 1 data 2 data 2 data 3 [2] set mst (when outputting the clock) [3] read icdrr [3] read icdrr figure 16.15 receive mode operation timing
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 340 of 516 rej09b0152-0300 16.4.7 noise canceler the logic levels on the scl and sda pins are in ternally latched via nois e cancelers. figure 16.16 shows a block diagram of th e noise canceler circuit. the noise canceler consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. c q d match detector internal scl or sda signal scl or sda input signal sampling clock sampling clock system clock period latch latch c q d figure 16.16 block di agram of noise conceler 16.4.8 example of use flowcharts in respective modes that use the i 2 c bus interface 2 are shown in figures 16.17 to 16.20.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 341 of 516 rej09b0152-0300 bbsy=0 ? no tend=1 ? no yes start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] initialize set mst and trs in iccr1 to 1. write 1 to bbsy and 0 to scp. write transmit data in icdrt write 0 to bbsy and scp set mst to 0 and trs to 0 in iccr1 read bbsy in iccr2 read tend in icsr read ackbr in icier mater receive mode yes ackbr=0 ? write transmit data in icdrt read tdre in icsr read tend in icsr clear tend in icsr read stop in icsr clear tdre in icsr end write transmit data in icdrt transmit mode? no yes tdre=1 ? last byte? stop=1 ? no no no no no yes yes tend=1 ? yes yes yes [1] test the status of the scl and sda lines. [2] set master transmit mode. [3] issue the start condition. [4] set the first byte (slave address + r/ w ) of transmit data. [5] wait for 1 byte to be transmitted. [6] test the acknowledge transferred from the specified slave device. [7] set the second and subsequent bytes (except for the final byte) of transmit data. [8] wait for icdrt empty. [9] set the last byte of transmit data. [10] wait for last byte to be transmitted. [11] clear the tend flag. [12] clear stop flag. [13] issue the stop condition. [14] wait for the creation of stop condition. [15] set slave receive mode. clear tdre. [12] clear stop in iscr figure 16.17 sample flowch art for master transmit mode
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 342 of 516 rej09b0152-0300 no yes rdrf = 1? no yes rdrf = 1 ? last receive - 1? master receive mode clear tend in icsr clear trs in iccr1 to 0 clear tdre in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 set rcvd in iccr1 to 1 read icdrr read rdrf in icsr write 0 to bbsy and scp read stop in icsr read icdrr clear rcvd in iccr1 to 0 clear mst in iccr1 to 0 end note: * do not activate an interrupt during the execution of steps [1] to [3]. for single-byte reception, skip steps [2] to [6] after step [1]. then, jump to step [7]. dummy-read in step [8]. no yes stop = 1? no yes [1] clear tend, select master receive mode, and then clear tdre. * [2] set acknowledge to the transmit device. * [3] dummy-read icddr. * [4] wait for 1 byte to be received [5] check whether it is the (last receive - 1). [6] read the receive data last. [7] set acknowledge of the final byte. disable continuous reception (rcvd = 1). [8] read the (final byte - 1) of receive data. [9] wait for the last byte to be receive. [10] clear stop flag. [11] issue the stop condition. [12] wait for the creation of stop condition. [13] read the last byte of receive data. [14] clear rcvd. [15] set slave receive mode. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] clear stop in icsr [10] [14] [15] figure 16.18 sample flowch art for master receive mode
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 343 of 516 rej09b0152-0300 tdre=1 ? yes yes no slave transmit mode clear aas in icsr write transmit data in icdrt read tdre in icsr last byte? write transmit data in icdrt read tend in icsr clear tend in icsr clear trs in iccr1 to 0 dummy read icdrr clear tdre in icsr end [1] clear the aas flag. [2] set transmit data for icdrt (except for the last data). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte to be transmitted. [6] clear the tend flag . [7] set slave receive mode. [8] dummy-read icdrr to release the scl line. [9] clear the tdre flag. no no yes tend=1 ? [1] [2] [3] [4] [5] [6] [7] [8] [9] figure 16.19 sample flowchart for slave transmit mode
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 344 of 516 rej09b0152-0300 no yes rdrf = 1? no yes rdrf = 1? last receive - 1? slave receive mode clear aas in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 read icdrr read rdrf in icsr read icdrr end no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. [2] set acknowledge to the transmit device. [3] dummy-read icdrr. [4] wait for 1 byte to be received. [5] check whether it is the (last receive - 1). [6] read the receive data. [7] set acknowledge of the last byte. [8] read the (last byte - 1) of receive data. [9] wait the last byte to be received. [10] read for the last byte of receive data. for single-byte reception, skip steps [2] to [6] after step [1]. then, jump to step [7]. dummy-read in step [8]. figure 16.20 sample flowch art for slave receive mode
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 345 of 516 rej09b0152-0300 16.5 interrupt request there are six interrupt requ ests in this module; transmit data em pty, transmit end, receive data full, nack receive, stop recogn ition, and arbitration lo st/overrun. table 16.3 shows the contents of each interrupt request. table 16.3 interrupt requests interrupt request abbreviat ion interrupt condition i 2 c mode clock synchronous mode transmit data empty txi (tdre = 1) ? (tie = 1) { { transmit end tei (tend = 1) ? (teie = 1) { { receive data full rxi (rdrf = 1) ? (rie = 1) { { stop recognition stpi (stop = 1) ? (stie = 1) { nack receive { arbitration lost/overrun naki {(nackf = 1) + (al = 1)} ? (nakie = 1) { { when interrupt conditions described in table 16.3 are 1 and the i bit in ccr is 0, the cpu executes interrupt exception processing. interrupt sources should be cleared in the exception processing. tdre and tend are automatically cl eared to 0 by writing the transmit data to icdrt. rdrf are automatically cl eared to 0 by readin g icdrr. tdre is set to 1 again at the same time when transmit data is written to icdrt. when tdre is cleared to 0, then an excessive data of one byte may be transmitted.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 346 of 516 rej09b0152-0300 16.6 bit synchronous circuit in master mode, this module has a possibility that high level period may be short in the two states described below. ? when scl is driven to low by the slave device ? when the rising speed of scl is lowered by the load of the scl line (load capacitance or pull- up resistance) therefore, it monitors scl and communicates by bit with synchronization. figure 16.21 shows the timing of the bit synchronous circuit and table 16.4 shows the time when scl output changes from low to hi-z then scl is monitored. scl vih scl monitor timing reference clock internal scl figure 16.21 timing of bit synchronous circuit table 16.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 347 of 516 rej09b0152-0300 16.7 usage notes 16.7.1 note on issuing stop condition and start (re-transmit) condition the stop condition or start (re-transmit) condition should be issued after recognizing the falling edge of the ninth clock. the falling edge of the ninth clock can be recognized by checking the sclo bit in the i2c control register 2 (iccr2). note that if the stop condition or start (re- transmit) condition is issued in a particular timing and the situations shown below, these conditions may not correctly output. 1. the rising edge of the scl becomes less sh arp and longer due to the scl bus load (load capacitor and pull-up resistor) than the period defined in section 16.6, bit synchronous circuit. 2. when the slave device elongates the low level period between the eighth and ninth clocks and activates the bit synchronous circuit. 16.7.2 note on setting wait bit in i2c bus mode register (icmr) the wait bit in the i 2 c bus mode register (icmr) should be set to 0. note that if the wait bit is set to 1, when a slave device holds the scl signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period. 16.7.3 restriction on transfer rate setting in multimaster operation in multimaster operation, if the iic transfer rate setti ng in this lsi is slower than those of the other masters, scl may be output with an unexpected width. to avoid this phenomenon, set the transfer rate by 1/1.8 or faster than the fastest rate of th e other masters. for example, if the fastest transfer rate of the other masters is set to 400 kbps, the iic transfer rate in this lsi should be set to 223 kbps (= 400/1.18) or more.
section 16 i 2 c bus interface 2 (iic2) rev. 3.00 may 15, 2007 page 348 of 516 rej09b0152-0300 16.7.4 restriction on the use of bit ma nipulation instructions for mst and trs setting in multimaster operation in multimaster operation, if the master transmit is set with bit manipulation instructions in the order from the mst bit to the trs bit, the al bit in the icsr register will be set to 1 but the master transmit mode (mst = 1, trs = 1) may be set, depending on the arbitration lost timing. to avoid this phenomenon, the following actions should be performed: ? in multimaster operation, use the mov instruction to set bits mst and trs. ? when arbitration is lost, confirm the contents of bits mst and trs. if the contents are other than mst = 0 and trs = 0, set mst = 0 and trs = 0 again. 16.7.5 usage no te on master receive mode in master receive mode, scl is fixed low on the falling edge of the 8th clock while the rdrf bit is set to 1. when icdrr is read around the falling edge of the 8th clock, the clock is only fixed low in the 8th clock of the next round of data reception. the scl is then released from its fixed state without reading icdrr and the 9th clock is output. as a result, some receive data is lost. to avoid this phenomenon, the following actions should be performed: ? read icdrr in master receive mode befo re the rising edge of the 8th clock. ? set rcvd to 1 in master receive mode and pe rform communication in units of one byte.
section 17 a/d converter adcms3aa_000020020900 rev. 3.00 may 15, 2007 page 349 of 516 rej09b0152-0300 section 17 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to six analog input channels to be selected. the block diagram of the a/d converter is shown in figure 17.1. 17.1 features ? 10-bit resolution ? six input channels ? high-speed conversion: 12.4 s per channel (at 10-mhz operation) ? sample and hold function ? conversion start method a/d conversion can be started by software and external trigger. ? interrupt source an a/d conversion end interrupt request can be generated. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (the a/d converter is halted as th e initial value. for details, refer to section 5.4, module standby function.) multiplexer internal data bus reference voltage + - comparator avcc vss control logic adsr amr adrr irrad an0 an1 an2 an3 an4 an5 adtrg avcc [legend] amr: adsr: adrr: irrad: a/d mode register a/d start register a/d result register a/d conversion end interrupt request flag vss figure 17.1 block di agram of a/d converter
section 17 a/d converter rev. 3.00 may 15, 2007 page 350 of 516 rej09b0152-0300 17.2 input/output pins table 17.1 shows the pin configuration of the a/d converter. table 17.1 pin configuration pin name abbreviation i/o function analog power supply pin avcc input power supply and reference voltage of analog part ground pin vss input ground and reference voltage analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input analog input pin 5 an5 input analog input pins external trigger input pin adtrg input external trigger i nput that controls the a/d conversion start. 17.3 register descriptions the a/d converter has the following registers. ? a/d result register (adrr) ? a/d mode register (amr) ? a/d start register (adsr) 17.3.1 a/d result register (adrr) adrr is a 16-bit read-only register that stores the results of a/d conversion. the data is stored in the upper 10 bits of adrr. adrr can be read by the cpu at any time, but the adrr value during a/d conversion is undefined. after a/d conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. the initial value of adrr is undefined. this register must be read in words.
section 17 a/d converter rev. 3.00 may 15, 2007 page 351 of 518 rej09b0152-0300 17.3.2 a/d mode register (amr) amr sets the a/d conversion time, and selects the external trigger and analog input pins. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 6 trge 0 r/w external trigger select enables or disables the a/d conversion start by the external trigger input. 0: disables the a/d conversion start by the external trigger input. 1: starts a/d conversion at the rising or falling edge of the adtrg pin the edge of the adtrg pin is selected by the adtrgneg bit in iegr. 5 4 cks1 cks0 0 0 r/w r/w clock select select the a/d conversion clock source. 00: /8 (conversion time = 124 states (max.) (reference clock = ) 01: /4 (conversion time = 62 states (max.) (reference clock = ) 10: /2 (conversion time = 31 states (max.) (reference clock = ) 11: w/2 (conversion time = 31 states (max.) (reference clock = sub ) while cks1 and cks0 are all 1 in subactive or subsleep mode, the a/d converter can be used only when the cpu operating clock is w.
section 17 a/d converter rev. 3.00 may 15, 2007 page 352 of 516 rej09b0152-0300 bit bit name initial value r/w description 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 3 to 0 select the analog input channel. 00xx: no channel selected 0100: an0 0101: an1 0110: an2 0111: an3 1000: an4 1001: an5 101x: no channel selected 11xx: no channel selected the channel selection should be made while the adsf bit is cleared to 0. [legend] x: don't care. 17.3.3 a/d start register (adsr) adsr starts and stops the a/d conversion. bit bit name initial value r/w description 7 adsf 0 r/w when this bit is set to 1, a/d conversion is started. when conversion is completed, the converted data is set in adrr and at the same time this bit is cleared to 0. if this bit is written to 0, a/d conversion can be forcibly terminated. 6 lads 0 r/w ladder resistance select 0: ladder resistance operates while the a/d converter is idle. 1: ladder resistance is halt ed while the a/d converter is idle. the ladder resistance is always halted in standby mode, watch mode, or module standby mode, and at a reset. 5 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified.
section 17 a/d converter rev. 3.00 may 15, 2007 page 353 of 518 rej09b0152-0300 17.4 operation the a/d converter operates by su ccessive approximation with 10-bit resolution. wh en changing the conversion time or analog inpu t channel, in order to prevent in correct operation, first clear the bit adsf to 0 in adsr. 17.4.1 a/d conversion 1. a/d conversion is started from the selected channel when the adsf bit in adsr is set to 1, according to software. 2. when a/d conversion is completed, the resu lt is transferred to the a/d result register. 3. on completion of conversion, the irrad flag in irr2 is set to 1. if the ienad bit in ienr2 is set to 1 at this time, an a/d conversion end interrupt request is generated. 4. the adsf bit remains set to 1 during a/d conversion. when a/d conversion ends, the adsf bit is automatically cleared to 0 and the a/d converter enters the wait state. 17.4.2 external tr igger input timing the a/d converter can also start a/d conversion by input of an external trigger signal. external trigger input is enabled at the adtrg pin when the adtstchg bit in pmrb is set to 1* and the trge bit in amr is set to 1. then when the input signal edge designated in the adtrgneg bit in iegr is detected at the adtrg pin, the adsf bit in adsr will be set to 1, starting a/d conversion. figure 17.2 shows the timing. note: * the adtrg input pin is shared with the test pin. therefore when the pin is used as the adtrg pin, reset should be cleared while the 0-fixed signal is input to the test pin. then the adtstchg bit should be set to 1 after the test signal is fixed. adtrg (when adtrgneg = 0) adsf a/d conversion figure 17.2 external trigger input timing
section 17 a/d converter rev. 3.00 may 15, 2007 page 354 of 516 rej09b0152-0300 17.4.3 operating stat es of a/d converter table 17.2 shows the operating states of the a/d converter. table 17.2 operating st ates of a/d converter operating mode reset active sleep watch sub- active sub-sleep standby module standby amr reset functions reta ined retained functions/ retained * 2 retained retained retained adsr reset functions func tions retained functions/ retained * 2 functions/ retained * 2 retained retained adrr retained * 1 functions functions retained functions/ retained * 2 functions/ retained * 2 retained retained notes: 1. undefined at a power-on reset. 2. function if w/2 is selected as the internal clock. halted and retained otherwise. 17.5 example of use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 17.3 shows the operation timing. 1. bits ch3 to ch0 in the a/d mode register (amr) are set to 0101, making pin an1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is completed, bit irrad is set to 1, and the a/d conversion result is stored in adrr. at the same time bit adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if bit adsf is set to 1 again afterward, a/d conv ersion starts and steps 2 through 6 take place.
section 17 a/d converter rev. 3.00 may 15, 2007 page 355 of 518 rej09b0152-0300 figures 17.4 and 17.5 show flowcharts of procedures for using the a/d converter. interrupt (irrad) ienad adsf adrr channel 1 (an1) operating state note: * indicates instruction execution by software. set * set * a/d conversion starts idle idle idle a/d conversion (1) a/d conversion (2) set * a/d conversion result (1) read conversion result a/d conversion result (2) read conversion result figure 17.3 example of a/d conversion operation
section 17 a/d converter rev. 3.00 may 15, 2007 page 356 of 516 rej09b0152-0300 start set a/d conversion speed and input channel disable a/d conversion end interrupt start a/d conversion perform a/d conversion? end read adsr adsf = 0? read adrr data yes yes no no figure 17.4 flowchart of procedure for using a/d converter (polling by software) set a/d conversion speed and input channel start enable a/d conversion end interrupt start a/d conversion clear irrad bit in irr2 to 0 read adrr data a/d conversion end interrupt generated? perform a/d conversion? end no no yes yes figure 17.5 flowchart of procedure fo r using a/d converter (interrupts used)
section 17 a/d converter rev. 3.00 may 15, 2007 page 357 of 518 rej09b0152-0300 17.6 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 17.6). ? offset error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 17.7). ? full-scale error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 17.7). ? nonlinearity error the error with respect to the ideal a/d conve rsion characteristics between zero voltage and full-scale voltage. does not include offset error, full-scal e error, or quantization error. ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error.
section 17 a/d converter rev. 3.00 may 15, 2007 page 358 of 516 rej09b0152-0300 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 17.6 a/d conversio n accuracy definitions (1) fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 17.7 a/d conversio n accuracy definitions (2)
section 17 a/d converter rev. 3.00 may 15, 2007 page 359 of 518 rej09b0152-0300 17.7 usage notes 17.7.1 permissible si gnal source impedance this lsi's analog input is designed such that conv ersion accuracy is guarant eed for an input signal for which the signal source impedance is 10 k ? or less. this specification is provided to enable the a/d converter's sample-and-hol d circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversion accuracy. however, with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog sign al with a large differenti al coefficient (e.g., 5 mv/ s or greater) (see figure 17.8). when conv erting a high-speed analog signal, a low- impedance buffer should be inserted. 17.7.2 influences on absolute accuracy adding capacitance results in coupling with gn d, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. 48 pf 10 k ? c in = 15 pf sensor output impedance to 10 k ? this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 17.8 example of analog input circuit
section 17 a/d converter rev. 3.00 may 15, 2007 page 360 of 516 rej09b0152-0300 17.7.3 usage notes 1. adrr should be read on ly when the adsf bit in adsr is cleared to 0. 2. changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. 3. when a/d conversion is started after clearing module standby mode, wait for 10 clock cycles before starting a/d conversion.
section 18 comparators adcms3aa_000020020900 rev. 3.00 may 15, 2007 page 361 of 516 rej09b0152-0300 section 18 comparators this lsi includes comparators to compare the input voltage and reference voltage. the block diagram of the comparators is shown in figure 18.1. 18.1 features ? reference voltage can be specified as internal power supply or external input (vcref). ? when the internal power supply is selected as the reference voltage, programmable selection of sixteen types of voltages is possible. ? when the internal power supply is selected, the hysteresis characteristics of the comparison result can be selected. ? two analog input channels each channel includes its own comparator. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (a comparator is halted as the in itial value. for details, refer to section 5.4, module standby function.) comp0 comp1 vcref 26/30 25/30 24/30 10/30 9/30 4r r r r 9r cmdr cmcr0 cmcr1 comparator selector interrupt generator interrupt request [legend] cmdr: cmcr0: cmcr1: compare data register compare control register 0 compare control register 1 + - comparator + - selector internal data bus figure 18.1 block diagram of comparators
section 18 comparators rev. 3.00 may 15, 2007 page 362 of 516 rej09b0152-0300 18.2 input/output pins table 18.1 shows the pin configuration of the comparators. table 18.1 pin configuration pin name abbreviation i/o function comparator reference voltage vcref input comparator reference voltage pin (external input) analog input channel 0 comp0 input comparator analog input pin 0 analog input channel 1 comp1 input comparator analog input pin 1 18.3 register descriptions the comparators have the following registers. for details on register addresses and register states during each processing, refer to section 20, list of registers. ? ? bit bit name initial value r/w description 7 cme 0 r/w comparator enable 0: comparator halted 1: comparator operates 6 cmie 0 r/w comparator interrupt enable 0: disables a comparator interrupt 1: enables a comparator interrupt 5 cmr 0 r/w comparator re ference voltage select 0: selects internal power supply as reference voltage 1: reference voltage is input from vcref pin for the combination of the cmr and cmls bits.
section 18 comparators rev. 3.00 may 15, 2007 page 363 of 518 rej09b0152-0300 bit bit name initial value r/w description 4 cmls 0 r/w comparator hysteresis select 0: selects non-hysteresis 1: selects hysteresis when cmr = 1, clear this bit to 0. for the combination of the cmr and cmls bits. 3 2 1 0 crs3 crs2 crs1 crs0 0 0 0 0 r/w r/w r/w r/w internal reference voltage select when cmr = 0 and cmls = 0, t he electric potential of v il is selected as the internal power supply. when cmr = 0 and cmls = 1, v il will be as follows. when cmr = 1, crs3 to crs0 settings are disabled. vih vil 0000: 11/30vcc 9/30vcc 0001: 12/30vcc 10/30vcc 0010: 13/30vcc 11/30vcc 0011: 14/30vcc 12/30vcc 0100: 15/30vcc 13/30vcc 0101: 16/30vcc 14/30vcc 0110: 17/30vcc 15/30vcc 0111: 18/30vcc 16/30vcc 1000: 19/30vcc 17/30vcc 1001: 20/30vcc 18/30vcc 1010: 21/30vcc 19/30vcc 1011: 22/30vcc 20/30vcc 1100: 23/30vcc 21/30vcc 1101: 24/30vcc 22/30vcc 1110: 25/30vcc 23/30vcc 1111: 26/30vcc 24/30vcc for the selectable range by the crs bits, see section 21, electrical characteristics.
section 18 comparators rev. 3.00 may 15, 2007 page 364 of 516 rej09b0152-0300 table 18.2 combination of cmr and cmls bits cmr cmls function 0 compares the internal power supply (voltage set for v ih by the crs3 to crs0 bits) and electric potential of the comp pin. no hysteresis. 0 1 compares the internal power s upply and electric potential of the comp pin. with hysteresis. v ih and v il are set by the crs3 to crs0 bits. 0 compares the electric potent ial of the vcref and comp pins. no hysteresis. 1 1 setting prohibited 18.3.2 compare data register (cmdr) cmdr stores the result of comparing the analog input pin and reference voltage. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 cmf1 0 r/(w) * 1 comp1 interrupt flag [setting condition] when comp1 interrupt occurs [clearing condition] 0 is written to cmf1 after reading cmf1 = 1 4 cmf0 0 r/(w) * 1 comp0 interrupt flag [setting condition] when comp0 interrupt occurs [clearing condition] 0 is written to cmf0 after reading cmf0 = 1 3, 2 ? all 0 ? reserved these bits are always read as 0.
section 18 comparators rev. 3.00 may 15, 2007 page 365 of 518 rej09b0152-0300 bit bit name initial value r/w description 1 cdr1 ? * 2 r [setting condition] comp1 pin > reference voltage [clearing condition] comp1 pin reference voltage 0 cdr0 ? * 2 r [setting condition] comp0 pin > reference voltage [clearing condition] comp0 pin reference voltage notes: 1. only 0 can be wr itten to clear the flag. 2. depends on the pin state and reference voltage. 18.4 operation 18.4.1 operation sequence the operation sequence of a comparator is as follows: 1. when using vcref, the pins to be used are enabled by the corresponding port mode registers. for details, see section 8, i/o ports. 2. select the reference voltage (cmr setting: internal power supply or vcref). when the internal power supply is selected as the reference voltage, select the hysteresis characteristics (cmls setting) and refere nce voltage (crs3 to crs0 setting). 3. set the comparator enable bit (cme). 4. after setting cme, wait for the conversion ti me (see section 21, electrical characteristics) so that the comparator becomes stabilized. 5. read from cdr. 6. after reading the cmf flag, write 0 to it (reading the cmf flag can be performed simultaneously with step 5). 7. if an interrupt is to be generated, set the comparator interrupt enable bit (cmie). note: steps 2 and 3 can be done simultaneously by writing to the entire register.
section 18 comparators rev. 3.00 may 15, 2007 page 366 of 516 rej09b0152-0300 18.4.2 hysteresis characteristics of comparator figure 18.2 shows cdr when hysteresis is or is not selected by the cmls bit cmcr and the input voltage to the comp pins. the hysteresis ch aracteristics for the comp arison result (cdr) by the comparator can be selected by the cmls bit, as shown in figure 18.2. when cmr = 0 and crs3 to crs0 = b'1000 (vih = 19/30vcc, vil = 17/30vcc) comp pin input voltage 19/30 vcc 17/30 vcc cdr (cmls = 0) cdr (cmls = 1) figure 18.2 hysteresis/non-h ysteresis selection by cdr 18.4.3 interrupt setting when the cdr bit is read while the comparator interrupt is enabled and both the cme and cmie bits are set to 1, it is latched in the internal la tch. when a difference occu rs between the output of the latch and the cdr bit, the interrupt is generated. while the cdr bit is being read, the interrupt is masked.
section 18 comparators rev. 3.00 may 15, 2007 page 367 of 518 rej09b0152-0300 to set the interrupt, follow the procedure shown in figure 18.3 or 18.4. [1] [3] [2] [4] [4] [5] [6] [5] [6] [6] [6] [6] [6] [7] [7] set the cme bit. wait a conversion time for the comparator stabilized. read the cdr bit. set the cmie bit. read the cdr bit. at this time, the cdr bit is latched in the internal latch for the comparator and the internal interrupt enable signal is asserted. as the relationship between the voltage on the comp pin and reference voltage is changed, a difference occurs between the output level of the internal latch and the cdr bit. then an interrupt is generated. clear the cmf bit in the interrupt handler. when reading the cmf bit for clearing it, the cdr bit is also read since those bits are in the same register. therefore, the output of the internal latch is updated. go to step [5] to continue use of the interrupt. clear the cmie bit to clear the interrupt setting and clear the cme bit to stop the comparator. clearing the cmie bit negates the internal interrupt enable signal. the interrupt flag may be set depending on the internal states of the comparator, pin states, the timing of setting the internal interrupt enable signal shown in step [4], and the timing of the cdr bit latched. to avoid this, execute steps [2] to [4] continuously or ensure that the cmf bit is cleared using the i bit in ccr as shown in figure 18.4. [1] [2] [3] [4] [5] [6] [7] when cmr = 0 and cmrs3 to cmrs0 = b'1000 (vih = 19/30 vcc) voltage on comp pin conversion time conversion time cdr (cmls = 0) cme cmie interrupt enable signal stabilization time (conversion time) cdr read signal internal latch for comparator cmf unstable 19/30 vcc figure 18.3 procedure for setting interrupt (1)
section 18 comparators rev. 3.00 may 15, 2007 page 368 of 516 rej09b0152-0300 disable interrupts by the i bit. set the comparator enable bit to 1. wait for the comparator stabilized. enable the interrupt. actually, the interrupt is masked by the i bit. the cdr bit is latched in the internal latch by reading it. clear the interrupt request flag. enable interrupts by the i bit. set i bit in ccr to 1 set cme bit to 1 set cmie bit to 1 read cdr bit clear cmf bit clear i bit in ccr to 0 figure 18.4 procedure for setting interrupt (2) 18.5 usage notes 1. the comp pin whose channel is operating as a comparator becomes a comparator analog input pin. it cannot be used for any other function. 2. when external input is used as the reference voltage (cmr0 = 1 or cmr1 = 1), the vcref pin cannot be used for any other function. 3. to stop the operation of a comparator, cl ear the cme0 and cme1 bits in cmcr0 and cmcr1 to 0, before clearing the compckstp bit in ckstpr2 to 0. 4. if the lsi enters the standby mode or watch mo de when a comparator is operating, the internal operation of the comparator is maintained. sin ce the comparator operates even in standby mode or watch mode, it returns to the same mo de after the specified interrupt is canceled, though the current for the comparator is consumed. if a comparator is not required to return to the standby mode or watch mode when an interrupt is canceled and the current consumption needs to be reduced, stop the co mparator by clearing the cme0 and cme1 bits in cmcr0 and cmcr1 to 0 before shifting the mode.
section 19 power-on reset circuit rev. 3.00 may 15, 2007 page 369 of 516 rej09b0152-0300 section 19 power-on reset circuit this lsi has an on-chip power-on reset circuit. a block diagram of the power-on reset circuit is shown in figure 19.1. 19.1 feature ? power-on reset circuit an internal reset signal is generated at turning the power on by externally connecting a capacitor. res voltage detector c res rp vcc vcc 3-bit counter internal reset signal r s q ck r cout figure 19.1 power-on reset circuit
section 19 power-on reset circuit rev. 3.00 may 15, 2007 page 370 of 516 rej09b0152-0300 19.2 operation 19.2.1 power-on reset circuit the operation timing of the power-on reset circuit is shown in figure 19.2. as the power supply voltage rises, the capacitor, whic h is externally connected to the res pin, is gradually charged through the on-chip pull-up resistor (rp). the low level of the res pin is sent to the lsi and the whole lsi is reset. when the level of the res pin reaches to the predet ermined level, a voltage detection circuit detects it. then a 3-bit counter starts counting up. when the 3-bit counter counts for 8 times, an overflow signal is generated and an internal reset signal is negated. the capacitance (c res ) which is connected to the res pin can be computed using the following formula; where the res rising time is t. for the on-chip resi stor (rp), see sect ion 21, electrical characteristics. the power supply rising time (t_vtr) should be shorter than half the res rising time (t). the res rising time (t) is also should be longer than the oscillation stabilization time (trc). t c res = (t > trc, t > t_vtr 2) rp note that the power supply voltage (vcc) must fall below vpor = 100 mv and rise after charge on the res pin is removed. to remove charge on the res pin, it is recommended that the diode should be placed near vcc. if the power supply vo ltage (vcc) rises from the point above vpor, a power-on reset may not occur. vcc t_vtr t_vtr 2 v_rst t_cr t_out (eight states) res internal reset signal figure 19.2 power-on rese t circuit operation timing
section 20 list of registers rev. 3.00 may 15, 2007 page 371 of 516 rej09b0152-0300 section 20 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? registers are classified by functional modules. ? the data bus width is indicated. ? the number of access states is indicated. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? when the bit number is in the bit name column, it indicates that the entire register is allocated to a counter or data. ? when registers consist of 16 bits, bits are described from the msb side. 3. register states in each operating mode ? register states are described in the sa me order as the register addresses. ? the register states described here are for the basic operating mode s. if there is a specific reset for an on-chip peripheral module, refer to th e section on that on-chip peripheral module.
section 20 list of registers rev. 3.00 may 15, 2007 page 372 of 516 rej09b0152-0300 20.1 register addresses (address order) the data bus width indicates the number of bits by which the register is accessed. the number of access states indicates the number of states based on the sp ecified reference clock. register name abbre- viation address module name data bus width access state flash memory control register 1 flmcr1 h'f020 rom 8 2 flash memory control register 2 flmcr2 h'f021 rom 8 2 flash memory power control register flpwcr h'f022 rom 8 2 erase block register 1 ebr1 h'f023 rom 8 2 flash memory enable register fenr h'f02b rom 8 2 rtc interrupt flag register rtcflg h'f067 rtc 8 2 second data register/free running counter data register rsecdr h'f068 rtc 8 2 minute data register rmindr h'f069 rtc 8 2 hour data register rhrdr h'f06a rtc 8 2 day-of-week data register rwkdr h'f06b rtc 8 2 rtc control register 1 rtccr1 h'f06c rtc 8 2 rtc control register 2 rtccr2 h'f06d rtc 8 2 clock source select regist er rtccsr h'f06f rtc 8 2 i 2 c bus control register 1 iccr1 h'f078 iic2 8 2 i 2 c bus control register 2 iccr2 h'f079 iic2 8 2 i 2 c bus mode register icmr h'f07a iic2 8 2 i 2 c bus interrupt enable register icier h'f07b iic2 8 2 i 2 c bus status register icsr h'f07c iic2 8 2 slave address register sar h'f07d iic2 8 2 i 2 c bus transmit data register icdrt h'f07e iic2 8 2 i 2 c bus receive data regist er icdrr h'f07f iic2 8 2
section 20 list of registers rev. 3.00 may 15, 2007 page 373 of 516 rej09b0152-0300 register name abbre- viation address module name data bus width access state port function control regist er pfcr h'f085 system 8 2 port pull-up control register 8 pucr8 h'f086 i/o ports 8 2 port pull-up control register 9 pucr9 h'f087 i/o ports 8 2 port open-drain control register 9 podr9 h'f08c i/o ports 8 2 timer mode register b1 tmb1 h'f0d0 timer b1 8 2 timer counter b1/ timer load register b1 tcb1 (r)/ tlb1 (w) h'f0d1 timer b1 8 2 compare control register 0 cmcr0 h'f0dc comparator 8 2 compare control register 1 cmcr1 h'f0dd comparator 8 2 compare data register cm dr h'f0de comparator 8 2 ss control register h sscrh h'f0e0 ssu * 1 8 3 ss control register l sscrl h'f0e1 ssu * 1 8 3 ss mode register ssmr h'f0e2 ssu * 1 8 3 ss enable register sser h'f0e3 ssu * 1 8 3 ss status register sssr h'f0e4 ssu * 1 8 3 ss receive data register ssrdr h'f0e9 ssu * 1 8 3 ss transmit data register sstdr h'f0eb ssu * 1 8 3 timer mode register w tmrw h'f0f0 timer w 8 2 timer control register w tcrw h'f0f1 timer w 8 2 timer interrupt enable register w tierw h'f0f2 timer w 8 2 timer status register w tsrw h'f0f3 timer w 8 2 timer i/o control register 0 tior0 h'f0f4 timer w 8 2 timer i/o control register 1 tior1 h'f0f5 timer w 8 2 timer counter tcnt h'f0f6 timer w 16 2 general register a gra h'f0f8 timer w 16 2 general register b grb h'f0fa timer w 16 2 general register c grc h'f0fc timer w 16 2 general register d grd h'f0fe timer w 16 2
section 20 list of registers rev. 3.00 may 15, 2007 page 374 of 516 rej09b0152-0300 register name abbre- viation address module name data bus width access state event counter pwm compare register ecpwcr h'ff8c aec * 2 16 2 event counter pwm data register ecpwdr h'ff8e aec * 2 16 2 serial port control register spcr h'ff91 sci3 8 2 input pin edge select register aegsr h'ff92 aec * 2 8 2 event counter control register eccr h'ff94 aec * 2 8 2 event counter control/status register eccsr h'ff95 aec * 2 8 2 event counter h ech h'ff96 aec * 2 8 2 event counter l ecl h'ff97 aec * 2 8 2 serial mode register 3 smr3 h'ff98 sci3 8 3 bit rate register 3 brr3 h'ff99 sci3 8 3 serial control register 3 scr3 h'ff9a sci3 8 3 transmit data register 3 tdr3 h'ff9b sci3 8 3 serial status register 3 ssr3 h'ff9c sci3 8 3 receive data register 3 rdr3 h'ff9d sci3 8 3 serial extended mode register semr h'ffa6 sci3 8 3 irda control register ircr h'ffa7 irda 8 2 timer mode register wd tmwd h'ffb0 wdt * 3 8 2 timer control/status register wd1 tcsrwd1 h'ffb1 wdt * 3 8 2 timer control/status register wd2 tcsrwd2 h'ffb2 wdt * 3 8 2 timer counter wd tcwd h'ffb3 wdt * 3 8 2 a/d result register adrr h'ffbc a/d converter 16 2 a/d mode register amr h'ffbe a/d converter 8 2 a/d start register adsr h'ffbf a/d converter 8 2
section 20 list of registers rev. 3.00 may 15, 2007 page 375 of 516 rej09b0152-0300 register name abbre- viation address module name data bus width access state port mode register 1 pmr1 h'ffc0 i/o ports 8 2 port mode register 3 pmr3 h'ffc2 i/o ports 8 2 port mode register b pmrb h'ffca i/o ports 8 2 port data register 1 pdr1 h'ffd4 i/o ports 8 2 port data register 3 pdr3 h'ffd6 i/o ports 8 2 port data register 8 pdr8 h'ffdb i/o ports 8 2 port data register 9 pdr9 h'ffdc i/o ports 8 2 port data register b pdrb h'ffde i/o ports 8 2 port pull-up control register 1 pucr1 h'ffe0 i/o ports 8 2 port pull-up control register 3 pucr3 h'ffe1 i/o ports 8 2 port control register 1 pcr1 h'ffe4 i/o ports 8 2 port control register 3 pcr3 h'ffe6 i/o ports 8 2 port control register 8 pcr8 h'ffeb i/o ports 8 2 port control register 9 pcr9 h'ffec i/o ports 8 2 system control register 1 syscr1 h'fff0 system 8 2 system control register 2 syscr2 h'fff1 system 8 2 interrupt edge select register iegr h'fff2 interrupts 8 2 interrupt enable register 1 ienr1 h'fff3 interrupts 8 2 interrupt enable register 2 ienr2 h'fff4 interrupts 8 2 oscillator control register osccr h'fff5 system 8 2 interrupt flag register 1 irr1 h'fff6 interrupts 8 2 interrupt flag register 2 irr2 h'fff7 interrupts 8 2 clock stop register 1 ckst pr1 h'fffa system 8 2 clock stop register 2 ckst pr2 h'fffb system 8 2 notes: 1. ssu: synchronous serial communication unit 2. aec: asynchronous event counter 3. wdt: watchdog timer
section 20 list of registers rev. 3.00 may 15, 2007 page 376 of 516 rej09b0152-0300 20.2 register bits register bit names of the on-chip peripheral modules are described below. the 16-bit register is indicated in two rows, 8 bits for each row. register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name flmcr1 ? swe esu psu ev pv e p flmcr2 fler ? ? ? ? ? ? ? flpwcr pdwnd ? ? ? ? ? ? ? ebr1 ? ? ? eb4 eb3 eb2 eb1 eb0 fenr flshe ? ? ? ? ? ? ? rom rtcflg foifg wkifg dyifg hrifg mnifg 1seifg 05seifg 025seifg rsecdr bsy sc12 sc11 sc 10 sc03 sc02 sc01 sc00 rmindr bsy mn12 mn11 mn 10 mn03 mn02 mn01 mn00 rhrdr bsy ? hr11 hr10 hr03 hr02 hr01 hr00 rwkdr bsy ? ? ? ? wk2 wk1 wk0 rtccr1 run 12/24 pm rst int ? ? ? rtccr2 foie wkie dyie hrie mnie 1seie 05seie 025seie rtccsr ? rcs6 rcs5 sub32k rcs3 rcs2 rcs1 rcs0 rtc iccr1 ice rcvd mst trs cks3 cks2 cks1 cks0 iccr2 bbsy scp sdao sdaop sclo ? iicrst ? icmr mls wait ? ? bcwp bc2 bc1 bc0 icier tie teie rie naki e stie acke ackbr ackbt icsr tdre tend rdrf nackf stop al/ove aas adz sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs icdrt icdrt7 icdrt6 icdrt5 icdrt 4 icdrt3 icdrt2 icdrt1 icdrt0 icdrr icdrr7 icdrr6 icdrr5 icdrr4 icdrr3 icdrr2 icdrr1 icdrr0 iic2 pfcr ? ? ? ssus irq1s1 irq1s0 ir q0s1 irq0s0 system pucr8 ? ? ? pucr84 pucr83 pucr82 ? ? pucr9 ? ? ? ? pucr93 pucr92 pucr91 pucr90 podr9 ? ? ? ? p93odr p92odr p91odr p90odr i/o ports tmb1 tmb17 tmb16 ? ? ? tmb12 tmb11 tmb10 tcb1 (r)/ tlb1 (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 timer b1
section 20 list of registers rev. 3.00 may 15, 2007 page 377 of 516 rej09b0152-0300 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name cmcr0 cme0 cmie0 cmr0 cmls0 crs03 crs02 crs01 crs00 cmcr1 cme1 cmie1 cmr1 cmls1 crs13 crs12 crs11 crs10 cmdr ? ? cmf1 cmf0 ? ? cdr1 cdr0 comparator sscrh mss bide soos sol solp scks css1 css0 sscrl ? ssums sres sckos csos ? ? ? ssmr mls cpos cphs ? ? cks2 cks1 cks0 sser te re rsstp ? teie tie rie ceie sssr ? orer ? ? tend tdre rdrf ce ssrdr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sstdr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssu * 1 tmrw cts ? bufeb bufea ? pwmd pwmc pwmb tcrw cclr cks2 cks1 cks0 tod toc tob toa tierw ovie ? ? ? imied imiec imieb imiea tsrw ovf ? ? ? imfd imfc imfb imfa tior0 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tior1 ? iod2 iod1 iod 0 ? ioc2 ioc1 ioc0 tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 tcnt tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 gra15 gra14 gra13 gra12 gra11 gra10 gra9 gra8 gra gra7 gra6 gra5 gra4 gra3 gra2 gra1 gra0 grb15 grb14 grb13 grb12 grb11 grb10 grb9 grb8 grb grb7 grb6 grb5 grb4 grb3 grb2 grb1 grb0 grc15 grc14 grc13 grc12 grc11 grc10 grc9 grc8 grc grc7 grc6 grc5 grc4 grc3 grc2 grc1 grc0 grd15 grd14 grd13 grd12 grd11 grd10 grd9 grd8 grd grd7 grd6 grd5 grd4 grd3 grd2 grd1 grd0 timer w ecpwcr15 ecpwcr14 ecpwcr13 ecpwcr12 e cpwcr11 ecpwcr10 ecpwcr9 ecpwcr8 ecpwcr ecpwcr7 ecpwcr6 ecpwcr5 ecpwcr4 ecpwcr3 ecpwcr2 ecpwcr1 ecpwcr0 ecpwdr15 ecpwdr14 ecpwdr13 ecpwdr12 e cpwdr11 ecpwdr10 ecpwdr9 ecpwdr8 ecpwdr ecpwdr7 ecpwdr6 ecpwdr5 ecpwdr4 ecpwdr3 ecpwdr2 ecpwdr1 ecpwdr0 aec * 2
section 20 list of registers rev. 3.00 may 15, 2007 page 378 of 516 rej09b0152-0300 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name spcr ? ? ? spc3 ? ? scinv1 scinv0 sci3 aegsr ahegs1 ahegs0 alegs1 alegs0 aiegs1 aiegs0 ecpwme ? eccr ackh1 ackh0 ackl1 ac kl0 pwck2 pwck1 pwck0 ? eccsr ovh ovl ? ch2 cueh cuel crch crcl ech ech7 ech6 ech5 ech4 ech3 ech2 ech1 ech0 ecl ecl7 ecl6 ecl5 ecl4 ecl3 ecl2 ecl1 ecl0 aec * 2 smr3 com chr pe pm stop mp cks1 cks0 brr3 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0 tdr3 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr3 tdre rdrf oer fer per tend mpbr mpbt rdr3 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 semr ? ? ? ? abcs ? ? ? sci3 ircr ire ircks2 ircks1 ircks0 ? ? ? ? irda tmwd ? ? ? ? cks3 cks2 cks1 cks0 tcsrwd1 b6wi tcwe b4wi tcsrwe b2wi wdon b0wi wrst tcsrwd2 ovf b5wi wt/ it b3wi ieovf ? ? ? tcwd tcw7 tcw6 tcw5 tcw4 tcw3 tcw2 tcw1 tcw0 wdt * 3 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adrr adr1 adr0 ? ? ? ? ? ? amr ? trge cks1 cks0 ch3 ch2 ch1 ch0 adsr adsf lads ? ? ? ? ? ? a/d converter pmr1 ? ? irqaec ftci aevl clkout tmow aevh pmr3 ? ? ? ? ? ? ? vcref pmrb ? ? ? ? adtstchg ? irq1 irq0 pdr1 ? ? ? ? ? p12 p11 p10 pdr3 ? ? ? ? ? p32 p31 p30 pdr8 ? ? ? p84 p83 p82 ? ? pdr9 ? ? ? ? p93 p92 p91 p90 pdrb ? ? pb5 pb4 pb3 pb2 pb1 pb0 pucr1 ? ? ? ? ? pucr12 pucr11 pucr10 i/o ports
section 20 list of registers rev. 3.00 may 15, 2007 page 379 of 516 rej09b0152-0300 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pucr3 ? ? ? ? ? pucr32 pucr31 pucr30 pcr1 ? ? ? ? ? pcr12 pcr11 pcr10 pcr3 ? ? ? ? ? pcr32 pcr31 pcr30 pcr8 ? ? ? pcr84 pcr83 pcr82 ? ? pcr9 ? ? ? ? pcr93 pcr92 pcr91 pcr90 i/o ports syscr1 ssby sts2 sts1 sts0 lson tma3 ma1 ma0 syscr2 ? ? ? nesel dton mson sa1 sa0 system iegr nmieg ? adtrgneg ? ? ? ieg1 ieg0 ienr1 ienrtc ? ? ? ? ienec2 ien1 ien0 ienr2 ? ienad ? ? ? ientb1 ? ienec interrupts osccr substp rfcut subsel ? ? ? oscf ? system irr1 ? ? ? ? ? irrec2 irri1 irri0 irr2 ? irrad ? ? ? irrtb1 ? irrec interrupts ckstpr1 ? s3ckstp ? adckstp ? tb1ckstp fromckstp rtcckstp ckstpr2 ? twckstp iicckstp ssuckstp aecckstp wdckstp compckstp ? system notes: 1. ssu: synchronous serial communication unit 2. aec: asynchronous event counter 3. wdt: watchdog timer
section 20 list of registers rev. 3.00 may 15, 2007 page 380 of 516 rej09b0152-0300 20.3 register states in each operating mode register abbreviation reset active sleep watch subactive subsleep standby module flmcr1 initialized ? ? ? ? ? initialized flmcr2 initialized ? ? ? ? ? ? flpwcr initialized ? ? ? ? ? ? ebr1 initialized ? ? ? ? ? initialized fenr initialized ? ? ? ? ? ? rom rtcflg ? ? ? ? ? ? ? rsecdr ? ? ? ? ? ? ? rmindr ? ? ? ? ? ? ? rhrdr ? ? ? ? ? ? ? rwkdr ? ? ? ? ? ? ? rtccr1 ? ? ? ? ? ? ? rtccr2 ? ? ? ? ? ? ? rtccsr initialized ? ? ? ? ? ? rtc iccr1 initialized ? ? ? ? ? ? iccr2 initialized ? ? ? ? ? ? icmr initialized ? ? ? ? ? ? icier initialized ? ? ? ? ? ? icsr initialized ? ? ? ? ? ? sar initialized ? ? ? ? ? ? icdrt initialized ? ? ? ? ? ? icdrr initialized ? ? ? ? ? ? iic2 pfcr initialized ? ? ? ? ? ? system pucr8 initialized ? ? ? ? ? ? pucr9 initialized ? ? ? ? ? ? podr9 initialized ? ? ? ? ? ? i/o ports tmb1 initialized ? ? ? ? ? ? tcb1/tlb1 initialized ? ? ? ? ? ? timer b1
section 20 list of registers rev. 3.00 may 15, 2007 page 381 of 516 rej09b0152-0300 register abbreviation reset active sleep watch subactive subsleep standby module cmcr0 initialized ? ? ? ? ? ? cmcr1 initialized ? ? ? ? ? ? cmdr initialized ? ? ? ? ? ? comparator sscrh initialized ? ? ? ? ? ? sscrl initialized ? ? ? ? ? ? ssmr initialized ? ? ? ? ? ? sser initialized ? ? ? ? ? ? sssr initialized ? ? ? ? ? ? ssrdr initialized ? ? ? ? ? ? sstdr initialized ? ? ? ? ? ? ssu * 1 tmrw initialized ? ? ? ? ? ? tcrw initialized ? ? ? ? ? ? tierw initialized ? ? ? ? ? ? tsrw initialized ? ? ? ? ? ? tior0 initialized ? ? ? ? ? ? tior1 initialized ? ? ? ? ? ? tcnt initialized ? ? ? ? ? ? gra initialized ? ? ? ? ? ? grb initialized ? ? ? ? ? ? grc initialized ? ? ? ? ? ? grd initialized ? ? ? ? ? ? timer w ecpwcr initialized ? ? ? ? ? ? ecpwdr initialized ? ? ? ? ? ? aec * 2 spcr initialized ? ? ? ? ? ? sci3 aegsr initialized ? ? ? ? ? ? eccr initialized ? ? ? ? ? ? eccsr initialized ? ? ? ? ? ? ech initialized ? ? ? ? ? ? ecl initialized ? ? ? ? ? ? aec * 2
section 20 list of registers rev. 3.00 may 15, 2007 page 382 of 516 rej09b0152-0300 register abbreviation reset active sleep watch subactive subsleep standby module smr3 initialized ? ? initialized ? ? initialized brr3 initialized ? ? initialized ? ? initialized scr3 initialized ? ? initialized ? ? initialized tdr3 initialized ? ? initialized ? ? initialized ssr3 initialized ? ? initialized ? ? initialized rdr3 initialized ? ? initialized ? ? initialized semr initialized ? ? initialized ? ? initialized sci3 ircr initialized ? ? initialized ? ? initialized irda tmwd initialized ? ? ? ? ? ? tcsrwd1 initialized ? ? ? ? ? ? tcsrwd2 initialized ? ? ? ? ? ? tcwd initialized ? ? ? ? ? ? wdt * 3 adrr ? ? ? ? ? ? ? amr initialized ? ? ? ? ? ? adsr initialized ? ? ? ? ? ? a/d converter pmr1 initialized ? ? ? ? ? ? pmr3 initialized ? ? ? ? ? ? pmrb initialized ? ? ? ? ? ? pdr1 initialized ? ? ? ? ? ? pdr3 initialized ? ? ? ? ? ? pdr8 initialized ? ? ? ? ? ? pdr9 initialized ? ? ? ? ? ? pdrb initialized ? ? ? ? ? ? pucr1 initialized ? ? ? ? ? ? pucr3 initialized ? ? ? ? ? ? pcr1 initialized ? ? ? ? ? ? pcr3 initialized ? ? ? ? ? ? pcr8 initialized ? ? ? ? ? ? pcr9 initialized ? ? ? ? ? ? i/o ports
section 20 list of registers rev. 3.00 may 15, 2007 page 383 of 516 rej09b0152-0300 register abbreviation reset active sleep watch subactive subsleep standby module syscr1 initialized ? ? ? ? ? ? syscr2 initialized ? ? ? ? ? ? system iegr initialized ? ? ? ? ? ? ienr1 initialized ? ? ? ? ? ? ienr2 initialized ? ? ? ? ? ? interrupts osccr initialized ? ? ? ? ? ? system irr1 initialized ? ? ? ? ? ? irr2 initialized ? ? ? ? ? ? interrupts ckstpr1 initialized ? ? ? ? ? ? ckstpr2 initialized ? ? ? ? ? ? system notes: ? is not initialized. 1 . ssu: synchronous serial communication unit 2. aec: asynchronous event counter 3. wdt: watchdog timer
section 20 list of registers rev. 3.00 may 15, 2007 page 384 of 516 rej09b0152-0300
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 385 of 516 rej09b0152-0300 section 21 electrical characteristics 21.1 absolute maximum ratings for f-ztat version table 21.1 lists the absolute maximum ratings. table 21.1 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +4.3 v * 1 analog power supply voltage av cc ?0.3 to +4.3 v input voltage other than port b v in ?0.3 to v cc +0.3 v port b av in ?0.3 to av cc +0.3 v operating temperature t opr ?20 to +75 (general specifications) * 2 c ?40 to +85 (wide temperature range specifications) * 2 storage temperature t stg ?55 to +125 c notes: 1. permanent damage may occur to the lsi if absolute maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. the operating temperature range for fl ash memory programming/erasing is t a = 0 to +75c.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 386 of 516 rej09b0152-0300 21.2 electrical characteristics for f-ztat version 21.2.1 power supply volt age and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 38.4 1.8 3.6 2.7 vcc (v) f w (khz) all operating modes refer to note all operating modes 32.768 81.25 1.8 3.6 2.7 vcc (v) f w (khz) 9.375 r osc /32 used (reference value) all operating modes 81.25 1.8 3.6 2.7 vcc (v) f w (khz) 9.375 r osc /32 used (reference value) all operating modes refer to note 38.4 1.8 3.6 2.7 vcc (v) f w (khz) 32.768 note: * when using a resonator, hold the vcc level in the range from 2.2 v to 3.6 v until the oscillation stabilization time has elapsed after switching on. 4.0 10.0 2.7 1.8 3.6 vcc (v) f osc (mhz) active (high-speed) mode sleep (high-speed) mode (1) system clock oscillator selected (10-mhz version) (2) system clock oscillator selected (4-mhz version) 2.0 4.2 2.7 1.8 3.6 vcc (v) f osc (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.1 power supply voltage and oscillation frequency range (1)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 387 of 516 rej09b0152-0300 all operating modes 81.25 1.8 3.6 2.7 vcc (v) f w (khz) 9.375 r osc /32 used (reference value) all operating modes refer to note 38.4 r osc used (reference value) 1.8 3.6 2.7 vcc (v) f w (khz) 32.768 note: * when using a resonator, hold the vcc level in the range from 2.2 v to 3.6 v until the oscillation stabilization time has elapsed after switching on. (3) on-chip oscillator selected 0.3 2.6 2.7 1.8 3.6 vcc (v) f osc (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.2 power supply voltage and oscillation frequency range (2)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 388 of 516 rej09b0152-0300 16.384 8.192 4.096 1.8 2.7 3.6 vcc (v) 1.8 2.7 3.6 vcc (v) sub ( khz) 19.2 9.6 4.8 32.768 38.4 4.0 1.8 2.7 3.6 vcc (v) 10.0 62.5 1.8 2.7 3.6 vcc (v) 1250 (1) system clock oscillator selected (10-mhz version) (mhz) (khz) active (high-speed) mode sleep (high-speed) mode 81.25 sub ( khz) 1.172 r osc /32 used (reference value) subactive mode subsleep mode (other than cpu) watch mode (other than cpu) active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode (other than cpu) watch mode (other than cpu) figure 21.3 power supply voltage and operating frequency range (1)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 389 of 516 rej09b0152-0300 16.384 8.192 4.096 1.8 2.7 3.6 vcc (v) sub ( khz) 19.2 9.6 4.8 32.768 38.4 2.0 1.8 2.7 3.6 vcc (v) 4.2 31.25 1.8 2.7 3.6 vcc (v) 525 (2) system clock oscillator selected (4-mhz version) 1.8 2.7 3.6 vcc (v) 81.25 sub ( khz) 1.172 r osc /32 used (reference value) subactive mode subsleep mode (other than cpu) watch mode (other than cpu) active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode (other than cpu) watch mode (other than cpu) (mhz) (khz) active (high-speed) mode sleep (high-speed) mode figure 21.4 power supply voltage and operating frequency range (2)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 390 of 516 rej09b0152-0300 16.384 8.192 4.096 1.8 2.7 3.6 vcc (v) sub ( khz) 19.2 9.6 4.8 32.768 38.4 0.3 1.8 2.7 3.6 vcc (v) 2.6 (3) on-chip oscillator selected 1.8 2.7 3.6 vcc (v) 1.8 2.7 3.6 vcc (v) 81.25 sub ( khz) 1.172 4.6875 325 (khz) r osc /32 used (reference value) r osc used (reference value) r osc used (reference value) subactive mode subsleep mode (other than cpu) watch mode (other than cpu) active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode (other than cpu) watch mode (other than cpu) (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.5 power supply voltage and operating frequency range (3)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 391 of 516 rej09b0152-0300 38.4 1.8 3.6 2.7 avcc (v) sub ( khz) all operating modes all operating modes 32.768 81.25 1.8 3.6 2.7 avcc (v) sub ( khz) 9.375 r osc /32 used (reference value) all operating modes 81.25 1.8 3.6 2.7 avcc (v) sub ( khz) 9.375 r osc /32 used (reference value) all operating modes 38.4 1.8 3.6 2.7 avcc (v) sub ( khz) 32.768 4.0 10.0 2.7 1.8 3.6 avcc (v) (mhz) active (high-speed) mode sleep (high-speed) mode (1) system clock oscillator selected (10-mhz version) (2) system clock oscillator selected (4-mhz version) 2.0 4.2 2.7 1.8 3.6 avcc (v) (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.6 analog power supply voltage and operating frequency range of a/d converter (1)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 392 of 516 rej09b0152-0300 all operating modes 81.25 1.8 3.6 2.7 avcc (v) sub (khz) 9.375 r osc /32 used (reference value) all operating modes 38.4 1.8 3.6 2.7 avcc (v) sub (khz) 32.768 0.3 2.6 2.7 1.8 3.6 avcc (v) ( mhz) active (high-speed) mode sleep (high-speed) mode r osc used (reference value) (3) on-chip oscillator selected figure 21.7 analog power supply voltage and operating frequency range of a/d converter (2)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 393 of 516 rej09b0152-0300 21.2.2 dc characteristics table 21.2 lists the dc characteristics. table 21.2 dc characteristics v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , test, nmi * 3 , aevl, aevh, adtrg , sck3, irqaec 0.9v cc ? v cc + 0.3 v irq0 * 4 , irq1 * 4 0.9v cc ? av cc + 0.3 rxd3, irrxd 0.8v cc ? v cc + 0.3 osc1 0.9v cc ? v cc + 0.3 x1 0.9v cc ? v cc + 0.3 p10 to p12, p30 to p32, p82 to p84, p90 to p93, ssi, sso, ssck, scs , ftci, ftioa, ftiob, ftioc, ftiod, e7_0 to e7_2, scl, sda 0.8v cc ? v cc + 0.3 pb0 to pb5 0.8v cc ? av cc + 0.3
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 394 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes input low voltage v il res , test, nmi * 3 , irq0 , irq1 , irqaec, aevl, aevh, adtrg , sck3 ?0.3 ? 0.1v cc v rxd3, irrxd ?0.3 ? 0.2v cc osc1 ?0.3 ? 0.1v cc x1 ?0.3 ? 0.1v cc p10 to p12, p30 to p32, p82 to p84, p90 to p93, scl, sda, pb0 to pb5, ssi, sso, ssck, scs , ftci, ftioa, ftiob, ftioc, ftiod, e7_0 to e7_2, scl, sda ?0.3 ? 0.2v cc ?i oh = 1.0 ma vcc = 2.7 v to 3.6 v v cc ? 1.0 ? ? p10 to p12, p30 to p32, p90 to p93 ?i oh = 0.1 ma v cc ? 0.3 ? ? ?i oh = 1.0 ma v cc = 2.7 v to 3.6 v v cc ? 1.0 ? ? output high voltage v oh p82 to p84 ?i oh = 0.1 ma v cc ? 0.3 ? ? v output low voltage v ol p10 to p12, p30 to p32, p90 to p93 i ol = 0.4 ma ? ? 0.5 v p82 to p84 i ol = 15 ma, vcc = 2.7 v to 3.6 v ? ? 1.0 i ol = 10 ma, vcc = 2.2 v to 3.6 v ? ? 0.5 i ol = 8 ma ? ? 0.5 scl, sda i ol = 3.0 ma ? ? 0.4
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 395 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes input/output leakage current | i il | test, nmi * 3 , osc1, x1, p10 to p12, p30 to p32, p82 to p84, p90 to p93, e7_0 to e7_2 v in = 0.5 v to v cc ? 0.5 v ? ? 1.0 a pb0 to pb5 v in = 0.5 v to av cc ? 0.5 v ? ? 1.0 pull-up mos current ?i p p10 to p12, p30 to p32, p82 to p84, p90 to p93 v cc = 3 v, v in = 0 v 30 ? 180 a input capacitance c in all input pins except power supply pin f = 1 mhz, v in =0 v, ta = 25c ? ? 15.0 pf active mode supply current i ope1 v cc active (high- speed) mode, v cc = 1.8 v, f osc = 2 mhz ? 1.1 ? ma max. guideline = 1.1 typ. * 1 * 2 active (high- speed) mode, v cc = 3 v, f osc = r osc ? 1.2 ? max. guideline = 1.1 typ. * 1 * 2 reference value active (high- speed) mode, v cc = 3 v, f osc = 4.2 mhz ? 2.6 4.0 * 1 * 2 4-mhz version active (high- speed) mode, v cc = 3 v, f osc = 10 mhz ? 6.0 10.0 * 1 * 2 10-mhz version
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 396 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes active mode supply current i ope2 v cc active (medium- speed) mode, v cc = 1.8 v, f osc = 2 mhz, osc /64 ? 0.4 ? ma max. guideline = 1.1 typ. * 1 * 2 active (medium- speed) mode, v cc = 3 v, f osc = 4.2 mhz, osc /64 ? 0.7 1.1 * 1 * 2 4-mhz version active (medium- speed) mode, v cc = 3 v, f osc = 10 mhz, osc /64 ? 0.8 1.3 * 1 * 2 10-mhz version i sleep v cc v cc = 1.8 v, f osc = 2 mhz ? 0.9 ? ma max. guideline = 1.1 typ. * 1 * 2 sleep mode supply current v cc = 3 v, f osc = 4.2 mhz ? 2.0 3.2 * 1 * 2 4-mhz version v cc = 3 v, f osc = 10 mhz ? 4.2 6.4 * 1 * 2 10-mhz version subactive mode supply current i sub v cc v cc = 2.7 v, 32-khz crystal resonator ( sub = w /8) ? 7.0 ? a * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ( sub = w /2) ? 25 ? * 1 * 2 reference value v cc = 2.7 v, on-chip oscillator/32 ( sub = w = r osc /32) ? 80 ? * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ( sub = w ) ? 45 75 * 1 * 2
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 397 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes subsleep mode supply current i subsp v cc v cc = 2.7 v, 32-khz crystal resonator ( sub = w /2) ? 3.5 ? a * 1 * 2 reference value v cc = 2.7 v, on-chip oscillator/32 ( sub = w = r osc /32) ? 34 ? * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ( sub = w ) ? 5.1 16.0 * 1 * 2 watch mode supply current i watch v cc v cc = 1.8 v, ta = 25 c, 32-khz crystal resonator ? 0.5 ? a * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ? 1.5 5.0 * 1 * 2 standby mode supply current i stby v cc v cc = 3.0 v, ta = 25 c, 32-khz crystal resonator not used ? 0.1 ? a * 1 * 2 reference value 32-khz crystal resonator not used ? 1.0 5.0 * 1 * 2 ram data retaining voltage v ram v cc 1.5 ? ? v i ol output pins except port 8 ? ? 0.5 ma permissible output low current (per pin) port 8 ? ? 15.0 i ol output pins except port 8 ? ? 20.0 ma permissible output low current (total) port 8 ? ? 45.0
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 398 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes ?i oh all output pins v cc = 2.7 v to 3.6 v ? ? 2.0 ma permissible output high current (per pin) other than above ? ? 0.2 permissible output high current (total) ? i oh all output pins ? ? 10.0 ma notes: 1. pin states during current measurement. mode res pin internal state other pins oscillator pins active (high-speed) mode (i ope1 ) v cc only cpu operates v cc active (medium-speed) mode (i ope2 ) sleep mode v cc only on-chip timers operate v cc system clock oscillator: crystal resonator subclock oscillator: pin x1 = gnd subactive mode v cc only cpu operates v cc subsleep mode v cc only on-chip timers operate, cpu stops v cc watch mode v cc only timer base operates, cpu stops v cc system clock oscillator: crystal resonator subclock oscillator: crystal resonator standby mode v cc cpu and timers both stop, substp = 1 v cc system clock oscillator: crystal resonator subclock oscillator: pin x1 = crystal resonator 2. excludes current in pull-up mos transistors and output buffers. 3. used for the determination of user mode or boot mode when the reset is released. 4. when bits irq0s1 and irq0s0 are set to b'01 or b'10, and bits irq1s1 and irq1s0 are set to b'01 or b'10, the maximum value is given v cc + 0.3 (v).
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 399 of 516 rej09b0152-0300 21.2.3 ac characteristics table 21.3 lists the control signal timing, table 21.4 lists the serial interface timing, table 21.5 lists the synchronous serial communication unit timing, and table 21.6 lists the i 2 c bus interface timing. table 21.3 control signal timing v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit reference figure f osc osc1, osc2 v cc = 2.7 v to 3.6 v (10-mhz version) 4.0 ? 10.0 mhz system clock oscillation frequency v cc = 1.8 v to 3.6 v (4-mhz version) 2.0 ? 4.2 t osc osc1, osc2 v cc = 2.7 v to 3.6 v (10-mhz version) 100 ? 250 ns figure 21.15 osc clock ( osc ) cycle time v cc = 1.8 v to 3.6 v (4-mhz version) 238 ? 500 1 ? 64 t osc v cc = 2.7 v to 3.6 v (10-mhz version) ? ? 16 s system clock ( ) cycle time t cyc v cc = 1.8 v to 3.6 v (4-mhz version) ? ? 32 on-chip oscillator oscillation frequency t rosc 0.3 ? 2.6 mhz reference value on-chip oscillator clock cycle time t rosc 0.38 ? 3.3 s reference value subclock oscillator oscillation frequency f w x1, x2 ? 32.768 or 38.4 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 or 26.0 ? s figure 21.15 subclock ( sub ) cycle time t subcyc 1 ? 8 t w * 1 instruction cycle time 2 ? ? t cyc t subcyc
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 400 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure oscillation stabilization time t rc osc1, osc2 ceramic resonator (v cc = 2.2 v to 3.6 v) ? 20 45 s figure 21.28 ceramic resonator (other than above) ? 80 ? crystal resonator (v cc = 2.7 v to 3.6 v) ? 300 800 crystal resonator (v cc = 2.2 v to 3.6 v) ? 600 1000 other than above ? ? 50 ms on-chip oscillator at switching on ? 15 25 s x1, x2 v cc = 2.2 v to 3.6 v ? ? 2 s figures 4.6 and 4.7 other than above ? 4 ? t cph osc1 v cc = 2.7 v to 3.6 v (10-mhz version) 40 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 95 ? ? external clock high width x1 ? 15.26 or 13.02 ? s figure 21.15 t cpl osc1 v cc = 2.7 v to 3.6 v (10-mhz version) 40 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 95 ? ? external clock low width x1 ? 15.26 or 13.02 ? s figure 21.15 t cpr osc1 v cc = 2.7 v to 3.6 v (10-mhz version) ? ? 10 ns v cc = 1.8 v to 3.6 v (4-mhz version) ? ? 24 external clock rising time x1 ? ? 55.0 ns figure 21.15
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 401 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure t cpf osc1 v cc = 2.7 v to 3.6 v (10-mhz version) ? ? 10 ns v cc = 1.8 v to 3.6 v (4-mhz version) ? ? 24 external clock falling time x1 ? ? 55.0 ns figure 21.15 t rel res at switching on or other than below t rc + 20 t cyc ? ? s res pin low width active mode or sleep mode 20 ? ? t cyc figure 21.16 * 2 input pin high width t ih irq0 , irq1 , nmi , irqaec, adtrg , ftci, ftioa, ftiob, ftioc, ftiod 2 ? ? t cyc t subcyc figure 21.17 aevl, aevh v cc = 2.7 v to 3.6 v (10-mhz version) 50 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 110 ? ? input pin low width t il irq0 , irq1 , nmi , irqaec, adtrg , ftci, ftioa, ftiob, ftioc, ftiod 2 ? ? t cyc t subcyc figure 21.17 aevl, aevh v cc = 2.7 v to 3.6 v (10-mhz version) 50 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 110 ? ? notes: 1. selected with the sa1 and sa0 bits in the system control register 2 (syscr2). 2. for details on the power-on reset characteri stics, refer to table 21.10 and figure 21.26.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 402 of 516 rej09b0152-0300 table 21.4 serial interface timing v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol test condition min. typ. max. unit reference figure asynchronous t scyc 4 ? ? figure 21.18 input clock cycle clock synchronous 6 ? ? t cyc or t subcyc input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 21.18 transmit data delay time (clock synchronous) t txd ? ? 1 t cyc or t subcyc figure 21.19 receive data setup time (clock synchronous) t rxs 400.0 ? ? ns figure 21.19 receive data hold time (clock synchronous) t rxh 400.0 ? ? ns figure 21.19
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 403 of 516 rej09b0152-0300 table 21.5 synchronous serial co mmunication unit (ssu) timing v cc = 1.8 v to 3.6 v, v ss = 0.0 v, output load = 100 pf, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit reference figure clock cycle t sucyc ssck 4 ? ? t cyc clock high pulse width t hi ssck 0.4 ? 0.6 t sucyc clock low pulse width t lo ssck 0.4 ? 0.6 t sucyc master t rise ssck ? ? 1 t cyc clock rising time slave ? ? 1.0 s master t fall ssck ? ? 1 t cyc clock falling time slave ? ? 1.0 s data input setup time t su sso ssi 1 ? ? t cyc data input hold time t h sso ssi 1 ? ? t cyc scs setup time slave t lead scs 1t cyc + 100 ? ? ns scs hold time slave t lag scs 1t cyc + 100 ? ? ns data output delay time t od sso ssi ? ? 1 t cyc slave access time t sa ssi ? ? 1t cyc + 100 ns slave out release time t or ssi ? ? 1t cyc + 100 ns figures 21.20 to 21.24
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 404 of 516 rej09b0152-0300 table 21.6 i 2 c bus interface timing v cc = 1.8 v to 3.6 v, v ss = 0.0 v, ta = ?20 to +75c, unless otherwise specified. test values reference item symbol condition min. typ. max. unit figure scl input cycle time t scl 12t cyc + 600 ? ? ns scl input high width t sclh 3t cyc + 300 ? ? ns figure 21.25 scl input low width t scll 5t cyc + 300 ? ? ns falling time for scl and sda inputs t sf ? ? 300 ns pulse width of spike on scl and sda to be suppressed t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns repeated start condition input setup time t stas 3t cyc ? ? ns stop condition input setup time t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc + 20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda cb 0 ? 400 pf falling time of scl and sda output t sf ? ? 300 ns
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 405 of 516 rej09b0152-0300 21.2.4 a/d converter characteristics table 21.7 lists the a/d converter characteristics. table 21.7 a/d convert er characteristics v cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit notes analog power supply voltage av cc av cc 1.8 ? 3.6 v * 1 analog input voltage av in an0 to an5 ?0.3 ? av cc + 0.3 v ai ope av cc av cc = 3.0 v ? ? 1.0 ma analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ? ? 5 a * 3 analog input capacitance c ain an0 to an5 ? ? 15.0 pf permissible signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bits nonlinearity error av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v ? ? 3.5 lsb other than subclock operation av cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v ? ? 5.5 subclock operating ? ? 5.5 subactive or subsleep mode, conversion time = 31/ w other than above ? ? 7.5 * 4 quantization error ? ? 0.5 lsb
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 406 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes absolute accuracy av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v ? ? 4.0 lsb av cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v ? ? 6.0 subclock operating ? ? 6.0 subactive or subsleep mode, conversion time = 31/ w other than above ? ? 8.0 * 4 conversion time av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 12.4 ? 124 s system clock oscillator is selected 31 62 124 on-chip oscillator is selected reference value (f rosc = 1 mhz) ? 807 ? sub = 38.4 khz ? 945 ? sub = 32.8 khz ? 992 ? sub = r osc /32 reference value (f rosc = 1 mhz) other than av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 29.5 ? 124 system clock oscillator is selected 31 62 124 on-chip oscillator is selected reference value (f rosc = 1 mhz) ? 807 ? sub = 38.4 khz ? 945 ? sub = 32.8 khz ? 992 ? sub = r osc /32 reference value (f rosc = 1 mhz) notes: 1. connect av cc to v cc when the a/d converter is not used. 2. ai stop1 is the current flowing through the ladder resistor while the a/d converter is idle. 3. ai stop2 is the current flowing at a reset, in standby mode or watch mode, through the ladder resistor while the a/d converter is idle. 4. conversion time is 29.5 s.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 407 of 516 rej09b0152-0300 21.2.5 comparator characteristics table 21.8 shows the comparator characteristics. table 21.8 comparator characteristics v cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item test condition min. typ. max. unit notes accuracy 1lsb = v cc /30 ? 1/2 ? lsb comparing with internal resistor network conversion time ? ? 15 s external input reference voltage vcref pin 0.9 ? 0.9 v cc v internal resistance compare voltage 0.9 ? 26/30 v cc v comparator input voltage comp0 and comp1 pins ?0.3 ? av cc + 0.3 v ladder resistance ? 3 ? m ? reference value 21.2.6 watchdog timer characteristics table 21.9 shows the watchdog timer characteristics. table 21.9 watchdog timer characteristics v cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit notes on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * indicates that the period from when the counter starts with 0 to when the counter reaches 255 and an internal reset occurs while the on-chip oscillator is selected.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 408 of 516 rej09b0152-0300 21.2.7 power-on reset circuit characteristics table 21.10 lists the power-on reset circuit characteristics. table 21.10 power-on reset circuit characteristics v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, ta = ? ? values item symbol test condition min. typ. max. unit notes reset voltage v_rst 0.7vcc 0.8vcc 0.9vcc v power supply rising time t_vtr the vcc rising time should be shorter than half the res rising time. reset count time t_out 0.8 ? 4.0 s 3.2 ? 26.7 on-chip oscillator is selected (reference value) count start time t_cr adjustable by the value of the external capacitor connected to the res pin. pull-up resistance r p 60 100 ? k ?
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 409 of 516 rej09b0152-0300 21.2.8 flash memory characteristics table 21.11 lists the flas h memory characteristics. table 21.11 flash memory characteristics av cc = 1.8 v to 3.6 v, v ss = 0.0 v, v cc = 1.8 v to 3.6 v (operating voltage range in reading), v cc = 3.0 v to 3.6 v (operating voltage range in programming/erasing), ta = 0 to +75c (operating temperature range in programming/erasing) values item symbol test condition min. typ. max. unit programming time (per 128 bytes) * 1 * 2 * 4 t p ? 7 200 ms erasing time (per block) * 1 * 3 * 6 t e ? 100 1200 ms maximum programming count n wec 1000 * 8 * 11 10000 * 9 ? times 100 * 8 * 12 10000 * 9 ? data retention time t drp 10 * 10 ? ? years programming wait time after setting swe bit * 1 x 1 ? ? s wait time after setting psu bit * 1 y 50 ? ? s wait time after setting p bit * 1 * 4 z1 1 n 6 28 30 32 s z2 7 n 1000 198 200 202 s z3 additional- programming 8 10 12 s wait time after clearing p bit * 1 5 ? ? s wait time after clearing psu bit * 1 5 ? ? s wait time after setting pv bit * 1 4 ? ? s wait time after dummy write * 1 2 ? ? s wait time after clearing pv bit * 1 2 ? ? s wait time after clearing swe bit * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 410 of 516 rej09b0152-0300 values item symbol test condition min. typ. max. unit erase wait time after setting swe bit * 1 x 1 ? ? s wait time after setting esu bit * 1 y 100 ? ? s wait time after setting e bit * 1 * 6 z 10 ? 100 ms wait time after clearing e bit * 1 10 ? ? s wait time after clearing esu bit * 1 10 ? ? s wait time after setting ev bit * 1 20 ? ? s wait time after dummy write * 1 2 ? ? s wait time after clearing ev bit * 1 4 ? ? s wait time after clearing swe bit * 1 100 ? ? s maximum erasing count * 1 * 6 * 7 n ? ? 120 times notes: 1. make the time se ttings in accordance with the programming/erasing algorithms. 2. the programming time for 128 bytes. (indica tes the total time for which the p bit in the flash memory control register 1 (flmcr1) is set. the programming-verifying time is not included.) 3. the time required to erase one block. (indi cates the total time for which the e bit in the flash memory control register 1 (flmcr1) is set. the erasing-verifying time is not included.) 4. programming time maximum value (t p (max.)) = wait time after setting p bit (z) maximum programming count (n) 5. set the maximum programming count (n) acco rding to the actual se t values of z1, z2, and z3, so that it does not exceed the programming time maximum value (t p (max.)). the wait time after setting p bit (z1, z2) s hould be changed as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. erasing time maximum value (t e (max.)) = wait time a fter setting e bit (z) maximum erasing count (n) 7. set the maximum erasing count (n) according to the actual set value of (z), so that it does not exceed the erasing time maximum value (t e (max.)). 8. the minimum number of times in whic h all characteristics are guaranteed following reprogramming. (the guarantee covers the r ange from 1 to the minimum value.) 9. reference value at 25c. (guideli ne showing programming count over which functioning will be retained under normal circumstances.) 10. data retention characteristics within the r ange indicated in the specifications, including the minimum programming count. 11. applies to an operating voltage rang e when reading data of 2.7 to 3.6 v. 12. applies to an operating voltage rang e when reading data of 1.8 to 3.6 v.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 411 of 516 rej09b0152-0300 21.3 absolute maximum ratings for masked rom version table 21.12 lists the absolute maximum ratings. table 21.12 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +4.3 v * analog power supply voltage av cc ?0.3 to +4.3 v input voltage other than port b v in ?0.3 to v cc +0.3 v port b av in ?0.3 to av cc +0.3 v operating temperature t opr ?20 to +75 (general specifications) c ?40 to +85 (wide temperature range specifications) storage temperature t stg ?55 to +125 c note: * permanent damage may occur to the chip if absolute maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 412 of 516 rej09b0152-0300 21.4 electrical characteristics for masked rom version 21.4.1 power supply volt age and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 38.4 1.8 3.6 2.7 vcc (v) f w (khz) all operating modes refer to note all operating modes 32.768 81.25 1.8 3.6 2.7 vcc (v) f w (khz) 9.375 r osc /32 used (reference value) all operating modes 81.25 1.8 3.6 2.7 vcc (v) f w (khz) 9.375 r osc /32 used (reference value) all operating modes refer to note 38.4 1.8 3.6 2.7 vcc (v) f w (khz) 32.768 note: * when using a resonator, hold the vcc level in the range from 2.2 v to 3.6 v until the oscillation stabilization time has elapsed after switching on. 4.0 10.0 2.7 1.8 3.6 vcc (v) f osc (mhz) active (high-speed) mode sleep (high-speed) mode (1) system clock oscillator selected (10-mhz version) (2) system clock oscillator selected (4-mhz version) 2.0 4.2 2.7 1.8 3.6 vcc (v) f osc (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.8 power supply voltage and oscillation frequency range (1)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 413 of 516 rej09b0152-0300 all operating modes 81.25 1.8 3.6 2.7 vcc (v) f w (khz) 9.375 r osc /32 used (reference value) all operating modes refer to note 38.4 r osc used (reference value) 1.8 3.6 2.7 vcc (v) f w (khz) 32.768 note: * when using a resonator, hold the vcc level in the range from 2.2 v to 3.6 v until the oscillation stabilization time has elapsed after switching on. (3) on-chip oscillator selected 0.3 2.6 2.7 1.8 3.6 vcc (v) f osc (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.9 power supply voltage and oscillation frequency range (2)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 414 of 516 rej09b0152-0300 16.384 8.192 4.096 1.8 2.7 3.6 vcc (v) 1.8 2.7 3.6 vcc (v) sub ( khz) 19.2 9.6 4.8 32.768 38.4 4.0 1.8 2.7 3.6 vcc (v) 10.0 62.5 1.8 2.7 3.6 vcc (v) 1250 (1) system clock oscillator selected (10-mhz version) (mhz) (khz) active (high-speed) mode sleep (high-speed) mode 81.25 sub ( khz) 1.172 r osc /32 used (reference value) subactive mode subsleep mode (other than cpu) watch mode (other than cpu) active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode (other than cpu) watch mode (other than cpu) figure 21.10 power supply voltage and operating frequency range (1)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 415 of 516 rej09b0152-0300 16.384 8.192 4.096 1.8 2.7 3.6 vcc (v) sub ( khz) 19.2 9.6 4.8 32.768 38.4 2.0 1.8 2.7 3.6 vcc (v) 4.2 31.25 1.8 2.7 3.6 vcc (v) 525 (2) system clock oscillator selected (4-mhz version) 1.8 2.7 3.6 vcc (v) 81.25 sub ( khz) 1.172 r osc /32 used (reference value) subactive mode subsleep mode (other than cpu) watch mode (other than cpu) active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode (other than cpu) watch mode (other than cpu) (mhz) (khz) active (high-speed) mode sleep (high-speed) mode figure 21.11 power supply voltage and operating frequency range (2)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 416 of 516 rej09b0152-0300 16.384 8.192 4.096 1.8 2.7 3.6 vcc (v) sub ( khz) 19.2 9.6 4.8 32.768 38.4 0.3 1.8 2.7 3.6 vcc (v) 2.6 (3) on-chip oscillator selected 1.8 2.7 3.6 vcc (v) 1.8 2.7 3.6 vcc (v) 81.25 sub ( khz) 1.172 4.6875 325 (khz) r osc /32 used (reference value) r osc used (reference value) r osc used (reference value) subactive mode subsleep mode (other than cpu) watch mode (other than cpu) active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode (other than cpu) watch mode (other than cpu) (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.12 power supply voltage and operating frequency range (3)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 417 of 516 rej09b0152-0300 38.4 1.8 3.6 2.7 avcc (v) sub ( khz) all operating modes all operating modes 32.768 81.25 1.8 3.6 2.7 avcc (v) sub ( khz) 9.375 r osc /32 used (reference value) all operating modes 81.25 1.8 3.6 2.7 avcc (v) sub ( khz) 9.375 r osc /32 used (reference value) all operating modes 38.4 1.8 3.6 2.7 avcc (v) sub ( khz) 32.768 4.0 10.0 2.7 1.8 3.6 avcc (v) (mhz) active (high-speed) mode sleep (high-speed) mode (1) system clock oscillator selected (10-mhz version) (2) system clock oscillator selected (4-mhz version) 2.0 4.2 2.7 1.8 3.6 avcc (v) (mhz) active (high-speed) mode sleep (high-speed) mode figure 21.13 analog power supply voltage and operating frequency range of a/d converter (1)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 418 of 516 rej09b0152-0300 all operating modes 81.25 1.8 3.6 2.7 avcc (v) sub (khz) 9.375 r osc /32 used (reference value) all operating modes 38.4 1.8 3.6 2.7 avcc (v) sub (khz) 32.768 0.3 2.6 2.7 1.8 3.6 avcc (v) ( mhz) active (high-speed) mode sleep (high-speed) mode r osc used (reference value) (3) on-chip oscillator selected figure 21.14 analog power supply voltage and operating frequency range of a/d converter (2)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 419 of 516 rej09b0152-0300 21.4.2 dc characteristics table 21.13 lists the dc characteristics. table 21.13 dc characteristics v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , test, nmi , aevl, aevh, adtrg , sck3, irqaec 0.9v cc ? v cc + 0.3 v irq0 * 3 , irq1 * 3 0.9v cc ? av cc + 0.3 rxd3, irrxd 0.8v cc ? v cc + 0.3 osc1 0.9v cc ? v cc + 0.3 x1 0.9v cc ? v cc + 0.3 p10 to p12, p30 to p32, p82 to p84, p90 to p93, ssi, sso, ssck, scs , ftci, ftioa, ftiob, ftioc, ftiod, e7_0 to e7_2, scl, sda 0.8v cc ? v cc + 0.3 pb0 to pb5 0.8v cc ? av cc + 0.3
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 420 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes input low voltage v il test, nmi , irq0 , irq1 , irqaec, aevl, aevh, adtrg , sck3 ?0.3 ? 0.1v cc v rxd3, irrxd ?0.3 ? 0.2v cc osc1 ?0.3 ? 0.1v cc x1 ?0.3 ? 0.1v cc p10 to p12, p30 to p32, p82 to p84, p90 to p93, scl, sda, pb0 to pb5, ssi, sso, ssck, scs , ftci, ftioa, ftiob, ftioc, ftiod, e7_0 to e7_2 ?0.3 ? 0.2v cc ?i oh = 1.0 ma vcc = 2.7 v to 3.6 v v cc ? 1.0 ? ? p10 to p12, p30 to p32, p90 to p93 ?i oh = 0.1 ma v cc ? 0.3 ? ? ?i oh = 1.0 ma v cc = 2.7 v to 3.6 v v cc ? 1.0 ? ? output high voltage v oh p82 to p84 ?i oh = 0.1 ma v cc ? 0.3 ? ? v output low voltage v ol p10 to p12, p30 to p32, p90 to p93 i ol = 0.4 ma ? ? 0.5 v p82 to p84 i ol = 15 ma, vcc = 2.7 v to 3.6 v ? ? 1.0 i ol = 10 ma, vcc = 2.2 v to 3.6 v ? ? 0.5 i ol = 8 ma ? ? 0.5 scl, sda i ol = 3.0 ma ? ? 0.4
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 421 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes input/output leakage current | i il | test, nmi , osc1, x1, p10 to p12, p30 to p32, p82 to p84, p90 to p93, e7_0 to e7_2 v in = 0.5 v to v cc ? 0.5 v ? ? 1.0 a pb0 to pb5 v in = 0.5 v to av cc ? 0.5 v ? ? 1.0 pull-up mos current ?i p p10 to p12, p30 to p32, p82 to p84, p90 to p93 v cc = 3 v, v in = 0 v 30 ? 180 a input capacitance c in all input pins except power supply pin f = 1 mhz, v in =0 v, ta = 25c ? ? 15.0 pf active mode supply current i ope1 v cc active (high- speed) mode, v cc = 1.8 v, f osc = 2 mhz ? 0.5 ? ma max. guideline = 1.1 typ. * 1 * 2 active (high- speed) mode, v cc = 3 v, f osc = r osc ? 0.6 ? max. guideline = 1.1 typ. * 1 * 2 reference value active (high- speed) mode, v cc = 3 v, f osc = 4.2 mhz ? 2.0 3.0 * 1 * 2 4-mhz version active (high- speed) mode, v cc = 3 v, f osc = 10 mhz ? 4.5 6.8 * 1 * 2 10-mhz version
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 422 of 516 rej09b0152-0300 applicable values item symbol pins test condition min. typ. max. unit notes active mode supply current i ope2 v cc active (medium-speed) mode, v cc = 1.8 v, f osc = 2 mhz, osc /64 ? 0.1 ? ma max. guideline = 1.1 typ. * 1 * 2 active (medium-speed) mode, v cc = 3 v, f osc = 4.2 mhz, osc /64 ? 0.3 0.5 * 1 * 2 4-mhz version active (medium-speed) mode, v cc = 3 v, f osc = 10 mhz, osc /64 ? 0.5 0.7 * 1 * 2 10-mhz version i sleep v cc v cc = 1.8 v, f osc = 2 mhz ? 0.3 ? ma max. guideline = 1.1 typ. * 1 * 2 sleep mode supply current v cc = 3 v, f osc = 4.2 mhz ? 1.0 1.5 * 1 * 2 4-mhz version v cc = 3 v, f osc = 10 mhz ? 1.8 2.7 * 1 * 2 10-mhz version i sub v cc v cc = 1.8 v, 32-khz crystal resonator ( sub = w /2) ? 4.0 ? a * 1 * 2 reference value subactive mode supply current v cc = 2.7 v, 32-khz crystal resonator ( sub = w /8) ? 3.6 ? * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ( sub = w /2) ? 7.4 ? * 1 * 2 reference value v cc = 2.7 v, on-chip oscillator/32 ( sub = w = r osc /32) ? 40 ? * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ( sub = w ) ? 13 25 * 1 * 2
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 423 of 516 rej09b0152-0300 applicable values item symbol pins test condition min. typ. max. unit notes subsleep mode supply current i subsp v cc v cc = 2.7 v, 32-khz crystal resonator ( sub = w /2) ? 3.1 ? a * 1 * 2 reference value v cc = 2.7 v, on-chip oscillator/32 ( sub = w = r osc /32) ? 30 ? * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ( sub = w ) ? 5.0 10.0 * 1 * 2 watch mode supply current i watch v cc v cc = 1.8 v, ta = 25 c, 32-khz crystal resonator ? 0.4 ? a * 1 * 2 reference value v cc = 2.7 v, 32-khz crystal resonator ? 1.5 5.0 * 1 * 2 standby mode supply current i stby v cc v cc = 3.0 v, ta = 25 c, 32-khz crystal resonator not used ? 0.1 ? a * 1 * 2 reference value 32-khz crystal resonator not used ? 1.0 5.0 * 1 * 2 ram data retaining voltage v ram v cc 1.5 ? ? v i ol output pins except port 8 ? ? 0.5 ma permissible output low current (per pin) port 8 ? ? 15.0 i ol output pins except port 8 ? ? 20.0 ma permissible output low current (total) port 8 ? ? 45.0
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 424 of 516 rej09b0152-0300 applicable values item symbol pins test condition min. typ. max. unit notes ?i oh all output pins v cc = 2.7 v to 3.6 v ? ? 2.0 ma permissible output high current (per pin) other than above ? ? 0.2 permissible output high current (total) ? i oh all output pins ? ? 10.0 ma notes: 1. pin states during current measurement. mode res pin internal state other pins oscillator pins active (high-speed) mode (i ope1 ) v cc only cpu operates v cc active (medium-speed) mode (i ope2 ) sleep mode v cc only on-chip timers operate v cc system clock oscillator: crystal resonator subclock oscillator: pin x1 = gnd subactive mode v cc only cpu operates v cc subsleep mode v cc only on-chip timers operate, cpu stops v cc watch mode v cc only timer base operates, cpu stops v cc system clock oscillator: crystal resonator subclock oscillator: crystal resonator standby mode v cc cpu and timers both stop, substp = 1 v cc system clock oscillator: crystal resonator subclock oscillator: pin x1 = crystal resonator 2. excludes current in pull-up mos transistors and output buffers. 3. when bits irq0s1 and irq0s0 are set to b'01 or b'10, and bits irq1s1 and irq1s0 are set to b'01 or b'10, the maximum value is given v cc + 0.3 (v).
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 425 of 516 rej09b0152-0300 21.4.3 ac characteristics table 21.14 lists the control signa l timing, table 21.15 lists the se rial interface timi ng, table 21.16 lists the synchronous serial communication unit timing, and table 21.17 lists the i 2 c bus interface timing. table 21.14 control signal timing v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit reference figure f osc osc1, osc2 v cc = 2.7 v to 3.6 v (10-mhz version) 4.0 ? 10.0 mhz system clock oscillation frequency v cc = 1.8 v to 3.6 v (4-mhz version) 2.0 ? 4.2 t osc osc1, osc2 v cc = 2.7 v to 3.6 v (10-mhz version) 100 ? 250 ns figure 21.15 osc clock ( osc ) cycle time v cc = 1.8 v to 3.6 v (4-mhz version) 238 ? 500 t cyc 1 ? 64 t osc v cc = 2.7 v to 3.6 v (10-mhz version) ? ? 16 s system clock ( ) cycle time v cc = 1.8 v to 3.6 v (4-mhz version) ? ? 32 on-chip oscillator oscillation frequency t rosc 0.3 ? 2.6 mhz reference value on-chip oscillator clock cycle time t rosc 0.38 ? 3.3 s reference value subclock oscillator oscillation frequency f w x1, x2 ? 32.768 or 38.4 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 or 26.0 ? s figure 21.15
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 426 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure subclock ( sub ) cycle time t subcyc 1 ? 8 t w * 1 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time t rc osc1, osc2 ceramic resonator (v cc = 2.2 v to 3.6 v) ? 20 45 s figure 21.28 ceramic resonator (other than above) ? 80 ? crystal resonator (v cc = 2.7 v to 3.6 v) ? 300 800 crystal resonator (v cc = 2.2 v to 3.6 v) ? 600 1000 other than above ? ? 50 ms on-chip oscillator at switching on ? 15 25 s x1, x2 v cc = 2.2 v to 3.6 v ? ? 2 s figures 4.6 and 4.7 other than above ? 4 ? t cph osc1 v cc = 2.7 v to 3.6 v (10-mhz version) 40 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 95 ? ? external clock high width x1 ? 15.26 or 13.02 ? s figure 21.15 t cpl osc1 v cc = 2.7 v to 3.6 v (10-mhz version) 40 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 95 ? ? external clock low width x1 ? 15.26 or 13.02 ? s figure 21.15
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 427 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit reference figure t cpr osc1 v cc = 2.7 v to 3.6 v (10-mhz version) ? ? 10 ns v cc = 1.8 v to 3.6 v (4-mhz version) ? ? 24 external clock rising time x1 ? ? 55.0 ns figure 21.15 t cpf osc1 v cc = 2.7 v to 3.6 v (10-mhz version) ? ? 10 ns v cc = 1.8 v to 3.6 v (4-mhz version) ? ? 24 external clock falling time x1 ? ? 55.0 ns figure 21.15 t rel res at switching on or other than below t rc + 20 t cyc ? ? s res pin low width active mode or sleep mode 20 t cyc figure 21.16 * 2 input pin high width t ih irq0 , irq1 , nmi , irqaec, adtrg , ftci, ftioa, ftiob, ftioc, ftiod 2 ? ? t cyc t subcyc figure 21.17 aevl, aevh v cc = 2.7 v to 3.6 v (10-mhz version) 50 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 110 ? ? input pin low width t il irq0 , irq1 , nmi , irqaec, adtrg , ftci, ftioa, ftiob, ftioc, ftiod 2 ? ? t cyc t subcyc figure 21.17 aevl, aevh v cc = 2.7 v to 3.6 v (10-mhz version) 50 ? ? ns v cc = 1.8 v to 3.6 v (4-mhz version) 110 ? ? notes: 1. selected with the sa1 and sa0 bits in the system control register 2 (syscr2). 2. for details on the power-on reset characteri stics, refer to table 21.21 and figure 21.26.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 428 of 516 rej09b0152-0300 table 21.15 serial interface timing v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol test condition min. typ. max. unit reference figure asynchronous t scyc 4 ? ? figure 21.18 input clock cycle clock synchronous 6 ? ? t cyc or t subcyc input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 21.18 transmit data delay time (clock synchronous) t txd ? ? 1 t cyc or t subcyc figure 21.19 receive data setup time (clock synchronous) t rxs 400.0 ? ? ns figure 21.19 receive data hold time (clock synchronous) t rxh 400.0 ? ? ns figure 21.19
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 429 of 516 rej09b0152-0300 table 21.16 synchronous serial co mmunication unit (ssu) timing v cc = 1.8 v to 3.6 v, v ss = 0.0 v, output load = 100 pf, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit reference figure clock cycle t sucyc ssck 4 ? ? t cyc clock high pulse width t hi ssck 0.4 ? 0.6 t sucyc clock low pulse width t lo ssck 0.4 ? 0.6 t sucyc master t rise ssck ? ? 1 t cyc clock rising time slave ? ? 1.0 s master t fall ssck ? ? 1 t cyc clock falling time slave ? ? 1.0 s data input setup time t su sso ssi 1 ? ? t cyc data input hold time t h sso ssi 1 ? ? t cyc scs setup time slave t lead scs 1t cyc + 100 ? ? ns scs hold time slave t lag scs 1t cyc + 100 ? ? ns data output delay time t od sso ssi ? ? 1 t cyc slave access time t sa ssi ? ? 1t cyc + 100 ns slave out release time t or ssi ? ? 1t cyc + 100 ns figures 21.20 to 21.24
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 430 of 516 rej09b0152-0300 table 21.17 i 2 c bus interface timing v cc = 1.8 v to 3.6 v, v ss = 0.0 v, ta = ?20 to +75c, unless otherwise specified. test values reference item symbol condition min. typ. max. unit figure scl input cycle time t scl 12t cyc + 600 ? ? ns scl input high width t sclh 3t cyc + 300 ? ? ns figure 21.25 scl input low width t scll 5t cyc + 300 ? ? ns falling time for scl and sda inputs t sf ? ? 300 ns pulse width of spike on scl and sda to be suppressed t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns repeated start condition input setup time t stas 3t cyc ? ? ns stop condition input setup time t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc + 20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda cb 0 ? 400 pf falling time of scl and sda output t sf ? ? 300 ns
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 431 of 516 rej09b0152-0300 21.4.4 a/d converter characteristics table 21.18 lists the a/d converter characteristics. table 21.18 a/d converter characteristics v cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit notes analog power supply voltage av cc av cc 1.8 ? 3.6 v * 1 analog input voltage av in an0 to an5 ?0.3 ? av cc + 0.3 v ai ope av cc av cc = 3.0 v ? ? 1.0 ma analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ? ? 5 a * 3 analog input capacitance c ain an0 to an5 ? ? 15.0 pf permissible signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bits nonlinearity error av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v ? ? 3.5 lsb av cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v ? ? 5.5 other than subclock operation subclock operating ? ? 5.5 subactive or subsleep mode, conversion time = 31/ w other than above ? ? 7.5 * 4 quantization error ? ? 0.5 lsb
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 432 of 516 rej09b0152-0300 values item symbol applicable pins test condition min. typ. max. unit notes absolute accuracy av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v ? ? 4.0 lsb av cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v ? ? 6.0 subclock operating ? ? 6.0 subactive or subsleep mode, conversion time = 31/ w other than above ? ? 8.0 * 4 conversion time av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 12.4 ? 124 s system clock oscillator is selected 31 62 124 on-chip oscillator is selected reference value (f rosc = 1 mhz) ? 807 ? sub = 38.4 khz ? 945 ? sub = 32.8 khz ? 992 ? sub = r osc /32 reference value (f rosc = 1 mhz) other than av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 29.5 ? 124 system clock oscillator is selected 31 62 124 on-chip oscillator is selected reference value (f rosc = 1 mhz) ? 807 ? sub = 38.4 khz ? 945 ? sub = 32.8 khz ? 992 ? sub = r osc /32 reference value (f rosc = 1 mhz) notes: 1. connect av cc to v cc when the a/d converter is not used. 2. ai stop1 is the current flowing through the ladder resistor while the a/d converter is idle. 3. ai stop2 is the current flowing at a reset, in standby mode or watch mode, through the ladder resistor while the a/d converter is idle. 4. conversion time is 29.5 s.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 433 of 516 rej09b0152-0300 21.4.5 comparator characteristics table 21.19 shows the comp arator characteristics. table 21.19 comparator characteristics v cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item test condition min. typ. max. unit notes accuracy 1lsb = v cc /30 ? 1/2 ? lsb comparing with internal resistor network conversion time ? ? 15 s external input reference voltage vcref pin 0.9 ? 0.9 v cc v internal resistance compare voltage 0.9 ? 26/30 v cc v comparator input voltage comp0 and comp1 pins ?0.3 ? av cc + 0.3 v ladder resistance ? 3 ? m ? reference value 21.4.6 watchdog timer characteristics table 21.20 shows the watchdog timer characteristics. table 21.20 watchdog timer characteristics v cc = 1.8 v to 3.6 v, v ss = 0.0 v, unless otherwise specified. values item symbol applicable pins test condition min. typ. max. unit notes on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * indicates that the period from when the counter starts with 0 to when the counter reaches 255 and an internal reset occurs while the on-chip oscillator is selected.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 434 of 516 rej09b0152-0300 21.4.7 power-on reset circuit characteristics table 21.21 lists the power-on reset circuit characteristics. table 21.21 power-on reset circuit characteristics v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = 0.0 v, ta = ? ? values item symbol test condition min. typ. max. unit notes reset voltage v_rst 0.7vcc 0.8vcc 0.9vcc v power supply rising time t_vtr the vcc rising time should be shorter than half the res rising time. reset count time t_out 0.8 ? 4.0 s 3.2 ? 26.7 on-chip oscillator is selected (reference value ) count start time t_cr adjustable by the value of the external capacitor connected to the res pin. pull-up resistance r p 60 100 ? k ?
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 435 of 516 rej09b0152-0300 21.5 operation timing figures 21.15 to 21.26 show operation timings. t osc , t w v ih v il t cph t cpl t cpr osc1, x1 t cpf figure 21.15 clock input timing res v il t rel figure 21.16 res low width timing v ih v il t il nmi , irq0 , irq1 , adtrg , irqaec, aevl, aevh, ftci, ftioa to ftiod t ih figure 21.17 input timing t scyc t sckw sck3 figure 21.18 sck3 input clock timing
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 436 of 516 rej09b0152-0300 t scyc t txd t rxs t rxh v oh * v ih or v oh * v il or v ol * v ol * sck3 txd3 (transmit data) rxd3 (receive data) note: * output timing referenced levels output high output low load conditions are shown in figure 21.27. v oh = 1/2vcc + 0.2 v v ol = 0.8 v figure 21.19 sci3 input/output timing in clock synchronous mode ssck sso (output) ssi (input) t su t h t od t sucyc t hi t lo v ih or v oh v il or v ol figure 21.20 ssu input/output ti ming in clock synchronous mode
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 437 of 516 rej09b0152-0300 ssck (output) cpos = 0 scs (output) ssck (output) cpos = 1 sso (output) ssi (input) t su t h t od t fall t rise t sucyc t oh t lo t hi t hi t lo v ih or v oh v il or v ol figure 21.21 ssu input/output timing (four-line bus communication mode, master, cphs = 1) ssck (output) cpos = 0 scs (output) ssck (output) cpos = 1 sso (output) ssi (input) t su t h t od t oh t fall t rise t sucyc t lo t hi t hi t lo v ih or v oh v il or v ol figure 21.22 ssu input/output timing (four-line bus communication mode, master, cphs = 0)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 438 of 516 rej09b0152-0300 ssck (input) cpos = 0 scs (input) ssck (input) cpos = 1 sso (input) ssi (output) t lead t fall t rise t sucyc t lag t oh t od t su t sa t lo t hi t hi t lo t or t h v ih or v oh v il or v ol figure 21.23 ssu input/output timing (four-line bus communication mode, slave, cphs = 1) ssck (input) cpos = 0 scs (input) ssck (input) cpos = 1 sso (input) ssi (output) t lead t fall t rise t sucyc t lag t oh t od t su t sa t lo t hi t hi t lo t od t h v ih or v oh v il or v ol figure 21.24 ssu input/output timing (four-line bus communication mode, slave, cphs = 0)
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 439 of 516 rej09b0152-0300 scl v ih v il t stah t buf p * s * t sf t sr t scl t sdah t sclh t scll sda sr * t stas t sp t stos t sdas p * note: * s, p, and sr represent the following: s: start condition p: stop condition sr: repeated start condition figure 21.25 i 2 c bus interface input/output timing v cc t_vtr v_rst t_cr t_out internal reset res figure 21.26 power-on re set circuit reset timing
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 440 of 516 rej09b0152-0300 21.6 output load circuit v cc 2.4 k 12 k 30 pf lsi output pin figure 21.27 output load condition 21.7 recommended resonators (1) recommended crystal resonators frequency (mhz) part no. manufacturer part no. murata manufacturing co., ltd. murata manufacturing co., ltd. murata manufacturing co., ltd. manufacturer 4.194304 nihon dempa kogyo co., ltd. nr-18 10 nihon dempa kogyo co., ltd. nr-18 (2) recommended ceramic resonators frequency (mhz) 2 cstcc2m00g53-b0 cstcc2m00g56-b0 4.19 cstls4m19g53-b0 cstls4m19g56-b0 10 cstls10m0g53-b0 cstls10m0g56-b0 figure 21.28 recommended resonators
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 441 of 516 rej09b0152-0300 21.8 usage note the f-ztat and masked rom versions satisfy the electrical characteris tics shown in this manual, however actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip rom, layout patterns, and so on. when system evaluation testing is carried out using the f-ztat version, the same evaluation testing should also be conducted for the masked rom version when changing over to that version.
section 21 electric al characteristics rev. 3.00 may 15, 2007 page 442 of 516 rej09b0152-0300
appendix rev. 3.00 may 15, 2007 page 443 of 516 rej09b0152-0300 appendix a. instruction set a.1 instruction list condition code symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (addr ess register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the op erand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides logical exclusive or of the operands on both sides ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7).
appendix rev. 3.00 may 15, 2007 page 444 of 516 rej09b0152-0300 condition code notation (cont) symbol description ? changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction ? varies depending on conditions, described in notes
appendix rev. 3.00 may 15, 2007 page 445 of 516 rej09b0152-0300 table a.1 instruction set 1. data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) operation #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32?1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) b b b b b b b b b b b b b b b b w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 4 6 2 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov
appendix rev. 3.00 may 15, 2007 page 446 of 516 rej09b0152-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 operation erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 erd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp sp?2 sp rn16 @sp sp?4 sp ern32 @sp cannot be used in this lsi cannot be used in this lsi w w w l l l l l l l l l l l l l l w l w l b b 6 2 4 4 6 10 6 10 2 4 4 4 6 6 8 6 8 4 4 2 4 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi cannot be used in this lsi mov pop push movfpe movtpe
appendix rev. 3.00 may 15, 2007 page 447 of 516 rej09b0152-0300 2. arithmetic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd operation rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8?rs8 rd8 rd16?#xx:16 rd16 rd16?rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8?#xx:8?c rd8 rd8?rs8?c rd8 erd32?1 erd32 erd32?2 erd32 erd32?4 erd32 rd8?1 rd8 rd16?1 rd16 rd16?2 rd16 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? ? ? ? * (1) (1) (2) (2) ? ? ? ? ? ? 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) (3) ? ? ? (3) (3) ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? add addx adds inc daa sub subx subs dec
appendix rev. 3.00 may 15, 2007 page 448 of 516 rej09b0152-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd operation erd32?1 erd32 erd32?2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8?#xx:8 rd8?rs8 rd16?#xx:16 rd16?rs16 erd32?#xx:32 erd32?ers32 l l b b w b w b w b w b b w w l l 2 4 6 2 2 2 2 2 4 4 2 2 4 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 14 22 16 24 14 22 16 24 2 2 4 2 4 2 normal advanced ? ? ? ? ? * ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? (7) (7) (7) (7) ? ? (6) (6) (8) (8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dec das mulxu mulxs divxu divxs cmp
appendix rev. 3.00 may 15, 2007 page 449 of 516 rej09b0152-0300 mnemonic operation operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd 0?rd8 rd8 0?rd16 rd16 0?erd32 erd32 0 ( of rd16) 0 ( of erd32) ( of rd16) ( of rd16) ( of erd32) ( of erd32) b w l w l w l 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? neg extu exts
appendix rev. 3.00 may 15, 2007 page 450 of 516 rej09b0152-0300 3. logic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd operation rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 ? #xx:8 rd8 rd8 ? rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ? rd8 rd8 ? rd16 rd16 ? rd32 rd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and or xor not
appendix rev. 3.00 may 15, 2007 page 451 of 516 rej09b0152-0300 4. shift instructions mnemonic operand size no. of states * 1 condition code ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 operation msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? shal shar shll shlr rotxl rotxr rotl rotr
appendix rev. 3.00 may 15, 2007 page 452 of 516 rej09b0152-0300 5. bit-manipulation instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd operation (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @erd) ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @erd) ? (rn8 of @erd) (rn8 of @aa:8) ? (rn8 of @aa:8) ? (#xx:3 of rd8) z ? (#xx:3 of @erd) z ? (#xx:3 of @aa:8) z ? (rn8 of @rd8) z ? (rn8 of @erd) z ? (rn8 of @aa:8) z (#xx:3 of rd8) c b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bset bclr bnot btst bld
appendix rev. 3.00 may 15, 2007 page 453 of 516 rej09b0152-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 operation (#xx:3 of @erd) c (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @erd24) ? c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bld bild bist bst band biand bor bior bxor bixor
appendix rev. 3.00 may 15, 2007 page 454 of 516 rej09b0152-0300 6. branching instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size no. of states * 1 condition code ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 normal advanced addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 operation always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 if condition is true then pc pc+d else next; branch condition bcc
appendix rev. 3.00 may 15, 2007 page 455 of 516 rej09b0152-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts operation pc ern pc aa:24 pc @aa:8 pc @?sp pc pc+d:8 pc @?sp pc pc+d:16 pc @?sp pc ern pc @?sp pc aa:24 pc @?sp pc @aa:8 pc @sp+ ? ? ? ? ? ? ? ? ? 2 2 4 4 2 4 2 2 2 ? ? ? ? ? ? ? ? ? 4 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 6 8 6 8 8 8 10 8 10 8 10 12 10 jmp bsr jsr rts
appendix rev. 3.00 may 15, 2007 page 456 of 516 rej09b0152-0300 7. system control instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop operation ccr @sp+ pc @sp+ transition to power- down state #xx:8 ccr rs8 ccr @ers ccr @(d:16, ers) ccr @(d:24, ers) ccr @ers ccr ers32+2 ers32 @aa:16 ccr @aa:24 ccr ccr rd8 ccr @erd ccr @(d:16, erd) ccr @(d:24, erd) erd32?2 erd32 ccr @erd ccr @aa:16 ccr @aa:24 ccr #xx:8 ccr ccr #xx:8 ccr ccr #xx:8 ccr pc pc+2 ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 2 2 2 4 4 6 10 6 10 4 4 6 8 6 8 2 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rte sleep trapa pc @-sp ccr @-sp pc ? ????? ? ? ???? ? ? ???? ? ? ???? ? ? ???? ? ? ???? ? ? ???? ? ? ???? ? ? ???? ? ? ???? 216 14 1 ldc stc andc orc xorc nop trapa #x:2
appendix rev. 3.00 may 15, 2007 page 457 of 516 rej09b0152-0300 8. block data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? eepmov. b eepmov. w operation if r4l 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l?1 r4l until r4l=0 else next if r4 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4?1 r4 until r4=0 else next ? ? 4 4 ? ? 8+4n * 2 normal advanced ? ? ? ? ? ? ? ? ? ? 8+4n * 2 eepmov notes: 1. the number of states in cases wher e the instruction code and its operands are located in on-chip memory is shown here. for ot her cases, see appendix a.3, number of execution states. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for executi on of an instruction t hat transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0.
appendix rev. 3.00 may 15, 2007 page 458 of 516 rej09b0152-0300 a.2 operation code map table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc beq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) bvs blt bge bsr table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b
appendix rev. 3.00 may 15, 2007 page 459 of 516 rej09b0152-0300 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a-2 (3) table a-2 (3) table a-2 (3) add mov sub cmp bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl subs adds shll shlr rotxl rotxr not shal shar rotl rotr neg
appendix rev. 3.00 may 15, 2007 page 460 of 516 rej09b0152-0300 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc
appendix rev. 3.00 may 15, 2007 page 461 of 516 rej09b0152-0300 a.3 number of execution states the status of execution for each instruction of the h8/300h cpu and the method of calculating the number of states required for instructio n execution are shown belo w. table a.4 shows the number of cycles of each type occurring in each instruction, such as in struction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chi p rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8
appendix rev. 3.00 may 15, 2007 page 462 of 516 rej09b0152-0300 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip me mory on-chip peripheral module instruction fetch s i 2 ? branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m ? internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 20.1, register addresses (address order).
appendix rev. 3.00 may 15, 2007 page 463 of 516 rej09b0152-0300 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2
appendix rev. 3.00 may 15, 2007 page 464 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc blt d:8 bgt d:8 ble d:8 bra d:16(bt d:16) brn d:16(bf d:16) bhi d:16 bls d:16 bcc d:16(bhs d:16) bcs d:16(blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1
appendix rev. 3.00 may 15, 2007 page 465 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bior bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 bsr d:16 2 2 1 1 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2
appendix rev. 3.00 may 15, 2007 page 466 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 divxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n+2 * 1 2n+2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1
appendix rev. 3.00 may 15, 2007 page 467 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern jmp @aa:24 jmp @@aa:8 2 2 2 1 2 2 jsr jsr @ern jsr @aa:24 jsr @@aa:8 2 2 2 1 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc@ers, ccr ldc@(d:16, ers), ccr ldc@(d:24,ers), ccr ldc@ers+, ccr ldc@aa:16, ccr ldc@aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @-erd mov.b rs, @aa:8 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2
appendix rev. 3.00 may 15, 2007 page 468 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16,ers), rd mov.w @(d:24,ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16,erd) mov.w rs, @(d:24,erd) mov.w rs, @-erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16,ers), erd mov.l @(d:24,ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers,@erd mov.l ers, @(d:16,erd) mov.l ers, @(d:24,erd) mov.l ers, @-erd mov.l ers, @aa:16 mov.l ers, @aa:24 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movfpe movfpe @aa:16, rd * 2 2 1 movtpe movtpe rs,@aa:16 * 2 2 1
appendix rev. 3.00 may 15, 2007 page 469 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1
appendix rev. 3.00 may 15, 2007 page 470 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16,erd) stc ccr, @(d:24,erd) stc ccr,@-erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1
appendix rev. 3.00 may 15, 2007 page 471 of 516 rej09b0152-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n subx subx #xx:8, rd subx. rs, rd 1 1 trapa trapa #xx:2 2 1 2 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. n: specified value in r4l and r4. the source and destination operands are accessed n+1 times respectively. 2. it cannot be used in this lsi.
appendix rev. 3.00 may 15, 2007 page 472 of 516 rej09b0152-0300 a.4 combinations of instructions and addressing modes table a.5 combinations of instructions and addressing modes addressing mode mov pop, push movfpe, movtpe add, cmp sub addx, subx adds, subs inc, dec daa, das mulxu, mulxs, divxu, divxs neg extu, exts and, or, xor not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc andc, orc, xorc nop data transfer instructions arithmetic operations logical operations shift operations bit manipulations branching instructions system control instructions block data transfer instructions bwl ? ? bwl wl b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? b ? ? #xx rn @ern @(d:16.ern) @(d:24.ern) @ern+/@ern @aa:8 @aa:16 @aa:24 @(d:8.pc) @(d:16.pc) @@aa:8 ? bwl ? ? bwl bwl b l bwl b bw bwl wl bwl bwl bwl b ? ? ? ? ? ? b b ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? b ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw functions instructions
appendix rev. 3.00 may 15, 2007 page 473 of 516 rej09b0152-0300 b. i/o ports b.1 i/o port block diagrams p12 v cc v cc pucr12 pmr15 (irqaec) pdr12 pcr12 sby v ss irqaec ecpwm aecpwm aec module internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 figure b.1 (a) port 1 block diagram (p12)
appendix rev. 3.00 may 15, 2007 page 474 of 516 rej09b0152-0300 p11 v cc v cc pucr11 pmr14 (ftci) pmr13 (aevl) pfcr (irq1s1, irq1s0) pdr11 pcr11 sby v ss internal data bus pdr1: pcr1: pmr1: pucr1: pfcr : port data register 1 port control register 1 port mode register 1 port pull-up control register 1 pin function control register aevl aec module ftci timer w module irq1 figure b.1 (b) port 1 block diagram (p11)
appendix rev. 3.00 may 15, 2007 page 475 of 516 rej09b0152-0300 p12 v cc v cc pucr10 pmr12 (clkout) pmr11 (tmow) pdr10 pmr10 (aevh) pcr10 sby v ss aevh aec module internal data bus pdr1: pcr1: pmr1: pucr1: watch: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 watch mode tmow rtc module osc , osc/2 , osc/4 timer w output control signal a ftioa watch clkout figure b.1 (c) port 1 block diagram (p10)
appendix rev. 3.00 may 15, 2007 page 476 of 516 rej09b0152-0300 p32 v cc v cc pucr32 spcr (scinv1) spcr (spc3) pdr32 pcr32 sci3 module sby v ss txd3/irtxd internal data bus pdr3: pcr3: pucr3: spcr: port data register 3 port control register 3 port pull-up control register 3 serial port control register figure b.2 (a) port 3 block diagram (p32)
appendix rev. 3.00 may 15, 2007 page 477 of 516 rej09b0152-0300 p31 v cc v cc pucr31 pdr31 pcr31 sci3 module sby v ss re3 rxd3/irrxd internal data bus pdr3: pcr3: pucr3: spcr: port data register 3 port control register 3 port pull-up control register 3 serial port control register spcr (scinv0) figure b.2 (b) port 3 block diagram (p31)
appendix rev. 3.00 may 15, 2007 page 478 of 516 rej09b0152-0300 p30 v cc v cc pucr30 pmr30 (vcref) pfcr (irq0s1, irq0s0) pdr30 pcr30 sby v ss vcref comparator internal data bus sckie3 sckoe3 scko3 scki3 sci3 module irq0 pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 figure b.2 (c) port 3 block diagram (p30)
appendix rev. 3.00 may 15, 2007 page 479 of 516 rej09b0152-0300 p8n v cc pucr8n pdr8n pcr8n sby v ss internal data bus pdr8: pcr8: pucr8: watch: watch port data register 8 port control register 8 port pull-up control register 8 watch mode timer w output control signals b to d ftiob to ftiod n = 4 to 2 figure b.3 (a) port 8 block diagram (p84 to p82)
appendix rev. 3.00 may 15, 2007 page 480 of 516 rej09b0152-0300 p93 v cc pucr93 pdr93 pfcr (irq1s1, irq1s0) podr93 pcr93 sby v ss pdr9: pcr9: podr9: pucr9: port data register 9 port control register 9 port open-drain control register 9 port pull-up control register 9 ssu ssi output control ssi input control ssi nmos open-drain output control ssi output ssi input internal data bus irq1 note: when the ssus bit in pfcr is 1, the ssi pin is switched to the scs pin. figure b.4 (a) port 9 block diagram (p93)
appendix rev. 3.00 may 15, 2007 page 481 of 516 rej09b0152-0300 p92 v cc pucr92 pdr92 pfcr (irq0s1, irq0s0) podr92 pcr92 sby v ss pdr9: pcr9: podr9: pucr9: port data register 9 port control register 9 port open-drain control register 9 port pull-up control register 9 ssu sso output control sso input control sso nmos open-drain output control sso output sso input internal data bus irq0 note: when the ssus bit in pfcr is 1, the sso pin is switched to the ssck pin. figure b.4 (b) port 9 block diagram (p92)
appendix rev. 3.00 may 15, 2007 page 482 of 516 rej09b0152-0300 p91 v cc pucr91 pdr91 podr91 pcr91 sby v ss v ss pdr9: pcr9: podr9: pucr9: port data register 9 port control register 9 port open-drain control register 9 port pull-up control register 9 ssu ssck output control ssck input control ssck nmos open-drain output control ssck output ssck input internal data bus note: priority: ssu pin > iic2 pin > p91 when the ssus bit in pfcr is 1, the ssck pin is switched to the sso pin. iic2 bus module ice sdai sdao figure b.4 (c) port 9 block diagram (p91)
appendix rev. 3.00 may 15, 2007 page 483 of 516 rej09b0152-0300 p90 v cc pucr90 pdr90 podr90 pcr90 sby v ss v ss pdr9: pcr9: podr9: pucr9: port data register 9 port control register 9 port open-drain control register 9 port pull-up control register 9 ssu scs output control scs input control scs nmos open-drain output control scs output scs input internal data bus note: priority: ssu pin > iic2 pin > p90 when the ssus bit in pfcr is 1, the scs pin is switched to the ssi pin. iic2 bus module ice scli sclo figure b.4 (d) port 9 block diagram (p90)
appendix rev. 3.00 may 15, 2007 page 484 of 516 rej09b0152-0300 internal data bus pbn dec a/d module amr3 to amr0 vin comparator compm n = 5 or 4 m = 1 or 0 figure b.5 (a) port b block diagram (pb5 or pb4) internal data bus pbn dec a/d module amr3 to amr0 vin n = 3 or 2 figure b.5 (b) port b block diagram (pb3 or pb2)
appendix rev. 3.00 may 15, 2007 page 485 of 516 rej09b0152-0300 internal data bus pbn dec a/d module amr3 to amr0 vin pmrb: pfcr: n = 1 or 0 port mode register b pin function control register pmrbn pfcr (irqns1, irqns0) irqn figure b.5 (c) port b block diagram (pb1 or pb0)
appendix rev. 3.00 may 15, 2007 page 486 of 516 rej09b0152-0300 b.2 port states in each operating state port reset sleep (high-speed/ medium- speed) subsleep standby subactive active (high-speed/ medium- speed) watch p12 to p10 high impedance retained retained high impedance * 1 * 2 functions functions retained p32 to p30 high impedance retained retained high impedance * 1 * 2 functions functions retained p84 to p82 high impedance retained retained high impedance * 1 * 2 functions functions retained p93 to p90 high impedance retained retained high impedance * 1 * 2 functions functions retained pb5 to pb0 high impedance high impedance high impedance high impedance * 1 high impedance high impedance high impedance notes: 1. registers are retained an d output level is high impedance. 2. high-level output when the pull-up mos is turned on.
appendix rev. 3.00 may 15, 2007 page 487 of 516 rej09b0152-0300 b.3 port 9 related register settings and pin functions table b.1 port 9 related register settings and pin functions ssu setting pfcr setti ng pin functions ssums bide mss te re iic2 setting ice ssus irq1s1, irq1s0 irq0s1, irq0s0 p93 p92 p91 p90 other then 01 other then 01 ssi input p92 i/o ssck input p90 i/o 0 other then 01 01 ssi input irq0n input ssck input p90 i/o other then 01 other then 01 p93 i/o ssck input p91 i/o ssi input 0 1 (receive) 0 (iic2 not used) 1 01 other then 01 irq1n input ssck input p91 i/o ssi input other then 01 other then 01 p93 i/o sso output ssck input p90 i/o 0 01 other then 01 irq1n input sso output ssck input p90 i/o other then 01 other then 01 p93 i/o ssck input sso output p90 i/o 1 (transmit) 0 0 (iic2 not used) 1 01 other then 01 irq1n input ssck input sso output p90 i/o 0 other then 01 other then 01 ssi input sso output ssck input p90 i/o other then 01 other then 01 p93 i/o ssck input sso output ssi input 0 (clock synchro- nous) * 0 (slave) 1 (transmit) 1 (receive) 0 (iic2 not used) 1 01 other then 01 irq1n input ssck input sso output ssi input
appendix rev. 3.00 may 15, 2007 page 488 of 516 rej09b0152-0300 ssu setting pfcr setti ng pin functions ssums bide mss te re iic2 setting ice ssus irq1s1, irq1s0 irq0s1, irq0s0 p93 p92 p91 p90 other then 01 other then 01 ssi input p92 i/o ssck output p90 i/o 0 other then 01 01 ssi input irq0n input ssck output p90 i/o other then 01 other then 01 p93 i/o ssck output p91 i/o ssi input 0 1 (receive) 0 (iic2 not used) 1 01 other then 01 irq1n input ssck output p91 i/o ssi input other then 01 other then 01 p93 i/o sso output ssck output p90 i/o 0 01 other then 01 irq1n input sso output ssck output p90 i/o other then 01 other then 01 p93 i/o ssck output sso output p90 i/o 1 (transmit) 0 0 (iic2 not used) 1 01 other then 01 irq1n input ssck output sso output p90 i/o 0 other then 01 other then 01 ssi input sso output ssck output p90 i/o other then 01 other then 01 p93 i/o ssck output sso output ssi input 0 (clock synchro- nous) * 1 (master) 1 (transmit) 1 (receive) 0 (iic2 not used) 1 01 other then 01 irq1n input ssck output sso output ssi input
appendix rev. 3.00 may 15, 2007 page 489 of 516 rej09b0152-0300 ssu setting pfcr setti ng pin functions ssums bide mss te re iic2 setting ice ssus irq1s1, irq1s0 irq0s1, irq0s0 p93 p92 p91 p90 other then 01 other then 01 p93 i/o sso input ssck input scs input 0 01 other then 01 irq1n input sso input ssck input scs input 0 1 (receive) 0 (iic2 not used) 1 other then 01 other then 01 scs input ssck input sso input p90 i/o other then 01 other then 01 ssi output p92 i/o ssck input scs input 0 other then 01 01 ssi output irq0n input ssck input scs input 1 (transmit) 0 0 (iic2 not used) 1 other then 01 other then 01 scs input ssck input p91 i/o ssi output 0 other then 01 other then 01 ssi output sso input ssck input scs input 0 (slave) 1 (transmit) 1 (receive) 0 (iic2 not used) 1 other then 01 other then 01 scs input ssck input sso input ssi output other then 01 other then 01 ssi input p92 i/o ssck output scs output 0 other then 01 01 ssi input irq0n input ssck output scs output 0 1 (receive) 0 (iic2 not used) 1 other then 01 other then 01 scs output ssck output p91 i/o ssi input other then 01 other then 01 p93 i/o sso output ssck output scs output 0 01 other then 01 irq1n input sso output ssck output scs output 1 (transmit) 0 0 (iic2 not used) 1 other then 01 other then 01 scs output ssck output sso output p90 i/o 0 other then 01 other then 01 ssi input sso output ssck output scs output 1 (four-line bus commu- nication) 0 (one-way) 1 (master) 1 (transmit) 1 (receive) 0 (iic2 not used) 1 other then 01 other then 01 scs output ssck output sso output ssi input
appendix rev. 3.00 may 15, 2007 page 490 of 516 rej09b0152-0300 ssu setting pfcr setti ng pin functions ssums bide mss te re iic2 setting ice ssus irq1s1, irq1s0 irq0s1, irq0s0 p93 p92 p91 p90 other then 01 other then 01 p93 i/o sso input ssck input scs input 0 01 other then 01 irq1n input sso input ssck input scs input 0 1 (receive) 0 (iic2 not used) 1 other then 01 other then 01 scs input ssck input sso input p90 i/o other then 01 other then 01 p93 i/o sso output ssck input scs input 0 01 other then 01 irq1n input sso output ssck input scs input 0 (slave) 1 (transmit) 0 0 (iic2 not used) 1 other then 01 other then 01 scs input ssck input sso output p90 i/o other then 01 other then 01 p93 i/o sso input ssck output scs output 0 01 other then 01 irq1n input sso input ssck output scs output 0 1 (receive) 0 (iic2 not used) 1 other then 01 other then 01 scs output ssck output sso input p90 i/o other then 01 other then 01 p93 i/o sso output ssck output scs output 0 01 other then 01 irq1n input sso output ssck output scs output 1 (four-line bus commu- nication) 1 (bidirec- tional) 1 (master) 1 (transmit) 0 0 (iic2 not used) 1 other then 01 other then 01 scs output ssck output sso output p90 i/o other then 01 other then 01 p93 i/o p92 i/o sda i/o scl i/o other then 01 01 p93 i/o irq0n input sda i/o scl i/o 01 other then 01 irq1n input p92 i/o sda i/o scl i/o 1 (iic2 used) * 01 01 irq1n input irq0n input sda i/o scl i/o other then 01 other then 01 p93 i/o p92 i/o p91 i/o p90 i/o other then 01 01 p93 i/o irq0n input p91 i/o p90 i/o 01 other then 01 irq1n input p92 i/o p91 i/o p90 i/o 0 (ssu not used) 0 0 0 0 0 (iic2 not used) * 01 01 irq1n input irq0n input p91 i/o p90 i/o [legend] * : don't care.
appendix rev. 3.00 may 15, 2007 page 491 of 516 rej09b0152-0300 c. product part no. lineup product classification product part no. model marking package (package code) (10 mhz) hd64f38602rft10 38602r10 (4 mhz) hd64f38602rft4 38602r4 32-pin qfn (tnp-32) (10 mhz) HD64F38602RFH10 f38602rfh10 flash memory version (4 mhz) hd64f38602rfh4 f38602rfh4 32-pin lqfp (32p6u-a) hd64338602rft 38602r( *** ) 32-pin qfn (tnp-32) h8/38602r masked rom version hd64338602rfh 38602r( *** ) 32-pin lqfp (32p6u-a) hd64338600rft 38600r( *** ) 32-pin qfn (tnp-32) h8/38602r group h8/38600r masked rom version hd64338600rfh 38600r( *** ) 32-pin lqfp (32p6u-a) [legend] ( *** ): rom code
appendix rev. 3.00 may 15, 2007 page 492 of 516 rej09b0152-0300 d. package dimensions the package dimensions that are shown in the renesas semiconductor packages data book have priority. previous code jeita package code renesas code tnp-32/tnp-32v mass[typ.] 0.06g p-vqfn32-5x6-0.50 pvqn0032ka-a max nom min dimension in millimeters symbol reference 0.05 0.5 0.17 0.22 0.27 0.95 6.2 0.05 5.2 6.0 5.0 0.50 0.60 0.70 0.89 0.005 0.02 0.04 0.20 0.20 0.20 1.0 1.0 0.17 0.20 0.22 0.25 t 1 y p e d 1 1 2 l z z y x b b a a e d a e e 1 e d c h c h 1 b p 2 1 1 c y e d d e x4 t y 1 25 17 26 32 16 9 10 1 l b h e h d a a a c z z m note: don't connect the exposed part of die-pad-support-leads to the pads on a printed wiring board (pwb). figure d.1 package dimensions (tnp-32)
appendix rev. 3.00 may 15, 2007 page 493 of 516 rej09b0152-0300 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark * 3 f 32 25 24 17 16 9 8 1 * 1 * 2 x b p e h e e d h d z d z e detail f l 1 l a c a 2 a 1 previous code jeita package code renesas code plqp0032gb-a 32p6u-a mass[typ.] 0.2g p-lqfp32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section b 1 c 1 bp c figure d.2 package dimensions (32p6u-a)
appendix rev. 3.00 may 15, 2007 page 494 of 516 rej09b0152-0300
rev. 3.00 may 15, 2007 page 495 of 516 rej09b0152-0300 main revisions and add itions in this edition item page revisions (s ee manual for details) section 1 overview 1.1 features ? compact package 1 the description on the package, p-lqfp-32, is added. section 2 cpu 2.8.2 eepmov instruction 36 modified eepmov is a block-transfer instruction and transfers the byte size of data indicated by r4 or r4l, which starts from the address indicated by r5, to the address indicated by r6. set r4, r4l, and r6 so that the end address of the destination address (value of r6 + r4l or r6 + r4) does not exceed h 'ffff (the value of r6 must not change from h'ffff to h'0000 during execution). section 3 exception handling 3.2 reset 44 modified a reset has the highest exception priority. there are three sources to generate a reset. table 3.2 lists the reset sources. table 3.2 reset sources 44 added 3.2.1 reset exception handling 44 the descr iption in this se ction is modified. 3.8.1 notes on stack area use 58 modified , so the stack pointer (sp: r7) should never indicate an odd address. to save register values, use push.w rn (mov.w rn, @?sp) or push.l ern (mov.l ern, @?sp). to restore register values, use pop.w rn (mov.w @sp+, rn) or pop.l ern (mov.l @sp+, ern).
rev. 3.00 may 15, 2007 page 496 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 67 modified the input level on the e7_2 pin during a reset is pulled up or down using a resistor according to the selected oscillator, and fixed on exit from the reset state. when the on-chip oscillator is selected, a resonator no longer needs to be connected to the osc1 and osc2 pins. in such a case, fix the osc1 pin to gnd or leave it open, and leave the osc2 pin open. section 4 clock pulse generators 4.2.4 on-chip oscillator selection method note is added. notes: 1. 2. when the on-chip debugger is connected, the value of the resistor should be high. when not connected, it is specified according to the selected oscillator. figure 4.5 typical connection to 32.768-khz/38.4-khz crystal resonator 68 modified note: consult with the crystal resonator manufacturer to determine the parameters. frequency manufacturer 32.768 khz 38.4 khz epson toyocom corporation products name c-4-type c-001r c = c = 7 pf (typ.) 1 2 equivalent series resistance epson toyocom corporation 30 k ? (max.) 35 k ? (max.) 4.3.1 connecting 32.768- khz/38.4-khz crystal resonator 68 added 1. when the resonator othe r than ones listed above is used, perform matching evaluation with the crystal resonator manufacture and connect it under the optimum condition. even when the resonator listed above or the equivalent is used, as the oscillation characteristics depend on the board specification, perform matching evaluation on the mounting board. 2. perform matching evaluatio n in the reset state (the res pin is low) and on exit from the reset state (the res pin is driven from low to high). 4.4.1 prescaler s 71 deleted the output from prescaler s is shared by the on-chip peripheral modules. the division ratio can be set separately for each on - chip peripheral function.
rev. 3.00 may 15, 2007 page 497 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 4.5.1 note on resonators and resonator circuits 72 modified resonator characteristics are closely related to board design. therefore, resonators should be assigned after being carefully evaluated by the user in the masked rom version and flash memory version, with referring to the examples shown in this section. 4.5.3 definition of oscillation stabilization wait time 74 the description in this section is modified. figure 4.12 oscillation stabilization wait time 75 modified oscillation waveform (osc2) system clock ( ) oscillation stabilization wait time standby mode, watch mode, or subactive mode oscillation start time active (high-speed) mode or active (medium-speed) mode wait time interrupt accepted operating mode 4.5.5 note on the oscillation stabilization of resonators 76 the title modified 4.5.6 note on using power-on reset 76 modified the power-on reset circuit in this lsi adjusts the reset clear time by the capacitor capacitance, which is externally connected to the res pin. the external capacitor capacitance should be adjusted to secure the oscillation stabilization time before reset clearing. for details, refer to section 19, power-on reset circuit. section 5 power-down modes 5.1.3 clock halt registers 1 and 2 (ckstpr1 and ckstpr2) ? ckstpr2 81 the note is modified. notes: 3. when the watchdog timer stops operating and the wdon bit is cleared to 0 by software, this bit is valid and the watchdog timer enter s module standby mode. table 5.3 internal state in each operating mode 86 the note is modified. notes: 6. functions if the 32.768- khz rtc is selected as an internal clock. halted and retained otherwise.
rev. 3.00 may 15, 2007 page 498 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 88 modified however, as long as the rated voltage is supplied, the contents of cpu registers, on - chip ram, and some on-chip peripheral module registers are retained. 5.2.2 standby mode modified or the requested interrupt is disabled by the interrupt enable bit. when a reset source is generated in standby mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes and the t rel period has elapsed. the cpu starts reset exception handling when the res pin is driven high. 5.2.3 watch mode 88 modified or the requested interrupt is disabled by the interrupt enable register. when a reset source is generated in watch mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes. the cpu starts reset exception handling when the res pin is driven high. 5.2.4 subsleep mode 89 modified or the requested interrupt is disabled by the interrupt enable register. when a reset source is generated in subsleep mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes. the cpu starts reset exception handling when the res pin is driven high. 5.2.5 subactive mode 89 modified on the combination of bits ssby, lson, and tma3 in syscr1 and bits mson and dton in syscr2. subactive mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enable register. when a reset source is generated in subactive mode, the system clock oscillator starts. if a reset is generated by the res pin, it must be kept low until the system clock oscillator output stabilizes and the t rel period has elapsed. the cpu starts reset exception handling when the res pin is driven high.
rev. 3.00 may 15, 2007 page 499 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 5.2.6 active (medium-speed) mode 90 modified in active (medium-speed) mode, the clock set by the ma1 and ma0 bits in syscr1 is used as the system clock, and the cpu and on-chip peripheral modules function. active (medium-speed) mode is cleared by the sleep instruction. when active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combinatio n of bits ssby, lson, and tma3 in syscr1, a transition to watch mode is made depending on the combination of bits ssby and tma3 in syscr1, or a trans ition to sleep mode is made depending on the combination of bits ssby and lson in syscr1. moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. active (medium - sleep) mode is not entered if the i bit in ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the res pin goes low, the cpu goes into the reset state and active (medium-sleep) mode is cleared. in active (medium - sp eed) mode, the on - chip peripheral modules function at the clock set by the ma1 and ma0 bits in syscr1. 5.3 direct transition 91 the description in this section is modified. 5.3.1 direct transition from active (high-speed) mode to active (medium-speed) mode 91 added when a sleep instruction is executed in active (high- speed) mode while the ssby and lson bits in syscr1 are cleared to 0 and the mson and dton bits in syscr2 are set to 1, a transition is made to active (medium-speed) mode via sleep mode. the time from the start of sleep instruction execution to the end of interrupt exc eption handling (the direct transition time) is calculated by equation (1). example: when osc/8 is selected as the cpu operating clock after the transition direct transition time = (2 + 1) 1tosc + 14 8tosc = 115tosc for the legend of symbols used above, refer to section 21, electrical characteristics.
rev. 3.00 may 15, 2007 page 500 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 5.3.2 direct transition from active (high-speed) mode to subactive mode 92 added when a sleep instruction is executed in active (high- speed) mode while the ssby, tma3, and lson bits in syscr1 are set to 1 and the dton bit in syscr2 is set to 1, a transition is made to subactive mode via watch mode. the time from the start of sleep instruction execution to the end of interrupt exc eption handling (the direct transition time) is calculated by equation (2). example: when w/8 is selected as the subactive operating clock after the transition direct transition time = (2 + 1) 1tosc + 14 8tw = 3tosc + 112tw for the legend of symbols used above, refer to section 21, electrical characteristics. 5.3.3 direct transition from active (medium-speed) mode to active (high-speed) mode 92 added when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. the time from the start of sleep instruction execution to the end of interrupt exc eption handling (the direct transition time) is calculated by equation (3). example: when osc/8 is selected as the cpu operating clock before the transition direct transition time = (2 + 1) 8tosc + 14 1tosc = 38tosc for the legend of symbols used above, refer to section 21, electrical characteristics.
rev. 3.00 may 15, 2007 page 501 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 5.3.4 direct transition from active (medium-speed) mode to subactive mode 93 added when a sleep instruction is executed in active (medium-speed) mode while the ssby, lson, and tma3 bits in syscr1 are set to 1 and the dton bit in syscr2 is set to 1, a transition is made to subactive mode via watch mode. the time from the start of sleep instruction execution to the end of interrupt exc eption handling (the direct transition time) is calculated by equation (4). example: when osc/8 and w/8 are selected as the cpu operating clock before and after the transition, respectively direct transition time = (2 + 1) 8tosc + 14 8tw = 24tosc + 112tw for the legend of symbols used above, refer to section 21, electrical characteristics. 5.3.5 direct transition from subactive mode to active (high- speed) mode 93 added and modified when a sleep instruction is executed in subactive mode while the ssby and tma3 bits in syscr1 are set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a trans ition is made directly to active (high-speed) mode via watch mode after the waiting time set in bits st s2 to sts0 in syscr1 has elapsed. the time from the start of sleep instruction execution to the end of interrupt exc eption handling (the direct transition time) is calculated by equation (5). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} (tsubcyc before transition) + (wait time set in bits sts2 to sts0) + (number of interrupt exception handling execution states) (tcyc after transition)?..(5) example: when w/8 is selected as the cpu operating clock after the transition and wait time = 8192 states direct transition time = (2 + 1) 8tw + (8192 + 14) 1tosc = 24tw + 8206tosc for the legend of symbols used above, refer to section 21, electrical characteristics.
rev. 3.00 may 15, 2007 page 502 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 5.3.6 direct transition from subactive mode to active (medium-speed) mode 94 added when a sleep instruction is executed in subactive mode while the ssby and tma3 bits in syscr1 are set to 1, the lson bit in syscr1 is cleared to 0, and the mson and dton bits in syscr2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits sts2 to sts0 in syscr1 has elapsed. the time from the start of sleep instruction execution to the end of interrupt exc eption handling (the direct transition time) is calculated by equation (6). example: when w/8 and osc/8 are selected as the cpu operating clock before and after the transition, respectively, and wait time = 8192 states direct transition time = (2 + 1) 8tw + 8192 1tosc + 14 8tosc = 24tw + 8304tosc for the legend of symbols used above, refer to section 21, electrical characteristics. section 6 rom 6.7 notes on setting module standby mode 117 modified then the flash memory should be set to enter the module standby mode. if an interrupt is generated in module standby mode, the vector address cannot be fetched. as a result, the program may run away. section 8 i/o ports 8.1.5 pin functions ? p10/aevh/ftioa/tmow/cl kout pin 122 added note: * switching the clock ( osc , osc /2, or osc /4) for clkout output must be performed when clkout output is halted (clkout = 0). when making a transition to a power-down mode wherein the system clock oscillator is halted, the output level is retained. (in standby mode, output is the hi gh-impedance state.) when making a transition from a power-down mode wherein the system clock oscillator is halted, to the active mode wherein the system clock oscillator operates, halt clkout output (clkout = 0) before the transition. 8.7.2 input characteristics difference due to pin function 124 this section is newly added.
rev. 3.00 may 15, 2007 page 503 of 516 rej09b0152-0300 item page revisions (s ee manual for details) section 9 timer b1 figure 9.2 timer b1 initial setting flow 148 modified cancel the module standby mode of timer b1 * 1 set counter function with bit tmb17 in tmb1 and counter clock with bits tmb12 to tmb10 in tmb1 (bit tmb16 must be cleared to 0 when writing to these bits) modified bit bit name description 3 2 1 0 rcs3 rcs2 rcs1 rcs0 clock source selection 0000: /8 ?????????????????? free running counter operation 0001: /32 ???????????????? free running counter operation 0010: /128 ?????????????? free running counter operation 0011: /256 ?????????????? free running counter operation 0100: /512 ?????????????? free running counter operation 0101: /2048 ???????????? free running counter operation 0110: /4096 ???????????? free running counter operation 0111: /8192 ???????????? free running counter operation 1000: w /4 ????????????????? rtc operation 1001 to 1111: setting prohibited section 11 realtime clock (rtc) 11.3.7 clock source select register (rtccsr) 193 11.4.1 initial settings of registers after power-on 196 modified the rtc registers that st ore second, minute, hour, and day-of-week data, control registers, and interrupt registers are not reset by a res input, or by a reset source caused by a watchdog timer. 11.5 interrupt sources 198 modified when using an interrupt, set the ienrtc (rtc interrupt request enable) bit in ienr1 to 1 last after other registers are set. 11.6.2 note when using rtc interrupts 199 added
rev. 3.00 may 15, 2007 page 504 of 516 rej09b0152-0300 item page revisions (s ee manual for details) added bit bit name description 0 wrst watchdog timer reset indicates whether a reset caused by the watchdog timer is generated. this bit is not cleared by a reset caused by the watchdog timer. [setting condition] when tcwd overflows and an internal reset signal is generated section 12 watchdog timer 12.2.1 timer control/status register wd1 (tcsrwd1) 203 12.3.1 watchdog timer mode 208 modified when a clock pulse is input after the tcwd count value has reached h'ff, the watchdog timer overflows and an internal reset signal is generated. the internal reset signal is output for a period of 512 clock cycles by the on-chip oscillator (r osc ). figure 12.2 example of watchdog timer operation 208 modified tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated start 512 clock cycles by r osc figure 12.3 interval timer mode operation 209 modified tcwd count value h'00 time h'ff interval timer interrupt request generated interval timer interrupt request generated interval timer interrupt request generated interval timer interrupt request generated interval timer interrupt request generated wt/ it = 1 12.5.3 clearing the wt/it or ieovf bit in tcsrwd2 to 0 210 added table 12.1 assemb ly program for clearing wt/it or ieovf bit to 0 211 added
rev. 3.00 may 15, 2007 page 505 of 516 rej09b0152-0300 item page revisions (s ee manual for details) table 12.2 the value of "xx" 211 added modified bit bit name description 7 ech7 6 ech6 5 ech5 4 ech4 3 ech3 2 ech2 1 ech1 0 ech0 either the external asynchronous event aevh pin, /2, /4, or /8, or the overflow signal from lower 8- bit counter ecl can be selected as the input clock source. ech can be cleared to h'00 when the crch bit in eccsr is cleared to 0. section 13 asynchronous event counter (aec) 13.3.6 event counter h (ech) 222 modified bit bit name description 7 ecl7 6 ecl6 5 ecl5 4 ecl4 3 ecl3 2 ecl2 1 ecl1 0 ecl0 either the external asynchronous event aevl pin, /2, /4, or /8 can be selected as the input clock source. ecl can be cleared to h'00 when the crcl bit in eccsr is cleared to 0. 13.3.7 event counter l (ecl) 222 section 14 serial communication interface 3 (sci3, irda) 231 deleted the serial communication interface 3 (sci3) can handle both asynchronous and clock synchronous serial communication. in the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function). modified bit bit name description 2 mp 5-bit communicationwhen this bit is set to 1, the 5-bit communication format is enabled. make sure to set bit 5 (pf) to 1 when setting this bit (mp) to 1. 14.3.5 serial mode register (smr) 235
rev. 3.00 may 15, 2007 page 506 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 14.3.6 serial control register (scr) 237 bit 3 is reserved. 240 deleted ssr consists of status flags of the sci3 and multiprocessor bits for transfer . 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. 14.3.7 serial status register (ssr) 240 bits 1 and 0 are reserved. modified bit bit name description 7 ire irda enableselects w hether the sci3 i/o pins function as the sci3 or irda.0: txd3/irtxd and rxd3/irrxd pins function as txd3 and rxd31: txd3/irtxd and rxd3/irrxd pins function as irtxd and irrxd 14.3.10 irda control register (ircr) 252 added bit bit name description 3 abcs asynchronous mode basic clock select selects the basic clock for the bit period in asynchronous mode. this setting is enabled only in asynchronous mode (com bit in smr3 is 0). 0: operates on a basic clock with a frequency of 16 times the transfer rate 1: operates on a basic clock with a frequency of eight times the transfer rate clear the abcs bit to 0, when the irda function is enabled. 14.3.11 serial extended mode register (semr) 253 table 14.8 data transfer formats (asynchronous mode) 255 the formats are modified. table 14.9 smr settings and corresponding data transfer formats 256 the settings are modified.
rev. 3.00 may 15, 2007 page 507 of 516 rej09b0152-0300 item page revisions (s ee manual for details) figure 14.4 sample sci3 initialization flowchart 258 modified wait no yes set spc3 bit in spcr to 1 [4] 1-bit interval elapsed? [[4] wait at least one bit interval, then set the te bit or re bit in scr to 1. setting bits te and re enables the txd3 and rxd3 pins to be used. also set the rie, tie, and teie bits, depending on whether interrupts are required. in asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. set te and re bits in scr to 1, and set rie, tie and teie bits. figure 14.6 sample serial transmission flowchart (asynchronous mode) 260 modified no yes [3] clear pdr to 0 and set pcr to 1 break output? note: * when the spc3 bit in spcr is cleared to 0, the pin functions as an i/o port. [3] to output a break in serial transmission, after setting pcr to 1 and pdr to 0, clear the spc3 bit in spcr and the te bit in scr to 0. clear spc3 bit in spcr and te bit in scr to 0 * 14.5 operation in clock synchronous mode 264 deleted after 8-bit data is output, the transmission line holds the msb state. in clock syn chronous mode, no parity or multiprocessor bit is added. 14.6 multiprocessor communication function 270 this section is deleted.
rev. 3.00 may 15, 2007 page 508 of 516 rej09b0152-0300 item page revisions (s ee manual for details) 14.8.2 mark state and break sending 277 modified when the spc3 bit in spcr is 0, the txd3 pin functions as an i/o port whose direction (input or output) and level are determined by pcr and pdr, regardless of the te setting. this can be used to set the txd3 pin to the mark state (high level) or send a break during data transmission. to maintain the communication line at the mark state until the spc3 bit in spcr is set to 1, set both pcr and pdr to 1. as the spc3 bit in spcr is cleared to 0 at this point, the txd3 pin functions as an i/o port, and 1 is output from the txd3 pin. to send a break during data transmission, first set pcr to 1 and pdr to 0, and then clear the spc3 and te bits to 0. when the te bit is cleared to 0 directly after the spc3 bit is cleared to 0, the transmitter is initialized regardless of the current transmission state after the te bit is cleared, the txd3 pin functions as an i/o port after the spc3 bit is cleared, and 0 is output from the txd3 pin. modified bit bit name description 3 stop stop condition detection flag[setting conditions] ? in master mode, when a stop condition is detected after the completion of frame transfer ? in slave mode, when a stop condition is detected, after the slave address of the first byte, following the general call and the detection of the start condition, matches the address set in sar section 16 i2c bus interface 2 (iic2) 16.3.5 i 2 c bus status register (icsr) 323
rev. 3.00 may 15, 2007 page 509 of 516 rej09b0152-0300 item page revisions (s ee manual for details) figure 16.15 receive mode operation timing 339 modified sda (input) 7812 data 2 data 3 data 1 data 2 bit 6 bit 7 bit 1 bit 0 scl mst trs rdrf icdrs icdrr user processing [3] read icdrr section 17 a/d converter 17.3.1 a/d result register (adrr) 350 modified adrr is a 16-bit read-only re gister that stores the results of a/d conversion. the data is stored in the upper 10 bits of adrr. adrr can be read by the cpu at any time, 17.7.3 usage notes 360 deleted 3. when a/d conversion is started after clearing module standby mode, wait for 10 clock cycles before starting a/d conversion. 4. when the la ds bit in ads r is changed as from halting to operating, wait for 10 clock cycles before starting a/d conversion.
rev. 3.00 may 15, 2007 page 510 of 516 rej09b0152-0300 item page revisions (s ee manual for details) section 18 comparators 18.5 usage notes 368 modified 4. if the lsi enters the software standby mode or watch mode when a comparator is operating, the internal operation of the comparator is maintained. since the comparator operates even in software standby mode or watch mode, it returns to the same mode after the specified interrupt is canc eled, though the current for the comparator is consumed. if a comparator is not required to return to the software standby mode or watch mode when an interrupt is canceled and the current consumption needs to be reduced, stop the comparator by clearing the cme0 and cme1 bits in cmcr0 and cmcr1 to 0 before shifting the mode. section 19 power-on reset circuit 19.2.1 power-on reset circuit 370 modified the operation timing of the power-on reset circuit is shown in figure 19.2. as the power supply voltage rises, the capacitor, which is externally connected to the res pin, is gradually charged through the on-chip pull-up resistor (rp). modified values item symbol applicable pins test condition min. typ. max. ceramic resonator (v cc = 2.2 v to 3.6 v) ? 20 45 ceramic resonator (other than above) ? 80 ? crystal resonator (v cc = 2.7 v to 3.6 v) ? 300 800 oscill ation stabili zation time trc osc1,osc2 crystal resonator (v cc = 2.2 v to 3.6 v) ? 600 1000 section 21 electrical characteristics table 21.3 control signal timing 411
rev. 3.00 may 15, 2007 page 511 of 516 rej09b0152-0300 item page revisions (s ee manual for details) modified values item symbol applicable pins test condition min. typ. max. ceramic resonator(vcc = 2.2 v to 3.6 v) ? 20 45 ceramic resonator(other than above) ? 80 ? crystal resonator(vcc = 2.7 v to 3.6 v) ? 300 800 oscill ation stabili zation time trc osc1,osc2 crystal resonator(vcc = 2.2 v to 3.6 v) ? 600 1000 table 21.14 control signal timing 425 appendix a.1 instruction list 2. arithmetic instructions 447 modified mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzv #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? operation rd8 decimal adjust rd8 b22 ? * 2 normal advanced ? ? * daa c ? c. product part no. lineup 491 the list is modified. d. package dimensions figure d.2 package dimensions (32p6u-a) 492 added
rev. 3.00 may 15, 2007 page 512 of 516 rej09b0152-0300
rev. 3.00 may 15, 2007 page 513 of 516 rej09b0152-0300 index a a/d converter ......................................... 349 addressing modes..................................... 27 absolute address................................... 28 immediate ............................................. 29 memory indirect ................................... 29 program-counter relative ...................... 29 register direct....................................... 28 register indirect.................................... 28 register indirect w ith displacement...... 28 register indirect with post-increment... 28 register indirect with pre-decrement.... 28 asynchronous event counter (aec) ....... 213 16-bit counter operation...................... 223 8-bit counter operation........................ 224 event counter pwm operation ........... 225 c clock pulse generators.............................. 63 system clock oscillator ......................... 66 comparators............................................ 361 hysteresis characteristics.................... 366 condition fi eld.......................................... 26 condition-code register (ccr)................. 11 cpu ............................................................ 7 e effective address....................................... 30 effective address extension ...................... 26 exception handling ................................... 41 f flash memory ........................................... 99 boot mode........................................... 105 boot program ...................................... 104 erasing a block.................................... 100 erasing/erasing-verifying.................... 112 error protection................................... 114 hardware protection............................ 114 on-board progra mming modes ........... 104 power-down st ates .............................. 115 programming units.............................. 100 programming/erasure in user program mode.................................................... 108 programming/programming-verifying 109 software protection............................. 114 g general registers ....................................... 10 i i/o ports .................................................. 119 i 2 c bus format ......................................... 328 i 2 c bus interface 2 (iic2)........................ 311 acknowledge ...................................... 328 bit synchronous circuit ....................... 346 clocked synchronous serial format..... 337 noise canceler..................................... 340 slave address....................................... 328 start cond ition..................................... 328 stop condition ..................................... 328 transfer rate ........................................ 316 instruction set............................................ 16 arithmetic operations instructions ........ 18 bit manipulation instructions ................ 21 block data transfer instructions............. 25 branch instructions ............................... 23 data transfer instructions ...................... 17 logic operations instructions ................ 20
rev. 3.00 may 15, 2007 page 514 of 516 rej09b0152-0300 shift instructions................................... 20 system control instructions................... 24 interrupt mask bit (i)................................. 11 irda........................................................ 271 l large current port ................................... 119 large current ports...................................... 1 m memory map .............................................. 8 o operation field.......................................... 26 p package....................................................... 2 pin assignment............................................ 3 power-down modes .................................. 77 power-down modes module standby function ...................... 96 sleep mode ........................................... 87 standby mode ....................................... 88 subactive mode .................................... 89 subsleep mode...................................... 89 power-on reset circuit............................. 369 program counter (pc)............................... 11 r realtime cloc k (rtc)............................. 185 data reading procedure....................... 197 initial setting procedure ...................... 196 register field ............................................ 26 registers adrr ......................... 350, 374, 378, 382 adsr.......................... 352, 374, 378, 382 aegsr ....................... 218, 374, 378, 381 amr ........................... 351, 374, 378, 382 brr ............................ 243, 374, 378, 382 ckstpr1 ..................... 81, 375, 379, 383 ckstpr2 ..................... 81, 375, 379, 383 cmcr......................... 362, 373, 377, 381 cmdr......................... 364, 373, 377, 381 ebr1........................... 103, 372, 376, 380 eccr.......................... 219, 374, 378, 381 eccsr........................ 220, 374, 378, 381 ech ............................ 222, 374, 378, 381 ecl............................. 222, 374, 378, 381 ecpwcr.................... 216, 374, 377, 381 ecpwdr.................... 217, 374, 377, 381 fenr .......................... 104, 372, 376, 380 flmcr1..................... 101, 372, 376, 380 flmcr2..................... 102, 372, 376, 380 flpwcr .................... 103, 372, 376, 380 gra............................ 165, 373, 377, 381 grb ............................ 165, 373, 377, 381 grc ............................ 165, 373, 377, 381 grd............................ 165, 373, 377, 381 iccr1 ......................... 314, 372, 376, 380 iccr2 ......................... 317, 372, 376, 380 icdrr ........................ 327, 372, 376, 380 icdrs................................................. 327 icdrt ........................ 326, 372, 376, 380 icier.......................... 321, 372, 376, 380 icmr .......................... 319, 372, 376, 380 icsr ........................... 323, 372, 376, 380 iegr ............................. 47, 375, 379, 383 ienr ............................. 48, 375, 379, 383 ircr ............................ 252, 374, 378, 382 irr................................ 50, 375, 379, 383 osccr ......................... 64, 375, 379, 383 pcr1........................... 120, 375, 379, 382 pcr3........................... 125, 375, 379, 382 pcr8........................... 129, 375, 379, 382
rev. 3.00 may 15, 2007 page 515 of 516 rej09b0152-0300 pcr9........................... 133, 375, 379, 382 pdr1 .......................... 120, 375, 378, 382 pdr3 .......................... 125, 375, 378, 382 pdr8 .......................... 129, 375, 378, 382 pdr9 .......................... 133, 375, 378, 382 pdrb.......................... 138, 375, 378, 382 pfcr .......................... 143, 373, 376, 380 pmr1.......................... 121, 375, 378, 382 pmr3.......................... 126, 375, 378, 382 pmrb ......................... 139, 375, 378, 382 podr9 ....................... 134, 373, 376, 380 pucr1........................ 121, 375, 378, 382 pucr3........................ 126, 375, 379, 382 pucr8........................ 130, 373, 376, 380 pucr9........................ 134, 373, 376, 380 rdr............................ 234, 374, 378, 382 rhrdr ...................... 189, 372, 376, 380 rmindr .................... 188, 372, 376, 380 rsecdr..................... 187, 372, 376, 380 rsr..................................................... 234 rtccr1 ..................... 191, 372, 376, 380 rtccr2 ..................... 192, 372, 376, 380 rtccsr..................... 193, 372, 376, 380 rtcflg..................... 194, 372, 376, 380 rwkdr ..................... 190, 372, 376, 380 sar ............................ 326, 372, 376, 380 scr............................. 237, 374, 378, 382 semr ......................... 253, 374, 378, 382 smr............................ 235, 374, 378, 382 spcr ...................142, 251, 374, 378, 381 sscrh ....................... 285, 373, 377, 381 sscrl........................ 287, 373, 377, 381 sser........................... 290, 373, 377, 381 ssmr ......................... 289, 373, 377, 381 ssr ............................. 240, 374, 378, 382 ssrdr ....................... 293, 373, 377, 381 sssr........................... 291, 373, 377, 381 sstdr........................ 293, 373, 377, 381 sstrsr.............................................. 293 syscr1 ....................... 78, 375, 379, 383 syscr2........................ 80, 375, 379, 383 tcb1........................... 147, 373, 376, 380 tcnt .......................... 164, 373, 377, 381 tcrw......................... 158, 373, 377, 381 tcsrwd1.................. 203, 374, 378, 382 tcsrwd2.................. 205, 374, 378, 382 tcwd......................... 206, 374, 378, 382 tdr ............................ 234, 374, 378, 382 tierw........................ 159, 373, 377, 381 tior0 ......................... 161, 373, 377, 381 tior1 ......................... 163, 373, 377, 381 tlb1................................................... 147 tmb1.......................... 146, 373, 376, 380 tmrw ........................ 157, 373, 377, 381 tmwd........................ 207, 374, 378, 382 tsr ..................................................... 234 tsrw ......................... 160, 373, 377, 381 s serial communication interface 3 (sci3) asynchronous mode............................ 253 bit rate................................................. 243 break................................................... 277 clocked synchronous mode ................ 265 framing error ...................................... 261 mark state ........................................... 277 overrun error ...................................... 261 parity error .......................................... 261 stack pointer (sp) ..................................... 11 synchronous serial communication unit (ssu) ...................................................... 283 clock polarity...................................... 294 clocked synchronous communication mode.................................................... 297 communication mode ......................... 296 transfer clock ..................................... 293
rev. 3.00 may 15, 2007 page 516 of 516 rej09b0152-0300 t timer b1................................................. 145 auto-reload timer operation ............... 150 interval timer operation ...................... 150 timer w ................................................. 153 pwm opera tion .................................. 170 v vector address........................................... 42 w watchdog timer....................................... 201
renesas 16-bit single-chip microcomputer hardware manual h8/38602r group publication date: rev.1.00, may 20, 2004 rev.3.00, may 15, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan.
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