View A3987SLP-T_7336120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the a3987 is a complete microstepping motor driver with built-in translator for easy operation. it is designed to operate bipolar stepper motors in full, half, quarter, and sixteenth step modes, with output drive capability of 50 v and 1.5 a. the a3987 includes a fixed off-time current regulator, which has the ability to operate in slow or mixed decay modes. the translator is the key to the easy implementation of the a3987. simply inputting one pulse on the step input drives the motor to take one microstep. there are no phase sequence tables, high frequency control lines, or complex interfaces to program. the a3987 interface is an ideal fit for applications where a complex microprocessor is unavailable or over-burdened. the a3987 chopping control automatically selects the current decay mode (slow or mixed). when a step signal occurs, the translator determines if that step results in a higher or lower current in each of the motor phases. if the change is to a higher current, then the decay mode is set to slow decay. if the change is to a lower current, then the decay mode is set to 30.1% fast decay. this current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. 3987ds, rev. 6 features and benefits ? low r ds(on) outputs ? short-to-ground protection ? shorted load protection ? automatic current decay mode detection/selection ? mixed and slow current decay modes ? synchronous rectification for low power dissipation ? internal uvlo and thermal shutdown circuitry ? crossover-current protection dmos microstepping driver with translator continued on the next page? package: 24 pin tssop with exposed thermal pad (suffix lp) typical application diagram approximate scale microcontroller or controller logic rosc vdd vreg cp1 cp2 vcp vbb1 vbb2 out1a out1b sense1 sense2 out2a out2b a3987 0.22 f 0.1 f x7r 100 f 0.1 f x7r 10 f 5 k step dir enable ms1 ms2 ref sleep/reset a3987
dmos microstepping driver with translator a3987 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com internal synchronous rectification control circuitry is provided to improve power dissipation during pwm operation. internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (uvlo), and crossover current protection. special power-up sequencing is not required. the a3987 is supplied in a thin profile (1.2 mm maximum height) 24-lead tssop (suffix lp) with exposed thermal tab. the package is lead (pb) free with 100% matte tin leadframe plating. description (continued) selection guide part number package packing A3987SLP-T 24-pin tssop with exposed thermal pad 62 pieces / tube a3987slptr-t 24-pin tssop with exposed thermal pad 4000 pieces / reel absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 50 v output current i out output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction tem- perature of 150c. 1.5 a logic supply voltage v dd 7.0 v logic input voltage range v in ?0.3 to v dd + 0.3 v vbbx to outx 50 v sense voltage v sense 0.5 v reference voltage v ref 0 to 4 v nominal operating temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc thermal characteristics* characteristic symbol notes rating units package thermal resistance r ja 4-layer pcb based on jedec standard 28 c/w 2-layer pcb with 3.8 in. 2 2 oz. copper each side 32 c/w *additional thermal data available on the allegro website. 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (w) 0.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 maximum power dissipation, p d (max) (r ja = 32 oc/w) (r ja = 28 oc/w)
dmos microstepping driver with translator a3987 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com sense1 sense2 vreg vcp cp2 vd d dac dac pwm latch blanking mixed decay pwm latch blanking mixed decay cp1 charge pump vbb1 out1a out1b vbb2 out2a out2b gate drive ocp v cp v reg dmos full bridge 2 dmos full bridge 1 0.1 f 0.22 f ms2 ms1 sleep/reset enable ref 0.1 f dir rosc to v dd step control logic translator regulator buffer osc to v dd gnd gnd functional block diagram
dmos microstepping driver with translator a3987 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics 1 valid at t a = 25c, v bb = 50 v, unless noted otherwise characteristics symbol test conditions min. typ. 2 max. units output drivers load supply voltage range v bb operating 8 ? 50 v during sleep mode 0 ? 50 v logic supply voltage range v dd operating 3.0 ? 5.5 v output on resistance r ds(on) source driver, i out = ?1.5 a ? 0.54 0.6 sink driver, i out = 1.5 a ? 0.54 0.6 body diode forward voltage v f source diode, i f = ?1.5 a ? ? 1.2 v sink diode, i f = 1.5 a ? ? 1.2 v motor supply current i bb f pwm < 50 khz ? ? 4 ma operating, outputs disabled ? ? 2 ma sleep (idle) mode ? ? 20 a logic supply current i dd f pwm < 50 khz ? ? 12 ma outputs off ? ? 10 ma sleep mode ? ? 100 a control logic logic input voltage v in(1) v dd 0.7 ? ? v v in(0) ??v dd 0.3 v logic input current i in(1) v in = v dd 0.7 ?20 <1.0 20 a i in(0) v in = v dd 0.3 ?20 <1.0 20 a input hysteresis 150 ? 600 mv blank time t blank f osc = 4 mhz 0.7 1 1.3 s fixed off-time t off rosc tied to ground 15 25 35 s r osc = 59 k 23 30 37 s reference input voltage range 0.8 ? 4 v reference input current i ref ?3 0 3 a gm error 3 err v ref = 4 v, dac = 37.5% ? ? 15 % v ref = 4 v, dac = 70.31% ? ? 10 % v ref = 4 v, dac = 100% ? ? 5 % crossover dead time t dt 300 650 900 ns reset pulse width t rp 0.2 ? 1 s sleep pulse width t s >2.5 ? ? s uvlo enable threshold v uvlo v dd rising 2.35 2.7 3 v uvlo hysteresis v uvhys 0.05 0.10 ? v continued on the next page?
dmos microstepping driver with translator a3987 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 1. logic interface timing diagram step t a t d t c ms1, ms2, reset/sleep, or dir t b time duration symbol typ. unit step minimum, high pulse width t a 1 s step minimum, low pulse width t b 1 s setup time, input change to step t c 200 ns hold time, input change to step t d 200 ns electrical characteristics 1 (continued) valid at t a = 25c, v bb = 50 v, unless noted otherwise characteristics symbol test conditions min. typ. 2 max. units protection circuitry overcurrent protection threshold 4 i ocpst 2??a overcurrent blanking t ocp 13 s thermal shutdown temperature t tsd ? 165 ? c thermal shutdown hysteresis t tsdhys ?15?c 1 negative current is defined as coming out of (sourcing) the specified device pin. 2 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for indi- vidual units, within the specified maximum and minimum limits. 3 v err = [(v ref / 8) ? v sense ] / (v ref / 8). 4 ocp is tested at t a = 25c in a restricted range and guaranteed by characterization.
dmos microstepping driver with translator a3987 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com table 2. step sequencing settings home microstep position at step angle 45o; dir = h full step (#) half step (#) 1/4 step (#) 1/16 step (#) phase 1 current (% of i trip (max)) phase 2 current (% of i trip (max)) step angle () full step (#) half step (#) 1/4 step (#) 1/16 step (#) phase 1 current (% of i trip (max)) phase 2 current (% of i trip (max)) step angle () 1 1 1 0.00 100.00 0.0 5 9 33 0.00 ?100.00 180.0 2 9.38 100.00 5.6 34 ?9.38 ?100.00 185.6 3 18.75 98.44 11.3 35 ?18.75 ?98.44 191.3 4 29.69 95.31 16.9 36 ?29.69 ?95.31 196.9 2 5 37.50 92.19 22.5 10 37 ?37.50 ?92.19 202.5 6 46.88 87.50 28.1 38 ?46.88 ?87.50 208.1 7 56.25 82.81 33.8 39 ?56.25 ?82.81 213.8 8 64.06 76.56 39.4 40 ?64.06 ?76.56 219.4 1 2 3 9 70.31 70.31 45.0 3 6 11 41 ?70.31 ?70.31 225.0 10 76.56 64.06 50.6 42 ?76.56 ?64.06 230.6 11 82.81 56.25 56.3 43 ?82.81 ?56.25 236.3 12 87.50 46.88 61.9 44 ?87.50 ?46.88 241.9 4 13 92.19 37.50 67.5 12 45 ?92.19 ?37.50 247.5 14 95.31 29.69 73.1 46 ?95.31 ?29.69 253.1 15 98.44 18.75 78.8 47 ?98.44 ?18.75 258.8 16 100.00 9.38 84.4 48 ?100.00 ?9.38 264.4 3 5 17 100.00 0.00 90.0 7 13 49 ?100.00 0.00 270.0 18 100.00 ?9.38 95.6 50 ?100.00 9.38 275.6 19 98.44 ?18.75 101.3 51 ?98.44 18.75 281.3 20 95.31 ?29.69 106.9 52 ?95.31 29.69 286.9 6 21 92.19 ?37.50 112.5 14 53 ?92.19 37.50 292.5 22 87.50 ?46.88 118.1 54 ?87.50 46.88 298.1 23 82.81 ?56.25 123.8 55 ?82.81 56.25 303.8 24 76.56 ?64.06 129.4 56 ?76.56 64.06 309.4 2 4 7 25 70.31 ?70.31 135.0 4 8 15 57 ?70.31 70.31 315.0 26 64.06 ?76.56 140.6 58 ?64.06 76.56 320.6 27 56.25 ?82.81 146.3 59 ?56.25 82.81 326.3 28 46.88 ?87.50 151.9 60 ?46.88 87.50 331.9 8 29 37.50 ?92.19 157.5 16 61 ?37.50 92.19 337.5 30 29.69 ?95.31 163.1 62 ?29.69 95.31 343.1 31 18.75 ?98.44 168.8 63 ?18.75 98.44 348.8 32 9.38 ?100.00 174.4 64 ?9.38 100.00 354.4 5 9 33 0.00 ?100.00 180.0 1 1 1 0.00 100.00 360.0 table 1. microstep resolution truth table ms1 ms2 microstep resolution excitation mode l l full step 2 phase h l half step 1-2 phase l h quarter step w1-2 phase h h sixteenth step 4w1-2 phase
dmos microstepping driver with translator a3987 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 4. decay modes for quarter-step increments figure 3. decay modes for half-step increments figure 2. decay mode for full-step increments slow slow phase 2 i out2a dir = h (%) phase 1 i out1a dir = h (%) step home microstep position home microstep position 100 70 ?70 0 ?100 100 70 ?70 0 ?100 home microstep position home microstep position 100 70 ?70 0 ?100 100 70 ?70 0 ?100 phase 2 i out2b dir = h (%) phase 1 i out1a dir = h (%) step slow mixed slow mixed slow mixed mixed slow mixed slow mixed slow slow 0 100 94 70 38 ?38 ?70 ?93 ?100 0 100 93 70 38 ?38 ?70 ?93 ?100 phase 2 i out2b dir = h (%) phase 1 i out1a dir = h (%) home microstep position slow mixed slow slow mixed slow mixed slow mixed mixed step slow
dmos microstepping driver with translator a3987 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 5. decay modes for sixteenth-step increments mixed slow mixed slow mixed slow slow slow 100 95 98 92 88 83 ?83 77 70 64 56 47 38 29 19 9 0 ?100 ?95 ?92 ?98 ?88 ?77 ?70 ?64 ?56 ?47 ?38 ?29 ?19 ?9 100 95 98 92 88 83 ?83 77 70 64 56 47 38 29 19 9 0 ?100 ?95 ?92 ?98 ?88 ?77 ?70 ?64 ?56 ?47 ?38 ?29 ?19 ?9 phase 2 i out2b dir = h (%) phase 1 i out1a dir = h (%) home microstep position mixed step
dmos microstepping driver with translator a3987 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional description device operation the a3987 is a complete microstepping motor driver with built-in translator for easy operation with a minimum of control lines. the a3987 is designed to oper- ate bipolar stepper motors in full, half, quarter, and sixteenth step modes. the full bridges on the dual outputs are composed entirely of n-channel dmos fets, and the full bridge currents are regulated by fixed off-time, pulse width modulated (pwm) control circuitry. for each full bridge, the individual step currents are set by the combination of: a common external reference volt- age, v ref ; an external current sense resistor, r sense x ; and the output voltage of an internal dac that is controlled by the output of the translator. at power-up or reset, the translator sets the dacs and phase current polarity to the initial home state (see figures 2 through 5 for home state conditions), and also sets the current regulator for both output phases to mixed decay mode. when a command signal occurs on the step input, the translator automatically sequences the dacs to the next level (see table 2 for the current level sequence) and current polarity. the microstep resolution is set by inputs ms1 and ms2 (see in table 1 for state settings). if logic inputs are pulled up to vdd, it is good practice to use a high value pull-up resistor in order to limit current to the logic inputs should an overvoltage event occur. if the new dac output level is lower than the previous level, then the decay mode for that full bridge will be set to mixed decay. if the new dac level is higher or equal to the previous level, then the decay mode for that full bridge will be slow decay. this automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform due to the motor bemf. low-power mode select (sleep/reset) an active- low control input used to minimize power consumption when the a3987 is not in use. this disables much of the internal circuitry including the output fets and internal regulator. a logic high allows normal device operation and power-up in the home state. when coming out of sleep mode, a 1 ms delay is required before issuing a step command, to allow the internal regulator to stabilize. the outputs can also be reset to the home state without entering sleep mode. to do so, pulse this input low for a duration between t rp (min) and t rp (max). step input (step) a low-to-high transition on the step input sequences the translator and advances the motor one incre- ment. the translator controls the input to the dacs and the direc- tion of current flow in each winding. the size of the increment is determined by the state of inputs ms1 and ms2. microstep select (ms1 and ms2) inputs ms1 and ms2 select the microstepping format (see table 1 for state settings). changes to these inputs do not take effect until the next step command. it is good practice to use a pull-up resistor to vdd in order to limit input current should an external overvoltage occur. a minimum of 5 k is recommended. direction input (dir) the state of the dir input determines the direction of rotation of the motor. a logic change on the dir pin will not take effect until the next step command is issued. internal pwm current control each full bridge is controlled by a fixed off-time pwm current control circuit that limits the load current to a desired value (i trip ). initially, a diagonal pair of source and sink fets are enabled and current flows through the motor winding and the corresponding current sense resistor, r sense x . when the voltage across r sense equals the dac output voltage, the current sense comparator resets the pwm latch, which turns off the source drivers (in slow decay mode) or the sink and source drivers (in fast or mixed decay modes). the maximum value of current limiting is set by the selection of r sense and the voltage at the ref input, with a transconductance function approximated by: i trip (max) = v ref / (8 r sense ) . the dac output reduces the v ref output to the current sense comparator in precise steps: i trip = (% i trip (max) / 100) i trip (max) , (see table 2 for % i trip (max) at each step). note: it is critical that the absolute maximum voltage rating (0.5 v) on the sense pins is not exceeded. fixed off-time the internal pwm current control circuitry uses a 4 mhz master oscillator to control the duration of time that the drivers remain off. the fixed off-time, t off , is determined by the selection of an external resistor connected from the rosc timing terminal to vdd. if the rosc terminal is tied directly to gnd, t off defaults to 25 s. the off-time is approximated by: t off r osc / (1.981 10 9 ) blanking this function blanks the output of the current sense comparator when the outputs are switched by the internal current control circuitry. the comparator output is blanked to prevent false overcurrent detections due to reverse recovery currents of
dmos microstepping driver with translator a3987 10 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com the internal body diodes, and switching transients related to the capacitance of the load. the blank time, t blank , is internally set to approximately 1 s. charge pump (cp1 and cp2) the charge pump is used to generate a gate supply greater than v bb x to drive the source fet gates. a 0.1 f ceramic capacitor is required between cp1 and cp2 for pumping purposes. a 0.1 f ceramic capacitor is required between vcp and the vbb terminals to act as a reservoir to oper- ate the high-side fets. internal regulator (vreg) the vreg terminal should be decoupled with a 0.22 f capacitor to ground. this internally generated voltage is used to operate the sink fet outputs. vreg is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. enable input (enable) this input activates all of the fet outputs. when logic high, the outputs are disabled, and when logic low, the outputs are enabled. inputs to the translator (step, dir, ms1, and ms2) are always active, except in sleep mode, regardless of the enable input state. shutdown in the event of a fault (either excessive junction temperature, or low voltage on vcp), the outputs of the device are disabled until the fault condition is removed. at power-up, the undervoltage lockout (uvlo) circuit disables the drivers and resets the translator to the home state. mixed decay operation the full bridges can operate in mixed decay mode when set by the step sequence (see figures 3 through 5). as the trip point is reached, the device goes into fast decay mode for 30.1% of the fixed off-time, t off . after this fast decay portion, t fd , the device switches to slow decay mode for the remainder of the fixed off-time period. synchronous rectification when a pwm off-cycle is triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. the a3987 synchronous rectification feature turns on the appropriate fets during current decay, effectively shorting out the body diodes in the low r ds(on) driver. this lowers power dissipation significantly, and can eliminate the need for external schottky diodes for many applications. to prevent reversal of load current, synchronous rectification is turned off when a zero current level is detected. short-to-ground should a motor winding short to ground, the current through the short will rise until the overcurrent thresh- old, i copst , a minimum of 2 a, is exceeded. the driver turns off after a short propagation delay and latches the fault. the device will remain disabled until the sleep/reset input goes high or vdd power is removed. as shown in figure 6, a short-to-ground produces a single overcurrent event. shorted load during a shorted load event, the current path is through the sense resistor. during this fault condition the device will be protected, however, the fault will not be latched. when the full bridge turns on, the current will rise and exceed the over- current threshold. after the blank time,t blank , of approximatly 1 s, the driver will look at the voltage on the sense x pin. the voltage on the sense x pin will be larger than the voltage set by the ref pin, and the full bridge will turn off for the time set by the rosc pin. figure 7 shows a shorted load condition with an off-time of 30 s. figure 6. short-to-ground event figure 7. short-to-load event t off = 30 s 2 a / div. 5 s / div. 2 a / div. 500 ns / div. fault latched
dmos microstepping driver with translator a3987 11 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com u1 rs1 cref cvdd rs2 rosc creg cvcp cin2 ccp vin out2b out2a vref gnd cin1 out1a out1b v in rosc cin2 cref cvdd creg cin1 ccp cvcp rs1 pad out1a out1b out2a out2b 1 rs2 a3987 sense1 out1a nc ms1 dir step gnd ref enable vdd out2a sense2 vbb1 ms2 out1b cp2 cp1 vcp gnd rosc sleep/reset vreg out2b vbb2 vref layout . the printed circuit board should use a heavy ground- plane. for optimum electrical and thermal performance, the a3987 must be soldered directly onto the board. on the under- side of the a3987 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad should be soldered directly to an exposed surface on the pcb. thermal vias are used to transfer heat to other layers of the pcb. in order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground , located very close to the device. by making the connection between the pad and the ground plane directly under the a3987, that area becomes an ideal location for a star ground point. a low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. the recom- mended pcb layout, shown in figure 8, illustrates how to create a star ground under the device, to serve both as a low impedance ground point and thermal path. the two input capacitors should be placed in parallel, and as close to the device supply pins as possible. the ceramic capaci- tor (cin1) should be closer to the pins than the bulk capacitor (cin2). this is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. the sense resistors, rsx , should have a very low impedance path to ground, because they must carry a large current while sup- porting very accurate voltage measurements by the current sense comparators. long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accu- rately measure the current in the windings. as shown in figure 8, the sensex pins have very short traces to the rsx resistors and very thick, low impedance traces directly to the star ground underneath the device. if possible, there should be no other com- ponents on the sense circuits. pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz. ) a3987 solder figure 8. printed circuit board layout with typical application circuit, shown at right. the copper area directly under the a3987 (u1) is soldered to the exposed thermal pad on the underside of the device. the thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the pcb , so the two copper areas together form the star ground.
dmos microstepping driver with translator a3987 12 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com terminal list table number name pin description 1 sense1 sense resistor terminal for full bridge 1 2 out1a dmos full bridge 1, output a 3 nc no connection 4 ms1 logic input 5 dir logic input 6 step logic input 7, 18 gnd ground terminals 8 ref g m reference input 9 enable logic input 10 vdd logic supply 11 out2a dmos full bridge 2, output a 12 sense2 sense resistor terminal for full bridge 2 13 vbb2 load supply 14 out2b dmos full bridge 2, output b 15 vreg internal regulator 16 sleep/reset logic input 17 rosc oscillator input 19 vcp reservoir capacitor terminal 20 cp1 charge pump capacitor terminal 21 cp2 charge pump capacitor terminal 22 out1b dmos full bridge 1, output b 23 ms2 logic input 24 vbb1 load supply ? pad exposed thermal pad for enhanced thermal dissipation. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vbb1 ms2 out1b cp2 cp1 vcp gnd rosc sleep/reset vreg out2b vbb2 sense1 out1a nc ms1 dir step gnd ref enable vdd out2a sense2 pad device pin-out diagrams
dmos microstepping driver with translator a3987 13 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com p a c k a g e l p , 2 4 p i n t s s o p w i t h e x p o s e d t h e r m a l p a d package lp, 24 pin tssop with exposed thermal pad 1.20 max c seating plane 0.15 max c 0.10 24x 0.65 6.10 3.00 4.32 1.65 0.45 0.65 0.25 2 1 24 3.00 4.32 (1.00) gauge plane seating plane b a a terminal #1 mark area b for reference only (reference jedec mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c 7.80 0.10 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06 for the latest version of this document, visit our website: www.allegromicro.com copyright ?2006-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

▲Up To Search▲

Price & Availability of A3987SLP-T

	To Download A3987SLP-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .