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1/20 october 2004 VN750SM-E high side driver rev. 1 table 1. general features cmos compatible input on state open load detection off state open load detection shorted load protection undervoltage and overvoltage shutdown protection against loss of ground very low stand-by current reverse battery protection (*) in compliance with the 2002/95/ec european directive description the VN750SM-E is a monolithic device designed in stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protect the device against overload. the device detects open load condition both in on and off state. the openload threshold is aimed at detecting the 5w/12v standard bulb as an openload fault in the on state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (*) see application schematic at page 9. type r ds(on) i out v cc VN750SM-E 55 m ? 6 a 36 v so-8 package tube tape and reel so-8 VN750SM-E vn750smtr-e
VN750SM-E 2/20 figure 2. block diagram table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k ?; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l=1.3mh; r l =0 ? ; v bat =13.5v; t jstart =150oc; i l =10a) 90 mj p tot power dissipation t c =25c 4.2 w t j junction operating temperature internally limited c t stg storage temperature - 55 to 150 c undervoltage overtemperature v cc gnd input output overvoltage current limiter logic driver power clamp status v cc clamp on state openload off state openload and output shorted to v cc detection detection detection detection detection
3/20 VN750SM-E figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins figure 4. current and voltage conventions table 4. thermal data ( 1 ) when mounted on a standard single-sided fr-4 board with 0.5 cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. ( 2 ) when mounted on a standard single-sided fr-4 board with 2 cm 2 of cu (at least 35 m thick) connected to all v cc pins. horizontal mount- ing and no artificial air flow. symbol parameter value unit r thj-lead thermal resistance junction-lead max 30 c/w r thj-amb thermal resistance junction-ambient max 93 ( 1 ) 82( 2 )c/w connection / pin status n.c. output input floating x x x x to ground x through 10k ? resistor v cc v cc output output n.c. gnd status input 1 4 5 8 input i s i in v in v cc status i stat v stat gnd v cc i out v out i gnd output v f
VN750SM-E 4/20 electrical characteristics (8v8v i out =2a; v cc >8v 55 110 m ? m ? i s supply current off state; v cc =13v; v in =v out =0v off state; v cc =13v; v in =v out =0v; t j =25 c on state; v cc =13v; v in =5v; i out =0a 10 10 2 25 20 3.5 a a ma i l(off1) off state output current v in =v out =0v 0 50 a i l(off2) off state output current v in =0v; v out =3.5v -75 0 a i l(off3) off state output current v in =v out =0v; v cc =13v; t j =125c 5 a i l(off4) off state output current v in =v out =0v; v cc =13v; t j =25c 3 a symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l =6.5 ? from v in rising edge to v out =1.3v 40 s t d(off) turn-off delay time r l =6.5 ? from v in falling edge to v out =11.7v 30 s dv out / dt (on) turn-on voltage slope r l =6.5 ? from v out =1.3v to v out =10.4v see relative diagram v/ s dv out / dt (off) turn-off voltage slope r l =6.5 ? from v out =11.7v to v out =1.3v see relative diagram v/ s symbol parameter test conditions min. typ. max. unit v il input low level 1.25 v i il low level input current v in =1.25v 1 a v ih input high level 3.25 v i ih high level input current v in =3.25v 10 a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in =1ma i in =-1ma 66.8 -0.7 8v v
5/20 VN750SM-E electrical characteristics (continued) table 8. v cc - output diode table 9. status pin table 10. protections (see note 1) note: 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. table 11. openload detection symbol parameter test conditions min. typ. max. unit v f forward on voltage -i out =1.4a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6ma 0.5 v i lstat status leakage current normal operation; v stat =5v 10 a c stat status pin input capacitance normal operation; v stat =5v 100 pf v scl status clamp voltage i stat =1ma i stat =-1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload condition t j >t tsd 20 s i lim current limitation 5.5v VN750SM-E 6/20 figure 5. table 12. truth table figure 6. switching time waveforms conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l v in v stat t dol(off) open load status timing (with external pull-up) overtemp status timing i out < i ol v out > v ol t dol(on) t j > t jsh v in v stat t sdl t sdl t t v outn v inn 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on)
7/20 VN750SM-E table 13. electrical transient requirements on v cc pin iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 ? 2 +25 v +50 v +75 v +100 v 0.2 ms 10 ? 3a -25 v -50 v -100 v -150 v 0.1 s 50 ? 3b +25 v +50 v +75 v +100 v 0.1 s 50 ? 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 ? 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 ? iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5ceee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
VN750SM-E 8/20 figure 7. waveforms open load without external pull-up status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc >v ov status input status status input status input open load with external pull-up undefined load voltage v cc v ol
9/20 VN750SM-E figure 8. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k ?) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 20ma; v oh c 4.5v 5k ? r prot 65k ? . recommended r prot value is 10k ?. v cc gnd output d gnd r gnd d ld c +5v r prot v gnd status input +5v r prot
VN750SM-E 10/20 open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l 11/20 VN750SM-E figure 10. off state output current figure 11. high level input current figure 12. input clamp voltage figure 13. status low output voltage figure 14. status leakage current figure 15. status clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc (oc) -1 -0.5 0 0.5 1 1.5 2 2.5 3 il(off1) (ua) off state vcc=36v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 1 2 3 4 5 6 7 iih (ua) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 0.1 0.2 0.3 0.4 0.5 0.6 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.01 0.02 0.03 0.04 0.05 ilstat (ua) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc (c) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma
VN750SM-E 12/20 figure 16. on state resistance vs t case figure 17. on state resistance vs v cc figure 18. openload on state detection threshold figure 19. input high level figure 20. openload off state voltage detection threshold figure 21. input low level -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 20 40 60 80 100 120 140 ron (mohm) iout=2a vcc=8v; 13v; 36v 5 10152025303540 vcc (v) 20 30 40 50 60 70 80 90 100 110 120 ron (mohm) iout=2a tc= - 40c tc= 25c tc= 125c tc= 150c -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 iol (a) vcc=13v vin=5v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 vil (v)
13/20 VN750SM-E figure 22. turn-on voltage slope figure 23. overvoltage shutdown figure 24. input hysteresis voltage figure 25. turn-off voltage slope figure 26. i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 100 200 300 400 500 600 700 800 900 1000 dvout/dt/(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 50 100 150 200 250 300 350 400 450 500 dvout/dt(off) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 2 4 6 8 10 12 14 16 18 20 ilim (a) vcc=13v
VN750SM-E 14/20 figure 27. so-8 maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 ? in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. 1 10 100 0.1 1 10 100 l(mh) i lmax (a) a b c v in , i l t demagnetization demagnetization demagnetization
15/20 VN750SM-E so-8 thermal data figure 28. so-8 pc board figure 29. r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m, copper areas: 0.14cm 2 , 2cm 2 ). 70 75 80 85 90 95 100 105 110 00.511.522.5 pcb cu heatsink area (cm^2) rthj_amb (oc/w) so8 at 2 pins connected to tab
VN750SM-E 16/20 figure 30. so-8 thermal impedance junction ambient single pulse figure 31. thermal fitting model of a single channel hsd in so-8 pulse calculation formula table 14. thermal parameter 0.01 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.5 cm 2 2 cm 2 t_amb c1 r1 r2 c2 r3 c3 r4 c4 r5 c5 r6 c6 pd tj area/island (cm 2 )0.52 r1 (c/w) 0.05 r2 (c/w) 0.8 r3 ( c/w) 3.5 r4 (c/w) 21 r5 (c/w) 16 r6 (c/w) 58 28 c1 (w.s/c) 0.006 c2 (w.s/c) 2.60e-03 c3 (w.s/c) 0.0075 c4 (w.s/c) 0.045 c5 (w.s/c) 0.35 c6 (w.s/c) 1.05 2 z th r th z thtp 1 ? () + ? = where t p t ? =
17/20 VN750SM-E package mechanical table 15. so-8 mechanical data figure 32. so-8 package dimensions symbol millimeters min typ max a 1.75 a1 0.1 0.25 a2 1.65 a3 0.65 0.85 b 0.35 0.48 b1 0.19 0.25 c 0.25 0.5 c1 45 (typ.) d4.8 5 e5.8 6.2 e1.27 e3 3.81 f3.8 4 l 0.4 1.27 m 0.6 s 8 (max.) l1 0.8 1.2
VN750SM-E 18/20 figure 33. so-8 tube shipment (no suffix) figure 34. so-8 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 c b a tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions all dimensions are in mm. base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4
19/20 VN750SM-E revision history table 16. revision history date revision description of changes oct. 2004 1 - first issue.
VN750SM-E 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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