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silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 1 pll for dts description the sc9256 is phase-locked loop (pll) lsis for digital tuning systems (dts) with built in 2 modulus prescalers. a ll functions ate controlled through 3 serial bus lines. these lsis are used to configure high-performance digital tuning system. features * optimal for configuring digital tuning systems in high-fi tuners and car stereos. * built-in prescalers. operate at input frequency ranging from 30~150 mhz during fm in input (with 2 modulus prescaler) and at 0.5~40mhz during am in input (with 2 modulus prescaler or direct dividing). * 16 bit programmable counter, dual parallel output phase comparator, crystal oscillator and reference counter. * 3.6mhz, 4.5mhz, 7.2mhz or 10.8mhz crystal oscillators can be used. * 15 possible reference frequencies. ( when using 4.5mhz crystal) * built-in 20 bit general-purpose counter for such uses as measuring intermediate frequencies (if in1 and if in2 ) * high-precision ( 0.55~ 7.15 s) pll phase error detection. * numerous general-purpose i/o pins for such uses as peripheral circuit control. * 3 n-channel open-drain output ports (off withstanding voltage:12v) for such uses as control signal output. dip-16-300-2.54 sop-16-300-1.27 * standby mode function (turns off fm, am and if amps) to save current consumption. * all functions controlled through 3 serial bus lines. * cmos structure with operating power supply range of v dd =5.0 0.5v. ordering information device package sc9256 dip-16-300-2.54 SC9256S sop-16-300-1.27 pin configuration 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sc9256 xt xt period clock data ot-1 ot-2 ot-3 do2/ot-4 do1 i/o-5/if in1 gnd i/o-6/if in2 fm in am in v dd
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 2 block diagram 1/2 2 modulus perscaler 4bit swallow counter 12bit programmable counter osc circuit reference counter max 24bit shift register 24bit register address decoder 24bit register output port 20bit binary counter universal counter control power on reset reset phase comparator tri-state buffer tri-state buffer unlock ot4 i/o port xt 1ms amp amp amp fm l psc v dd gnd hf fm h 4 12 fm lf mode 15 4 1ms osc 8 test 24 22 5 5 10 4 4 do1 do2/ot-4 i/o-6/if in2 i/o-5/if in1 ot-1 ot-2 ot-3 fm in am in xt xt data clock period gate absolute maximum ratings (ta=25 c) characteristic symbol value unit supply voltage v cc -0.3~6.0 v input voltage v in -0.3~v dd +0.3 v n-ch open-drain off withstanding voltage v off 13 v power dissipation p d 300(200) mw operating temperature t opr -40~85 c storage temperature t stg -65~150 c ( ): flat package
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 3 electrical characteristics (unless otherwise specified, ta= -40~85 c, v dd =4.5~5.58v.) characteristic symbol test condition/pin min typ. max unit operating power supply voltage v dd1 pll operation (normal operating) 4.5 5.0 5.5 v operating power supply current i dd1 v dd =5.0v, xt=10.8mhz, fmin=150mhz -- 7 15 ma stand-by mode crystal oscillation frequency supply voltage v dd2 pll off (operating crystal oscillation) 4.0 5.0 5.5 v operating power supply current i dd2 v dd =5.0v, xt =10.8mhz pll off -- 0.8 1.5 ma operating power supply current i dd3 v dd =5.0v, xt stop, pll off -- 120 240 a operating frequency range crystal oscillation frequency f xt connect crystal resonator to xt- xt terminal 3.6 ~ 10.8 mhz fm in (fm h ,fm l )f fm fm h, fm l mode, v in =0.2vp-p 30 ~ 130 mhz fm in (fm l )f fml fm l mode, v in =0.3vp-p 30 ~ 150 mhz am in (hf) f hf hf mode, v in =0.2vp-p 1 ~ 40 mhz am in (lf) f lf lf mode, v in =0.2vp-p 0.5 ~ 20 mhz if in1 ,if in2 f if v in =0.2vp-p 0.1 ~ 15 mhz sc in f sc v ih =0.7v dd ,v il =0.3v dd , square wave input. -- ~ 100 khz operating input amplitude range fm in (fm h ,fm l ) v fm fm h, fm l mode, f in =30~130mhz 0.2 ~ v dd -0.5 vp-p fm in (fm l )v fml fm l mode, f in =30~150mhz 0.3 ~ v dd -0.5 vp-p am in (hf) v hf hf mode, f in =1~40mhz 0.2 ~ v dd -0.5 vp-p am in (lf) v lf lf mode, f in =0.5~20mhz 0.2 ~ v dd -0.5 vp-p if in1 ,if in2 v if f in =0.1~15mhz 0.2 ~ v dd -0.5 vp-p ot1~ot4 n-ch open drain output current ?l? level i ol1 v ol =1.0v 5.0 10.0 -- ma off-leak current i oef v off =12v -- --- 2.0 a (to be continued)
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 4 (continued) characteristic symbol test condition/pin min typ. max unit i/o-5~i/o-9, sc in ?h? level v ih1 0.7v dd ~v dd input voltage ?l? level v il1 0 ~ 0.3v dd v ?h? level i ih v ih =5v -- -- 2.0 input current ?l? level i il v il =0v -- -- -2.0 a ?h? level i oh4 v oh =4.0v (expect sc in ) -2.0 -4.0 -- output current ?l? level i ol4 v ol =1.0v (expect sc in )2.04.0-- ma period, clock, data ?h? level v ih2 0.8v dd ~v dd input voltage ?l? level v il2 0 ~ 0.2v dd v ?h? level i ih v ih =5v -- -- 2.0 input current ?l? level i il v il =0v -- -- -2.0 a ?h? level i oh5 v oh =4.0v (data) -1.0 -3.0 -- output current ?l? level i ol5 v ol =1.0v (data) 1.0 3.0 -- ma do1, do2 ?h? level i oh3 v oh =4.0v -2.0 -4.0 -- input current ?l? level i ol3 v ol =1.0v 2.0 4.0 -- ma tri-state lead current i tl v tlh =5v, v tll =0v -- -- 1.0 a xt ?h? level i oh2 v oh =4.0v -0.1 -0.3 -- output current ?l? level i ol2 v ol =1.0v 0.1 0.3 -- ma input feedback resistance ?h? level rf1 fmin, amin, ifin (ta=25 c) 350 700 1400 input feedback resistance ?l? level rf2 xt- xt (ta=25 c) 500 1000 4000 k ? pin description pin no. symbol pin name description circuit diagram 1xt 2 xt crystal oscillator pins connects 3.6mhz, 4.5mhz, 7.2mhz or 10.8mhz crystal oscillator to supply reference frequency and internal clock xt xt v dd (to be continued)
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 5 (continued) pin no. symbol pin name description circuit diagram 3 period period signal input 4 clock clock signal input 5data serial data input/output serial i/o ports. these pins transfer data to and from the controller to set divisions and dividing modes, and to control the general-purpose counter and general-purpose i/o ports. schmitt input data v dd schmitt input clock,period 6ot-1 7ot-2 8ot-3 general-purpose output ports n channel open drain port pins, for such uses as control signal output. these pins are set to the off state when power is turned on. n-channel open drain 10 amin 11 fmin programmable counter input these pins input fm and am band local oscillator signals by capacitor coupling. fm in and am in operate at low amplitude. v dd 13 i/o- 6/ifin2 14 i/o-5 /ifin1 general-purpose i/o ports/general- purpose counter frequency measurement input general-purpose i/o port input /output pins. can be switched for use as input pins to measure general purpose counter frequencies. the frequency measurement function has such uses as measuring inter- mediate frequencies (if). these pins feature built-in amps. data are input by capacitor coupling. fm in and am in operate at low amplitude. (note) pins are set for input when power is turned on. v dd 15 do1 16 do2/ot-4 phase comparator output (general- purpose output ports) these pins are for phase comparator tri-state output. do1 and do2 are output in parallel. v dd 12 gnd 9v dd power supply pins applies 5.0v 10%
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 6 function description serial i/o ports as the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2 sets of 24 bit registers. each bit of data in these register is transferred through the serial ports between the controller and the data, clock and period pins. each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits. since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address and functions of each register. these registers consist of 24 bits and are selected by an 8 bit address. a list of the address assignment for each register is given below under register assignments. register address contents of 24 bits no. of bit input register 1 d0h pll divisor setting reference frequency setting pll input and mode setting crystal oscillator selection 16 4 2 2 total 24 input register 2 d2h general=purpose counter control (including lock detection bit control) i/o port and general-purpose counter switching bits i/o-5/clk pin switching bit do pin control test bit i/o port control (also used as general-purpose counter input selection bits) output data 4 3 1 1 1 5 9 total 24 output register 1 d1h general-purpose counter numeric data not used 22 2 total 24 output register 2 d3h lock detection data i/o port control data output data input data (undefined during output port selection) not used 5 5 4 5 5 total 24 when the period signal falls, the input data are latched in register 1 or register 2 and the function is performed. when the clock signal falls for 9 time, the output data are latched in parallel in the output registers. the data are subsequently output serially from the data pin.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 7 register assigments p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 r0 r1 r2 r3 mode fm osc1 osc2 programmable counter data reference frequency code data programmable counter mode crystal oscillator selection bits g0 g1 -- if1 if2 o4c dohz reset start xt -- -- m5 m6 o1 o2 o3 o4 -- -- o5 -- o6 test address=d0h lsb lsb address=d2h (*2) gate time select i/o port and general-purpose counter switching bits clk bit dohz bit reset bit start bit test bit also used as general-purpose counter input selection bits i/o port control output port output data input registers f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 busy over "0" "0" general-purpose counter data ena- ble un lock pe1 pe2 pe3 "0" "0" "0" "0" 0 0 0 m5 m6 o1 o2 o3 o4 0 0 i5 0i6 "0" address=d1h lsb address=d3h input registers not used lock detection data not used i/o port control data output data input data when power is turned on, the input registers are set as shown below. (*1) (*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)1111 1 100 000000000 00000000000 0 00 0 address=d0h lsb address=d2h input registers (*1) msb note: 1. data are undefined. 2. set data to ?0? for test bit.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 8 serial transfer format the serial transfer format consists of 8 address bits and 24 data bits (fig. 1). addresses d0h~d3h are used. start t3 t4 t5 t6 t7 end t1 t2 9 clock signal fall t8 (*)(*)0010 1 1 lsb msb 8addressbits 24 data bits (24bit register) period clock data msb lsb fig.1 ? serial data transfer serial data are transferred in sync with the clock signal. in the idle state, the period, clock and data pin lines are all set to ?h? level. when the period signal is at ?l? level, the falling of the clock signal initiates serial data transfer. data transfer ceases when the period signal is set to ?l? level when the clock signal is at ?h? level. once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time the period signal is at ?l? level. since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the sending side to produce output in sync with the clock signal fall. to receive serial data from the output registers (d1h, d3h), set the serial data output to high impedance after the 8 bit address is output but before the next clock signal falls. data reception subsequently continues until the period signal becomes ?l? level; data transfer ends just before the period signal rises. therefore, the data pin must have an open-drain or tristate interface. note: 1. when power is turned on, some internal circuit have undefined states. to set internal circuit states, execute a dummy data transfer before performing regular data transfer. 2. times t1~t8 have the following value: t1 1.0 s t2 1.0 s t3 0.3 s t4 0.3 s t5 0.3 s t6 1.0 s t7 1.0 s t8 0.3 s 3. asterisks represent numbers taken from addresses, as in d*h.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 9 crystal oscillator pins (xt, xt ) as fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal oscillator between capacitors. use the crystal oscillator selection bit to select an oscillating frequency of 3.6mhz, 4.5mhz, 7.2mhz or 10.8mhz which matches that of the crystal oscillator used. lsb msb address d0h osc1 osc2 osc1 osc2 oscillator frequency 00 0 1 01 11 3.6mhz 4.5mhz 7.2mhz 10.8mhz divider xt xt c c x'tal c=30pf typ. fig.2 note: set to 3.6mhz (osc1=?0? and osc2=?0?) when power is turned on. the crystal is not oscillating at this time because the system is in standby mode. reference counter (reference frequency divider) the reference counter section consists of a crystal oscillator and a counter. a crystal oscillator frequency of 3.6mhz, 7.2mhz or 10.8mhz can be selected .a maximum of 15 reference frequencies can be generated. 1. setting reference frequency the reference frequency is set using bits r0~r3. lsb msb address d0h r3 r2 r0 r1 r2 r3 0000 000 1 0100 1100 0010 1010 0110 1110 reference frequency r0 r1 r2 r3 0001 1001 0101 1101 0011 1011 0111 1111 0.5 khz 1khz 2.5 khz 3khz 3.125 khz *3.90654 khz 5khz 6.25 khz *7.8125 khz reference frequency 9khz 10 khz 12.5 khz 25 khz 50 khz 100 khz standby mode (*1) r1 r0
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 10 note: 1. reference frequencies marked with an asterisk ?*?can only be generated with a 4.5mhz crystal oscillator. 2. (*1)standby mode standby mode occurs when bits r0,r1,r2,and r3 are all set to ?1?.in standby mode, the programmable counter stops, and fm, am and if in (when selected if in ) are set to ?amp off? state (pins at ?l? level). this saves current consumption when the radio is turned off. the do pins become high impedance during standby mode. during standby mode, the i/o ports (i/o-5~i/o-6) and output ports (ot1~ot4) can be controlled and the crystal oscillator can be turned on and off. 3.the system is set to standby mode when power is turned on. at this time, the crystal oscillator is not oscillating and the i/o ports are set to input mode. programmable counter the programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a 4bit +12bit programmable binary counter. 1. setting programmable counter 16 bits of divisor data and 2 bits, which indicate the dividing mode, are set in the programmable counter. ( 1) setting dividing mode the fm and mode bits are used to select the input pin and the dividing mode (pulses wallow mode or direct dividing mode). there are 4 possible choices, shown in the table below .select one based on the frequency band used. lsb msb address d0h fm mode mode fm mode lf hf fm l fm h 0 0 1 1 0 1 0 1 dividing mode direct dividing mode pulse swallow mode 1/2 + pulse swallow mode typical receiving band lw,mw,swl swh fm fm input frequency range 0.5 ~ 20mhz 1~40mhz 30 ~ 130mhz 30 ~ 150mhz 30 ~ 130mhz input pin am in fm in frequency n 2n (2) setting divisor the divisor for the programmable counter is set as binary data in bits p0~p15. ? pulse swallow mode (16 bits) lsb msb address d0h p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 2 0 2 15 divisor setting range (pulse swallow mode):n=210h~fffh (528~65535) (note) with the 1/2+pulse swallow mode, the actual divisor is twice the programmed value.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 11 ? direct dividing mode (12 bits) lsb msb address d0h p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 2 0 2 11 p0 p1 p2 p3 don't care divisor setting range (direct dividing mode):n=10h~fffh(16~4095) with the direct dividing mode, data p0~p3 are don?t-care and bit p4 is the lsb. 2. prescaler and programmable counter circuit configuration (1) pulse swallow mode circuit configuration 1/2 2 modulus prescaler 4bit swallow counter 12bit programmable counter fm,mode preset to phase comparator psc p4-p15 p0-p3 fm l fm h prescaler section fm in am in hf fig.3 this circuit consists of a 2 modulus prescaler, a 4 bit swallow counter and a 12bit programmable counter. during fm in (fm in mode),a 1/2 prescaler is added to the preceding step. (2) direct dividing method circuit configuration am in 12bit program counter amp p4-p15 to phase comparator preset fig.4 with the direct dividing mode, the prescaler section is bypassed and the 12bit programmable counter is used. (3) both fm in and am in have built-in amps. data are input by capacitor coupling. fm in and am in operate at low amplitude. general-purpose counter the general-purpose counter is a 20bit counter. it has such uses as counting am/fm band intermediate frequencies (if) and detecting auto-stop signals during auto-search tuning. general-purpose counter pins can also be used as i/o ports. 1. general-purpose counter control bits (1) bits g0 and g1 ? used for selecting the general-purpose counter gate time.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 12 g0 g1 lsb msb address d2h g0 g1 gate time cycle measurement pulse 00 0 1 01 1 1 1ms 4ms 16ms 64ms 50 khz 150 khz 900 khz crystal oscillator frequency (2) bits sc,if1 and if2 ?i/o port and general-purpose counter switching bits. (*) the functions of the following pins are switched by data. lsb msb address d2h if1 if2 if1 1 0 i/o-5/if in1 if in1 i/o-5 if2 1 0 i/o-6/if in2 if in2 i/o-6 (3) bits m5 sets the state for pin i/o-5/if in1 ; m6, for pin i/o-6/if in2. these operations are valid when bits sc, if1 and if2 are all set to 1. lsb msb address d2h m5 m6 pin states (when bits sc, if1 and if2 are all set to "1") if in1 if in2 0 0 (*) 1 1 0 00 input pulled down input enabled input pulled down input pulled down input enabled input pulled down m6 m5 note: bits marked with an asterisk ?(*)? are don?t care (4) bits f0~f9?the general-purpose counter results can be read in binary from bits f0~f9 of the output register (d1h). lsb msb address d1h f12 f14 f13 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f15 f16 f17 f18 f19 over busy "0" "0" 2 0 2 19 general-purpose counter data (5 ) over and busy bits?detect the operating state of the general-purpose counter.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 13 address d1h msb busy over "0" "0" general-purpose counter option monitor bit general-purpose counter overflow detection bit general-purpose counter busy counted value in general- purpose counter 2 20 -1 general-purpose counter ended counting counted value in general- purpose counter 2 20 (overflow state) bit data = "1" bit data = "0" note: when using the general-purpose counter, before referring to the contents of the general-purpose counter result bit (f0~f9), confirm that the busy bit is ?0? (counting is ended) and the over bit is ?0? (general-purpose counter data are normal). (6) start bit?when the data are set to ?1?, the general-purpose counter is reset then counting begins. lsb msb address d2h start 0 1 counting continues uninterrupted. counting begins after general - purpose counter is reset. 2. general-purpose counter circuit configuration the general-purpose counter section consists of input amps, a gate time control circuit and a 20 bit binary counter. over amp if in1 if in2 20bit binary counter overflow detection gate time control circuit cycle measurement pulse gate sc in (cmos input) sc if1 if2 start g0 g1 busy f xt f0-f19 fig.5 3. general-purpose counter measurement timing
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 14 t1 start bit set to "1" end t2 period if in1 or if in2 busy bit gate binary counter input clock pulse to be measured frequency measurement timing chart 0 silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 15 (1) sc9256 lsb msb address d2h o3 o1~o4 pin output state 0 1 ot-1~ot-3 high impedance (n channel open drain output =off) "l" level (n channel open drain output =on) o4 o2 o1 ot-4 (*1) "l" level (*1) "h" level (*1) o4c o4c 0 1 do2/ot-4pin do2 (phase comparator output) ot-4 (general-purpose output port) (2)output register the data set in bits o1~o4 of the input register can read as serial data o1~o4 from the output register (d3h). lsb msb address d2h o3 o4 o2 o1 lsb msb address d3h o3 o4 o2 o1 input register output register 2. general-purpose i/o ports (i/o-5~i/o-6) pins i/o-5~ i/o-6 are general-purpose i/o ports used for control signal input and output. they are configured for cmos input and output. these i/o ports are set for input or output using bits m5~m6 of the input register (d2h). setting m5~m6 to ?0? sets these ports for input. data which are input in parallel from i/o-5~i/o-6 are latched in the internal register on the ninth fall of the serial clock signal. these data can then be read as serial data i5~i6 from the data pins. data which are set in bits o5~o6 of the input register (d2h) are output in parallel from their corresponding general-purpose i/o port pin i/o-5~i/o6. these operations are valid when bits sc, if1, if2 and clk are all set to ?0?.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 16 (1) sc9256 lsb msb address d2h if1 "0" if2 "0" m5 m6 m5, m6 pin input /output state (when if1 and if2 are "0") i/o -5, i/o -6 "l" level "h" level 0 1 ? setting data for output ports lsb msb address d2h if1 "0" if2 "0" clk "0" m5 "1" o5, o6 pin output state (when if1 and if2 are "0") i/o -5, i/o -6 "l"level "h"level 0 1 o6 o5 m6 "1" (2)output register?data which are set in bits m5~m6 of the input register (d2h) can be read as serial data m5~m6 from the output register (d3h). lsb msb address d2h lsb msb address d3h input register output register xt -- -- m5 m6 000m5m6
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 17 lsb msb address d3h input register i6 i5 0 0 0 i/o-5 i/o-6 input data input ports (i/o-5 ~ i/o-6) bit data (i5-i6) "l" level "h" level 0 1 note: 1. when pins i/o-5~i/o-6 are used for output, the data in i5~i6 of the output register(d3h) are undefined.. 2. when power is turned on, input register (d2h) i/o port control bits m5~m6 and output data bits o5~o6 are set to ?0?. general-purpose i/o ports are set as input ports. pins which are used both as general-purpose i/o ports and for general-purpose counter input are set for i/o port input. the output state of general-purpose output ports is set to high impedance (n channel open drain output =off). 3. pin i/o-5 and i/o-6 also serve as general-purpose counter input pins. therefore, bits if1 and if2 of input register 2 must be set to ?0? when these pins are used as i/o ports. phase comparator the phase comparator outputs the phase error after comparing the phase difference of the reference frequency signal supplied by the reference counter and the divided output from the programmable counter. the frequencies and phase differences of these two signals are then equalized by passing them through low-pass filters. these signals then control the vco. the filter constants can be customized for fm and am bands since the signals are output in parallel from the phase comparator then pass through the two tristate buffer pins, do1 and do2. phase comparator fm vco am vco programmable counter output reference frequency signal r s v dd v dd do1 do2 l.p.f l.p.f fig.7
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 18 r s do low level floating high level do output timing chart fig.8 do r1 r2 tr1 tr2 r3 r l c v cc to vco varactor diode typical low-pass filter constants (fm band reference values) c=0.33 f r1=10k r2=8.2k r3=330 r l =10k standard tr1:2sc1815 tr2:2sk246 typical active low-pass filter circuit fig.9 the figures above show the do output timing chart and a typical active low-pass filter circuit featuring a darlington connection between the fet and transistor. the filter circuit shown above is just one example. actual circuits should be designed based on the band composition and the properties desired from the system. pin do2 can be switched for use as pin ot-4. lock detection bits the lock detection bits detect locked states in the pll system. these systems have an unlock detection bit (unlock bit) which is used to detect, using the reference frequency cycle, the phase difference between the reference frequency and divided output of programmable counter. these systems also have phase error detection bits ( bits pe1~pe3), which are capable of more precise detection ( 0.55 s~ 7.15 s). 1. unlock detection bit (unlock) this bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. when there is no lock, that is, when the reference frequency and the divided output of the programmable counter are not the same, unlock f/f is set. unlock f/f is reset every time the input register (d2h) unlock reset bit (reset) is set to ?1?. after unlock f/f has been reset in this way, locked state can detected by checking the unlock detection bit (unlock) of the output register (d3h). after unlock f/f has been reset, the unlock detection bit must be checked after a time interval exceeding that of the reference frequency cycle has elapsed. this is because the reference frequency cycle inputs the lock detection strobe to unlock f/f. if the time interval is short, the correct locked state cannot be detected. therefore, the output register (d3h) has a lock enable bit (enable). this bit is reset every time the input register (d2h) reset bit is set to ?1?, and set to ?1? through the lock detection timing. that is, the locked state is correctly detected when the lock enable bit (enable) is ?1?.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 19 "h" level high impedance "l" level reference frequency programmable counter output do output phase comparator lock detection strobe unlock is reset (reset) unlock f/f (unlock) lock enable (enable) phase error detection counts phase difference. fig.10 lsb msb address d2h lsb msb address d3h input register output register ena- ble un lock reset setting data to "1" resets unlock detection bit and lock enable bit. 1 0 pll lock detection enabled pll lock detection in waiting state 1 0 pllinunlockedstate(*) pllinlockedstate note: the asterisk (*) indicates an error state of over 180 phase difference relative to the reference frequency 2. phase error detection bits (pe1~pe3) the unlock bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. the phase error detection bits (bits pe1~pe3) are capable of precise phase error detection of 0.55 s~ 7.15 s using the reference frequency cycle.( if the unlock bit is set to ?1? and the phase difference relative to the reference frequency is over 180 ,bits pe1~pe3 cannot correctly detect the phase error. therefore, bits pe1~pe3 are normally used when the unlock bit is set to ?0?.) bits pe1~pe3 detect phase error normally when the phase difference is -180 ~180 relative to the reference frequency cycle.
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 20 lsb msb address d3h pe1 pe2 pe3 pe1 pe2 pe3 000 001 010 011 100 11 0 110 111 phase error (pe) pe< 0.55 s 0.55 s pe< 1.65 s 1.65 s pe< 2.75 s 2.75 s pe< 3.85 s 3.85 s pe< 4.95 s 4.95 s pe< 6.05 s 6.05 s pe< 7.15 s 7.15 s pe the phase error data can be read from the output register (d3h) as serial data pe1~pe3. following is a typical lock detection operation. it shows the operation flow from locked state to frequency change with a phase error greater than 6.05 s. frequency change wait phase error detection start reset bit 1 wait time interval exceeding that of reference frequcncy cycle enable=1? unlock bit =0? check phase error detection bits pe1,pe2 and pe3 pe1=1,pe2=0,pe3=1? phase error=greater than 4.95 s and less than 6.05 s yes yes (lock) yes no no no (unlock) fig.11
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 21 other control bits 1. clk and c5 bits?control bits which switch the function for the ot-4/do2 pin. the o4c bit controls switching of the do2 pin and ot-4 pin. when bits r0~r3 of the input register (d0h) are set to ?1? (standby mode). lsb msb address d2h o4c xt o4c xt 00 1 0 10 11 do2/ot-4 pin state do2 output ot-4 output crystal oscillator circuit state oscillator circuit on oscillator circuit off oscillator circuit off oscillator circuit on when one of bit r0~r3 of the input register (d0h) is set to ?0? (not standby mode) lsb msb address d2h o4c xt o4c xt 00 1 0 10 11 do2/ot-4 pin state do2 output ot-4 output crystal oscillator circuit state oscillator circuit on 2. dohz bit?controls the do2 pin output state. lsb msb address d2h dohz 0 1 phase comparison error output do2 output fixed at high impedance 3. test bit? data should normally be set to ?0?. lsb msb address d2h test "0"
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 22 electrical characteristics curve 1414 1000 500 200 106 71 50 20 10 5 2 1 0.1 0.2 0.5 1 2 5 20 10 50 100 amin(lf) frequency characteristics input level (mvrms) input frequency (mhz) 1414 1000 500 200 106 71 50 20 10 5 2 1 0.1 0.2 0.5 1 2 5 20 10 50 100 amin(hf) frequency characteristics input level (mvrms) input frequency (mhz) 40 1414 1000 500 200 106 71 50 20 10 5 2 1 020 fmin(lf) frequency characteristics input level (mvrms) input frequency (mhz) 40 60 80 100 120 140 160 180 200 1414 1000 500 200 106 71 50 20 10 5 2 1 ifin(lf) frequency characteristics input level (mvrms) input frequency (mhz) 0.05 0.1 0.2 0.5 1 2 5 10 50 15 20 (note) operating guarantee range v dd =4.5~5.5v,ta = -40 ~ 85 ) standard characteristics(v dd =5v,ta=25 ) (note) operating guarantee range (v dd =4.5~5.5v,ta = -40 ~ 85 ) + fm in :fm h fm in :fm l standard characteristics(v dd =5v,ta=25 )
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 23 application circuit 1 2 3 4 5 6 7 8 13 11 10 9 sc9256 16 15 micro- controller period clock data cx'tal v cc am vco am vco 3 5vtyp. varator diode am if signal fm if signal 0.001 f 0.01 f 4.7 f0.1 f output port 0.01 f c 14 12 0.01 f
silan semiconductors sc9256 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2002.01.30. 24 package outline dip-16-300-2.54 unit: mm 6.35 0.25 2.54 4.36max 3.00min 7.62(300) 15 degree 0.5 0.1 19.55 0.3 1.52 0.25 0.05 0.5min 1.27max sop-16-300-1.27 unit:mm 7.80 0.40 5.30 0.30 7.62(300) 10.15 0.25 8.89 1.27 0.45 0.10 0.15 2.25max +0.05 -0.02

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