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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. 1991 data sheet mos integrated circuit m pd78c10a(a), 78c11a(a), 78c12a(a) description the m pd78c11a(a) is a cmos 8-bit microcomputer that features single-chip integration of a 16-bit alu, rom, ram, an a/d converter, a multifunctional timer/event counter, and a universal serial interface, as well as up to 60 kbytes of expandable external memory (rom/ram). the m pd78c10a(a) is the romless version of the m pd78c11a(a) which can directly address up to 64 kbytes of external memory. the m pd78c12a(a) is a version of the m pd78c11a(a) that has greater on-chip rom capacity and is expandable to up to 56 kbytes of external memory (rom/ram). the m pd78c10a(a), m pd78c11a(a), and m pd78c12a(a) all use cmos technology to enable low-power operation and they also feature standby functions to enable data retention and other operations using very low power consumption. in addition, the m pd78cp14(a) and 78cp18(a) are available as on-chip prom versions appropriate for evaluating and prototyping during system development as well as for early development of application sets and low-volume production. detailed functional descriptions are provided in the following users manual. this manual is required reading for design work. 87ad series m pd78c18 users manual: ieu-1314 features ? higher reliability than m pd78c10a, 78c11a, or 78c12a ? 159 instructions: the 87ad series instruction set with multiply and divide instructions and 16-bit arithmetic instructions ? 0.8 m s instruction cycle time (15-mhz operation) ? on-chip rom: 4096-w x 8 ( m pd78c11a(a)), 8192-w x 8 ( m pd78c12a(a)), or none ( m pd78c10a(a)) ? on-chip ram: 256-w x 8 ? high-precision 8-bit a/d converter: 8 analog inputs ? universal serial interface: asynchronous, synchronous, and i/o interface modes ? multifunctional 16-bit timer/event counter ? two 8-bit timers ? i/o lines: 32 in m pd78c10a(a) and 44 in m pd78c11a(a) or 78c12a(a) ? interrupt functions (3 external, 8 internal): 1 nonmaskable interrupt and 10 maskable interrupts ? standby functions: halt mode and hardware/software stop mode ? zero-cross detection function: 2 inputs ? on-chip mask optional pull-up resistors are available (for ports a, b, and c on m pd78c11a(a) or 78c12a(a) only) caution mask options are not available on the m pd78c10a(a). document no. ic-2846b (o.d. no. ic-8253b) date published may 1995 p printed in japan the information in this document is subject to change without notice. 8-bit single-chip microcomputer (with a/d converter) the mark h shows revised points. m pd78c10a(a), 78c11a(a), 78c12a(a) 2 ordering information part no. package on-chip rom m pd78c10agf(a)-3be 64-pin plastic qfp (14 x 20 mm) none m pd78c10agq(a)-36 64-pin plastic quip none m pd78c10al(a) 68-pin plastic qfj (950 x 950 mil) none m pd78c11agf(a)-xxx-3be 64-pin plastic qfp (14 x 20 mm) mask rom m pd78c11agq(a)-xxx-36 64-pin plastic quip mask rom m pd78c11al(a)-xxx 68-pin plastic qfj (950 x 950 mil) mask rom m pd78c12agf(a)-xxx-3be 64-pin plastic qfp (14 x 20 mm) mask rom m pd78c12agq(a)-xxx-36 64-pin plastic quip mask rom m pd78c12al(a)-xxx 68-pin plastic qfj (950 x 950 mil) mask rom quality grade special (for high-reliability electronic devices) please refer to "quality grade on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. m pd78c10a(a), 78c11a(a), 78c12a(a) 3 pin configuration (top view) m pd78c10agq(a)-36, 78c11agq(a)-xxx-36, or 78c12agq(a)-xxx-36 m pd78c10agf(a)-3be, 78c11agf(a)-xxx-3be, or 78c12agf(a)-xxx-3be pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/txd pc1/rxd pc2/scr pc3/int2 pc4/to pc5/ci pc6/co0 pc7/co1 nmi int1 mode1 reset mode0 x2 x1 v ss v dd stop pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd av dd v aref an7 an6 an5 an4 an3 an2 an1 an0 av ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pd3 pd2 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd av dd v aref an7 an6 an5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/t x d pc1/r x d pc2/sck pc3/int2 pc4/to pc5/ci pc6/co0 pc7/co1 nmi pd4 pd5 pd6 pd7 stop v dd pa0 pa1 pa2 pa3 pa4 pa5 an4 an3 an2 an1 an0 av ss v ss x1 x2 mode0 reset mode1 int1 52 53 54 55 56 57 58 59 60 61 62 63 64 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 30 29 28 27 26 25 24 23 22 21 20 m pd78c10a(a), 78c11a(a), 78c12a(a) 4 m pd78c10al(a), 78c11al(a)-xxx, or 78c12al(a)-xxx pc7/cop1 nmi int1 mode1 reset mode0 x2 x1 v ss av ss an0 an1 an2 an3 an4 an5 an6 ic pa6 pa5 pa4 pa3 pa2 pa1 pa0 v dd stop pd7 pd6 pd5 pd4 pd3 pd2 ic pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/t x d pc1/r x d pc2/sck pc3/int2 ic pc4/to pc5/ci pc6/co0 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd av dd ic v aref an7 9876543216867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 m pd78c10a(a), 78c11a(a), 78c12a(a) 5 block diagram osc serial i/o timer timer/ event counter int. control a/d converter x1 x2 pc0/t x d pc1/r x d pc2/sck nmi int1 pc3/int2/ti pc4/to pc5/ci pc6/co0 pc7/co1 an7-0 v aref av dd av ss 8 8 4 8 8 8 8 8 16 16 6 latch psw latch 16 16 16 alu (8/16) internal data bus 8/16 program memory (note 1) data memory (256-byte) 88 12/13 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 port f port d port c port b port a pf7-0/ab15-8 pd7-0/ad7-0 pc7-0 (note 2) pb7-0 (note 2) pa7-0 (note 2) inst.reg inst. decoder read/write control system control standby control rd wr ale mode0 mode1 reset stop v dd v ss latch inc/dec pc sp ea ea' buffer a c e l a' c' e' l' v b d h v' b' d' h' main g, r alt g, r notes 1. varies depending on model. 2. on-chip mask optional pull-up resistors are available ( pd78c11a(a) or 78c12a(a) only). the pd78c11a(a) has 4 kbytes and the pd78c12a(a) has 8 kbytes. the pd78c10a(a) does not have any program memory. m m m m m pd78c10a(a), 78c11a(a), 78c12a(a) 6 quality grade electrical specifica- tions packages m pd78c10a, 78c11a, 78c12a standard (for ordinary electronic equipment) input leakage current an0 to an7, 10 m a (max) ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic quip ? 64-pin plastic quip straight (note) ? 64-pin plastic qfp (14 x 20 mm) ? 68-pin plastic qfj (950 x 950 mil) m pd78c10a(a), 78c11a(a), 78c12a(a) special (for high-reliability electronic equipment) input leakage current an0 to an7, 1 m a (max) ? 64-pin plastic qfp (14 x 20 mm) ? 64-pin plastic quip ? 68-pin plastic qfj (950 x 950 mil) category part differences between (1) m pd78c10a(a), 78c11a(a), and 78c12a(a) and (2) m pd78c10a, 78c11a, and 78c12a note m pd78c11a and 78c12a only m pd78c10a(a), 78c11a(a), 78c12a(a) 7 contents 1. pin functions ................................................................................................................ .............. 8 1.1 pin function list ........................................................................................................... ......... 8 1.2 pin i/o lines ............................................................................................................... ............ 10 1.3 pin mask options ............................................................................................................ ...... 15 1.4 recommended connections of unused pins ...................................................................... 15 2. differences between (1) m pd78c10a(a) and (2) m pd78c11a(a) and 78c12a(a) ............ 16 3. reset operation .............................................................................................................. ........... 18 4. instruction set .............................................................................................................. ............ 21 4.1 operand symbols and definitions ....................................................................................... 21 4.2 description of instruction code symbols ........................................................................... 22 4.3 instruction execution times ................................................................................................. 23 5. mode register list ........................................................................................................... ......... 35 6. electrical specifications .................................................................................................... ... 36 7. characteristic curves (reference values) .................................................................... 47 8. package drawings ............................................................................................................. ....... 50 9. recommended soldering conditions ................................................................................ 54 appendix development tools ................................................................................................... 56 m pd78c10a(a), 78c11a(a), 78c12a(a) 8 1. pin functions 1.1 pin function list pin name pa7-0 (port a) pb7-0 (port b) pc0/txd pc1/rxd pc2/sck pc3/int2/ti pc4/to pc5/ci pc6/co0 pc7/co1 pd7-0/ad7-0 pf7-0/ab15-8 wr (write strobe) rd (read strobe) ale (address latch enable) i/o i/o i/o i/o or o i/o or i i/o or i/o i/o or i or i i/o or o i/o or i i/o or o i/o or i/o i/o or o o o o function port a is an 8-bit i/o port for which the input or output mode can be specified bit-wise. port b is an 8-bit i/o port for which the input or output mode can be specified bit-wise. port c when used as port c, it is an 8-bit i/o port for which the input or output mode can be speci- fied bit-wise. port d when used as port d, it is an 8-bit i/o port for which the input or output mode can be speci- fied byte-wise ( m pd78c11a(a)). port f when used as port f, it is an 8-bit i/o port for which the input or output mode can be speci- fied bit-wise. this is a strobe signal that is output for external memory write operations. it goes high except during the external memorys data write cycle. output has high impedance when the reset signal is low or during hardware stop mode. this is a strobe signal that is output for external memory read operations. it goes high except during the external memorys data read cycle. output has high impedance when the reset signal is low or during hardware stop mode. a strobe signal is used to externally latch the low-order address data output to pd0 to pd7 for external memory access. output has high impedance when the reset signal is low or during hardware stop mode. transmit data when used for transmit data output, it is a serial data output pin. receive data when used for receive data input, it is a serial data input pin. serial clock when used for serial clock i/o, it is an output pin for the internal clock or an input pin for an external clock. interrupt request/timer input when used for interrupt request or timer input, it is a falling-edge triggered maskable interrupt input pin, or a timer input pin for external clock input, or an ac-input, zero- cross detection pin. timer output when used for timer output, it outputs a square wave having a count time of one- half cycle per internal clock cycle. counter input when used for counter input, it is an input pin for external pulses to the timer/event counter. counter output0, 1 when used for counter outputs 0 and 1, these pins output a programmable square wave from the timer/event counter. address/data bus when using external memory, it acts as a multiplexed address/data bus. address bus when using external memory, it acts as an address bus. m pd78c10a(a), 78c11a(a), 78c12a(a) 9 pin name mode0 mode1 (mode) nmi (non-maskable interrupt) int1 (interrupt request) an7-0 (analog input) v aref (reference voltage) av dd (analog v dd ) av ss (analog v ss ) x1, x2 (crystal) reset (reset) stop (stop) v dd v ss i/o i/o i i i i i i function in the m pd78c11a(a) and 78c12a(a), the mode0 pin is set to 0 (low) and the mode1 pin is set to 1 (high) (note) . in the m pd78c10a(a), the mode0 and mode1 pins are used to select one of three external memory sizes: 4 kbytes, 16 kbytes, or 64 kbytes. if mode0 and mode1 are both set to 1 (note) , a control signal is output synchronously with ale. this is a falling edge-triggered nonmaskable interrupt input pin. int1 is a rising edge-triggered maskable interrupt input pin. it is also an ac-input, zero- cross detection pin. these are eight analog inputs to the a/d converter. an4 to an7 can also be used as inputs for falling edge detection. this pin can be used as a reference voltage input for the a/d converter or as a control pin for a/d converter operation. this is the power supply pin for the a/d converter. this is the ground pin for the a/d converter. these are the crystal pins for the system clock oscillator. x1 inputs an external clock. x2 inputs the inverted clock from x1. this is the system reset input pin (active low). this is the control signal input pin during hardware stop mode. low-level input stops the system clock oscillator. positive power supply pin ground pin mode0 mode1 external memory 0 0 4 kbytes 1 0 16 kbytes 1 1 64 kbytes note these must be pulled up using a pull-up resistance value (r) of 4 (k w ) r 0.4 t cyc (k w ). (t cyc is in ns units.) remark on-chip pull-up resistors for ports a, b, and c are available as mask options on the m pd78c11a(a) or 78c12a(a). h m pd78c10a(a), 78c11a(a), 78c12a(a) 10 1.2 pin i/o lines tables 1-1 and 1-2 list the i/o lines to the various pins, and (1) to (15) show partial diagrams of these lines. table 1-1. pin type numbers ( m pd78c10a(a)) table 1-2. pin type numbers ( m pd78c11a(a), 78c12a(a)) pin name pa7-0 pb7-0 pc1-0 pc2/sck pc3/int2 pc7-4 pd7-0 pf7-0 nmi int1 type no. 5 5 5 8 10 5 5 5 2 9 pin name reset rd wr ale stop mode0 mode1 an3-0 an7-4 v aref type no. 2 4 4 4 2 11 11 7 12 13 pin name pa7-0 pb7-0 pc1-0 pc2/sck pc3/int2 pc7-4 pd7-0 pf7-0 nmi int1 type no. 5-a 5-a 5-a 8-a 10-a 5-a 5 5 2 9 pin name reset rd wr ale stop mode0 mode1 an3-0 an7-4 v aref type no. 2 4 4 4 2 11 11 7 12 13 m pd78c10a(a), 78c11a(a), 78c12a(a) 11 v dd p-ch n-ch out output disable output data (1) type1 (2) type2 (3) type4 (4) type4-a v dd p-ch n-ch out output disable output data p-ch v dd n-ch in in m pd78c10a(a), 78c11a(a), 78c12a(a) 12 (5) type5 (6) type5-a (7) type7 (8) type8 in/out output disable output data type4 type1 in/out output disable output data type4-a type1 in/out output disable output data type2 type5 mcc av dd av dd av ss av ss reference voltage (from series resistor string's voltage tap). n-ch p-ch + - sampling c in m pd78c10a(a), 78c11a(a), 78c12a(a) 13 (9) type8-a (10) type9 (11) type10 in/out output disable output data type2 type5-a mcc in/out output disable output data type5 type9 self bias enable mcc type1 self bias enable in data m pd78c10a(a), 78c11a(a), 78c12a(a) 14 (12) type10-a (13) type11 (14) type12 (15) type13 in/out output disable output data type5-a type9 self bias enable mcc in/out output data type1 n-ch type7 type2 in edge detection circuit type1 in stop mode av ss m pd78c10a(a), 78c11a(a), 78c12a(a) 15 1.3 pin mask options the following mask options are available for pins in the m pd78c11a(a) and 78c12a(a). they are selectable bit-wise according to the use objective. cautions 1. if there is an on-chip pull-up resistor for pc3, the zero-cross function will not operate normally. 2. the m pd78c10a(a) has no mask options. 1.4 recommended connections of unused pins pin name pa7-0 pb7-0 pc7-0 mask option (a) on-chip pull-up resistor (b) no on-chip pull-up resistor pin pa7-0 pb7-0 pc7-0 pd7-0 pf7-0 rd wr ale stop int1, nmi av dd v aref av ss an7-0 recommended connection connect via a resistor to v ss or v dd . no connection connect to v dd . connect to v ss or v dd . connect to v dd . connect to v ss . connect to av ss or av dd . m pd78c10a(a), 78c11a(a), 78c12a(a) 16 2. differences between (1) m pd78c10a(a) and (2) m pd78c11a(a) and 78c12a(a) the main difference between the m pd78c10a(a) and the m pd78c11a(a) and 78c12a(a) is that the m pd78c10a(a) does not have an on-chip mask programmable rom. this results in the memory mapping differences described below. (1) m pd78c10a(a) because the m pd78c10a(a) does not have on-chip rom, all memory except for the on-chip ram area (ff00h to ffffh) are installed externally. the amount of externally installed memory can be set using the mode0 and mode1 pins. as shown in the following table and in figure 2-1, there are three memory access options: 4 kbytes (0000h to 0fffh), 16 kbytes (0000h to 3fffh) and 64 kbytes (0000h to feffh). external memory can be accessed via pd0 to pd7 (multiplexed address/data buses), pf0 to pf7 (address buses), or the rd, wr, or ale signals. when accessing 4 kbytes or 16 kbytes of external memory, address buses (pf0 to pf7) that are not being used as address lines can be used as an ordinary i/o port. use the mode0 and mode1 pins to select the amount of externally installed memory and set the memory mapping registers mm2, mm1, and mm0 bits to 0. (2) m pd78c11a(a), 78c12a(a) the m pd78c11a(a) has on-chip mask programmable rom from addresses 0000h to 0fffh and on-chip ram from addresses ff00h to ffffh. up to 60 kbytes (addresses 1000h to feffh) of external expansion memory can be added in steps. the m pd78c12a(a) has on-chip mask programmable rom from addresses 0000h to 1fffh and on-chip ram from addresses ff00h to ffffh. up to 56 kbytes (addresses 2000h to feffh) of external expansion memory can be added in steps. set the memory mapping register to select among five external expansion memory modes: no external memory, 256 bytes, 4 kbytes, 16 kbytes, and 56 or 60 kbytes (note) . external memory can be accessed via pd0 to pd7 (multiplexed address/data buses), pf0 to pf7 (address buses), or using the rd, wr, or ale signals. external memory can contain either programs or data. some address buses (pf0 to pf7) are used as address lines, depending on the memory size, and any remaining address buses can be used as an ordinary i/o port. note 56 kbytes for the m pd78c12a(a) and 60 kbytes for the m pd78c11a(a) operation mode 4-kbyte access 16-kbyte access 64-kbyte access control pins mode1 mode0 00 01 11 external memory 4 kbytes (addresses 0000h to 0fffh) 16 kbytes (addresses 0000h to 3fffh) 64 kbytes (addresses 0000h to feffh) on-chip ram addresses ff00h to ffffh addresses ff00h to ffffh addresses ff00h to ffffh pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 external memory port port port port port port port port 256 bytes max port port port port ab11 ab10 ab9 ab8 4 kbytes max port port ab13 ab12 ab11 ab10 ab9 ab8 16 kbytes max ab15 ab14 ab13 ab12 ab11 ab10 ab9 ab8 56/60 kbytes max (note) m pd78c10a(a), 78c11a(a), 78c12a(a) 17 figure 2-1. m pd78c10a(a) memory map 4 - kbyte access 16 - kbyte access 64 - kbyte access mode0 = 0 mode1 = 0 mode0 = 1 mode1 = 0 mode0 = 1 mode1 = 1 external memory external memory external memory on - chip ram on - chip ram on - chip ram not used not used 0000h 0fffh ff00h ffffh 3fffh m pd78c10a(a), 78c11a(a), 78c12a(a) 18 3. reset operation low-level input to the reset input causes a system reset, after which the following states occur. interrupt enable f/f is reset and the interrupt disable state occurs. all interrupt mask registers are set (to 1) so that all interrupts are masked. the interrupt request flag is set (to 0) so that any pending interrupt is released. all psws are reset (to 0). 0000h is loaded into the program counter (pc). the mode a register, mode b register, mode c register, and mode f register are set to ffh and the mm0, mm1, and mm2 bits in the mode control c register and memory mapping register are reset (to 0). port a, port b, port c, port d, and port f all become input ports (high-impedance output). all test flags except the sb flag are reset (to 0). the timer mode register is set to ffh and the timer f/f is reset. the timer/event counters mode registers (etmm, eom) are reset (to 0). the serial interfaces serial mode high register (smh) is reset (to 0) and the serial mode low register (sml) is set to 48h. the a/d converters a/d channel mode register is reset (to 0). the wr, rd, and ale signal are set for high impedance. zero cross mode register (zcm) bits zc1 and zc2 are set to 1. the internal timers are initialized. the data memory and the contents of the following registers are undefined. stack pointer (sp) expansion accumulators (ea, ea) and accumulators (a, a) general-purpose registers (b, c, d, e, h, l, b, c, d, e, h, l) output latch for each port timer reg0 and reg1 (tm0, tm1) timer/event counter reg0 and reg1 (etm0, etm1) memory mapping registers rae bit test flags sb flag when reset input goes high, the reset state is canceled and program execution begins from address 0000h. at that point, initialize or reinitialize the various register contents as required by the program. table 3-1 lists various hardware states after reset and table 3-2 lists various pin states after reset. m pd78c10a(a), 78c11a(a), 78c12a(a) 19 table 3-1. hardware states after reset hardware internal data memory expansion accumulators (ea, ea) accumulators (a, a) general-purpose registers (b, c, d, e, h, l, b, c, d, e, h, l) working registers vector registers (v, v) program counter (pc) stack pointer (sp) ports output latch for each port interrupt test flags (except sb flag) standby flag (sb) timer timer/event counter serial interface a/d channel mode register (anm) mm register (mm3, rae bit) zero-cross mode register (bits zc1 and zc2) state after reset previous contents are retained undefined previous contents are retained undefined 0000h undefined ffh 00h 0 undefined 0 0 ffh 0 1 previous contents are retained contents prior to re- set input are retained ffh 0 undefined 00h undefined 00h 48h 00h undefined 1 reset input during nor- mal operation during cpu write operation operation other than cpu write write address data other address data during power-on reset reset input during standby mode mode registers (ma, mb, mc, mf) mcc register mm register (bits mm0 to mm2) interrupt enable f/f request flag mask register during power-on reset during standby mode reset input during normal operation timer mode register (tmm) timer f/f timer registers (tm0, tm1) timer/event counter mode register (etmm) timer/event counter output mode register (eom) timer/event counter registers (etm0, etm1) timer/event counter capture register (ecpt) timer/event counter (ecnt) serial mode high register (smh) serial mode low register (sml) h h h m pd78c10a(a), 78c11a(a), 78c12a(a) 20 table 3-2. pin states after reset pin wr rd ale all ports (pa, pb, pc, pd, pf) state after reset high impedance m pd78c10a(a), 78c11a(a), 78c12a(a) 21 3. rpa to rpa3 (rp addressing) 4. instruction set 4.1 operand symbols and definitions note nmi can also be written as fnmi. remarks 1. sr to sr4 (special register) 2. rp to rp3 (register pair) 4. f (flag) symbol r r1 r2 sr sr1 sr2 sr3 sr4 rp rp1 rp2 rp3 rpa rpa1 rpa2 rpa3 wa word byte bit f irf definition v, a, b, c, d, e, h, l eah, eal, b, c, d, e, h, l a, b, c pa, pb, pc, pd, pf, mkh, mkl, anm, smh, sml, eom, etmm, tmm, mm, mcc, ma, mb, mc, mf, txb, tm0, tm1, zcm pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm, rxb, cr0, cr1, cr2, cr3 pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm etm0, etm1 ecnt, ecpt sp, b, d, h v, b, d, h, ea sp, b, d, h, ea b, d, h b, d, h, d +, h +, d C, h C b, d, h b, d, h, d +, h +, d C, h C, d + byte, h + a, h + b, h + ea, h + byte d, h, d ++, h ++, d + byte, h + a, h + b, h + ea, h + byte 8 bit immediate data 16 bit immediate data 8 bit immediate data 3 bit immediate data cy, hc, z nmi (note) , ft0, ft1, f1, f2, fe0, fe1, fein, fad, fsr, fst, er, ov, an4, an5, an6, an7, sb pa : port a etmm : timer/event pb : port b counter mode pc : port c eom : timer/event pd : port d counter output mode pf : port f anm : a/d channel mode ma : mode a cr0 : a/d conversion mb : mode b to result 0 to 3 mc : mode c cr3 mcc : mode control c txb : tx buffer mf : mode f rxb : rx buffer mm : memory mapping smh : serial mode high tm0 : timer reg0 sml : serial mode low tm1 : timer reg1 mkh : mask high tmm : timer mode mkl : mask low etm0: timer/event zcm : zero cross mode counter reg0 etm1: timer/event counter reg1 ecnt : timer/event counter upcounter ecpt : timer/event counter capture cy : carry hc : half carry z : zero nmi : nmi input ft0 : intft0 ft1 : intft1 f1 : intf1 f2 : intf2 fe0 : intfe0 fe1 : intfe1 fein : intfein fad : intfad fsr : intfsr fst : intfst er : error ov : overflow an4 : analog input4 to 7 to an7 sb : standby sp : stack pointer b:bc d:de h:hl v:va ea : extended accumulator b : (bc) d : (de) h : (hl) d + : (de) + h + : (hl) + d C : (de) C h C : (hl) C d ++ : (de) ++ h ++ : (hl) ++ d + byte : (de + byte) h + a : (hl + a) h + b : (hl + b) h + ea : (hl + ea) h + byte : (hl + byte) 5. irf (interrupt flag) m pd78c10a(a), 78c11a(a), 78c12a(a) 22 4.2 description of instruction code symbols rpa r1 r sr sr3 sr4 r 2 0 0 0 0 1 1 1 1 reg v a b c d e h l u 0 0 1 special-reg etm0 etm1 r 0 0 1 0 1 0 1 0 1 r 1 0 0 1 1 0 0 1 1 r r2 rp3 rp2 rp sr sr1 sr2 rpa rpa2 rpa1 t 2 0 0 0 0 1 1 1 1 reg eah eal b c d e h l t 0 0 1 0 1 0 1 0 1 t 1 0 0 1 1 0 0 1 1 a 3 0 0 0 0 0 0 0 0 1 1 1 1 1 a 2 0 0 0 0 1 1 1 1 0 1 1 1 1 a 1 0 0 1 1 0 0 1 1 1 0 0 1 1 addressing (bc) (de) (hl) (de) + (hl) + (de) - (hl) - (de + byte) (hl + a) (hl + b) (hl + ea) (hl + byte) a 0 0 1 0 1 0 1 0 1 1 0 1 0 1 rpa3 c 3 0 0 0 0 1 1 1 1 1 c 2 0 0 1 1 0 1 1 1 1 c 1 1 1 0 0 1 0 0 1 1 addressing (de) (hl) (de) ++ (hl) ++ (de + byte) (hl + a) (hl + b) (hl + ea) (hl + byte) c 0 0 1 0 1 1 0 1 0 1 irf i 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 i 3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 i 2 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 intf nmi ft0 ft1 f1 f2 fe0 fe1 fein fad fsr fst er ov an4 an5 an6 an7 sb i 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 i 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 s 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 s 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 s 3 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 special-reg pa pb pc pd pf mkh mkl anm smh sml eom etmm tmm mm mcc ma mb mc mf txb rxb tm0 tm1 cr0 cr1 cr2 cr3 zcm s 2 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 s 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 s 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 rp p 2 0 0 0 0 1 reg-pair sp bc de hl ea p 0 0 1 0 1 0 p 1 0 0 1 1 0 v 0 0 1 special-reg ecnt ecpt rp1 q 2 0 0 0 0 1 reg-pair va bc de hl ea q 0 0 1 0 1 0 q 1 0 0 1 1 0 f f 2 0 0 0 1 flag cy hc z f 0 0 0 1 0 f 1 0 1 1 0 m pd78c10a(a), 78c11a(a), 78c12a(a) 23 4.3 instruction execution times below, one state is equal to three clock cycles. when using a 15-mhz clock, one state is 200 ns (= 3 x 1/ 15 m s). in this case, the minimum execution time for a four-state instruction time is 0.8 m s. m pd78c10a(a), 78c11a(a), 78c12a(a) 24 00011t 2 t 1 t 0 00001t 2 t 1 t 0 01001101 01001100 01110000 01110000 01101r 2 r 1 r 0 01100100 01110001 010010a 1 a 0 01100011 00000001 a 3 0111a 2 a 1 a 0 a 3 0101a 2 a 1 a 0 00010001 00010000 01010000 00110001 101101p 1 p 0 101001p 1 p 0 4 4 10 10 17 17 7 14 13 10 10 10 7/13 (note 3) 7/13 (note 3) 4 4 4 4 4 r1 ? a a ? r1 sr ? a a ? sr1 r ? (word) (word) ? r r ? byte sr2 ? byte (v.wa) ? byte (rpa1) ? byte (v.wa) ? a a ? (v.wa) (rpa2) ? a a ? (rpa2) v,a ? v',a', ea ? ea' h,l ? h',l' rp3 l ? eal, rp3 h ? eah eal ? rp3 l , eah ? rp3 h r1, a a, r1 sr, a a, sr1 r, word word, r r, byte sr2, byte wa, byte rpa1, byte wa wa rpa2 rpa2 rp3, ea ea, rp3 * * * * * * * * * mov mvi mviw mvix staw ldaw stax ldax exx exa exh block dmov instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 low adrs low adrs data data high adrs high adrs 11s 5 s 4 s 3 s 2 s 1 s 0 11s 5 s 4 s 3 s 2 s 1 s 0 01101r 2 r 1 r 0 01111r 2 r 1 r 0 data s 3 0000s 2 s 1 s 0 offset data offset offset data (note 1) data (note 1) instruction code 16-bit data transfer instructions 8-bit data transfer instructions 13 (c+1) (de) + ? (hl) + ,c ? c - 1 end if borrow b ? b', c ? c', d ? d' e ? e', h ? h', l ? l' m pd78c10a(a), 78c11a(a), 78c12a(a) 25 14 14 20 20 20 20 14/20 (note 3) 20 20 20 20 14/20 (note 3) 13 10 10 17 8 8 8 8 sr3 ? ea ea ? sr4 (word) ? c, (word + 1) ? b (word) ? e, (word + 1) ? d (word) ? l, (word + 1) ? h (word) ? sp l , (word + 1) ? sp h (rpa3) ? eal, (rpa3 + 1) ? eah c ? (word), b ? (word + 1) e ? (word), d ? (word + 1) l ? (word), h ? (word + 1) sp l ? (word), sp h ? (word + 1) eal ? (rpa3), eah ? (rpa3 + 1) rp2 ? word a ? a + r r ? r + a a ? a + r + cy r ? r + a + cy sr3, ea ea, sr4 word word word word rpa3 word word word word rpa3 rp1 rp1 rp2, word a, r r, a a, r r, a * dmov sbcd sded shld sspd steax lbcd lded lhld lspd ldeax push pop lxi table add adc instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 low adrs data (note 2) low adrs data (note 2) high byte high adrs high adrs 1101001u 0 1100000v 0 00011110 00101110 00111110 00001110 1001c 3 c 2 c 1 c 0 00011111 00101111 00111111 00001111 1000c 3 c 2 c 1 c 0 low byte 10101000 11000r 2 r 1 r 0 0100 1101 0101 instruction code 8-bit arithmetic instructions (register) 16-bit data transfer instructions (sp - 1) ? rp1 h , (sp - 2) ? rp1 l sp ? sp - 2 rp1 l ? (sp), rp1 h ? (sp + 1) sp ? sp + 2 c ? (pc + 3 + a) b ? (pc + 3 + a + 1) 01001000 01110000 01001000 01110000 01001000 10110q 2 q 1 q 0 10100q 2 q 1 q 0 0p 2 p 1 p 0 0100 01001000 01100000 m pd78c10a(a), 78c11a(a), 78c12a(a) 26 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 a ? a + r r ? r + a a ? a - r r ? r - a a ? a - r - cy r ? r - a - cy a ? a - r r ? r - a a ? a r r ? r a a ? a r r ? r a a ? a " r r ? r " a a - r - 1 r - a - 1 a - r r - a a - r r - a a, r r, a a, r r, a a, r r, a a, r r, a a, r r, a a, r r, a a, r r, a a, r r, a a, r r, a a, r r, a addnc sub sbb subnb ana ora xra gta lta nea instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 10100r 2 r 1 r 0 0010 0r 2 r 1 r 0 1110 0r 2 r 1 r 0 0110 0r 2 r 1 r 0 1111 0r 2 r 1 r 0 0111 0r 2 r 1 r 0 1011 0r 2 r 1 r 0 0011 0r 2 r 1 r 0 10001r 2 r 1 r 0 0000 0r 2 r 1 r 0 1001 0r 2 r 1 r 0 0001 0r 2 r 1 r 0 10010r 2 r 1 r 0 0001 0r 2 r 1 r 0 10101r 2 r 1 r 0 0010 0r 2 r 1 r 0 1011 0r 2 r 1 r 0 0011 0r 2 r 1 r 0 1110 0r 2 r 1 r 0 0110 0r 2 r 1 r 0 instruction code 8-bit arithmetic instructions (register) 01100000 no carry no carry no borrow no borrow no borrow no borrow borrow borrow no zero no zero m pd78c10a(a), 78c11a(a), 78c12a(a) 27 8 8 8 8 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 a - r r - a a r r a a ? a + (rpa) a ? a + (rpa) + cy a ? a + (rpa) a ? a - (rpa) a ? a - (rpa) - cy a ? a - (rpa) a ? a (rpa) a ? a (rpa) a ? a " (rpa) a - (rpa) - 1 a - (rpa) a - (rpa) a - (rpa) a (rpa) a (rpa) a, r r, a a, r a, r rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa eqa ona offa addx adcx addncx subx sbbx subnbx anax orax xrax gtax ltax neax eqax onax offax instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 11111r 2 r 1 r 0 0111 0r 2 r 1 r 0 1100 0r 2 r 1 r 0 1101 0r 2 r 1 r 0 11000a 2 a 1 a 0 1101 0a 2 a 1 a 0 1010 0a 2 a 1 a 0 1110 0a 2 a 1 a 0 1111 1a 2 a 1 a 0 1011 0a 2 a 1 a 0 10001a 2 a 1 a 0 1001 0a 2 a 1 a 0 10010a 2 a 1 a 0 10101a 2 a 1 a 0 1011 1a 2 a 1 a 0 1110 0a 2 a 1 a 0 1111 0a 2 a 1 a 0 1100 0a 2 a 1 a 0 1101 0a 2 a 1 a 0 instruction code 8-bit arithmetic instructions (memory) 01100000 01110000 zero zero no zero zero no carry no borrow no borrow borrow no zero zero no zero zero 8-bit arithmetic instructions (register) m pd78c10a(a), 78c11a(a), 78c12a(a) 28 01000110 01110100 0110 0000 01010110 01110100 0110 0000 00100110 01110100 0110 0000 01100110 01110100 0110 0000 01110110 01110100 0110 0000 00110110 01110100 0110 0000 00000111 01110100 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11 a ? a + byte r ? r + byte sr2 ? sr2 + byte a ? a + byte + cy r ? r + byte + cy sr2 ? sr2 + byte + cy a ? a + byte r ? r + byte sr2 ? sr2 + byte a ? a - byte r ? r - byte sr2 ? sr2 - byte a ? a - byte - cy r ? r - byte - cy sr2 ? sr2 - byte - cy a ? a - byte r ? r - byte sr2 ? sr2 - byte a ? a byte r ? r byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte * * * * * * * adi aci adinc sui sbi suinb ani instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 data data data data data data data data 01000r 2 r 1 r 0 s 3 1000s 2 s 1 s 0 data 01010r 2 r 1 r 0 s 3 1010s 2 s 1 s 0 data 00100r 2 r 1 r 0 s 3 0100s 2 s 1 s 0 data 01100r 2 r 1 r 0 s 3 1100s 2 s 1 s 0 data 01110r 2 r 1 r 0 s 3 1110s 2 s 1 s 0 data 00110r 2 r 1 r 0 s 3 0110s 2 s 1 s 0 data 00001r 2 r 1 r 0 instruction code immediate data arithmetic instructions no carry no caryy no carry no borrow no borrow no borrow m pd78c10a(a), 78c11a(a), 78c12a(a) 29 01100100 00010111 01110100 0110 0000 00010110 01110100 0110 0000 00100111 01110100 0110 0000 00110111 01110100 0110 0000 01100111 01110100 0110 0000 01110111 01110100 0110 0000 20 7 11 20 7 11 20 7 11 14 7 11 14 7 11 14 7 11 14 sr2 ? sr2 byte a ? a byte r ? r byte sr2 ? sr2 byte a ? a " byte r ? r " byte sr2 ? sr2 " byte a - byte - 1 r - byte - 1 sr2 - byte - 1 a - byte r - byte sr2 - byte a - byte r - byte sr2 - byte a - byte r - byte sr2 - byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte r, byte sr2, byte * * * * * * ani ori xri gti lti nei eqi instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 data data data data data data data s 3 0001s 2 s 1 s 0 data 00011r 2 r 1 r 0 s 3 0011s 2 s 1 s 0 data 00010r 2 r 1 r 0 s 3 0010s 2 s 1 s 0 data 00101r 2 r 1 r 0 s 3 0101s 2 s 1 s 0 data 00111r 2 r 1 r 0 s 3 0111s 2 s1s 0 data 01101r 2 r 1 r 0 s 3 1101s 2 s 1 s 0 data 01111r 2 r 1 r 0 s 3 1111s 2 s 1 s 0 instruction code immediate data arithmetic instructions no borrow no borrow no borrow borrow borrow borrow no zero no zero no zero zero zero zero m pd78c10a(a), 78c11a(a), 78c12a(a) 30 01000111 01110100 0110 0000 01010111 01110100 0110 0000 01110100 01110100 7 11 14 7 11 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 a byte r byte sr2 byte a byte r byte sr2 byte a ? a + (v.wa) a ? a + (v.wa) + cy a ? a + (v.wa) a ? a - (v.wa) a ? a - (v.wa) - cy a ? a - (v.wa) a ? a (v.wa) a ? a (v.wa) a ? a " (v.wa) a - (v.wa) - 1 a - (v.wa) a - (v.wa) a - (v.wa) a (v.wa) a, byte r, byte sr2, byte a, byte r, byte sr2, byte wa wa wa wa wa wa wa wa wa wa wa wa wa wa * * oni offi addw adcw addncw subw sbbw subnbw anaw oraw xraw gtaw ltaw neaw eqaw onaw instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 data data offset data 01001r 2 r 1 r 0 s 3 1001s 2 s 1 s 0 data 01011r 2 r 1 r 0 s 3 1011s 2 s 1 s 0 11000000 1101 0000 1010 0000 1110 0000 1111 0000 1011 0000 10001000 1001 0000 10010000 10101000 1011 0000 1110 0000 1111 0000 1100 0000 instruction code immediate data arithmetic instructions no zero no zero no zero zero zero zero no carry no borrow no borrow borrow no zero zero no zero working register arithmetic instructions m pd78c10a(a), 78c11a(a), 78c12a(a) 31 01110100 00000101 0001 0000 0010 0000 0011 0000 0110 0000 0111 0000 0100 0000 0101 0000 01110000 0000 0100 0000 0000 0000 0100 14 19 19 13 13 13 13 13 13 11 11 11 11 11 11 11 11 11 11 11 a (v.wa) (v.wa) ? (v.wa) byte (v.wa) ? (v.wa) byte (v.wa) - byte - 1 (v.wa) - byte (v.wa) - byte (v.wa) - byte (v.wa) byte (v.wa) byte ea ? ea + r2 ea ? ea + rp3 ea ? ea + rp3 + cy ea ? ea + rp3 ea ? ea - r2 ea ? ea - rp3 ea ? ea - rp3 - cy ea ? ea - rp3 ea ? ea rp3 ea ? ea rp3 ea ? ea " rp3 wa wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte ea, r2 ea, rp3 ea, rp3 ea, rp3 ea, r2 ea, rp3 ea, rp3 ea, rp3 ea, rp3 ea, rp3 ea, rp3 * * * * * * * * offaw aniw oriw gtiw ltiw neiw eqiw oniw offiw eadd dadd dadc daddnc esub dsub dsbb dsubnb dan dor dxr instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 offset data 11011000 offset 010000r 1 r 0 110001p 1 p 0 1101 01p 1 p 2 1010 01p 1 p 2 011000r 1 r 0 111001p 1 p 0 1111 01p 1 p 2 1011 01p 1 p 2 100011p 1 p 0 1001 01p 1 p 2 100101p 1 p 0 instruction code zero no borrow borrow no zero zero no zero zero no carry no borrow working register arithmetic instructions 16-bit arithmetic instructions m pd78c10a(a), 78c11a(a), 78c12a(a) 32 01110100 01001000 010000r 1 r 2 00100000 00p 1 p 0 0010 10101000 010100r 1 r 2 00110000 00p 1 p 0 0011 10101001 01100001 01001000 11 11 11 11 11 11 32 59 4 16 7 7 4 16 7 7 4 8 8 8 ea - rp3 - 1 ea - rp3 ea - rp3 ea - rp3 ea rp3 ea rp3 ea ? a r2 ea ? ea ? r2, r2 ? remainder r2 ? r2 + 1 (v.wa) ? (v.wa) + 1 rp ? rp + 1 ea ? ea + 1 r2 ? r2 - 1 (v.wa) ? (v.wa) - 1 rp ? rp - 1 ea ? ea - 1 decimal adjust accumulator cy ? 1 cy ? 0 a ? a + 1 ea, rp3 ea, rp3 ea, rp3 ea, rp3 ea, rp3 ea, rp3 r2 r2 r2 wa rp ea r2 wa rp ea * * dgt dlt dne deq don doff mul div inr inrw inx dcr dcrw dcx daa stc clc nega instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 101011p 1 p 0 1011 01p 1 p 0 1110 01p 1 p 0 1111 01p 1 p 0 1100 01p 1 p 0 1101 01p 1 p 0 001011r 1 r 0 0011 11r 1 r 0 offset offset 00101011 00101010 00111010 instruction code no borrow borrow no zero zero no zero zero carry carry borrow borrow 16-bit arithmetic instructions multiply /divide instructions increment/decrement instructions other arithmetic instructions m pd78c10a(a), 78c11a(a), 78c12a(a) 33 01001000 01010100 00100001 11 000000 0100111 0 01001000 01000000 01001000 01111 000 17 17 8 8 8 8 8 8 8 8 8 8 10 4 10 10 8 16 17 13 rotate left digit rotate right digit r2 m+1 ? r2 m , r2 0 ? cy, cy ? r2 7 r2 m - 1 ? r2 m , r2 7 ? cy, cy ? r2 0 r2 m+1 ? r2 m , r2 0 ? 0, cy ? r2 7 r2 m - 1 ? r2 m , r2 7 ? 0, cy ? r2 0 r2 m+1 ? r2 m , r2 0 ? 0, cy ? r2 7 r2 m - 1 ? r2 m , r2 7 ? 0, cy ? r2 0 ea n+1 ? ea n , ea 0 ? cy, cy ? ea 15 ea n - 1 ? ea n , ea 15 ? cy, cy ? ea 0 ea n+1 ? ea n , ea 0 ? 0, cy ? ea 15 ea n - 1 ? ea n , ea 15 ? 0, cy ? ea 0 pc ? word pc h ? b, pc l ? c pc ? pc + 1 + jdisp1 pc ? pc + 2 + jdisp pc ? ea r2 r2 r2 r2 r2 r2 ea ea ea ea word word word word word * * * * rld rrd rll rlr sll slr sllc slrc drll drlr dsll dslr jmp jb jr jre jea call calb calf instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 00111000 0000 1001 0000 01r 1 r 0 0000 00r 1 r 0 001001r 1 r 0 0000 00r 1 r 0 000001r 1 r 0 0000 00r 1 r 0 10110100 0000 0000 10100100 0000 0000 low adrs jdisp 00101000 low adrs 00101001 fa instruction code carry carry rotation/shift instructions jump instructions call instructions high adrs high adrs (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l pc ? word, sp ? sp - 2 (sp - 1) ? (pc + 2) h , (sp - 2) ? (pc + 2) l pc h ? b, pc l ? c, sp ? sp - 2 (sp - 1) ? (pc + 2) h , (sp - 2) ? (pc + 2) l pc 15-11 ? 00001, pc 10-0 ? fa, sp ? sp - 2 jdisp 1 m pd78c10a(a), 78c11a(a), 78c12a(a) 34 100 00000 01110010 10111000 0000 1001 01100010 01011b 2 b 1 b 0 01001000 00000000 10101010 10111010 01001000 01001000 16 16 10 10 13 10 8 8 8 8 4 4 4 12 12 skip if (v.wa) bit = 1 skip if f = 1 skip if f = 0 skip if irf = 1, then reset irf no operation enable interrupt disable interrupt set halt mode set stop mode word bit, wa f f irf irf * calt softi ret rets reti bit sk skn skit sknit nop ei di hlt stop instruction group skip condition mnemonic operand states operation b1 b2 b3 b4 offset 00001f 2 f 1 f 0 0001 1f 2 f 1 f 0 010i 4 i 3 i 2 i 1 i 0 011i 4 i 3 i 2 i 1 i 0 00111011 10111011 instruction code (v.wa)bit = 1 f = 1 f = 0 irf = 1 irf = 0 call instructions return instructions skip instructions cpu control instructions ta (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l pc l ? (128 + 2ta), pc h ? (129 + 2ta), sp ? sp - 2 (sp - 1) ? psw, (sp - 2) ? (pc + 1) h , (sp - 3) ? (pc + 1) l , pc ? 0060h, sp ? sp - 3 pc l ? (sp), pc h ? (sp + 1) sp ? sp + 2 pc l ? (sp), pc h ? (sp + 1), psw ? (sp + 2), sp ? sp + 3 pc l ? (sp), pc h ? (sp + 1), sp ? sp + 2 pc ? pc + n skip if irf = 0 reset irf, if irf = 1 unconditional skip notes 1. b2 (data) indicates the case when rpa2 = d + byte or h + byte. notes 2. b3 (data) indicates the case when rpa3 = d + byte or h + byte. notes 3. in the "states" column, the value on the right side of the slash indicates the case when rpa2 or rpa3 = d + byte, h + a, h + b, h + ea, or h + byte. remark for the skip condition, the idle states differ from the execution states and are as follows. 1-byte instructions 2-byte instructions with* 2-byte instructions : 4 states : 7 states : 8 states 3-byte instructions with * 3-byte instructions 4-byte instructions : 10 states : 11 states : 14 states m pd78c10a(a), 78c11a(a), 78c12a(a) 35 5. mode register list ma mb mcc mc mm mf tmm etmm eom sml smh mkl mkh anm zcm read/ write w w w w w w r/w w r/w w r/w r/w r/w w function bit-wise specification of input or output for port a bit-wise specification of input or output for port b bit-wise specification of port or control mode for port c bit-wise specification of input or output for port c in port mode specification of port or expansion mode for port d and port f bit-wise specification of input or output for port f in port mode specification of timer operation mode specification of timer/event counters op- eration mode control of output level for co0 and co1 specification of serial interfaces operation mode specification of interrupt request enable/ disable state specification of a/d converters operation mode specification of zero-cross detection circuit operation mode register mode a register mode b register mode control c register mode c register memory mapping reg- ister mode f register timer mode register timer/event counter mode register timer/event counter output mode register serial mode register interrupt mask register a/d channel mode reg- ister zero-cross mode regis- ter h m pd78c10a(a), 78c11a(a), 78c12a(a) 36 6. electrical specifications absolute maximum ratings (t a = 25 c) caution if the absolute maximum rating for any of the above parameters is exceeded even momentarily, it may adversely affect the quality of this product. in other words, these absolute maximum ratings have been set to prevent physical damage to the product. do not use the product in such a way as to exceed any of these ratings. symbol v dd av dd av ss v i v o i ol i oh v aref t a t stg conditions each output pin total (all pins) each output pin total (all pins) ratings C0.5 to +7.0 av ss to v dd + 0.5 C0.5 to +0.5 C0.5 to v dd + 0.5 C0.5 to v dd + 0.5 4.0 100 C2.0 C50 C0.5 to av dd + 0.3 C40 to +85 C65 to +150 unit v v v v v ma ma ma ma v c c parameter power supply voltage input voltage output voltage output current, low output current, high a/d converter reference input voltage operating ambient temperature storage temperature h m pd78c10a(a), 78c11a(a), 78c12a(a) 37 oscillation characteristics (t a = C40 to +85 c, v dd = av dd + 5.0 v 10%, v ss = av ss = 0 v, v dd C 0.8 v < av dd < v dd , 3.4 v < v aref < av dd ) cautions 1. the oscillation circuit should be placed as close to the x1 and x2 pins as possible. 2. do not place other signal lines in the shaded area. note when using a crystal resonator, the following external capacitance values are recommended. c1 = c2 = 10 pf capacitance (t a = 25 c, v dd = v ss = 0 v) resonator ceramic resona- tor or crystal resonator (note) external clock unit mhz mhz mhz mhz ns ns max. 15 15 15 15 20 250 min. 4 5.8 4 5.8 0 20 condition a/d converter not used a/d converter used a/d converter not used a/d converter used parameter oscillation frequency (f xx ) x1 input frequency (f x ) x1 input rise, fall time (t r , t f ) x1 input low-level and high-level width (t ? l , t ? h ) recommended circuit unit pf pf pf max. 10 20 20 typ. min. symbol c i c o c io parameter input capacitance output capacitance i/o capacitance condition f c = 1 mhz unmeasured pins returned to 0 v. x1 x2 hcmos inverter x1 x2 c1 c2 m pd78c10a(a), 78c11a(a), 78c12a(a) 38 dc characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v +10 %, v ss = av ss = 0 v) caution for details of the hardware stop mode, see the 87ad series m pd78c18 users manual. notes 1. assumes self-bias is set from the zcm register 2. when control mode is set from the mcc register, assumes self-bias is set from the zcm register 3. assumes self-bias is not set 4. m pd78c11a(a) and 78c12a(a) only unit v v v v v v v m a m a m a m a ma m a ma ma v m a m a k w max. 0.8 0.2v dd v dd v dd 0.45 200 10 1 10 1.3 20 25 13 15 50 75 typ. 0.5 10 13 7 1 10 27 min. 0 0 2.2 0.8v dd v dd - 1.0 v dd - 0.5 2.5 17 parameter input voltage, low input voltage, high output voltage, low output voltage, high input current input leakage current output leakage current av dd supply current v dd supply current data retention voltage data retention current pull-up resistor (note 4) condition all except reset, stop, nmi, sck, int1, ti, and an4 to an7 reset, stop, nmi, sck, int1, ti, and an4 to an7 all except reset, stop, nmi, sck, int1, ti, an4 to an7, x1, and x2 reset, stop, nmi, sck, int1, ti, an4 to an7, x1, and x2 i ol = 2.0 ma i oh = C1.0 ma i oh = C100 m a int1 (note 1) , ti (pc3) (note 2) ; 0 v v i v dd all except int1, ti (pc3), and an0 to an7; 0 v v i v dd an7-0; 0 v v i v dd 0 v v o v dd operation mode; f xx = 15 mhz stop mode operation mode; f xx = 15 mhz halt mode; f xx = 15 mhz hardware/software stop mode hardware/soft- ware stop mode (note 3) ports a, b, and c v dddr = 2.5 v v dddr = 5 v 10 % 3.5 v v dd 5.5 v, v i = 0 v symbol v il1 v il2 v ih1 v ih2 v ol v oh i i i li i lo ai dd1 ai dd2 i dd1 i dd2 v dddr i dddr r l m pd78c10a(a), 78c11a(a), 78c12a(a) 39 ac characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10%, v ss = av ss = 0 v) read/write operation: unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter x1 input cycle time address setup time (to ale ) address hold time (to ale ) address to rd delay time rd to address float time address to data input time ale to data input time rd to data input time ale to rd delay time data hold time (to rd - ) rd - to ale - delay time rd width low ale width high m1 setup time (to ale ) m1 hold time (to ale ) io/m setup time (to ale ) io/m hold time (to ale ) address to wr delay time ale to data output time wr to data output time ale to wr delay time data setup time (to wr - ) data hold time (to wr - ) wr - to ale - delay time wr width low max. 250 20 250 135 120 180 100 min. 66 30 35 100 15 0 80 215 415 90 30 35 30 35 100 15 165 60 80 215 condition f xx = 15 mhz, c l = 100 pf c l = 100 pf f xx = 15 mhz, c l = 100 pf c l = 100 pf f xx = 15 mhz, c l = 100 pf data read f xx = 15 mhz, c l = 100 pf opcode fetch f xx = 15 mhz, c l = 100 pf f xx = 15 mhz, c l = 100 pf f xx = 15 mhz f xx = 15 mhz, c l = 100 pf c l = 100 pf f xx = 15 mhz, c l = 100 pf symbol t cyc t al t la t ar t afr t ad t ldr t rd t lr t rdh t rl t rr t ll t ml t lm t il t li t aw t ldw t wd t lw t dw t wdh t wl t ww m pd78c10a(a), 78c11a(a), 78c12a(a) 40 serial operation: notes 1. when in asynchronous mode with x1 clock rate, synchronous mode, or i/o interface mode 2. when in asynchronous mode with x16 or x64 clock rate remark the values shown in the above table are when f xx = 15 mhz and c l = 100 pf. zero-cross characteristics: other operation: unit ns ns m s ns ns ns ns ns ns ns ns ns parameter sck cycle time sck width low sck width high r x d setup time (to sck - ) r x d hold time (to sck - ) sck to t x d delay time max. 210 min. 800 400 1.6 335 160 700 335 160 700 80 80 condition note 1 sck input note 2 sck output note 1 sck input note 2 sck output note 1 sck input note 2 sck output note 1 note 1 note 1 symbol t cyk t kkl t kkh t rxk t krx t ktx unit vac p-p mv khz parameter zero-cross detection input zero-cross accuracy zero-cross detection input fre- quency max. 1.8 135 1 min. 1 0.05 condition ac-coupled 60-hz sine wave symbol v zx a zx f zx unit t cyc t cyc t cyc m s t cyc t cyc t cyc m s parameter ti width high, low ci width high, low nmi width high, low int1 width high, low int2 width high, low an4 to an7 width high, low reset width high, low max. min. 6 6 48 10 36 36 36 10 condition event counter mode pulse-width measurement mode symbol t tih , t til t ci1h , t ci1l t ci2h , t ci2l t nih , t nil t i1h , t i1l t i2h , t i2l t anh , t anl t rsh , t rsl m pd78c10a(a), 78c11a(a), 78c12a(a) 41 test points v dd - 1.0 v 0.45 v 2.2 v 0.8 v 2.2 v 0.8 v a/d converter characteristics (t a = C40 to +85 c, v dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C 0.5 v av dd v dd , 3.4 v v aref av dd ) note quantizing error ( 1/2 lsb) is not included. ac timing test points unit bits fsr fsr fsr t cyc t cyc t cyc t cyc v m w v ma ma ma m a max. 0.8 % 0.6 % 0.4 % v aref + 0.3 av dd 3.0 1.5 1.3 20 typ. 50 1.5 0.7 0.5 10 min. 8 576 432 96 72 C0.3 3.4 symbol t conv t samp v ian r an v aref i aref1 i aref2 ai dd1 ai dd2 parameter resolution absolute accuracy (note) conversion time sampling time analog input voltage analog input impedance reference voltage v aref current av dd supply current condition 3.4 v v aref av dd , 66 ns t cyc 170 ns 4.0 v aref av dd , 66 ns t cyc 170 ns t a = C10 to +70 c, 4.0 v aref av dd , 66 ns t cyc 170 ns 66 ns t cyc 110 ns 110 ns t cyc 170 ns 66 ns t cyc 110 ns 110 ns t cyc 170 ns an0 to an7 (including unused pins) operation mode stop mode operation mode; f xx = 15 mhz stop mode h m pd78c10a(a), 78c11a(a), 78c12a(a) 42 calculation formulas for ac characteristics dependent on t cyc notes 1. when in asynchronous mode with x1 clock rate, synchronous mode, or i/o interface mode 2. when in asynchronous mode with x16 or x64 clock rate cautions 1. t = t cyc = 1/f xx 2. the items not included in this list are independent of oscillation frequency (f xx ). unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min/max. min. min. min. max. max. max. min. min. min. min. min. min. min. min. min. max. min. min. min. min. min. min. min. min. symbol t al t la t ar t ad t ldr t rd t lr t rl t rr t ll t ml t lm t il t li t aw t ldw t lw t dw t wdh t wl t ww t cyk t kkl t kkh calculation formula 2t C 100 t C 30 3t C 100 7t C 220 5t C 200 4t C 150 t C 50 2t C 50 4t C 50 (data read) 7 t C 50 (opcode fetch) 2t C 40 2t C 100 t C 30 2t C 100 t C 30 3t C 100 t + 110 t C 50 4t C 100 2t C 70 2t C 50 4t C 50 12t (sck input) (note 1) /6t (sck input) (note 2) 24t (sck output) 5t + 5 (sck input) (note 1) /2.5t + 5 (sck input) (note 2) 12t C 100 (sck output) 5t + 5 (sck input) (note 1) /2.5t + 5 (sck input) (note 2) 12t C 100 (sck output) m pd78c10a(a), 78c11a(a), 78c12a(a) 43 timing waveforms read operation notes 1. the m1 signal is output to the mode1 pin during the first opcode fetch cycle when the mode1 pin is pulled up. 2. the io/m signal is output to the mode0 pin during the sr to sr2 register read cycle when the mode0 pin is pulled up. write operation notes 3. the io/m signal is output to the mode0 pin during the sr to sr2 register write cycle when the mode0 pin is pulled up. t cyc address (high - order) address (low - order) read data t ad t ldr t rdh t la t lr t ll t al t afr t rd t rr t rl t ar t ml t lm t il t li x1 pf7-0 pd7-0 ale rd mode1 (m1) (note 1) mode0 (io/m) (note 2) address (high - order) write data t ldw t la t wd t ll t al t aw t lw t li t il t dw t ww t wl t wdh x1 pf7-0 pd7-0 ale wr mode0 (io/m) (note 3) address (low - order) m pd78c10a(a), 78c11a(a), 78c12a(a) 44 serial operation timer input timing timer/event counter input timing event counter mode pulse-width measurement mode t tih t til ti t ci1h t ci1l ci t ci2h t ci2l ci t cyk t kkl t ktx t rxk t kkh t krx sck t x d r x d m pd78c10a(a), 78c11a(a), 78c12a(a) 45 interrupt input timing reset input timing external clock timing t rsh t rsl reset 0.8v dd 0.2v dd t nih t nil t i1l t i1h nmi int1 t i2h t i2l int2 t h f t l t cyc f t f t r 0.8v dd 0.8v x1 m pd78c10a(a), 78c11a(a), 78c12a(a) 46 data memory stop mode low-voltage data retention characteristic (t a = C40 to +85 c) data retention timing unit v m a m a m s m s m s max. 5.5 15 50 typ. 1 10 min. 2.5 200 12t + 0.5 12t + 0.5 parameter data retention power sup- ply voltage data retention power sup- ply current v dd rise, fall time stop setup time (to v dd ) stop hold time (from v dd ) condition v dddr = 2.5 v v dddr = 5 v 10 % symbol v dddr i dddr t rvd , t fvd t sstvd t hvdst h 90 % 10 % v dddr t fvd t sstvd t rvd t hvdst v ih2 v il2 stop v dd m pd78c10a(a), 78c11a(a), 78c12a(a) 47 7. characteristic curves (reference values) 20 15 10 5 0 30 20 10 0 5 10 15 4.5 5 5.5 6 i dd2 (typ.) i dd1 (typ.) i dd1 , i dd2 vs v dd i dd1 , i dd2 vs f xx (t a = 25 c, f xx = 15 mhz) (t a = 25 c, v dd = 5 v) i dd1 (typ.) i dd2 (typ.) v dd power supply current i dd1 , i dd2 (ma) v dd power supply current i dd1 , i dd2 (ma) power supply voltage v dd (v) oscillation frequency f xx (mhz) m pd78c10a(a), 78c11a(a), 78c12a(a) 48 0 0.5 1.0 1.5 2.0 2.5 0.1 0.2 0.3 0.4 0.5 i ol vs v ol (t a = 25 c, v dd = 5 v) (t a = 25 c, v dd = 5 v) output current, low i ol (ma) output current, high i oh (ma) typ. output voltage, low v ol (v) 0 -0.5 -1.0 -1.5 0.1 0.2 0.3 0.4 0.5 power supply voltage - output voltage, high v dd - v oh (v) typ. i oh vs v oh m pd78c10a(a), 78c11a(a), 78c12a(a) 49 i dddr vs v dddr data retention supply voltage v dddr (v) (t a = 25 c) data retention supply current i dddr ( a) typ. m 10 8 6 4 2 02 3 4 5 6 m pd78c10a(a), 78c11a(a), 78c12a(a) 50 8. package drawings h i m c p a 64 132 33 m n j k s w x p64gq-100-36 item millimeters inches a c h i j k m n p s w 1.27 (t.p.) 0.25 16.5 0.100 (t.p.) 0.050 (t.p.) 0.010 0.157 1.634 note x 4.0 0.750 each lead centerline is located within 0.25 mm (0.010 inch) of its true position (t.p.) at maxi- mum material condition. 0.142 0.043 0.020 24.13 0.950 0.010 0.25 2.54 (t.p.) +0.004 ?.005 +0.011 ?.006 +0.012 ?.008 +0.004 ?.005 41.5 +0.3 ?.2 0.50 +0.10 1.1 +0.25 ?.15 +0.10 ?.05 +0.3 3.6 +0.1 +1.05 19.05 +1.05 0.650 +0.004 ?.003 +0.013 ?.012 +0.042 +0.042 64 pin plastic quip m pd78c10a(a), 78c11a(a), 78c12a(a) 51 n a m f b 51 52 32 k l 64 pin plastic qfp (14 20) 64 1 20 19 33 p d c detail of lead end s q 55 g m i h j p64gf-100-3b8,3be,3br-1 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 1.0 0.40 0.10 0.20 20.0 0.2 0.929 0.016 0.039 0.039 0.008 0.039 (t.p.) 0.795 note m n 0.12 0.15 1.8 0.2 1.0 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 0.071 0.016 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009 m pd78c10a(a), 78c11a(a), 78c12a(a) 52 m pd78c10a(a), 78c11a(a), 78c12a(a) 53 p68l-50a1-2 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. +0.007 ?.006 a b c d e f g h i j k m n p q t u 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 min. 3.4 1.27 (t.p.) 0.40 1.0 0.12 23.12 0.20 0.15 r 0.8 0.20 +0.10 ?.05 0.992 0.008 0.953 0.953 0.992 0.008 0.076 0.024 0.173 0.110 0.035 min. 0.134 0.050 (t.p.) 0.016 0.005 0.910 0.006 r 0.031 0.008 +0.009 ?.008 +0.009 ?.008 +0.004 ?.005 +0.004 ?.002 +0.009 ?.008 n k m q a u 68 b d c 1 f e t p m g h ij 68 pin plastic qfj ( 950 mil) m pd78c10a(a), 78c11a(a), 78c12a(a) 54 9. recommended soldering conditions use the following recommended soldering conditions when solder-mounting the m pd78c10a(a), 78c11a(a), or 78c12a(a). for details of recommended soldering conditions, see the semiconductor device mounting technology manual (iei-1207) in the information materials. consult your local nec sales representative concerning soldering methods and conditions other than those recommended. table 9-1. soldering conditions for surface mounting types (1) m pd78c10agf(a)-3be : 64-pin plastic qfp (14 x 20 mm) m pd78c11agf(a)-xxx-3be : 64-pin plastic qfp (14 x 20 mm) caution do not use different soldering methods together (except when one method is pin partial heating). (2) m pd78c12agf(a)-xxx-3be: 64-pin plastic qfp (14 x 20 mm) caution do not use different soldering methods together (except when one method is pin partial heating). soldering method infrared ray reflow vps wave soldering pin partial heating symbol ir35-00-2 vp15-00-2 ws60-00-1 - soldering conditions package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of operations: 2 max. m pd78c10a(a), 78c11a(a), 78c12a(a) 55 (3) m pd78c10al(a) : 68-pin plastic qfj (950 x 950 mil) m pd78c11al(a)-xxx : 68-pin plastic qfj (950 x 950 mil) m pd78c12al(a)-xxx : 68-pin plastic qfj (950 x 950 mil) caution do not use different soldering methods together (except when one method is pin partial heating). table 9-2. soldering conditions for through hole types m pd78c10agq(a)-36 : 64-pin plastic quip m pd78c11agq(a)-xxx-36 : 64-pin plastic quip m pd78c12agq(a)-xxx-36 : 64-pin plastic quip caution perform wave soldering on pins only and do not allow the solder to make direct contact with the body. soldering method infrared ray reflow vps pin partial heating symbol ir30-00-1 vp15-00-1 - soldering conditions package peak temperature: 230 c, time: 3 seconds max. (210 c min.), number of operations: 1 package peak temperature: 215 c, time: 40 seconds max. (200 c min.), number of operations: 1 pin temperature: 300 c max., time: 3 seconds max. (per device side) soldering method wave soldering (pins only) pin partial heating soldering conditions solder bath temperature: 260 c max., time: 10 seconds max. pin temperature: 300 c max., time: 3 seconds max. (per one pin) m pd78c10a(a), 78c11a(a), 78c12a(a) 56 appendix development tools the following development tools are available for system development using the m pd78c10a(a), 78c11a(a), and 78c12a(a). language processor prom programming tools note this software does not include a task swapping function, although a task swapping function is provided in ver.5.00/5.00a. remark operation of the assembler and pg-1500 controller is guaranteed only on the host machines and operating systems described above. operating system ms-dos tm ver.2.11 to ver.5.00a (note) pc dos tm (ver.3.1) 87ad series relocatable assembler (ra87) this program converts symbolic (mnemonic) programs into object code that is executable by microcomputers. in addition, it includes functions for automatic generation of symbol tables and optimum processing of branch instructions. host machine pc-9800 series ibm pc/at tm pg-1500 pa-78cp14gq pa-78cp14gq pg-1500 controller host machine pc-9800 series ibm pc/at this is a prom programmer that, when connected to an auxiliary board and a (separately sold) programmer adapter, can be operated as a stand-alone device or from a host machine for prom programming of single-chip microcomputers that have on-chip prom. it can also be used to program prom devices in sizes ranging from 256 kbits to 4 mbits. this is the prom programmer adapter for the m pd78cp14(a), which is connected to the pg-1500. m pd78cp14g(a)-36, this controller controls the pg-1500 from a host machine that is connected to the pg-1500 via a serial or parallel interface. hard- ware soft- ware medium 3.5-inch 2hd 5-inch 2hd 3.5-inch 2hc 5-inch 2hc medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc operating system ms-dos ver.2.11 to ver.5.00a (note) pc dos (ver.3.1) ordering code (product name) m s5a13pg1500 m s5a10pg1500 m s7b10pg1500 ordering code (product name) m s5a13ra87 m s5a10ra87 m s7b13ra87 m s7b10ra87 h m pd78c10a(a), 78c11a(a), 78c12a(a) 57 debugging tools an in-circuit emulator (ie-78c11-m) is available as a program debugging tool for the m pd78c10a(a), 78c11a(a), and 78c12a(a). the system configuration is shown below. remark operation of the ie controller is guaranteed only on the host machines and operating systems described above. ie-78c11-m ie-78c11-m control program (ie controller) host machine pc-9800 series ibm pc/at hard- ware soft- ware the ie-78c11-m is an in-circuit emulator that supports the 87ad series. it enables efficient debugging when connected to a host machine. this controller controls the ie-78c11-m from a host machine that is connected to the ie-78c11-m via the rs-232-c. ordering code (product name) m s5a13ie78c11 m s5a10ie78c11 m s7b10ie78c11 medium 3.5-inch 2hd 5-inch 2hd 5-inch 2hc operating system ms-dos ver.2.11 to ver.3.30d pc dos (ver.3.1) m pd78c10a(a), 78c11a(a), 78c12a(a) 58 [memo] m pd78c10a(a), 78c11a(a), 78c12a(a) 59 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function. m pd78c10a(a), 78c11a(a), 78c12a(a) 1 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. license not needed : m pd78c10agf(a)-3be, 78c10agq(a)-36, 78c10al(a) the customer must : m pd78c11agf(a)-xxx-3be, 78c11agq(a)-xxx-36, 78c11al(a)-xxx, judge the need for m pd78c12agf(a)-xxx-3be, 78c12agq(a)-xxx-36, 78c12al(a)-xxx license the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. m4 94.11 |
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