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MP1499 high efficiency 5a peak, 16v, 500khz synchronous step down converter MP1499 rev. 1.0 www.monolithicpower.com 1 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the MP1499 is a high frequency synchronous rectified step-down switch mode converter with built in internal power mosfets. it offers a very compact solution to achieve 5a peak output current over a wide input supply range with excellent load and line regulation. the MP1499 has synchronous mode operation for higher efficiency over output current load range. current mode operation provides fast transient response and eases loop stabilization. full protection features include over current protection and thermal shut down. the MP1499 requires a minimum number of readily available standard external components and is available in a space saving 10-pin qfn (2x3mm) package. features ? wide 4.5v to 16v operating input range ? 70m ? /25m ? low r ds(on) internal power mosfets ? proprietary switching loss reduction technique ? fixed 500khz switching frequency ? sync from 200khz to 2mhz external clock ? aam power save mode ? external soft start ? ocp protection and hiccup ? thermal shutdown ? output adjustable from 0.8v ? available in a qfn10 (2x3mm) package applications ? digital set top boxes ? flat panel television and monitors ? distributed power systems a ll mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application bst in sw en/sync fb gnd nc MP1499 94 8 1 6, 7 5 3 10 v in v out 3.3v/5a c2 47 r1 40.2k r8 33k r2 r5 10 13k l1 3.3 c4 100nf c1 22 r3 100k ss c5 22nf c6 vcc 2 output current(a) efficiency vs. output current v out =3.3v 50 55 60 65 70 75 80 85 90 95 100 0.01 0.10 1.00 10.00 v in =16v v in =12v v in =5v
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 2 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number* package top marking MP1499gd qfn10 (2x3mm) adh * for tape & reel, add suffix ?z (e.g.MP1499gd?z); package reference 3 2 5 4 8 9 10 6 7 fb sw in ss nc bst en/sync vcc gnd gnd 1 top view absolute maxi mum ratings (1) v in ................................................. ?0.3v to 17v v sw ...................................................................... -0.3v (-5v for <10ns) to 17v(19v for <10ns) v bst ........................................................ v sw +6v all other pins ............................ ?0.3v to 6.5 v (2) continuous power dissipation (t a = +25c) (3) ........................................................... 1.92w junction temperature ............................... 150 ? c lead temperature .................................... 260 ? c storage temperature ................. -65 ? c to 150 ? c recommended operating conditions (4) supply voltage v in ........................... 4.5v to 16v output voltage v out ................ 0.807v to vin-3v operating junction temp. (t j ). -40c to +125c thermal resistance (5) ja jc qfn10 (2x3mm) ..................... 65 ...... 13 ... ? c/w notes: 1) exceeding these ratings may damage the device. 2) about the details of en pin?s abs max rating, please refer to page 10, en/sync control section. 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 4) the device is not guaranteed to function outside of its operating conditions. 5) measured on jesd51-7, 4-layer pcb.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 3 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v in = 12v, t a = 25 ? c, unless otherwise noted. parameter symbol condition min typ max units supply current supply current (shutdown) i in v en = 0v 1 a supply current (quiescent) i q v en = 2v, v fb = 1v 0.6 1 ma mosfet hs switch on resistance hs rds-on v bst-sw =5v 70 m ? ls switch on resistance ls rds-on v cc =5v 25 m ? switch leakage sw lkg v en = 0v, v sw =12v 1 a mosfet current limit ( 6 ) i limit 40% duty cycle 7 9 a oscillator and timer oscillator frequency f sw v fb =750mv 430 500 580 khz maximum duty cycle d max v fb =700mv 90 95 % minimum on time ( 6 ) t on min 60 ns sync frequency range f sync 0.2 2 mhz reference and soft start feedback voltage v fb t a =25c 791 807 823 mv -40c MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 4 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical characteristics v in = 12v, v out = 3.3v, l = 3.3h, t a = 25c, unless otherwise noted. input voltage (v) output current (a) line regulation v in =5v-16v current limit vs. duty cycle load regulation enabled supply current vs. input voltage v fb =1v input voltage (v)) 200 300 400 500 600 700 800 900 1000 4 6 8 1012141618 switching frequency vs. ambient temperature disabled supply current vs. input voltage v en =0v switching frequency (khz) disabled supply current (na) input voltage (v) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 400 425 450 475 500 525 550 -40 -20 0 20 40 60 80 100 120 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 012345 v in =12v v in =5v v in =16v -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 5 6 7 8 9 10111213141516 i out =5a i out =2.5a 3 5 7 9 11 13 15 10 20 30 40 50 60 70 80 current limit (a)
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 5 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) performance waveforms are tested on the evaluation board of the design example section. v in = 12v, v out = 3.3v, l = 3.3h, t a = 25c, unless otherwise noted. output current (a) output current (a) output current (a) case temperature rise vs. output current v in =12v, i out =0a-5a, 4 layers pcb, size: 6.5cmx6.5cm output current (a) output current (a) output current (a) 50 55 60 65 70 75 80 85 90 95 100 0.0 1.0 2.0 3.0 4.0 5.0 v in =16v v in =12v v in =5v 50 55 60 65 70 75 80 85 90 95 100 0.0 1.0 2.0 3.0 4.0 5.0 v in =5v v in =12v v in =16v 50 55 60 65 70 75 80 85 90 95 100 0.0 1.0 2.0 3.0 4.0 5.0 v in =5v v in =12v v in =16v 50 55 60 65 70 75 80 85 90 95 100 0.0 1.0 2.0 3.0 4.0 5.0 v in =5v v in =12v v in =16v 50 55 60 65 70 75 80 85 90 95 100 0.0 1.0 2.0 3.0 4.0 5.0 v in =6.5v v in =12v v in =16v 0 10 20 30 40 50 60 012345 v out =1.2v v out =5v v out =3.3v output current (a) output voltage (v) output current (a) case temperature rise vs. output current v in =5v, i out =0a-5a, 4 layers pcb, size: 6.5cmx6.5cm 0 10 20 30 40 50 60 70 80 012345 v out =3.3v v out =1.2v 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -30 -40 -20-10 0 10 20 30 40 50 60 70 output current (a) 0 1 2 3 4 5 6 v in =5v v in =12v 0 1 2 3 4 5 6 v out =5v v out =3.3v v out =1.8v
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 6 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) performance waveforms are tested on the evaluation board of the design example section. v in = 12v, v out = 3.3v, l = 3.3h, t a = 25c, unless otherwise noted. short entry i out =0a short recovery i out =0a startup through enable i out =0a startup through enable i out =5a shutdown through enable i out =0a shutdown through enable i out =5a startup through input voltage i out =0a v in 10v/div. v sw 5v/div. v out 2v/div. iinductor 1a/div. v in 10v/div. v sw 5v/div. v out 2v/div. iinductor 5a/div. v in 10v/div. v out 2v/div. v sw 5v/div. i l 10a/div. v en 5v/div. v out 2v/div. v sw 5v/div. iinductor 1a/div. v en 5v/div. v out 2v/div. v sw 5v/div. iinductor 5a/div. v en 5v/div. v out 2v/div. v sw 5v/div. iinductor 1a/div. v en 5v/div. v out 2v/div. v sw 5v/div. iinductor 5a/div. v in 10v/div. v out 2v/div. v sw 5v/div. i l 10a/div. startup through input voltage i out =5a output current (a) -40-30-20-10 0 10 20 30 40 50 60 70 0 1 2 3 4 5 6 v out =3.3v v out =1.8v
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 7 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) performance waveforms are tested on the evaluation board of the design example section. v in = 12v, v out = 3.3v, l = 3.3h, t a = 25c, unless otherwise noted. shutdown through input voltage i out =0a shutdown through input voltage i out =5a input / output ripple i out =5a load transient reponse i out =2.5a-5a v in 10v/div. v sw 5v/div. v out 2v/div. iinductor 1a/div. v in 10v/div. v sw 5v/div. v out 2v/div. iinductor 5a/div. v in ac coupled 200mv/div. v sw 10v/div. v out ac coupled 20mv/div. v out ac coupled 100mv/div. i l 5a/div. i out 2a/div.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 8 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions package pin # name description 1 fb feedback. an external resistor divider from the output to gnd, tapped to the fb pin, sets the output voltage. to prevent current limit run away during a short circuit fault condition the frequency fold-back comparat or lowers the oscillator frequency when the fb voltage is below 400mv. it is recommended to place the resistor divider as close to fb pin as possible. vias should be avoided on the fb traces. 2 vcc internal 5v ldo output. the driver and cont rol circuits are powered from this voltage. decouple with 0.1 f-0.22 f cap. and the capacitance should be no more than 0.22 f. 3 en/sy nc en=high to enable the MP1499. external clock can be applied to en pin for changing switching frequency. for automatic start-up, connect en pin to vin with 100k ? resistor. 4 bst bootstrap. a capacitor connected between sw and bst pins is required to form a floating supply across the high-side switch driver. 5 nc no connection internal. this pin can connect to gnd. 6, 7 gnd system ground. this pin is the referenc e ground of the regulated output voltage. for this reason care must be taken in pcb layout. suggested to be connected to gnd with copper and vias. 8 sw switch output. connect this pin to the induct or and bootstrap capacitor. this pin is driven up to the vin voltage by the high-side switch during the on-time of the pwm duty cycle. the inductor current drives the sw pin negativ e during the off-time. the on-resistance of the low-side switch and the internal body diode fixes the negative voltage. use wide pcb traces and multiple vias to make the connection. 9 in supply voltage. the in pin supplies power for internal mosfet and regulator. the MP1499 operates from a +4.5v to +16v input rail. low esr, and low inductance capacitor c1 is needed to decouple the input rail. place the input capacitor very close to this pin and connect it with wide pcb traces and multiple vias to make the connection. 10 ss soft start. connect on external capacitor to prog ram the soft start time for the switch mode regulator.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 9 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. functional block diagram 50pf 1meg 6.5v bst rsen in oscillator vcc regulator boost regulator vcc currrent sense amplifer vcc current limit comparator error amplifier reference en/sync ss + + - + - + - fb sw gnd ls driver hs driver comparator on time control logic control 1pf 400k figure 1?functional block diagram
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 10 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation the MP1499 is a high frequency synchronous rectified step-down switch mode converter with built in internal power mosfets. it offers a very compact solution to achieve 5a peak output current over a wide input supply range with excellent load and line regulation. the MP1499 operates in a fixed frequency, peak current control mode to regulate the output voltage. a pwm cycle is initiated by the internal clock. the integrated high-side power mosfet is turned on and remains on until its current reaches the value set by the comp voltage. when the power switch is off, it remains off until the next clock cycle starts. if, in 90% of one pwm period, the current in the power mosfet does not reach the comp set current value, the power mosfet will be forced to turn off. internal regulator most of the internal circuitries are powered from the 5v internal regulator. this regulator takes the vin input and operates in the full vin range. when vin is greater than 5.0v, the output of the regulator is in full regulation. when vin is lower than 5.0v, the output decreases, a 0.1uf ceramic capacitor for decoupling purpose is required. error amplifier the error amplifier compares the fb pin voltage with the internal 0.807v reference (ref) and outputs a current proportional to the difference between the two. this output current is then used to charge or discharge the internal compensation network to form the comp voltage, which is used to control the power mosfet current. the optimized internal compensation network minimizes the external component counts and simplifies the control loop design. enable/sync control en/sync is a digital control pin that turns the regulator on and off. drive en high to turn on the regulator, drive it low to turn it off. there is an internal 1m ? resistor from en/sync to gnd thus en/sync can be floated to shut down the chip. the en pin is clamped internally using a 6.5v series-zener-diode as shown in figure 2. connecting the en input pin through a pullup resistor to the voltage on the v in pin limits the en input current to less than 100a. for example, with 12v connected to vin, r pullup (12v ? 6.5v) 100a = 55k ? . connecting the en pin directly to a voltage source without any pullup resistor requires limiting the amplitude of the voltage source to 6v to prevent damage to the zener diode. figure 2?6.5v zener diode connection the chip can be synchronized to external clock range from 200khz up to 2mhz through this pin as soon as an external clock is added to this pin, with the internal clock rising edge synchronized to the external clock rising edge. under-voltage lockout (uvlo) the MP1499 has under-voltage lock-out protection (uvlo). when the vcc voltage is higher than the uvlo rising threshold voltage, the MP1499 will be powered up. it shuts off when the vcc voltage is lower than the uvlo falling threshold voltage. this is non-latch protection. the MP1499 is disabled when the input voltage falls below 3.25 v. if an application requires a higher under-voltage lockout (uvlo), use the en pin as shown in figure 3 to adjust the input voltage uvlo by using two external resistors. it is recommended to use the enable resistors to set the uvlo falling threshold (vstop) above 4.5v. the rising threshold (vstart) should be set to provide enough hysteresis to allow for any input supply variations.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 11 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. figure 3?adjustable uvlo soft-start the MP1499 employs soft start (ss) mechanism to ensure smooth output during power-up. when the en pin becomes high, an internal current source (11 a) charges up the ss capacitor. the ss capacitor voltage takes over the ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. once the ss voltage reaches the same level as the ref voltage, it keeps ramping up while v ref takes over the pwm comparator. at this point, the soft start finishes and it enters into steady state operation. if the output is pre-biased to a certain voltage during startup, the ic will disable the switching of both high-side and low-side switches until the voltage on the internal soft-start capacitor exceeds the sensed output voltage at the fb pin. the ss capacitor value can be determined as follows: ?? ? ? ? ? ?? ?? ? ss ss ss ref tmsi a cnf vv (1) if the output capacitors have large capacitance value, it?s not recommended to set the ss time too small. otherwise, it?s easy to hit the current limit during ss. a minimum value of 4.7nf should be used if the output capacitance value is larger than 330 f. power save mode for light load condition the MP1499 has aam (advanced asynchronous modulation) power save mode for light load. the aam voltage is set at 0.4v internally. under the heavy load condition, the v comp is higher than v aam . when clock goes high, the high-side power mosfet turns on and remains on until v ilsense reaches the value set by the comp voltage. the internal clock resets every time when v comp is higher than v aam . under the light load condition, the value of v comp is low. when v comp is less than v aam and v fb is less than v ref , v comp ramps up until it exceeds v aam , during this time, the internal clock is blocked, thus the MP1499 skips some pulses for pfm (pulse frequency modulation) mode and achieves the light load power save. v aam clock v out r1 1pf 50pf 400k r2 v ref v fb v il sense v comp hs_driver - + + - qs r + - figure 4?simplified aam control logic when the load current is light, the inductor peak current is set internally which is about 1a for v in =12v, v out =3.3v, and l=3.3 h.the curve of inductor peak current vs. inductor is shown in figure 5. inductor peak current (a) inductor peak current vs. inductor 0 0.5 1 1.5 2 2.5 0123456 v out =1v v out =1.8v v out =2.5v v out =3.3v v out =5v figure5?inductor peak current vs. inductor over-current-protection and hiccup the MP1499 has cycle-by-cycle over current limit when the inductor current peak value
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 12 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. exceeds the set current limit threshold. meanwhile, output voltage starts to drop until fb is below the under-voltage (uv) threshold, typically 50% below the reference. once a uv is triggered, the MP1499 enters hiccup mode to periodically restart the part. this protection mode is especially useful when the output is dead-short to ground. the average short circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. the MP1499 exits the hiccup mode once the over current condition is removed. thermal shutdown thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. when the silicon die temperature is higher than 150c, it shuts down the whole chip. when the temperature is lower than its lower threshold, typically 130c, the chip is enabled again. floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection. this uvlo?s rising threshold is 2.2v with a hysteresis of 150mv. the bootstrap capacitor voltage is regulated internally by v in through d1, m1, c4, l1 and c2 (figure 6). if (v in -v sw ) is more than 5v, u1 will regulate m1 to maintain a 5v bst voltage across c4. a 10 ? resistor placed between sw and bst cap is strongly recommended to reduce sw spike voltage. r4 figure 6?internal bootstrap charging circuit startup and shutdown if both vin and en are higher than their appropriate thresholds, the chip starts. the reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. the regulator provides stable supply for the remaining circuitries. three events can shut down the chip: en low, vin low and thermal shutdown. in the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. the comp voltage and the internal supply rail are then pulled down. the floating driver is not subject to this shutdown command.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 13 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. application information setting the output voltage the external resistor divider is used to set the output voltage (see typical application on page 1). the feedback resistor r1 also sets the feedback loop bandwidth with the internal compensation capacitor (see typical application on page 1). choose r1 to be around 40k ? . r2 is then given by: out r1 r2 v 1 0.807v ? ? (2) the t-type network is highly recommended when vout is low, as figure 7 shows. fb 8 rt r2 r1 vout figure 7? t-type network table 1 lists the recommended t-type resistors value for common output voltages. table 1?resistor selection for common output voltages v out (v) r1 (k ? ) r2 (k ? ) rt (k ? ) 1 20.5(1%) 84.5(1%) 160(1%) 1.2 30.1(1%) 61.9(1%) 160(1%) 1.8 40.2(1%) 32.4(1%) 82(1%) 2.5 40.2(1%) 19.1(1%) 33(1%) 3.3 40.2(1%) 13(1%) 33(1%) 5 40.2(1%) 7.68(1%) 33(1%) selecting the inductor a 1h to 10h inductor with a dc current rating of at least 25% percent higher than the maximum load current is recommended for most applications. for highest efficiency, the inductor dc resistance should be less than 15m ? . for most designs, the inductance value can be derived from the following equation. out in out 1 in l s v(vv) l vif ?? ? ?? ? (3) where i l is the inductor ripple current. choose inductor current to be approximately 30% of the maximum load current. the maximum inductor peak current is: 2 i i i l load ) max ( l ? ? ? (4) under light load conditions below 100ma, larger inductance is recommended for improved efficiency. selecting the input capacitor the input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the ac current to the step-down converter while maintaining the dc input voltage. use low esr capacitors for the best performance. ceramic capacitors with x5r or x7r dielectrics are highly recommended because of their low esr and small temperature coefficients. for most applications, two pieces 22f capacitor is sufficient. since the input capacitor (c1) absorbs the input switching current it requires an adequate ripple current rating. the rms current in the input capacitor can be estimated by: ? ? ? ? ? ? ? ? ? ? ? ? in out in out load 1 c v v 1 v v i i (5) the worse case condition occurs at vin = 2vout, where: 2 i i load 1 c ? (6) for simplification, choose the input capacitor whose rms current rating greater than half of the maximum load current.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 14 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the input capacitor can be electrolytic, tantalum or ceramic. when using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1 f, should be placed as close to the ic as possible. when using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. the input voltage ripple caused by capacitance can be estimated by: load out out in in sin iv v v1 fc1v v ?? ?? ? ?? ?? ? ?? (7) selecting the output capacitor the output capacitor (c2) is required to maintain the dc output voltage. ceramic, tantalum, or low esr electrolytic capacitors are recommended. low esr capacitors are preferred to keep the output voltage ripple low. the output voltage ripple can be estimated by: out out out esr s1 in s vv 1 v1r fl v 8fc2 ?? ?? ?? ?? ? ? ?? ?? ??? ?? ?? (8) where l 1 is the inductor value and resr is the equivalent series resistance (esr) value of the output capacitor. in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated by: out out out 2 in s1 vv v1 v 8f l c2 ?? ??? ?? ??? ?? (9) in the case of tantalum or electrolytic capacitors, the esr dominates the impedance at the switching frequency. for simplification, the output ripple can be approximated to: out out out esr in s1 vv v1r fl v ?? ???? ?? ? ?? (10) the characteristics of the output capacitor also affect the stability of the regulation system. the MP1499 can be optimized for a wide range of capacitance and esr values. external bootstrap diode an external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external bst diode are: ? v out is 5v or 3.3v; and ? duty cycle is high: d= in out v v >65% in these cases, an external bst diode is recommended from the vcc pin to bst pin, as shown in figure 8. figure 8?add optional external bootstrap diode to enhance efficiency the recommended external bst diode is in4148, and the bst cap is 0.1-1uf. pc board layout (8) pcb layout is very important to achieve stable operation especially for vcc capacitor and input capacitor placement. for best results, follow these guidelines: 1) use large ground plane directly connect to gnd pin. add vias near the gnd pin if bottom layer is ground plane. 2) place the vcc capacitor to vcc pin and gnd pin as close as possible. make the trace length of vcc pin-vcc capacitor anode-vcc capacitor cathode-chip gnd pin as short as possible. 3) place the ceramic input capacitor close to in and gnd pins. keep the connection of input capacitor and in pin as short and wide as possible.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 15 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. 4) route sw, bst away from sensitive analog areas such as fb. it?s not recommended to route sw, bst trace under chip?s bottom side. 5) place the t-type feedback resistor r8 close to chip to ensure the trace which connects to fb pin as short as possible. notes: 8) the recommended layout is based on the figure 9 typical application circuit on the next page. design example below is a design example following the application guidelines for the specifications: table 2?design example v in 12v v out 3.3v io 5a peak the detailed application schematic is shown in figure 9. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more device applications, please refer to the related evaluation board datasheets.
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 16 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical application circuits 33k r8 40.2k r1 10 r5 13k r2 c3 2 1 l1 c2a c2b c2c 33pf c6 c1b c1a 1 vout 1 1 1 vin c4 100k r3 1 vcc 1 en/sync en/sync 22nf c7 1 ss 1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd fb 1 vin 9 sw 8 6, 7 bst 4 3 vcc 2 ss 10 MP1499gd nc 5 u1 c1c figure 9?12v input-3.3v/5a peak output 33k r8 40.2k r1 10 r5 7.68k r2 c3 2 1 l1 c2a c2b c2c 33pf c6 c1b c1a 1 vout 1 gnd 1 vin c4 100k r3 1 vcc 1 en/sync 22nf c7 1 ss 1 gnd gnd vout gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd fb 1 vi n 9 sw 8 gnd 6,7 bst 4 en/sync 3 vcc 2 ss 10 MP1499gd nc 5 u1 c1c gnd figure 10?12v input-5v/5a peak output
MP1499 ? 16v/5a peak synchron ous step-down converter MP1499 rev. 1.0 www.monolithicpower.com 17 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. 82k r8 40.2k r1 10 r5 32.4k r2 c3 2 1 l1 c2a c2b c2c 47pf c6 c1b c1a 1 vout 1 gnd 1 vin c4 100k r3 1 vcc 1 en/sync 22nf c7 1 ss 1 gnd gnd vout gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd fb 1 vi n 9 sw 8 gnd 6,7 bst 4 en/sync 3 vcc 2 ss 10 MP1499gd nc 5 u1 c1c gnd figure 11?12v input-1.8v/5a peak output 160k r8 20.5k r1 10 r5 84.5k r2 c3 2 1 l1 c2a c2b c2c 47pf c6 c1b c1a 1 vout 1 gnd 1 vin c4 100k r3 1 vcc 1 en/sync 22nf c7 1 ss 1 gnd gnd vout gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd fb 1 vi n 9 sw 8 gnd 6,7 bst 4 en/sync 3 vcc 2 ss 10 MP1499gd nc 5 u1 c1c gnd figure 12 ? 12v input-1v/5a peak output
MP1499 ? 16v/5a peak synchron ous step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP1499 rev. 1.0 www.monolithicpower.com 18 7/26/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information qfn10 (2x3mm)

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