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asahikasei [AK8811/12] rev.1.1 - 1 - 2000/01 AK8811/12 ntsc/pal digital video encoder general description the AK8811 and ak8812 are low voltage, low power and small packaged digital video encoder. they are suitable for a portable dvd or vcd player. they convert itu-r.bt601/656 standard 8- bit parallel data into analog composite video, s-video or analog component signals y/cb/cr in ntsc and pal formats. ak8812 and AK8811 support macrovision copy protection rev.7.1(only ak8812), closed captioning and video blanking id(cgms). these functions are controlled by high-speed i 2 c bus interface. features ? ntsc-m, pal-b,d,g,h,i,m,n encoding. ? simultaneous composite video signal and s-video signal outputs ? y/cb/cr component output (based on eiaj guideline) ? ccir-656 4:2:2 8-bit parallel input - eav decoding ? master/slave operation - digital field sync i/o - digital vertical/horizontal sync i/o ? y filtering 2 x over-sampling ? c filtering 4 x over-sampling ? single 27mhz clock (the polarity could be inverted by sysinv pin) ? triple 10-bit dacs ? i 2 c interface (400khz) ? closed caption encoding (ntsc: line 21,284-smpte pal: line 21,334-ccir) ? macrovision copy protection rev. 7.1* (only for ak8812) ? vbid, cgms(eiaj cpr-1024) ? on-chip color bar generator ? low power consumption ? 3.3v only, cmos monolithic ? 48pin lqfp package * this device is protected by u.s. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual rights. the use of macrovision?s copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in written by macrovision. reverse engineering or disassembly is prohibited.
asahi kasei [AK8811/12] rev.1.1 2000/01 2 x2 lpf- luma x2 lpf- chroma-2 sub carrier run in clock video timing & base wave generator i 2 c interface u,v mod vref scl sda 10-bit dac ycbcr (4:2:2) to yuv (4:4:4) 10-bit dac 10-bit dac lpf chroma-1 v refin v refout iref /reset dvdd fid/vsync hsync sysclk data d7 - d0 sela composite / u y chroma / v sysinv selector avdd avss dvss
asahi kasei [AK8811/12] rev.1.1 2000/01 3 pin layout 48pin lqfp 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pd9 d7 d6 d5 d4 dvdd dvss d3 d2 d1 d0 test1 36 35 34 33 32 31 30 29 28 27 26 25 pd4 pd3 pd2 pd1 pd0 dvdd dvss iref vrefin vrefout avdd avss fid/vsync sysinv dvss hsync dvdd pd8 dvdd syscl k dvss pd7 pd6 pd5 test2 sela scl sda dvss /reset a vss y a vdd chroma / v a vss composite / u AK8811/12
asahi kasei [AK8811/12] rev.1.1 2000/01 4 pin/function no. pin name i/o description 2-5, 8-11 d7 - d0 i 27mhz 8-bit 4:2:2 multiplexed y,cb,cr data input. for rec.656 format, AK8811/12 decodes eav. for non-rec.656 format (without eav), AK8811/12 operates in master or slave mode. 41 sysclk i 27mhz clock input. the polarity could be inverted by sysinv. 48 sysinv i ?l ? : data is latched with rising edge. ?h? : data is latched with falling edge. 18 /reset i after this pin becomes ?l?, AK8811/12 starts the internal initializing sequence. after initializing sequence, AK8811/12 is set ntsc mode, rec.656 decoding mode. all dacs off condition. 45 fid /vsync i/o either of fid or vsync selected by the register. rec.656 decode mode :output master mode : output slave mode : input fid shows that ?l? is odd field and ?h? is even field. 46 hsync i/o rec.656 decode mode : output master mode : output slave mode : input 15 scl i serial interface clock 16 sda i/o serial interface data 14 sela i the slave address is set with this pin. ?l?:40h ?h?:42h 27 vrefout o output of the internal vref. terminate with 0.1uf or more capacitor. 28 vrefin i input of the reference voltage 29 iref o the currents flow this pin adjusts the full-scale output current of the dac. 24 composite/u o output of composite video signal or component u 22 chroma/v o output of the c signal or component v 20 y o output of luminance signal. 21,26 avdd p analog +3.3v 6,31, 42,44 dvdd p digital +3.3v 19,23,25 avss g analog ground 7,17,47, 40,30 dvss g digital ground 12,13 test1 test2 i test pin. ground for normal operation 1, 32- 39,43 pd[9:0] i/o test pin. open for normal operation
asahi kasei [AK8811/12] rev.1.1 2000/01 5 electrical characteristics absolute maximum ratings parameter min max units supply voltage (vdd) dvdd, pvdd, avdd -0.3 4.6v v input pin voltage (vin) -0.3 vdd+0.3 v input pin current (iin) - 10 ma analog reference current (iref) - 0.21 ma analog output current - 6.5 ma power dissipation 1000 mw storage temperature -40 125 c (note)when all ground pins(dvss, avss) are set to 0v. recommended operating conditions parameter min typ. max units supply voltage (vdd) 3.0 3.3 3.6 v operating temperature -40 85 c
asahi kasei [AK8811/12] rev.1.1 2000/01 6 dc characteristics [power supply:3.3v temperature:25 c] parameter symbol min max units conditions digital input high voltage vih1 0.7vdd v note1) digital input low voltage vil1 0.3vdd v note1) digital input leak current il 10 ua note1) digital output high voltage voh 2.4 v ioh = - 1ma note 2) digital output low voltage vol1 0.4 v iol = 2ma note 2) digital maximum load capacitance 20 pf i 2 c input high voltage i 2 c(sda,scl) vih2 0.7vdd v i 2 c input low voltage i 2 c(sda,scl) vil2 0.3vdd v i 2 c(sda) output voltage vol2 0.4 v iol = 3ma note 1) d[9:0],fid/vsync, hsync, sysclk, /reset pin note 2) fid/vsync, hsync pin note ) connected test pin to ground, sela and sysinv pin are desired polarity. analog characteristics and dissipation current [ power supply:3.3v temperature:25 c] parameter min typ max units conditions dac resolution 10 bit dac integral linearity error 0.6 2lsb dac differential linearity error 0.4 1lsb dac output full scale voltage 1.21 1.28 1.38 v note1) dac output offset voltage 5.0 mv note2) unbalances between dacs 1 5% note3) isolation between dacs 50 db 1mhz full scale dac load capacitance 30 pf note4) internal reference voltage 1.17 1.235 1.33 v internal reference drift 50 ppm/ c dac current (active mode) 15 ma note5) dac current (sleep mode) 10 ua note6) total current 50 72 ma note7) note 1) under the condition of output load 390 ? , iref pin with 12k ? , using internal reference. the output full-scale current iout is calculated as full scale output voltage (typ. 1.28v) /390 ? =typ. 3.3ma. note 2) dac output when feeding code of 0 (decimal). note 3) deviation between the dac output when feeding 1v generating code of 800(decimal). note 4) the value is a design target. this value is not tested. note 5) all dacs are operating. note 6) all dacs are turned off with no system clock. note 7) ntsc internal color bar with 3ch dacs operation and slave mode operation. dac output pins is connected with only 390 ? load.
asahi kasei [AK8811/12] rev.1.1 2000/01 7 ac characteristic 1. sysclk [ 3.3v temperature 25 c ] parameter symbol min. typ. max unit sysclk fsysclk 27 mhz sysclk pulse width h tclkh 15 nsec sysclk pulse width l tclkl 15 nsec sysclk fsysclk tclkh tclkl vil vih mid-points between vih and vil.
asahi kasei [AK8811/12] rev.1.1 2000/01 8 2. in case of sysinv = l (2-1). pixel data input pixel data input timing [ 3.3v temperature 25 c ] parameter symbol min typ max units data setup time tds 5 nsec data hold time tdh 8 nsec (2-2). synchronizing signal ( fid/vsync, hsync ) (2-2-1) input synchronizing signal timing [ 3.3v temperature 25 c ] parameter symbol min typ. max units data setup time tds 5 nsec data hold time tdh 8 nsec tds tdh sysclk d7 - d0 vil vih tds tdh sysclk fid/vsync, hsync vil vih
asahi kasei [AK8811/12] rev.1.1 2000/01 9 (2-2-2) output synchronizing signal timing [ 3.3v temperature 25 c ] parameter symbol min typ. max units delay from sysclk tdel 27 nsec (2-3). reset (initialize) reset timing [ 3.3v temperature 25 c ] parameter symbol min typ. max units /reset pulse width pres 10 sysclk /reset pres sysclk sysclk fid/vsync, hsync tdel vih
asahi kasei [AK8811/12] rev.1.1 2000/01 10 (3). in case of sysinv = h (3-1). pixel data input pixel data input timing [ 3.3v temperature 25 c ] parameter symbol min typ max units data setup time tds 5 nsec data hold time tdh 8 nsec (3-2). synchronizing signal ( fid/vsync, hsync ) (3-2-1) input synchronizing signal timing [ 3.3v temperature 25 c ] parameter symbol min typ. max units data setup time tds 5 nsec data hold time tdh 8 nsec tds tdh sysclk d7 - d0 vil vih tds tdh sysclk fid/vsync, hsync vil vih
asahi kasei [AK8811/12] rev.1.1 2000/01 11 (3-2-2) output synchronizing signal timing [ 3.3v temperature 25 c ] parameter symbol min typ. max units delay from sysclk tdel 27 nsec (3-3). reset (initialize) reset timing [ 3.3v temperature 25 c ] parameter symbol min typ. max units /reset pulse width pres 10 sysclk /reset pres sysclk sysclk fid/vsync, hsync tdel vil
asahi kasei [AK8811/12] rev.1.1 2000/01 12 ( 4). i 2 c bus (scl 400khz cycle mode ) (4-1) i/o timing 1 [ 3.3v temperature 25 c ] parameter symbol min max units bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec bus signal rise time tr 300 nsec bus signal fall time tf 300 nsec setup time(start condition) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec all the figures shown above list are not restricted by AK8811/12 but are restricted by i 2 c bus standard. please see the i 2 c bus standard for further details. (4-2) i/o timing 2 [ 3.3v temperature 25 c ] parameter symbol min. max. unit. data setup time tsu:dat 100 (1) nsec data hold time thd:dat 0.0 0.9 (2) usec clock pulse high time thigh 0.6 usec (1) in case of normal i 2 c bus mode tsu:dat 250nsec (2) using under minimum tlow, this value must be satisfied. tlow sda tf tr tsu:sta scl sda thd:dat thigh tsu:dat scl tbuf thd:sta tr tf tsu:sto
asahi kasei [AK8811/12] rev.1.1 2000/01 13 functional description ? reset when the reset pin [ /reset ] set to ?l?, AK8811/12 is in reset state. AK8811/12 starts in the internal initializing sequence at the trailing edge of the first sysclk after the reset pin is ?l?. all internal registers are set to be default value by this initializing sequence. AK8811/12 needs at least 10 clock counts of sysclk for this reset operation. after the reset operation, the video output pins are in high-impedance. AK8811/12 requires sysclk for the reset operation. ? master-clock AK8811/12 requires 27mhz clock at sysclk pin for operation. video input data (itu-r bt.656) is sampled at the trailing edge of this 27mhz. sysinv decides the edge direction. sysinv = l data is sampled at rising edge of sysclk. sysinv = h data is sampled at falling edge of sysclk. ? video signal interface AK8811/12 can interface with the video input data by the following 3 modes. the mode is set by the register [ interface mode register(00h) ]. 1. itu-r bt.656 format AK8811/12 decodes eav in stream data and manages an internal synchronization. in this case, AK8811/12 outputs fid (odd : ?l? even : ?h?)/ vsync and hsync. ccir-bit of [ interface mode register (00h) ] should be set ?1? . 2. itu-r bt.656 like format (4:2:2 y/cb/cr) there are master and slave modes, for itu-r bt.656 like format which does not include eav. in this mode, ccir-bit of [ interface mode register(00h) ] should be set ?0? . AK8811/12 provides fid/vsync and hsync to an external device according to the AK8811/12 internal timing counter. AK8811/12 starts to sample the input data at the fixed value on the internal pixel counter. in this mode, following setting should be done to [interface mode register(00h)]. ccir-bit = 0 mas-bit = 1 fid/vsync and hsync are supplied by an external device. AK8811/12 samples the data as same manner of master mode. in this mode, following setting should be done to [interface mode register(00h)]. ccir-bit = 0 mas-bit = 0
asahi kasei [AK8811/12] rev.1.1 2000/01 14 ? video signal conversion video reconstruction module converts the multiplexed data (itu-r. bt601 y/cb/cr) to the interlace format of ntsc-m, pal-m, pal-b,d,g,h,i,n and other formats (ex. ntsc-4.43 and pal60). the video reconstruction format, the line number, the color encode way(ntsc or pal) and the frequency of color sub-carrier is specified by [video process 1 register(01h)]. (cf. burst signal table) the frequency and the phase of color sub-carrier are also adjustable by [sub c. freq. register(06h)] and [sub c. phase register(07h)]. the sub-carrier has a free-running mode and a reset-mode. in the reset-mode, the sub-carrier is reset automatically to the initial phase for every 4 fields (ntsc) or 8 fields (pal). ? component video output video output mode is set by vs-bit of [ video process 3 register (03h) ]. AK8811/12 can output not only the set of composite video signal and s-video signal but also can output component video signals(y/cb/cr). the component video signals are complied with eiaj guideline 1998/3. vs-bit = 0 : composite video signal and s-video signal output vs-bit = 1 : component video signal output ? luminance filter luminance signal passes through the 2x low pass filter fig.1 is the characteristic of luminance filter. fig. 1 luminance filter -70 -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency [mhz] gain [db]
asahi kasei [AK8811/12] rev.1.1 2000/01 15 ? chroma filter chroma signals (cb,cr) before sub-carrier modulation pass through the 1.3 mhz low pass filter shown in fig.2. chroma signal modulated by sub-carrier passes through the filter shown in fig.3. fig. 2 chroma-1 lpf fig. 3 chroma-2 lpf -70 -60 -50 -40 -30 -20 -10 0 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 frequency [mhz] gain [db] -70 -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency [mhz] gain [db]
asahi kasei [AK8811/12] rev.1.1 2000/01 16 ? color burst signal color burst signal is generated by 24bits-length digital frequency synthesizer. the default frequency of the color burst is selected by [video process 1 register(0x01)]. standard sub-carrier freq. [mhz] video process 1 [vm1,vm0] ntsc-m 3.57954545 [0,0] pal-m 3.57561188 [0,1] pal-b,d,g,h,i 4.43361875 [1,1] pal-n(arg.) 3.5820558 [1,0] pal-n(non-arg.) 4.43361875 [1,1] pal60 4.43361875 [1,1] ntsc-4.43 4.43361875 [1,1] burst signal table sub-carrier frequency 3.57561188mhz is allowed when pal-m mode is selected. the burst frequency and initial phase resolution are as follows. frequency resolution 0.8046hz sch phase resolution 360 /256 ? video dac AK8811/12 has the three current driven 10bits-dacs at 27mhz operation. the full scale voltage of dac is determined by the current output from iref pin. typical output voltage is 1.28vo-p under the condition of vrefin 1.235v, 12k ? between iref pin and ground(avss) and dac load resistance of 390 ? . this full-scale voltage should be set in the range of 1.17v to 1.33v by adjusting the resistor which terminates iref pin. each dac output can be set to ?active state? or to ?inactive state? individually by [dac mode register(05h)]. when dac is in ?inactive state?, the output is hi-impedance. when all dacs are set to ?inactive state?, the analog part of AK8811/12 goes into sleep mode. in this case AK8811/12 stops outputing the reference voltage(vref) output. when any dac is switched over in ?active state? from sleep mode, AK8811/12 starts outputing reference voltage. in this case AK8811/12 needs several milisecond for vref wake-up time. using internal vref as the reference voltage, connect [vref out] pin with [vref in] pin and [vref out] pin is terminated with more than 0.1uf capacitor. ? use external reference voltage in order to improve the accuracy of dac output, external reference voltage may be used. in this case, vrefout pin still needs to be terminated with more than 0.1uf capacitor.
asahi kasei [AK8811/12] rev.1.1 2000/01 17 ? copy protection macrovision copy protection rev.7.1 information about the macrovision encoding functions of the ak8812 is available to macrovision licensees. macrovision may be contacted at: macrovision corporation 1341 orleans drive sunnyvale, california 94089 usa attention: acp-ppv technical support fax: (408) 743 ? 8610
asahi kasei [AK8811/12] rev.1.1 2000/01 18 ? closed caption and extended data AK8811/12 supports both closed captioning and extended data. they are controlled ?on? or ?off? respectively by [ video process 2 register(02h) ]. each data consists of 2 continuous bytes register( closed caption r (16h,17h) ), and it is recognized as the data is renewed when the second byte(17h register) is written in the register. after the data is renewed, AK8811/12 encodes closed captioning and extended data at the designated line. if the data isn?t renewed, AK8811/12 outputs ?ascii-null? code. the data is supposed as odd parity and 7 bit us- ascii code. host should provide a parity bit. *in pal encoding mode, AK8811/12 outputs them at the same timing and same pattern as ntsc. *the line where closed captioning data is encoded is as follows. 525/60 system (smpte) 625/50 system (ccir) closed caption 21 line default 21 line default extended data 284 line default 334 line default fig. 4 closed captioning wave form s t a p a r i t y p a r i t y 10.5 0.25us 12.91 us 10.003 0.25us 27.382 us ( 33.764 us ) 61 us 240 48nsec rise/fall times ( 2t bar shaping ) two 7-bit+parity ascii characters ( data ) 7 cycles of 0.5035mhz ( clock run-in ) 50 2ire 40ire
asahi kasei [AK8811/12] rev.1.1 2000/01 19 ? video id AK8811/12 supports video id (eiaj standard, cpr-1204) encoding for the distinction of an aspect ratio, etc. setting or resetting the vbid-bit of [ video process 2 register(02h) ], this function is switched on/off. the data is set by using [ video id data register(1ah, 1bh) ]. vbid data renewal timing . vsync set control register new data si/sda data #1 old data new data fig. 5 vbid data renewal timing vbid data layout vbid is consists of 20 bits and its format is shown as follows. AK8811/12 generates crc code automatically and appends it to the data. initial value of the polynomial is 1. fig. 6 vbid code assignment word 0 2 bit crc 6 bit word 2 8 bit word 1 4 bit data bit 20 bit 1
asahi kasei [AK8811/12] rev.1.1 2000/01 20 vbid waveform fig. 7 vbid wave form 525/60 s y stem 625/50 s y stem am p litude 70 ire 490 mv encode line 20/283 20/333 vbid parameter table 0 -40 ire 100 2.235 usec 50ns 11.2 usec 0.3 usec 49.1 usec 0.44 usec ref. bit 1 bit 2 bit 3 ????? bit 20 70 ire 10 ire 0 ire -5 ire / +10 ire
asahi kasei [AK8811/12] rev.1.1 2000/01 21 ? AK8811/12 interface timing (part 1) master mode & itu-r bt. 656 mode on itu-r bt.656 decoding mode or master mode operation, AK8811/12 outputs hsync and fid or vsync (selected by register). when AK8811/12 receives itu-r bt. 656 signal, AK8811/12 decodes [eav] code in the data for synchronization then outputs the hsync. AK8811/12 outputs hsync at the rising edge of sysclk in the timing of the 32nd/24th(ntsc/pal) data slot, which is counted from the [eav] starting point as below. (see also ac characteristics 2-2[input synchronizing signal]) on master mode operation, the front device connected with AK8811/12 (ex. mpeg decoder) starts to set cb on the 276th/288th(ntsc/pal) slot, after starting to count hsync falling edge as 32nd/24th(ntsc/pal) slot. fid/vsync is output synchronously with hsync at the timing of solid line as in fig. 10 video field. fig. 8 interface timing (itu-r bt.656 or master mode) 276 (288) cb cr y y 27mhz sysclk hsync itu-r. bt601(656) 32 (24) 244t (264t) ntsc(pal) t=1/27mhz * uncertainty of 1t occurs according to the reset timing.
asahi kasei [AK8811/12] rev.1.1 2000/01 22 ? AK8811/12 interface timing (part 2) slave mode on slave mode operation, hsync and fid or vsync (selected by register) are input to AK8811/12. AK8811/12 monitors the transition of hsync at the timing of the rising edge of sysclk. (refer to ac characteristic 2-1. [input synchronizing signal]) after AK8811/12 recognizes hsync is low-logic, AK8811/12 sets the slot number to the 32nd/24th(ntsc/pal), internally, then AK8811/12 starts to sample the data as cb on 276th/288th(ntsc/pal) slot. video field is recognized the transition timing between fid/vsync and hsync. (fig.10. video field) as in the figure, there is a toreralnce of 1/4h. 1/2 h 1 h 1/2 h 1/2 h 1/2 h fid/vsync hsync fid/vsync odd field start even field start fig. 9. interfacing timing (slave mode) fi g . 10. video field 276 (288) cb cr y y 27mhz sysclk hsync itu-r. bt601(656) ntsc(pal) 32 (24) t=1/27mhz * uncertainty of 1t occurs according to the reset timing. 244t (264t)
asahi kasei [AK8811/12] rev.1.1 2000/01 23 ? hsync fid/vsync timing 6 7 5 3 4 odd even hsync fid vsync odd even 269 270 268 266 267 hsync fid vsync 3 4 2 625 1 odd even hsync fid vsync odd even 316 317 315 313 314 hsync fid vsync fig. 11. ntsc / pal/m fig. 12 pal
asahi kasei [AK8811/12] rev.1.1 2000/01 24 ? color bars AK8811/12 generates the common color bar signal for ntsc and pal internally. the generated color bar is ?100% amplitude, 100% saturation?. the following values are code for itu-r. bt601 white yellow cyan green magenta red blue black cb 128 16 166 54 202 90 240 128 y 235 210 170 145 106 81 41 16 cr 128 146 16 34 222 240 110 128 blank level white level sync level white yellow cyan green magenta red blue black luminance chrominace
asahi kasei [AK8811/12] rev.1.1 2000/01 25 ? component video output the levels of each component video outputs are following. ( color bar ntsc 100/0/100/0 ) magnitude is compliant to the guideline of eiaj cpr-1024. [mv] white yellow cyan green magenta red blue black cb 0 -350 118 -232 232 -118 350 0 y 714 632 500 418 296 213 82 0 cr 0 57 -350 -293 293 350 -57 0 y signal level : : : : 1.00vpp y ( video signal level ) : 0.714v y ( sync level ) : 0.286v setup : none cb/cr signal level : 0.350v 714mv (100 ire) white y ellow c y an green ma g enta red blue black 286mv 350mv - 350mv 350mv - 350mv
asahi kasei [AK8811/12] rev.1.1 2000/01 26 ? i 2 c control sequence AK8811/12 is controlled by i 2 c bus. the slave address can be selected as 40h or 42h by selecting sela pin. sela pull-down 40h pull-up 42h operation : write sequence: *continuous data writing is capable for the all registers. sequential read: (only sub address of 24h, 25h, 26h could be read ) s : start condition a : acknowledge(sda low) a: not acknowledge(sda high) stp : stop condition r/w: 1: read 0:write - it ignores the general call s slave address w a sub address data_1 a a data_n a/a stp by host by AK8811/12 data_24h a data_25h a stp data_26h a s slave w a sub address 24h a rs slave r a
asahi kasei [AK8811/12] rev.1.1 2000/01 27 AK8811/12 register map sub address name r/w explanation 00h interface mode w setting interface mode 01h video process 1 w setting standard (ntsc, pal etc.) 02h video process 2 w setting closed caption/extended data/vbid 03h video process 3 w setting composite signal or component signal adjusting chroma/luma delay 04h reserved 05h dac mode w each dac on/off switch 06h sub c. freq. w adjusting sub-carrier frequency 07h sub c. phase w adjusting sub-carrier phase 08h-15h reserved 16h closed caption r w closed caption lower byte data 17h closed caption r w closed caption upper byte data 18h closed caption r w extended lower byte data 19h closed caption r w extended upper byte data 1ah video id data w video id lower byte data 1bh video id data w video id upper byte data 1ch-23h reserved 24h sts data r status 25h device id r device id 26h device rev r revision 27h-29h reserved
asahi kasei [AK8811/12] rev.1.1 2000/01 28 interface mode register (w only default a4h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h bln4 bln3 bln2 bln1 bln0 fid mas ccir symbol value description bln4 - bln0 ***** line blanking no. default 10100 fid 0 select vsync 1 select fid default mas 0 slave mode default 1 master mode when ccir=0,it?s valid ccir 0 ccir656 non-decode default 1 ccir656 decode video process 1 register (w only default 18h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01h reserved cbg setup scr vm3 vm2 vm1 vm0 symbol value description cbg 0 video encode default 1 generates color bar setup 0 no set-up 1 7.5 ire set-up default scr 0 sub c. phase reset off 1 standard field reset default vm3 ? vm2 00 525/60 default 01 525/60 pal (pal-m etc.) 10 reserved 11 pal vm1-vm0 00 3.57954545 mhz default 01 3.57561188 mhz (pal-m only) 10 3.5820558 mhz 11 4.43361875 mhz register setting of each standard is showend as following ; vm3-vm0 ntsc-m 0000 pal-b,d,g,h,i 1111 pal-m 0101 pal-60 0111 ntsc4.43 0011 ? when scr is ?on?, the subcarrier phase is reset every 4 fields for ntsc, every 8 fields for pal. ? even when setup is ?on?, there is no set-up (pedestal) during the blanking lines.
asahi kasei [AK8811/12] rev.1.1 2000/01 29 video process 2 register (w only default 00h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02h reserved reserved reserved reserved reserved cc284 cc21 vbid symbol value description cc284 0 extended data off default 1on cc21 0 closed caption off default 1on vbid 0 video id off default 1on video process 3 register (w only default 00h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 03h reserved vs syd2 syd1 syd0 cyd2 cyd1 cyd0 symbol value description video set 0 composite, s-video set 1 component set default syd2 - syd0 s-video y component default delay no. from chroma: 2's comp. 000 cyd2 - cyd0 composite y component default delay no. from chroma: 2's comp. 000 ? vs-bit selects the one of the setting of signals from the 2 signal sets (composite, y /c or y/cb/cr) ? s video and y component of the composite signal can be shifted for the chroma signal independently at 3-system clock (27mhz).
asahi kasei [AK8811/12] rev.1.1 2000/01 30 dac mode register (w only default 00h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05h reserved reserved reserved reserved reserved outcp outc outy symbol value description outcp 0 composite video signal or u signal output : off default 1 composite video singal or u signal output : on outc 0 chroma signal or v signal output : off default 1 chroma signal or v signal output : on outy 0 y signal output : off default 1 y signal output : on ? video output of AK8811/12 (dac) can be forced ?off? independently. the output of dac that is forced ?off? is hi-impedance. when three dacs are forced ?off?, then the internal vref is also forced ?off?. in this case, it takes several miliseconds before the internal vref reaches the proper voltage after any dac becomes ?on?. subc freq. register (w only default 00h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06h subf7 subf6 subf5 subf4 subf3 subf2 subf1 subf0 symbol value description subf7-subf0 adjustment of frequency between +127 and ?128 step of 0.8hz default 0 ? AK8811/12 generates the necessary sub-carrier frequency from a system clock by dfs (digital frequency synthesizer) ? frequency of default is adjustable by specifying this bit. this bit adjusts the default frequency. subc phase register (w only default 00h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07h subp7 subp6 subp5 subp4 subp3 subp2 subp1 subp0 symbol value description subp7 ? subp0 step: (360 /256 ) default 0 ? sub- carrier phase is adjustable by (360 /256) step.
asahi kasei [AK8811/12] rev.1.1 2000/01 31 closed caption register (w only default 00h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16h cc1[7] cc1[6] cc1[5] cc1[4] cc1[3] cc1[2] cc1[1] cc1[0] 17h cc2[7] cc2[6] cc2[5] cc2[4] cc2[3] cc2[2] cc2[1] cc2[0] 18h cc3[7] cc3[6] cc3[5] cc3[4] cc3[3] cc3[2] cc3[1] cc3[0] 19h cc4[7] cc4[6] cc4[5] cc4[4] cc4[3] cc4[2] cc4[1] cc4[0] symbol description cc1[7] ? cc1[0] line 21 ?1 closed caption cc2[7] ? cc2[0] line 21 ?2 cc3[7] ? cc3[0] line 284 -1 extended data cc4[7] ? cc4[0] line 284 -2 ? when the 2nd byte of closed caption data and extended data is written in, AK8811/12 recognizes the renewed data and encodes it in the video line. when the data is not renewed AK8811/12 outputs null code. video id data register (w only default 00h) sub add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ah reserved reserved bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 1bh bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 ? please write value 0 at reserved bit. ? bit numbers correspond to fig. 5 vbid code assignment. ? AK8811/12 generates crc 6 bit data automatically.
asahi kasei [AK8811/12] rev.1.1 2000/01 32 followings are read only register status register (r only) sub add bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 24h reserved reserved en284 en21 sync sts2 sts1 sts 0 symbol value description en284 0 wait for the appointed video line to encode. 1 ready for the c.c. data input to the register. en21 0 wait for the appointed video line to encode. 1 ready for the c.c. data input to the register. sync 0 1 missing synchronization in slave mode. synchronization was achieved. sts2 - sts 0 *** shows the processing field no. ? status register becomes effective when sync bit turns to ?1?. when in master mode operation, this bit is ?1?. ? sts2-sts2 holds the field number of processing. some time lag is inevitable for the i 2 c acquisition. ? closed caption data should be renewed after firm that the en* flag is ?1?. en* flag bit is cleared after the second byte( sub address 17h,19h) was accessed. ? reserved-bit is always value 0. device id (r only default 21h) sub add bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 25h00010001 ? represents device id. AK8811 is assigned 11h. sub add bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 25h00010010 ? represents device id. AK8811/12 is assigned 12h. device rev (r only default 01h) sub add bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 26h00000001 ? represents device revision. initial is 01h.
asahi kasei [AK8811/12] rev.1.1 2000/01 33 system connection example analog gnd digital gnd analog 3.3v amp + filter 390 ? 75 ? composite - luma - chroma - vrefin iref vrefout d0 - d7 sysclk fid/ vsync hsync sda scl 0.1u 10uf a vss 12 k ? mpeg2 decoder i2c bus dvss a vdd dvdd AK8811/12 digital 3.3v 0.1u 10u 10u 0.1u
asahi kasei [AK8811/12] rev.1.1 2000/01 34 package 48pin lqfp package & lead frame material package molding compound : epoxy lead frame material : cu lead frame surface treatment : solder plate 1.70 max 1.4 typ 0.13 0.13 0.17 0.08 units = mm 9.0 0.2 9.0 0.2 0.22 0.08 0.5 0.10 m 7.0 1 48 0.5 0.2 0 ? 10 0.10
asahi kasei [AK8811/12] rev.1.1 2000/01 35 marking 1) pin #1 indication 2) date code : xxxxxxx (7 digits) 3) marketing code : AK8811/ak8812 4) country of origin 5) asahi kasei logo
asahi kasei [AK8811/12] rev.1.1 2000/01 36 important notice ?? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ?? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ?? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ?? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ?? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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