sp8680a 550mhz 4 4 4 4 4 10/11 ds3644-12 the sp8680a is an ecl variable modulus divider, with ecl and ttl compatible outputs. the circuit can operate from either ecl or ttl supplies. it divides by 10 when either of the ecl control inputs, pe1 or pe2, is in the high state and by 11 when both are low (or open circuit). the divider can be set asynchronously to the eleventh state by applying a high level to the master set (ms) input. features n very high speed C 650mhz (typ.) n ecl and ttl compatible inputs/outputs n dc or ac clocking n clock inhibit n asynchronous master set n equivalent to fairchild 11c90 quick reference data n supply voltage: 2 475v to 2 55v (ecl), 475v to 55v (ttl) n power consumption: 420mw n temperature range: 2 55 c to 1 125 c fig. 1 pin connections - top view dg16 clock input input bias master set input v ee (ttl o/p) v ee ttl output nc ecl output clock inhibit pe1 pe2 v cc o/p stage v cc a pe1 pullup pe2 pullup ecl output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ? control inputs sp8680a fig. 2 functional diagram v cc d1 s q1 d2 s q2 d3 s q3 d4 s q4 pe1 pe2 clock inhibit clock input ttl output output output q4 v ee 2 3 1 16 4 12 11 8 9 7 pe2 pullup pe1 pullup ck ck ck ck master set 14 input bias 15 bias gen ttl v ee 13 v cc a 5 6 absolute maximum ratings supply voltage, |v cc 2 v ee | ecl output source current storage temperature range max. junction temperature ttl output sink current max. clock input voltage 8v 50ma 2 65 c to 1 150 c 1 175 c 30ma 25v p-p ordering information sp8680 a dg advance information
2 sp8680a characteristic maximum frequency (sinewave input) minimum frequency (sinewave input) power supply current ecl output high voltage ecl output low voltage input high voltage input low voltage input low currents input high current, clock and ms input high current, pe1 and pe2 propagation delay, clock to q4 low propagation delay, clock to q4 high propagation delay, ms to q4 high modulus control set-up time modulus control release time ecl output rise time (20% - 80%) ecl output fall time (80% - 20%) conditions notes 5 6 5 6 6 6 3, 6 4, 6 6 6 electrical characteristics unless otherwise stated, the electrical characteristics are guaranteed over specified supply, frequency and temperature range ecl operation supply voltage, v ee = 2 475v to 2 55v, v cc = 0v temperature, t amb = 2 55 c to 1 125 c symbol f max f min i ee v oh v ol v inh v inl i il i h i h t phl t plh t plh t s t r t elh t ehl 550 2 093 2 185 2 0095 2 185 05 4 4 min. max. units value 10 105 2 078 2 162 2 081 2 1475 400 250 4 3 6 2 2 mhz mhz ma v v v v m a m a m a ns ns ns ns ns ns ns ac coupled clock = 350mv p-p ac coupled clock = 600mv p-p v ee = 2 55v, pins 6, 7, 13 o/c v ee = 2 52v (25 c), r l = 100 w to 2 2v v ee = 2 52v (25 c), r l = 100 w to 2 2v v ee = 2 52v (25 c) v ee = 2 52v (25 c) 25 c v in = 2 185v (25 c) v in = 2 08v (25 c) r l = 100 w to 2 2v (25 c) r l = 100 w to 2 2v (25 c) 25 c 25 c 25 c 25 c 25 c ttl operation supply voltage, v cc = v cc a = 475v to 55v, v ee = 0v temperature, t amb = 2 55 c to 1 125 c characteristic conditions notes 5 6 5 5 5 6 6 6 3, 6 4, 6 6 6 symbol f max f min i cc v oh v ol v inh v inl i il t phl t plh t p t s t r t tlh t thl 550 23 39 2 4 6 6 4 4 min. max. units value mhz mhz ma v v v v ma ns ns ns ns ns ns ns ac coupled clock = 350mv p-p ac coupled clock = 600mv p-p v cc = 55v, pins 6, 7 o/c, pin 13 to pin 12 v cc = 475v, i oh = 2 640 m a v cc = 55v, i ol = 2 20 m a v cc = 50v (25 c) v cc = 50v (25 c) v cc = 55v (25 c), pins 6, 7 = v cc , v in = 04v v cc = 50v (25 c) v cc = 50v (25 c) v cc = 50v (25 c) v cc = 50v (25 c) v cc = 50v (25 c) v cc = 50v (25 c) v cc = 50v (25 c) 10 111 05 35 14 14 17 5 5 maximum frequency (sinewave input) minimum frequency (sinewave input) power supply current ttl output high voltage ttl output low voltage input high voltage, pe1 and pe2 input low voltage, pe1 and pe2 input low current, pe1 and pe2 propagation delay, clock to ttl low propagation delay, clock to ttl high propagation delay, ms to ttl high modulus control set-up time modulus control release time ttl output rise time (20% - 80%) ttl output fall time (80% - 20%) notes 1. the temperature coefficients of v oh = 1 12mv/ c, v ol = 1 024mv/ c and of v in = 1 08mv/ c. 2. the test configuration for dynamic testing is shown in fig.6. 3. the set-up time t s is defined as the minimum time that can elapse between l ? h transition of control input and the next l ? h clock pulse transition to ensure that the 4 10 mode is obtained. 4. the release time t r is defined as the minimum time that can elapse between h ? l transition of control input and the next l ? h clock pulse transition to ensure that the 4 11 mode is obtained. 5. tested at 1 25 c and 1 125 c only. 6. guaranteed but not tested.
3 sp8680a 6 t r t s 5 5 clock input pe input q4 and ttl 1600 1400 1200 1000 800 600 400 200 0 0 100 200 300 400 500 600 700 800 input frequency (mhz) input amplitude (mv p-p) 2 55 c 1 125 c fig. 3 typical input sensitivity x x l l h h all outputs set high hold 4 11 4 10 4 10 4 10 pe2 output response fig. 4 truth table and timing diagram x x l h l h pe1 clock inhibit x h l l l l ms h l l l l l j 2 j 1 j 0.5 j 0.2 0 2 j 0.2 2 j 0.5 2 j 1 2 j 2 1 0.5 0.2 j 5 2 j 5 2 5 100 200 300 400 500 600 fig. 5 typical input impedance. test conditions: supply voltage = 5v, ambient temperature = 25 c. frequencies in mhz, impedances normalised to 50 w .
4 sp8680a dut 200 ttl output v ee 4 8 9 12 16 15 33 33 20 input from generator to monitor 200 200 v cc 160 11 13 q4 q4 v ee (ttl) 5 160 160 ecl output to 50 w ecl output to to sampling scope fig. 6 test circuit operating notes 1. the clock input, which is ecl10k compatible throughout the temperature range 2 55 c to 1 125 c , can also be coupled to ttl as shown in fig. 9. the clock can also be capacitively coupled to the signal source (see fig, 7). connecting the internally-generated bias voltage to the clock input i.e., pin 15 to pin 16, centres the clock input about the switching threshold (see fig. 8). 2. the two complementary outputs are ecl10k compatible but internal pulldown resistors are not included and therefore external pulldown resistors to v ee are required. 3. the ttl totem pole output operates with the same supply and is powered up by connecting v ee (pin 12) to ttl v ee (pin 13). if the ttl output is not required then the ttl v ee pin should be left open circuit, reducing the power consumption by 20mw, typically. 4. both control inputs ( pe1 and pe2) are ecl10k compatible throughout the temperature range. each control input is provided with a pullup resistor, the remote ends of which are connected to pins 6 and 7, respectively. this allows the pullup resistors to be unused if so desired or to be used to interface from ttl (see fig. 9). if interfacing to ecl is required then pins 6 and 7 should be left open circuit; alternatively, they can be connected to v ee to act as pulldown resistors. when high, the master set input sets the divider to the eleventh state, is asynchronous and overrides the clock input. 5. all the inputs have internal 50k w pulldown resistors. 6. the circuit will operate down to dc but inputslew rate must be better than 20v/ m s. 7. input impedance is a function of frequency. see fig. 5. 50k 2 (3) 5 13 16 15 6 (7) 01 m ttlmodulus control clock input ttl output 1 5v divide by 10/11 bias gen 2k 50k 400 12 10 v ee v ee (ttl) 01 m v cc a v cc fig. 8 typical application showing ttl interfacing. fig. 7. ac coupled input 01 m 15 16 sp8680
5 sp8680a (a) low speed v cc 6 or 7 2 or 3 ttl 2k ttl 270 470 v cc (a) high speed v ee 6 or 7 2 or 3 2k fig. 9 ttl interface to pe1 and pe2
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