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1 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm features ? jedec-standard, pc66 and pc100 rev 1.0 144-pin, small-outline, dual in-line memory module (sodimm) utilizes 100 mhz, 125 mhz and 133 mhz sdram components unbuffered 128mb (16 meg x 64) single +3.3v 0.3v power supply fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst lengths: 1, 2, 4, 8 or full page auto precharge and auto refresh modes self refresh mode: standard and low power 64ms, 4,096-cycle refresh lvttl-compatible inputs and outputs serial presence-detect (spd) options marking self refresh current standard none low power l package 144-pin sodimm (gold) g frequency/cas latency 133 mhz/cl=2 (7.5ns, 133 mhz sdrams) -13e 133 mhz/cl=3 (7.5ns, 133 mhz sdrams) -133 100 mhz/cl=2 (8ns, 125 mhz sdrams) -10e 66 mhz/cl=2 (10ns, 100 mhz sdrams) -662 small-outline sdram module mt8lsdt1664(l)h for the latest data sheet, please refer to the micron web site: www.micron.com/mti/msp/html/datasheet.html pin assignment (front view, 100 mhz) 144-pin small-outline dimm pin front pin back pin front pin back 1v ss 2v ss 73 dnu 74 ck1 3 dq0 4 dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 nc 78 nc 7 dq2 8 dq34 79 nc 80 nc 9 dq3 10 dq35 81 v dd 82 v dd 11 v dd 12 v dd 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 v dd 28 v dd 99 dq23 100 dq55 29 a0 30 a3 101 v dd 102 v dd 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 v dd 114 v dd 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 v dd 46 v dd 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 v ss 56 v ss 127 dq27 128 dq59 57 nc 58 nc 129 v dd 130 v dd 59 nc 60 nc 131 dq28 132 dq60 61 ck0 62 cke0 133 dq29 134 dq61 63 v dd 64 v dd 135 dq30 136 dq62 65 ras# 66 cas# 137 dq31 138 dq63 67 we# 68 cke1 139 v ss 140 v ss 69 s0# 70 rfu (a12) 141 sda 142 scl 71 s1# 72 rfu (a13) 143 v dd 144 v dd note: symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. key sdram component timing parameters module speed cas access setup hold marking grade latency time time time -13e -7e 2 5.4ns 1.5ns 0.8ns -133 -75 3 5.4ns 1.5ns 0.8ns -10e -8e 2 6ns 2ns 1ns -662 -10 2 9ns 2ns 1ns
2 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm general description the micron ? mt8lsdt1664(l)h is a high-speed cmos, dynamic random-access, 128mb memory orga- nized in a x64 configuration. this module uses sdrams that are internally configured as quad-bank drams with a synchronous interface (all signals are registered on the positive edge of the clock signals ck0-ck1). read and write accesses to the sdram module are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank, a0-a11 select the row). the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. this module provides for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. this module uses an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one bank while accessing the alternate bank will hide the precharge cycles and provide seamless, high-speed, random- access operation. this module is designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs, outputs and clocks are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to syn- chronously burst data at a high data rate with auto- matic column-address generation, the ability to inter- leave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram operation, refer to the 128mb x4, x8, x16 sdram data sheet. serial presence-detect operation this module incorporates serial presence-detect (spd). the spd function is implemented using a 2,048- bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the cus- tomer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals. part numbers part number configuration version mt8lsdt1664hg-13e__ 16 meg x 64 133 mhz, cl = 2 mt8lsdt1664hg-133__ 16 meg x 64 133 mhz, cl = 3 mt8lsdt1664hg-10e__ 16 meg x 64 100 mhz, cl = 2 mt8lsdt1664hg-662__ 16 meg x 64 66 mhz, cl = 2 mt8lsdt1664lhg-13e__ 16 meg x 64* 133 mhz, cl = 2 mt8lsdt1664lhg-133__ 16 meg x 64* 133 mhz, cl = 3 mt8lsdt1664lhg-10e__ 16 meg x 64* 100 mhz, cl = 2 mt8lsdt1664lhg-662__ 16 meg x 64* 66 mhz, cl = 2 note : all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt8lsdt1664hg-10e b1. *low power option.
3 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm functional block diagram mt8lsdt1664(l)h (128mb, 66 mhz) dqm cs# u8 note: all resistor values are 10 ohms. u1-u8 = mt48lc16m8a2tg sdrams a0 spd u9 scl sda a1 a2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmb7 dqm cs# u7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dqm cs# u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmb5 dqm cs# u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dqm cs# u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmb3 dqm cs# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dqm cs# u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb1 dqm cs# u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 we# ras#: sdrams u1-u8 cas#: sdrams u1-u8 cke: sdrams u1-u8 we#: sdrams u1-u8 a0-a11: sdrams u1-u8 ba0-1: sdrams u1-u8 a0-a11 ba0-1 v dd v ss sdrams u1-u8 sdrams u1-u8 ck0 u1, u5 u2, u6 ck1 u3, u7 u4, u8
4 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm functional block diagram mt8lsdt1664(l)h (128mb, 133/100 mhz) note: all resistor values are 10 ohms. u2-u9 = mt48lc8m16a2tg sdrams a0 spd scl sda a1 a2 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmh u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 cke1 cas#: sdrams u2-u9 cke: sdrams u2-u5 cke: sdrams u6-u9 we#: sdrams u2-u9 a0-a11: sdrams u2-u9 ba0-1: sdrams u2-u9 a0-a11 ba0-1 v dd v ss sdrams u2-u9 sdrams u2-u9 u2-u5 u6-u9 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb1 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmh u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb4 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmh u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb3 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmh u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmb6 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmb7 ck0 dqmh u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmh u7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmh u8 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# dqmh u9 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqml cs# s1# ck1 ras#: sdrams u2-u9 we# u1
5 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm pin descriptions pin numbers symbol type description 65-67 ras#, cas#, input command inputs ras#, cas# and we# (along with we# s0#) define the command being entered. 61, 74 ck0, ck1 input clock: ck0 and ck1 are driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. 62, 68 cke0, cke1 input clock enable: cke0 and cke1 activates (high) and deactivates (low) the ck0-ck1 signals. deactivating the clock provides power-down and self refresh operation (all banks idle) or clock suspend operation (burst access in progress). cke0 and cke1 are synchro- nous except after the device enters power-down and self refresh modes, where cke0 and cke1 become asynchronous until after exiting the same mode. the input buffers, including ck0-ck1, are disabled during power-down and self refresh modes, providing low standby power. 69, 71 s0#, s1# input chip select: s0# and s1# e nable (registered low) and disable (registered high) the command decoder. all commands are masked when s0# and s1# are registered high. s0# and s1# are considered part of the command code. 23-26, 115-118 dqmb0-dqmb7 input input mask: dqmb is an input mask signal for write accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (after a two-clock latency) when dqmb is sampled high during a read cycle. 106, 110 ba0, ba1 input bank address: ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. ba0 is also used to program the twelfth bit of the mode register. 29-34, 103-105, 109, a0-a11 input address inputs: a0-a11 are sampled during the 111, 112 active command (row-address a0-a11) and read/ write command (column-address a0-a8/a9, with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high). the address inputs also provide the op-code during a load mode register command. 142 scl input serial clock for presence-detect: scl is used to synchro- nize the presence-detect data transfer to and from the module.
6 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm pin descriptions (continued) pin numbers symbol type description 3-10, 13-20, 37-44, dq0-dq63 input/ data i/os: data bus. 47-54, 83-90, 93-100, output 121-128, 131-138 141 sda input/output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 11, 12, 27, 28, 45, v dd supply power supply: +3.3v 0.3v. 46, 63, 64, 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 1, 2, 21, 22, 35, 36, v ss supply ground. 55, 56, 75, 76, 91, 92, 107,108, 119, 120, 139, 140 70, 72 rfu ? reserved for future use: these pins should be left unconnected. 73 dnu ? do not use: this pin is not connected on these modules but is an assigned pin on the compatible dram version.
7 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm scl sda data stable data stable data change figure 1 data validity scl sda start bit stop bit figure 2 definition of start and stop scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an ac- knowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each subsequent eight- bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
8 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm serial presence-detect matrix (notes: 1) byte description entry (version) mt8lsdt1664(l)h(hex) 0 number of bytes used by micron 128 80 1 total number of spd memory bytes 256 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 9 (-13e/-133/-10e) 09 10 (-662) 0a 5 number of banks 2 (-13e/-133/-10e) 02 1 (-662) 01 6 module data width 64 40 7 module data width (continued) 0 00 8 module voltage interface levels lvttl 01 9 sdram cycle time, t ck 7 (-13e) 70 (cas latency = 3) 7.5 (-133) 75 8 (-10e) 80 10 (-662) a0 10 sdram access from clock, t ac 5.4 (-13e/-133) 54 (cas latency = 3) 6 (-10e) 60 7.5 (-662) 75 11 module configuration type nonparity 00 12 refresh rate/type 15.6s/self 80 13 sdram width (primary sdram) 16 (-13e/-133/-10e) 10 8 (-662) 08 14 error-checking sdram data width none 00 15 minimum clock delay, t ccd 1 01 16 burst lengths supported 1, 2, 4, 8, page 8f 17 number of banks on sdram device 4 04 18 cas latencies supported 2, 3 06 19 cs latency 0 01 20 we latency 0 01 21 sdram module attributes unbuffered 00 22 sdram device attributes: general 0e 0e 23 sdram cycle time, t ck 7.5 (-13e) 75 (cas latency = 2) 10 (-133/-10e) a0 15 (-662) f0 24 sdram access from clk, t ac 5.4 (-13e) 54 (cas latency = 2) 6 (-133/-10e) 60 9 (-662) 90 25 sdram cycle time, t ck ? 00 (cas latency = 1) 26 sdram access from clk, t ac ? 00 (cas latency = 1) 27 minimum row precharge time, t rp 15 (-13e) 0f 20 (-133/-10e) 14 30 (-662) 1e 28 minimum row active to row active, t rrd 14 (-13e) 0e 15 (-133) 0f 20 (-10e/-662) 14 note: ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ?
9 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm serial presence-detect matrix (continued) (notes: 1,2) byte description entry (version) mt8lsdt1664(l)h(hex) 29 minimum ras# to cas# delay, t rcd 15 (-13e) 0f 20 (-133/-10e) 14 30 (-662) 1e 30 minimum ras# pulse width, t ras 37 (-13e) 25 44 (-133) 2c 50 (-10e) 32 60 (-662) 3c 31 module bank density 64mb (-13e/-133/-10e) 10 128mb (-662) 20 32 command and address setup time 1.5 (-13e/-133) 15 2 (-10e) 20 0 (-662) 00 33 command and address hold time 0.8 (-13e/-133) 08 1 (-10e) 10 0 (-662) 00 34 data signal input setup time 1.5 (-13e/-133) 15 2 (-10e) 20 0 (-662) 00 35 data signal input hold time 0.8 (-13e/-133) 08 1 (-10e) 10 0 (-662) 00 36-61 reserved 00 62 spd revision 1.2 (-13e/-133/-10e) 12 1.0 (-662) 01 63 checksum for bytes 0-62 -13e 58 -133 a6 -10e ee -662 58 64 manufacturer ? s jedec id code micron 2c 65-71 manufacturer ? s jedec id code (continued) ff 72 manufacturing location 01 02 03 04 05 06 07 08 09 73-90 module part number (ascii) x 91 pcb identification code 1 01 202 303 404 505 606 707 808 909 note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data.
10 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm serial presence-detect matrix (continued) (notes: 1,2) byte description entry (version) mt8lsdt1664(l)h(hex) 92 identification code (continued) 0 00 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95-98 module serial number x 99-125 manufacturer-specific data (rsvd) - 126 system frequency 133/100 (-13e/-133/-10e) 64 66 (-662) 66 127 sdram component and clock detail -13e/-133/-10e cf -662 06 note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data.
11 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm truth table 1 ? commands and dqmb operation (notes: 1) name (function) cs# ras# cas# we# dqmb addr dqs notes command inhibit (nop) h xxxx x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, l h l h l/h 8 bank/col x 4 and start read burst) write (select bank and column, l h l l l/h 8 bank/col valid 4 and start write burst) burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x op-code x 2 write enable/output enable ???? l ? active 8 write inhibit/output high-z ???? h ? high-z 8 commands truth table 1 provides a general reference of avail- able commands. for a more detailed description of note: 1. cke is high for all commands shown except self refresh. 2. a0-a11 define the op-code written to the mode register. 3. a0-a11 provide row address and ba0, ba1 determine which bank is made active. 4. a0-a8/a9 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine which bank is being precharged. a10 high: all banks are precharged and ba0, ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). commands and operations, refer to the 128mb x4, x8, x16 sdram data sheet.
12 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm figure 4 mode register definition table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a8/a9 cn, cn+1, cn+2 page (location cn+3, cn+4... not supported (y) 0-y) ? cn-1, cn ? m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved m6 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 burst length burst length cas lat ency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 a11 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices. note: 1. for full-page accesses: y = 512 (133 mhz/100 mhz), y = 1,024 (66 mhz). 2. for a burst length of two, a1-a8/a9 select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-a8/a9 select the block-of-four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a8/a9 select the block-of-eight burst; a0-a2 select the starting column within the block. 5. for a full-page burst, the full row is selected, and a0-a8/a9 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a8/a9 select the unique column to be accessed, and mode register bit m3 is ignored.
13 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm absolute maximum ratings* voltage on v dd supply relative to v ss .... -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ..................................... -1v to +4.6v operating temperature, t a (ambient) ... 0c to +70c storage temperature (plastic) ............ -55c to +125c power dissipation ................................................... 8w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1) (v dd = +3.3v 0.3v) p arameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd +0.3 v 2 input low voltage: logic 0; all inputs v il -0.5 0.8 v 2 input leakage current: ck0, ck1, s0#, s1#, i i 1 -20 20 a 3 any input 0v v in v dd cke0, cke1 (all other pins not under ras#, cas#, we#, i i 2 -40 40 a test = 0v) ba0, ba1, a0-a11 dqmb0-dqmb7 i i 3 -10 10 a 4 output leakage current: dq0-dq63 i oz -10 10 a 4 dqs are disabled; 0v v out v dd output levels: v oh 2.4 ? v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol ? 0.4 v note: 1. all voltages referenced to v ss . 2. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. 3. 133 mhz/100 mhz module values for so# and cded will be twice those shown. 4. 66 mhz module values will be half of those shown.
14 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm i dd specifications and conditions (notes: 1, 2, 3, 4) (v dd = +3.3v 0.3v) parameter/condition symbol -13e -133 -10e -662 units notes operating current: active mode; burst = 2; i dd 1 840 800 720 1,040 ma 5, 6, read or write; t rc = t rc (min); 7, 8 cas latency = 3 standby current: power-down mode; i dd 2 16 16 16 16 ma 8 cke = low; all banks idle standby current: active mode; s0#, s1# = high; i dd 3 400 400 320 400 ma 5, 7, cke = high; all banks active after t rcd met; 8, 9 no accesses in progress operating current: burst mode; i dd 4 860 800 720 1,120 ma 5, 6, continuous burst; read or write; 7, 8 all banks active; cas latency = 3 auto refresh current: t rc = t rc (min); i dd 5 1,520 1,440 1,240 1,600 ma 5, 6, cke = high; s0# = high cl = 3 7, 8, t rc = 15.625s; i dd 6 24 24 24 24 ma 10, 12 cl = 3 self refresh current: standard i dd 7 16 16 16 16 ma 11 cke 0.2v low power (l) i dd 7 8 888ma max note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac timing tests have v il = 0v and v ih = 3v, with timing referenced to the 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v il (min) and no longer at the 1.5v crossover point. 4. i dd specifications are tested after the device is properly initialized. 5. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 6. the i dd current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 7. address transitions average one transition every two clocks. 8. t ck = 7.5ns for -13e/-133; t ck = 10ns for -10e. 9. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 10. cke is high during refresh command period ( t rfc [min]) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 11. enables on-chip refresh and address counters. 12. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels.
15 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm capacitance parameter symbol min max min max units notes input capacitance: a0-a11, ba0, ba1, ras#, cas#, we# c i 1 22 32 22 32 pf 1 input capacitance: s0#, s1#, cke0, cke1 c i 2 12 18 22 32 pf 1 input capacitance: ck0, ck1 c i 2 12 18 12 18 pf 1 input capacitance: dqmb0#-dqmb7# c i 3 7104 6pf1 input capacitance: scl, sda c i o1 ? 10 ? 10 pf 1 input/output capacitance: dq0-dq63 c io 2 10 14 6 8 pf 1 -13x/-10e -662 note: 1. this parameter is sampled. v dd = +3.3v; f = 1 mhz.
16 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm *specifications for the sdram components used on the module. sdram component* ac electrical characteristics (notes: 1, 2, 3, 4, 5, 6) ac characteristics -13e -133 -10e -662 parameter sym min max min max min max min max units notes access time from clk cl = 3 t ac 5.4 5.4 6 7.5 ns (pos. edge) cl = 2 t ac 5.4 6 6 9 ns address hold time t ah 0.8 0.8 1 1 ns address setup time t as 1.5 1.5 2 2 ns clk high-level width t ch 2.5 2.5 3 3 ns clk low-level width t cl 2.5 2.5 3 3 ns clock cycle time cl = 3 t ck 7 7.5 8 10 ns 7 cl = 2 t ck 7.5 10 10 15 ns 7 cke hold time t ckh 0.8 0.8 1 1 ns cke setup time t cks 1.5 1.5 2 2 ns cs#,ras#,cas#,we#,dqm hold time t cmh 0.8 0.8 1 1 ns cs#,ras#,cas#,we#,dqm setup time t cms 1.5 1.5 2 2 ns data-in hold time t dh 0.8 0.8 1 1 ns data-in setup time t ds 1.5 1.5 2 2 ns data-out high-impedance cl = 3 t hz 5.4 5.4 6 8 ns 8 time cl = 2 t hz 5.4 6 7 10 ns 8 data-out low-impedance time t lz 1 1 1 2 ns data-out hold time (load) t oh 2.7 2.7 3 3 ns data-out hold time (no load) t oh n 1.8 1.8 1.8 n/a ns 9 active to precharge command t ras 37 120,000 44 120,000 50 120,000 60 120,000 ns active to active command period t rc 60 66 70 90 ns active to read or write delay t rcd 15 20 20 30 ns refresh period (4,096 rows) t ref 64 64 64 64 ms auto refresh period t rfc 66 66 70 90 ns precharge command period t rp 15 20 20 30 ns 10 active bank a to active bank b command t rrd 14 15 20 20 ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 1 1.2 ns 11 write recovery time t wr 1 clk + 1 clk + 1 clk + 1 clk + ? 12 7ns 7.5ns 7ns 7ns 14 15 15 15 ns 13 exit self refresh to active command t xsr 67 75 80 90 ns 14 note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0c t a +70c) is ensured. 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 1.5v with equivalent load: 6. ac timing tests have v il = 0v and v ih = 3v, with timing referenced to the 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v il (min) and no longer at the 1.5v crossover point. q 50pf
17 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm notes (continued) 7. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including t wr, and precharge com- mands). cke may be used to reduce the data rate. 8. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 9. parameter guaranteed by design. 10. based on t ck = 133 mhz (-13e/-133), 100 mhz (-10e), or 66 mhz (-662). 11. ac characteristics assume t t = 1ns. 12. auto precharge mode only. the precharge timing budget ( t rp) begins 7.5ns/7ns after the first clock delay, after the last write is executed. 13. precharge mode only. 14. clk must be toggled a minimum of two times during this period.
18 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm ac functional characteristics (notes: 1, 2, 3, 4, 5, 6) parameter symbol -13e -133 -10e/-662 units notes read/write command to read/write command t ccd 1 1 1 t ck 7 cke to clock disable or power-down entry mode t cked 1 1 1 t ck 8 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 8 dqm to input data delay t dqd000 t ck 7 dqm to data mask during writes t dqm 0 0 0 t ck 7 dqm to data high-impedance during reads t dqz 2 2 2 t ck 7 write command to input data delay t dwd 0 0 0 t ck 7 data-in to active command t dal 4 5 4 t ck 9, 10 data-in to precharge command t dpl 2 2 2 t ck 10, 11 last data-in to burst stop command t bdl 1 1 1 t ck 7 last data-in to new read/write command t cdl 1 1 1 t ck 7 last data-in to precharge command t rdl 2 2 2 t ck 10, 11 load mode register command to active or refresh command t mrd 2 2 2 t ck 12 data-out to high-impedance from precharge command cl = 3 t roh 3 3 3 t ck 7 cl = 2 t roh 2 2 2 t ck 7 note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a +70 c) is ensured. 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 1.5v with equivalent load: 6. ac timing tests have v il = 0v and v ih = 3v, with timing referenced to the 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v il (min) and no longer at the 1.5v crossover point. 7. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 8. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 9. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 10. based on t ck = 133 mhz (-13e/-133), 100 mhz (-10e), or 66 mhz (-662). 11. timing actually specified by t wr. 12. jedec and pc100 specify three clocks. q 50pf
19 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm serial presence-detect eeprom dc operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ? 0.4 v input leakage current: v in = gnd to v dd i li ? 10 a output leakage current: v out = gnd to v dd i lo ? 10 a standby current: i sb ? 30 a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i dd ? 2ma scl clock frequency = 100 khz serial presence-detect eeprom ac operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 2 note: 1. all voltages referenced to v ss . note: 1. all voltages referenced to v ss . 2. timing actually specified by t wr.
20 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0 s t hd:sta 4 s spd eeprom symbol min max units t high 4 s t low 4.7 s t r1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s
21 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm 144-pin sodimm (128mb, 66 mhz) .043 (1.10) .035 (0.90) 1.055 (26.80) 1.045 (26.54) pin 1 2.666 (67.72) 2.656 (67.45) .787 (20.00) typ .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .130 (3.30) (2x) .024 (.60) typ .079 (2.00) r (2x) pin 143 (pin 144 on backside) front view .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ .157 (4.00) .150 (3.80) max note: all dimensions in inches (millimeters) max or typical where noted. min
22 16 meg x 64 sdram sodimm micron technology, inc., reserves the right to change products or specifications without notice. zm29.p65 ? rev. 1/00 ?2000, micron technology, inc. 16 meg x 64 sdram sodimm 144-pin sodimm (128mb, 133 mhz/100 mhz) 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc. .150 (3.80) max .043 (1.10) .035 (0.90) pin 1 2.666 (67.72) 2.656 (67.45) .787 (20.00) typ .071 (1.80) (2x) 2.386 (60.60) .0315 (.80) typ .83.82 (3.30) .024 (.60) typ .079 (2.00) r (2x) pin 143 (pin 144 on backside) front view .079 (2.00) .236 (6.00) 2.504 (63.60) .100 (2.55) .059 (1.50) typ .157 (4.00) 1.255 (31.88) 1.245 (31.62) note: all dimensions in inches (millimeters) max or typical where noted. min

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