View 5962P1022902QXC_7214229.PDF datasheet online --- IC-ON-LINE

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1 features ? organized as 64m x 40 (16meg x 40 x 4 banks) and 64meg x 48 (16meg x 48 x 4 banks) ? single jedec standard 3.3v power supply ? pc100-compliant ? operation -40 o c to +105 o c ? lvttl compatible with multiplexed address ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? programmable burst lengths: 1,2,4,8, or full page ? auto-precharge, includes conc urrent auto precharge, and auto-refresh mode ? 32ms, 8,192-cycle refresh ? operational environment: - total dose: 100 krad(si) - sel immune 111 mev-cm 2 /mg ? package options: 128-lead ceramic quad flatpack ? standard microcircuit drawing tbd - ut8sdmq64m40: 5962-10229 - ut8sdmq64m48: 5962-10230 - qml q and q+ pending introduction the ut8sdmq64m40 and ut8sdmq64m48 are high performance, highly integrated synchronous dynamic random access memory (sdram) multi-chip modules (mcms). total module density is 2,684,354,560 bits for the 2.5g device and 3,221,225,472 bits for the 3g device. each bit bank is organized as 8192 rows by 2048 columns. read and write accesses to the dram are burst oriented; accesses start at a selected lo cation and co ntinue for a programmed number of locations in a programmed sequence. the programmable read and wr ite burst lengths (bl) are 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. aeroflex?s sdrams are designed to operate at 3.3v. an auto- refresh mode is provided, along with a power-saving, power- down mode. all inputs and outputs are lvttl compatible. sdrams offer significant advances in dram operating execution, including the capability to synchronously burst data at a high data rate with auto matic column-address generation, to interleave between internal ba nks to mask precharging time, and to randomly change column addresses on each clock cycle during a burst access. standard products ut8sdmq64m40 2.5-gigabit sdram mcm ut8sdmq64m48 3.0-gigabit sdram mcm advanced datasheet september 22, 2010 figure 1. block diagrams a[12:0] ba[1:0] clk cke ras# cas# we# cs# 15 dqm0 dqm1 dqm2 dqm3 dqm4 8 8 8 8 8 40 u0 u1 u2 u3 u4 dq[7:0] dq[15:8] dq[23:16] dq[31:24] dq[39:32] sdram 16meg x 8 x4 dq[7:0](0) dq[7:0](1) dq[7:0](2) dq[7:0](3) dq[7:0](4) a[12:0] ba[1:0] clk cke ras# cas# we# cs# 15 dqm0 dqm1 dqm2 dqm3 dqm4 dqm5 8 8 8 8 8 8 48 u0 u1 u2 u3 u4 u5 dq[7:0] dq[15:8] dq[23:16] dq[31:24] dq[39:32] dq[47:40] sdram 16meg x 8 x4 dq[7:0](0) dq[7:0](1) dq[7:0](2) dq[7:0](3) dq[7:0](4) dq[7:0](5) 3.0gigabit (64mx48) 2.5gigabit (64mx40)
table of contents features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..11 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 burst length (bl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 burst type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 write burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..16 command inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 load mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..20 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 clock suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...32 burst read/single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..34 read wth auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 write with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...36 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 operational environment specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 dc electrical characteritics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 i dd specifications and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..... .43 capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ac characteristics and recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .44 ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ....45 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . 46 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..47 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .65 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .66
3 list of figures figure 1: block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .1 figure 2: 128-lead package 2.5g sdram module pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: 128-lead package 3.0g sdram module pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 5: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 6: activating a specific row in a specific bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .19 figure 7: example meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 8: read command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 20 figure 9: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 21 figure 10: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .22 figure 11: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 22 figure 12: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .23 figure 13: read-to-write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .24 figure 14: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .25 figure 15: terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .25 figure 16: write command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..26 figure 17: write burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .27 figure 18: write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .27 figure 19: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .28 figure 20: write-to-read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .28 figure 21: write-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .29 figure 22: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .30 figure 23: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .31 figure 24: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .32 figure 25: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .33 figure 26: clock suspend during read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .33 figure 27: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . .34 figure 28: read with auto precharge inte rrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .35 figure 29: write with auto precharge inte rrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .36 figure 30: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .37 figure 31: initialize and load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . .47 figure 32: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . .48 figure 33: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .49 figure 34: auto-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .50 figure 35: read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . .. . . . . .51 figure 36: read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . ..52 figure 37: single read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .53 figure 38: single read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .54 figure 39: alternating bank read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .55 figure 40: read ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .56 figure 41: read dqm operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..57 figure 42: write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . .. . . . . .58 figure 43: write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..59 figure 44: single write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . .60 figure 45: single write with auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..61 figure 46: alternating bank write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .62 figure 47: write ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . ..63 figure 48: write ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . ..64 figure 49: 128 - cqfp package drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . 65
4 list of tables table 1: 2.5g sdram module pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .6 table 2: 3.0g sdram module pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 9 table 3: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . .14 table 4: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . .. . . . . .15 table 5: truth table 1 ? commands and dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ... . . . .. . . . . . .16 table 6: truth table 2 ? cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ... . . . .. . . . 38 table 7: truth table 3 ? current state bank n , command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . .. . . . . .38 table 8: truth table 4 ? current state bank n , command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . .. . . . . .40
5 device package pinout drawing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 14 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 1 106 107 108 109 110 128 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 64 63 62 61 60 42 vddq vssq vss vdd vddq vssq vss vdd vddq vssq vss vdd vddq vssq vddq dqm3 vss dq3(3) vss dq4(3) vss dq2(3) vss dq5(3) vss dq1(3) vss dq6(3) vss dq0(3) vss dq7(3) vss vddq vssq vss vdd vddq vssq vss vdd vssq vddq vdd vss vssq vddq vdd vss vssq vddq a4 a3 a5 a2 a6 a1 a7 a0 a8 a10/ap a9 ba1 a11 ba0 a12 cs# cke ras# clk cas# we# vddq vssq vss vdd vddq vssq vss vdd vddq vssq dq7(0) dq7(1) dq0(0) dq0(1) dq6(0) dq6(1) dq1(0) dq1(1) dq5(0) dq5(1) dq2(0) dq2(1) dq4(0) dq4(1) dq3(0) dq3(1) dqm0 dqm1 vdd vss vssq vddq vssq dq7(4) dq7(2) dq0(4) dq0(2) dq6(4) dq6(2) dq1(4) dq1(2) dq5(4) dq5(2) dq2(4) dq2(2) dq4(4) dq4(2) dq3(4) dq3(2) dqm4 dqm2 nc vssq vddq vdd vss figure 2: 128-lead package 2.5g (512mb x 5) sdram module
6 2.5g (512mb x 5) sdram module table 1. pin descriptions pin numbers symbols type description 77 clk input clock: clk is driven by th e system clock. all sdram input signals are sampled on the positive edge of clk. clk also incr ements the internal burst counter and controls the output registers. 79 cke input clock enable: cke activates (high) an d deactivates (low) the clk signal. deactivating the clock provides precharge power-down, active power-down (row active in any bank), or clock suspend op eration (burst/access in progress). cke is synchronous except after the device enters power-down where cke becomes asynchronous until after exiting the same mo de. the input buffers, including clk, are disabled during power-down providing low standby power. cke may be tied high. 80 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 78, 76, 75 ras#, cas#, we# input input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. 112, 16, 111, 59, 58 dqm(4:0) input input/output mask: dqm is an input mask signal for write accesses and an output enable signal for read accesses. input da ta is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqm is sample d high during a read cycle. 84 ,82 ba (1:0) input bank address inputs: ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. 81, 83, 86, 85, 87, 89, 91, 93, 95, 94, 92, 90, 88 a(12:0) input address inputs: a0?a12 are sampled during the active command (row-address a0?a12) and read/write command (colum n-address a0?a9, a11); with a10 defining auto precharge) to se lect one location out of the me mory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10[high]) or bank se lected by (a10 [low]) . the address inputs also provide the opcode during a load mode register command. 42, 46, 50, 54, 56, 52, 48, 44 dq[7.0](0) data i/o data input/output 43, 47, 51, 55, 57, 53, 49, 45 dq[7:0](1) data i/o data input/output 127, 123, 119, 115, 113, 117, 121, 125 dq[7:0](2) data i/o data input/output 32, 28, 24, 20, 18, 22, 26, 30 dq[7:0](3) data i/o data input/output
7 128, 124, 120, 116, 114, 118, 122, 126 dq[7:0](4) data i/o data input/output 110 nc no connect: this pin should be left unconnected. 1, 5, 9, 13, 15, 34, 38, 63, 66, 70, 74, 96, 100, 104, 108 vddq supply dq power: isolated dq power to the die for improved noise immunity. 2, 6, 10, 14, 35, 39, 62, 64, 65, 69, 73, 97, 101, 105, 109 vssq supply dq ground: isolated dq ground to the die for improved noise immunity. 4, 8, 12, 37, 41, 60, 67, 71, 99, 103, 107 vdd supply power supply: +3.3v + 0.3v 3, 7, 11, 17, 19, 21, 23, 25, 27, 29, 31, 33, 36, 40, 61, 68, 72, 98, 102, 106 vss supply ground table 1. pin descriptions pin numbers symbols type description
8 package drawing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 14 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 1 106 107 108 109 110 128 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 64 63 62 61 60 42 vddq vssq vss vdd vddq vssq vss vdd vddq vssq vss vdd vddq vssq vddq dqm3 dqm5 dq3(3) dq3(5) dq4(3) dq4(5) dq2(3) dq2(5) dq5(3) dq5(5) dq1(3) dq1(5) dq6(3) dq6(5) dq0(3) dq0(5) dq7(3) dq7(5) vddq vssq vss vdd vddq vssq vss vdd vssq vddq vdd vss vssq vddq vdd vss vssq vddq a4 a3 a5 a2 a6 a1 a7 a0 a8 a10/ap a9 ba1 a11 ba0 a12 cs# cke ras# clk cas# we# vddq vssq vss vdd vddq vssq vss vdd vddq vssq dq7(0) dq7(1) dq0(0) dq0(1) dq6(0) dq6(1) dq1(0) dq1(1) dq5(0) dq5(1) dq2(0) dq2(1) dq4(0) dq4(1) dq3(0) dq3(1) dqm0 dqm1 vdd vss vssq vddq vssq dq7(4) dq7(2) dq0(4) dq0(2) dq6(4) dq6(2) dq1(4) dq1(2) dq5(4) dq5(2) dq2(4) dq2(2) dq4(4) dq4(2) dq3(4) dq3(2) dqm4 dqm2 nc vssq vddq vdd vss figure 3: 128-lead package 3.0g (512mb x 6) sdram module
9 3.0g (512mb x 6) sdram module table 2. pin descriptions pin numbers symbols type description 77 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also incr ements the internal burst counter and controls the output registers. 79 cke input clock enable: cke activates (high) an d deactivates (low) the clk signal. deactivating the clock provides precharg e power-down, active power-down (row active in any bank), or clock suspend op eration (burst/access in progress). cke is synchronous except after the device enters power-down where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down providing low standby power. cke may be tied high. 80 cs# input chip select: cs# enables (registered lo w) and disables (registered high) the command decoder. all commands are mask ed when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 75, 76, 78 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. 16, 17, 58, 59, 111, 112 dqm(5:0) input input/output mask: dqm is an input mask signal for write accesses and an output enable signal for read accesses. input da ta is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqm is sampled high during a read cycle. 82 ,84 ba(1:0) input bank address inputs: ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. 81, 83, 85, 86, 87, 88, 89, 90, 91,92, 93, 94, 95 a(12:0) input address inputs: a0?a12 are sampled during the active command (row-address a0?a12) and read/write command (address a0?a9, a11 with a10 defining auto precharge) to select one locatio n out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10[high]) or bank selected by (a 10 [low]). the address inputs also provide the opcode during a load mode register command. 42, 44, 46, 48, 50, 52, 54, 56 dq(7:0)(0) data i/o data input/output 43, 45, 47, 49, 51, 53, 55, 57 dq[7:0](1) data i/o data input/output 113, 115, 117, 119, 121, 123, 125, 127 dq[7:0](2) data i/o data input/output 18, 20, 22, 24, 26, 28, 30, 32 dq[7:0](3) data i/o data input/output
10 114, 116, 118,120, 122, 124,126, 128 dq[7:0](4) data i/o data input/output 19, 21, 23, 25, 27, 29, 31, 33 dq[7:0](5) data i/o data input/output 110 nc no connect: this pin should be left unconnected. 1, 5, 9, 13, 15, 34, 38, 63, 66, 70, 74, 96, 100, 104, 108 vddq supply dq power: isolated dq power to the die for improved noise immunity. 2, 6, 10, 14, 35, 39, 62, 64, 65, 69, 73, 97, 101, 105, 109 vssq supply dq ground: isolated dq ground to the die for improved noise immunity. 4, 8, 12, 37, 41, 60, 67, 71, 99, 103, 107 vdd supply power supply: +3.3v 0.3v. 3, 7, 11, 36, 40, 61, 68, 72, 98, 102, 106 vss supply ground table 2. pin descriptions pin numbers symbols type description
11 functional description the 2.5g and 3.0g sdrams are organized as 16m x 40 x 4 banks a nd 16m x 48 x 4 banks that operate on 3.3v using a synchronous interface (signals are registered on the pos itive clk edge). read and write accesses to the sdram are burst oriented. accesses start at address locations selected an d continue for programmed numb er of locations in a programm ed sequence. device accesses start with the registration of the active command followed by a read or write command. some addre ss and both bank bits are reg- istered coincident to the active command registration and are used to select the ro w and bank locations, while column location to initiate burst access address bi ts a0-a9 are registered at time of read/write command. previous to normal operation the device must initialized properly. initialization the sdrams must be powered up and initialized in a certain manner. failure to initial devices may result in unpredictable behav ior. once stable power is applied to vdd and vddq (simultaneously), a nd the clock is running and stable (cycling within specified pa - rameters) the device requires a minimum 100 s delay prior to issuing any command ot her than nop or co mmand inhibit. at some time during this period the command in hibit or nop can be issued and should continue through the end of the 100 s period. after the delay has been completed with at least one command inhibit or nop command, a precharge command should be applied. all banks must then be precharged, thereby placing all banks in th e device into the idle state. once in the idle state, two auto refresh cycles must be perfor med. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode regist er powers up in an unknown st ate, it should be loaded pr ior to applying any opera- tional command. the recommended power-up sequence for sdrams: 1. simultaneously apply power to vdd and vddq. 2. assert and hold cke at a lvttl logic low since all inputs and outputs are lvttl-compatible. 3. provide stable clock si gnal. stable clock is defined as a signal cycling within timing constraints speci fied for the clock p in. 4. wait at least 100 s prior to issuing any command other than a command inhibit or nop. 5. starting at some point during this 100 s period, bring cke high. continuing at least through the end of this period, one or more command inhibit or nop commands must be applied. 6. perform a prec harge all command. 7. wait at least t rp time; during this time, nops or deselect commands mu st be given. all banks will complete their precharge, thereby placing the device in the all banks idle state. 8. issue an auto refresh command. 9. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 10. issue an auto refresh command. 11. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 12. the sdram is now ready for mode regist er programming. because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying an y operational command. using the lmr command, program the mode register. the mode register is programmed via the mode register set command with ba1 = 0, ba0 = 0 and retains the stored information until it is programmed again or the device loses powe r. not programming the mode register upon initialization will result in default settings which may not be desired. outputs are guaran teed high-z after the lmr command is issued. outputs should be high-z already before the lmr command is issued. 13. wait at least t mrd time, during which only nop or deselect commands are allowed. at this point, the dram is ready for any valid command. note: if desired, more than two auto refresh commands can be issu ed in the sequence. after steps 9 and 10 are complete, repeat them until the desired number of auto refresch + t rfc loops is achieved. register definition mode register the mode register is used to set a specifi c mode of operation for the sdram. these definitions include burst length (bl), the c as latency (cl), and the write burst mode as shown in figure 4. the mode register is programmed using the load mode register command and retains the stored setting information until either re programmed or device power is lost. mode register bits m0-m2
12 specifies the bl, m3 specifies th e type of burst (sequential or interleaved), m4 -m6 specify the cl, m7 an d m8 specifies the ope ration mode, m9 specifies the write burst mode, m10 and m11 are reserved. address m12 is undefined, but should be driven low during mode register programming. all references to bit(s) mx in this document affect the mode register. burst length (bl) all read and write activity to the sdrams are burst oriented. the burst mode is selected by programming bl as described above. burst length of 1, 2, 4, and 8 locations are available for both sequential and interleav ed burst types. a full page burst is also available in sequential mode only and is used in conjunction with bu rst terminate command to generate arbitrary burst lengths. re- served states for bl should not be used as they may result in undefined operations. whenever a read or write comman d is issued a block of columns is selected that is equal to the bl. all access for that burst ta kes place within this block, m eaning that the burst wraps within the block if a b oundary is reached. the block is uniquely selected by a1- a9, and a11when bl = 2, a2-a9, and a11when bl = 4, a3-a9, and a11when bl = 8. the remaining least significant address bits are used to select the starting location within the block. full-page bursts wrap wi thin the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved: this is referr ed to as the burst type a nd is selected via bit m3. the ordering of the accesses with the burst is determined by bl 1 , the burst type and the staring colu mn address, as shown in table 3.
13 notes: 1. program m12, m11, m10 = ?0, 0, 0? to ensure compatibility with future devices. m9 write burst mode 0 programmed burst length 1 single location access figure 4: mode register definition a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved 1 wb op mode cas latency bt burst length m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved m8 burst type 0 sequential 1 interleaved m2 m1 m0 burst length m3 = 0 m3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved m8 m7 m6-m0 operating mode 0 0 defined standard operation - - - all other states reserved address bus mode register (mx)
14 notes: 1. for full-page accesses: y = 2,048 2. for bl = 2, a1?a9, a11 select the block-of-two bu rst; a0 selects the starting column within the block. 3. for bl = 4, a2?a9, a11 select the block-of-four bur st; a0?a1 select the starting column within the block. 4. for bl = 8, a3?a9, a-11 select the block-of-eight burst; a0?a2 select the startin g column within the block. 5. for a full-page burst, the full row is select ed and a0?a9, a11 sel ect the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for bl = 1, a0?a9, a11 select the unique column to be accessed, and mode register bit m3 is ignored. table 3. burst definition burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 - - a0 - - 0 0-1 0-1 - - 1 1-0 1-0 4 - a1 a0 - 0 0 0-1-2-3 0-1-2-3 - 0 1 1-2-3-0 1-0-3-2 - 1 0 2-3-0-1 2-3-0-1 - 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0-a12/11/9 (location 0-y) cn, cn + 1, cn + 2 cn + 3 cn + 4... ...cn - 1 cn... not supported
15 cas latency (cl) cl is the delay, in clock cycles, between the registration of a read command and the availabi lity of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, as shown in figure 5, assuming that the clock cycle time is such that all relevant access times are met, if a read comman d is registered at t0 and the latency is programmed to two clocks, the dqs start driving after t1 and the data will be valid by t2. table 4 indicates th e operating frequencies at wh ich each cl setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. table 4. cas latency allowable operating frequency (mhz) frequency latency < 100 cl = 2 figure 5: cas latency read nop nop data t3 t2 t1 t0 toh tac tlz cl = 2 clk command dq read nop nop data t3 t2 t1 t0 toh tac tlz cl = 3 clk dq nop command don?t care undefined
16 operating mode the normal operating mode is selected by se tting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with fu ture versions may result. write burst mode when m9 = 0, bl programmed via m0?m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read burst, but write accesse s are single-location (nonburst) accesses. commands table 5 provides a quick reference of avai lable commands. this is followed by a wr itten description of each command. three additional truth tables appear in the op erations section; these tables provide current state/next state information. notes: 1. cke is high for all commands shown. 2. a0?a11 define the op-code written to the mode register, and a12 should be driven low. 3. a0?a12 provide row address, and ba0, ba1 determine which bank is made active. 4. a0?a9, a11 provide column address; a10 high enables the auto precharge feature (non persistent), while a10 low disables the a uto precharge feature; ba0, ba1 determine which bank is bein g read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). command inhibit the command inhibit function prevents new commands from bein g executed by the sdram, regardless of whether the clk signal is enabled. the sdram is ef fectively deselected. op erations already in pr ogress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram that is se lected (cs# is low). this prevents unwanted commands from being registered during idle or wa it states. operations already in progress are not affected. table 5: truth table 1 commands and dqm operation name (function) cs# ras# cas# we# dqm address dqs notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/ row x 3 read (select bank and column, and start read burst) l h l h l/h 8 bank/ col x 4 write (select bank and column, and start write burst) l h l l l/h 8 bank/ col valid 4 burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh l l l h x x x 6, 7 load mode register l l l l x op-code x 4 write enable/output enable -- -- -- -- l -- active 8 write inhibit/output high-z -- -- -- -- h -- high-z 8
17 load mode register the mode register is loaded via inputs a0?a11 (a12 should be driven low). see ?mode register ? on page 13. the load mode register command can only be issued when all banks are idle and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a par ticular bank for a subsequent acces s. the value on the ba0, ba1 inputs selects the bank a nd the address provided on inputs a0?a12 selects the row. this ro w remains active (or open) for access es until a precharge command is issued to th at bank. a precharge command must be is sued before opening a different row in the same bank. read the read command is used to in itiate a burst read access to an active row. the va lue on the ba0, ba1 inpu ts selects the bank an d the address provided on inputs; a0?a9, a11 selects the starting co lumn location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be prechar ged at the end of the read burst; if au to precharge is not selected, the row remains open for subsequent acc esses. read data appears on th e dqs subject to the logic leve l on the dqm inputs two clocks earlier. if a given dqm signal was regi stered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was registered low, the dqs provides valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba 0, ba1 inputs selects the bank, and the address provided on inputs a0?a9, a11 selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the ro w being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subseque nt accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coinci dent with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm sign al is registered high, the corresponding data inputs will be ignored and a write will not be ex ecuted to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks . the bank(s) will be available for a subsequent row access at a specified time (t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case wh ere only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treat ed as ?don?t care.? after a bank has been prech arged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature that performs the same individual-bank precharge functi on described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full- page burst mode, where auto precharge does not apply. auto precharge is non-persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the ear liest valid stage within a burst. the user must not issue anot her command to the same bank until the precharge time (trp) is completed. this is determined as if an explicit precharge command was issued at the earliest po ssible time, as described for each burs t type in the operations section. burst terminate the burst terminate command is used to tr uncate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in the ?operations? section on page 17. the burst terminate command does not precharge the row; the row will remain open until a precharge
18 command is issued. auto refresh auto refresh is used during normal opera tion of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonpers istent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum trp has been met after the precharge co mmand as shown in the operations section. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 512mb sdram requires 8,192 auto refresh cycles every 32ms (tref). providing a distributed auto refresh command every 3.9 s will meet the refresh requirement and ensure that each row is refr eshed. alternatively, 8,192 auto refresh commands can be issued in a burst at the minimum cycle rate (trc), once every 32ms. operations bank/row activation before any read or write commands can be issued to a bank with in the sdram, a row in that bank must be ?opened.? this is accomplished via the active command which selects both the bank and the row to be activated (see figure 6). after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rou nded to 3. this is reflected in figure 7, which covers any cas e where 2 < t rcd (min)/ t ck 3 (the same procedure is used to convert other speci fication limits from time units to clock cycles). a subsequent active command to a different row in the same bank can only be issued after the prev ious active row has been ?closed ? (precharged). the minimum time interv al between successive active comma nds to the same bank is defined by t rc.
19 figure 6: activating a speci fic row in a specific bank don?t care row address bank address t0 clk cke cs# ras# cas# we# address ba figure 7: example meeting t rcd (min) when 2 < t rcd (min)/tck < 3 don?t care active nop nop read or write t3 t2 t1 t0 trcd trcd clk command
20 reads read bursts are initiated with a read command, as shown in figure 8. the starting column and bank addresses are provided with the read command, and auto precharge either is enabled or disabled for that burst access. if auto precharge is en abled, the row being accessed is precharged at the completion of the burst. for the g eneric read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out elem ent from the starting column address will be available following cl after the read command. each subsequent data-out element w ill be valid by the next positive clock edge. figure 9 on page 20 shows general timi ng for each possible cl setting. a subsequent active command to another ba nk can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time in terval between successive active comman ds to different banks is defined by t rrd. figure 8: read command column address bank address enable auto precharge disable auto precharge clk cke cs# ras# cas# we# a0-a9, a11 a12 a10 ba(0,1) don?t care
21 upon completion of a burst, assuming no other commands have b een initiated, the dqs will go high-z. a full-page burst will continue until terminated (at the end of the page, it wraps to the start address and continue). data from any read burst may be truncated with a subsequent re ad command, and data from a fixed-length read bur st may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst either follows the last element of a completed burst or the last desired data element of a long er burst that is being truncated . the new read command should be issued x cycles before the clock edge at which the last desired data element is valid where x = cl - 1. this is shown in figure 9 for cl = 2 and cl = 3; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the sdram uses a pipelined architecture a nd, therefore, does not require the 2 n rule associated with a pre-fetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 11, or each subsequent read may be pe rformed to a different bank. figure 9: cas latency read nop nop data t3 t2 t1 t0 toh tac tlz cl = 2 clk command dq read nop nop data t3 t2 t1 t0 toh tac tlz cl = 3 clk dq nop command don?t care undefined
22 figure 10: consecutive read bursts read nop nop nop read nop nop dout n n+1 n+2 n+3 dout b dout n n+1 n+2 n+3 dout b cl = 3 cl = 2 notes: 1. each read command may be to any bank. dqm is low. t0 t1 t2 t3 t4 t5 t6 t7 clk command address dq(cl=2) dq(cl=3) don?t care transitioning data bank col n bank col b read nop nop nop read nop nop bank dout n dout a dout x dout m dout n dout a dout x dout m t6 t5 t4 t3 t2 t1 t0 cl = 3 cl = 2 notes: 1. each read command may be to any bank. dqm is low. clk command address dq(cl=2) dq(cl=3) don?t care transitioning data col n bank col a bank col x bank col m figure 11: random read accesses
23 data from any read burst may be truncated with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or la st desired) data element from the read burst, provided that i/ o contention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this cas e, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figu re 12 and figure 13. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress dataout from the read. after the write command is regi stered, the dqs go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the wri te command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low du ring t4 in figure 13, then th e writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero cloc ks for input buffers) to ensure that the written data is not masked. figure 12 shows the case where the clock frequency allows for bus contention to be avoided without add- ing a nop cycle, and figure 13 shows the case where the additional nop is needed. figure 12: read-to-write read nop nop nop write bank dout n din b t5 t4 t3 t2 t1 t0 thz tds tck notes: 1. cl = 3 is used for illustration. the read or write command may be to any bank. clk dqm command address dq if a burst of one is used, dqm is not required. don?t care transitioning data col n bank col b
24 a fixed-length read burst may be followed by, or truncated w ith, a prechargecommand to the same bank (provided that auto precharge was not activated), and a full page burst may be truncated with a pr echarge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 14 for each possible cl; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. note: part of the row precharge tim e is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to comple tion, a precharge command issu ed at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires the command and address buses be avai lable at the appropriate time to issue the command. the advantage of the precharge command is it can be used to truncate fixed-length or full-page bursts. full-page read bursts can be truncat ed with the burst terminate command, and fixed-length read bursts may be truncated with a burst terminate comma nd, provided that auto precharge wa s not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 15 for each possible cl; data element n + 3 is the last desired data element of a longer burst. figure 13: read-to-write with extra clock cycle don?t care transitioning data read nop nop nop nop write bank dout n din b t5 t4 t3 t2 t1 t0 thz tds tck tck notes: 1. clk dqm command address dq if a burst of one is used, dqm is not required cl = 3 is used for illustration. the read or write command may be to any bank. col n bank col b
25 figure 14: read-to-precharge read nop nop nop precharge nop nop active bank a, col n bank (a or all) bank a, row dout n n+1 n+2 n+3 dout n n+1 n+2 n+3 cl = 3 cl = 2 notes: 1. dqm is low. t0 t1 t2 t3 t4 t5 t6 t7 clk command address dq(cl = 2) dq(cl = 3) don?t care transitioning data figure 15: terminat ing a read burst read nop nop nop burst nop nop bank col n dout n n+1 n+2 n+3 dout n n+1 n+2 n+3 t6 t5 t4 t3 t2 t1 t0 cl = 3 cl = 2 notes: 1. dqm is low. clk command address dq(cl=2) dq(cl=3) terminate don?t care transitioning data
26 writes write bursts are initiated with a writ e command, as shown in figure 16. the starting column and bank addresses are provided with the write comma nd, and auto precharge is ei ther enabled or disabled for that access. if auto precharge is en abled, the row being accessed is precharged at the completion of th e burst. for the gen eric write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be re gistered coincident with the write command. subsequent data elements will be registered on each successive positive clock e dge. upon completion of a fixed- length burst, assuming no other commands have been initiated, the dqs remains high-z and any additio nal input data will be ignored (see figure 17 on page 26). a full-page burst will continue until terminated (at the end of the page, it will wrap to the start address and continue). data f or any write burst may be truncated with a subs equent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coincident w ith the new command applies to the new comm and. an example is shown in figure 18. data n + 1 is either the last of a burst of two or the last desire d of a longer burst. the 512mb sdram uses a pipelined architecture and, therefore, does not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. fu ll-speed random write accesses within a pa ge can be performed to the same bank, as shown in figure 19, or each subsequent write may be performed to a different bank. figure 16: write command don?t care column address bank address t0 enable auto precharge disable auto precharge clk cke cs# ras# cas# we# a[0-9], a11 a10 ba(0,1) a12
27 figure 17: write burst write nop nop nop bank col n din n din n+1 t3 t2 t1 t0 notes: 1. bl = 2. dqm is low. clk command a dq don?t care transitioning data figure 18: write-to-write write nop write bank col n bank col b din n din n+1 din b notes: 1. dqm is low. each write command may bo to any bank. clk command address dq don?t care transitioning data t2 t1 t0
28 figure 19: random write cycles write write write write bank col. n bank col. a bank col. x bank col. m din n din a din x din m notes: 1. dqm is low. each write command may be to any bank. clk command a dq t0 t1 t2 t3 transitioning data figure 20: write-to-read write nop read nop nop nop bank col. n bank col. b din n din n+1 dout b dout b+1 tck notes: t0 t1 t2 t3 t4 t5 t6 clk command address dq the write or read command may be to any bank. dqm is low don?t care transitioning data
29 data for a fixed-length write burst may be followed by, or tr uncated with, a precharge comman d to the same bank (provided that auto precharge was not act ivated), and a full-page write burst may be tr uncated with a precharge command to the same bank. the precharge command should be issued twr after the cl ock edge at which the last desired input data element is registered. the auto precharge mode requires a twr of at least one clock plus time, regardless of frequency. in addition, when truncating a write burst, the dqm signal mu st be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 21. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. the precharge can be issu ed coincident with the first coincident s econd clock (figure 21). in the case of a f ixed- length burst being executed to completion, a precharge command is sued at the optimum time (as de scribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires th at the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-leng th or full-page bursts. fixed-length or full- page write bursts can be truncated with the burst terminate command. when truncating a wr ite burst, the input data applied coincident with the burst terminate command will be i gnored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 22, where data n is the last desired data element of a longer burst. figure 21: write-to-precharge write nop precharge nop nop active nop bank a, col n bank (a or all) bank a, row din n din n+1 write nop nop precharge nop nop active bank a, col n bank (a or all) bank a, row din n din n+1 trp twr trp twr notes: 1. dqm could remain low in this example if the write burst is a fixed length of two. twr = tclk > = 15 ns twr = tclk < 15 ns t0 t1 t2 t3 t4 t5 t6 clk dqm command address dq dqm command address dq don?t care transitioning data twr trp
30 figure 22: terminat ing a write burst write burst terminate next command bank col. n address din n (data) clk command a dq t0 t1 t2 don?t care transitioning data note: dqms are low.
31 precharge the precharge command shown in figure 23 is used to deactivat e the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access at the specified time (trp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case wh ere only one bank is to be precharged, inputs ba0, ba1 select the bank . when all banks are to be precharged, inpu ts ba0, ba1 are treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issue d to that bank. figure 23: precharge command bank address all banks bank selected clk cke cs# ras# cas# we# a(0-9,11,12) a10 ba(0,1) don?t care
32 power-down power-down occurs if cke is registered low coincident with a nop or command i nhibit when no accesses are in progress. if power-down occurs when all banks are idle , this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maximumpower savings while in standby. the device may not remain in the power-down state longer than the refresh period (32ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting tcks). see figure 24. clock suspend the clock suspend mode occurs when a colu mn access/burst is in progress and cke is re gistered low. in the clock suspend mode, the internal clock is deactivated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the ne xt internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended intern al clock edge is ignored; any data present on the dq pins remai ns driven. burst counters are not incremented, as long as th e clock is suspended (see examples in figures 25 and 26). clock suspend mode is exited by registering cke high; the internal clock and related operation resumes on the subsequent positive clock edge. the device may not remain in clock suspend state longer than the refresh period (32ms) since no refresh operations are performed in this mode. figure 24: power-down nop nop active input buffers gated off tcks all banks idle enter power-down mode exit power-down mode clk cke command don?t care tcks trcd tras trc
33 figure 25: clock suspen d during write burst write nop nop nop bank col. n bank col. b din n din n+1 dout b dout b+1 t0 t1 t2 t3 t4 t5 clk cke internal command address dq don?t care transitioning data note: 1. bl = 4 or greater. dm is low. clock figure 26: clock suspen d during read burst read nop nop nop nop nop bank col. n dout n dout n+1 dout n+2 dout n+3 notes: 1. for this example cl = 2, bl = 4 or greater, and dqm is low. t0 t1 t2 t3 t4 t5 t6 clk sysclk cke command address dq don?t care transitioning data
34 burst read/single write the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), re gardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of opera - tion (m9 = 0). concurrent auto precharge an access command to (read or wr ite) another bank, while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurre nt auto precharge. sdrams support concurrent auto precharge. four cases where concurrent au to precharge occurs are defined below. read with auto precharge interrupted by a read (with or without auto precharge): a read to bank m interrupts a read on bank n , cl later. the precharge to bank n begins when the read to bank m is registered (see figure 28). interrupted by a write (with or without auto precharge): a write to bank m interrupts a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begins when the write to bank m is registered (see figure 29). figure 27: read with auto prech arge interrupted by a read nop read ap nop nop nop nop nop page active read with burst of 4 interrupt burst, precharge idle page active read with burst of 4 precharge bank n dout a dout a+1 dout d dout d+1 cl = 3 (bank m) cl = 3 (bank n) trp bank n notes: 1. dqm is low. t0 t1 t2 t3 t4 t5 t6 t7 clk command bankn bankm address dq(cl=3) don?t care transitioning data internal states bank n col a read ap bank m bank m col d trp bank m
35 figure 28: read with auto prech arge interrupted by a write read ap nop nop nop nop nop nop page read with burst of 4 interrupt burst, precharge idle page active write with burst of 4 write back bank n dout a din d din d+1 din d+2 din d+3 cl = 3 (bank n) trp bank n notes: 1. dqm is high at t2 to prevent dout a+1 from contending with din d at t4. internal states t0 t1 t2 t3 t4 t5 t6 t7 t8 clk ccommand bankn bankm address dqm dq(cl=3) active bank n read ap bank m don?t care transitioning data twr bank m col a bank m col d
36 data for any write burst may be truncated with a subsequent read comment, and data for a fixed-length write burst may be immediately followed by a read command. after the read command is registered, the data inputs will be ignored, and writes will not be executed. an example is shown. data n+1 is either the last of a bur st of two or the latest desired of a longer burs t. write with auto precharge interrupted by a read (with or without auto precharge): a read to bank m interrupts a write on bank n when registered, with the data-out appearing cl later. the precharge to bank n begins after twr is met, where twr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (see figure 29). interrupted by a write (with or without auto precharge): a write to bank m interrupts a write on bank n when registered. the precharge to bank n begins after twr is met, where twr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (see figure 30). figure 29: write with auto p recharge interrupted by a read nop write ap nop nop nop nop nop page active read with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 bank n col a bank m cl d din a a+1 dout d d+1 twr bank n notes: 1. dqm is low. t0 t1 t2 t3 t4 t5 t6 t7 clk command bankn bankm address dq(cl=3) bank n read ap bank m internal states trp bank n twr bank m don?t care transitioning data
37 figure 30: write with auto prech arge interrupted by a write nop write ap nop nop nop nop nop page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back bank n din a a+1 a+2 din d d+1 d+2 d+3 twr bank n notes: 1. dqm is low. t0 t1 t2 t3 t4 t5 t6 t7 clk command bankn bankm address dq(cl=3) bank n write ap bank m trp bank n twr bank m col a bank m col d internal states don?t care transitioning data
38 notes: 1. cken is the logic state of cke at clock edge n ; cken - 1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. commandn is the command registered at clock edge n , and actionn is a result of commandn. 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tcks is met). 6. after exiting clock suspend at clock edge n, the device resumes operation and r ecognize the next command at clock edge n + 1. table 6: truth table 2 - cke notes 1-4 apply to entire table; notes appear below. cke n-1 cke n current state command n action n notes l l power-down x maintain power-down clock suspend x maintain clock suspend l h power-down command inhibit or nop exit power-down 5 clock suspend x exit clock suspend 6 h l all banks idle command inhibit or nop power-down entry all banks idle auto refresh reading or writing valid clock suspend entry h h see table 7 table 7: truth table 3 - current state bank n , command to bank n current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle l l h h active (select an d activiate row) l l l h auto refresh 7 l l l l load mode register 7 l l h l precharge 11 row active l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) l h l h read (select column and start new read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (truncate read burst, start precharge) 8 l h h l burst terminate 9
39 notes: 1. this table applies when cken - 1 was high and cken is high (see ta ble 7) and after txsr has been met. 2. this table is bank-specific (except where noted) the curren t state is for a specific bank and the commands shown are those a llowed to be issued to that bank when in that state. exceptions ar e covered in the notes below. 3. current state definitions: idle: the bank has been prech arged, and trp has been met. row active: a row in the bank has been ac tivated, and trcd has been met. no data bursts/accesses and no register accesses are i n progress. read: a read burst has been initiated, w ith auto precharge disabled and has no t yet terminated or been terminated. write: a write burst has been initiated, w ith auto precharge disabled, and has no t yet terminated or been terminated. 4. the following states must not be interrupted by a command issu ed to the same bank. command i nhibit or nop commands or allowa ble commands to the other bank should be issued on any clock ed ge occurring during these states. allowabl e commands to the other bank are determine d by its current state and table 7 and according to table 8. precharging: starts with registration of a precharge command and en ds when trp is met. after trp is met, the bank will be in th e idle state. row activating: starts with registration of an active command and ends when trcd is me t. after trcd is met, the bank will be in the row active state. read with auto starts with registration of a read command with au to precharge enabled and ends wh en trp has been met. after trp is met, the bank precharge enabled: will be in the idle state. write w/auto: starts with registration of a write command with au to precharge enabled and ends wh en trp has been met. after tr p is met, the bank precharge enabled: will be in the idle state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on e ach positive clock edge during these states. refreshing: starts with registratio n of an auto refresh command and ends when trc is met. after trc is met, the sdram will be i n the al banks idle state. accessing mode starts with registration of a load mode register co mmand and ends when tmrd has been met. after tmrd is met, the sdram register: will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when trp is met. after trp is met, all banks will be in the idle state. 6. all states and sequences no t shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the mo st recent read or write burst, regardless of bank. 10. reads or writes listed in the command (a ction) column include reads or writes with auto precharge enabled and reads or writ es with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank. write (auto precharge disabled) l h l h read (select column and start read burst) 10 l h l l write (select column a nd start new write burst) 10 l l h l precharge (truncate write burst, start precharge) 8 l h h l burst terminate 9 table 7: truth table 3 - current state bank n , command to bank n
40 notes: 1. this table applies when cken - 1 was high and ck en is high (see table 6) and after txsr has been met. 2. this table describes alternate bank operation, except where noted; that is, the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the give n command is allowable) . exceptions are covere d in the notes below. 3. current state definitions: idle: the bank has been precharged, and trp has been met. active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in pr ogress. read: a read burst has been initiated, w ith auto precharge disabled , and has not yet terminat ed or been terminated. write: a write burst has been initiated, with auto precharg e disabled, and has not yet te rminated or been terminate read with auto starts with registration of a read command with auto precharg e enabled, and ends when trp has been met. after t rp is met, the precharge enabled: bank will be in the idle state. write with autostarts with registration of a write command with au to precharge enabled, and ends when trp has been met. after t rp is met, the precharge enabled: bank will be in the idle state. table 8: truth table 4 - current state bank n , command to bank m current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging l l h h active (select and activate row) l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 l l h l precharge read (auto precharge disabled) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7, 10 l h l l write (select column and start write burst) 7, 11 l l h l precharge 9 write (auto precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 12 l h l l write (select column a nd start new write burst) 7, 13 l l h l precharge 9 read (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7, 8, 14 l h l l write (select column and start write burst) 7, 8, 15 l l h l precharge 9 write (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 8, 16 l h l l write (select column a nd start new write burst) 7, 8, 17 l l h l precharge 9
41 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command ca nnot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences no t shown are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column incl ude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n initiates the auto precharge command when its burst has been interrupted by bank m ?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (with or wit hout auto precharge), the read to bank m interrupts the read on bank n , cl later (figure 10). 11. for a read without auto precharge in terrupted by a write (with or without auto precharge), the write to bank m interrupts the read on bank n when registered (figure 12 and figure 13). dqm should be used one clock prior to the write comm and to prevent bus contention. 12. for a write without auto precharge interrupted by a re ad (with or without auto prech arge), the read to bank m interrupst the write on bank n when registered (figure 20), with the data-out app earing cl later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 13. for a write without auto precharge interrupted by a wr ite (with or without auto pr echarge), the write to bank m interrupts the write on bank n when registered (figure 18). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge in terrupted by a read (with or withou t auto precharge), the read to bank m interrupts the read on bank n , cl later. the precharge to bank n will begin when the read to bank m is registered (figure 27). 15. for a read with auto precharge inte rrupted by a write (with or without auto precharge), the write to bank m interrupts the read on bank n when registered. dqm should be used two clocks prior to the wr ite command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 28). 16. for a write with auto precharge interrupted by a re ad (with or without auto precharge), the read to bank m interrupts the write on bank n when registered, with the data-out appear ing cl later. the precharge to bank n will begin after twr is met, where twr begins when the read to bank m is registered. the last valid write to bank n will be datain registered one clock prior to the read to bank m (figure 29). 17. for a write with auto precharge in terrupted by a write (with or without auto precharge), the write to bank m interrups the write on bank n when registered. the precharge to bank n begins after twr is met, where tw r begins when the write to bank m is registered. the last valid write to bank n will be data registered one cloc k prior to the write to bank m (figure30).
42 electrical specifications absolute maximum ratings (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may aff ect device reliability and performance. recommended operating conditions (referenced to v ss ) operational environment specifications symbol parameter limits v dd and v ddq dc supply voltage -1.0 to +4.3v v in , v out voltage on any pin relative to v ss -0.3 to v dd +0.3v t stg storage temperature -65 to +150 c p d maximum power dissipation 5w t j maximum junction temperature +125 o c o jc thermal resistance, junction-to-case tbd o c/w symbol parameter limits v dd and v ddq positive supply voltage 3.0 to 3.6v t c case temperature range -40 to 105 o c v in dc input voltage 0v to v ddq total dose 100k rad(si) heavy ion event rate 2 1.1 e-10 events/bit-day
43 dc electrical characterist ics and operating conditions (pre/post-radiation )* notes 1, 4, and 5 apply to entire table. (v dd , v ddq = +3.3v +/-0.3v; unless otherwise noted, tc is per temperature range ordered.) parameter/condition symbol min max units notes input high voltage: logic 1; all inputs v ih 2 v input low voltage: logic 0; all inputs v il 0.8 v input leakage current: any input 0v< v in < v dd (all other pins not under test = 0v) i i -5 5 a output leakage curren t: dqs are disabled; 0v < v out < v ddq i oz -5 5 a output levels: output high voltage (iout = -4ma) v oh 2.4 -- v output low voltage (iout = 4ma) v ol -- 0.4 v i dd specifications and condit ions (pre/post-radiation ) * notes 1, 4, 5, 9, and 11 apply to entire table. (v dd , v ddq = +3.3v +/-0.3v ; unless otherwise noted, tc is per temperature range ordered.) parameter/condition symbol max units notes x40 x48 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 600 720 ma 3, 12, 13, 15 standby current: power-down mode; cke = low; all banks idle i dd 2 17.5 21 ma 15 standby current: active mode; cs# = high cke = high; all banks active after t rcd met; no accesses in progress i dd 3 225 270 ma 3, 10,13, 15 operating current: burst mode; page burst; read or write; all banks active i dd 4 625 750 ma 3, 12, 13, 15 auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 1300 1300 ma 3, 12, 13, 15, 16 t rfc =3.9 s i dd 6 30 36 ma capacitance notes 2 apply to entire table parameter condition symbol max units input capacitance: all other input-only pins f=1mhz @ 0v c in cl 1 tbd pf input/output capacitance: dqs f=1mhz @ 0v c io cl 1 tbd pf
44 ac characteristics and recommended op erating conditions (pre/post-radiation )* notes 4, 5, 6, 7, 8 a nd 9 apply to entire table. ( v dd , v ddq = +3.3v +/-0.3v; unless otherwise noted, tc is per temperat ure range ordered.) symbol parameter min max unit notes t ac(3) access time from clk (p ositive edge) cl=3 5.4 ns t ac(2) access time from clk (positive edge) cl=2 6 t ah address hold time 0.8 ns t as address setup time 1.5 ns t ch clk high-level width 2.5 ns t cl clk low-level width 2.5 ns t ck3 clock cycle time cl=3 7.5 ns t ck2 clock cycle time cl = 2 10 ns 14 t ckh cke hold time 0.8 ns t cks cke setup time 1.5 ns t cmh cs#, rs#, cas#, we#, dqm hold time 0.8 ns t cms cs#, rs#, cas#, we#, dqm setup time 1.5 ns t dh data-in hold time 0.8 ns t ds data-in setup time 1.5 ns t hz3 data-out high-z time cl = 3 5.4 ns t hz2 data-out high-z time cl = 2 6.0 ns t lz data-out low-z time 1 ns t oh data-out hold time (load) 2.7 ns t ohn data-out hold time (no load) 1.8 ns t ras active-to-precharge command 44 120,000 ns t rc active-to-active command period 66 ns t rcd active-to-read or write delay 20 ns t ref refresh period (8,192 rows) 32 ms t rfc auto refresh period 66 ns t rp precharge command period 20 ns t rrd active bank a-to-active bank b command 15 ns t t transition time 0.3 1.2 ns 6 t wr write recovery time 1 clk + 7ns 15 ns
45 ac functional characteristics (pre/post-radiation )* notes 4, 5, 6, 7, 8, and 9apply to entire table. (v dd , v ddq = +3.3v +/-0.3v; unless otherwise noted , tc is per temperature range ordered.) parameter symbol x40 x48 units notes read/write command-to-read/write command t ccd 1 1 t ck cke to clock disable or power-down entry mode t cked 1 1 t ck cke to clock enable or power-down exit setup mode t ped 1 1 t ck dqm input data delay t dqd 0 0 t ck dqm to data mask during writes t dqm 0 0 t ck dqm to data high-z during reads t dqz 2 2 t ck write command to input data delay t dwd 0 0 t ck data-in to active command t dal 5 5 t ck data-in to precharge command t dpl 2 2 t ck last data-in to burst stop command t bdl 1 1 t ck last data-in to new read/write command t cdl 1 1 t ck last data-in to precharge command t rdl 2 2 t ck load mode register comma nd to active or refresh command t mrd 2 2 t ck dataout to high-z form precharge command t roh(3) 3 3 t ck t roh(2) 2 2 t ck
46 notes: * for devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maxi mum tid level procured. 1. all voltages referenced to v ss . 2. measured only for initial qualification and after process or design change that c ould affect this parameter. 3. idd is dependent on output loading and cycle rates. specified values are obtained with mini mum cycle time and the outputs op en. 4. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (?40c tc 105c) is ensured. 5. an initial pause of 100 s is required after power-up, followed by two auto refresh co mmands, before proper device operation is ensured. (vdd and vddq must be powered up simultaneously. vss and v ssq must be at same potential.) the two au to refresh command wake-ups should be rep eated any time the tref refresh requir ement is exceeded. 6. ac characteristics assume t t = 1ns, supplied as a design limit, neither tested nor guaranteed. 7. in addition to meeting the tr ansition rate specification, the clock and cke mu st transit between vih and vil (or between vil and vih) in a monotonic manner. 8. outputs measured at 1.5v with equivalent load: 9. ac timing and i dd tests have vil = 0v and vih = 3v, with timing refere nced to 1.5vcrossover point. if the input transition t ime is longer than 1ns, then the timing is referenced at vil (max) and vih (min) and no longer at the 1.5v crossover point. 10. other input signals are allowe d to transition no more than once every two clocks and are otherwise at valid vih or vil leve ls. 11. idd specifications are tested afte r the device is properly initialized. 12. the idd current will in crease or decrease in a proportiona l amount by the amount the frequency is altered for the test cond ition. 13. address transitions average one transition every two clocks. 14. the clock frequency must remain constant (stable clock is de fined as a signal cycling within timing constraints specified f or the clock pin) during access or precharge states (read, write, including twr, and precha rge commands). cke may be used to reduce the data rate. 15. cl = 2, tck = 7.5ns. 16. cke is high during refresh command period trfc (min) else cke is low. the idd6 limit is actually a nominal value and does n ot result in a fail value. v dd dut zo = 50-ohms v dd c l = 40pf r term 100-ohms test point r term 100-ohms equivalent test load circuit
47 timing diagrams figure 31: initialize and load mode register nop pre nop load nop active code row code row all banks bank tah tas tah tas tcmh tcms tckh tcks tmrd trfc trfc tcl tch trp tck notes: 1. the mode register may be loaded prior to the auto refresh cycles if desired. 2. if cs is high at clock high time, all commands applied are nop. 3. jedec and pc100 specify three clocks. 4. outputs are guaranteed high-z after command is issued. 5. a12 should be a low at tp+1. all banks single bank high-z t0 t1 tn + 1 clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq to +1 tp + 1 tp + 2 tp + 3 don?t care charge mode register nop nop nop auto refresh auto refresh power-up: vdd and clk stable precharge all banks auto refresh auto refresh program mode register 2, 3, 4
48 figure 32: power-down mode pre nop nop nop active row row bank(s) bank all banks idle input buffers gated off while in power-down mode two clock cycles tah tas tcmh tcms tcks tcks tckh tcks note: violating refresh requirements during power down may result in a loss of data. all banks single bank high-z precharge all active banks all banks idle, enter power-down mode t0 t1 t2 tn + 1 tn + 2 clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care exit power-down mode charge tck tch tcl
49 figure 33: clock suspend mode read nop nop nop nop nop write nop column bank bank dout m dout m+1 din e din + 1 tdh thz tac toh tac tlz tds tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks tcl tch tck notes: 1. for this example, bl=2, cl=3 and auto precharge is disabled. 2. a12 = "dont care." high-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care undefined m2 column e 2
50 figure 34: auto-refresh mode nop auto nop row bank(s) bank tah tas tcmh tcms tckh tcks trfc tcl tch trp tck all banks single bank high-z t0 t1 t2 clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care nop pre refresh nop nop active row row trfc auto refresh charge tn+1 tn+1 precharge all active banks
51 figure 35: read - without auto precharge active nop nop read nop nop nop nop row column row row row bank bank dout m m+1 m+2 m+3 thz tac toh tac toh tac tlz cas latency tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trc tras tcl tch trcd tck high-z all banks single bank disable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq t0 t1 t2 t3 t4 t5 t6 t7 t8 notes: 2. a12 = ?don?t care? don?t care undefined pre charge active tac toh toh bank bank trp m 2 1. for this example bl = 4, cl = 2, and the read burst is followed by a ?manual? precharge
52 figure 36: read - with auto precharge active nop nop read nop nop nop nop nop active row column row row row bank bank dout m m+1 m+2 m+3 thz toh tac tlz tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trc trp tras tcl tch trcd tck notes: 1. for this example bl=4, and cl = 2. 2. a12 = "dont care." high-z enable auto precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care undefined tac tac toh tac toh toh nop cas latency bank m 2
53 figure 37: single read - without auto precharge active nop nop read nop nop nop pre nop row column row row row bank dout m thz toh tac tlz tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trc tras tcl tch trcd tck notes: 1. for this example, bl = 1, cl = 2, and the read burst is followed by a manual precharge. 2. a12 = "dont care." high-z all banks single bank disable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 bank bank(s) bank active charge m 2
54 figure 38: single read - with auto precharge active nop nop 3 read nop nop nop row column row row row bank bank dout m thz toh tac tlz cas latency tah tas tah tas tah tas tcmh tcms tckh tcks trp trc tras trcd tcl tch tck notes : 1. for this example, bl=1, and cl = 2. 2. 3. a12 = "dont care." high-z enable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care undefined t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 bank active nop 3 read command not allowed (would violate tras). m 2
55 figure 39: alternatin g bank read accesses active nop nop read nop nop nop read nop active row column row row row row row bank bank 0 bank 3 bank 3 bank 0 dout m m+1 m+2 m+3 dout b tac toh tac tlz cas latency - bank 3 cas latency - bank 0 tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trc - bank 0 trcd - bank 3 tras - bank 0 trrd trcd - bank 0 tck notes: 1. for this example, bl=4, cl = 2. 2. a12 = "dont care." high-z enable auto precharge enable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tcl tch tac toh tac toh tac toh tac toh m 3 column b 3 trp- bank 0 don?t care undefined
56 figure 40: read - full-page burst active nop nop read nop nop nop nop nop burst nop nop row column row bank bank dout m m+1 m+2 m-1 dout m m+1 thz tac toh tac tlz cas latency tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks tcl tch trcd tck notes: 1. for this example, cl = 2. 2. a12 = "dont care" 3. page left open; no trp 1024 locations within same row clk cke command dqm a(10) ba(0,1) dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 don?t care undefined term toh tac tac toh tac toh tac toh toh m 2
57 figure 41: read dqm operation active nop nop read nop nop nop nop nop nop row column m row bank dout m m+2 m+3 thz toh toh tac tlz toh tac tlz tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks tcl tch tck notes: 1. for this example, bl=4, and cl = 2 2. a12 = "dont care" high-z enable auto precharge disable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 don?t care undefined bank cas latency trcd tac tac
58 figure 42: write - without auto precharge active nop nop write nop nop nop nop nop pre nop nop row column row row row bank din m m+1 m+2 m+3 tdh tds tdh tds tdh tds tdh tds tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trp trc twr 3 tras tcl tch trcd tck notes: 1. for this example, bl= 4, and the write burst is followed by a manual precharge. 2. 14ns to 15 ns is required between and the precharge command, regardless of frequency. 3. a12 = "dont care." all banks single bank disable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 charge active bank bank bank bank m 3
59 figure 43: write - with auto precharge active nop nop write nop nop nop nop nop nop nop row column row row row bank din m m+1 m+2 m+3 tdh tds tdh tds tdh tds tdh tds tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trp trc twr tras tcl tch trcd tck notes: 1. for this example, bl= 4. 2. a12 = "dont care." enable auto precharge clk cke dqm a(10) ba(0,1) dq don?t care t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 active bank bank bank nop m 2
60 figure 44: single write - without auto precharge active nop nop write nop nop nop nop nop pre nop nop row column row row row bank din m m+1 m+2 m+3 tdh tds tdh tds tdh tds tdh tds tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trp trc twr 2 tras tcl tch trcd tck notes: 1. for this example, bl= 1, and the write burst is followed by a manual precharge. 2. 14ns to 15ns is required between and the precharge command, regardless of frequency. 3. a12 = "dont care." all banks single bank disable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 charge active bank bank bank bank 4. precharge command not allowed else t ras would be violated. m 3
61 figure 45: single write - with auto precharge active nop 4 write nop nop nop nop row row row row bank bank din m cas latency tdh tds tah tas tcmh tcms tckh tcks trp trc twr 2 tras trcd 3 tcl tch tck enable auto precharge notes: 1. for this example, bl = 1, and the write burst is followed by a manual precharge. 2. 3. a12 = "dont care." 4. precharge command not allowed (would violate tras). 14 to 15 ns is required between and the precharge command, regardless of the frequency. don?t care clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq column t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tah tas tah tas bank m 3 active nop 4 nop 4
62 figure 46: alternating bank write accesses active nop nop write nop nop nop active row column row row row row row bank 0 bank 0 bank 1 bank 1 bank 0 cas latency - bank 1 cas latency - bank 0 tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks trc - bank 0 trcd - bank 1 tras - bank 0 trrd trcd - bank 0 tck enable auto precharge enable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tcl tch active write m 3 column b 3 din m m+1 m+2 m+3 din b b+1 b+2 tdh tds dq notes: 1. for this example, bl=4, cl=2. 2. requires one clock plus time (7ns to 7.5ns) with auto precharge or 14 to 15ns with precharge. 3. a12 = "dont care." don?t care twr - bank 0 trp - bank 0
63 figure 47: write full-page burst active nop nop write nop nop nop nop burst nop row column row bank bank din m m+1 m+2 m+3 din m-1 tdh tds tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks tcl tch trcd tck notes: 1. a12 = "dont care." 2. twr must be satisfied prior to precharge command. 3. page left open; no trp. 2048 locations within same row full-page burst does can use burst terminate clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq t0 t1 t2 t3 t4 t5 t6 tn+1 tn+2 tn+3 don?t care terminate m 1 not self-terminate. command to stop. full page completed
64 figure 48: write - dqm operation active nop nop write nop nop nop nop nop row column row bank bank din m m+2 m+3 tdh tds tah tas tah tas tah tas tcmh tcms tcmh tcms tckh tcks tcl tch trcd tck notes: 1. for this example, bl=4. 2. a12 = "dont care." enable auto precharge disable auto precharge clk cke command dqm a(0:9,11:12) a(10) ba(0,1) dq don?t care undefined t0 t1 t2 t3 t4 t5 t6 t7 t8 m 2
65 packaging figure 49: 128-lead flatpack
66 ordering information 64meg x 40 sdram 64meg x 48 sdram access time: (75) = 7.5ns cycle time @ cl=3 (pci33) package type: (x) = 128-lead ceramic, side brazed, dual cavity, quad flatpack screening: (notes 2 and 3) (e) = hirel flow (temperature range: -40 o c to +105 0 c) (p) = prototype flow (temperature range: 25 o c only) device type: (8sdmq64m40) = 64meg x 40 (8sdmq64m48) = 64meg x 48 lead finish: (note 1) (c) = gold notes: 1. lead finish is "c" (gold) only, and must be specified. 2. prototype flow per aeroflex manufacturing flows document. devices are tested at 25 o c only. radiation is neither tested nor guaranteed. 3. hirel flow per aeroflex manufacturing flows docu ment. radiation is neither tested nor guaranteed. ut ********** - ** * * *
67 64meg x 40 sdram: smd 64meg x 48 sdram: smd 5962 - ***** ** * * * notes : 1. lead finish is "c" (gold) only. 2. aeroflex?s q+ assembly flow, as defined in section 4.2.2.d of the smd, provides qml q product through the smd that is manufa ctured with aeroflex?s standard qml v flow. federal stock class designator: no options total dose (-) = none (d) = 1e4 (10krad(si)) (p) = 3e4 (30krad(si)) (l) = 5e4 (50krad(si)) (r) = 1e5 (100krad(si)) drawing number: 10229: 2.5g sdram (64 meg x 40) 10230: 3.0g sdram (64 meg x 48) device type ( note 2 ) (01) = sdram (-40 o c to +105 o c) (02) = sdram assembled to aeroflex q+ flow (-40 o c to +105 o c) class designator: (q) = qml class q case outline: (x) = 128-lead ceramic quad flatpack, side brazed, dual cavity lead finish: note 1 (c) = gold
68 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs (aeroflex) reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel

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