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rev.5.00, sep.11.2003, page 1 of 161 hd404374/hd404384/hd404389/ hd404082/hd404084 series low-voltage as microcomputers with on-chip a/d converter rej03b0050-0500h rev.5.00 sep.11.2003 description the hd404374, hd404384, and hd404389 series comprise low-voltage, 4-bit single-chip microcomputers equipped with four 10-bit a/d converter channels, a serial interface, and large-current i/o pins. these devices are suitable for use in applications requiring high resolution a/d converter control, such as battery chargers. the hd404082 and hd404084 series offer less advanced features than the hd404384 series. they are 4- bit microcomputers that support low-voltage operation for backward software compatibility. hd404374 series microcomputers have a 32.768 khz sub-resonator for realtime clock use, providing a time counting facility, and a variety of low-power modes to reduce current drain. the hd407a4374, hd407a4384, hd407a4389, hd407c4374, hd407c4384, and hd407c4389 are ztat tm microcomputers with on-chip prom that drastically shortens development time and ensures a smooth transition from debugging to mass production. (the prom programming specifications are the same as for the 27256 type.) ztat tm : zero turn-around time. ztat tm is a trademark of renesas technology corp. features ? 20 i/o pins large-current i/o pins (source: 10 ma max.):4 large-current i/o pins (sink: 15 ma max.):4 analog input multiplexed pins: 4 (hd404374, hd404384, and hd404389 series) ? 8-bit timer: 1 channel 16-bit timer: 1 channel (can also be used as two 8-bit timer channels) ? two timer outputs (including pwm output) ? event counter inputs (edge-programmable) ? clock-synchronous 8-bit serial interface ? a/d converter 4 channels 10-bits (hd404374 and hd404384 series) 6 channels 10-bits (hd404389 series) none (hd404082 and hd404084 series)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 2 of 161 ? on-chip oscillators ? hd404374 series ? main clock (ceramic resonator, crystal resonator, cr oscillation* or external clock operation possible) ? sub-clock (32.768 khz crystal resonator) ? hd404384, hd404389, hd404082, and hd404084 series ? main clock (ceramic resonator, crystal resonator, cr oscillation* or external clock operation possible) note: * cr oscillation in an optional function. ? interrupts external: 2 (including one edge-programmable) internal : 5 (hd404374/hd404384/hd404389 series) : 4 (hd404082/hd404084 series) ? subroutine stack up to 16 levels, including interrupts ? low-power dissipation modes ? hd404374 series: 4 ? hd404384, hd404389, hd404082, and hd404084 series: 2 ? module standby (timers, serial interface, a/d converter) ? system clock division software switching (1/4 or 1/32) ? inputs for return from stop mode (wakeup): 1 ? instruction execution time min. 0.89 s (f osc = 4.5 mhz, division by 1/4) min. 0.47 s (f osc = 8.5 mhz, division by 1/4) ? operation voltage 1.8 v to 5.5 v 2.0 v to 5.5 v (ztat tm ) cautions about operation! ? electrical properties presented on the data sheet for the mask rom and ztat tm versions will surely and sufficiently satisfy the standard values. however, real capabilities, operation margin, noise margin, and other properties may vary depending on differences of manufacturing processes, internal wiring patterns, etc. therefore, it is requested for users to carry out an evaluation test for each product on an actual system under the same conditions to see its operation. ? after power supply has been connected, the values for the memory register, data and stack areas will be undefined. initialize prior to use.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 3 of 161 ordering information hd404374 series type product name model name rom (words) ram (digits) package hd404372ft 30-pin plastic ssop(fp-30d) hd404372 hd404372h 48-pin plastic lqfp(fp-48b) * 1 hd40a4372ft 30-pin plastic ssop(fp-30d) hd40a4372 hd40a4372h 48-pin plastic lqfp(fp-48b) * 1 hd40c4372ft 30-pin plastic ssop(fp-30d) hd40c4372 hd40c4372h 2,048 48-pin plastic lqfp(fp-48b) * 1 hd404374ft 30-pin plastic ssop(fp-30d) hd404374 hd404374h 48-pin plastic lqfp(fp-48b) * 1 hd40a4374ft 30-pin plastic ssop(fp-30d) hd40a4374 hd40a4374h 48-pin plastic lqfp(fp-48b) * 1 hd40c4374ft 30-pin plastic ssop(fp-30d) mask rom hd40c4374 hd40c4374h 4,096 48-pin plastic lqfp(fp-48b) * 1 hd407a4374 hd407a4374ft 30-pin plastic ssop (fp-30d) ztat tm hd407c4374 hd407c4374ft 4,096 512 30-pin plastic ssop(fp-30d)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 4 of 161 hd404384 series type product name model name rom (words) ram (digits) package hd404382ft 30-pin plastic ssop (fp-30d) hd404382s 28-pin plastic dilp (dp-28s) hd404382 hd404382h 48-pin plastic lqfp (fp-48b) * 1 hd40a4382ft 30-pin plastic ssop (fp-30d) hd40a4382s 28-pin plastic dilp (dp-28s) hd40a4382 hd40a4382h 48-pin plastic lqfp (fp-48b) * 1 hd40c4382ft 30-pin plastic ssop (fp-30d) hd40c4382s 28-pin plastic dilp (dp-28s) hd40c4382 hd40c4382h 2,048 48-pin plastic lqfp (fp-48b) * 1 hd404384ft 30-pin plastic ssop (fp-30d) hd404384s 28-pin plastic dilp (dp-28s) hd404384 hd404384h 48-pin plastic lqfp (fp-48b) * 1 hd40a4384ft 30-pin plastic ssop (fp-30d) hd40a4384s 28-pin plastic dilp (dp-28s) hd40a4384 hd40a4384h 48-pin plastic lqfp (fp-48b) * 1 hd40c4384ft 30-pin plastic ssop (fp-30d) hd40c4384s 28-pin plastic dilp (dp-28s) mask rom hd40c4384 hd40c4384h 4,096 48-pin plastic lqfp (fp-48b) * 1 hd407a4384ft 30-pin plastic ssop (fp-30d) hd407a4384 hd407a4384s 28-pin plastic dilp (dp-28s) hd407c4384ft 30-pin plastic ssop (fp-30d) ztat tm hd407c4384 hd407c4384s 4,096 512 28-pin plastic dilp (dp-28s)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 5 of 161 hd404389 series type product name model name rom (words) ram (digits) package hd404388 hd404388ft hd40a4388 hd40a4388ft hd40c4388 hd40c4388ft 8,192 hd404389 hd404389ft hd40a4389 hd40a4389ft mask rom hd40c4389 hd40c4389ft 16,384 hd407a4389 hd407a4389ft ztat tm hd407c4389 hd407c4389ft 16,384 512 30-pin plastic ssop (fp-30d)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 6 of 161 hd404082 series type product name model name rom (words) ram (digits) package hd404081ft 30-pin plastic ssop (fp-30d) hd404081s 28-pin plastic dilp (dp-28s) hd404081 hd404081h 48-pin plastic lqfp (fp-48b) * 2 HD40A4081FT 30-pin plastic ssop (fp-30d) hd40a4081s 28-pin plastic dilp (dp-28s) hd40a4081 hd40a4081h 48-pin plastic lqfp (fp-48b) * 2 hd40c4081ft 30-pin plastic ssop (fp-30d) hd40c4081s 28-pin plastic dilp (dp-28s) hd40c4081 hd40c4081h 1,024 48-pin plastic lqfp (fp-48b) * 2 hd404082ft 30-pin plastic ssop (fp-30d) hd404082s 28-pin plastic dilp (dp-28s) hd404082 hd404082h 48-pin plastic lqfp (fp-48b) * 2 hcd404082 hcd404082 chip hd40a4082ft 30-pin plastic ssop (fp-30d) hd40a4082s 28-pin plastic dilp (dp-28s) hd40a4082 hd40a4082h 48-pin plastic lqfp (fp-48b) * 2 hd40c4082ft 30-pin plastic ssop (fp-30d) hd40c4082s 28-pin plastic dilp (dp-28s) hd40c4082 hd40c4082h 48-pin plastic lqfp (fp-48b) * 2 mask rom hcd40c4082 hcd40c4082 2,048 128 chip ztat tm uses hd404384 series ztat tm . notes: 1. the fp-48b is subject to the following limitations: (1) it is available in a mask rom version only. for debugging, etc., the ztat tm version of a different package will need to be used. (2) the ws version will become available at the beginning of mass production. 2. currently in planning stage.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 7 of 161 hd404084 series type product name model name rom (words) ram (digits) package hd404084ft 30-pin plastic ssop (fp-30d) hd404084 hd404084s 28-pin plastic dilp (dp-28s) hcd404084 hcd404084 chip hd40a4084ft 30-pin plastic ssop (fp-30d) hd40a4084 hd40a4084s 28-pin plastic dilp (dp-28s) hd40c4084ft 30-pin plastic ssop (fp-30d) hd40c4084 hd40c4084s 28-pin plastic dilp (dp-28s) mask rom hcd40c4084 hcd40c4084 4,096 256 chip ztat tm uses hd404384 series ztat tm
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 8 of 161 list of functions product name hd404372, hd40a4372, hd40c4372 hd404374, hd40a4374, hd40c4374, hd407a4374, hd407c4374 hd404382, hd40a4382, hd40c4382 hd404384, hd40a4384, hd40c4384, hd407a4384, hd407c4384 hd404388, hd40a4388, hd40c4388 rom(words) 2,048 4,096 ztat prom 2,048 4,096 ztat prom 8,192 ram (digit) 512 20 (max) large-current i/o pins 4 (source, 10 ma max), 4 (sink, 15 ma max) i/o analog input multiplexed pins 4 3 timer output 2 (pwm output possible) timer/ counter event input 1 (edge selection possible) serial interface 1 (8-bit synchronous) a/d converter 10 bits 4 channels 10 bits 6 channels interrupt external 2 sources internal 5 4 2 stop mode available watch mode available ? standby mode available low-power modes subactive mode available ? module standby available system clock division software switching available main oscillator ceramic oscillation available crystal oscillation available cr oscillation available (hd40c4372, hd40c4374, hd407c4374, hd40c4382, hd40c4384, hd407c4384, hd40c4388, hd40c4389, hd407c4389, hd40c4081, hd40c4082, hcd40c4082, hd40c4084, hcd40c4084) sub-oscillator crystal oscillation available (32.768khz) ?
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 9 of 161 product name hd404372, hd40a4372, hd40c4372 hd404374, hd40a4374, hd40c4374, hd407a4374, hd407c4374 hd404382, hd40a4382, hd40c4382 hd404384, hd40a4384, hd40c4384, hd407a4384, hd407c4384 hd404388, hd40a4388, hd40c4388 0.47 ms (f osc = 8.5 mhz) : hd40a4372, hd40a4374, hd407a4374, hd40a4382, hd40a4384, hd407a4384, hd40a4388, hd40a4389, hd407a4389, hd40a4081, hd40a4082, hd40a4084 0.89 ms (f osc = 4.5 mhz) : hd404372, hd404374, hd404382, hd404384, hd404388, hd404389, hd404081, hd404082, hcd404082, hd404084, hcd404084 minimum instruction execution time 1.14 ms (f osc = 3.5 mhz) : hd40c4372, hd40c4374, hd407c4374, hd40c4382, hd40c4384, hd407c4384, hd40c4388, hd40c4389, hd407c4389, hd40c4081, hd40c4082, hcd40c4082, hd40c4084, hcd40c4084 operating voltage (v) 1.8 to 5.5 v : mask rom, 2.0 to 5.5 v : ztattm fp-30d available dp-28s ? available ? package fp-48b available ? chip ? guaranteed operation temperature( c) ? 20 to +75: mask rom ? 40 to +85: ztat tm
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 10 of 161 product name hd404389, hd40a4389, hd40c4389, hd407a4389, hd407c4389 hd404081, hd40a4081, hd40c4081 hd404082, hd40a4082, hd40c4082 hcd404082, hcd40c4082 hd404084, hd40a4084, hd40c4084 hcd404084, hcd40c4084 rom(words) 16,384 ztat prom 1,024 2,048 4,096 ram (digit) 512 128 20 (max) large-current i/o pins 4 (source, 10 ma max), 4 (sink, 15 ma max) i/o analog input multiplexed pins 4 ? 3 timer output 2 (pwm output possible) timer/ counter event input 1 (edge selection possible) serial interface 1 (8-bit synchronous) a/d converter 10 bits 6 channels ? e x t e r n a l 2 interrupt sources internal 5 4 low-power 4 stop mode available watch mode available standby mode available modes subactive mode available module standby available system clock division software switching available ceramic oscillation available crystal oscillation available main oscillator cr oscillation available (hd40c4372, hd40c4374, hd407c4374, hd40c4382, hd40c4384, hd407c4384, hd40c4388, hd40c4389, hd407c4389, hd40c4081, hd40c4082, hcd40c4082, hd40c4084, hcd40c4084) sub-oscillator crystal oscillation ?
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 11 of 161 product name hd404389, hd40a4389, hd40c4389, hd407a4389, hd407c4389 hd404081, hd40a4081, hd40c4081 hd404082, hd40a4082, hd40c4082 hcd40482, hcd40c4082 hd404084, hd40a4084, hd40c4084 hcd404084, hcd40c4084 0.47 s (f osc = 8.5 mhz) : hd40a4372, hd40a4374, hd407a4374, hd40a4382, hd40a4384, hd407a4384, hd40a4388, hd40a4389, hd407a4389, hd40a4081, hd40a4082, hd40a4084 0.89 s (f osc = 4.5 mhz) : hd404372, hd404374, hd404382, hd404384, hd404388, hd404389, hd404081, hd404082, hcd404082, hd404084, hcd404084 minimum instruction execution time 1.14 s (f osc = 3.5 mhz) : hd40c4372, hd40c4374, hd407c4374, hd40c4382, hd40c4384, hd407c4384, hd40c4388, hd40c4389, hd407c4389, hd40c4081, hd40c4082, hcd40c4082, hd40c4084, hcd40c4084 operating voltage (v) 1.8 to 5.5 v : mask rom, 2.0 to 5.5 v : ztat tm fp-30d available dp-28s ? available ? available ? package fp-48b ? in planning stage ? chip ? available ? available guaranteed operation temperature( c) ? 20 to +75: mask rom ? 40 to +85: ztat tm +75 ? 20 to +75: mask rom ? 40 to +85: ztat tm +75
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 12 of 161 pin arrangement gnd vcc avcc r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 avss osc 1 ocs 2 test x2 x1 r0 0 / 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 / 0 r2 2 /si/so r2 1 / r2 0 /toc r1 3 /tob r1 0 /evnb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fp-30d (top view) p-mos large current pins n-mos large current pins hd404374 series 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 d 5 d 4 nc d 3 nc d 2 nc d 1 nc d 0 / 0 nc r2 2 /si/so r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 nc av ss osc 1 nc osc 2 nc test x2 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 x1 nc nc r0 0 / 0 nc r1 0 /evnb nc r1 3 /tob nc r2 0 /toc r2 1 / av cc v cc nc gnd nc d 9 nc nc d 8 d 7 nc d 6 fp-48b (top view) p-mos large current pins n-mos large current pins
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 13 of 161 gnd vcc avcc r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 avss osc 1 ocs 2 test nc nc r0 0 / 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 / 0 r2 2 /si/so r2 1 / r2 0 /toc r1 3 /tob r1 0 /evnb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fp-30d (top view) p-mos large current pins n-mos large current pins gnd vcc avcc r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 avss osc 1 ocs 2 test r0 0 / 0 r1 0 /evnb d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 / 0 r2 2 /si/so r2 1 / r2 0 /toc r1 3 /tob 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dp-28s (top view) p-mos large current pins n-mos large current pins hd404384 series 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 d 5 d 4 nc d 3 nc d 2 nc d 1 nc d 0 / 0 nc r2 2 /si/so r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 nc av ss osc 1 nc osc 2 nc test nc 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 nc nc nc r0 0 / 0 nc r1 0 /evnb nc r1 3 /tob nc r2 0 /toc r2 1 / av cc v cc nc gnd nc d 9 nc nc d 8 d 7 nc d 6 fp-48b (top view) n-mos large current pins n-mos large current pins
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 14 of 161 gnd vcc avcc r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 an 4 an 5 av ss test osc 1 osc 2 r0 0 / 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 / 0 r2 2 /si/so r2 1 / r2 0 /toc r1 3 /tob r1 0 /evnb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fp-30d (top view) p-mos large current pins n-mos large current pins hd404389 series 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 / 0 r2 2 /si/so r2 1 / r2 0 /toc r1 3 /tob r1 0 /evnb gnd v cc nc r7 0 r7 1 r7 2 r7 3 nc osc 1 osc 2 test nc nc r0 0 / 0 fp-30d (top view) p-mos large current pins n-mos large current pins 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 / 0 r2 2 /si/so r2 1 / r2 0 /toc r1 3 /tob gnd v cc nc r7 0 r7 1 r7 2 r7 3 nc osc 1 osc 2 test r0 0 / 0 r1 0 /evnb dp-28s (top view) p-mos large current pins n-mos large current pins hd404082 and hd404084 series
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 15 of 161 pad arrangement hcd404082 and hcd404084 4 5 6 7 8 9 10 11 12 13 14 15 2 1 26 25 24 23 22 21 20 19 18 17 16 model name model name: hd404082 (hcd404082) hd404084 (hcd404084) 3
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 16 of 161 pad coordinates hcd404082 and hcd404084 chip size (x y): coordinates: home point position: pad size (x y): chip thickness: 4.63 4.77 (mm) pad center chip center 90 90 (m) 280 (m) chip center (x=0,y=0) y x mold coodinates coodinates pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 gnd -458 1403 14 r2 0 572 -1403 2 v cc -826 1403 15 r2 1 982 -1403 3 r7 0 -1338 1403 16 r2 2 1338 -1403 4 r7 1 -1338 1006 17 d 0 1338 -1020 5 r7 2 -1338 525 18 d 1 1338 -637 6 r7 3 -1338 285 19 d 2 1338 -254 7 osc1 -1338 -550 20 d 3 1338 129 8 osc2 -1338 -954 21 d 4 1338 768 9 test -1338 -1251 22 d 5 1338 1170 10 resetn -1197 -1403 23 d 6 1153 1403 11 r0 0 -577 -1403 24 d 7 751 1403 12 r1 0 -194 -1403 25 d 8 349 1403 13 r1 3 189 -1403 26 d 9 -53 1403
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 17 of 161 pin description hd404374 and hd404384 series pin number item symbol fp-30d dp-28s * 2 dp-48b i/o function v cc 2 2 47 ? apply the power supply voltage to this pin. power supply gnd 1 1 45 ? connect to ground. test test 11 11 11 input not for use by the user application. connect to gnd potential. reset reset 14 12 15 input used to reset the mcu. osc 1 9 9 7 input internal oscillator input/output pins. connect a ceramic resonator, crystal resonator, or external oscillator circuit. osc 2 10 10 9 output when using cr oscillation, connect a resistor. x1 13* 1 ? 13 * 1 input realtime clock oscillator input/output pins. connect a 32.768 khz crystal. if 32.768 khz crystal oscillation is not used, fix the oscillation x2 12* 1 ? 12 * 1 output x1 pin to v cc and leave the x2 pin open. d 0 ?d 9 21?30 19?28 27, 29, 31, 33, 35? 37, 39, 40, 43 i/o i/o pins addressed bit by bit. d 0 to d 3 are large-current source pins (max. 10 ma), and d 4 to d 9 are large-current sink pins (max. 15 ma). port r0 0 , r1 0 , r1 3 , r2 0 , r2 1 , r2 2 , r7 0 ?r7 3 15?20, 4?7 13?18, 4?7 17, 19, 21, 23?25, 1?4 i/o i/o pins, addressed in 4-bit units. interrupt int 0 21 19 27 input external interrupt input pin wakeup wu 0 15 13 17 input input pin used for transition from stop mode to active mode. sck 19 17 24 i/o serial interface clock i/o pin si 20 18 25 input serial interface receive data input pin serial interface so 20 18 25 output serial interface transmit data output pin tob,toc 17, 18 15, 16 21, 23 output timer output pins timer evnb 16 14 19 input event count input pin av cc 3 3 48 ? a/d converter power supply pin. connect as close as possible to the v cc pin so as to be at the same potential as v cc . av ss 8 8 6 ? ground pin for av cc . connect as close as possible to the gnd pin so as to be at the same potential as gnd. a/d converter an 0 ?an 3 4?7 4?7 1?4 input a/d converter analog input pins other nc 12 * 2 , 13* 2 ? 5, 8, 10, 12 * 2 , 13 * 2 , 14, 16, 18, 20, 22, 26, 28, 30, 32, 34, 38, 41, 42, 44, 46 ? connect to gnd potential. notes: * 1 applies to hd404374 series. * 2 applies to hd404384 series.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 18 of 161 hd404389 series pin number item symbol fp-30d i/o function v cc 2 ? apply the power supply voltage to this pin. power supply gnd 1 ? connect to ground. test test 11 input not for use by the user application. connect to gnd potential. reset reset 14 input used to reset the mcu. osc 1 12 input internal oscillator input/output pins. connect a ceramic resonator, crystal resonator, or external oscillator circuit. oscillation osc 2 13 output when using cr oscillation, connect a resistor. d 0 ? d 9 21? 30 i/o i/o pins addressed bit by bit. d 0 to d 3 are large-current source pins (max. 10 ma), and d 4 to d 9 are large-current sink pins (max. 15 ma). port r0 0 , r1 0 , r1 3 , r2 0 , r2 1 , r2 2 , r7 0 ? r7 3 15? 20, 4 ? 7 i/o i/o pins, addressed in 4-bit units. interrupt int 0 21 input external interrupt input pin wakeup wu 0 15 input input pin used for transition from stop mode to active mode. sck 19 i/o serial interface clock i/o pin si 20 input serial interface receive data input pin serial interface so 20 output serial interface transmit data output pin tob,toc 17, 18 output timer output pins timer evnb 16 input event count input pin av cc 3 ? a/d converter power supply pin. connect as close as possible to the v cc pin so as to be at the same potential as v cc . av ss 10 ? ground pin for av cc . connect as close as possible to the gnd pin so as to be at the same potential as gnd. a/d converter an 0 ? an 5 4 ? 9 input a/d converter analog input pins
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 19 of 161 hd404082 and hd404084 series pin number item symbol fp-30d dp-28s chip i/o function v cc 2 2 2 ? apply the power supply voltage to this pin. power supply gnd 1 1 1 ? connect to ground. test test 11 11 9 input not for use by the user application. connect to gnd potential. reset reset 14 12 10 input used to reset the mcu. osc 1 9 9 7 input internal oscillator input/output pins. connect a ceramic resonator, crystal resonator, or external oscillator circuit. oscillation osc 2 10 10 8 output when using cr oscillation, connect a resistor. d 0 ? d 9 21? 30 19 ? 28 17? 26 i/o i/o pins addressed bit by bit. d 0 to d 3 are large-current source pins (max. 10 ma), and d 4 to d 9 are large-current sink pins (max. 15 ma). port r0 0 , r1 0 , r1 3 , r2 0 , r2 1 , r2 2 , r7 0 ? r7 3 15? 20, 4 ? 7 13 ? 18, 4 ? 7 11? 16, 3 ? 6 i/o i/o pins, addressed in 4-bit units. interrupt int 0 21 19 17 input external interrupt input pin wakeup wu 0 15 13 11 input input pin used for transition from stop mode to active mode. sck 19 17 15 i/o serial interface clock i/o pin si 20 18 16 input serial interface receive data input pin serial interface so 20 18 16 output serial interface transmit data output pin tob,toc 17, 18 15, 16 13, 14 output timer output pins timer evnb 16 14 12 input event count input pin other nc 3, 8, 12, 13 3, 8 ? ? connect to gnd potential.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 20 of 161 block diagram 0 tob hd404374 and hd404384 series evnb toc si/so avcc an 0 an 1 an 2 an 3 avss hmcs400 cpu rom ram external interrupt control circuit 8-bit timer a 8-bit timer b 8-bit timer c 8-bit synchronous serial interface a/d converter 10 bit 4 channels test osc1 osc2 x1 * x2 * vcc gnd d port r0 port r1 port r2 port r7 port d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 r0 0 : data bus : signal line r7 0 r7 1 r7 2 r7 3 r1 0 r1 3 r2 0 r2 1 r2 2 p-mos large current buffer n-mos large current buffer note : * applies to hd404374 series. 0
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 21 of 161 0 tob hd404389 series evnb toc si/so avcc an 0 an 1 an 2 an 3 an 4 an 5 avss hmcs400 cpu rom ram external interrupt control circuit 8-bit timer a 8-bit timer b 8-bit timer c 8-bit synchronous serial interface a/d converter 10 bit 6 channels test osc1 osc2 vcc gnd d port r0 port r1 port r2 port r7 port d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 r0 0 : data bus : signal line r7 0 r7 1 r7 2 r7 3 r1 0 r1 3 r2 0 r2 1 r2 2 p-mos large current buffer n-mos large current buffer 0
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 22 of 161 0 tob hd404082 and hd404084 series evnb toc si/so hmcs400 cpu rom ram external interrupt control circuit 8-bit timer a 8-bit timer b 8-bit timer c 8-bit synchronous serial interface test osc1 osc2 vcc gnd d port r0 port r1 port r2 port r7 port d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 r0 0 : data bus : signal line r7 0 r7 1 r7 2 r7 3 r1 0 r1 3 r2 0 r2 1 r2 2 p-mos large current buffer n-mos large current buffer 0
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 23 of 161 memory map rom memory map the rom memory map is shown in figure 1 and is described below. vector address area ($0000 to $000f): when an mcu reset or interrupt handling is performed, the program is executed from the vector address. a jmpl instruction should be used to branch to the start address of the reset routine or the interrupt routine. zero page subroutine area ($0000 to $003f):a branch can be made to a subroutine in the area $0000 to $003f with the cal instruction. pattern area ($0000 to $0fff): rom data in the area $0000 to $0fff can be referenced as pattern data with the p instruction. program area ($0000 to $03ff (hd404081, hd40a4081, hd40c4081)), ($0000 to $07ff (hd404372, hd40a4372, hd40c4372, hd404382, hd40a4382, hd40c4382, hd404082, hcd404082, hd40a4082, hd40c4082, hcd40c4082)), ($0000 to $0fff (hd404374, hd40a4374, hd40c4374, hd404384, hd40a4384, hd40c4384, hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd404084, hcd404084, hd40a4084, hd40c4084, hcd40c4084)), ($0000 to $1fff (hd404388, hd40a4388, hd40c4388)), ($0000 to $3fff (hd404389, hd40a4389, hd40c4389, hd407a4389, hd407c4389)).
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 24 of 161 $0000 $000f $0010 $003f $0040 $03ff $0400 $07ff $0800 vector addresses (16 words) zero page subroutine area (64 words) pattern and program area (2,048 words) *2 pattern and program area (1,024 words) *1 pattern and program area (4,096 words) *3 $0fff $1000 $1fff $3fff $2000 pattern and program area (8,192 words) *4 pattern and program area (16,384 words) *5 $0000 $0001 $0002 $0003 $0004 $0005 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset routine) jmpl instruction (jump to 0 routine) jmpl instruction (jump to 0 routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to a/d or serial interface routine) rom address rom address * 1 hd404081, hd40a4081, hd40c4081 * 2 hd40372, hd40a4372, hd40c4372, hd404382, hd40a4382, hd40c4382, hd404082, hcd404082, hd40a4082, hd40c4082, hcd40c4082 * 3 hd404374, hd40a4374, hd40c4374, hd404384, hd40a4384, hd40c4384, hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd404084, hcd404084, hd40a4084, hd40c4084, hcd40c4084 * 4 hd404388, hd40a4388, hd40c4388 * 5 hd404389, hd40a4389, hd40c4389, hd407a4389, hd407c4389 notes: figure 1 rom memory map ram memory map the mcu has on-chip ram comprising a memory register area, data area, and stack area. in addition to these areas, an interrupt control bit area, special register area, and register flag area are mapped onto ram memory space as a ram-mapped register area.the ram memory map is shown in figure 2 and described below. after power supply has been connected, regardless of a reset, the values for the memory register, data and stack areas will be undefined. make sure to initialize prior to use.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 25 of 161 speed select reg. miscellaneous reg. port mode reg.0 port mode reg.1 port mode reg.2 port mode reg.3 module standby reg.1 module standby reg.2 timer mode reg.a timer mode reg.b1 timer mode reg.b2 timer mode reg.c1 timer mode reg.c2 serial mode reg.1 serial mode reg.2 serial data reg.lower serial data reg.upper a/d mode reg. a/d data reg.lower a/d data reg.middle a/d data reg.upper port d 0 ~ d 3 dcr port d 4 ~ d 7 dcr port d 8 ~ d 9 dcr port r0 dcr port r1 dcr port r2 dcr port r7 dcr $000 $03f $040 $04f $050 $08f $090 $23f $240 $3bf $3c0 $3ff hd404374 series hd404384 series hd404389 series hd404082 series memory register (mr) area (16 digits) data (432 digits) stack area (64 digits) interrupt control bit area not used w w w w w w w w w w w r/w r/w w w r/w r/w w w r/w r/w w r r r w w w w w w w timer-b timer-c not used register flag area not used not used not used not used not used $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $01f $020 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02f $030 $031 $032 $033 $034 $035 $036 $037 $03a $03b $03c $03f timer read reg.b lower (trbl) r timer write reg.b lower (twbl) w timer read reg.b upper (trbu) r timer write reg.b upper (twbu) w timer read reg.c lower (trcl) r timer write reg.c lower (twcl) w timer read reg.c upper (trcu) r timer write reg.c upper (twcu) w $012 $013 $016 $017 *1 *1 *2 *2 *2 *2 not used not used $000 $03f $040 $04f $050 $08f $090 $0bf $0c0 $3bf $3c0 $3ff memory register (mr) area (16 digits) data (48 digits) stack area (64 digits) not used not used (ssr) (mis) (pmr0) (pmr1) (pmr2) (pmr3) (msr1) (msr2) (tma) (tmb1) (tmb2) (trbl/twbl) (trbu/twbu) (tmc1) (tmc2) (trcl/twcl) (trcu/twcu) (smr1) (smr2) (srl) (sru) (amr) (adrl) (adrm) (adru) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr7) notes: r : read w : write r/w : read/write *1 two registers are mapped onto the same address ($012, $013, $016, $017). *2 applies to hd404374, hd404384, and hd404389 series. ram?mapped register area ram?mapped register area hd404084 series $000 $03f $040 $04f $050 $08f $090 $13f $140 $3bf $3c0 $3ff memory register (mr) area (16 digits) data (176 digits) stack area (64 digits) not used not used ram?mapped register area figure 2 ram memory map
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 26 of 161 ram-mapped register area ($000 to $03f): ? interrupt control bit area ($000 to $003) this area consists of bits used for interrupt control. its configuration is shown in figure 3. individual bits can only be accessed by ram bit manipulation instructions (sem/semd, rem/remd, tm/tmd). there are restrictions on access to certain bits. the individual bits and instruction restrictions are shown in figure 4. ? special register area ($004 to $01f, $024 to $03f) this area comprises mode registers and data registers for external interrupts, the serial interface, timers, a/d converter, etc., and i/o pin data control registers. its configuration is shown in figures 2 and 5. these registers are of three kinds: write-only (w), read-only (r), and read/write (r/w). ram bit manipulation instructions cannot be used on the other registers. ? register flag area ($020 to $023) this area consists of the dton and wdon flags and interrupt control bits. its configuration is shown in figure 3. individual bits can only be accessed by ram bit manipulation instructions (sem/semd, rem/remd, tm/tmd). there are restrictions on access to certain bits. the individual bits and instruction restrictions are shown in figure 4. memory register (mr) area ($040 to $04f): in this data area, the 16 memory register digits (mr(0) to mr(15)) can also be accessed by the register- register instructions lamr and xmra. the configuration of this area is shown in figure 6. data area ($090 to $23f (hd404374, hd404384, hd404389 series)) ($090 to $0bf (hd404082 series)) ($090 to $13f (hd404084 series)) stack area ($3c0 to $3ff): this is the stack area used to save the contents of the program counter (pc), status flag (st), and carry flag (ca) when a subroutine call (cal or call instruction) or interrupt handling is performed. as four digits are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. the saved data and saved status information are shown in figure 6. the program counter is restored by the rtn and rtni instructions. the status and carry flags are restored by the rtni instruction, but are not affected by the rtn instruction. any part of the area not used for saving can be used as a data area.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 27 of 161 ram address $000 $001 $002 $003 bit 1 rsp (stack pointer reset) im0 ( 0 interrupt mask) imta (timer a interrupt mask) imtc (timer c interrupt mask) bit 0 ie (interrupt enable flag) if0 ( 0 interrupt request flag) ifta (timer a interrupt request flag) iftc (timer c interrupt request flag) $020 $021 $022 $023 if im ie sp : interrupt request flag : interrupt mask : interrupt enable flag : stack pointer notes: *1 applies to hd404374 series. *2 applies to hd404374, hd404384, and hd404389 series. bit 3 imwu ( 0 interrupt mask) not used imtb (timer b interrupt mask) imad *2 (a/d converter interrupt mask) bit 2 ifwu ( 0 interrupt request flag) not used iftb (timer b interrupt request flag) ifad *2 (a/d converter interrupt request flag) adsf *2 (a/d start flag) not used not used ifs (serial interrupt request flag) wdon (watchdog on flag) not used not used not used lson *1 (low speed on flag) not used not used not used dton *1 (dton flag) gef (gear enable flag) not used ims (serial interrupt mask) figure 3 interrupt control bit and register flag area configuration
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 28 of 161 ie im lson *1 if icsf icef gef rsp wdon adsf *2 dton *1 not used sem/semd allowed not executed not executed allowed allowed not executed in active mode used in subactive mode not executed allowed allowed allowed not executed inhibited allowed not executed allowed allowed allowed allowed inhibited inhibited inhibited allowed allowed inhibited rem/remd tm/tmd bits in the interrupt control bit area and register flag area can be set and reset by the sem or semd instruction and the rem or remd instruction, and tested by the tm or tmd instruction. they are not affected by any other instructions. the following restrictions apply to individual bits. the wdon bit is reset only by stop mode clearance by means of an mcu reset. do not use the rem or remd instruction on the adsf bit during a/d conversion. the dton bit is always in the reset state in active mode. if the tm or tmd instruction is used on a bit for which its use is prohibited, or on a nonexistent bit, the status flag value will be undetermined notes : * 1 applies to hd404374 series. * 2 applies to hd404374, hd404384, and hd404389 series. figure 4 instruction restrictions
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 29 of 161 ram address bit 3 bit 2 bit 1 bit 0 $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $01f $020 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02f $030 $031 $032 $033 $034 $035 $036 $037 $03a $03b $03c $03f ssr mis pmr0 pmr1 pmr2 pmr3 msr1 msr2 tma tmb1 tmb2 trbl/twbl trbu/twbu tmc1 tmc2 trcl/twcl trcu/twcu smr1 smr2 srl sru amr adrl adrm adru dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr7 interrupt control bit area 32 khz oscillation stop setting 32 khz frequency division ratio selection system clock selection system clock frequency division ratio switching pull-up mos control interrupt frame period selection d 0 / 0 r1 3 /tob r0 0 / 0 r1 0 /evnb r2 2 /si/so r2 1 / r2 0 /toc timer c clock on/off timer a / time base timer b lock on/off a/d clock on/off serial clock on/off timer a clock source selection timer b clock source selection timer c clock source selection reload on/off reload on/off timer b output mode setting time c output mode selection evnb edge detection selection timer b register (lower) timer b register (upper) timer c register (lower) timer c register (upper) serial data register (lower) serial data register (upper) a/d data register (bit 5 to 2) a/d data register (bit 9 to 6) register flag area serial transfer clock speed selection r2 2 /si/so pmos control so idle h/l setting analog channel selection a/d conversion time a/d data register (bit 1, 0) portd 3 dcr portd 2 dcr portd 1 dcr portd 0 dcr portr0 0 dcr portr1 3 dcr portr1 0 dcr portr2 2 dcr portr2 1 dcr portr2 0 dcr portr7 3 dcr portr7 2 dcr portr7 1 dcr portr7 0 dcr portd 7 dcr portd 6 dcr pord 5 dcr portd 4 dcr portd 9 dcr portd 8 dcr *1 *1 *1 *1 *2 *2 *2 *2 *2 *2 notes: *1 applies to hd404374 series. *2 applies to hd404374, hd404384, and hd404389 series. not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used figure 5 special function register area
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 30 of 161 mr (0) mr (1) mr (2) mr (3) mr (4) mr (5) mr (6) mr (7) mr (8) mr (9) mr (10) mr (11) mr (12) mr (13) mr (14) mr (15) $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f level level level level level level level level level level level level level level level level st 10 ca 3 13 9 6 2 12 8 5 1 11 7 4 0 $3fc $3fd $3fe $3ff 1020 1021 1022 1023 bit 3 bit 2 bit 1 bit 0 $3ff 1,023 960 $3c0 (a) memory registers (b) stack area 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pc 13 to pc 0 : program counter st : status flag ca : carry flag figure 6 configuration of memory registers and stack area, and stack position
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 31 of 161 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 7 and described below. accumulator b register w register x register y register spx register spy register carry flag status flag initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w program counter initial value: $0000, no r/w stack pointer initial value: $3ff, no r/w 30 (a) 30 (b) 10 (w) 30 (x) 30 (y) 30 (spx) 30 (spy) 0 (ca) 0 (st) 13 0 (pc) 50 (sp) 9 1111 figure 7 registers and flags accumulator (a) and b register (b): the accumulator and b register are 4-bit registers used to hold the result of an alu operation, and for data transfer to or from memory, an i/o area, or another register.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 32 of 161 w register (w), x register (x) and y register (y): the w register is a 2-bit register, and the x and y registers are 4-bit registers, used for ram register indirect addressing. the y register is also used for d port addressing. spx register (spx) and spy register (spy): the spx and spy registers are 4-bit registers used as x register and y register auxiliary registers, respectively. carry flag (ca): this flag holds alu overflow when an arithmetic/logic instruction is executed. it is also affected by the sec, rec, rotl, and rotr instructions. the contents of the carry flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the rtni instruction (but are not affected by the rtn instruction). status flag (st): this flag holds alu overflow when an arithmetic/logic or compare instruction is executed, and the result of an alu non-zero or bit test instruction. it is used as the branch condition for the br, brl, cal, and call instructions. the status flag is a latch-type flag, and does not change until the next arithmetic/logic, compare, or bit test instruction is executed. after a br, brl, cal, or call instruction, the status flag is set to 1 regardless of whether the instruction is executed or skipped. the contents of the status flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the rtni instruction (but are not affected by the rtn instruction). program counter (pc): this is a 14-bit binary counter that holds rom address information. stack pointer (sp): the stack pointer is a 10-bit register that holds the address of the next save space in the stack area. the stack pointer is initialized to $3ff by an mcu reset. the stack pointer is decremented by 4 each time data is saved, and incremented by 4 each time data is restored. the upper 4 bits of the stack pointer are fixed at 1111, so that a maximum of 16 stack levels can be used. there are two ways in which the stack pointer is initialized to $3ff: by an mcu reset as mentioned above, or by resetting the rsp bit with the rem or remd instruction. reset an mcu reset is performed by driving the reset pin low. at power-on, and when subactive mode, watch mode, or stop mode is cleared, reset should be input for at least trc to provide the oscillation settling time for the oscillator.in other cases, the mcu is reset by inputting reset for at least two instruction cycles. table 1 shows the areas initialized by an mcu reset, and their initial values.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 33 of 161 table 1 (1) initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 program executed from rom start address status flag (st) 1 branching by conditional branch instruction enabled stack pointer (sp) $3ff stack level is 0 interrupt interrupt enable flag (ie) 0 all interrupts disabled interrupt request flag (if) 0 no interrupt requests flags/ mask interrupt mask (im) 1 interrupt requests masked port data register (pdr) all bits 1 "1" level output possible data control registers (dcd0 ~ 2) all bits 0 data control registers (dcr0 0 , dcr1 0 , dcr1 3 , dcr2 0 ? dcr2 2 , dcr7 0 ? dcr7 3 ) all bits 0 output buffer off (high impedance) port mode register 0 (pmr0) ---0 see port mode register 0 section port mode register 1 (pmr1) ---0 see port mode register 1 section port mode register 2 (pmr2) 0--0 see port mode register 2 section i/o port mode register 3 (pmr3) 0000 see port mode register 3 section timer mode register a (tma) 0000 see timer mode register a section timer mode register b1 (tmb1) 0000 see timer mode register b1 section timer mode register b2 (tmb2) -000 see timer mode register b2 section timer mode register c1 (tmc1) 0000 see timer mode register c1 section timer mode register c2 (tmc2) -0-- see timer mode register c2 section prescaler s (pss) $000 prescaler w (psw) $00 timer/counter a (tca) $00 timer/counter b (tcb) $00 timer/counter c (tcc) $00 timer write register b (twbu,l) $x0 timers timer write register c (twcu,l) $x0
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 34 of 161 table 1 (2) initial values after mcu reset item abbr. initial value contents serial mode register 1 (smr1) 0000 see serial mode register 1 section serial mode register 2 (smr2) -0x- see serial mode register 2 section serial data register (sru,l) $xx serial interface octal counter 000 a/d mode register (amr) 0000 see a/d mode register section a/d data register u (adru) 0111 a/d data register m (adrm) 1111 a/d converter a/d data register l (adrl) 11- - see a/d data register section low speed on flag (lson) 0 see low-power mode section watchdog timer on flag (wdon) 0 see timer c section a/d start flag (adsf) 0 see a/d converter section direct transfer on flag (dton) 0 see low-power mode section bit registers gear enable flag (gef) 0 see system clock gear function miscellaneous register (mis) 0-00 see low-power mode and input/output sections system clock select register (ssr) 0000 see low-power mode and oscillator circuit sections module standby register 1 (msr1) --00 see timer section others module standby register 2 (msr2) --00 see serial interface and a/d converter sections notes: 1. the state of registers and flags other than those listed above after an mcu reset is shown in table 1 (3). 2. x: indicates invalid value, - indicates that the bit does not exist. table 1 (3) initial values after mcu reset item abbr. after stop mode clearance by wu wuwu wu 0 after other mcu reset carry flag (ca) accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) ram retain value immediately prior to entering stop mode value immediately prior to mcu reset is not guaranteed. must be initialized by program.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 35 of 161 interrupts there are a total of seven interrupt sources, comprising wakeup input ( wu 0 ), external interrupts ( int 0 ), timer/counter (timer a, timer b, timer c) interrupts, a serial interface interrupt, and an a/d converter interrupt. each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for storing and controlling interrupt requests. in addition, an interrupt enable flag is provided to control interrupts as a whole. of the interrupt sources, the a/d converter and serial interface share the same vector address. software must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt handling. interrupt control bits and interrupt handling: the interrupt control bits are mapped onto ram addresses $000 to $003 and $023, and can be accessed by ram bit manipulation instructions. however, the interrupt request flags (if) cannot be set by software. when the mcu is reset, the interrupt enable flag (ie) and interrupt request flags (if) are initialized to 0, and the interrupt masks (im) are initialized to 1. figure 8 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of interrupt source. when the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an interrupt is requested. if the interrupt enable flag is set to 1 at this time, interrupt handling is started. the vector address corresponding to the interrupt source is generated by the priority control circuit. the interrupt handling sequence is shown in figure 9, and the interrupt handling flowchart in figure 10. when an interrupt is accepted, execution of the previous instruction is completed in the first cycle. in the second cycle, the interrupt enable flag (ie) is reset. in the second and third cycles, the contents of the carry flag, status flag, and program counter are saved on the stack. in the third cycle, a jump is made to the vector address and instruction execution is resumed from that address. in each vector address area, a jmpl instruction should be written that branches to the start address of the interrupt routine. in the interrupt routine, the interrupt request flag that caused interrupt handling must be reset by software. table 2 vector addresses and interrupt priorities interrupt source priority vector address reset ? $0000 wu 0 1 $0002 int 0 2 $0004 timer a 3 $0008 timer b 4 $000a timer c 5 $000c serial interface, a/d converter 6 $000e
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 36 of 161 $000,2 $000,3 ifwu imwu $001,0 $001,1 if0 im0 $002,0 $002,1 ifta imta $002,2 $002,3 iftb imtb $003,0 $003,1 iftc imtc $003,2 $003,3 ifad imad $000,0 i/e $023,2 $023,3 ifs ims ( 0 interrupt) ( 0 interrupt) (timer a interrupt) (timer b interrupt) (timer c interrupt) (a/d interrupt) priority control circuit interrupt request vector address (serial interrupt) figure 8 block diagram of interrupt control circuit
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 37 of 161 table 3 interrupt processing and activation conditions interrupt source interrupt control bit wu wuwu wu 0 int intint int 0 timer a timer b timer c a/d or serial ie 1 1 1 1 1 1 ifwu imwu 1 0 0 0 0 0 if0 im0 * 1 0 0 0 0 ifta imta * * 1 0 0 0 iftb imtb * * * 1 0 0 iftc imtc * * * * 1 0 ifad imad +ifs ims * * * * * 1 note: * operation is not affected whether the value is 0 or 1. 1 2 3 4 5 6 instruction execution* interrupt acceptance save to stack ie reset execution of jmpl instruction at vector address save to stack vector address generated execution of instruction at start address of interrupt routine instruction cycle note: * the stack is accessed and the ie reset after the instruction is executed, even if it is a 2cycle instruction. figure 9 interrupt sequence
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 38 of 161 power on ="0"? yes no yes yes no no no no no no yes yes yes yes yes reset mcu interrupt request? execute instruction pc(pc)+1 pc$0002 pc$0004 pc$0008 pc$000a pc$000c pc$000e ie="1"? accept interrupt ie"0" stack(pc) stack(ca) stack(st) 0 interrupt? 0 interrupt? timer a interrupt? timer b interrupt? timer c interrupt? (a/d, serial interrupt) figure 10 interrupt handling flowchart
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 39 of 161 interrupt enable flag (ie: $000,0): the interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4. the interrupt enable flag is reset by interrupt handling and set by the rtni instruction. table 4 interrupt enable flag (ie: $000,0) interrupt enable flag (ie) interrupt enabling/disabling 0 interrupts disabled 1 interrupts enabled wakeup interrupt request flag (ifwu: $000,2): the wakeup interrupt request flag (ifwu) is set by the detection of a falling edge in wu 0 input in active mode, subactive mode,watch mode, or standby mode. in stop mode, when a falling edge is detected at the wakeup pin, the mcu waits for the oscillation settling time, then switches to active mode. when a transition is made from stop mode to active mode with ie set to 1 and imwu cleared to 0, wakeup interrupt handling is executed after the switch to active mode. the wakeup interrupt request flag (ifwu) is not set in this case (table 5). table 5 wakeup interrupt request flag (ifwu: $000,2) wakeup interrupt request flag (ifwu) interrupt request 0 no wakeup interrupt request 1 wakeup interrupt request generated wakeup interrupt mask (imwu: $000,3): his bit masks an interrupt request by the wakeup interrupt request flag (table 6). table 6 wakeup interrupt request mask (imwu: $000,3) wakeup interrupt mask (imwu) interrupt request 0 wakeup interrupt request enabled 1 wakeup interrupt request masked (held pending) external interrupt request flag (if0: $001, 0): the external interrupt request flag is set by an int 0 input falling edge (table 7). table 7 external interrupt request flag (if0: $001, 0) external interrupt request flag (if0) interrupt request 0 no external interrupt request 1 external interrupt request generated
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 40 of 161 external interrupt mask (im0: $001, 1): this bit masks an interrupt request by the external interrupt request flag (table 8). table 8 external interrupt mask (im0: $001, 1) external interrupt mask (im0) interrupt request 0 external interrupt request enabled 1 external interrupt request masked (held pending) timer a interrupt request flag (ifta: $002,0): the timer a interrupt request flag is set by timer a overflow output (table 9). table 9 timer a interrupt request flag (ifta: $002,0) timer a interrupt request flag (ifta) interrupt request 0 no timer a interrupt request 1 timer a interrupt request generated timer a interrupt mask (imta: $002,1): this bit masks an interrupt request by the timer a interrupt request flag (table 10). table 10 timer a interrupt mask (imta: $002,1) timer a interrupt mask (imta) interrupt request 0 timer a interrupt request enabled 1 timer a interrupt request masked (held pending) timer b interrupt request flag (iftb: $002,2): the timer b interrupt request flag is set by timer b overflow output (table 11). table 11 timer b interrupt request flag (iftb: $002,2) timer b interrupt request flag (iftb) interrupt request 0 no timer b interrupt request 1 timer b interrupt request generated
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 41 of 161 timer b interrupt mask (imtb: $002,3): this bit masks an interrupt request by the timer b interrupt request flag (table 12). table 12 timer b interrupt mask (imtb: $002,3) timer b interrupt mask (imtb) interrupt request 0 timer b interrupt request enabled 1 timer b interrupt request masked (held pending) timer c interrupt request flag (iftc: $003,0): the timer c interrupt request flag is set by timer c overflow output (table 13). table 13 timer c interrupt request flag (iftc: $003,0) timer c interrupt request flag (iftc) interrupt request 0 no timer c interrupt request 1 timer c interrupt request generated (held pending) timer c interrupt mask (imtc: $003,1): this bit masks an interrupt request by the timer c interrupt request flag (table 14). table 14 timer c interrupt mask (imtc: $003,1) timer c interrupt mask (imtc) interrupt request 0 timer c interrupt request enabled 1 timer c interrupt request masked (held pending) serial interrupt request flag (ifs: $023,2): the serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted midway (table 15). table 15 serial interrupt request flag (ifs: $023,2) serial interrupt request flag (ifs) interrupt request 0 no serial interrupt request 1 serial interrupt request generated
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 42 of 161 serial interrupt mask (ims: $023,3): this bit masks an interrupt request by the serial interrupt request flag (table 16). table 16 serial interrupt mask (ims: $023,3) serial interrupt mask (ims) interrupt request 0 serial interrupt request enabled 1 serial interrupt request masked (held pending) a/d interrupt request flag (ifad: $003,2) (applies to hd404374, hd404384, and hd404389 series): the a/d interrupt request flag is set on completion of a/d conversion (table 17). table 17 a/d interrupt request flag (ifad: $003,2) a/d interrupt request flag (ifad) interrupt request 0 no a/d interrupt request 1 a/d interrupt request generated a/d interrupt mask (imad: $003,3) (applies to hd404374, hd404384, and hd404389 series): this bit masks an interrupt request by the a/d interrupt request flag (table 18). table 18 a/d interrupt mask (imad: $003,3) serial interrupt mask (imad) interrupt request 0 a/d interrupt request enabled 1 a/d interrupt request masked (held pending)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 43 of 161 operating modes the five operating modes shown in table 19 can be used for the mcu. the function of each mode is shown in table 20, and the state transition diagram among each mode in figure 11. table 19 operating modes and clock status mode name active standby stop watch * 1 subactive * 1, * 3 activation method reset cancellation, interrupt request, wu 0 input in stop mode stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 int 0 /timer a or wu 0 interrupt request in watch mode system oscillator op op stopped stopped stopped status subsystem oscillator * 1 op op op * 2 op op cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, wu 0 input reset input, int 0 /timer a or wu 0 interrupt request reset input, stop/sby instruction notes: op: implies in operation. 1. applies to hd404374 series. 2. operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (ssr: $004) 3. subactive mode is an optional function; specify it on the fnction option list.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 44 of 161 table 20 operation in low-power dissipation modes function stop mode watch mode * 1 standby mode subactive mode * 1, * 3 cpu retained retained retained op ram retained retained retained op timer a stopped op op op timer b stopped stopped op op timer c stopped stopped op op serial interface stopped * 2 stopped * 2 op op a/d * 4 stopped stopped op stopped i/o retained retained retained op notes: op: implies in operation. 1. applies to hd404374 series. 2. transmission/reception is activated if a clock is input in external clock mode. however, interrupts stop. 3. subactive mode is an optional function specified on the function option list. 4. applies to hd404374, hd404384, and hd404389 series.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 45 of 161 reset by pin input or watchdog timer reset (tma3=0) (tma3=1) timer a, 0 or 0 interrupt standby mode active mode sby instruction interrupt sby instruction interrupt stop instruction (tma3=1,lson=0) (tma3=1,lson=1) f osc : fx : fcyc : fw : f sub : cpu : clk : per : lson : dton : tma3 : main oscillator frequency sub-oscillator frequency (for realtime clock) f osc /32 or fosc/4 (selected by software) fx/8 fx/8 or fx/4 (selected by software) system clock clock for realtime clock peripheral function clock low speed on flag direct transfer on flag timer mode register a bit3 timer a, 0 or 0 interrupt 0 stop instruction 0 stop instruction stop instruction stop mode (tma3=0,ssr3=0,lson=0) (tma3=0,ssr3=1,lson=0) subactive mode *4 *2 *3 *1 *5 dton 1 0 don't care 0 transition condition stop/sby instruction stop/sby instruction stop/sby instruction stop/sby instruction lson 0 0 1 0 *1 *2 *3 *4 tma3 1 1 1 0 watch mode f osc fx cpu clk per : stop : stop : stop : stop : stop f osc fx cpu clk per : active : active : fcyc : fcyc : fcyc f osc fx cpu clk per : stop : active : stop : stop : stop f osc fx cpu clk per : active : active : stop : fcyc : fcyc f osc fx cpu clk per : stop : active : f sub : fw : f sub f osc fx cpu clk per : active : active : fcyc : fw : fcyc f osc fx cpu clk per : active : active : stop : fw : fcyc f osc fx cpu clk per : stop : active : stop : fw : stop f osc fx cpu clk per : stop : active : stop : fw : stop * 5 applies to hd404384, hd404389, hd404082, and hd404084 series. note: watch mode and subactive mode apply to hd404374 series. figure 11 mcu status transitions
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 46 of 161 active mode: in active mode all functions operate. in this mode, the mcu operates on clocks generated by the osc 1 and osc 2 oscillator circuits. standby mode: in standby mode the oscillators continue to operate but clocks relating to instruction execution halt. as a result, cpu operation stops, and registers, ram, and the d port/r port set for output retain their state immediately prior to entering standby mode. interrupts, timers, the serial interface, and other peripheral functions continue to operate. power consumption is lower than in active mode due to the halting of the cpu. the mcu is switched to standby mode by executing the sby instruction in active mode. standby mode is cleared by reset input or an interrupt request. when standby mode is cleared by reset input, an mcu reset is performed. when standby mode is cleared by an interrupt request, the mcu enters active mode and executes a instruction following the sby instruction. after executing the instruction, if the interrupt enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt request is held pending and normal instruction execution is continued. mcu operation flowchart is shown in figure 12.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 47 of 161 stop mode system clock oscillator started system reset next instruction execution system clock oscillator started interrupts enabled ifwu =1? if0 = 1? ifta = 1? iftb = 1? iftc = 1? if = 1, im = 0, ie = 1? no no yes yes yes no no no no no no yes 1. applies to hd404374 series 2. only when clearing from standby mode notes: standby mode watch mode * 1 =0? yes* 2 yes* 2 yes* 2 yes no yes yes no =0? nop system clock oscillator started next instruction execution 0 = ? ifad + ifs = 1? figure 12 mcu operation flowchart
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 48 of 161 stop mode: in stop mode, all mcu function stop except that states prior to entry into stop mode are retained. this mode thus has the lowest power consumption of all operating mode. in stop mode, the osc 1 and osc 2 oscillators stop. bit 3 (ssr3) of the system clock select register (ssr: $004) (figure 22) can be used to select the active (= 0) or stopped (= 1) state for the x1 and x2 oscillators. the mcu is switched to stop mode by executing a stop instruction while bit 3 (tma3) of timer mode register a (tma: $00f) (figure 33) is cleared to 0 in active mode. stop mode is cleared by reset or wu 0 input. when stop mode is cleared by reset , the reset signal should be input for at least the oscillation settling time (trc) (see "ac characteristics") shown in figure 13. then, the mcu is initialized and starts instruction execution from the start (address 0) of the program (ie = 0, imwu = 0). if ie is set before entering stop mode (ie = 1, imwu = 0), wakeup interrupt handling is executed after the transition to active mode. when the mcu detects a falling edge at wu 0 in stop mode, it automatically waits for the oscillation settling time, then switches to active mode. after the transition to active mode, the mcu resumes program execution from the instruction following the stop instruction. if stop mode is cleared by wakeup input, ram data and registers retain their values prior to entering stop mode. stop mode oscillator internal clock stop instruction executed t res (at least oscillation settling time (t rc )) figure 13 timing chart for clearing stop mode by reset input note: if stop mode is cleared by wakeup input when an external clock is used as the system clock (osc1), the subclock should not be stopped in stop mode. watch mode ( applies to hd404374 series) : in watch mode, the realtime clock function (timer a) and lcd function using the x1 and x2 oscillators operate, but other functions stop. this mode thus has the second lowest power consumption after stop mode, and is useful for performing realtime clock display only. in watch mode, the osc 1 and osc 2 oscillators stop but the x1 and x2 oscillators continue to operate. the mcu is switched to watch mode by executing a stop instruction while tma3 = 1 in active mode, or by executing a stop/sby instruction in subactive mode.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 49 of 161 watch mode is cleared by reset input or an int 0 ,timer a or wu 0 interrupt request. for reset input, refer to the section on stop mode. when watch mode is cleared by an int 0 , timer a or wu 0 interrupt request, the mode transition depends on the value of the lson bit: the mcu enters active mode if lson = 0, and enters subactive mode if lson = 1. in the case of a transition to active mode, interrupt request generation is delayed to secure the oscillation settling time: the delay is the trc set time for the timer a interrupt, and, for the int 0 interrupt or wu 0 interrupt, tx (t + t rc < tx < 2t + t rc ) if bit 1 and 0 (mis1, mis0) of the miscellaneous register are set to 00, or tx (t rc < tx < t + t rc ) if mis1 and mis0 are set to 01 or 10 (figures 14 and 15). other operations when the transition is made are the same as when watch mode is cleared (figure 12). subactive mode ( applies to hd404374 series): in subactive mode, the osc 1 and osc 2 oscillator circuits stop and the mcu operates on clocks generated by the x1 and x2 oscillator circuits. in this mode, functions other than the a/d converter operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. a cpu instruction processing speed of 244 s or 122 s can be selected according to whether bit 2 (ssr2) of the system clock select register (ssr: $004) is set to 1 or cleared to 0. the value of the ssr2 bit should be changed (0 1 or 1 0) only in active mode. if the value is changed in subactive mode, the mcu may operate incorrectly. subactive mode is cleared by executing a stop/sby instruction. a transition is then made to either watch mode or active mode according to the value of the low speed on flag (lson: $020,0) and the direct transfer on flag (dton: $020,3). subactive mode is a function option, and should be specified in the function option list. interrupt frame ( applies to hd404374 series): in watch mode and subactive mode, ? clk is supplied to the timer a, wu 0 , and int 0 acceptance circuits. prescaler w and timer a operate as time bases, and generate interrupt frame timing. either of two values can be selected for the interrupt frame period, t, by means of the miscellaneous register (mis: $005) (figure 15). in watch mode and subactive mode, the timing for generation of timer a, int 0 and wu 0 interrupts is synchronized with the interrupt frame. except for the case of an active mode transition, the interrupt strobe timing is used for interrupt request generation. timer a generates overflow and interrupt requests at the interrupt strobe timing.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 50 of 161 watch mode oscillation stabilization period active mode active mode interrupt strobe 0, 0 interrupt request generation t ttt rc t x t: interrupt frame period t rc : oscillation stabilization period only in case of transition to active mode note: if the time from the fall of the 0 or 0 signal until the interrupt is accepted and active mode is entered and is designated t x , then t x will be in the following range : t+t rc t x 2t+t rc (mis1, mis0=00) t rc t x t+t rc (mis1, mis0=01 or 10) figure 14 interrupt frame miscellaneous register (mis: $005) bit read/write reset bit name 3 w 0 mis3 2 w 0 not used* 4 1 w 0 mis1* 1 0 w 0 mis0* 1 interrupt frame period t( ms )* 2 oscillation settling time t rc ( ms )* 2 mis1 mis0 0 1 0 1 0 1 0.24414 3.90625 3.90625 0.12207(0.24414)* 3 7.8125 31.25 oscillator circuit condition external clock input, cr oscillation frequency ceramic resonator crystal resonator not used notes: *1. applies to hd404374 series. *2. t and t rc values are for use of a 32.768 khz crystal oscillator at the x1-x2 pins. *3. this value applies only in case of direct transition operation. *4. must always be cleared to 0. setting to 1 will cause incorrect operation. see pull-up mos control, figure 30 figure 15 miscellaneous register (mis)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 51 of 161 direct transition from subactive to active mode (applies to hd404374 series): a direct transition can be made from subactive mode to active mode by controlling the direct transfer on flag (dton: $020,3) and low speed on flag (lson: $020,0). the procedure is shown below. (a) set lson = 0 and dton = 1 in subactive mode. (b) execute a stop or sby instruction. (c) after the lapse of the mcu internal processing time and the oscillation settling time, the mcu automatically switches from subactive mode to active mode (figure 16). notes: 1. the dton flag ($020,3) can be set in only subactive mode. it is always in the reset state in active mode. 2. the condition for transition time t d from the subactive mode to active mode is as follows: t rc < t d < t + t rc . subactive mode stop/sby instruction execution mcu internal processing time oscillation stabilization time active mode (set lson =0, dton =1) interrupt strobe direct transition completion timing t t d t rc t: interrupt frame period t rc : oscillation settling time t d : direct transition time figure 16 direct transition timing mcu operation sequence: the mcu operates in accordance with the flowchart shown in figure 17. reset input is asynchronous input, and the mcu immediately enters the reset state upon reset input, regardless of its current state. in the low-power mode operation sequence, if a stop/sby instruction is executed while the ie flag is cleared and the interrupt flag is set, releasing the relevant interrupt mask, the stop/sby instruction is canceled (regarded as nop) and the next instruction is executed. therefore, when executing a stop/sby instruction, all interrupt flags must be cleared, or interrupts masked, beforehand.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 52 of 161 yes yes yes yes no no no no if=1 im=0 ie=0 if=1 im=0 stop/sby instruction standby/watch mode (hd404374 series) stop mode 0 = hardware nop execution hardware nop execution clearing standby watch mode pc (pc)+1 pc (pc)+1 mcu operation cycle note: see figure 12, mcu operation flowchart, for if and im operation. interrupt handling routine instruction execution instruction execution clearing stop mode nop pc (pc)+2 figure 17 mcu operating sequence (low-power mode operation)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 53 of 161 usage notes (applies to hd404374 series): in watch mode and subactive mode, an interrupt will not be detected correctly if the int 0 or wu 0 high or low-level period is shorter than the interrupt frame period. the mcu ? s edge sensing method is shown in figure 18. the mcu samples the int 0 and wu 0 signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a falling edge has been generated. interrupt detection errors occur since this sampling is performed at the interrupt frame period. if the high- level period of the int 0 or wu 0 signal is within an interrupt frame, as shown in figure 19 (a), the signal will be low at point a and point b, with the result that the falling edge will not be recognized. similarly, if the low-level period of the int 0 or wu 0 signal is within an interrupt frame, as shown in figure 19 (b), the signal will be high at point a and point b, with the result that the falling edge will not be recognized. in watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the int 0 and wu 0 signals is at least as long as the interrupt frame period. 0 or 0 sampling high low low figure 18 edge sensing method 0 or 0 interrupt frame point a: low point b: low 0 or 0 interrupt frame point a: high point b: high (a) high-level mode (b) low-level mode figure 19 sampling examples
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 54 of 161 internal oscillator circuit figure 20 shows the clock pulse generator circuit. as shown in table 21, a ceramic oscillator or crystal oscillator can be connected to osc1 and osc2, and a 32.768 khz crystal oscillator can be connected to x1 and x2. external clock operation is possible for the system oscillator. cr oscillation for system oscillator is possible. cr oscillation function is optional. set bit 1 (ssr1) of the system clock select register (ssr: $004) according to the frequency of the oscillator connected to osc1 and osc2 (figure 22). note: if the setting of bit 1 in the system clock select register does not match the frequency of the system oscillator, the subsystem using 32.768 khz oscillation will not operate correctly in the hd404374 series. also, the cr oscillation frequency differs depending on the operating voltage and resistance value. set bit 1 of the system clock select register to match the operating frequency. note that if the frequency being used does not match the setting of bit 1 of the system clock select register, subsystems using the 32.768 khz oscillation frequency will not operate correctly. osc 1 x1 lson system clock selection circuit osc 2 system oscillator 1/4 or 1/32 division circuit* timing generation circuit f osc f cyc t cyc x2 sub system clock oscillator 1/8 or 1/4 division circuit* timing generator circuit f x f sub t subcyc 1/8 division circuit timing generation circuit f w t wcyc cpu per cpu rom ram registers, flags i/o peripheral functions interrupts tma3 bit timer a interrupts time base clock selection circuit clk notes: * the division ratio can be selected by setting bit 0 or bit 2 in the system clock select register (ssr:$004). hd404374 series figure 20 clock pulse generator circuit
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 55 of 161 system clock gear function the mcu has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be selected by software for the instruction execution time. efficient power consumption can be achieved by operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at the other times. figure 21 shows the system clock conversion method. system clock conversion from division-by-4 to division-by-32 is performed as follows. first, make the division-by-32 setting (ssr0 write), then set the gear enable flag (gef: $021,3). this flag is used to distinguish between gear conversion and a transition to standby mode. next, execute an sby instruction. when the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is entered. in this case a transition is made to standby mode for the duration of the gear conversion, but after the synchronization time has elapsed, a transition is made automatically to active mode. as soon as the transition is made to active mode, the gear enable flag is reset. the same procedure is used for conversion from division-by-32 to division-by-4. clear all interrupts, then disable interrupts, before carrying out gear conversion. incorrect operation may result if an interrupt is generated during gear conversion. division-by-32 setting (ssr0 = 1) set gear enable flag execute sby instruction execute next instruction synchronization time division-by-4 setting (ssr0 = 0) set gear enable flag execute sby instruction execute next instruction synchronization time figure 21 system clock division ratio conversion flowchart
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 56 of 161 system clock select register (ssr: $004) make sure to set bit 3 of the system clock select register to 1 if the hd404374 series is being used without the subsystem clock, and on the hd404384, hd404389, hd404082, and hd404084 series. the microcomputer will malfunction if the setting is not 1. bit read/write initial value on reset bit name 3 w 0 ssr3 2 w 0 ssr2* 1 w 0 ssr1* 0 w 0 ssr0 system clock division ratio switch 0 1 division-by-4 (f cyc - f osc /4) division-by-32 (f cyc - f osc /32) system clock division ratio switch 0 1 f osc =0.4?1.0mhz f osc =1.6?8.5mhz subsystem clock division ratio switch 0 1 f sub =fx/8 f sub =fx/4 (hd404374 series) 0 1 subsystem clock operates in stop mode subsystem clock stops in stop mode note: * applies to hd404374 series. the cr oscillation frequency differs depending on the operating voltage and resistance value. set ssr1 to match the operating frequency. note that if the frequency being used does not match the ssr1 setting, subsystems using the 32.768 khz oscillation frequency will not operate correctly. subsystem clock stop setting this bit must be set to 1 following power-on and reset if the hd404374 series is being used without the subsystem clock, and on the hd404384, hd404389, hd404082, and hd404084 series. if it is set to 0 (the initial value), malfunctioning may occur in the stop mode. figure 22 system clock select register
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 57 of 161 table 21 oscillator circuit examples circuit structure circuit constants external clock operation external oscillator osc 1 osc 2 open ceramic oscillator (osc 1 , osc 2 ) osc 1 osc 2 c 1 c 2 r f gnd ceramic oscillator ceramic oscillator: csa4.00mg (murata) r f =1m ? 20% c 1 =c 2 =24pf20% crystal oscillator (osc 1 , osc 2 ) osc 1 osc 2 c 1 c 2 r f gnd crystal oscillator r f =1m ? 20% c 1 =c 2 =10 ? 20pf20% cr oscillator * 4 (osc 1 , osc 2 ) osc 1 osc 2 r f r f =20k ? ?% crystal oscillator (x1, x2) hd404374 series x1 x2 c 1 c 2 gnd crystal oscillator crystal: 32.768 khz: mx38t (nihon denpa kogyo) c 1 =c 2 =20pf20% notes: 1. with a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray capacitance in the interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator manufacturer. 2. make the connections between the osc 1 and osc 2 pins (x1 and x2 pins) and external components as short as possible, and ensure that no other lines cross these lines (see layout example in figure 23). 3. when 32.768 khz crystal oscillation is not used, fix the x1 pin at v cc and leave the x2 pin open. 4. applies to hd40c4372, hd40c4374, hd40c4382, hd40c4384, hd40c4388, hd40c4389, hd40c4081, hd40c4082, hcd40c4082, hd40c4084, hcd40c4084, hd407c4374 and hd407c4384.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 58 of 161 av ss osc 1 osc 2 test x2 x1 reset av ss osc 1 osc 2 test nc nc reset hd404384/hd404389/hd404082/hd404084 series hd404374 series (gnd) (gnd) figure 23 typical layouts of crystal and ceramic oscillator
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 59 of 161 input/output the mcu has 20 input/output pins (d 0 to d 9 , r0, r1 0 , r1 3 , r2 0 to r2 2 , r7 0 to r7 3 ). the features of these pins are described below. ? the four pins d 0 to d 3 are source large-current (10 ma max.) i/o pins. ? the four pins d 4 to d 7 are sink large-current (15 ma max.) i/o pins. ? i/o pins comprise pins (d 0 , r0 0 , r1 0 , r1 3 , r2 0 to r2 2 , r7 0 to r7 3 ) that also have a peripheral function (timer, serial interface, etc.). with these pins, the peripheral function setting has priority over the d port or r port pin setting. when a peripheral function setting has been made for a pin, the pin function and input/output mode will be switched automatically in accordance with that setting. ? selection of input or output for i/o pins, or selection of the port or peripheral function for pins multiplexed as peripheral function pins, is performed by the program. ? all output of the peripheral function pins are cmos outputs. the so pin and r2 2 port pin can be designated as nmos open-drain output by the program. ? a reset clears peripheral function selection. and since the data control registers (dcd, dcr) are also reset, input/output pins go to the high-impedance state. ? each i/o pin has a built-in pull-up mos that can be turned on and off individually by the program. figure 24 shows the i/o buffer configuration, and table 22 shows i/o pin circuit configuration control by the program. table 23 shows the circuit configuration of each i/o pin. pull-up mos pull-up control signal buffer control signal output data input data v cc pmos nmos input control signal mis3 dcd, dcr pdr v cc figure 24 i/o pin circuit configuration
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 60 of 161 table 22 programmable i/o circuits mis3 (bit 3 of mis) 0 1 dcd,dcr 0 1 0 1 pdr 0 1 0 1 0 1 0 1 pmos ? ? ? on ? ? ? on cmos buffer nmos ? ? on ? ? ? on ? pull-up mos ? ? ? ? ? on ? on note: ? : off table 23 circuit configurations of i/o pins type circuit configuration pins v cc v cc input control signal mis3 dcd, dcr pdr pull-up control signal buffer control signal output data input data d 0 -d 9 r0 0 r1 0 , r1 3 r2 0 , r2 1 v cc v cc input control signal mis3 dcr pdr pull-up control signal buffer control signal output data input data smr22 r2 2 r7 0 ? r7 3 * 2 i/o pins v cc v cc input control signal pull-up control signal buffer control signal output data a/d input a/d channel control signal input data mis3 dcr pdr r7 0 -r7 3 an 0 -an 3 * 1 notes: in a reset, since the i/o control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. applies to hd404374, hd404384, and hd404389 series. 2. applies to hd404082 and hd404084 series.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 61 of 161 table 23 circuit configurations of i/o pins (cont) type circuit configuration pins i/o pins v cc v cc mis3 pdr pull-up control signal i/o control signal output data input data sck sck v cc v cc mis3 pdr pull-up control signal pmos control signal output data smr22 so so output pins v cc v cc mis3 pdr pull-up control signal output data tob, toc tob, toc reset input data reset v cc mis3 pdr 0 etc. wu 0 , int 0 , evnb, si perip- heral function pins input pins a/d input a/d channel control signal an 4 , an 5 * 1 note: in a reset, since the i/o control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. applies to hd404389 series.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 62 of 161 d port the d port consists of 10 i/o pins that are addressed bit-by-bit. ports d 0 to d 3 are source large-current i/o pins, and ports d 4 to d 7 are sink large-current i/o pins. the d port can be set and reset by the sed and red instructions or the sedd and redd instructions. output data is stored in the port data register (pdr) for each pin. the entire d port can be tested by the td or tdd instruction. the d port output buffer is turned on and off by the d port data control registers (dcd0 to dcd2: $030 to $032). the dcd registers are mapped onto memory addresses (figure 25). port d 0 is multiplexed as interrupt input pin int 0 . setting as interrupt pin is performed by bit 0 (pmr00) of port mode register 0 (pmr0: $008) (figure 26). data control registers (dcd0 ?2 : $030?$032) (dcr0?2, 7 : $034?$036, $03b) register name dcdn dcrm bit read/write reset bit name read/write reset bit name 3 w 0 dcdn3 w 0 dcrm3 2 w 0 dcdn2 w 0 dcrm2 1 w 0 dcdn1 w 0 dcrm1 0 w 0 dcdn0 w 0 dcrm0 all bits 0 1 cmos buffer off (high impedance) cmos buffer active cmos buffer control register name dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr7 bit 3 d 3 d 7 r1 3 r7 3 bit 2 d 2 d 6 r2 2 r7 2 bit 1 d 1 d 5 d 9 r2 1 r7 1 bit 0 d 0 d 4 d 8 r0 0 r1 0 r2 0 r7 0 correspondence between each bit of dcd and dcr and ports (n=0 to 2) (m=0 to 2, 7) figure 25 data control registers (dcd, dcr)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 63 of 161 r port the r port consists of 10 i/o pins that are addressed in 4-bit units. input can be performed by means of the lar and lbr instructions, and output by means of the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the r port output buffer is turned on and off by the r port data control registers (dcr0 to dcr2, dcr7: $034 to $036, $03b). the dcr registers are mapped onto memory addresses (figure 25). port r0 0 is multiplexed as wakeup input pin wu 0 . setting of this pin as peripheral function pins is performed by port mode register 1 (pmr1: $009) (figure 27). port r1 0 is multiplexed as peripheral function pin evnb. setting of this pin as peripheral function pins is performed by bit 0 (pmr20) of port mode register 2 (pmr2: $00a) (figure 28). ports r1 3 and r2 0 are multiplexed as peripheral function pins tob, and toc, respectively. setting of these pins as peripheral function pins is performed by bits 3 (pmr23) of port mode register 2 (pmr2: $00a) and bit 0 (pmr30) of port mode register 3 (pmr3: $00b)(figures 28 and 29). ports r2 1 and r2 2 are multiplexed as peripheral function pins sck and si/so, respectively. setting of these pins as peripheral function pins is performed by bits 1 to 3 (pmr31 to pmr33) of port mode register 3 (pmr3: $00b) (figure 29). ports r7 0 to r7 3 are multiplexed as peripheral function pins an 0 to an 3 (hd404374, hd404384, and hd404389 series only). setting of these pins as peripheral function pins is performed by bits 1 to 3 (amr1 to amr3) of the a/d mode register (amr: $028) (see figure 64 in section 8, a/d converter). port mode register 0 (pmr0: $008) bit read/write initial value on reset bit name 3 not used 2 not used 1 not used 0 w 0 pmr00 pmr00 0 1 d 0 /int 0 pin mode selection d 0 int 0 figure 26 port mode register 0 (pmr0: $008)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 64 of 161 r0 0 /wu 0 pin mode selection r0 0 wu 0 bit read/write initial value on reset bit name 3 not used 2 not used 1 not used 0 w 0 pmr10 pmr10 0 1 port mode register 1 (pmr1: $009) figure 27 port mode register 1 (pmr1: $009) r1 0 /evnb pin mode selection r1 0 evnb bit read/write initial value on reset bit name 3 w 0 pmr23 pmr23 0 1 r1 3 /tob pin mode selection r1 3 tob 0 w 0 pmr20 pmr20 0 1 port mode register 2 (pmr2: $00a) 1 not used 2 not used figure 28 port mode register 2 (pmr2: $00a)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 65 of 161 r2 0 /toc pin mode selection r2 0 toc bit read/write initial value on reset bit name 3 w 0 pmr33 2 w 0 pmr32 pmr32 * 0 1 pmr33 0 1 r2 2 /si/so pin mode selection r2 2 si so 1 w 0 pmr31 pmr31 0 1 r2 1 /sck pin mode selection r2 1 sck 0 w 0 pmr30 pmr30 0 1 port mode register 3 (pmr3: $00b) * : don't care figure 29 port mode register 3 (pmr3: $00b) pull-up mos control program-controllable pull-ups mos are incorporated in all i/o pins. on/off control of all pull-ups mos is performed by bit 3 (mis3) of the miscellaneous register (mis: $005) and the port data register (pdr) for each pin, enabling the pull-up mos to be turned on or off independently for each pin (table 22, figure 30). except for analog input multiplexed pins, the pull-up mos on/off setting can be made independent of the setting as an on-chip supporting module pin.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 66 of 161 bit read/write initial value on reset bit name 3 w 0 mis3 2 w 0 not used * 1 w 0 mis1 0 w 0 mis0 t rc selection (see figure 15 in the operating modes section) miscellaneous register (mis: $005) bit 2 of the miscellaneous register must always be set to 0. the microcomputer will malfunction if it is set to 1. mis3 0 1 pull-up mos control all pull-ups mos off pull-up mos active note: * this bit must always be set to 0. the microcomputer will malfunction if it is set to 1. mis2 0 1 setting bit2 set to 0 use prohibited figure 30 miscellaneous register (mis:$005) handling of i/o pins not used by user system if i/o pins that are not used by the user system are left floating, they may generate noise that can result in chip malfunctions. therefore, the pin potential must be fixed. in this case, pull the pins up to v cc with the built-in pull-up mos or with an external resistor of approximately 100 k ? .
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 67 of 161 prescalers the mcu has the following prescalers, s and w (hd404374 series). the operating conditions for each prescaler are shown in table 24, and the output supply destinations in figure 31. timer a to c input clocks other than external events, and serial transfer clocks other than external clocks are selected from the prescaler outputs in accordance with the respective mode register. prescaler operation prescaler s (pss): prescaler s is an 11-bit counter that has the system clock as input. when the mcu is reset, prescaler s is reset to $000, then divides the system clock. prescaler s operation is stopped by a reset by the mcu, and in stop mode and watch mode *1 . it does not stop in any other modes. prescaler w (psw) (hd404374 series): prescaler w is a counter that has a clock divided from the x1 input (32 khz crystal oscillation) as input. when the mcu is reset, prescaler w is reset to $00, then divides the input clock. prescaler w can also be reset by software. table 24 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock in active and standby modes, subsystem clock in subactive mode * 1 mcu reset, stop mode clearance mcu reset, stop mode, watch mode * 1 prescaler w clock obtained by division- by-8 of 32.768 khz oscillation by subsystem clock oscillator mcu reset, software * 2 mcu reset, stop mode notes: * 1 applies to hd404374 series * 2 if bits tma3 to tma1 in timer mode register a (tma) are all set to 1, psw is cleared to $00.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 68 of 161 prescaler w system clock prescaler s clock selector subsystem clock serial interface timer c timer b timer a hd404374 series figure 31 prescaler output destinations
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 69 of 161 timers the mcu incorporates three timers, a to c. ? timer a: free-running timer ? timer b: multifunctional timer ? timer c: multifunctional timer timer a is an 8-bit free-running timer. timers b and c are 8-bit multifunctional timers; each one of their have the functions shown in table 25 and their operating mode can be set by the program. table 25 timer functions functios timer a timer b timer c prescaler s available available available prescaler w * available ? ? clock source external event ? available ? free-running available available available time-base * available ? ? event counter ? available ? reload ? available available timer functions watchdog ? ? available toggle ? available available timer outputs pwm ? available available note: ? implies not available * applies to hd404374 series timer a timer a functions timer a has the following functions. ? free-running timer ? realtime clock time base the block diagram of timer a is shown in figure 32.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 70 of 161 1/4 1/2 32.768-khz oscillator system clock data bus clock line signal line prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 t wcyc f t wcyc ? per 2 4 8 32 128 512 1024 2048 2 8 16 32 w w hd404374 series figure 32 timer a block diagram timer a operation free-running timer operation: the timer a input clock is selected by timer mode register a (tma: $00f). timer a is reset to $00 by an mcu reset, and counts up each time the input clock is input. when the input clock is input after the timer a value reaches $ff, overflow output is generated, and the timer a value becomes $00. the generated overflow output sets the timer a interrupt request flag (ifta: $002,0). timer a continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. realtime clock time base operation (hd404374 series): timer a can be used as the realtime clock time base by setting bit 3 (tma3) of timer mode register a to 1. as the prescaler w output is input to timer/counter a, interrupts are generated with accurate timing using the 32.768 khz crystal oscillator as the basic clock. when timer a is used as the realtime clock time base, prescaler w and timer/counter a can be reset to $00 by the program.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 71 of 161 timer a register timer a operation is set by means of the following register. timer mode register a (tma: $00f): timer mode register a (tma: $00f) is a 4-bit write-only register. timer a operation and input clock selection are set as shown in figure 33.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 72 of 161 bit read/write initial value on reset bit name 3 w 0 tma3* 4 2 w 0 tma2 1 w 0 tma1 0 w 0 tma0 tma3* 4 0 1 tma2 0 1 1 0 tma1 0 1 1 0 1 0 0 1 tma0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x source prescaler pss pss pss pss pss pss pss pss psw psw psw psw psw input clock period 2,048 t cyc 1,024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 32 t wcyc 16 t wcyc 8 t wcyc 2 t wcyc 1/2 t wcyc operating mode timer a mode time base mode timer mode register a (tma: $00f) not used psw, tca reset x : don't care notes : 1. t wcyc = 244.14 ? (using 32.768 khz crystal oscillator) 2. timer/counter overflow output period (s) = input clock period (s) 256. 3. the division ratio must not be changed while time base mode is being used, as this will result in an error in the overflow period. 4. applies to hd404374 series. in hd404384, hd404389, hd404082 and hd404084 series, write as 0. figure 33 timer mode register a (tma)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 73 of 161 timer b timer b functions: timer b has the following functions. ? free-running/reload timer ? external event counter ? timer output operation (toggle output, pwm output) the block diagram of timer b is shown in figure 34. 3 3 4 4 4 timer b ineterrupt request flag (iftb) (tcbl) (tcbu) timer read register bu (trbu) internal data bus timer read register bl (trbl) timer counter b timer write register b (twbl) (twbu) free-runnning/reload control timer mode register b1 (tmb1) timer mode register b2 (tmb2) data bus clock line signal line selector overflow prescaler s (pss) system clock 2 4 8 32 128 512 2048 timer output control logic timer c clock source edge detection logic tob evnb ? per 1 2 figure 34 timer b block diagram
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 74 of 161 timer b operation ? free-running/reload timer: free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register b1 (tmb1). timer b is initialized to the value written to timer write register b (twbl, twbu) by software, and counts up by 1 each time the input clock is input. when the input clock is input after the timer b value reaches $ff, overflow output is generated. timer b is then set to the value in timer write register b if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. overflow output sets the timer b interrupt request flag (iftb). this flag is reset by the program or by an mcu reset. for details, see figure 3, interrupt control bit and register flag area configuration, and table 1, initial values after mcu reset. ? external event counter operation: when external event input is designated for the input clock, timer b operates as an external event counter. when external event input is used, the r1 0 /evnb pin is designated as the evnb pin by port mode register 2 (pmr2). the external event detected edge for timer b can be designated as a falling edge, rising edge, or both falling and rising edges in the input signal by means of timer mode register b2 (tmb2). if both falling and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc. timer b counts up by 1 each time a falling edge is detected in the signal input at the evnb pin. other operations are the same as for the free-running/reload timer function. ? timer output operation: with timer b, the r13/tob pin is designated as the tob pin by the setting of bit 3 of port mode register 2 (pmr2), and toggle waveform output or pwm waveform output can be selected by timer mode register b2 (tmb2). ? toggle output: with toggle output, the output level is changed upon input of the next clock pulse after the timer b value reaches $ff. use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. the output waveform is shown in figure 35 (1). ? pwm output: with pwm output, variable-duty pulses are output. the output waveform is as shown in figure 35 (2), according to the contents of timer mode register b1 (tmb1) and timer write register b (twbl, twbu). when the waveform is output with bit 3 (tmb13) of timer mode register b1 cleared to 0, the write to timer write register b to change the duty is effective from the next frame, whereas if the waveform is output with the tmb13 bit set to 1 (reload setting), the next frame is output immediately after the timer write register write. ? module standby: with timer b, the supply of the system clock to the timer/counter can be halted by setting bit 0 of module standby register 1 (msr1: $00d) to 1. in the module standby state, the mode register value is retained but the counter value is not guaranteed.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 75 of 161 (1) toggle output waveform (timer b, timer c) (2) pwm output waveform (timer b, timer c) ( ) 256 clock periods 256 clock periods free-running timer (256 ? n) clock periods (256 ? n) clock periods reload timer t (n + 1) t 256 t t (256 ? n) tmb13 = 0 tmc13 = 0 (free-running timer) tmb13 = 1 tmc13 = 1 (reload timer) notes: t: counter input clock period the clock input source and division ratio are controlled by timer mode register b1 and timer mode register c1. n: value in timer write register b or timer write register c when n = 255 (= $ff), pwm output is always fixed at the timer low level.) figure 35 timer output waveforms
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 76 of 161 timer b registers timer b operation setting and timer b value reading/writing is controlled by the following registers. timer mode register b1 (tmb1: $010) timer mode register b2 (tmb2: $011) timer write register b (twbl: $012, twbu: $013) timer read register b (trbl: $012, trbu: $013) port mode register 2 (pmr2: $00a) module standby register 1 (msr1: $00d) ? timer mode register b1 (tmb1: $010): timer mode register b1 (tmb1) is a 4-bit write-only register, used to select free-running/reload timer operation and the input clock as shown in figure 36. timer mode register b1 (tmb1) is reset to $0 by an mcu reset: a modification of timer mode register b1 (tmb1) becomes effective after execution of two instructions following the timer mode register b1 (tmb1) write instruction. the program must provide for timer b initialization by writing to timer write register b (twbl, twbu) to be executed after the post- modification mode has become effective. 3 w 0 tmb13 2 w 0 tmb12 1 w 0 tmb11 0 w 0 tmb10 bit read/write initial value on reset bit name 0 1 tmb12 tmb11 tmb10 0 1 0 1 0 1 0 1 0 1 input clock period and input clock source 1 2,048 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc r1 0 /evnb (external event input) 0 tmb13 0 1 free-running/reload timer free-running timer reload timer timer mode register b1 (tmb1: $010) figure 36 timer mode register b1 (tmb1)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 77 of 161 ? timer mode register b2 (tmb2: $011): timer mode register b2 (tmb2) is a 3-bit write-only register, used to select the timer b output mode and evnb pin detected edge as shown in figure 37. timer mode register b2 (tmb2) is reset to $0 by an mcu reset. tmb20 0 1 0 1 evnb pin detected edge not detected falling edge detection rising edge detection both rising and falling edge detection tmb22 0 1 timer b output waveform toggle output pwm output tmb21 0 1 timer mode register b2 (tmb2: $011) bit read/write initial value on reset bit name 3 ? ? ? 2 w 0 tmb22 1 w 0 tmb21 0 w 0 tmb20 figure 37 timer mode register b2 (tmb2) ? timer write register b (twbl: $012, twbu:$013): timer write register b (twbl, twbu) is a write-only register composed of a lower digit (twbl) and an upper digit (twbu) (figures 38 and 39). the lower digit (twbl) of timer write register b is reset to $0 by an mcu reset, while the upper digit (twbu) is undetermined. timer b can be initialized by writing to timer write register b (twbl, twbu). to write the data, first write the lower digit (twbl). the lower digit write does not change the timer b value. next, write the upper digit (twbu). timer b is then initialized to the timer write register b (twbl, twbu) value. when writing to timer write register b (twbl, twbu) from the second time onward, if it is not necessary to change the lower digit (twbl) reload value, timer b initialization is completed by the upper digit write alone.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 78 of 161 3 w 0 twbl3 2 w 0 twbl2 1 w 0 twbl1 0 w 0 twbl0 timer write register b (lower) (twbl: $012) bit read/write initial value on reset bit name figure 38 timer write register b (lower) (twbl) 3 w undetermined twbu3 2 w undetermined twbu2 1 w undetermined twbu1 0 w undetermined twbu0 timer write register b (upper) (twbu: $013) bit read/write initial value on reset bit name figure 39 timer write register b (upper) (twbu) ? timer read register b (trbl: $012, trbu: $013): timer read register b (trbl, trbu) is a read-only register composed of a lower digit (trbl) and an upper digit (trbu) from which the value of the upper digit of timer b is read directly (figures 40 and 41). first, read the upper digit (trbu) of timer read register b. the current value of the timer b upper digit is read and, at the same time, the value of the timer b lower digit is latched in the lower digit (trbl) of timer read register b. the timer b value is obtained when the upper digit (trbu) of timer read register b is read by reading the lower digit (trbl) of timer read register b. 3 r undetermined trbl3 2 r undetermined trbl2 1 r undetermined trbl1 0 r undetermined trbl0 timer read register b (lower) (trbl: $012) bit read/write initial value on reset bit name figure 40 timer read register b (lower) (trbl)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 79 of 161 bit read/write initial value on reset bit name 3 r undetermined trbu3 2 r undetermined trbu2 1 r undetermined trbu1 0 r undetermined trbu0 timer read register b (upper) (trbu: $013) figure 41 timer read register b (upper) (trbu) ? port mode register 2 (pmr2: $00a): port mode register 2 (pmr2) is a write-only register used to set the function of the r1 0 /evnb and r1 3 /tob pins as shown in figure 42. port mode register 2 (pmr2) is reset to $0 by an mcu reset. r1 0 /evnb pin mode selection r1 0 evnb bit read/write initial value on reset bit name 3 w 0 pmr23 pmr23 0 1 r1 3 /tob pin mode selection r1 3 tob 2 ? ? not used 1 ? ? not used 0 w 0 pmr20 pmr20 0 1 port mode register 2 (pmr2: $00a) figure 42 port mode register 2 (pmr2: $00a) ? module standby register 1 (msr1: $00d): module standby register 1 (msr1) is a write-only register used to designate supply or stopping of the clock to timer b as shown in figure 43. module standby register 1 (msr1) is reset to $0 by an mcu reset.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 80 of 161 timer b clock supply control supplied stopped bit read/write initial value on reset bit name 3 ? ? not used 2 ? ? not used 1 w 0 msr11 msr11 0 1 timer c clock supply control supplied stopped 0 w 0 msr10 msr10 0 1 module standby register 1 (msr1: $00d) figure 43 module standby register 1 (msr1)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 81 of 161 timer c timer c functions:timer : c has the following functions. ? free-running/reload timer ? watchdog timer ? timer output operation (toggle output, pwm output) the block diagram of timer c is shown in figure 44.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 82 of 161 (twcl) (twcu) 2 4 8 32 128 512 per 3 4 4 4 toc 2048 (tccl) (tccu) system reset signal watchdog on flag (wdon) timer output control logic timer b overflow system clock prescaler (pss) watchdog timer control logic timer c interrupt request flag (iftc) timer read register cl (trcl) timer read register cu (trcu) overflow timer counter c timer write register c timer mode register c1 (tmc1) timer output control timer mode register c2 (tmc2) selector free-running/reload control internal data bus data bus clock line signal line figure 44 timer c block diagram
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 83 of 161 timer c operation ? free-running/reload timer: free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register c1 (tmc1). timer c is initialized to the value written to timer write register c (twcl, twcu) by software, and counts up by 1 each time the input clock is input. when the input clock is input after the timer c value reaches $ff, overflow output is generated. timer c is then set to the value in timer write register c (twcl, twcu) if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. overflow output sets the timer c interrupt request flag (iftc). this flag is reset by the program or by an mcu reset. for details, see figure 3, interrupt control bit and register flag area configuration, and table 1, initial values after mcu reset. ? 16-bit timer operation: when timer b overflow flag is selected as the clock source, timer c can be used as a 16-bit timer that counts the timer b clock source pulses. in this case, since the timer b and timer c free-running/reload settings are independent, the settings should be made to suit the purpose. ? watchdog timer operation: by using the timer c overflow output, timer c can be used as a watchdog timer for detecting program runaway. the watchdog timer is enabled when the watchdog on flag (wdon) is set to 1, and generates an mcu reset when timer c overflows. usually, timer c initialization is performed by the program before the timer c value reaches $ff, so controlling program runaway. ? timer output operation: with timer c, the r2 0 /toc pin is designated as the toc pin by setting bit 0 of port mode register 3 (pmr3) to 1, and toggle waveform output or pwm waveform output can be selected by timer mode register c2 (tmc2). ? toggle output the operation is similar to that for timer b toggle output. ? pwm output the operation is similar to that for timer b pwm output. ? module standby: the operation is similar to that for timer b module standby.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 84 of 161 timer c registers timer c operation setting and timer c value reading/writing is controlled by the following registers. timer mode register c1 (tmc1: $014) timer mode register c2 (tmc2: $015) timer write register c (twcl: $016, twcu: $017) timer read register c (trcl: $016, trcu: $017) port mode register 3 (pmr3: $00b) module standby register 1 (msr1: $00d) ? timer mode register c1 (tmc1: $014): timer mode register c1 (tmc1) is a 4-bit write-only register, used to select free-running/reload timer operation, the input clock, and the prescaler division ratio as shown in figure 45. timer mode register c1 (tmc1) is reset to $0 by an mcu reset. a modification of timer mode register c1 (tmc1) becomes effective after execution of two instructions following the timer mode register c1 (tmc1) write instruction. the program must provide for timer c initialization by writing to timer write register c (twcl, twcu) to be executed after the post- modification mode has become effective.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 85 of 161 3 w 0 tmc13 2 w 0 tmc12 1 w 0 tmc11 0 w 0 tmc10 timer mode register c1 (tmc1: $014) tmc12 tmc11 tmc10 input clock period 2,048 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc timer b overflow 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tmc13 0 1 bit read/write initial value on reset bit name free-running/reload timer free-running timer reload timer figure 45 timer mode register c1 (tmc1)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 86 of 161 ? timer mode register c2 (tmc2: $015): timer mode register c2 (tmc2) is a 1-bit write-only register, used to select the timer c output mode as shown in figure 46. timer mode register c2 (tmc2) is reset to $0 by an mcu reset. 3 ? ? ? 2 w 0 tmc22 tmc22 0 1 1 ? ? ? 0 ? ? ? timer mode register c2 (tmc2: $015) bit read/write initial value on reset bit name timer c output waveform toggle output pwm output figure 46 timer mode register c2 (tmc2) ? timer write register c (twcl: $016, twcu: $017): timer write register c (twcl, twcu) is a write-only register composed of a lower digit (twcl) and an upper digit (twcu) (figures 47 and 48). timer write register c (twcl, twcu) operation is similar to that for timer write register b (twbl, twbu). timer write register c (lower) (twcl: $016) 3 w 0 twcl3 2 w 0 twcl2 1 w 0 twcl1 0 w 0 twcl0 bit read/write initial value on reset bit name figure 47 timer write register c (lower) (twcl)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 87 of 161 timer write register c (upper) (twcu: $017) bit read/write initial value on reset bit name 3 w undetermined twcu3 2 w undetermined twcu2 1 w undetermined twcu1 0 w undetermined twcu0 figure 48 timer write register c (upper) (twcu) ? timer read register c (trcl: $016, trcu: $017): timer read register c (trcl, trcu) is a read-only register composed of a lower digit (trcl) and an upper digit (trcu) from which the value of the upper digit of timer c is read directly (figures 49 and 50). timer read register c (trcl, trcu) operation is similar to that for timer read register b (trbl, trbu). timer read register c (lower) (trcl: $016) bit read/write initial value on reset bit name 3 r undetermined trcl3 2 r undetermined trcl2 1 r undetermined trcl1 0 r undetermined trcl0 figure 49 timer read register c (lower) (trcl) timer read register c (upper) (trcu: $017) bit read/write initial value on reset bit name 3 r undetermined trcu3 2 r undetermined trcu2 1 r undetermined trcu1 0 r undetermined trcu0 figure 50 timer read register c (upper) (trcu)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 88 of 161 ? port mode register 3 (pmr3: $00b): port mode register 3 (pmr3) is a write-only register used to set the function of the r2 0 /toc pin as shown in figure 51. port mode register 3 (pmr3) is reset to $0 by an mcu reset. r2 0 /toc pin mode selection r2 0 toc bit read/write initial value on reset bit name 3 w 0 pmr33 2 w 0 pmr32 pmr32 ? 0 1 pmr33 0 1 r2 2 /si/so pin mode selection r2 2 si so 1 w 0 pmr31 pmr31 0 1 r2 1 / pin mode selection r2 1 sck 0 w 0 pmr30 pmr30 0 1 port mode register 3 (pmr3: $00b) ? : don't care figure 51 port mode register 3 (pmr3) ? module standby register 1 (msr1: $00d): module standby register 1 (msr1) is a write-only register used to designate supply or stopping of the clock to timer c as shown in figure 43. module standby register 1 (msr1) is reset to $0 by an mcu reset.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 89 of 161 serial interface the serial interface serially transfers and receives 8-bit data, and includes the following features. ? multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock ? output level control in idle states five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. ? serial data register (srl: $026, sru: $027) ? serial mode register 1 (smr1: $024) ? serial mode register 2 (smr2: $025) ? port mode register 3 (pmr3: $00b) ? octal counter (oc) ? selector the block diagram of the serial interface is shown in figure 52.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 90 of 161 2 8 32 128 si/so sck system clock per 512 2048 1/2 1/2 serial interrupt request flag (ifs) octal counter (oc) idle control logic i/o control logic clock transfer control data bus clock line signal line serial mode register 1 (smr1) serial mode register 2 (smr2) serial data register (srl/u) internal data bus selector selector prescalers (pss) 2 4 figure 52 serial interface block diagram
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 91 of 161 serial interface operation selecting and changing serial interface operating mode: the operating modes that can be selected for the serial interface are shown in table 26. the combination of port mode register 3 (pmr3) values should be selected from this table. when the serial interface operating mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1 (smr1). note : the serial interface is initialized by writing to serial mode register 1 (smr1: $024). see figure 56 serial mode register 1, for details. table 26 serial interface operating modes pmr3 bit3 bit2 bit1 serial interface operating mode 0 * 1 clock continuous output mode 1 0 1 receive mode 1 1 1 transmit mode note : * don't care serial interface pin setting: the r2 1 / sck pin and r2 2 /si/so pin are set by writing data to port mode register 3 (pmr3). see serial interface registers, for details. serial clock source setting: the serial clock is set by writing data to serial mode register 1 (smr1). see serial interface registers, for details. serial data setting: transmit serial data is set by writing data to the serial data register (srl, sru). receive serial data is obtained by reading the serial data register (srl, sru). serial data is shifted by means of the serial clock to perform input/output from/to an external device. the output level of the so pin is undetermined until the first data is output after a reset by the mcu, or until high/low control is performed in the idle state. transfer control: serial interface operation is started by an sts instruction. the octal counter is reset to 000 by the sts instruction, and is incremented by 1 on each rise of the serial clock. when 8 serial clock pulses have been input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial interrupt request flag (ifs) is set, and transfer is terminated. the serial clock is selected by means of serial mode register 1 (smr1). see figure 56.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 92 of 161 serial interface operating states: the serial interface has the operating states shown in figure 53 in external clock mode and internal clock mode. sts instruction wait state serial clock wait state transfer state clock continuous output state (internal clock mode only) ? sts instruction wait state upon mcu reset ((00) and (10) in figure 53), the serial interface enters the sts instruction wait state. in the sts instruction wait state, the internal state of the serial interface is initialized. even if the serial clock is input at this time, the serial interface will not operate. when the sts instruction is executed ((01), (11)), the serial interface enters the serial clock wait state. ? serial clock wait state the serial clock wait state is the interval from sts instruction execution until the first serial clock falling edge. when the serial clock is input in the serial clock wait state ((02), (12)), the octal counter begins counting, the contents of the serial data register (srl, sru) begin shifting, and the serial interface enters the transfer state. however, if clock continuous output mode is selected in internal clock mode, the serial interface enters the clock continuous output state ((17)) instead of the transfer state. if a write to serial mode register 1 (smr1) is performed in the serial clock wait state, the serial interface enters the sts instruction wait state ((04), (14)). ? transfer state the transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising edge. in the transfer state, if an sts instruction is executed or if eight serial clocks have been input, the octal counter is cleared to 000, and the serial interface makes a state transition. if an sts instruction is executed ((05), (15)), the serial interface enters the serial clock wait state. after eight serial clocks have been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and enters the sts instruction wait state ((13)) when in internal clock mode. in internal clock mode, the serial clock stops after output of eight clocks. if a write to serial mode register 1 (smr1) is performed in the transfer state ((06), (16)), the serial interface is initialized and enters the sts instruction wait state. when the serial interface switches from the transfer state to another state, the octal counter is reset to 000 and the serial interrupt request flag (ifs) is set. ? clock continuous output state (internal clock mode only) in the clock continuous output state, no receive or transmit operation is performed, and the serial clock is only output from the sck pin. it is therefore effective in internal clock mode. if the serial clock is input ((17)) when bit 3 (pmr33) of port mode register 3 (pmr3) is cleared to 0 and the serial interface is in the serial clock wait state, a transition is made to the clock continuous output state. if a write to serial mode register 1 (smr1) is performed in the clock continuous output state ((18)), the serial interface enters the sts instruction wait state.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 93 of 161 sts instruction wait state (octal counter ="000", serial clock disabled) mcu reset (00) serial clock wait state (octal counter ="000") transfer state (octal counter ?"000") smr1 write (14) sts instruction (11) serial clock (12) serial clocks (03) sts instruction (05) (ifs "1") sts instruction (15) (ifs"1") external clock mode sts instruction wait state (octal counter ="000", serial clock disabled) serial clock wait state (octal counter ="000") transfer state (octal counter ?"000") smr1 write (04) sts instruction (01) serial clock (02) smr1 write (06) (ifs "1") 8 serial clocks (13) smr1 write (16) (ifs"1") mcu reset (10) serial clock (17) smr1 write (18) clock continuous output state (pmr33 ="0") internal clock mode ( ) refer to the text for details on the circled numbers in the figure. 8 figure 53 serial interface operating states
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 94 of 161 idle high/low control: when the serial interface is in the sts instruction wait state or the serial clock wait state (i.e. when idle), the output level of the so pin can be set arbitrarily by software. idle high/low control is performed by writing the output level to bit 1 (smr21) of serial mode register 2 (smr2). an example of idle high/low control is shown in figure 54. idle high/low control cannot be performed in the transfer state.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 95 of 161 state pin (input) so pin ifs msb lsb undefined idle idle idle idle idle h/l setting dummy write to cause state transition port setting sts wait state serial clock wait state transfer state sts wait state serial clock wait state external clock setting idle h/l setting (flag reset by transfer completion processing) mcu reset pmr3 write smr1 write smr2 write srl, sru write sts instruction state pin (output) so pin ifs msb lsb undefined idle h/l setting port setting sts wait state serial clock wait state transfer state sts wait state (flag reset by transfer completion processing) mcu reset pmr3 write smr1 write smr2 write srl, sru write sts instruction (2) internal clock mode (1) external clock mode external clock setting transmit data write transmit data write idle h/l setting figure 54 examples of serial interface operation sequence
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 96 of 161 serial clock error detection (external clock mode): the serial interface will operate incorrectly in the transfer state if external noise results in unnecessary pulses being added to the serial clock. serial clock error detection in such cases is carried out as shown in figure 55. if more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt request flag (ifs) is set. at the same time, the serial interface exits the transfer state and enters the serial clock wait state, but returns to the transfer state at the next regular clock pulse falling edge. meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt request flag is reset, and a dummy write is performed into serial mode register 1 (smr1). the serial interface then returns to the sts wait state, and the serial interrupt request flag (ifs) is set again. it is therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy write to serial mode register 1. usage notes: ? initialization after register modification if a port mode register 3 (pmr3) write is performed in the serial clock wait state or transfer state, a serial mode register 1 (smr1) write should be performed again to initialize the serial interface. ? serial interrupt request flag (ifs:$023, 2) setting if a serial mode register 1 (smr1) write or sts instruction is executed during the first low-level interval of the serial clock in the transfer state, the serial interrupt request flag (ifs) will not be set. to ensure that the serial interrupt request flag (ifs) is properly set in this case, programming is required to make sure that the sck pin is in the 1 state (by executing an input instruction for the r2 port) before executing a serial mode register 1 (smr1) write or an sts instruction.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 97 of 161 transfer end (ifs"1") disable interrupts ifs"0" smr1 write ifs=1? normal termination serial clock error processing (1) serial clock error detection flowchart serial clock wait state transfer state serial clock wait state transfer state (noise) state sck pin (input) smr1 write ifs 1234567 8 (2) serial clock error detection sequence flag set by octal counter reaching 000 flag reset by transfer end processing yes no because the serial interface returns to the transfer state, a write to smr1 resets ifs. figure 55 example of serial clock error detection
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 98 of 161 serial interface registers serial interface operation setting and serial data reading/writing is controlled by the following registers. serial mode register 1 (smr1: $024) serial mode register 2 (smr2: $025) serial data register (srl: $026, sru: $027) port mode register 3 (pmr3: $00b) module standby register 2 (msr2: $00e) serial mode register 1 (smr1: $024): serial mode register 1 (smr1) has the following functions. see figure 56. ? serial clock selection ? prescaler division ratio selection ? serial interface initialization the serial mode register 1 (smr1) is a 4-bit write-only register, and is reset to $0 by an mcu reset. a write to serial mode register 1 (smr1) halts the supply of the serial clock to the serial data register (srl, sru) and the octal counter, and resets the octal counter to 000. therefore, if serial mode register 1 (smr1) is written to during serial interface operation, data transmission/reception will be suspended and the serial interrupt request flag (ifs) will be set. a modification of serial mode register 1 (smr1) becomes effective after execution of two instructions following the serial mode register 1 (smr1) write instruction. the program must therefore provide for the sts instruction to be executed two cycles after the instruction that writes to serial mode register 1 (smr1).
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 99 of 161 serial mode register 1 (smr1: $024) smr13 smr12 smr11 smr10 sck pin serial clock source serial clock (pss division ratio + 2 or 4) serial clock cycle 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 output output output output output output output input output output output output output output output input pss pss pss pss pss pss system clock external clock pss pss pss system clock external clock pss pss pss ( per /2048)+2 ( per /512)+2 ( per /128)+2 ( per /32)+2 ( per /8)+2 ( per /2)+2 per ( per /2048)+4 ( per /512)+4 ( per /128)+4 ( per /32)+4 ( per /8)+4 ( per /2)+4 per 4096 tcyc 1024 tcyc 256 tcyc 64 tcyc 16 tcyc 4 tcyc tcyc 8192 tcyc 2048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc tcyc bit read/write initial value on reset bit name 3 w 0 smr13 2 w 0 smr12 1 w 0 smr11 0 w 0 smr10 figure 56 serial mode register 1 (smr1) serial mode register 2 (smr2: $025): serial mode register 2 (smr2) has the following functions. see figure 57. ? r2 2 /si/so pin pmos control ? idle high/low control serial mode register 2 (smr2) is a 2-bit write-only register. the register value cannot be modified in the transfer state. bit 2 (smr22) of serial mode register 2 (smr2) controls the on/off status of the r2 2 /si/so pin pmos. the bit 2 (smr22) only is reset to 0 by an mcu reset. bit 1 (smr21) of serial mode register 2 (smr2) performs so pin high/low control in the idle state. the so pin changes at the same time as the high/low write.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 100 of 161 smr21 0 1 r2 2 /si/so pin output buffer control pmos active pmos off (nmos open-drain output) smr22 0 1 idle high/low control so pin set to low-level output in idle state so pin set to high-level output in idle state serial mode register 2 (smr2: $025) bit read/write initial value on reset bit name 3 ? ? ? 2 w 0 smr22 1 w undeternined smr21 0 ? ? figure 57 serial mode register 2 (smr2) serial data register (srl: $026, sru: $027): the serial data register (srl, sru) has the following functions. see figures 58 and 59. ? transmit data write and shift operations ? receive data shift and read operations the data written to the serial data register (srl, sru) is output lsb-first from the so pin in synchronization with the falling edge of the serial clock. external data input lsb-first from the si pin is latched in synchronization with the rising edge of the serial clock. figure 60 shows the serial clock and data input/output timing chart. writing and reading of the serial data register (srl, sru) must be performed only after data transmission/reception is completed. the data contents are not guaranteed if a read or write is performed during data transmission or reception.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 101 of 161 serial data register (lower) (srl: $026) 3 r/w undetermined sr3 2 sr2 1 sr1 0 sr0 r/w r/w r/w undetermined undetermined undetermined bit read/write initial value on reset bit name figure 58 serial data register (srl) serial data register (upper) (sru: $027) 3 r/w undetermined sr7 2 sr6 1 sr5 0 sr4 r/w r/w r/w undetermined undetermined undetermined bit read/write initial value on reset bit name figure 59 serial data register (sru) 12345678 serial clock serial output data serial input data latch timing lsb msb figure 60 serial interface input/output timing chart
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 102 of 161 port mode register 3 (pmr3: $00b): port mode register 3 (pmr3) has the following functions. see figure 61. ? r2 1 / sck pin selection ? r2 2 /si/so pin selection port mode register 3 (pmr3) is a 4-bit write-only register used to select serial interface pin settings as shown in figure 61. it is reset to $0 by an mcu reset. r2 0 /toc pin mode selection pmr30 r2 1 /sck pin mode selection pmr31 0 1 r2 0 toc 0 1 r2 1 sck pmr33 pmr32 0 1 ? 0 1 r2 2 /si/so pin mode selection r2 2 si so ? : don't care port mode register 3 (pmr3: $00b) bit read/write initial value on reset bit name 3 w 0 pmr33 2 w 0 pmr32 1 w 0 pmr31 0 w 0 pmr30 figure 61 port mode register 3 (pmr3)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 103 of 161 module standby register 2 (msr2: $00e): module standby register 2 (msr2) is a write-only register used to designate supply or stopping of the clock to the serial interface as shown in figure 62. module standby register 2 (msr2) is reset to $0 by an mcu reset. serial clock supply control supplied stopped msr20 a/d clock supply control supplied stopped msr21 0 1 0 1 module standby register 2 (msr2: $00e) bit read/write initial value on reset bit name 3 ? ? ? 2 ? ? ? 1 w 0 msr21 0 w 0 msr20 figure 62 module standby register 2 (msr2)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 104 of 161 a/d converter (hd404374/hd404384/hd404389 series) the mcu has a built-in successive approximation type a/d converter using a resistance ladder method, capable of digital conversion of four analog inputs with an 10-bit resolution. the a/d converter block diagram is shown in figure 63. the a/d converter comprises the following four registers. ? a/d mode register (amr: $028) ? a/d start flag (adsf: $020,2) ? a/d data register (adrl: $029, adrm: $02a, adru: $02b) ? module standby register 2 (msr2: $00e) note : with the hd404374, hd404384, and hd404389 series emulator, write 1 to bit 0 (adrl0) of a/d data register-lower (adrl). this bit need not be written in the mask rom and ztat tm versions in these series, although writing 1 will have no effect. interrupt flag (ifad) encoder a/d data register (adru, adrm, adrl) internal data bus selector conversion time control a/d start flag (adsf) comp reference voltage reference voltage control r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 *an 4 *an 5 r7 3 /an 3 + ? a/d control logic a/d mode register (amr) av cc note: * applies to hd404389 series. av ss d/a 3 operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby) figure 63 a/d converter block diagram
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 105 of 161 a/d mode register (amr: $028): the a/d mode register is a 4-bit write-only register that shows the a/d converter speed setting and information on the analog input pin specification. the a/d conversion time is selected by bit 0, and the channel by bits 1, 2, and 3 (figure 64). a/d start flag (adsf: $020,2): a/d conversion is started by writing 1 to the a/d start flag. when conversion ends, the converted data is placed in the a/d data register and the a/d start flag is cleared at the same time. (figure 65). bit read/write initial value on reset bit name 3 w 0 amr3 2 w 0 amr2 1 w 0 amr1 0 w 0 amr0 analog input channel selection no selection an0 an1 an2 an3 an4* an5* amr1 ? 0 1 0 1 0 1 amr2 0 1 0 1 amr3 0 1 amr0 0 1 a/d conversion time 65 t cyc 125 t cyc a/d mode register (amr: $028) note: * applies to the hd404389 series. this selection is not available on the hd 404374 and hd404384 series. figure 64 a/d mode register (amr)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 106 of 161 bit read/write initial value on reset bit name 3 r/w 0 dton 2 r/w 0 adsf 1 r/w 0 wdon 0 r/w 0 lson a/d start flag (adsf: $020,2) 1 0 dton (see low-power mode section) wdon (see timer section) lson (see low-power mode section) a/d start flag (adsf) a/d conversion starts indicates end of a/d conversion figure 65 a/d start flag (adsf) a/d data register (adrl: $029, adrm: $02a, adru: $02b): the a/d data register is a read-only register consisting of a middle 4 bits and lower 2 bits. this register is not cleared by a reset. also, data read during a/d conversion is not guaranteed. at the end of a/d conversion, the resulting 10-bit data is stored in this register, and is held until the next conversion operation starts (figures 66, 67, 68, and 69). msb lsb bit9 bit0 adru : $02b adrm : $02a adrl : $029 3 2 1 0 3 2 1 0 3 2 figure 66 a/d data register
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 107 of 161 bit read/write initial value on reset bit name 3 r 1 adrl3 2 r 1 adrl2 1 ? ? not used 0 ? ?* not used a/d data register-lower (adrl: $029) note: * should be written with 1 with the emulator. figure 67 a/d data register-lower (adrl) bit read/write initial value on reset bit name 3 r 1 adrm3 2 r 1 adrm2 1 r 1 adrm1 0 r 1 adrm0 a/d data register-middle (adrm: $02a) figure 68 a/d data register-middle (adrm) bit read/write initial value on reset bit name 3 r 0 adru3 2 r 1 adru2 1 r 1 adru1 0 r 1 adru0 a/d data register-upper (adru: $02b) figure 69 a/d data register-upper (adru) module standby register 2 (msr2: $00e): writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the a/d module and cuts the current (i ad ) flowing in the ladder resistor.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 108 of 161 usage notes: ? use the sem or semd instruction to write to the a/d start flag (adsf). ? do not write to the adsf during a/d conversion. ? data in the a/d data register is undetermined during a/d conversion. ? as the a/d converter operates on a clock from osc, it stops in stop mode, watch mode, and subactive mode. the current flowing in the a/d converter ladder resistor is also cut in these low-power modes to reduce power consumption. ? when an analog input pin is selected by the a/d mode register, the pull-up mos for that pin is disabled. ? use of bit 0 of a/d data register-lower (adrl) is prohibited, but with the emulator it should be written with 1. this bit need not be written in the mask rom and ztat tm versions, although writing 1 will have no effect.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 109 of 161 ztat tm microcomputer with built-in programmable rom precautions for use of ztattm microcomputer with built-in programmable rom (1) precautions for writing to programmable rom built in ztattm microcomputer in the ztat tm microcomputer with built-in plastic mold one-time programmable rom, incomplete electrical connection between the prom writer and socket adapter causes writing errors and, makes the computer unoperatable. to enhance the writing efficiency, attention should be paid to the following points: (a) make sure that the socket adapter is firmly fixed to the prom writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) to secure the electrical connection between the contact pin and ic lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) when inserting the ic, be careful to protect the ic lead from bending in order to secure the electrical connection between the contact pin and ic lead. if the lead is bent, correct the bending and insert it again. (d) if any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) during the writing process, do not touch the socket adapter and ic to prevent erroneous writing. (f) to write continuously in the ic, follow steps (a), (b), (c), (d) and (e). (g) if a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the prom writer, socket adapter, etc. for defects. (h) if any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) precautions when new prom writer, socket adapter or ic is used when a new prom writer, socket adapter or ic is employed, breakdown of the ic may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured ic writing characteristics. to avoid such troubles, check the following points before starting the writing process. (a) to ensure stable writing operation, check that the v cc of the power supplied to the prom writer, power source current capacity of v pp , and current consumption at the time of writing to ic are provided with sufficient margin. (b) to prevent breakdown of the ic, check that the power source voltage between gnd-v cc and gnd- v pp , and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n connection may be damaged, leading to permanent breakdown. if overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) to prevent breakdown of the ic and for stable writing and reading operation, insert the ic into the socket adapter and check the power noise between the gnd-v cc and gnd-v pp near the ic connecting
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 110 of 161 terminal. if power source noise is noticed, insert an appropriate capacitor between the gnd power sources depending on the noise generated. in case of high frequency noise , insert a capacitor of low inductance. (d) for stable writing and reading operation, insert the ic into the socket adapter and check the input waveform, timing and noise near the r/w, cs, address and data terminals. particularly, since recent ics have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. to avoid these problems, inserting a low inductance capacitor between the gnd and power source or inserting a damping resistance to the output data terminal is effective. (e) particularly, when a multiple prom writer is used, perform above items (a), (b), (c), and (d) assuming all ics inserted into the socket adapter. (f) in the case of a multiple prom writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. therefore, the potential increases due to erroneous writing because of improper connection. be sure to check the electrical connection between the prom writer and socket adapter and ic. (g) if any abnormality is noticed while checking a written program, consult our technical staff. programming of built-in programmable rom the mcu can stop its function as an mcu in prom mode for programming the built-in prom. prom mode is set up by setting the reset and mo terminals to ? low ? level and the test terminal to ? vpp ? level. writing and reading specifications of the prom are the same as those for the commercial eprom27256. using a socket adapter for specific use of each product, programming is possible with a general-purpose prom writer. since an instruction of the hmcs400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose prom writer. this circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. this enables use of a general-purpose prom. for instance, to write to a 16kword of built-in prom writer with a general-purpose prom, specify 32kbyte address ($0000-$7fff). an example of prom memory map is shown in figure 70.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 111 of 161 notes: 1. when programming with a prom writer, set up each rom size to the address given in table 29. if it is programmed erroneously to an address given in table 29 or later, check of writing of prom may become impossible. particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. set the data in unused addresses to $ff. 2. if the indexes of the prom writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. be sure to check that they are properly set to the writer before starting the writing process. 3. two levels of program voltages (v pp ) are available for the prom: 12.5v and 21v. our product employs a v pp of 12.5v. if a voltage of 21v is applied, permanent breakdown of the product will result. the v pp of 12.5v is obtained for the prom writer by setting it according to the intel 27258 specifications. table 27 socket adapters package model name manufacturer fp-30d please ask renesas technology service section. dp-28s please ask renesas technology service section. writing/verification programming of the built-in program rom employs a high speed programming method. with this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. a basic programming flow chart is shown in figure 71 and a timing chart in figure 72. for precautions for prom writing procedure, refer to ? precautions for use of ztat tm microcomputer with build-in programmable rom ? . table 28 selection of mode mode ce cece ce oe oeoe oe v pp o 0 to o 4 writing ? low ? ? high ? v pp data input verification ? high ? ? low ? v pp data output prohibition of programming ? high ? ? high ? v pp high impedance
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 112 of 161 table 29 prom writer program address rom size address 2k $0000~$0fff 4k $0000~$1fff 8k $0000~$3fff 16k $0000~$7fff
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 113 of 161 programmable rom the hd407a4374/hd407c4374/hd407a4384/hd407c4384, hd407a4389/hd407c4389 are ztat tm microcomputers with built-in prom that can be programmed in prom mode. prom mode pin description (1) hd407a4374/hd407c4374/hd407a4384/hd407c4384 pin no. mcu mode prom mode. fp-30d dp-28s pin name i/o pin name i/o 1 1 gnd ? gnd ? 2 2 v cc ? v cc ? 3 3 av cc ? v cc ? 4 4 r7 0 /an 0 i/o o 0 i/o 5 5 r7 1 /an 1 i/o o 1 i/o 6 6 r7 2 /an 2 i/o o 2 i/o 7 7 r7 3 /an 3 i/o o 3 i/o 8 8 av ss ? gnd ? 9 9 osc 1 i a 0 i 10 10 osc 2 o ? ? 11 11 test i v pp ? 12 ? x 2 o ? ? 13 ? x 1 i gnd ? 14 12 reset i reset i 15 13 r0 0 / wu 0 i/o a 1 i 16 14 r1 0 /evnb i/o a 2 i 17 15 r1 3 /tob i/o o 4 i/o 18 16 r2 0 /toc i/o ce i 19 17 r2 1 / sck i/o a 2 i 20 18 r2 2 /si/so i/o a 3 i 21 19 d 0 / int 0 i/o mo i 22 20 d 1 i/o a 5 i 23 21 d 2 i/o a 6 i 24 22 d 3 i/o a 7 i 25 23 d 4 i/o a 8 i 26 24 d 5 i/o a 9 i 27 25 d 6 i/o a 10 i 28 26 d 7 i/o a 11 i 29 27 d 8 i/o a 12 i 30 28 d 9 i/o oe i
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 114 of 161 (2) hd407a4389 and hd407c4389 pin no. mcu mode prom mode. fp-30d pin name i/o pin name i/o 1 gnd ? gnd ? 2 v cc ? v cc ? 3 av cc ? v cc ? 4 r7 0 /an 0 i/o o 0 i/o 5 r7 1 /an 1 i/o o 1 i/o 6 r7 2 /an 2 i/o o 2 i/o 7 r7 3 /an 3 i/o o 3 i/o 8 an 4 i ce i 9 an 5 i oe i 10 av ss ? gnd 11 test i v pp ? 12 osc 1 i a 0 i 13 osc 2 o ? ? 14 reset i reset i 15 r0 0 / wu 0 i/o a 1 i 16 r1 0 /evnb i/o a 4 i 17 r1 3 /tob i/o o 4 i/o 18 r2 0 /toc i/o a 14 i 19 r2 1 / sck i/o a 2 i 20 r2 2 /si/so i/o a 3 i 21 d 0 / int 0 i/o mo i 22 d 1 i/o a 5 i 23 d 2 i/o a 6 i 24 d 3 i/o a 7 i 25 d 4 i/o a 8 i 26 d 5 i/o a 9 i 27 d 6 i/o a 10 i 28 d 7 i/o a 11 i 29 d 8 i/o a 12 i 30 d 9 i/o a 13 i note: i/o: i/o pin, i: input-only pin, o: output-only pin
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 115 of 161 1. unused data pins (o 5 to o 7 ) on the prom programmer side should be handled as shown below on the socket. v cc o 5 , o 6 , o 7 2. pin a 9 should be handled as shown below on the socket. v cc hd407a4374 hd407c4374 hd407a4384 hd407c4384 hd407a4389 hd407c4389 writer side a 9
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 116 of 161 pin functions in prom mode v pp : applies the on-chip prom programming voltage (12.5 v 0.3 v). ce cece ce : inputs a control signal to set the on-chip prom to the write/verify enabled state. oe oeoe oe : inputs a data output control signal during verification. a 0 to a 14 : on-chip prom address input pins. o 0 to o 4 : on-chip prom data bus i/o pins. mo momo mo , reset resetreset reset , test: prom mode setting pins. prom mode is set by driving the reset , and mo pins low, and driving the test pin to the v pp level. other pins: v cc and av cc should be connected to v cc potential. gnd, av ss , and x1 should be connected to gnd potential. other pins should be left open.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 117 of 161 $0000 1 11 1 11 vector address zero-page subroutine (64 words) pattern (4,096 words) program (16,384 words) $0001 $001f $0080 $007f $2000 $1fff $7fff $0020 bit 4 bit 8 bit 3 bit 7 bit 2 bit 6 bit 1 bit 5 bit 0 bit 9 upper three bits are not to be used (fill them with 111) upper 5 bits lower 5 bits $0000 $000f $0010 $003f $0040 $3fff $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to routine) jmpl instruction (jump to 0 routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to 0 routine) jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) . . . . . . . . . jmpl instruction (jump to a/d, serial routine) $07ff $0800 figure 70 memory map in prom mode
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 118 of 161 start set prog./verify mode v pp =12.50.3v, v cc =6.00.25v address=0 n=0 n+1n program t pw = 1ms5% verify go program t opw = 3nms last address? yes no nogo set read mode v cc =5.00.5v, v pp =v cc 0.6v read all address go end address + 1address yes n hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 119 of 161 programming electrical characteristics dc characteristics (v cc = 6v 0.25v, v pp = 12.5v 0.3v, v ss = 0v, t a = 25c 5c, unless otherwise specified) item symbol test conditions min typ max unit input high voltage o 0 to o 4 ,a 0 to a 14 , oe , ce v ih 2.2 ? v cc +0.3 v input low voltage o 0 to o 4 ,a 0 to a 14 , oe , ce v il ?0.3 ? 0.8 v output high voltage o 0 to o 4 v oh i oh =?200a 2.4 ? ? v output low voltage o 0 to o 4 v ol i ol =1.6ma ? ? 0.4 v input leakage current o 0 to o 4 ,a 0 to a 14 , oe , ce ? i il ? v in =5.25v/0.5v ? ? 2 a v cc current i cc ? ? 30 ma v pp current i pp ? ? 40 ma ac characteristics (v cc = 6v 0.25v, v pp = 12.5v 0.3v, t a = 25c 5c, unless otherwise specified) item symbol test conditions min typ max unit address setup time t as 2 ? ? s oe setup time t oes 2 ? ? s data setup time t ds 2 ? ? s address hold time t ah 0 ? ? s data hold time t dh 2 ? ? s data output disable time t df ? ? 130 ns v pp setup time t vps 2 ? ? s program pulse width t pw 0.95 1.0 1.05 ms ce pulse width during overprogramming t opw 2.85 ? 78.75 ms v cc setup time t vcs 2 ? ? s data output delay time t oe see figure 72 0 ? 500 ns notes: input pulse level: 0.8 v to 2.2 v input rise/fall times: 20ns input timing reference levels: 1.0 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 120 of 161 program verify address data v pp v cc v cc v pp v cc gnd ce oe data in stable data out valid t as t ds t dh t df t ah t pw t oes t oe t opw t vps t vcs figure 72 prom write/verify timing
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 121 of 161 notes on prom programming principles of programming/erasure: a memory cell in a ztat ? microcomputer is the same as an eprom cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. these electrons are stable, surrounded by an energy barrier formed by an sio 2 film. the change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 73). the charge in a memory cell may decrease with time. this decrease is usually due to one of the following causes: ? ultraviolet light excites electrons, allowing them to escape. this effect is the basis of the erasure principle. ? heat excites trapped electrons, allowing them to escape. ? high voltages between the control gate and drain may erase electrons. if the oxide film covering a floating gate is defective, the electron erasure rate will be greater. however, electron erasure does not often occur because defective devices are detected and removed at the testing stage. control gate floating gate drain sio 2 source write (0) control gate floating gate drain sio 2 source erasure (1) n + n + n + n + figure 73 cross-sections of a prom cell prom programming: prom memory cells must be programmed under specific voltage and timing conditions. the higher the programming voltage v pp and the longer the programming pulse t pw is applied, the more electrons are injected into the floating gates. however, if v pp exceeds specifications, the pn junctions may be permanently damaged. pay particular attention to overshooting in the prom programmer. in addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. the ztat ? microcomputer is electrically connected to the prom programmer by a socket adapter. therefore, note the following points: ? check that the socket adapter is firmly mounted on the prom programmer. ? do not touch the socket adapter or the lsi during the programming. touching them may affect the quality of the contacts, which will cause programming errors.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 122 of 161 prom reliability after programming: in general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. these initial defects can be detected and rejected by screening. baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (refer to the previous principles of programming/erasure section.) ztat ? microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but hitachi recommends that each device be exposed to 150 c at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. the recommended screening procedure is shown in figure 74. note: if programming errors occur continuously during prom programming, suspend programming and check for problems in the prom programmer or socket adapter. if programming verification indicates errors in programming or after high-temperature exposure, please inform renesas technology. programming, verification exposure to high temperature, without power 150?c 10?c, 48 h 8h* 0h program read check v cc = 4.5 v or 5.5 v note: * exposure time is measured from when the temperature in the heater reaches 150?c. figure 74 recommended screening procedure programming percentage: programming percentage is guarenteed to more than 95%.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 123 of 161 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 75 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register indirect addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 75 ram addressing modes
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 124 of 161 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 76 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ? pc 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ? pc 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 78. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross assembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 ? $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ? pc 0 ), and 0s are placed in the eight high- order bits (pc 13 ? pc 6 ). table data addressing mode: a program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 77. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter. branch destination of br instruction on page boundary: if a br instruction is located on a page boundary (256n + 255), because of the hardware architecture the program counter contents will shift to the next page when that instruction is executed. when using a br instruction on a page boundary, therefore, the branch destination must be set within the next page (see figure 78). the hmcs400-series cross assembler has an automatic paging feature for rom pages, regardless of the model.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 125 of 161 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pcpcpcpc 10111213 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10111213 program counter 00 00 0000 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pcpcpc 10111213 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 00 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pcpcpc 111213 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 76 rom addressing modes
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 126 of 161 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 rarara 101112 13 b 2 b 3 b register 00 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data note: designate ro 9 as 0. cannot assign pattern output to port r. figure 77 p instruction br aaa aaa nop 256 (n 1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 78 branching when the branch destination is on a page boundary
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 127 of 161 instruction set the mcu series has 101 instructions, classified into the following 10 groups: ? immediate instructions ? register-to-register instructions ? ram addressing instructions ? ram register instructions ? arithmetic instructions ? compare instructions ? ram bit manipulation instructions ? rom addressing instructions ? input/output instructions ? control instructions the functions of these instructions are listed in tables 30 to 39, and an opcode map is shown in table 40. table 30 immediate instructions operation mnemonic operation code function status words/ cycles load a from immediate lai i 1 0 0 0 1 1 i 3 i 2 i 1 i 0 i a 1/1 load b from immediate lbi i 1 0 0 0 0 0 i 3 i 2 i 1 i 0 i b 1/1 load memory from immediate lmid i,d 0 1 1 0 1 0 i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m 2/2 load memory from immediate, increment y lmiiy i 1 0 1 0 0 1 i 3 i 2 i 1 i 0 i m, y + 1 y nz 1/1 table 31 register-register instructions operation mnemonic operation code function status words/ cycles load a from b lab 0 0 0 1 0 0 1 0 0 0 b a 1/1 load b from a lba 0 0 1 1 0 0 1 0 0 0 a b 1/1 load a from w law 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w a 2/2 * load a from y lay 0 0 1 0 1 0 1 1 1 1 y a 1/1 load a from spx laspx 0 0 0 1 1 0 1 0 0 0 spx a 1/1 load a from spy laspy 0 0 0 1 0 1 1 0 0 0 spy a 1/1 load a from mr lamr m 1 0 0 1 1 1 m 3 m 2 m 1 m 0 mr (m) a 1/1 exchange mr and a xmra m 1 0 1 1 1 1 m 3 m 2 m 1 m 0 mr (m) ? a 1/1 note: * the assembler automatically provides an operand for the second word of the law instruction.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 128 of 161 table 32 ram address instructions operation mnemonic operation code function status words/ cycles load w from immediate lwi i 0 0 1 1 1 1 0 0 i 1 i 0 i w 1/1 load x from immediate lxi i 1 0 0 0 1 0 i 3 i 2 i 1 i 0 i x 1/1 load y from immediate lyi i 1 0 0 0 0 1 i 3 i 2 i 1 i 0 i y 1/1 load w from a lwa * 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a w 2/2 * load x from a lxa 0 0 1 1 1 0 1 0 0 0 a x 1/1 load y from a lya 0 0 1 1 0 1 1 0 0 0 a y 1/1 increment y iy 0 0 0 1 0 1 1 1 0 0 y + 1 y nz 1/1 decrement y dy 0 0 1 1 0 1 1 1 1 1 y ? 1 y nb 1/1 add a to y ayy 0 0 0 1 0 1 0 1 0 0 y + a y ovf 1/1 subtract a from y syy 0 0 1 1 0 1 0 1 0 0 y ? a y nb 1/1 exchange x and spx xspx 0 0 0 0 0 0 0 0 0 1 x ? spx 1/1 exchange y and spy xspy 0 0 0 0 0 0 0 0 1 0 y ? spy 1/1 exchange x and spx, y and spy xspxy 0 0 0 0 0 0 0 0 1 1 x ? spx,y ? spy 1/1 note: * the assembler automatically provides an operand for the second word of the law and lwa instruction.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 129 of 161 table 33 ram register instructions operation mnemonic operation code function status words/ cycles lam 0 0 1 0 0 1 0 0 0 0 m a lamx 0 0 1 0 0 1 0 0 0 1 m a x ? spx lamy 0 0 1 0 0 1 0 0 1 0 m a y ? spy load a from memory lamxy 0 0 1 0 0 1 0 0 1 1 m a x ? spx, y ? spy 1/1 load a from memory lamd d 0 1 1 0 0 1 0 0 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m a 2/2 lbm 0 0 0 1 0 0 0 0 0 0 m b lbmx 0 0 0 1 0 0 0 0 0 1 m b x ? spx lbmy 0 0 0 1 0 0 0 0 1 0 m b y ? spy load b from memory lbmxy 0 0 0 1 0 0 0 0 1 1 m b x ? spx, y ? spy 1/1 lma 0 0 1 0 0 1 0 1 0 0 a m lmax 0 0 1 0 0 1 0 1 0 1 a m x ? spx lmay 0 0 1 0 0 1 0 1 1 0 a m y ? spy load memory from a lmaxy 0 0 1 0 0 1 0 1 1 1 a m x ? spx, y ? spy 1/1 load memory from a lmad d 0 1 1 0 0 1 0 1 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m 2/2 lmaiy 0 0 0 1 0 1 0 0 0 0 a m, y + 1 y load memory from a, increment y lmaiyx 0 0 0 1 0 1 0 0 0 1 a m, y + 1 y x ? spx nz 1/1 lmady 0 0 1 1 0 1 0 0 0 0 a m, y ? 1 y load memory from a, decrement y lmadyx 0 0 1 1 0 1 0 0 0 1 a m, y ? 1 y x ? spx nb 1/1
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 130 of 161 table 33 ram register instructions (cont) operation mnemonic operation code function status words/ cycles xma 0 0 1 0 0 0 0 0 0 0 m ? a xmax 0 0 1 0 0 0 0 0 0 1 m ? a x ? spx xmay 0 0 1 0 0 0 0 0 1 0 m ? a y ? spy exchange memory and a xmaxy 0 0 1 0 0 0 0 0 1 1 m ? a x ? spx, y ? spy 1/1 exchange memory and a xmad d 0 1 1 0 0 0 0 0 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m ? a 2/2 xmb 0 0 1 1 0 0 0 0 0 0 m ? b xmbx 0 0 1 1 0 0 0 0 0 1 m ? b x ? spx xmby 0 0 1 1 0 0 0 0 1 0 m ? b y ? spy exchange memory and b xmbxy 0 0 1 1 0 0 0 0 1 1 m ? b x ? spx, y ? spy 1/1
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 131 of 161 table 34 arithmetic instructions operation mnemonic operation code function status words/ cycles add immediate to a ai i 1 0 1 0 0 0 i 3 i 2 i 1 i 0 a + i a ovf 1/1 increment b ib 0 0 0 1 0 0 1 1 0 0 b + 1 b nz 1/1 decrement b db 0 0 1 1 0 0 1 1 1 1 b ? 1 b nb 1/1 decimal adjust for addition daa 0 0 1 0 1 0 0 1 1 0 1/1 decimal adjust for subtraction das 0 0 1 0 1 0 1 0 1 0 1/1 negate a nega 0 0 0 1 1 0 0 0 0 0 a + 1 a 1/1 complement b comb 0 1 0 1 0 0 0 0 0 0 b b 1/1 rotate right a with carry rotr 0 0 1 0 1 0 0 0 0 0 1/1 rotate left a with carry rotl 0 0 1 0 1 0 0 0 0 1 1/1 set carry sec 0 0 1 1 1 0 1 1 1 1 1 ca 1/1 reset carry rec 0 0 1 1 1 0 1 1 0 0 0 ca 1/1 test carry tc 0 0 0 1 1 0 1 1 1 1 ca 1/1 add a to memory am 0 0 0 0 0 0 1 0 0 0 m + a a ovf 1/1 add a to memory amd d 0 1 0 0 0 0 1 0 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m + a a ovf 2/2 add a to memory with carry amc 0 0 0 0 0 1 1 0 0 0 m + a + ca a ovf ca ovf 1/1 add a to memory with carry amcd d 0 1 0 0 0 1 1 0 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m + a + ca a ovf ca ovf 2/2 subtract a from memory with carry smc 0 0 1 0 0 1 1 0 0 0 m ? a ? ca a nb ca nb 1/1 subtract a from memory with carry smcd d 0 1 1 0 0 1 1 0 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m ? a ? ca a nb ca nb 2/2 or a and b or 0 1 0 1 0 0 0 1 0 0 a b a 1/1 and memory with a anm 0 0 1 0 0 1 1 1 0 0 a m a nz 1/1 and memory with a anmd d 0 1 1 0 0 1 1 1 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m a nz 2/2 or memory with a orm 0 0 0 0 0 0 1 1 0 0 a m a nz 1/1 or memory with a ormd d 0 1 0 0 0 0 1 1 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m a nz 2/2 eor memory with a eorm 0 0 0 0 0 1 1 1 0 0 a m a nz 1/1 eor memory with a eormd d 0 1 0 0 0 1 1 1 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m a nz 2/2
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 132 of 161 table 35 compare instructions operation mnemonic operation code function status words/ cycles immediate not equal to memory inem i 0 0 0 0 1 0 i 3 i 2 i 1 i 0 i m nz 1/1 immediate not equal to memory inemd i,d 0 1 0 0 1 0 i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m nz 2/2 a not equal to memory anem 0 0 0 0 0 0 0 1 0 0 a m nz 1/1 a not equal to memory anemd d 0 1 0 0 0 0 0 1 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m nz 2/2 b not equal to memory bnem 0 0 0 1 0 0 0 1 0 0 b m nz 1/1 y not equal to immediate ynei i 0 0 0 1 1 1 i 3 i 2 i 1 i 0 y i nz 1/1 immediate less than or equal to memory ilem i 0 0 0 0 1 1 i 3 i 2 i 1 i 0 i m nb 1/1 immediate less than or equal to memory ilemd i,d 0 1 0 0 1 1 i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m nb 2/2 a less than or equal to memory alem 0 0 0 0 0 1 0 1 0 0 a m nb 1/1 a less than or equal to memory alemd d 0 1 0 0 0 1 0 1 0 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m nb 2/2 b less than or equal to memory blem 0 0 1 1 0 0 0 1 0 0 b m nb 1/1 a less than or equal to immediate alei i 1 0 1 0 1 1 i 3 i 2 i 1 i 0 a i nb 1/1 table 36 ram bit manipulation instructions operation mnemonic operation code function status words/ cycles set memory bit sem n 0 0 1 0 0 0 0 1 n 1 n 0 i m (n) 1/1 set memory bit semd n,d 0 1 1 0 0 0 0 1 n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m (n) 2/2 reset memory bit rem n 0 0 1 0 0 0 1 0 n 1 n 0 0 m (n) 1/1 reset memory bit remd n,d 0 1 1 0 0 0 1 0 n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 m (n) 2/2 test memory bit tm n 0 0 1 0 0 0 1 1 n 1 n 0 m (n) 1/1 test memory bit tm n,d 0 1 1 0 0 0 1 1 n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m (n) 2/2
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 133 of 161 table 37 rom address instructions operation mnemonic operation code function status words/ cycles branch on status 1 br b 1 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 1/1 long branch on status 1 brl u 0 1 0 1 1 1 p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2/2 long jump unconditionally jmpl u 0 1 0 1 0 1 p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2/2 subroutine jump on status 1 cal a 0 1 1 1 a 5 a 4 a 3 a 2 a 1 a 0 1 1/2 long subroutine jump on status 1 call u 0 1 0 1 1 0 p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2/2 table branch tbr p 0 0 1 0 1 1 p 3 p 2 p 1 p 0 1/1 return from subroutine rtn 0 0 0 0 0 1 0 0 0 0 1/3 return from interrupt rtni 0 0 0 0 0 1 0 0 0 1 1 ie, carry restored st 1/3 table 38 input/output instructions operation mnemonic operation code function status words/ cycles set discrete i/o latch sed 0 0 1 1 1 0 0 1 0 0 1 d (y) 1/1 set discrete i/o latch direct sedd m 1 0 1 1 1 0 m 3 m 2 m 1 m 0 1 d (m) 1/1 reset discrete i/o latch red 0 0 0 1 1 0 0 1 0 0 0 d (y) 1/1 reset discrete i/o latch direct redd m 1 0 0 1 1 0 m 3 m 2 m 1 m 0 0 d (m) 1/1 test discrete i/o latch td 0 0 1 1 1 0 0 0 0 0 d (y) 1/1 test discrete i/o latch direct tdd m 1 0 1 0 1 0 m 3 m 2 m 1 m 0 d (m) 1/1 load a from r-port register lar m 1 0 0 1 0 1 m 3 m 2 m 1 m 0 r (m) a 1/1 load b from r-port register lbr m 1 0 0 1 0 0 m 3 m 2 m 1 m 0 r (m) b 1/1 load r-port register from a lra m 1 0 1 1 0 1 m 3 m 2 m 1 m 0 a r (m) 1/1 load r-port register from b lrb m 1 0 1 1 0 0 m 3 m 2 m 1 m 0 b r (m) 1/1 pattern generation p p 0 1 1 0 1 1 p 3 p 2 p 1 p 0 1/2
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 134 of 161 table 39 control instructions operation mnemonic operation code function status words/ cycles no operation nop 0 0 0 0 0 0 0 0 0 0 1/1 start serial sts 0 1 0 1 0 0 1 0 0 0 1/1 standby mode/watch mode * sby 0 1 0 1 0 0 1 1 0 0 1/1 stop mode/watch mode stop 0 1 0 1 0 0 1 1 0 1 1/1 note: * only after a transition from subactive mode.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 135 of 161 table 40 opcode map r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lbi i(4) lyi i(4) lxi i(4) lai i(4) lbr m(4) lar m(4) redd m(4) lamr m(4) ai i(4) lmiiy i(4) tdd m(4) alei i(4) lrb m(4) lra m(4) sedd m(4) xmra m(4) 0 0 1 one word/two cycle instructions one word/three cycle instructions ram direct address instructions (two word/two cycle) two word/two cycle instructions 0123456789abcdef nop xspx xspy xspxy anem am orm lbm(xy) bnem lab ib lmaiy(x) ayy laspy iy rtn rtni alem amc eorm nega red laspx tc inem i(4) ilem i(4) ynei i(4) xma(xy) lam(xy) sem n(2) lma(xy) rem n(2) smc tm n(2) anm rotr daa das lay rotl db dy sec lba lya rec lxa blem syy sed xmb(xy) lmady(x) td lwi i(2) tbr p(4)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 136 of 161 absolute maximum ratings item symbol value unit notes power supply voltage v cc ? 0.3 to +7.0 v programming voltage v pp ? 0.3 to +14.0 v 1 pin voltage v t ? 0.3 to v cc +0.3 v allowable input current (total) l 0 100 ma 2 allowable output current (total) ? l 0 50 ma 3 l 0 4 ma 4,5 allowable input current (per pin) 30 ma 4,6 ? l 0 4 ma 7,8 allowable output current (per pin) 20 ma 7,9 topr ? 20 to +75 c 10, 12 operating temperature ? 40 to +85 c 11, 12 storage temperature tstg ? 55 to +125 c 13 notes: permanent damage may occur if these maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to the hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd407a4389, and hd407c4389 test (v pp ) pin. 2. the allowable input current (total) is the sum of all currents flowing from i/o pins to ground at the same time. 3. the allowable output current (total) is the sum of all currents flowing from v cc to i/o pins. 4. the allowable input current (per pin) is the maximum current allowed to flow from any one i/o pin to ground. 5. applies to pins d 0 to d 3 , d 8 , d 9 and port r. 6. applies to pins d 4 to d 7 . 7. the allowable output current (per pin) is the maximum current allowed to flow from v cc to any one i/o pin. 8. applies to pins d 4 to d 9 and port r. 9. applies to pins d 0 to d 3 . 10. applies to mask rom 11. applies to ztat tm . 12. the operating temperature indicates the temperature range in which power can be supplied to the lsi (voltage vcc shown in the electrical characteristics tables can be applied). 13. in the case of chips, the storage specification differs from that of the package products. please consult your hitachi sales representative for details.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 137 of 161 electrical characteristics dc characteristics (hd404372, hd40a4372, hd40c4372, hd404374, hd40a4374, hd40c4374, hd404382, hd40a4382, hd40c4382, hd404384, hd40a4384, hd40c4384, hd404388, hd40a4388, hd40c4388, hd404389, hd40a4389, hd40c4389, hd404081, hd40a4081, hd40c4081, hd404082, hd40a4082, hd40c4082, hd404084, hd40a4084, hd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = ? 20 c to +75 c; hcd404082, hcd40c4082, hcd40 4084, hcd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd407a4389, hd407c4389: v cc = 2.0 v to 5.5 v, gnd = 0 v, t a = ? 40 c to +85 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes reset , sck , si, int 0 , wu 0 , evnb 0.90v cc ? v cc +0.3 v input high voltage v ih osc 1 v cc ? 0.3 ? v cc +0.3 v external clock operation reset , sck , si, int 0 , wu 0 , evnb ? 0.3 ? 0.10v cc v input low voltage v il osc 1 ? 0.3 ? 0.3 v external clock operation output high voltage v oh sck ,so, tob, toc v cc ? 0.5 ? ? v ? i oh =0.3ma output low voltage v ol sck ,so, tob, toc ? ? 0.4 v i ol =0.4ma i/o leakage current | i il | reset , sck , si, int 0 , wu 0 , evnb, osc 1 , tob, toc, so ? ? 1 a v in =0v to v cc 1 ? 1.5 3.5 ma v cc =5v, f osc =4mhz 2, 7 l cc1 ? 1.2 2.5 ma 2, 8 ? 0.4 1.0 ma v cc =3v, f osc =800khz 2, 7 l cc2 ? 0.3 0.7 ma 2, 8 ? 2.7 9.0 ma v cc =5v, f osc =8mhz 2, 9 active mode current dissipation l cc3 v cc ? 2.2 4.5 ma 2, 10 ? 1.0 1.5 ma v cc =5v, f osc =4mhz 3, 7 l sby1 ? 0.6 1.3 ma 3, 8 ? 0.3 0.6 ma v cc =3v, f osc =800khz 3, 7 l sby2 ? 0.2 0.5 ma 3, 8 ? 1.4 4.0 ma v cc =5v, f osc =8mhz 3, 9 standby mode current dissipation l sby3 v cc ? 1.0 2.5 ma 3, 10 subactive mode current dissipation l sub v cc ? 18 35 a v cc = 3v, 32 khz oscillator used 4, 5 watch mode current dissipation l wtc v cc ? 6 10 a v cc = 3 v, 32 khz oscillator used 4, 5
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 138 of 161 item symbol pins min. typ. max. unit test conditions notes stop mode current dissipation l stop v cc ? ? 5 a v cc = 3 v, no 32 khz oscillator 4 stop mode retention voltage v stop v cc 1.5 ? ? v no 32 khz oscillator 6 notes: 1. excludes output buffer current. 2. power supply current when the mcu is in the reset state and there are no i/o currents. mcu state reset state test conditions pin states reset , test: at ground 3. power supply current when the on-chip timers are operating and there are no i/o currents. mcu state i/o: same as reset state standby mode f cyc = f osc /4 test conditions pin states reset : at v cc test: at ground d port, r port: at v cc 4. power supply current when there are no i/o currents. test conditions pin states reset : at v cc test: at ground d port, r port: at v cc 5. applies to hd404374 series. 6. voltage needed to retain ram data. 7. applies to hd404374, hd404384, and hd404389 series. 8. applies to hd404082 and hd404084 series. 9. applies to hd40a4374/2, hd407a4374, hd40a4384/2, hd407a4384, hd40a4389/8 and hd407a4389. 10. applies to hd40a4082/1 and hd40a4084.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 139 of 161 i/o characteristics for standard pins dc characteristics (hd404372, hd40a4372, hd40c4372, hd404374, hd40a4374, hd40c4374, hd404382, hd40a4382, hd40c4382, hd 404384, hd40a4384, hd40c4384, hd404388, hd40a4388, hd40c4388, hd404389, hd40a4389, hd40c4389, hd404081, hd40a4081, hd40c4081, hd404082, hd40a4082, hd40c4082, hd404084, hd40a4084, hd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = ? 20 c to +75 c; hcd404082, hcd40c4082, hcd404084, hcd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd407a4389, hd407c4389: v cc = 2.0 v to 5.5 v, gnd = 0 v, t a = ? 40 c to +85 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes input high voltage v ih r port, d 8 , d 9 0.7v cc ? v cc +0.3 v input low voltage v il r port, d 8 , d 9 ? 0.3 ? 0.3v cc v output high voltage v oh r port, d 8 , d 9 v cc ? 0.5 ? ? v ? i oh =0.3ma output low voltage v ol r port, d 8 , d 9 ? ? 0.4 v i ol =0.4ma i/o leakage current | i il | r port, d 8 , d 9 ? ? 1 a v in =0v to v cc 1 mos pull-up current ? i pu r port, d 8 , d 9 10 50 150 a v cc =3v, v in =0v note: 1. excludes output buffer current. i/o characteristics for high-current pins dc characteristics (hd404372, hd40a4372, hd40c4372, hd404374, hd40a4374, hd40c4374, hd404382, hd40a4382, hd40c4382, hd404384, hd40a4384, hd40c4384, hd404388, hd40a4388, hd40c4388, hd404389, hd40a4389, hd40c4389, hd404081, hd40a4081, hd40c4081, hd404082, hd40a4082, hd40c4082, hd404084, hd40a4084, hd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = ? 20 c to +75 c; hcd404082, hcd40c4082, hcd404084, hcd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd407a4389, hd407c4389: v cc = 2.0 v to 5.5 v, gnd = 0 v, t a = ? 40 c to +85 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes input high voltage v ih d 0 to d 7 0.7v cc ? v cc +0.3 v input low voltage v il d 0 to d 7 ? 0.3 ? 0.3v cc v d 4 to d 7 v cc ? 0.5 ? ? v ? i oh =0.3ma output high voltage v oh d 0 to d 3 v cc ? 2.0 ? ? v ? i oh =10ma, v cc =4.5 to 5.5v d 0 to d 3 ? ? 0.4 v i ol =0.4ma output low voltage v ol d 4 to d 7 ? ? 2.0 v i ol =15ma v cc =4.5v to 5.5v i/o leakage current | i il | d 0 to d 7 ? ? 1 a v in =0v to v cc 1 mos pull-up current ? i pu d 0 to d 7 10 50 150 a v cc =3v, v in =0v note: 1. excludes output buffer current.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 140 of 161 a/d converter characteristics (hd404374/hd404384/hd404389 series) (mask rom: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = ? 20 c to +75 c; ztat tm : v cc = 2.0 v to 5.5 v, gnd = 0 v, t a = ? 20 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes analog power supply voltage av cc av cc v cc ? 0.3 v cc v cc +0.3 v 1 analog input voltage av in an 0 to an 5 av ss ? av cc v av cc -av ss current i ad ? ? 500 a v cc =av cc =5.0v analog input capacitance ca in an 0 to an 5 ? 15 ? pf resolution ? 10 ? bit number of inputs 0 ? 4 channel v cc =av cc =1.8v to 5.5v 2 absolute accuracy ? ? 4.0 lsb v cc =av cc =2.0v to 5.5v 3 125 ? ? t cyc v cc =av cc =1.8v to 2.0v or less 2 conversion time 65 ? ? t cyc v cc =av cc =2.0v to 5.5v input impedance an 0 to an 5 1 ? ? m notes: 1. connect to the v cc pin when the a/d converter is not used. the av cc setting range is 1.8 v av cc 5.5v (mask rom), 2.0v av cc 5.5v (ztat tm ). 2. applies to mask rom. 3. applies to ztat tm .
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 141 of 161 ac characteristics dc characteristics (hd404372, hd40a4372, hd40c4372, hd404374, hd40a4374, hd40c4374, hd404382, hd40a4382, hd40c4382, hd404384, hd40a4384, hd40c4384, hd404388, hd40a4388, hd40c4388, hd404389, hd40a4389, hd40c4389, hd404081, hd40a4081, hd40c4081, hd404082, hd40a4082, hd40c4082, hd404084, hd40a4084, hd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = ? 20 c to +75 c; hcd404082, hcd40c4082, hcd404084, hcd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd407a4389, hd407c4389: v cc = 2.0 v to 5.5 v, gnd = 0 v, t a = ? 40 c to +85 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes 0.4 ? 4.5 1 f osc osc 1 , osc 2 0.4 ? 8.5 mhz division by 4 1, 3 clock oscillation frequency (ceramic oscillator, crystal oscillator) f x x1,x2 ? 32.768 ? khz 4 0.5 2.0 3.5 2, 13 clock oscillation frequency (resistance oscillation) f osc osc 1 , osc 2 0.5 2.2 3.5 mhz division by 4 rf=20 k 2, 12 0.89 ? 10 t cyc 0.47 ? 10 s division by 4 3 ? 244.14 ? s 32 khz oscillator used, division by 8 4 instruction cycle time (external clock, ceramic oscillator, crystal oscillator) t subcyc ? 122.07 ? s 32 khz oscillator used, division by 4 4 instruction cycle time (resistance oscillation) t cyc 1.14 ? 8.0 s division by 4 rf=20 k 5 oscillation settling time (external clock input) t rc osc 1 , osc 2 ? ? 7.5 ms 6 oscillation settling time (ceramic oscillator) t rc osc 1 , osc 2 ? ? 7.5 ms v cc =2.0 to 5.5v 6 osc 1 , osc 2 ? ? 30 ms v cc =2.0 to 5.5v 6 oscillation settling time(crystal oscillator) t rc x1,x2 ? ? 2 s t a = ? 10 to +60 c, v cc =2.0 to 5.5v 4, 6 oscillation setting time (resistance oscillation) t rc osc 1 , osc 2 ? ? 0.5 ms rf=20 k v cc =2.0 to 5.5v 5, 6 105 f osc =4mhz 7 external clock high- level width t cph osc 1 52.5 ? ? ns f osc =8mhz 3, 7 105 f osc =4mhz 7 external clock low- level width t cpl osc 1 52.5 ? ? ns f osc =8mhz 3, 7 20 f osc =4mhz 7 external clock rise time t cpr osc 1 ? ? 10 ns f osc =8mhz 3, 7 20 f osc =4mhz 7 external clock fall time t cpf osc 1 ? ? 10 ns f osc =8mhz 3, 7 int 0 , evnb, wu 0 , high-level width t ih int 0 , evnb, wu 0 2 ? ? t cyc /t subcyc 8
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 142 of 161 item symbol pins min. typ. max. unit test conditions notes int 0 , evnb, wu 0 , low-level width t il int 0 , evnb, wu 0 2 ? ? t cyc /t subcyc 8 reset low-level width t rstl reset 2 ? ? t cyc 9 reset rise time t rstr reset ? ? 20 ms 9 all input pins except test ? ? 15 pf test ? ? 15 pf 10 input capacitance c in test ? ? 40 pf f=1mhz,v in =0v 11 capacitance between osc 1 and osc 2 (resistance oscillation) c rf osc 1 , osc 2 ? ? 1 pf 5 notes: 1. when the subsystem oscillator (32.768 khz crystal oscillation) is used, use within the range 0.4 mhz f osc 1.0 mhz or 1.6 mhz f osc 8.5 mhz. the ssr1 bit of the system clock select register (ssr) should be set to 0 and 1, respectively. 2. the typ. value is the value when v cc = 3.5 v. 3. applies to hd40a4372/4, hd40a4382/4, hd40a4388/9, hd40a4081/2, hd40a4084, hd407a4374, hd407a4384 and hd407a4389 when v cc = 4.0 to 5.5 v. 4. applies to hd404374 series. 5. applies to hd40c4372/4, hd407c4374, hd40c4382/4, hd407c4384, hd40c4388/9, hd407c4389, hd40c4081/2, hcd40c4082, hd40c4084, hcd40c4084. 6. the oscillation settling time is defined as follows: (1) the time required for the oscillation to settle after v cc has reached standard minimum at power-on. (2) the time required for the oscillation to settle after reset input has gone low when stop mode is cleared. to ensure enough time for the oscillation to settle at power-on hold the reset input low for at least time t rc . the oscillation settling time will depend on the circuit constants and stray capacitance. the resonator should be determined in consultation with the resonator manufacturer. with regard to the system clock (osc 1 , osc 2 ), bits mis1 and mis0 in the miscellaneous register (mis) should be set according to the oscillation settling time of the resonator used. 7. see figure 79. 8. see figure 80. 9. see figure 81. 10. applies to mask rom. 11. applies to ztat tm . 12. applies to hd40c4081/2, hcd40c4082, hd40c4084, hcd40c4084. 13. applies to hd40c4372/4, hd407c4374, hd40c4382/4, hd407c4384, hd40c4388/9, hd407c4389.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 143 of 161 serial interface timing characteristics dc characteristics (hd404372, hd40a4372, hd40c4372, hd404374, hd40a4374, hd40c4374, hd404382, hd40a4382, hd40c4382, hd404384, hd40a4384, hd40c4384, hd404388, hd40a4388, hd40c4388, hd404389, hd40a4389, hd40c4389, hd404081, hd40a4081, hd40c4081, hd404082, hd40a4082, hd40c4082, hd404084, hd40a4084, hd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = ? 20 c to +75 c; hcd404082, hcd40c4082, hcd404084, hcd40c4084: v cc = 1.8 v to 5.5 v, gnd = 0 v, t a = +75 c; hd407a4374, hd407c4374, hd407a4384, hd407c4384, hd407a4389, hd407c4389: v cc = 2.0 v to 5.5 v, gnd = 0 v, t a = ? 40 c to +85 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes serial clock cycle time t scyc sck 1 ? ? t cyc see load in figure 83 1 serial clock high-level width t sckh sck 0.4 ? ? t scyc see load in figure 83 1 serial clock low-level width t sckl sck 0.4 ? ? t scyc see load in figure 83 1 serial clock rise time t sc kr sck ? ? 100 ns see load in figure 83 1 serial clock fall time t sckf sck ? ? 100 ns see load in figure 83 1 serial output data delay time t dso so ? ? 300 ns see load in figure 83 1 serial input data setup time t ssi si 200 ? ? ns 1 serial input data hold time t hsi si 200 ? ? ns 1 during serial clock input item symbol pins min. typ. max. unit test conditions notes serial clock cycle time t scyc sck 1 ? ? t cyc 1 serial clock high-level width t sckh sck 0.4 ? ? t scyc 1 serial clock low-level width t sckl sck 0.4 ? ? t scyc 1 serial clock rise time t sc kr sck ? ? 100 ns 1 serial clock fall time t sckf sck ? ? 100 ns 1 serial output data delay time t dso so ? ? 300 ns see load in figure 83 1 serial input data setup time t ssi si 200 ? ? ns 1 serial input data hold time t hsi si 200 ? ? ns 1 note: 1. see figure 82.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 144 of 161 1/f cp 0.3v v cc -0.3v t cpl t cph t cpr t cpf osc 1 figure 79 external clock input waveform 0.9v cc 0.1v cc t ih t il 0 ,evnb, 0 figure 80 interrupt timing 0.9v cc 0.1v cc t rstl t rstr figure 81 reset timing
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 145 of 161 so si t sck f v cc 0.5v(0.9v cc )* 0.4v(0.1v cc )* t scyc t sckr t sckl t dso t t sckh t hsi t ssi v cc 0.5v 0.4v 0.9v cc 0.1v cc note : v cc 0.5v and 0.4v are the voltages during serial clock output. 0.9 v cc and 0.1 v cc are the voltages during serial clock input. figure 82 serial interface timing v cc test point r l =2.6k? r=12k? c=30pf 1s2074(h) or equivalent figure 83 timing load circuit
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 146 of 161 0.0 1.0 2.0 3.0 4.0 5.0 23456 1 i cc (ma) v cc (v) fosc=8mhz fosc=4mhz fosc=2mhz fosc=800khz fosc=400khz 0.0 0.5 1.0 1.5 2.0 2.5 23456 1 i cc (ma) v cc (v) 1.0 1.5 2.0 2.5 23456 1 fosc (mhz) v cc (v) 0.0 1.0 2.0 3.0 4.0 5.0 10 20 30 40 50 0 fosc (mhz) rf (k ) 0.0 0.5 1.0 1.5 2.0 2.5 10 20 30 40 50 0 v ol (v) i ol (ma) 0.0 1.0 2.0 3.0 4.0 5.0 5 10152025 0 v cc -voh (v) -i oh (ma) ta=25?c fcyc=fosc/4 typ ta=25?c rf=20k typ ta=25?c typ ta=25?c typ ta=25?c typ ta=25?c rf=20k fcyc=fosc/4 typ v cc =5v v cc =3.5v v cc =4.5v v cc =5v v cc =5.5v v cc =4.5v v cc =5v v cc =5.5v v cc =2v (a) i cc vs. v cc characteristic (ceramic oscillation, crystal oscillation) (b) i cc vs. v cc characteristic (resistance oscillation) (c) f osc vs. v cc characteristic (resistance oscillation) (d) f osc vs. rf characteristic (resistance oscillation) (e) v ol vs. i ol characteristic (pins d4 to d7) (f) v cc - v oh vs. i oh characteristic (pins d0 to d3) figure 84 hd404374, hd404384, and hd404389 series characteristic curves (reference values)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 147 of 161 0.0 0.5 1.0 1.5 2.0 2.5 2 1 3456 0.0 0.5 1.0 1.5 2.0 2.5 2 1 3456 1.0 1.5 2.0 2.5 2 1 3456 0.0 1.0 2.0 3.0 4.0 5.0 10 0 20304050 0.0 0.5 1.0 1.5 2.0 2.5 0.0 1.0 2.0 3.0 4.0 5.0 10 0 20304050 5 0 10152025 fosc=8mhz fosc=4mhz fosc=2mhz fosc=800khz fosc=400khz ta=25c fcyc=fosc/4 typ i cc (ma) v cc (v) i cc (ma) v cc (v) (a) i cc vs. v cc characteristic (ceramic oscillation, crystal oscillation) ta=25c rf=20k ? fcyc=fosc/4 typ (b) i cc vs. v cc characteristic (resistance oscillation) fosc (mhz) rf (k?) ta=25c typ v cc =5v v cc =3.5v v cc =2v (d) f osc vs. rf characteristic (resistance oscillation) fosc (mhz) v cc (v) ta=25c rf=20k ? typ (c) f osc vs. v cc characteristic (resistance oscillation) v cc -voh (v) -i oh (ma) ta=25c typ v cc =4.5v v cc =5v v cc =5.5v (f) v cc - v oh vs. i oh characteristic (pins d0 to d3) v ol (v) i ol (ma) ta=25c typ v cc =4.5v v cc =5v v cc =5.5v (e) v ol vs. i ol characteristic (pins d4 to d7) figure 85 hd404082 and hd404084 series characteristic curves (reference values)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 148 of 161 package dimensions package code jedec eiaj weight (reference value) fp-30d unit: mm *dimension including the plating thickness base material dimension 0.10 m 0.10 0.10 2.00 max *0.32 0.08 0.65 15 30 11.0 11.2 max 8.0 *0.17 0.05 0.5 0.1 10.0 0.2 0? 8? 16 1.05 max 1 0.10 1.0 0.30 0.06 0.15 0.04
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 149 of 161 package code jedec eiaj weight (reference value) dp-28s conforms 1.9 g unit: mm 10.16 0.51 min 2.54 min 5.10 max 0.25 0? 15? + 0.11 0.05 0.48 0.10 1.78 0.25 27.1 27.9 max 1.0 8.8 10.8 max 28 15 11 4 2.41 max 9.0 0.2 7 * 0.22 0.05 0.08 36 25 112 37 48 24 13 0.5 9.0 0.2 0.08 1.0 0? 8? 0.5 0.1 * 0.17 0.05 1.70 max 0.10 0.07 m 0.75 package code jedec eiaj weight (reference value) fp-48b 0.2 g 0.20 0.04 1.40 0.15 0.04 unit: mm *dimension including the plating thickness base material dimension
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 150 of 161 note on rom ordering please note the following when ordering hd404372, hd40a4372, hd40c4372, hd404382, hd40a4382 and hd40c4382 rom. when ordering rom, please fill the "not used" areas below with all-1 data, to give the same amount of data as for the 4-kwords version (hd404374, hd40a4374, hd40c4372, hd404384, hd40a4384, hd40c4384). the program that converts rom data to mask drawing data is the same as that used for the 4-kwords version, and therefore the same amount of data is necessary. this applies both to orders using eprom and orders using data transmission. vector addresses program and pattern area (2,048 words) zero page subroutine area (64 words) not used* 2-kword rom version: hd404372, hd40a4372, hd40c4372, hd404382, hd40a4382, hd40c4382 write all-1 data to addresses $0800 to $0fff. $0000 $000f $0010 $003f $0040 $07ff $0800 $0fff note: * write all-1 data in not used area.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 151 of 161 please note the following when ordering hd404388, hd40a4388 and hd40c4388 rom. when ordering rom, please fill the "not used" areas below with all-1 data, to give the same amount of data as for the 16-kwords version (hd404389, hd40a4389, hd40c4389). the program that converts rom data to mask drawing data is the same as that used for the 16-kwords version, and therefore the same amount of data is necessary. this applies both to orders using eprom and orders using data transmission. vector addresses program and pattern area (8,192 words) zero page subroutine area (64 words) not used* 8-kword rom version: hd404388, hd40a4388, hd40c4388 write all-1 data to addresses $2000 to $3fff. $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff note: * write all-1 data in not used area.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 152 of 161 please note the following when ordering hd404081, hd40a4081 and hd40c4081 rom. when ordering rom, please fill the "not used" areas below with all-1 data, to give the same amount of data as for the 2-kwords version (hd404082, hd40a4082, hd40c4082). the program that converts rom data to mask drawing data is the same as that used for the 2-kwords version, and therefore the same amount of data is necessary. this applies both to orders using eprom and orders using data transmission. vector addresses program and pattern area (1,024 words) zero page subroutine area (64 words) not used* 1-kword rom version: hd404081, hd40a081, hd40c4081 write all-1 data to addresses $0400 to $07ff. $0000 $000f $0010 $003f $0040 $03ff $0400 $07ff note: * write all-1 data in not used area.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 153 of 161 option list hd404372, hd404374, hd40a4372, hd40a4374, hd40c4372, hd40c4374 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (renesas technology entry) 1. rom size ? standard operation version: hd404372 ? high-speed operation version: hd40a4372 ? cr oscillation version: hd40c4372 2 kwords ? standard operation version: hd404374 ? high-speed operation version: hd40a4374 ? cr oscillation version: hd40c4374 4 kwords 2. function options * ? 32 khz cpu operation, realtime clock time base * ? no 32 khz cpu operation, realtime clock time base ? no 32 khz cpu operation, no realtime clock time base note: * when an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (x1 x2). 3. rom code data organization for a microcomputer with eprom mounted (including a ztat ? microcomputer), specify the combined upper/lower type. ? combined lower/upper type both the lower 5 data bits (l) and the upper 5 data bits (u) are written to a single eprom in the order lululu... ? separate lower/upper type the lower 5 data bits (l) and upper 5 data bits (u) are written to separate eproms respectively.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 154 of 161 4. system oscillator (osc1-osc2) (shading means selection is not available) hd404372/4, hd40a4372/4 hd40c4372/4 ? ceramic oscillator f = mhz ? crystal oscillator f = mhz ? external clock f = mhz ? resistance oscillator 5. subsystem oscillator (x1 x2) ? not used ? ? crystal resonator f = 32.768 khz 6. stop mode ? yes (used) ? no (not used) 7. package ? fp-30d ? fp-48b * note: * the ws version will become available at the beginning of mass production.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 155 of 161 option list hd404382, hd404384, hd40a4382, hd40a4384, hd40c4382, hd40c4384 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (renesas technology entry) 1. rom size ? standard operation version: hd404382 ? high-speed operation version: hd40a4382 ? cr oscillation version: hd40c4382 2 kwords ? standard operation version: hd404384 ? high-speed operation version: hd40a4384 ? cr oscillation version: hd40c4384 4 kwords 2. rom code data organization for a microcomputer with eprom mounted (including a ztat ? microcomputer), specify the combined upper/lower type. ? combined lower/upper type both the lower 5 data bits (l) and the upper 5 data bits (u) are written to a single eprom in the order lululu... ? separate lower/upper type the lower 5 data bits (l) and upper 5 data bits (u) are written to separate eproms respectively. 3. system oscillator (osc1-osc2) (shading means selection is not available) hd404382/4, hd40a4382/4 hd40c4382/4 ? crystal oscillator f = mhz ? ceramic oscillator f = mhz ? external clock f = mhz ? resistance oscillator f = mhz
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 156 of 161 4. stop mode 5. package ? yes (used) ? fp-30d ? no (not used) ? dp-28s ? fp-48b * note: * the ws version will become available at the beginning of mass production.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 157 of 161 option list hd404388, hd404389, hd40a4388, hd40a4389, hd40c4388, hd40c4389 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (renesas technology entry) 1. rom size ? standard operation version: hd404388 ? high-speed operation version: hd40a4388 ? cr oscillation version: hd40c4388 8 kwords ? standard operation version: hd404389 ? high-speed operation version: hd40a4389 ? cr oscillation version: hd40c4389 16 kwords 2. rom code data organization for a microcomputer with eprom mounted (including a ztat ? microcomputer), specify the combined upper/lower type. ? combined lower/upper type both the lower 5 data bits (l) and the upper 5 data bits (u) are written to a single eprom in the order lululu... ? separate lower/upper type the lower 5 data bits (l) and upper 5 data bits (u) are written to separate eproms respectively. 3. system oscillator (osc1-osc2) (shading means selection is not available) hd404388/9, hd40a4388/9 hd40c4388/9 ? crystal oscillator f = mhz ? ceramic oscillator f = mhz ? external clock f = mhz ? resistance oscillator f = mhz
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 158 of 161 4. stop mode 5. package ? yes (used) ? fp-30d ? no (not used)
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 159 of 161 option list hd404081, hd404082, hcd404082, hd40a4081, hd40a4082, hd40c4081, hd40c4082, hcd40c4082 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (renesas technology entry) 1. rom size ? standard operation version: hd404081 ? high-speed operation version: hd40a4081 ? cr oscillation version: hd40c4081 1 kwords ? standard operation version: hd404082 ? standard operation version: hcd404082 ? high-speed operation version: hd40a4082 ? cr oscillation version: hd40c4082 ? cr oscillation version: hcd40c4082 2 kwords 2. system oscillator (osc1-osc2) (shading means selection is not available) hd404081/2, hd40a4081/2, hcd404082 hd40c4081/2, hcd40c4082 ? crystal oscillator f = mhz ? ceramic oscillator f = mhz ? external clock f = mhz ? resistance oscillator f = mhz 3. stop mode 4. package ? yes (used) ? fp-30d ? no (not used) ? dp-28s ? chip note: the specifications of shipped chips differ from those of the package product. please contact our sales staff for details.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 160 of 161 option list hd404084, hcd404084, hd40a4084, hd40c4084, hcd40c4084 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (renesas technology entry) 1. rom size ? standard operation version: hd404084 ? standard operation version: hcd404084 ? high-speed operation version: hd40a4084 ? cr oscillation version: hd40c4084 ? cr oscillation version: hcd40c4084 4 kwords 2. system oscillator (osc1-osc2) (shading means selection is not available) hd404084, hd40a4084, hcd404084 hd40c4084, hcd40c4084 ? crystal oscillator f = mhz ? ceramic oscillator f = mhz ? external clock f = mhz ? resistance oscillator 3. stop mode 4. package ? yes (used) ? fp-30d ? no (not used) ? dp-28s ? chip note: the specifications of shipped chips differ from those of the package product. please contact our sales staff for details.
hd404374/hd404384/hd404389/hd404082/hd404084 series rev.5.00, sep.11.2003, page 161 of 161 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. colophon 0.0

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