(preliminary) pl611s-15 1.8v-3.3v picopll tm 32k programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 07/18/06 page 1 features ? advanced programmable pll design for low- frequency (khz) input applications. ? otp selectable ac/dc ref. coupling. ? accepts <1.0v reference signal input voltage ? very low jitter and phase noise (30-70ps pk-pk typical) ? output frequency up to o 133mhz @ 1.8v operation o 166mhz @ 2.5v operation o 200mhz @ 3.3v operation ? offered in tiny green /rohs compliant packages o 6-pin dfn (2.0mmx1.3mmx0.6mm) o 6-pin sc70 (2.3mmx2.25mmx1.0mm) o 6-pin sot23 (3.0mmx3.0mmx1.35mm) ? input frequency: 10khz ? 200mhz ? single 1.8v, 2.5v, or 3.3v 10% power supply ? operating temperature range from 0 c to 70 c description the pl611s-15 is a low-cost general purpose frequency synthesizer and a member of phaselink?s picopll tm factory programmable ?quick turn clock (qtc)? family. designed to fit in a small sot23, sc70, or dfn package for high performance applications, the pl611s-15 accepts low frequency (>10khz) reference input and generates up to 200mhz output with the best phase noise, jitter performance, and power consumption for handheld devices and notebook applications. cascading pl611s-15 with other picopll ics could result in producing all required system clocks with specific savings in board space, power consumption, and cost. package pin assignment block diagram charge pump vco fin programmable function phase detector r-counter (7-bit) m-counter (16-bit) p-counter (4-bit) f vco = f ref * (2* m/r) clk0 f out = f vco /2*p 1 2 34 5 6 vdd gnda fin gnd lf clk0 dfn-6l (2.0mmx1.3mmx0.6mm) sot23-6l (3.0mmx3.0mmx1.35mm) 1 2 34 5 6 fin gnda vdd gnd sc70-6l (2.3mmx2.25mmx1.0mm) lf clk0 fin vdd lf gnd clk0 gnda pl611s-15 pl611s-15 1 2 3 6 5 4 pl611s-15
(preliminary) pl611s-15 1.8v-3.3v picopll tm 32k programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 07/18/06 page 2 package pin as signment pin # name sot sc70 dfn type description vdd 1 3 3 p vdd connection. gnda 2 2 2 p ground connection for analog circuitry. fin 3 1 1 i reference input pin. lf 4 6 6 i loop filter input pin. gnd 5 5 5 p gnd connection clk0 6 4 4 o programmable clock output guidelines for external component selection for the optimum performance, accurate external loop filter components must be selected. a general guideline for selecting these components based on the input frequency is shown in the below table. please contact phaselink for more accurate component selections. input frequency capacitor value resistor value 3mhz ~ 200mhz 4.7nf 2.2k ? 300khz ~ 10mhz 4.7nf 6.8k ? 30khz ~ 1.0mhz 4.7nf 22k ? 10khz ~ 100khz 47nf 22k ? application recommendations for pl611s-15 pl611s-15 can accept a reference input >10khz and produ ce a clock output in the mhz range, as shown in the diagram ?1?, below. however, to sav e costs in consumer product system designs and for greater area optimization, it is possible to use the xout of the rtc crystal (32. 768khz) as the reference input to the pl611s-15, as shown in diagram ?2?, below. diagram ?1? diagram ?2? note: an ac coupling cap may be required if rtc clock amplitude is too small. 32.768k hz c1 c2 refin mhz clk (any frequency) 1.8~3.3v lf lpgnd p l 6 1 1 s - 1 5 asic xin xout xin xout refin mhz clk ( a ny frequenc y 1.8~3.3v lf lpgnd p l 6 1 1 s - 1 5
(preliminary) pl611s-15 1.8v-3.3v picopll tm 32k programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 07/18/06 page 3 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 4.6 v input voltage range v i - 0.5 v dd + 0.5 v output voltage range v o - 0.5 v dd + 0.5 v data retention @ 85 c 10 year storage temperature t s -65 150 c ambient operating temperature -40 85 c exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the device at th ese or any other conditions above the operational limits noted in this specification is not implied. ac specifications parameters conditions min. typ. max. units input frequency (fin) reference clock input 10khz 200 mhz output frequency @ vdd=3.3v 2.5 200 mhz output frequency @ vdd=2.5v 2.5 166 mhz output frequency @ vdd=1.8v 2.5 133 mhz settling time at power-up (after vdd increases over 1.62v) 2 ms input (fin) signal amplitude internally ac coupled 0.9 vdd vpp output rise time 15pf load, 10/90%vdd, high drive, 3.3v 1 1.2 ns output fall time 15pf load, 90/10%vdd, high drive, 3.3v 1 1.2 ns duty cycle vdd/2 45 50 55 % * note: jitter performance depends on the programming parameters.
(preliminary) pl611s-15 1.8v-3.3v picopll tm 32k programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 07/18/06 page 4 dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic, with loaded cmos outputs i dd @vdd=3.3v,30mhz, load=15pf 6.0 ma supply current, dynamic, with loaded cmos outputs i dd @vdd=2.5v,30mhz, load=15pf 3.9 ma supply current, dynamic with loaded cmos outputs i dd @vdd=1.8v,30mhz, load=5pf 2.1* ma operating voltage v dd 1.62 3.3 3.63 v output low voltage v ol i ol = +4ma standard drive 0.4 v output high voltage v oh i oh = -4ma standard drive v dd ? 0.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v 16 ma short-circuit current i s 50 ma * note: please see pl611s-16 datasheet if lower power is required. pcb layout considerations fo r performance optimization the following guidelines are to assist you with a performance optimized pcb design: - keep all the pcb traces to pl611s-15 as short as possible, as well as keeping all other traces as far away from it as possible. - when a reference input clock is generated from a crystal (see diagram above), place the pl611s-15 ?fin? as close as possible to the ?xout? crystal pin. this will reduce the cross- talk between the reference input and the other signals. - place the loop filter (lf) components as close to the package pin of pl611s-15 as possible. - place a 0.01f~0.1f decoupling capacitor between vdd and gnd, on the component side of the pcb, close to the vdd pin. it is not recommended to place this component on the backside of the pcb. going through vias will reduce the signal integrity, causing additional jitter and phase noise. - it is highly recommended to keep the vdd and gnd traces as short as possible. - when connecting long traces (> 1 inch) to a cmos output, it is important to design the traces as a transmission line or ?stripline?, to avoid reflections or ringing. in this case, the cmos output needs to be matched to the trace impedance. usually ?striplines? are designed for 50 ? impedance and cmos outputs usually have lower than 50 ? impedance so matching can be achieved by adding a resistor in series with the cmos output pin to the ?stripline? trace. - please contact phaselink for the application note on how to design outputs driving long traces or the gerber files for the pl611s-15 layout.
(preliminary) pl611s-15 1.8v-3.3v picopll tm 32k programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 07/18/06 page 5 d e pin1 dot d1 b e e1 l a3 a a1 pin 6 id chamfer package drawings (green package co mpliant) sot23-6 l sc70-6l dfn-6l dimension in mm symbol min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1.70 h 2.60 3.0 l 0.35 0.55 e 0.95 bsc dimension in mm symbol min. max. a 0.80 1.00 a1 0.00 0.09 a2 0.80 0.91 b 0.15 0.30 c 0.08 0.25 d 1.85 2.25 e 1.15 1.35 h 2.00 2.30 l 0.21 0.41 e 0.65bsc dimension in mm symbol min. max. a 0.50 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 c l a2 e h d a1 e b a pin1 dot c l a2 e h d a1 e b a pin1 dot
(preliminary) pl611s-15 1.8v-3.3v picopll tm 32k programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 07/18/06 page 6 ordering information ( green package compliant) for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: device number, package type an d operating temperature range pl611s-xxx x x x part number order number marking ? package option pl611s-xxx pl611s-15-xxxgc-r 15xxx 6-pin sc70 (tape and reel) pl611s-xxx pl611s-15-xxxuc-r 15xxx 6-pin sc70 (tape and reel) pl611s-xxx pl611s-15-xxxtc-r 15xxx 6-pin sot-23 (tape and reel) ? note: ?xxx? designates marking identifier th at could be independent of the part number. phaselink corporation, reserves the right to make changes in its products or specifications, or bo th at any time without notice . the information furnished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning t he accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of phaselink corporation. part number temperature c=commercial i = industrial package type t=sot u=sc70 g=dfn 3 digit id code * (will be assigned at p ro g rammin g time ) none= tube r=tape and reel
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