View KL5KUSB201_7167210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 1/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. kl5kusb 201 usb2.0 compliant transceiver chip datasheet (digest) rev 1. 1e (2002.4.8) kawasaki microelectronics inc. kawasaki lsi inc.
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 2/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. intellectual property disclaimer and copyright notice ? kawasaki microelectronics inc. disclaims all liability, including liability for infringement of any propriety rights, relating to use of information in this document. ? this document is provided ?as is? with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. ? kawasaki microelectronics inc. reserves the right to make any changes, at any time, without notice, the description in this document. ? neither the whole nor any part of the information contained in, or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of kawasaki micro ? kawasaki products are not intended for use in medical, life saving, or life sustaining applications. ? all product names are trademarks, registered trademarks, or service marks of their respective owners.
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 3/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. revision history revision date update 0.10j 2001.9.28 release first version 0.21j 2001.10.18 minor error correction 0.30e 2002.3.15 translation from japanese to english with some minor change 1.0e 2002.3.25 document review is closed. 1.1e 2002.4.8 table 5-3 pin78, 79 error corrected.
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 4/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. table of contents 1. overview 5 1.1 chip functionality 5 1.2 KL5KUSB201 product feature 6 2. chip architecture 6 3. application example 8 4. pinout diagram 8 5. package information 9 5.1 top view 9 5.2 package size 10 5.3 pin assignment 10 6. signal description 11 7. sie bus timing 13 7.1 sie bus output timing 13 7.2 sie bus input timing 13 8. usb bus timing 14 8.1 bulk in transaction 14 8.2 bulk out transaction 15 9. usb2.0 lsi family 15 9.1 t&mt evaluation daughter card (uut) 15 9.2 pci evaluation add-in card 16 9.3 kl5budv002 lsi (u2pci) 17 9.4. usb201 and hs_sie asic ip 19 9.4.1 hs_sie asic ip 19 9.4.2 usb201 asic ip 20 10. references 21
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 5/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 1. overview kawasaki microelectronics inc. and kawasaki lsi inc. introduce KL5KUSB201 lsi, which is designed based on usb specification revision 2.0 and operates as both usb2.0 high speed and full speed transceiver chip. it has two modes ? utmi specification compatible mode and kawasaki original mode. in kawasaki original mode, the lsi has several convenient function such as automatic crc generation and verification, transmit packet abortion and automatic test packet generation for high speed signal quality test. the lsi is recognized as usb2.0 phy chip and customers are able to build up usb2.0 compliant device system with their logic and phy control / endpoint buffer function (sie), which is available by kawasaki or other ip vendor. figure 1. KL5KUSB201 image 1.1 chip functionality KL5KUSB201 fucntionality is summarized below. 1. hs chirp signal generation and detection 2. support for both high speed (480mbit/sec) and full speed (12mbit/sec) 3. for received packet, phase lock, buffering, sync detection, nrzi decode, bit un-stuffing, crc error detection (optional), serial to parallel conversion are performed. 16bit data is drived on sie bus 4.for packet transmission, parallel 16bit data is received, serialized, crc
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 6/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. generation (optional), bit stuffed and nrzi encoded. packet is transmitted onto usb bus with sync and eop attached 5. usb bus status is delivered for outside sie to monitor it 6. function is controlled by input signals 7. function defined by utmi specification is supported 8. stand-alone test packet generation for high speed signal quality 1.2 KL5KUSB201 product feature KL5KUSB201 product feature is shown below. table 1-2 KL5KUSB201 product feature no item feature 1 process 0.18um cmos 2 package lqfp 80 pin plastic package 3 input clock frequency 48mhz 4 internal clock frequency 480mhz 48mhz and other 5 output clock frequency (ckout) 30mhz 6 usb port 1 port (usb pin is separated for hs and fs) 7 parallel data width (sie_dat) 16bit 8 power voltage 3.3 0.3v 1.8 0.15v 9 operation current in fs typical 50ma 10 operation current in hs typical 90ma 11 operation current at suspend 1ua 12 ambient temperature 0 70c please contact to our sales and marketing person to request samples, datasheet, usb201 ip and / or hs_sie included ascp planning. 2. chip architecture internal architecture of KL5KUSB201 is shown in figure 2. the lsi consists of 6 major blocks as follows. frontend block transmits and receives usb signals. hs dll block is used to re-clock high speed signals with internal 480mhz clock. ebuf block is for buffering high speed signals. shared logic block includes such function as nrzi decode, bit un-stuffing, crc check, serial to parallel conversion for both high speed and full speed usb signals. sie_if block interfaces with sie bus signals. for full speed operation, dpll block is used to re-clock the full speed signals with
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 7/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. internal 12mhz clock instead of frontend, hsdll and ebuf blocks . for received signals, the lsi locks them in hs dll and is buffering them in ebuf . then signals are transferred to shared logic to convert data format, check the crc , convert from serial to parallel. the data is finally delivered to the sie bus through sie_if . for transmit operation, incoming parallel data is received in sie_if and sent to shared logic to perform parallel to serial conversion, crc generation, bit stuffing and nrzi encoding. finally the data is transmitted onto the usb bus through frontend block . high speed or full speed operation is selected by sie control signals. usb bus status can be monitored by usb bus status signals. figure 2 KL5KUSB201 internal architecture hs frontend fs frontend sie_if status clk gen sie_dat rpu_ena fsdp fsdm hsdp hsdm external 48mhz clock usb bus sie bus hs dll ebuf shared logic dpll ctrl ckout
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 8/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 3. application example example of system configuration using KL5KUSB201 is shown in figure 3. to realize the usb device application, other than the lsi, sie phy control and function logic are needed. also suitable resistors such as rpu, rs and rext and 48mhz clock oscillator or crystal and related parts are required. figure 3 application example usb201 udp rpu endpoint buffer usb201 controller udm rs osc 48mhz function function function function logic logic logic logic hs_sie rs rext 4. pinout diagram symbol block of KL5KUSB201 is shown in figure 4. the lsi has two interfaces ? usb bus and sie bus. usb related bus signals are shown in the left side of the symbol block, while sie bus signal is in the right side. sie control signals select lsi operation mode. these signals are fs_hsn, pu_se0n, mode, crcact, suspn and rstn. usb bus status signals are bstat. crcerr and rxerr are receiving error indicators. sie_dat is bi-directional bus. signal direction and valid timing are controlled by rxact, rxvld, txact, txrdy and wdvld.
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 9/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. figure 4 KL5KUSB201 symbol block KL5KUSB201 usb bus sie bus xin hsdp hsdm xout fsdp rpu_ena ckout fs_hsn rxact rxvld txact txrdy sie_dat[15:0] wdvld bstat[1:0] rstn suspn mode[3:0] crcact crcerr rxerr pu_se0n fsdm rext 5. package information 5.1 top view KL5KUSB201 1 21 top view index 60 80 20 40 41 61
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 10/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 5.2 package size lqfp-80 package size is shown in table 5.2. table 5-2. lqfp-80 size information no item size unit 1 body size 12.0 mm 2 thickness max 1.70 mm 3 pin pitch 0.5 mm 5.3 pin assignment package pin number and signal name table is listed below. please note that power pins named vdd18 (pin no 39, 45, 56 and 62) are required to be supplied 1.8v, while other power pins named avdd and vdd should be supplied 3.3v. table 5-3. pin assignment pin no i/o signal name pin no i/o signal name pin no i/o signal name pin no i/o signal name 1 -- avdd 21 i rstn 41 i/o sie_dat[7] 61 -- gnd 2 -- gnd 22 i suspn 42 i/o sie_dat[8] 62 -- vdd18 3 -- avdd 23 o bstat[0] 43 i/o sie_dat[9] 63 in pu_se0n 4 -- gnd 24 o bstat[1] 44 -- gnd 64 in fs_hsn 5 o rext 25 i/o sie_dat[0] 45 -- vdd18 65 -- gnd 6 3s rpu_ena 26 -- vdd 46 -- gnd 66 in crcact 7 -- avdd 27 -- gnd 47 -- vdd 67 in txact 8 -- gnd 28 i/o sie_dat[1] 48 i/o sie_dat[10] 68 -- gnd 9 i/o fsdp 29 i/o sie_dat[2] 49 i/o sie_dat[11] 69 -- vdd 10 i/o hsdp 30 -- gnd 50 -- gnd 70 i/o wdvld 11 i/o hsdm 31 i/o sie_dat[3] 51 i/o sie_dat[12] 71 o txrdy 12 i/o fsdm 32 -- vdd 52 -- gnd 72 o rxerr 13 -- gnd 33 -- gnd 53 i/o sie_dat[13] 73 o crcerr 14 -- avdd 34 i/o sie_dat[4] 54 i/o sie_dat[14] 74 -- gnd 15 -- vdd 35 -- gnd 55 -- gnd 75 o rxvld 16 i mode[0] 36 -- vdd 56 -- vdd18 76 o rxact 17 i mode[1] 37 i/o sie_dat[5] 57 -- gnd 77 -- vdd 18 -- gnd 38 i/o sie_dat[6] 58 -- vdd 78 i xin 19 i mode[2] 39 -- vdd18 59 o ckout 79 o xout 20 i mode[3] 40 -- gnd 60 i/o sie_dat[15] 80 -- gnd
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 11/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 6. signal description table 6 describes signal function description and related name in utmi. table 6 signal description no signal name i/o description utmi name 1 rext o reference bias current pin. connect to gnd via external resistor rext. -- 2 hsdp i/o high speed dp pin. connect to usb bus d+. dp 3 hsdm i/o high speed dm pin. connect to usb bus d-. dm 4 rpu_ena o pull up resister source pin. connect to external resistor rpu, which is tied to usb bus d+. rpu_ena becomes 3-state in high speed operation. -- 5 fsdp i/o full speed dp pin. connect to usb bus d+ via termination resistor rs. (dp) 6 fsdm i/o full speed dm pin. connect to usb bus d- via termination resistor rs. (dm) 7 xin i 48mhz clock input pin. connect to crystal oscillator or crystal oscillation circuit. -- 8 xout o 48mhz clock output pin for crystal oscillation circuit. -- 9 fs_hsn i usb bus speed control pin. xcvrselect 10 pu_se0n i termination control pin. with fs_hsn and mode, lsi operation mode is selected. ter m s elect 11 ckout o sie bus clock pin. frequency is 30mhz. clk 12 rxact o usb packet received signal. rxactive 13 rxvld o sie bus out data valid signal. active h. rxvalid (rxvalidh) 14 crcerr o crc error detection signal. active when crc logic is enabled. -- 15 rxerr o receive error detection signal. rx error indicator except for crc error. rxerror 16 txact i usb bus data transmit control signal. sie bus switches from output to input when active. txvalid (txvalidh) 17 txrdy o sie input data ready signal. valid when txact is active. txready 18 crcact i crc detection logic enable signal. also used for data transmit abortion. -- 19 sie_dat[15:0] i/o 16bit parallel 3-state sie data bus. synchronized with ckout. data direction is input when txact assertion. default direction is output. data15-8, data7-0 20 wdvld i/o sie data width indication signal. if last sie data is a byte data, wdvld is asserted. validh 21 rstn i hardreset signal. active l. assertion required when power on and usb reset recognition. rst (assert h)
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 12/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 22 suspn i asynchronous suspend signal. active l. when asserted, the lsi internal circuit is set to be in stand-by mode. only bstat[1:0] is active for monitoring usb bus status. suspendm 23 bstat[1:0] o usb bus monitor signals. in normal operation, the signal is synchronized with ckout, while asynchronous during suspend. when utmi mode is selected, bstat is compatible with linestate. linestate [1:0] 24 mode[3:0] i operation mode selection. one of utmi mode, device test mode, normal operation mode and stand-alone usb2.0 signal quality test mode is selected. opmode [1:0]
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 13/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 7. sie bus timing 7.1 sie bus output timing timing diagram of usb data output to sie bus is shown in figure 7-1. sie bus direction is output in default. the lsi asserts rxact to notice output of data to the external sie logic. valid data is indicated by rxvld assertion. odd byte of received usb data is driven to the lower byte of sie bus. if sie output data is in odd byte length, the lsi negates wdvld at the final data valid phase to indicate that the last one is byte data. figure 7-1 sie bus output timing ckout (o) txact (i) txrdy (o) sie_dat[7:0] ( i o) wdvld ( i o) sie_dat[15:8] ( i o) rxact (o) rxvld (o) b1 b2 b3 b4 b5 7.2 sie bus input timing figure 7-2 shows the receive timing diagram of the lsi from sie bus. external sie circuit asserts txact to notice the lsi to get data on sie bus. when txrdy is asserted, valid data is latched by the lsi. if data from sie is odd byte length, sie negates wdvld at the final data stage like the case in sie bus output timing. please note that in figure 7-2, a case of even byte length data is depicted.
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 14/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. figure 7-2 sie bus input timing ckout (o) txact (i) txrdy (o) sie_dat[7:0] (i o ) wdvld (i o ) sie_dat[15:8] (i o ) rxact (o) rxvld (o) b3 b4 b5 b6 // // // // // b2 b1 // 8. usb bus timing 8.1 bulk in transaction figure 8-1 shows the data timing of a bulk in transaction from usb host. when the lsi receives in packet from the host pc, it asserts rxact and drives 3 bytes received data on sie bus. external sie logic receives the data, checks the information of address, endpoint and crc if necessary. if it finds the data valid, the sie returns the data packet to be transmitted. finally the lsi receives ack packet and finishes a bulk in transaction. figure 8-1 bulk in transaction 2' rxact (o) usb bus (io) se0 in se0 sie_dat[7:0] ( i o) sie_dat[15:8] ( i o) txact (i) sie_dat[7:0] (i o ) sie_dat[15:8] (i o ) ep ae in ec 2 dat 3 4 n-1 n .... .... d 3' 4' n' c16 se0 ep se0 ep ak .... sync aec sync sync ak
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 15/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 8.2 bulk out transaction figure 8-2 shows the data timing of a bulk out transaction from the host pc. when the lsi receives out packet from the usb host, the lsi asserts rxact and drives 3 bytes data received from the host. if the external sie logic recognizes the out packet is valid, it waits for the next data packet from usb host. if the sie logic receives the data packet correctly, it returns ack. figure 8-2 bulk out transaction 2' rxact (o) usb bus (io) se0 o aec sync sie_dat[7:0] ( i o) sie_dat[15:8] ( i o) txact (i) sie_dat[7:0] (i o ) sie_dat[15:8] (i o ) ep ae out ec 2 dat 3 4 n-1 n .... .... d 3' 4' n' c16 se0 ep se0 ep .... c1 c2 se0 ack ak sync sync 9. usb2.0 lsi family this section introduces kawasaki?s usb2.0 lsi family. 9.1 t&mt evaluation daughter card (uut) the daughter card which is designed based on transceiver and macrocell tester (t&mt) interface specification is available for evaluating the KL5KUSB201 chip. all necesary parts including the lsi, usb connector, resistors and crystal oscillator are attached. with using your t&mt compatible controller, the function of the lsi is able to be evaluated such as usb2.0 test mode function, data transfer in high speed or full speed mode and verification of functionality with the external utmi compatible sie.
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 16/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. figure 9-1 KL5KUSB201 t&mt daughter board 9.2 pci evaluation add-in card the usb2.0 to pci adapter card is developed for the purpose of evaluating the lsi as a usb device system using pc. the pci card includes the lsi, usb connector, all necessary parts and u2pci chip, which is described later. the pci card performs the control of the lsi, usb packet buffering, pci bus transfer operation with high throughput. evaluation software is available together with the board. figure 9-2 KL5KUSB201 pci evaluation add-in card
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 17/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 9.3 kl5budv002 lsi (u2pci) the kl5budv002 lsi is usb2.0 to pci adapter chip, which consists of hs_sie block, pci interface block and data buffer ram. with KL5KUSB201, chipset performs data transfer with high throughput between usb2.0 and pci bus. the chipset makes it easy to build up a usb2.0 device system. main feature of kl5budv002 lsi is as follows. 1. directly connected with KL5KUSB201 and realizes usb2.0 data transfer in both high speed and full speed 2. includes hs_sie function and support up to 4 endpoints endpoint 0 control transfer 64bytes buffer endpoint 1 bulk out 512bytes x2 buffers endpoint 2 bulk in 512bytes x2 buffers endpoint 5 interrupt in 8bytes buffer option 3. includes 33mhz, 32bit pci bus interface target single access for memory mapped register access master burst access with 2 dma master controllers for memory access 4. independent data buffers for data transmit and receive 5. usb configuration transfer is controlled by the external pci controller. figure 9-3-1 kl5budv002 symbol kl5budv002 sie bus pci bus idsel reqn clk intan ad[31:0] trdyn testo rstn gntn ckout fs_hsn rxact rxvld txact txrdy sie_dat[15:0] wdvld bstat[1:0] urstn suspn mode[3:0] crcact crcerr rxerr pu_se0n cben[3:0] framen irdyn misc bus pmode[2:0] testi[3:0] par devseln stopn vbdet usb
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 18/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. figure 9-3-2 kl5budv002 application example kl5k usb201 udp rpu dbuf hs_sie udm rs osc 48mhz udv002 rs pci 32b 33mhz 30mhz pci if sie16b rext figure 9-3-3 kl5budv002 package image
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 19/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 9.4 hs_sie and usb201 asic ip 9.4.1 hs_sie asic ip hs_sie ip is useful for kawasaki asic users to design their lsi, which connects to KL5KUSB201 or includes usb201 ip inside. together with KL5KUSB201 chip, the ip performs usb2.0 lower level protocol. the main features of hs_sie are shown below. 1. rtl design makes it easy to implement with various processes 2. compact design such as 20 k logic gates, 4x512 bytes and 1x64 bytes 1-p ram 3. performs hs chirp protocol and speed detection 4. processes the basic usb transaction such as token decode, miss-hit judgment, error detection and data toggle bit control 5. controls transaction flow 6. supports up to 6 endpoints in total ? control, 2 bulk in, 2 bulk out and interrupt. 7. ease-of-use internal bus interface such as 16bit bus register access or dma figure 9-4-1 hs_sie ip symbol hs_sie sie bus ihost bus ckout fs_hsn rxact rxvld wdvld pu_se0n sie_dat[15:0] rxerr crcerr txact txrdy crcact bstat[1:0] suspn urstn mode[3:0] hcsn hirq hwrn hrdy hdat[15:0] hreq sysck hrdn hadr[4:0] hack rxlbvld rxlast txlbvld txlast rstn txnul
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 20/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 9.4.2 usb201 asic ip usb201 macro function is also prepared as asic ip in kawasaki?s ks6000 0.18um cmos technology. together with synthesizable hs_sie, a single chip solution of usb device function can be realized. figure 9-4-2-1 usb device integration concept usb201 ip hs_sie ip usb bus ihost bus sie bus user logic user i/o asic usb201 & hs_sie core asic concept figure 9-4-2-2 usb201 ip included asic chip image usb201 ip hs_sie ip user logic i/o buffer
kawasaki usb device KL5KUSB201 datasheet (digest) rev 1.1e page 21/21 copyright ? 2002 kawasaki microelectronics inc. kawasaki lsi inc. all rights reserved. 10. references 10.1 usb2.0 specification latest usb specification, which describes both full speed and high speed operation. the specification is available from usb_if web site. following three specifications are piled up to one zip file. a. usb specification (april 27,2000) b. errata to the usb2.0 specification (december 7,2000) c. mini-b connector engineering change notice to the usb 2.0 specification ( http://www.usb.org/developers/docs.html ) 10.2 utmi specification this is the usb2.0 phy function macro specification proposed by intel corp. the interface between phy and sie is defined. it is downloadable from intel site. a. the usb 2.0 transceiver macrocell interface, version 1.05(utmi) specification ( http://developer.intel.com/technology/usb/spec.htm ) 10.3 t&mt interface specification this document is the macrocell test interface proposed by intel corp. to test phy efficiently, card dimensions, connector pin layout and interface signals are defined. it is also downloadable from intel web site. a. the usb 2.0 transceiver and macrocell tester (t&mt) interface specification ( http://developer.intel.com/technology/usb/spec.htm ) 10.4 high speed board design guide this document depicts the general guideline of high speed usb device board design. design tips of handling the high speed signals are available in this document. this document is downloadable from the intel web site, too. ( http://developer.intel.com/technology/usb/spec.htm ) 10.5 kawasaki?s datasheet more detailed documents are available by kawasaki. please contact our sales person. a. KL5KUSB201 datasheet b. kl5budv002 datasheet

▲Up To Search▲

Price & Availability of KL5KUSB201

	To Download KL5KUSB201 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .