k6t4008s1c family cmos sram revision 1.0 april 1999 1 document title 512kx8 bit low power and low voltage cmos static ram revision history revision no. 0.0 1.0 remark preliminary final history initial draft finalize draft data june 15, 1998 april 17, 1999 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the speci fications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices.
k6t4008s1c family cmos sram revision 1.0 april 1999 2 512k x 8 bit low power and low voltage cmos static ram general description the k6t4008s1c families are fabricated by samsung s advanced cmos process technology. the families support industrial operating temperature range and have various package type for user flexibility of system design. the fami- lies also support low data retention voltage for battery back- up operation with low data retention current. features process technology: tft organization: 512k 8 power supply voltage k6t4008s1c family: 2.3~2.7v low data retention voltage: 2v(min) three state output and ttl compatible package type: 32-tsop2-400f/r 32-tsop1-0820f, 32-tsop1-0813.4f pin description name function name function a 0 ~a 18 address inputs vcc power we write enable input vss ground cs chip select input i/o 1 ~i/o 8 data inputs/outputs oe output enable input product family 1. the paramerter is measured with 30pf test load. product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) k6t4008s1c-f industrial(-40~85 c) 2.3~2.7v 100*/120ns 15 m a 16ma 32-tsop2-f/r 32-tsop1-f 32-stsop1-f functional block diagram (forward) 32-tsop2 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-tsop2 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (reverse) a18 a17 a17 a18 samsung electronics co., ltd. reserves the right to change products and specifications without notice. a15 precharge circuit. memory array 1024 rows 512 8 columns i/o circuit column select clk gen. row select a2 a3 a8 a9 a10 a13 a11 a0 a1 a4 a5 a6 a7 a14 cs we i/o 1 data cont data cont oe i/o 8 a12 a16 a18 a11 a9 a8 a13 we a17 a15 vcc a18 a16 a14 a12 a7 a6 a5 a4 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 32-tsop1 32- s tsop1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a17 control logic (forward)
k6t4008s1c family cmos sram revision 1.0 april 1999 3 product list industrial temp products(-40~85 c) part name function k6t4008s1c-vf10 k6t4008s1c-vf12 k6t4008s1c-mf10 k6t4008s1c-mf12 K6T4008S1C-TF10 k6t4008s1c-tf12 k6t4008s1c-yf10 k6t4008s1c-yf12 32-tsop2-f, 100ns, 2.5v, ll 32-tsop2-f, 120ns, 2.5v, ll 32-tsop2-r, 100ns, 2.5v, ll 32-tsop2-r, 120ns, 2.5v, ll 32-tsop1-f, 100ns, 2.5v, ll 32-tsop1-f, 120ns, 2.5v, ll 32-stsop1-f, 100ns, 2.5v, ll 32-stsop1-f, 120ns, 2.5v, ll functional description 1. x means don t care (must be in low or high state) cs oe we i/o mode power h x 1) x 1) high-z deselected standby l h h high-z output disabled active l l h dout read active l x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to v cc +0.5 v - voltage on vcc supply relative to vss v cc -0.3 to 4.6 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a -40 to 85 c industrial product
k6t4008s1c family cmos sram revision 1.0 april 1999 4 recommended dc operating conditions 1) note: 1. t a =-40 to 85 c, otherwise specified 2. overshoot : v cc +1.0v in case of pulse width 20ns 3. undershoot : -1.0v in case of pulse width 20ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc k6t4008s1c family 2.3 2.5 2.7 v ground vss all family 0 0 0 v input high voltage v ih all family 2.0 - vcc+0.3 2) v input low voltage v il all family -0.3 3) - 0.6 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs =v il , v in =v il or v ih , read - - 1 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma cs 0.2v,v in 0.2v or v in 3 vcc-0.2v - - 3 ma i cc2 cycle time=min, 100% duty, i io =0ma, cs =v il , v in =v ih or v il - - 16 ma output low voltage v ol i ol =0.5ma - - 0.4 v output high voltage v oh i oh =-0.5ma 2.0 - - v standby current(ttl) i sb cs =v ih , other inputs = v il or v ih - - 0.3 ma standby current (cmos) i sb1 cs 3 vcc-0.2v, other inputs=0~vcc - - 15 m a
k6t4008s1c family cmos sram revision 1.0 april 1999 5 ac characteristics (v cc =2.3~2.7v, t a =-40 to 85 c) parameter list symbol speed bins units 100ns 120ns min max min max read read cycle time t rc 100 - 120 - ns address access time t aa - 100 - 120 ns chip select to output t co - 100 - 120 ns output enable to valid output t oe - 50 - 60 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 30 0 35 ns output disable to high-z output t ohz 0 30 0 35 ns output hold from address change t oh 15 - 15 - ns write write cycle time t wc 100 - 120 - ns chip select to end of write t cw 80 - 100 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 80 - 100 - ns write pulse width t wp 70 - 80 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 30 0 35 ns data to write time overlap t dw 40 - 50 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns c l 1) 1. including scope and jig capacitance ac operating conditions test conditions (test load and input/output reference) input pulse level : 0.4 to 2.2v input rising and falling time : 5ns input and output reference voltage : 1.1v output load(see right) : c l =100pf+1ttl c l =30pf 1) +1ttl 1. k6t4008s1c-10 family data retention characteristics item symbol test condition min typ max unit vcc for data retention v dr cs 3 vcc-0.2v 2.0 - 3.6 v data retention current i dr vcc=2.5v, cs 3 vcc-0.2v - 0.5 15 m a data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
k6t4008s1c family cmos sram revision 1.0 april 1999 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs address oe data ou t notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. t oh t aa t olz t lz t ohz t hz t rc t oe t co
k6t4008s1c family cmos sram revision 1.0 april 1999 7 timing waveform of write cycle(1) ( we controlled) address cs t cw(2) t wr(4) timing waveform of write cycle(2) ( cs controlled) address cs t wc t wr(4) t as(3) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z t wc t aw t as(3) t cw(2) t wp(1) t aw notes (write cycle) 1. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low : a write end at the earliest transition among cs going high and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. data retention wave form cs controlled v cc 2.3v 2.2v v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr
k6t4008s1c family cmos sram revision 1.0 april 1999 8 package dimensions units: millimeters(inches) 32 pin thin small outline package type i (0813.4f) 1.00 0.10 0.039 0.004 max 8.40 0.331 1 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 13.40 0.10 0.528 0.008 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 #32 #17 32 pin thin small outline package type i (0820f) #32 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16
k6t4008s1c family cmos sram revision 1.0 april 1999 9 32 pin thin small outline package type ii (400f) 0~8 #32 20.95 0.10 0.825 0.004 max 21.35 0.841 max 1.00 0.10 0.039 0.004 1.20 0.047 min 0.002 0.05 0.004 max 0.10 max #1 0.95 ( ) 0.037 1 0 . 1 6 0 . 4 0 0 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 11.76 0.20 0.463 0.008 #17 #16 0.50 ( ) 0.020 0.45~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 1.27 0.050 0.40 0.10 0.016 0.004 package dimensions units: millimeters(inches) 32 pin thin small outline package type ii (400r) 0~8 #32 #1 1 0 . 1 6 0 . 4 0 0 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 11.76 0.20 0.463 0.008 #17 #16 0.50 ( ) 0.020 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 20.95 0.10 0.825 0.004 max 21.35 0.841 max 1.00 0.10 0.039 0.004 1.20 0.047 min 0.002 0.05 0.004 max 0.10 max 0.95 ( ) 0.037 1.27 0.050 0.40 0.10 0.016 0.004
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