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features v auxp v in v in v in sync in enable sync out v main v auxs v 5ref uvsd enable ovsd v 5ref sync in sync out program oam oa out ouvdelay dlyset fadj i lim1 i lim2 ramp1 ramp2 v fb1 v fb2 v ss v dd v cc gate1 gate2 gate2b v in r1 r2 r3 r4 c3 cs5106 c4 d1 t1 d2 c5 r5 c7 q1 v auxs cny17-4 v auxp d3 c9 c10 r9 r10 r12 d4 t4 t3 r23 r22 r21 q6 q7 q3 q4 c12 t2 c11 q5 r19 r18 r17 c14 c13 tl431 r16 d5 r15 r14 c8 r24 r25 r8 q2 r11 r13 l1 d6 r20 c1 c2 r6 r26 r27 d8 r7 c6 d7 programmable fixed frequency programmable fet non- overlap enable lead 12v fixed auxiliary supply control under and overvoltage shutdown output undervoltage protection with timer master/slave clock syncing capability sync frequency range detection 80ns pwm propagation delay 20ma 5v reference output small 24 lead ssop package controlled hiccup mode package options cs5106 multi-feature, synchronous plus auxiliary pwm controller cs5106 description the cs5106 is a fixed frequency, current mode controller with one single nfet driver and one dual fet, synchronous driver. the syn- chronous driver allows for increased efficiency of the main iso- lated power stage and the single driver allows the designer to devel- op auxiliary supplies for controller power as well as secondary side house keeping. in addition, because the synchronous drivers have programmable fet non-over- lap, the cs5106 is an ideal con- troller for soft-switched converter topologies. the cs5106 is specifically designed for isolated topologies where speed, flexibility, reduced size and reduced component count are requirements. the controller con- tains the following features: undervoltage shutdown, overvoltage shutdown, programmable frequency, programmable synchronous non- overlap time, master/slave clocking with frequency range detection, enable, output undervoltage protection with timer, 20ma 5v output, 80ns pwm propagation delay, and controlled hiccup mode. the cs5106 has junction tempera- ture and supply ranges of -40 ? c to 125 ? c and 9v to 16v respectively and is available in the 24 lead ssop package. applications diagram 24 lead ssop 1 1 uvsd ovsd oam oaout v 5ref ouvdelay i lim1 ramp1 v fb1 v ss v cc gate1 enable program sync in sync out fadj dlyset i lim2 ramp2 v fb2 v dd gate2b gate2 rev. 6/24/99 48v to 3.3v forward converter with synchronous rectifiers cherry semiconductor corporation 2000 south county trail, east greenwich, ri 02818 tel: (401)885-3600 fax: (401)885-5786 email: info@cherry-semi.com web site: www.cherry-semi.com a company ?
cs5106 2 absolute maximum ratings lead symbol lead name v max v min i source i sink uvsd undervoltage shutdown input 6v -0.3v 1ma n/a ovsd overvoltage shutdown input 6v -0.3v 1ma n/a v 5ref 5v reference output 6v -0.3v 150ma 25ma oam error amp minus input 6v -0.3v 250a 1.2ma oaout error amp output 6v -0.3v 300a 100ma ouvdelay output overcurrent timer capacitor 6v -0.3v 15a n/a i lim1 auxiliary primary side current limit input 6v -0.3v 10a n/a ramp1 auxiliary primary side current ramp input 6v -0.3v 10a n/a v fb1 auxiliary voltage feedback input 6v -0.3v 5a 100a v ss bootstrapped power input 20v -0.3v 2a 0.5a peak 300ma dc v cc main power input 20v -0.3v see note 1 0.5a peak 300ma dc gate1 auxiliary fet driver output 20v -0.3v 0.5a peak 0.5peak 100ma dc 100ma dc gnd ground 0v 0v 0.5a peak n/a 300ma dc gate2 synchronous fet driver output 20v -0.3v 0.5a peak 0.5apeak 100ma dc 100ma dc gate2b synchronous fet driver output b 20v -0.3v 0.5a peak 0.5a peak 100ma dc 100ma dc v fb2 synchronous voltage feedback input 6v -0.3v 10a 100a ramp2 synchronous primary side current ramp input 6v -0.3v 10a n/a i lim2 synchronous primary side current limit input 6v -0.3v 10a n/a dlyset gate non-overlap programming input 2.5v -0.3v 125a n/a fadj frequency programming input 2.5v -0.3v 125a n/a sync out clock master output 6v -0.3v 50ma 100ma sync in clock slave input 6v -0.3v n/a 1ma program enable programming input 16v -0.3v 30a n/a enable enable input 16v -0.3v 300a n/a note 1: current out of v cc is not limited. care should be taken to prevent shorting v cc to ground. operating junction temperature, t j ............................................................................................................................... ...... 150c operating temperature range, t a ............................................................................................................................... -40 to 85c storage temperature range, t s ............................................................................................................................... ....-65 to 150c esd (human body model)......................................................................................................... ................................................2kv lead temperature soldering: reflow (smd styles only).............................................60 sec. max above 183c, 230c peak
cs5106 3 parameter test conditions min typ max unit electrical characteristics: t j = -40c to 125c, v ss = 9 to 16v, v 5ref i load = 2ma, sync out free running, unless other- wise specified. for all specs: uvsd=6v, ovsd = 0v, enable = 0v, i lim(1,2) = 0,v fb(1,2) = 3v,r fadj = r dlyset = 27.4k ? . v ss supply current measure current into v ss when 16.00 23.00 ma v 5ref i load =0ma. 9v v ss 13v. measure current into v ss when 16.00 25.00 ma v 5ref i load =0ma. 13v < v ss 16v. measure current into v ss when 16.00 30.00 ma v 5ref i load =0ma. 16v < v ss 20v. low v cc supply current float v ss . set v cc =7v & measure 1.50 3.50 ma v cc current while v 5ref i load =0ma. v ss to v cc diode diode on voltage measure v ss - v cc . 0.20 0.75 1.00 v reference 5v internal voltage reference measure v ref voltage when 4.85 5.00 5.15 v i ref =0 and i ref =20 ma. v ref ok threshold adjust v ref from 4.8v-4.0v until 4.30 4.55 4.70 v pwm1,2 goes low. low v cc lockout v cc turnon threshold voltage v cc increasing until i cc > 3.5ma 7.00 7.25 7.50 v v 5ref i load = 0ma v cc turnoff threshold voltage v cc decreasing until i cc < 3.5ma 6.30 6.70 7.10 v v 5ref i load = 0ma hysteresis turnon - turnoff 0.40 0.55 0.70 v clock operating frequency1 measure frequency from sync out . 485.0 512.0 540.0 khz sync in input impedance measure input impedance. 7.00 15.00 k ? sync out output low voltage r load = 2k ? to v 5ref 1.00 1.50 v sync out output high r load = 2k ? to gnd 3.50 4.20 v voltage sync in detect frequency verify sync out = sync in , 425.0 555.0 khz r load = 2k ? to gnd max. low sync rej. frequency verify sync out = fclk when 340.0 khz r load = 2k ? to gnd. min. high sync rej. frequency verify sync out = fclk when 690 khz r load = 2k ? to gnd. sync in input threshold functional testing 0.90 1.85 2.90 v voltage verify fclk from 1.0v to 2.8v. main pwm clock pulse (gbd) - clph1 width one shot pulse width 80.0 100.0 120.0 ns aux pwm clock pulse (gbd) -clph2 width one shot pulse width 80.0 100.0 120.0 ns bias supply error amplifier output low voltage v ss > 12.6v. measure oaout 43.0 85.0 mv voltage when sinking 1.0 ma. output high voltage v ss < 11.4v. measure oaout 4.55 4.75 v voltage when sourcing 150a. output high source current v ss < 11.4v. measure oaout source 150.0 225.0 300.0 a current when oaout = 0.5v.
cs5106 4 parameter test conditions min typ max unit electrical characteristics: t j = -40c to 125c, v ss = 9 to 16v, v 5ref i load = 2ma, sync out free running, unless other- wise specified. for all specs: uvsd=6v, ovsd = 0v, enable = 0v, i lim(1,2) = 0,v fb(1,2) = 3v,r fadj = r dlyset = 27.4k ? . bias supply error amplifier: continued output low sink current v ss > 12.6v. measure oaout sink 3.0 20.0 50.0 ma current when oaout = 2.5v. v ss set point adjust v ss until oaout goes low. 11.60 12.25 12.80 v large signal gain (gbd) 15.00 v/mv unity gain bandwidth (gbd) 1.00 mhz common mode input range (gbd) 1.00 2.00 v v ss voltage v ss reset voltage toggle enable between gnd & v cc , then adjust v ss from 2.0v-0.8v until oaout goes high. 1.00 1.40 1.80 v undervoltage lockout uvsd turn on adjust uvsd from 4.7v-5.3v 4.80 5.00 5.10 v threshold voltage until gate 1, 2 goes high. uvsd turn off threshold adjust uvsd from 5.1v-4.3v 4.45 4.70 4.95 v voltage until gate 1, 2 goes low. hysteresis turnon - turnoff 0.20 0.27 0.40 v uvsd input bias current set uvsd=0v. measure current 0.20 0.50 a out of uvsd lead. overvoltage lockout ovsd threshold voltage adjust ovsd from 4.7v-5.3v 4.85 5.00 5.15 v until gate 1, 2 goes low. ovsd input bias current set ovsd=0v. measure current out 0.20 0.50 a of ovsd lead. enable & program enable lead output current measure current out of 100.0 266.0 500.0 a enable when enable = 0v. program lead output measure current out of 20.0 60.0 100.0 a current program when program = 0v. program threshold enable = gnd. adjust 1.20 1.40 1.60 v voltage program from 1.0v - 1.8v until gate 1, 2 goes high. enable threshold voltage program = gnd. 1.20 1.40 1.60 v adjust enable from 1.0v - 1.8v until gate 1, 2 goes high. output undervoltage delay ouvdelay charging set ouvdelay = 1v, v fb1 = 4.4v 7.50 10.00 12.50 a current measure ouvdelay i charge . ouvdelay latchoff voltage toggle enable between gnd & v cc , 4.80 5.00 5.20 v then adjust ouvdelay from 4.7v - 5.3v until gate 1, 2, goes low. ouvdelay set current ouvdelay = voclo + 50mv 0.50 1.00 ma measure current into ouvdelay. v fb1 charge threshold v ss =1v. toggle enable between 4.05 4.22 4.40 v gnd & v cc , adjust v fb1 from 3.8v - 4.6v until gate 1, 2 goes low. v fb2 charge threshold v ss = 1v. toggle enable between 3.90 4.15 4.35 v gnd & v cc , adjust v fb2 from 3.8v - 4.6v until gate 1, 2 goes low.
parameter test conditions min typ max unit cs5106 5 electrical characteristics: t j = -40c to 125c, v ss = 9 to 16v, v 5ref i load = 2ma, sync out free running, unless other- wise specified. for all specs: uvsd=6v, ovsd = 0v, enable = 0v, i lim(1,2) = 0,v fb(1,2) = 3v,r fadj = r dlyset = 27.4k ? . current limit circuits i lim1 current limit threshold adjust i lim1 from 1.0v - 1.3v until 1.16 1.24 1.30 v voltage gate1 goes low. i lim1 short circuit threshold adjust i lim1 from 1.30v - 1.50v until 1.35 1.44 1.51 v voltage gate1 skips 2-cycles with reference to sync out. i lim1 input bias current set i lim1 =0v. measure current 0.50 5.00 a out of i lim1 lead. i lim2 current limit adjust i lim2 from 1.0v - 1.3v until 1.16 1.24 1.30 v threshold v gate2 goes low. i lim2 short circuit adjust i lim2 from 1.30v - 1.50v until 1.35 1.44 1.51 v threshold voltage gate2 skips 2-cycles with reference to sync out . i lim2 input bias current set i lim 2 = 0v. measure current out 0.50 5.00 a of i lim2 lead. voltage feedback control ramp1 offset voltage v fb1 =0v. adjust ramp1 from 0v - 0.3v 0.08 0.13 0.20 v until gate1 goes low. measure v ramp1 . ramp1 input bias current set ramp1 = 0v. measure current 0.50 5.00 a out of ramp1 lead. ramp2 offset voltage v fb2 = 0v. adjust ramp2 from 0.08 0.13 0.20 v 0v-3v until gate2 goes low. measure v ramp2 . ramp2 input bias current set ramp2 = 0v. measure current out of ramp2 lead. 0.50 5.00 a v fb1 input impedance measure input impedance. 60.0 120.0 220.0 k ? v fb2 input impedance measure input impedance. 60.0 120.0 220.0 k ? gate1,2,2b output voltages v ss = 12v. v cc = v ss - v don gate1 low state program = 0v. measure gate1 0.15 0.80 v voltage when sinking 1ma. gate2 low state program = 0v. measure gate2 0.18 0.80 v voltage when sinking 1ma. gate2b low state program = 0v. measure gate2b 0.18 0.80 v voltage when sinking 1ma. gate2b high state measure v cc - gate2b voltage 1.65 2.00 v when sourcing 1ma. gate2 high state measure v cc - gate2 voltage 1.65 2.00 v when sourcing 1ma. gate1 high state measure v cc - gate1 voltage 1.65 2.00 v when sourcing 1ma. propagation delays i lim1 delay to output gate1 measure delay from i lim1 going 80.0 120.0 ns high to gate1 going low. i lim2 delay to output gate2 measure delay from i lim2 going 80.0 100.0 ns high to gate2 going low. ramp1 delay to output gate1 measure delay from ramp1 going 80.0 115.0 ns high to gate1 going low. ramp2 delay to output gate2 measure delay from ramp2 going 80.0 100.0 ns high to gate2 going low.
package lead description cs5106 6 parameter test conditions min typ max unit electrical characteristics: t j = -40c to 125c, v ss = 9 to 16v, v 5ref i load = 2ma, sync out free running, unless other- wise specified. for all specs: uvsd=6v, ovsd = 0v, enable = 0v, i lim(1,2) = 0,v fb(1,2) = 3v,r fadj = r dlyset = 27.4k ? . package lead # lead symbol function gate 2, 2b non-overlap delay gate2 turn-on delay measure delay from gate2b going low 20.0 45.0 70.0 ns from gate2b @1.7v to gate2 going high @1.7v. gate2b turn-on delay measure delay from gate2 going low 20.0 45.0 70.0 ns from gate2 @1.7v to gate2b going high @1.7v. gate 1, 2, 2b rise & fall times v ss =12v,v cc =v ss -v don gate1 rise time measure gate1 rise time from 50.0 80.0 ns 90% to 10%. c load = 150pf. gate1 fall time measure gate1 fall time from 10% to 90%. c load = 150pf. 30.0 60.0 ns gate2 rise time measure gate2 rise time from 90% to10%. c load = 50pf. 50.0 80.0 ns gate2 fall time measure gate2 fall time from 10% to 90%. c load = 50pf. 15.0 30.0 ns gate2b rise time measure gate2b rise time from 90% to10%. c load = 50pf. 50.0 80.0 ns gate2b fall time measure gate2b fall time from 10% to 90%. c load = 50pf. 15.0 30.0 ns 1 uvsd undervoltage shutdown lead. typically this lead is connected through a resistor divider to the main high voltage (v in ) line. if the voltage on this lead is less than 5v then a fault is initiated such that gate1, gate2 and gate2b go low. 2 ovsd overvoltage shutdown lead. typically this lead is connected through a resistor divider to the main high voltage (v in ) line. if the voltage on this lead exceeds 5v then a fault is initiated such that gate1, gate2 and gate2b go low. 3v 5ref 5v reference output lead. capable of 20ma nominal output. if this lead falls to 4.5v, a fault is initiated such that gate1, gate2 and gate2b go low. 4 oam auxiliary error amplifier minus input. this lead is compared to 1.2v nominal on the auxiliary error amp plus lead and represents the v ss voltage divided by ten. 5 oaout auxiliary error amplifier output lead. source current 300a max. 6 ouvdelay output undervoltage timing capacitor lead. if the controlled output voltages of either the main or the auxiliary supply are such that either v fb1 or v fb2 is greater that 4.1v nominal, then capacitor from ouvdelay to ground will begin charging. if the over voltage duration is such that the ouvdelay voltage exceeds 5v, then a fault will be initiated such that gate1, gate2 and gate2b will go low. 7i lim1 pulse by pulse over current protection lead for the auxiliary pwm. a voltage exceeding 1.2v nominal on i lim1 will cause gate1 to go low. a voltage exceeding 1.4v nominal on i lim1 will cause gate1 to go low for at least two clock cycles. 8 ramp1 current ramp input lead for the auxiliary pwm. a voltage which is linear with respect to current in the primary side of the auxiliary trans former is usually represented on this lead. a voltage exceeding v fb1 - 0.13 on ramp1 will cause gate1 to go low.
cs5106 7 package lead # lead symbol function package lead description: continued 9v fb1 voltage feedback lead for the auxiliary pwm. a voltage which represents the auxiliary power supply output voltage is fed to this lead. a voltage less than ramp1+0.13 on v fb1 will cause gate1 to go low. 10 v ss v ss power/feedback input lead. see v cc for description of power operation. in addition, this lead is fed to a divide by ten resistor divider and compared to 1.2v nominal at the positive side of the error amplifier. 11 v cc v cc power input lead. this input runs off a zener referenced supply until v ss > v cc . then an internal diode which runs between v ss and v cc turns on and all main power is derived from v ss . 12 gate1 auxiliary pwm gate drive lead. this output normally drives the fet which drives the auxiliary transformer. 13 gnd ground lead. 14 gate2 synchronous pwm gate drive lead. this output normally drives the fet which drives the main transformer. 15 gate2b synchronous pwm gate drive lead. this output normally drives the fet for the gate drive transformer used for synchronous rectification. 16 v fb2 voltage feedback lead for the synchronous pwm. a voltage which represents the main power supply output voltage is fed to this lead. a voltage less than ramp2+0.13 on v fb2 will cause gate2 to go low and gate2b to go high. 17 ramp2 current ramp input lead for the synchronous pwm. a voltage which is linear with respect to current in the primary side of the main trans former is usually represented on this lead. a voltage exceeding v fb2 - 0.13 on ramp2 will cause gate2 to go low and gate2b to go high. 18 i lim2 pulse by pulse over current protection lead for the synchronous pwm. a volt- age exceeding 1.2v nominal on i lim2 will cause gate2 to go low and gate2b to go high. a voltage exceeding 1.4v nominal on i lim2 will cause gate2 to go low and gate2b to go high for at least two clock cycles. 19 dlyset gate2, gate2b non-overlap time adjustment lead. a 27k ? resistor from dlyset to ground sets the non-overlap time to 45ns nominal. 20 fadj frequency adjustment lead. a 27k ? resistor from fadj to ground sets the clock frequency to 512khz nominal. 21 sync out clock output lead. this is a 50% duty cycle, 1v to 5v pulse whose rising edge is in phase with gate1. this signal can be used to synchronize other power supplies. 22 sync in clock synchronization lead. the internal clock frequency can be adjusted +10%, -15% by the onset of positive edges of an external clock occurring on the sync in lead. if the external clock frequency is out side the internal clock fre- quency by +25%, -35% the external clock is ignored and the internal clock free runs. 23 program enable programming input. see enable for programming states. pro- gram has at least 20a min. of available source current. 24 enable pwm enable input. if program is high then a low on enable will allow gate1, gate2 and gate2b to switch. if program is low then a high on enable will allow gate1, gate2 and gate2b to switch. if enable is left floating, it will pull up to a high level. enable has at least 100a (min) of available source current.
cs5106 8 block diagram + - + - + - + - + - + - + - v v v v v v v v v v v v v ouvdelay oaout oam v ss aux. error amp a1 1.2v + 5k 45k v cc d1 output undervoltage timer v 5ref 100k p1 run1 run 2 g6 + - c9 v ref ok v fb1 sync in program enable uvsd sync out dylset fadj ramp2 gate2 gate2b i lim2 v fb2 a2 a2 g1 v refok run 1 v ss g7 g3 c1 g8 freq too low aux.pwm comparator v refok comparator main pwm comparator sync detection main 2nd current threshold comparator aux. 2nd current threshold comparator aux. current limit comparator main current limit comparator c11 1.2v v skip two clock pulses set clock set clock skip two clock pulses g15 c17 c16 skip2b g14 g18 1.4v gate1 gnd i lim1 rsff qr f2 s t period driver + - c10 c12 + - c13 osc ifset clk1 clk2 idset sync in sync out + - c8 + - c5 ovsd + - + - g13 c14 g16 g17 c15 delay delay g12 run2 run2 1.7v + driver reset dominant g11 g10 g9 vref enable v ref = 5v v cc 5v + - c2 rsff rq s f1 set dominant + - over voltage comparator v ss restart comparator reset dominant rsff q f3 s r reset dominant rsff q f4 s r + - c4 - + c7 skip2b enable comparator under voltage comparator r 2r g5 g4 driver tff t1 q + 0.13v 0.13v + start stop r 2r run1 + 1.5v fault latch c3 + - + - freq too high 1.4v 5v 4.5 7.4/6.8v 1.4v ramp1 1.4v q theory of application powering the ic the ic has one supply, v cc , and one ground lead. if v ss is used for a bootstrapped supply the diode between v ss and v cc is forward biased, and the ic will derive its power from v ss . the internal logic monitors the supply voltage, v cc . during abnormal operating conditions, all gate drivers are held in a low state. the cs5106 requires 1.5ma nominal of startup current. startup assume the part is enabled and there are no over voltage or under voltage faults present. also, assume that all auxil- iary and main regulated output voltages start at 0v. an 8v, zener referenced supply is typically applied to v cc . when v cc exceeds 7.5v, the 5v reference is enabled and the osc begins switching. if the v 5ref lead is not exces- sively loaded such that v 5ref < 4.5v nominal, ?v ref ok? goes ?high? and ?run1? will go ?high?, releasing gate1 from its low state. after gate1 is released, it begins switching according to conditions set by the auxiliary con- trol loop and the auxiliary supply, v ss begins to rise. when v ss > v cc + v(d1), p1 turns on and ?run2? goes ?high?, releasing gate2 and gate2b from their low state. gate2 and gate2b begin switching according to condi- tions set by the main control loop and the main regulated output begins to rise. see startup waveforms in figure 1. soft start soft start for the auxiliary power supply is accomplished by placing a capacitor between oaout and ground. the error amplifier has 200a of nominal of source current and is ideal for setting up a soft start condition for the auxiliary regulator. care should be taken to make sure that the soft start timing requirements are not in conflict with any tran- sient load requirements for the auxiliary supply as large capacitors on oaout will slow down the loop response. also, the soft start capacitor must be chosen such that dur- ing start or restart, both outputs will come into regulation before the ouvdelay timer trips. soft start for the main supply is accomplished by charging soft start capacitor c6 through d5 and r7 at start up. after the main supply has come into regulation c6 continues to charge and is discon- nected from the feedback loop by d8. theory of operation
cs5106 9 figure 1: startup waveforms. voltage and current ramp pwm comparator inputs (v fb1 , 2 and ramp1,2 leads) c10 and c11 are the pwm comparators for the auxiliary and main supplies. the feedback voltage (v fb ) is divided by three and compared with a linear, voltage representa- tion of the current in the primary side of the transformer (ramp). when the output of the feedback comparator goes ?high?, a reset signal is sent to the pwm flip-flop and the gate driver is driven ?low?. a 130mv offset on the ramp leads allows the drivers to go to 0% duty cycle in the presence of light loads. feedback voltage for gate1 driver (v fb1 ) typically the output of the auxiliary error amplifier (a1) is tied to v fb1 . the v ss output is programmed to 12v by a 10:1 resistive divider on the negative input of the error amplifier and a fixed 1.2v reference on the positive input of the error amplifier. pulse by pulse over current protection and hiccup mode (i lim1,2 leads) c12 and c13 are the pulse by pulse current limit compara- tors for the auxiliary and main supplies. when the current in the primary side of the transformer increases such that the voltage across the current sense resistor exceeds 1.2v nominal, the output of the current limit comparator goes ?high? and a reset signal is sent to the pwm flip-flop and the gate driver is driven ?low?. c16 and c17 are the second threshold, pulse by pulse cur- rent limit comparators for the auxiliary and main supplies. if the current in the primary side of the transformer increases so quickly that the current sense voltage is not limited by c12 or c13 and the voltage across the current sense resistor exceeds 1.4v, the second threshold compara- tor will trip a delay circuit and force the gate driver stage to go low and stay low for the next two clock cycles. undervoltage and overvoltage thresholds c5 and c8 are the undervoltage and overvoltage detection comparators. typically, these inputs are tied across the middle resistor in a three resistor divider with the top resistor to v in and bottom resistor to ground. the under voltage comparator has 200mv of built in hysteresis with respect to a direct input on the uvsd lead. the under volt- age comparator has its positive input referenced to 5v while the over voltage comparator has its negative input referenced to 5v. the output of both comparators are ored at (g4) with the over current and enable inputs. the output of g4 feeds the input to the fault latch (f2). program and enable leads the program lead controls the polarity of the enable lead. if the program lead is ?high? or floating, the gate outputs will go low if the enable input is tied ?high? or floating. if the program lead is tied low, the gate out- puts will go low if the enable input is tied ?low?. if the part is then enabled after switching the outputs low, the part will restart according to the procedure outlined in the ?startup? section. fault logic if a v ref , uvsd or ovsd fault occurs at any time, g4 resets the fault latch (f2). run1 goes low and all gate drivers cease switching and return to their ?low? state. when run1 goes low, the output of the auxiliary op-amp (a1) discharges the soft start capacitor and holds it low while run1 is low. if the fault condition is removed before the ouvdelay timer is tripped, the ic will restart the power supplies when v ss < 1.4v. if the ouvdelay timer trips, the power supply must be restarted as explained in the following section. output undervoltage delay timer for the main and auxiliary regulated outputs c7 and c4 are the output under voltage monitor compara- tors for the auxiliary and main supplies. if a regulated out- put drops such that its associated v fb voltage exceeds 4.1v, the output undervoltage monitor comparator goes ?high? and the ouvdelay capacitor begins charging from 0v. a timing relation is set up by a 10a nominal current source, the ouvdelay capacitor and a 5v fault threshold at the input of c2 (see figure 2). if any regulated output drops and stays low for the entire charge time of the ouvdelay capacitor, a fault is triggered and all gate drivers will go into a low state. once this fault is triggered, the ic will restart the power supplies only if the ouvdelay fault is reset and enable or uvsd is toggled while v ss < 1.4v. to reset the ouvde- lay fault, both the v fb inputs must be less than 4.1v. in the application circuit shown, v fb1 is brought low by oaout when run1 stops the oscillators. v fb2 is brought low when v auxp bleeds down and the v fb2 opto-isolator is no longer powered. figure 2: ouvdelay time vs. ouvdelay capacitance capacitance (nf) time (ms) 0.01 100 1 0.1 10 1 100 1000 0.1 10 1000 v ss > v cc 7.5v v cc v ref ,v ref(ok) ,run1 clk1 gate1 ramp1 v fb1 v ss v fb2 run2 clk2 gate2 ramp2 gate2b theory of application: continued
fadj and dlyset leads amplifier a2 and transistor n3 create a current source fol- lower whose output is fadj. an external resistor from fadj to ground completes the loop. the voltage across the resistor is set by a buffered, trimmed, precision reference. in this fashion, an accurate current is created which is used to charge and discharge an internal capacitor thereby creat- ing an oscillator with a tight frequency tolerance. for fadj resistor value selection, see figure 3. transistor n2 is in parallel with n3 and is used to created an independent cur- rent across the resistor from dlyset to ground. this cur- rent is used to program the gate non-overlap delay blocks in the main pwm drivers. for dlyset resistor value selection, see figure 4. figure 3: sync out frequency vs. fadj resistors figure 4: gate non-overlap time vs. dlyset resistance oscillator the oscillator generates two clock signals which are 180 degrees out of phase with respect to time. one clock signal feeds the main driver and the other feeds the auxiliary driver. because the drivers are never turned on at the same time, ground noise and supply noise is minimized. the clock signals are actually 100ns pulse spikes. these spikes create a narrow driver turn-on window. this narrow win- dow prevents the driver from spurious turn on in the mid- dle of a clock cycle. the oscillator can be synchronized by an external clock (slave) or drive the clocks of other con- trollers (master). see figure 5 for the relationship between sync, clk, and gate waveforms. figure 5: sync, gate and clock waveforms . sync in and sync out leads multiple supplies can be synchronized to one supply by using the sync leads. the sync in and sync out pulses are always 180 degrees out of phase. the sync in input is always in phase with the clock signal for the main driver and the sync out output is always in phase with the clock signal for the auxiliary driver. if the ic is being used as a slave, the incoming frequency must be within +10%, -20% of the programmed frequency set by its own fadj resistor. if the frequency on the sync in lead is outside the internal frequency by +25%, -35%, the sync in input will be ignored. if the sync signal stops while the power supplies are in synchronized operation, the synchronized supplies will stop and restart free running. if the sync in signal drifts out of frequency specification while the power sup- plies are in synchronized operation, the synchronized sup- plies will begin to free run without restarting. slope compensation dc-dc converters with current mode control require slope compensation to avoid instability at duty cycles greater than 50%. a slope is added to the current sense waveform (or subtracted from the voltage waveform) that is equal to a percentage (75% typical) of the down slope of the induc- tor current. in the application diagram shown, the boot- strap (flyback) transformer inductance can be chosen so that the duty cycle never exceeds 50% and therefore does not require slope compensation. the buck indicator in the forward converter would typically be chosen to work in continuous conduction mode with a maximum duty cycle of 50-60% and would require slope compensation. slope compensation is accomplished as follows: r9 and c9 form a ramp waveform rising each time gate 2 turns on. c9 is discharged through d3 to the same level each cycle regard- less of duty cycle. r10 and r11 are chosen to control the amount of slope compensation. c10 provides filtering for noise and turn-on spikes. to calculate the required slope compensation, calculate the buck indicator down current and the corresponding voltage slope at the current sense resistor - r12. the buck inductor down slope is: inductor_slope = ) a s ( v out + v q5 l1(h) sync out clk1 gate1 clk2 gate2 gate2b sync in time (ns) resistance (k ? ) 80 70 60 50 40 30 20 10 0 010 51520253035404550 1100 900 800 600 500 400 300 200 100 0 010203040 50 80 70 700 1000 frequency (khz) resistance k ? 60 theory of application: continued cs5106 10
cs5106 11 the equivalent down slope at the current sense resistor for this application circuit is: slope @ r12 = inductor_slope r12 after choosing r9 and c9 to generate a ramp with a time constant of about 5 times the oscillator period, r10 and r11 can be chosen for the voltage at ramp2 to be 1.75 of the voltage across r12. synchronous rectification synchronous rectification was chosen to reduce losses in the forward converter. improvements in efficiency will be most significant in low voltage, medium and high current converters where improvement in conduction loss offsets any added losses for gate drive. in the application circuit q4 is turned on and off by the for- ward transformer. q5 is turned on and off through pulse transformer t4 and the gate driver formed by q6 and q7. because q4 and q5 are driven through different types of components, differences in propagation delay must be con- sidered. the dlyset resistor should be chosen to avoid shoot-through or excessive off time. gate drive capability all gate drive outputs have nominal peak currents of 0.5 . see figures 6 and 7 for typical rise and fall times. figure 6: typical gate2, 2b switching times. figure 7: typical gate1 switching times. design considerations the circuit board should utilize high frequency layout techniques to avoid pulse width jitter and false triggering of high impedance inputs. ground plane(s) should be employed. signal grounds and power grounds should be run separately. portions of the circuit with high slew rates or current pulses should be segregated from sensitive areas. shields and decoupling capacitors should be used as required. special care should be taken to prevent coupling between the sync leads and the surrounding leads. depending on the circuit board layout and component values, decoupling capacitors or reduction in resistor values might be required to reduce noise pick-up on the fadj and dlyset resistors. decoupling capacitors or active pull-up/down might be required to prevent false triggering of the enable and program leads. time (ns) load capacitance (pf) 60 50 40 30 20 10 0 50 rise time fall time 70 1500 500 1000 2000 200 time (ns) load capacitance (pf) 70 60 50 40 30 20 10 0 rise time fall time 50 100 500 1000 2000 200 ) v s ( np t3 ns t3 ns t2 np t2 theory of application: continued
12 thermal data 24 lead ssop r jc typ 23 ? c/w r ja typ 117 ? c/w rev. 6/24/99 ? 1999 cherry semiconductor corporation package specification package dimensions in mm (inches) d lead count metric english max min max min 24 lead ssop 8.50 7.90 .335 .311 package thermal data cs5106 ordering information part number description cs5106lsw24 24 lead ssop CS5106LSWR24 24 lead ssop (tape & reel) cherry semiconductor corporation reserves the right to make changes to the specifications without notice. please contact cherry semiconductor corporation for the latest available information. seating plane 0.65 (.026) bsc 0.38 (.015) 0.22 (.009) d 0.25 (.010) 0.05 (.002) 1.88 (.074) 1.62 (.064) 2.13 (.084) max 1.03 (.041) 0.77 (.030) 8.20 (.323) 7.40 (.291) 0.20 (.008) 0.09 (.004) 5.60 (.220) 5.00 (.197) see detail a parting line detail a ref: jedec mo-150 ssop (sw); 5.3mm body

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