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high-speed multi-phase pll clock buffe r roboclock ? cy7b993v cy7b994v cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07127 rev. *f revised august 10, 2005 features ? 500-ps max. total timing budget? (ttb?) window ? 12?100-mhz (cy7b993v), or 24?200-mhz (cy7b994v) input/output operation ? matched pair output skew < 200 ps ? zero input-to-output delay ? 18 lvttl outputs driving 50 ? terminated lines ? 16 outputs at 200 mhz: commercial temperature ? 6 outputs at 200 mhz: industrial temperature ? 3.3v lvttl/lvpecl, fault-tole rant, and hot insertable reference inputs ? phase adjustments in 625-/1300-ps steps up to 10.4 ns ? multiply/divide rati os of 1?6, 8, 10, 12 ? individual output bank disable ? output high-impedance option for testing purposes ? fully integrated phase-locked loop (pll) with lock indicator ? <50-ps typical cycle-to-cycle jitter ? single 3.3v 10% supply ? 100-pin tqfp package ? 100-lead bga package functional description the cy7b993v and cy7b994v high-speed multi-phase pll clock buffers offer user-selectable control over system clock functions. this multiple-output clock driver provides the system integrator with functi ons necessary to optimize the timing of high-performance computer and communication systems. these devices feature a g uaranteed maximum ttb window specifying all occurrences of out put clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. eighteen configurable output s each drive terminated trans- mission lines with impedances as low as 50 ? while delivering minimal and specified output skews at lvttl levels. the outputs are arranged in five banks. banks 1 to 4 of four outputs allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 625?1300-ps increments up to 10.4 ns. one of the output banks also includes an independent clock invert function. the feedback bank consists of two outputs, which allows divide-by functional ity from 1 to 12 and limited phase adjustments. any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs. selectable reference input is a fault tolerance feature that allows smooth change-over to secondary clock source, when the primary clock source is not in operation. the reference inputs and feedback inputs are configurable to accommodate both lvttl or differential (l vpecl) inputs. the completely integrated pll reduces jitter and simplifies board layout. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 fs output_mode fbf0 fbds0 fbds1 fbdis 4f0 4f1 4ds0 4ds1 dis4 3f0 3f1 3ds0 3ds1 dis3 2f0 2f1 2ds0 2ds1 dis2 1f0 1f1 1ds0 1ds1 dis1 qfa0 qfa1 4qa0 4qa1 4qb0 4qb1 3qa0 3qa1 3qb0 3qb1 2qa0 2qa1 2qb0 2qb1 1qa0 1qa1 1qb0 1qb1 lock fbka+ fbka? fbkb+ fbkb? fbsel refa+ refa? refb+ refb? refsel 3 inv3 divide and phase select matrix divide and phase select matrix divide and phase select matrix divide and phase select matrix divide and phase select matrix phase freq. detector filter vco control logic divide and phase generator feedback bank bank 4 bank 3 bank 2 bank 1 functional block diagram [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 2 of 15 pin configurations 100-pin tqfp 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 vccq refa+ refa ? refsel refb? refb+ vccn fs 2qa0 gnd gnd 2qb1 gnd gnd 2f0 2qb0 vccn fbf0 1f0 gnd vccq fbdis dis4 dis3 2qa1 58 57 56 55 54 53 52 51 gnd 3f1 4f1 3f0 4f0 4ds1 4qb0 gnd vccn gnd 4qa1 gnd 2ds1 4qb1 3ds1 vccn 4qa0 1ds1 vccq 4ds0 3ds0 2ds0 1ds0 gnd gnd 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 lock fbds1 fbds0 gnd 1qb1 vccn vccn gnd 1qa1 gnd gnd qfa1 gnd gnd 1qb0 qfa0 vccn gnd fbkb+ fbkb? fbsel fbka? fbka+ vccq 1qa0 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 gnd vccq output_mode gnd inv3 3qb0 gnd vccn 3qa1 vccn dis2 dis1 3qb1 vccq 3qa0 gnd 1f1 2f1 vccq vccq gnd gnd gnd gnd 33 32 31 30 29 28 27 26 cy7b993/4v gnd [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 3 of 15 100-lead bga pin definitions [1] pin name i/o pin type pin description fbsel input lvttl feedback input select : when low, fbka inputs are se lected. when high, the fbkb inputs are selected. this input has an internal pull-down. fbka+, fbka? fbkb+, fbkb? input lvttl/ lvdiff feedback inputs : one pair of inputs selected by the fbsel is used to feedback the clock output xqn to the phase detector. the pll will operate such that the rising edges of the reference and feedback signals are aligned in both phase and frequency. these inputs can operate as differential pecl or single-ended ttl inputs. when operating as a single-ended lvttl input, the complementary input must be left open. refa+, refa? refb+, refb? input lvttl/ lvdiff reference inputs : these inputs can operate as differential pecl or single-ended ttl reference inputs to the pll. when operating as a single-ended lvttl input, the comple- mentary input must be left open. refsel input lvttl reference select input : the refsel input controls how the reference input is configured. when low, it will use the refa pair as the reference input. when high, it will use the refb pair as the reference i nput. this input has an internal pull-down. fs input 3-level input frequency select : this input must be set according to the nominal frequency (f nom ) (see table 1 ). fbf0 input 3-level input feedback output phase function select : this input determines the phase function of the feedback bank?s qfa[0:1] outputs (see table 3 ). note: 1. for all three-state inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. pin configurations (continued) 12345678910 a 1qb1 1qb0 1qa1 1qa0 qfa0 qfa1 fbkb+ vccq fbka? fbka+ b vccn vccn vccn vccn vccn vccn vccq fbkb? fbsel refa+ c gnd gnd gnd gnd gnd gnd vccq gnd gnd refa? d lock 4f0 (3_level) 3f1 (3_level) gnd fbds1 (3_level) fbds0 (3_level) 2f0 (3_level) vccq refsel refb? e 4qb1 vccn 4ds1 (3_level) gnd 3f0 (3_level) 4f1 (3_level) gnd fs (3_level) vccn refb+ f 4qb0 vccn 3ds1 (3_level) gnd gnd gnd gnd fbf0 (3_level) vccn 2qa0 g 4qa1 2ds1 (3_level) vccq gnd gnd gnd gnd vccq 1f0 (3_level) 2qa1 h 4qa0 1ds1 (3_level) 1ds0 (3_level) vccq gnd gnd vccq output mode (3_level) fbdis 2qb0 j 4ds0 (3_level) 3ds0 (3_level) 2ds0 (3_level) dis1 vccn vccn gnd inv3 (3_level) dis3 2qb1 k 2f1 (3_level) 1f1 (3_level) dis2 vccn 3qa0 3qa1 gnd 3qb0 3qb1 dis4 [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 4 of 15 block diagram description phase frequency detector and filter these two blocks accept signals from the ref inputs (refa+, refa?, refb+, or refb?) and the fb inputs (fbka+, fbka?, fbkb+, or fbkb?). co rrection information is then generated to control the frequency of the voltage-controlled oscillator (vco). these two bl ocks, along with the vco, form a pll that tracks the incoming ref signal. the cy7b993v/994v have a flexible ref and fb input scheme. these inputs allow the use of either differential lvpecl or single-ended lvttl inputs. to configure as single-ended lvttl inputs, the complementary pin must be left open (internally pulled to 1.5v). the other input pin can then be used as an lvttl input. the ref inputs are also tolerant to hot insertion. the ref inputs can be changed dynamically. when changing from one reference input to the other of the same frequency, the pll is optimized to ensure that the clock output period will not be less than the calculated system budget (t min = t ref (nominal reference clock period) ? t ccj (cycle-to-cycle jitter) ? t pdev (max. period deviation)) while reacquiring the lock. vco, control logic, divider, and phase generator the vco accepts analog control inputs from the pll filter block. the fs control pin setting determines the nominal operational frequency range of the divide by one output (f nom ) of the device. f nom is directly related to the vco frequency. there are two versions: a low-speed device (cy7b993v) where f nom ranges from 12 mhz to 100 mhz, and a high-speed device (cy7b994v) that ranges from 24 mhz to 200 mhz. the fs setting for each device is shown in ta ble 1 . the f nom frequency is seen on ?divide-by-one? outputs. for the cy7b994v, the upper f nom range extends from 96 mhz to 200 mhz. fbds[0:1] input 3-level input feedback divider function select : these inputs determine the function of the qfa0 and qfa1 outputs (see ta ble 4 ). fbdis input lvttl feedback disable : this input controls the state of qfa[0:1]. when high, the qfa[0:1] is disabled to the ?hold-off? or ?hi-z? state; the disable state is determined by output_mode. when low, the qfa[0:1] is enabled (see table 5 ). this input has an internal pull-down. [1:4]f[0:1] input 3-level input output phase function select : each pair controls the phase function of the respective bank of outputs (see table 3 ). [1:4]ds[0:1] input 3-level input output divider function select : each pair controls the divider function of the respective bank of outputs (see table 4 ). dis[1:4] input lvttl output disable : each input controls the state of the respective output bank. when high, the output bank is disabled to the ?hold-off? or ?hi-z? state; the disable state is deter- mined by output_mode. when low, th e [1:4]q[a:b][0:1] is enabled (see table 5 ). these inputs each have an internal pull-down. inv3 input 3-level input invert mode : this input only affects bank 3. when th is input is low, each matched output pair will become complementary (3qa0+, 3qa1?, 3qb0+, 3qb1?). when this input is high, all four outputs in the same bank will be inverted. when this input is mid all four outputs will be non inverting. lock output lvttl pll lock indicator : when high, this output indicates the internal pll is locked to the reference signal. when low, the pll is attempting to acquire lock. output_mode input 3-level input output mode : this pin determines the clock outputs? disable state. when this input is high, the clock outputs will disable to high-impedance (hi-z). when this input is low, the clock outputs will disable to ?hold-off? mode. when in mid, the device will enter factory test mode. qfa[0:1] output lvttl clock feedback output : this pair of clock outputs is intended to be connected to the fb input. these outputs have numerous divi de options and three choices of phase adjust- ments. the function is determined by the setting of the fbds[0:1] pins and fbf0. [1:4]q[a:b][0:1] output lvttl clock output : these outputs provide numerous divide and phase select functions deter- mined by the [1:4]ds[0:1] and [1:4]f[0:1] inputs. vccn pwr output buffer power : power supply for each output pair. vccq pwr internal power : power supply for the internal circuitry. gnd pwr device ground . pin definitions (continued) [1] pin name i/o pin type pin description [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 5 of 15 time unit definition selectable skew is in discret e increments of time unit (t u ). the value of a t u is determined by the fs setting and the maximum nominal output frequency. the equation to be used to determine the t u value is as follows: t u = 1/(f nom *n). n is a multiplication factor which is determined by the fs setting. f nom is nominal frequency of the device. n is defined in table 2 . divide and phase select matrix the divide and phase select matrix is comprised of five independent banks: four banks of clock outputs and one bank for feedback. each clock output bank has two pairs of low-skew, high-fanout output bu ffers ([1:4]q[a:b][0:1]), two phase function select inputs ([ 1:4]f[0:1]), two divider function selects ([1:4]ds[0:1]), and one output disable (dis[1:4]). the feedback bank has one pa ir of low-skew, high-fanout output buffers (qfa[0:1]). one of these outputs may connect to the selected feedback input (fbk[a:b]). this feedback bank also has one phase function select input (fbf0), two divider function selects fsds[0:1], and one output disable (fbdis). the phase capabilities that are chosen by the phase function select pins are shown in table 3 . the divide capabilities for each bank are shown in table 4 . figure 1 illustrates the timing relationship of programmable skew outputs. all times are measured with respect to ref with the output used for feedback programmed with 0t u skew. the pll naturally aligns the rising edge of the fb input and ref input. if the output used for feedback is programmed to another skew position, then the whole t u matrix will shift with respect to ref. for example, if the output used for feedback is programmed to shift ?8t u , then the whole matrix is shifted forward in time by 8t u . thus an output programmed with 8t u of skew will effectively be skewed 16t u with respect to ref. notes: 2. the level to be set on fs is determined by the ?nominal? operating frequency (f nom ) of the v co and phase generator. f nom always appears on an output when the output is operating in the undivided mode. the ref and fb are at f nom when the output connected to fb is undivided. 3. bk1, bk2 denotes following the skew sett ing of bank1 and bank2, respectively. table 1. frequency range select fs [2] cy7b993v cy7b994v f nom (mhz) f nom (mhz) min. max. min. max. low12262452 mid 24 52 48 100 high 48 100 96 200 table 2. n factor determination fs cy7b993v cy7b994v n f nom (mhz) at which t u =1.0 ns n f nom (mhz) at which t u =1.0 ns low 64 15.625 32 31.25 mid 32 31.25 16 62.5 high 16 62.5 8 125 table 3. output skew select function function selects output skew function [1:4]f1 [1:4]f0 and fbf0 bank1 bank2 bank3 bank4 feed- back bank low low ?4t u ?4t u ?8t u ?8t u ?4t u low mid ?3t u ?3tu ?7t u ?7t u na low high ?2t u ?2t u ?6t u ?6t u na mid low ?1t u ?1t u bk1 [3] bk1 [3] na mid mid 0t u 0t u 0t u 0t u 0tu mid high +1t u +1t u bk2 [3] bk2 [3] na high low +2t u +2t u +6t u +6t u na high mid +3t u +3t u +7t u +7t u na high high +4t u +4t u +8t u +8t u +4t u table 4. output divider function function selects output divider function [1:4]ds1 and fbds1 [1:4]ds0 and fbds0 bank 1 bank 2 bank 3 bank 4 feed- back bank low low /1 /1 /1 /1 /1 low mid /2 /2 /2 /2 /2 low high /3 /3 /3 /3 /3 mid low /4 /4 /4 /4 /4 mid mid /5 /5 /5 /5 /5 mid high /6 /6 /6 /6 /6 highlow/8/8/8/8 /8 high mid /10 /10 /10 /10 /10 high high /12 /12 /12 /12 /12 [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 6 of 15 output disable description the feedback divide and phase select matrix bank has two outputs, and each of the four divide and phase select matrix banks have four outputs. the outputs of each bank can be independently put into a hold-off or high-impedance state. the combination of the output_mode and dis[1:4]/fbdis inputs determines the clock outputs? state for each bank. when the dis[1:4]/fbdis is low, the outputs of the corresponding bank will be enabled. when the dis[1:4]/fbdis is high, the outputs for that bank will be disabled to a high-impedance (hi-z) or hold-off state depending on the output_mode input. table 5 defines the disabled output functions. the hold-off state is intended to be a power saving feature. an output bank is disabled to the hold-off state in a maximum of six output clock cycl es from the time when the disable input (dis[1:4]/fbdis) is high. when disabled to the hold-off state, non-inverting outputs are driven to a logic low state on its falling edge. inverting outputs are driven to a logic high state on its rising edge. this ensures the output clocks are stopped without glitch . when a bank of outputs is disabled to hi-z state, the res pective bank of outputs will go hi-z immediately. note: 4. fb connected to an output selected for ?zero? skew (i.e., fbf0 = mid or xf[1:0] = mid). figure 1. typical outputs with fb connected to a zero-skew output [4] t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fbinput refinput ?8t u ?7t u ?6t u ?4t u ?3t u ?2t u ?1t u 0t u +1t u +2t u +3t u ll lm lh (n/a) (n/a) (n/a) (n/a) mm (n/a) (n/a) (n/a) (n/a) hl 3f[1:0] 4f[1:0] (n/a) ll lm lh ml mh mm hm hh (n/a) (n/a) (n/a) 1f[1:0] 2f[1:0] +4t u +6t u +7t u +8t u t 0 ? 8t u t 0 ? 7t u t 0 +7t u t 0 +8t u hm hh hl (n/a) (n/a) table 5. dis[1:4]/fbdis pin functionality output_mode dis[1:4]/fbdis output mode high/low low enabled high high hi-z low high hold-off mid x factory test [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 7 of 15 inv3 pin function bank3 has signal invert capability. the four outputs of bank3 will act as two pairs of complementary outputs when the inv3 pin is driven low. in complementary output mode, 3qa0 and 3qb0 are non-inverting; 3qa1and 3qb1 are inverting outputs. all four outputs will be inverted when the inv3 pin is driven high. when the inv3 pin is left in mid, the outputs will not invert. inversion of the outputs are independent of the skew and divide functions. therefore, clock outputs of bank3 can be inverted, divided, and skewed at the same time. lock detect output description the lock detect output indica tes the lock condition of the integrated pll. lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. phase error is declared when the phase difference between the two inputs is greater than the specified device propagation delay limit (t pd ). when in the locked state, afte r four or more consecutive feedback clock cycles with phase-errors, the lock output will be forced low to indi cate out-of-lock state. when in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are required to allow the lock output to indicate lock condition (lock = high). if the feedback clock is removed after lock has gone high, a ?watchdog? circuit is implemented to indicate the out-of-lock condition after a time-out period by deasserting lock low. this time out period is based upon a divided down reference clock. this assumes that there is acti vity on the selected ref input. if there is no activity on the selected ref input then the lock detect pin may not accurately reflect the state of the internal pll. factory test mode description the device will enter factory test mode when the output_mode is driven to mid. in factory test mode, the device will operate with its in ternal pll disconnected; input level supplied to the reference input will be used in place of the pll output. in test mode the selected fb input(s) must be tied low. all functions of the device are still operational in factory test mode except the internal pll and output bank disables. the output_mode input is designed to be a static input. dynamically toggling this input from low to high may temporarily cause the device to go into factory test mode (when passing through the mid state). factory test reset when in factory test mode (output_mode = mid), the device can be reset to a deterministic state by driving the dis4 input high. when the dis4 input is driven high in factory test mode, all clock outputs will go to hi-z; after the selected reference clock pin has five positive transitions, all the internal finite state machines (fsm) will be set to a deterministic state. the deterministic state of the state machines will depend on the configurations of the divi de selects, skew selects, and frequency select input. all clock outputs will stay in high-impedance mode and all fsms will stay in the determin- istic state until dis4 is deass erted. when dis4 is deasserted (with output_mode still at mid), the device will re-enter factory test mode. safe operating zone figure 2 illustrates the operating condition at which the device does not exceed its allowable maximum junction temperature of 150c. figure 2 shows the maximum number of outputs that can operate at 185 mhz (with 25-pf load and no air flow) or 200 mhz (with 10-pf load and no air flow) at various ambient temperatures. at the limit line, all other outputs are configured to divide-by-two (i.e., operating at 92.5 mhz) or lower frequencies. the device will operate below maximum allowable junction temperatur e of 150c when its configu- ration (with the specified constraints) falls within the shaded region (safe operating zone). figure 2 shows that at 85c, the maximum number of outputs t hat can operate at 200 mhz is 6; and at 70c, the maximum number of outputs that can operate at 185 mhz is 16 (with 25-pf load and 0-m/s air flow). typical safe operating zone (25-pf load, 0-m /s air flow ) 50 55 60 65 70 75 80 85 90 95 100 24681012141618 num ber of outputs at 185 mhz ambient temperature (c) safe operating zone figure 2. typical safe operating zone [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 8 of 15 absolute maximum conditions [5] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................ ?40 c to + 125 c ambient temperature with power applied............................................ ?40 c to + 125 c supply voltage to ground potential .............. ?0.5v to + 4.6v dc input voltage....................................?0.3v to v cc + 0.5v output current into outputs (low)............................. 40 ma static discharge voltage........................................... > 1100v (per mil-std-883, method 3015) latch-up current.................................................. > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 10% industrial ?40 c to +85 c 3.3v 10% electrical characteristics over the operating range parameter description test conditions min. max. unit lvttl compatible output pins (q fa[0:1], [1:4]q[a:b][0:1], lock) v oh lvttl high voltage qfa[0:1], [1:4]q[a:b][0:1] v cc = min., i oh = ?30 ma 2.4 ?v lock i oh = ?2 ma, v cc = min. 2.4 ? v v ol lvttl low voltage qfa[0:1], [1:4]q[a:b][0:1] v cc = min., i ol = 30 ma ? 0.5 v lock i ol = 2 ma, v cc = min. ? 0.5 v i oz high-impedance state leakage current ?100 100 a lvttl compatible input pins (fbka, fbkb, re fa, refb, fbsel, refsel, fbdis, dis[1:4]) v ih lvttl input high fbk[a: b], ref[a:b] min. < v cc < max. 2.0 v cc + 0.3 v refsel, fbsel, fbdis, dis[1:4] 2.0 v cc + 0.3 v v il lvttl input low fbk[a:b], ref[a:b] min. < v cc < max. ?0.3 0.8 v refsel, fbsel, fbdis, dis[1:4] ?0.3 0.8 v i i lvttl v in >v cc fbk[a:b], ref[a:b] v cc = gnd, v in = 3.63v ? 100 a i lh lvttl input high current fbk[a:b], ref[a:b] v cc = max., v in = v cc ? 500 a refsel, fbsel, fbdis, dis[1:4] v in = v cc ? 500 a i ll lvttl input low current fbk[a:b], ref[a:b] v cc = max., v in = gnd ?500 ? a refsel, fbsel, fbdi s, dis[1:4] ?500 ? a three-level input pins (fbf0, fbds[0:1], [1:4]f[0:1 ], [1:4]ds[0:1], fs, output_mode(test)) v ihh three-level input high [6] min. < v cc < max. 0.87*v cc ?v v imm three-level input mid [6] min. < v cc < max. 0.47*v cc 0.53*v cc v v ill three-level input low [6] min. < v cc < max. ? 0.13*v cc v i ihh three-level input high current three-level input pins excl. fbf0 v in = v cc ? 200 a fbf0 ? 400 a i imm three-level input mid current three-level input pins excl. fbf0 v in = v cc /2 ?50 50 a fbf0 ?100 100 a i ill three-level input low current three-level input pins excl. fbf0 v in = gnd ?200 ? a fbf0 ?400 ? a lvdiff input pins (f bk[a:b], ref[a:b]) v diff input differential voltage 400 v cc mv v ihhp highest input high voltage 1.0 v cc v v illp lowest input low voltage gnd v cc ? 0.4 v v com common mode range (c rossing voltage) 0.8 v cc v notes: 5. multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 6. these inputs are normally wired to v cc , gnd, or left unconnected (actual thres hold voltages vary as a percentage of v cc ). internal termination resistors hold the unconnected inputs at v cc /2. if these inputs are switched, the function and timing of t he outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved. [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 9 of 15 operating current i cci internal operating current cy7b993v v cc = max., f max [7] ? 250 ma cy7b994v ? 250 ma i ccn output current dissipation/pair [8] cy7b993v v cc = max., c load = 25 pf, r load = 50 ? at v cc /2, f max ?40ma cy7b994v ? 50 ma electrical characteristics over the operating range (continued) parameter description test conditions min. max. unit capacitance parameter description test conditions min. max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 5 pf switching characteristics over the operating range [9, 10, 11, 12, 13] parameter description cy7b993/4v-2 cy7b993/4v-5 unit min. typ. max. min. typ. max. f in clock input frequency cy7b993v 12 ? 100 12 ? 100 mhz cy7b994v 24 ? 200 24 ? 200 mhz f out clock output frequency cy7b993v 12 ? 100 12 ? 100 mhz cy7b994v 24 ? 200 24 ? 200 mhz t skewpr matched-pair skew [14, 15] ? ? 200 ? ? 200 ps t skewbnk intrabank skew [14, 15] ? ? 200 ? ? 250 ps t skew0 output-output skew (same fr equency and phase, rise to rise, fall to fall) [14, 15] ? ? 250 ? ? 550 ps t skew1 output-output skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall) [14, 15] ? ? 250 ? ? 650 ps t skew2 output-output skew (invert to nominal of different banks, compared banks at same frequency, rising edge to falling edge aligned, other banks at same frequency) [14, 15] ? ? 250 ? ? 700 ps t skew3 output-output skew (all output configurations outside of t skew1 and t skew2 ) [14, 15] ? ? 500 ? ? 800 ps t skewcpr complementary outputs skew (crossing to crossing, complementary outputs of the same bank) [14, 15, 16, 17] ? ? 200 ? ? 300 ps t ccj1-3 cycle-to-cycle jitter (divide by 1 output frequency, fb = divide by 1, 2, 3) ? 50 150 ? 50 150 ps peak t ccj4-12 cycle-to-cycle jitter (divide by 1 output frequency, fb = divide by 4, 5, 6, 8, 10, 12) ? 50 100 ? 50 100 ps peak t pd propagation delay, ref to fb rise ?250 ? 250 ?500 ? 500 ps notes: 7. i cci measurement is performed with bank1 and fb bank configured to run at maximum frequency (f nom = 100 mhz for cy7b993v, f nom = 200 mhz for cy7b994v), and all other clock output banks to run at half the maximum frequency. fs and output_mode are asserted to the high s tate. 8. this is dependent upon frequency and number of outputs of a bank being loaded. the value indicates maximum i ccn at maximum frequency and maximum load of 25 pf terminated to 50 ? at v cc /2. 9. this is for non-three level inputs. 10. assumes 25-pf max. load capacitance up to 185 mhz. at 200 mhz the max. load is 10 pf. 11. both outputs of pair must be terminated, even if only one is being used. 12. each package must be properly decoupled. 13. ac parameters are measured at 1.5v unless otherwise indicated. 14. test load c l = 25 pf, terminated to v cc /2 with 50 ? up to185 mhz and 10-pf load to 200 mhz. 15. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pf and properly terminated up to 185 mhz. at 200 mhz the max load is 10 pf. 16. complementary output skews are measured at complementary signal pair intersections. 17. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 10 of 15 ac test loads and waveform [26] notes: 18. ttb is the window between the earliest and the latest output clocks with respect to the input reference clock across variati ons in output frequency, supply voltage, operating temperature, input clock edge rate, and process. the meas urements are taken with the ac test load specified and inclu de output-output skew, cycle-cycle jitter, and dynamic phase error. ttb will be equal to or smaller than the maximum specified value at a given frequency. 19. tested initially and after any design or proc ess changes that may affect these parameters. 20. rise and fall times are measured between 2.0v and 0.8v. 21. f nom must be within the frequency range defined by the same fs state. 22. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 23. ui = unit interval. examples: 1 ui is a full period. 0.1ui is 10% of period. 24. measured at 0.5v deviation from starting voltage. 25. for t oza minimum, c l = 0 pf. for t oza maximum, c l = 25 pf to 185 mhz or 10 pf to 200 mhz. 26. these figures are for illustrations only. the actual ate loads may vary. ttb total timing budget window (same frequency and phase) [17, 18] ? ? 500 ? ? 700 ps t pddelta propagation delay difference between two devices [17] ? ? 200 ? ? 200 ps t refpwh ref input (pulse width high) [19] 2.0 ? ? 2.0 ? ? ns t refpwl ref input (pulse width low) [19] 2.0 ? ? 2.0 ? ? ns t r /t f output rise/fall time [20] 0.15 ? 2.0 0.15 ? 2.0 ns t lock pll lock time from power-up ? ? 10 ? ? 10 ms t relock1 pll relock time (from same frequency, different phase) with stable power supply ? 500 ? 500 s t relock2 pll relock time (from different frequency, different phase) with stable power supply [21] ? 1000 ? 1000 s t odcv output duty cycle deviation from 50% [13] ?1.0 1.0 ?1.0 1.0 ns t pwh output high time deviation from 50% [22] ?1.5? 1.5ns t pwl output low time deviation from 50% [22] ?2.0? 2.0ns t pdev period deviation when changing from reference to reference [23] ? 0.025 ? 0.025 ui t oaz dis[1:4]/fbdis high to output high-impedance from active [14, 24] 1.0 10 1.0 10 ns t oaz dis[1:4]/fbdis low to output active from output high-impedance [24, 25] 0.5 14 0.5 14 ns switching characteristics over the operating range [9, 10, 11, 12, 13] (continued) parameter description cy7b993/4v-2 cy7b993/4v-5 unit min. typ. max. min. typ. max. 2.0v 0.8v 3.3v gnd 2.0v 0.8v 3.3v output (a) lvttl ac test load < 1ns < 1 ns (b) ttl input test waveform r1 r2 c l r1 = 910 ? r2 = 910 ? c l <30pf (includes fixture and probe capacitance) r1 = 100 ? r2 = 100 ? c l < 25 pf to 185 mhz for lock output only for all other outputs or 10 pf at 200 mhz [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 11 of 15 ac timing diagrams [13] ordering information propagation delay (ps) max. speed (mhz) ordering code package type operating range 250 100 cy7b993v-2ac 100-lead thin quad flat pack commercial 250 100 cy7b993v-2act 100-lead thin quad flat pack - tape and reel commercial 250 100 cy7b993v-2ai 100-lead thin quad flat pack industrial 250 100 cy7b993v-2ait 100-lead thin quad flat pack - tape and reel industrial 250 200 cy7b994v-2ac 100-lead thin quad flat pack commercial 250 200 cy7b994v-2act 100-lead thin quad flat pack - tape and reel commercial 250 200 cy7b994v-2bbc 100-ball thin ball grid array commercial 250 200 cy7b994v-2bbct 100-ball thin ball grid array - tape and reel commercial 250 200 cy7b994v-2ai 100-lead thin quad flat pack industrial 250 200 cy7b994v-2ait 100-lead thin quad flat pack - tape and reel industrial 250 200 cy7b994v-2bbi 100-ball thin ball grid array industrial 250 200 cy7b994v-2bbit 100-ball thin ball grid array -tape and reel industrial t pwl t pwh ref fb q q inverted q t refpwh t refpwl t pd t ccj1-3,4-12 complementary b complementary a t skewcpr t skew2 [1:4]q[a:b]0 [1:4]q[a:b]1 t skewpr [1:4]qa[0:1] [1:4]qb[0:1] t skewbnk t skewpr t skewbnk t skew2 q other q t skew0,1 t skew0,1 2.0v 0.8v qfa0 or qfa1 or t odcv t odcv ref to device 1 and 2 fb device1 fb device2 t pd t pdelta t pdelta crossing crossing [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 12 of 15 500 100 cy7b993v-5ac 100-lead thin quad flat pack commercial 500 100 CY7B993V-5ACT 100-lead thin quad flat pack - tape and reel commercial 500 100 cy7b993v-5ai 100-lead thin quad flat pack industrial 500 100 cy7b993v-5ait 100-lead thin quad flat pack - tape and reel industrial 500 200 cy7b994v-5ac 100-lead thin quad flat pack commercial 500 200 cy7b994v-5act 100-lead thin quad flat pack - tape and reel commercial 500 200 cy7b994v-5bbc 100-ball thin ball grid array commercial 500 200 cy7b994v-5bbct 100-ball thin ball grid array - tape and reel commercial 500 200 cy7b994v-5bbi 100-ball thin ball grid array industrial 500 200 cy7b994v-5bbit 100-ball thin ball grid array -tape and reel industrial 500 200 cy7b994v-5ai 100-lead thin quad flat pack industrial 500 200 cy7b994v-5ait 100-lead thin quad flat pack - tape and reel industrial lead-free 250 100 cy7b993v-2axc 100-lead thin quad flat pack commercial 250 100 cy7b993v-2axct 100-lead thin quad flat pack - tape and reel commercial 250 100 cy7b993v-2axi 100-lead thin quad flat pack industrial 250 100 cy7b993v-2axit 100-lead thin quad flat pack - tape and reel industrial 250 200 cy7b994v-2axc 100-lead thin quad flat pack commercial 250 200 cy7b994v-2axct 100-lead thin quad flat pack - tape and reel commercial 250 200 cy7b994v-2bbxc 100-ball thin ball grid array commercial 250 200 cy7b994v-2bbxct 100-ball thin ball grid array - tape and reel commercial 250 200 cy7b994v-2axi 100-lead thin quad flat pack industrial 250 200 cy7b994v-2axit 100-lead thin quad flat pack - tape and reel industrial 250 200 cy7b994v-2bbxi 100-ball thin ball grid array industrial 250 200 cy7b994v-2bbxit 100-ball thin ball grid array -tape and reel industrial 500 100 cy7b993v-5axc 100-lead thin quad flat pack commercial 500 100 cy7b993v-5axct 100-lead thin quad flat pack - tape and reel commercial 500 100 cy7b993v-5axi 100-lead thin quad flat pack industrial 500 100 cy7b993v-5axit 100-lead thin quad flat pack - tape and reel industrial 500 200 cy7b994v-5axc 100-lead thin quad flat pack commercial 500 200 cy7b994v-5axct 100-lead thin quad flat pack - tape and reel commercial 500 200 cy7b994v-5bbxc 100-ball thin ball grid array commercial 500 200 cy7b994v-5bbxct 100-ball thin ball grid array -tape and reel commercial 500 200 cy7b994v-5bbxi 100-ball thin ball grid array industrial 500 200 cy7b994v-5bbxit 100-ball thin ball grid array - tape and reel industrial 500 200 cy7b994v-5axi 100-lead thin quad flat pack industrial 500 200 cy7b994v-5axit 100-lead thin quad flat pack - tape and reel industrial ordering information (continued) propagation delay (ps) max. speed (mhz) ordering code package type operating range [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 13 of 15 package diagrams 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-*b [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 14 of 15 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. roboclock is a registered trademark, and ttb and total timing budget are trademarks, of cypr ess semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 100-ball thin ball grid array (11 x 11 x 1.4 mm) bb100 51-85107-*b [+] feedback
roboclock ? cy7b993v cy7b994v document #: 38-07127 rev. *f page 15 of 15 document history page document title: roboclock ? cy7b994v/cy7b993v high-speed multi-phase pll clock buffer document number: 38-07127 rev. ecn no. issue date orig. of change description of change ** 109957 12/16/01 szv changed from spec number: 38-00747 to 38-07127 *a 114376 05/06/02 ctk added three industrial packages *b 116570 09/04/02 hwt added ttb features *c 122794 12/14/02 rbi power-up requirements to operating conditions information *d 123694 03/04/03 rgl added min. f out value of 12 mhz for cy7b993v and 24 mhz for cy7b994v to switching characteristics table corrected prop delay limit parameter from (t pdsl ,m,h) to t pd in the lock detect output description paragraph *e 128462 07/29/03 rgl added clock input frequency (f in ) specifications in the switching characteristics table *f 391560 see ecn rgl added lead-free devices added typical values for jitter [+] feedback

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