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d?a?t?a?b?o?o?k samsung v samsung asic STD80/stdm80 0.5 m m 5v/3.3v standard cell library april 1997
STD80/stdm80 0.5 m m 5v/3.3v standard cell library data book ? 1997 samsung electronics co., ltd. all rights reserved. no part of this document may be reproduced, in any form or by any means, without the prior written consent of the publisher. samsung assumes no responsibility for any errors resulting from the use of the information contained herein, nor does it convey any license under the patent rights of samsung or others. samsung reserves the right to make changes in its products or product specification to improve function or design at any time, without notice. sec, STD80 and stdm80 are trademarks of samsung electronics co., ltd. verilog is a registered trademark of cadence design systems, inc. viewlogic is a registered trademark of viewlogic systems, inc. mentor is a registered trademark or mentor graphics co. synopsys is a registered trademark of synopsys, inc. gards is a registered trademark of silvar-lisco. head office samsung electronics co., ltd lsi division, asic team san #24, nongseo-ree, kiheung-eup, yongin-shi, kyunggi-do, korea tel 02-760-6500 (hot line) fax 02-760-6499 printed in the republic of korea marketing team samsung electronics co., ltd semiconductor sales division, lsi export team 15th fl., severance bldg. 84-11, 5-ka, namdaemoon-ro, chung-ku, seoul, korea tel 02-259-4988 fax 02-259-2494
sec asic iii STD80/stdm80 introduction this databook contains information about STD80/stdm80, 0.5 m m 5v/3.3v dlm/tlm standard cell library developed by sec (samsung electronics corporation). the library basically contains various kinds of internal and i/o cells and soft-macros which are used for developing asic (application specific integrated circuit). it also includes a design kit helping designers to work in a workstation platform, and all sorts of design environments needed for an automatic chip design. there are seven chapters in this databook: chapter 1 introduction to STD80/stdm80 chapter 2 electrical characteristics chapter 3 internal macrocells chapter 4 input/output cells chapter 5 memory compilers chapter 6 datapath compilers chapter 7 jtag boundary scans. in this databook each cell is followed by its ac electrical characteristics, and these characteristic values are almost equal when the corresponding cell is operated in a real chip. the purpose of this databook is to prevent any misuse or misapplication of STD80/stdm80 cell library by providing precise information about the cell list, electrical data, directions for use, and matters demanding special attention.
STD80/stdm80 iv sec asic table of contents 1 introduction to STD80/stdm80 library description ........................................................................................................................1-1 features ........................................................................................................................................1-1 cae support .................................................................................................................................1-2 product family ..............................................................................................................................1-2 internal macrocells ...............................................................................................................1-2 macrofunctions .....................................................................................................................1-2 megafunctions ......................................................................................................................1-2 memory compilers ...............................................................................................................1-2 datapath compilers ..............................................................................................................1-2 input/output cells.................................................................................................................1-3 v dd /v ss rules and guidelines .....................................................................................................1-6 power dissipation..........................................................................................................................1-7 propagation delays .......................................................................................................................1-9 delay model ..................................................................................................................................1-13 testability design methodology.....................................................................................................1-14 maximum fanouts .........................................................................................................................1-15 product line-up ............................................................................................................................1-22 packages.......................................................................................................................................1-22 dedicated corner v dd /v ss pads ..................................................................................................1-23 external design interface considerations .....................................................................................1-23 crystal oscillator considerations ..................................................................................................1-29 2 electrical characteristics dc electrical characteristics.........................................................................................................2-1 input buffer dc curves .................................................................................................................2-3 output drive capabilities...............................................................................................................2-5 3 internal macrocells overview .......................................................................................................................................3-1 summary tables ...........................................................................................................................3-2 logic cells ad2/ad2d2...................................................................................................................................3-11 ad3/ad3d3...................................................................................................................................3-13 ad4/ad4d2...................................................................................................................................3-16
sec asic v STD80/stdm80 ad5/ad5d2...................................................................................................................................3-19 nd2/nd2d2 ..................................................................................................................................3-22 nd3/nd3d2 ..................................................................................................................................3-24 nd4/nd4d2 ..................................................................................................................................3-27 nd5/nd5d2 ..................................................................................................................................3-30 nd6/nd6d2 ..................................................................................................................................3-33 nd8/nd8d2 ..................................................................................................................................3-38 nr2/nr2d2 ..................................................................................................................................3-43 nr3/nr3d2 ..................................................................................................................................3-45 nr4/nr4d2 ..................................................................................................................................3-48 nr5/nr5d2 ..................................................................................................................................3-51 nr6/nr6d2 ..................................................................................................................................3-54 nr8/nr8d2 ..................................................................................................................................3-59 or2/or2d2 ..................................................................................................................................3-64 or3/or3d3 ..................................................................................................................................3-66 or4/or4d2 ..................................................................................................................................3-69 or5/or5d2 ..................................................................................................................................3-72 xn2/xn2d2...................................................................................................................................3-75 xn3/xn3d3...................................................................................................................................3-77 xo2/xo2d2 ..................................................................................................................................3-80 xo3/xo3d3 ..................................................................................................................................3-82 ao21/ao21d2...............................................................................................................................3-85 ao211/ao211d2...........................................................................................................................3-88 ao22/ao22d2...............................................................................................................................3-91 ao22a/ao22d2a..........................................................................................................................3-94 ao222/ao222d2...........................................................................................................................3-97 ao222a/ao222d2a......................................................................................................................3-102 ao33/ao33d2...............................................................................................................................3-105 ao333/ao333d2...........................................................................................................................3-110 oa21/oa21d2 ..............................................................................................................................3-115 oa211/oa211d2 ..........................................................................................................................3-118 oa22/oa22d2 ..............................................................................................................................3-121 oa22a/oa22d2a..........................................................................................................................3-124 oa2222/oa2222d2 ......................................................................................................................3-127 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 ........................................................................................3-132 iv/ivd2/ivd3/ivd4/ivd6/ivd8 ......................................................................................................3-138 iva/ivd2a/ivd3a/ivd4a...............................................................................................................3-142 ivcd(11/13)/ivcd(22/26)/ivcd44................................................................................................3-145 ivt/ivtd2/ivtd4/ivtd8 ...............................................................................................................3-149 ivtn/ivtnd2/ivtnd4/ivtnd8.....................................................................................................3-153 nid/nid2/nid3/nid4/nid6/nid8 ..................................................................................................3-157 nit/nitd2/nitd4/nitd8 ..............................................................................................................3-161 nitn/nitnd2/nitnd4/nitnd8 ....................................................................................................3-165
STD80/stdm80 vi sec asic flip-flops fd1/fd1d2 ...................................................................................................................................3-172 fd1cs/fd1csd2 .........................................................................................................................3-175 fd1s/fd1sd2 ..............................................................................................................................3-179 fd1q/fd1qd2 .............................................................................................................................3-182 fd1x2 ...........................................................................................................................................3-184 fd1x4 ...........................................................................................................................................3-186 yfd1/yfd1d2 ..............................................................................................................................3-189 fd2/fd2d2 ...................................................................................................................................3-192 fd2cs/fd2csd2 .........................................................................................................................3-195 fd2s/fd2sd2 ..............................................................................................................................3-199 fd2q/fd2qd2 .............................................................................................................................3-202 fd2x2 ...........................................................................................................................................3-204 fd2x4 ...........................................................................................................................................3-207 yfd2/yfd2d2 ..............................................................................................................................3-210 fd2t/fd2td2...............................................................................................................................3-213 fd2tcs/fd2tcsd2.....................................................................................................................3-216 fd2ts/fd2tsd2 ..........................................................................................................................3-221 fd3/fd3d2 ...................................................................................................................................3-225 fd3cs/fd3csd2 .........................................................................................................................3-228 fd3s/fd3sd2 ..............................................................................................................................3-232 fd3q/fd3qd2 .............................................................................................................................3-235 fd3x2 ...........................................................................................................................................3-237 fd3x4 ...........................................................................................................................................3-240 yfd3/yfd3d2 ..............................................................................................................................3-243 fd4/fd4d2 ...................................................................................................................................3-246 fd4cs/fd4csd2 .........................................................................................................................3-250 fd4s/fd4sd2 ..............................................................................................................................3-256 fd4q/fd4qd2 .............................................................................................................................3-260 fd4x2 ...........................................................................................................................................3-263 fd4x4 ...........................................................................................................................................3-266 yfd4/yfd4d2 ..............................................................................................................................3-271 fd5/fd5d2 ...................................................................................................................................3-274 fd5s/fd5sd2 ..............................................................................................................................3-277 fd5x4 ...........................................................................................................................................3-280 fd6/fd6d2 ...................................................................................................................................3-283 fd6s/fd6sd2 ..............................................................................................................................3-286 fd7/fd7d2 ...................................................................................................................................3-289 fd7s/fd7sd2 ..............................................................................................................................3-292 fd8/fd8d2 ...................................................................................................................................3-295 fd8s/fd8sd2 ..............................................................................................................................3-299 fds2/fds2d2 ..............................................................................................................................3-303 fds2cs/fds2csd2 ....................................................................................................................3-306
sec asic vii STD80/stdm80 fds2s/fds2sd2..........................................................................................................................3-310 fds3/fds3d2 ..............................................................................................................................3-313 fg1 ...............................................................................................................................................3-316 fg1x4 ...........................................................................................................................................3-318 fg2 ...............................................................................................................................................3-323 fg2x4 ...........................................................................................................................................3-326 fj1/fj1d2.....................................................................................................................................3-331 fj1s/fj1sd2 ................................................................................................................................3-334 fj2/fj2d2.....................................................................................................................................3-337 fj2s/fj2sd2 ................................................................................................................................3-340 fj4/fj4d2.....................................................................................................................................3-344 fj4s/fj4sd2 ................................................................................................................................3-348 ft2/ft2d2 ....................................................................................................................................3-352 ft3/ft3d2 ....................................................................................................................................3-355 latches ld1/ld1d2 ...................................................................................................................................3-360 ld1s/ld1sd2...............................................................................................................................3-363 ld1q/ld1qd2 ..............................................................................................................................3-368 ld1x4/ld1x4d2...........................................................................................................................3-371 yld1/yld1d2...............................................................................................................................3-380 ld1a .............................................................................................................................................3-383 ld1b .............................................................................................................................................3-385 ld2/ld2d2 ...................................................................................................................................3-388 ld2q/ld2qd2 ..............................................................................................................................3-393 yld2/yld2d2...............................................................................................................................3-396 ld3/ld3d2 ...................................................................................................................................3-401 ld4/ld4d2 ...................................................................................................................................3-406 ld5/ld5d2 ...................................................................................................................................3-411 ld5s/ld5sd2...............................................................................................................................3-414 ld5x4/ld5x4d2...........................................................................................................................3-419 ld6/ld6d2 ...................................................................................................................................3-428 ld7/ld7d2 ...................................................................................................................................3-433 ld8/ld8d2 ...................................................................................................................................3-438 lds2 .............................................................................................................................................3-443 lds6 .............................................................................................................................................3-446 ls0/ls0d2 ....................................................................................................................................3-449 ls1 ................................................................................................................................................3-452 ls2 ................................................................................................................................................3-455 bus holder busholder ................................................................................................................................3-458
STD80/stdm80 viii sec asic internal clock drivers ck2/ck4/ck6/ck8/ck12 .............................................................................................................3-459 decoders dc4 ...............................................................................................................................................3-463 dc4i ..............................................................................................................................................3-466 dc8i ..............................................................................................................................................3-469 adders fa/fad2 ........................................................................................................................................3-477 ha/had2.......................................................................................................................................3-482 multiplexers mx2/mx2d3 ..................................................................................................................................3-486 mx2x4 ..........................................................................................................................................3-489 ymx2/ymx2d2 .............................................................................................................................3-494 mx2i/mx2id2 ................................................................................................................................3-497 mx2ia/mx2id2a ...........................................................................................................................3-500 mx2ix4 .........................................................................................................................................3-503 mx3i/mx3id2 ................................................................................................................................3-508 mx4/mx4d2 ..................................................................................................................................3-511 ymx4/ymx4d2 .............................................................................................................................3-516 mx5/mx5d2 ..................................................................................................................................3-521 mx8/mx8d2 ..................................................................................................................................3-526 ymx8/ymx8d2 .............................................................................................................................3-532 4 input/output cells overview .......................................................................................................................................4-1 summary tables ...........................................................................................................................4-2 input buffers pvic/pvicd/pvicu........................................................................................................................4-9 pvil/pvild/pvilu .........................................................................................................................4-13 pvis/pvisd/pvisu ........................................................................................................................4-16 pvit/pvitd/pvitu .........................................................................................................................4-20 output buffers pvobyz .........................................................................................................................................4-24 pvodyz .........................................................................................................................................4-41 pvotyz ..........................................................................................................................................4-64 bi-directional buffers pvbadyz/pvbaudyz .....................................................................................................................4-98 pvbatyz/pvbadtyz/pvbautyz .....................................................................................................4-98
sec asic ix STD80/stdm80 input clock drivers psckdcy/psckdcdy/psckdcuy.............................................................................................4-100 psckdly/psckdldy/psckdluy...............................................................................................4-107 psckdsy/psckdsdy/psckdsuy .............................................................................................4-111 psckdty/psckdtdy/psckdtuy ..............................................................................................4-118 oscillators psosck(1/2/16/26) ......................................................................................................................4-123 psoscm(1/2/3/4/5/6/16/26/36/46/56/66) .....................................................................................4-132 pci buffers psipcia/plsipcia/psipcia3/phsipcia ....................................................................................4-148 psopcia/plsopcia/psopcia3/phsopcia.............................................................................4-149 psipciau......................................................................................................................................4-150 psopciau ....................................................................................................................................4-151 pcmcia buffers pvic(5/3) ......................................................................................................................................4-155 pvil(d/u)(5/3)/pvit(d/u)(5/3)......................................................................................................4-155 pvob(4/8/12)(5/3).........................................................................................................................4-156 pvod(4/8/12)(5/3) ........................................................................................................................4-156 pvot(4/8/12)(5/3) .........................................................................................................................4-157 pvot(8/12)sm(5/3).......................................................................................................................4-157 pvbtt(4/8/12)(5/3) .......................................................................................................................4-158 pvbtdt8sm/pvbct8sm(5/3) .....................................................................................................4-158 cardbus i/o buffers pvitcbu .......................................................................................................................................4-162 pvotcbu/pvotcckcbu/pvotcvscbu ...................................................................................4-163 pvodcckcbu..............................................................................................................................4-164 pvbttcbu/pvbtcckcbu/pvbtcvscbu ..................................................................................4-165 pvbdcckcbu ..............................................................................................................................4-166 plscb ..........................................................................................................................................4-167 usb i/o buffers pbusb/pbusb1 ...........................................................................................................................4-170 voltage detector vdet.............................................................................................................................................4-173 power pads vdd(5/3)(i/p/o/ip/oi/op/t) ..........................................................................................................4-174 vss(5/3)(i/p/o/ip/oi/op/t)...........................................................................................................4-174
STD80/stdm80 x sec asic 5 memory compilers overview .......................................................................................................................................5-1 memory compilers selection guide..............................................................................................5-2 crom gen....................................................................................................................................5-3 drom gen....................................................................................................................................5-10 spsram gen ...............................................................................................................................5-17 spsrama gen .............................................................................................................................5-27 sparam gen................................................................................................................................5-39 dpsram gen ...............................................................................................................................5-48 dpsrama gen.............................................................................................................................5-59 6 datapath compilers overview .......................................................................................................................................6-1 datapath compilers information....................................................................................................6-3 macro cells adder/subtracter ...........................................................................................................................6-5 arithmetic logic unit .....................................................................................................................6-7 array multiplier ..............................................................................................................................6-10 barrel shifter .................................................................................................................................6-16 carry-select adder........................................................................................................................6-19 comparator ...................................................................................................................................6-21 decrementer .................................................................................................................................6-23 fast multiplier ................................................................................................................................6-25 incrementer ...................................................................................................................................6-27 incrementer/decrementer .............................................................................................................6-29 normalizer.....................................................................................................................................6-31 one detector .................................................................................................................................6-33 parity .............................................................................................................................................6-35 priority encoder.............................................................................................................................6-37 register file ..................................................................................................................................6-39 saturating adder ...........................................................................................................................6-49 zero detector ................................................................................................................................6-51 logic cells and-or ........................................................................................................................................6-53 and-or-invert..........................................................................................................................6-55 buffer/inverter................................................................................................................................6-57 bus holder ....................................................................................................................................6-59 d flip-flop.....................................................................................................................................6-60 full adder ......................................................................................................................................6-72
sec asic xi STD80/stdm80 latch .............................................................................................................................................6-74 multiplexer .....................................................................................................................................6-82 nand/and....................................................................................................................................6-85 nor/or ........................................................................................................................................6-87 or-and ........................................................................................................................................6-89 or-and-invert..........................................................................................................................6-91 tri-state buffer/inverter .................................................................................................................6-93 xnor/xor ...................................................................................................................................6-95 7 jtag boundary scans overview .......................................................................................................................................7-1 boundary scan architecture..........................................................................................................7-2 boundary scan register macrocells .............................................................................................7-4 jtbi1 ....................................................................................................................................7-5 jtck.....................................................................................................................................7-12 jtin1 ....................................................................................................................................7-14 jtint1 ..................................................................................................................................7-18 jtout1 ................................................................................................................................7-24 jtag tap controller macrofunction..............................................................................................7-28 instruction register/decoder macrofunction .................................................................................7-31 implementation of ieee p1149.1/jtag ........................................................................................7-32 system clock considerations .......................................................................................................7-32
intrduction to STD80/stdm80 1
table of contents library description....................................................................................................... 1-1 features....................................................................................................................... 1-1 cae support................................................................................................................ 1-2 product family ............................................................................................................. 1-2 internal macrocells.............................................................................................. 1-2 macrofunctions.................................................................................................... 1-2 megafunctions..................................................................................................... 1-2 memory compilers.............................................................................................. 1-2 datapath compilers ............................................................................................ 1-2 input/output cells ............................................................................................... 1-3 v dd /v ss rules and guidelines .................................................................................... 1-6 power dissipation ........................................................................................................ 1-7 propagation delays ..................................................................................................... 1-9 delay model ................................................................................................................. 1-13 testability design methodology ................................................................................... 1-14 maximum fanouts ....................................................................................................... 1-15 product line-up........................................................................................................... 1-22 packages ..................................................................................................................... 1-22 dedicated corner v dd /v ss pads................................................................................. 1-23 external design interface considerations ................................................................... 1-23 crystal oscillator considerations................................................................................. 1-29
introduction to STD80/stdm80 library description sec asic 1-1 STD80/stdm80 library description STD80 and stdm80 are 5v and 3.3v 0.5 m m cmos standard cell libraries supporting triple- and double-layer metal interconnections provided by samsung electronics. every types of internal macrocells and input/output buffers are contained in these cell libraries. with the regard to the current increase of power mixture, 5v-to-3.3v and 3.3v-to-5v convertible cells having a level shifter inside are included in these libraries. in addition, the other interface (cmos, ttl and schmitt trigger) cells are fully equipped for your wide selection. various kinds of macrofunctions, megafunctions, memory and datapath compilers may satisfy the complicated design requirements. moreover, core & megafunction cells such as mpu and dsp, and analog cells are under development. we ensure the product reliability by preventing any possible noise, esd and latch-up eftciently. every work operation in a design ?ow has been systematized and automated, and each stage is designed to go through enough reviews and veritcations. it makes the design work easier and faster, and also prevents any errors or mistakes possible through a design ?ow. features q STD80: 5volt standard cell library stdm80: 3.3volt standard cell library q mixed 5v/3.3v i/o interface q 0.5 m m 5v hcmos technology e double and triple layer metal options q high basic cell usages e up to 700,000 total number of gates e maximum usage: 70% for triple layer metal e maximum usage: 40% for double layer metal q high speed e 0.2 ns (for STD80) and 0.3ns (for stdm80) delay of 2-input nand with fanout = 2 q fully contgurable ram, rom and dpram e up to 512k-bit rom available e up to 128k-bit ram available e up to 64k-bit dpram available q contgurable datapath elements available e 4 ~ 128-bit bus width q operating temperature (t a ) e commercial range: 0?c to +70?c e industrial range: e40?c to +85?c q esd and latch-up protection e esd: 2000v (min.) e latch-up: 300ma (min.) q selectable output current drive capability e 1/2/4/8/12/16/20/24ma available for 5v e 1/2/4/6/8/10/12/16ma available for 3.3v q ttl, cmos, lvttl, lvcmos and schmitt trigger i/os q x-tal oscillators q pci, pcmcia buffers q gtl, ntl, cardbus, scsi, pecl, usb under-developed q various package options q fully integrated cad software support e verilog, viewlogic, mentor and synopsys
cae support introduction to STD80/stdm80 STD80/stdm80 1-2 sec asic cae support STD80/stdm80 supports popular design platforms and environments such as verilog, viewlogic, mentor and synopsys for front-end logic design capture and simulation, and arccell for back-end placement and routing. for a high simulation accuracy, STD80/stdm80 uses a proprietary delay calculator. cell delay calculations are based on a matrix of delay parameters for each macrocell, and signal interconnection delay is based on the rc tree analysis. product family STD80/stdm80 library include the following design elements: (a) internal macrocells (b) input/output cells (c) macrofunctions (d) megafunctions (e) memory compilers (f) datapath compilers (g) jtag boundary scans. < internal macrocells > macrocells are the lowest level of logic functions such as nand, nor and ?ip-?op used for logic designs. there are about 300 different types of internal macrocells. they usually come in two levels of drive strength (1x and 2x). these macrocells have many levels of representationslogic symbol, logic model, timing model, transistor schematic, hspice netlist, physical layout, and placement and routing model. < macrofunctions > macrofunctions are netlists of logic function which have the complexity of a standard msi circuit. macrofunctions are logic building blocks. there are 44 kinds of 74xx (ttl) compatible functions in this library. < megafunctions > megafunctions are also netlists of logic function, but with a high logic complexity of a standard lsi circuit. multipliers, barrel shifters, 82xx intel functions, etc. are supported in this library. < memory compilers> memory compilers of stdl80 consist of two roms (synchronous contact programmable and synchronous diffusion programmable), three single-port rams (synchronous and asynchronous) and three dual-port rams (synchronous and asynchronous). in addition, a register file and a fifo are under-developed. < datapath compilers > datapath compilers of STD80/stdm80 consist of 16 macro cells (adder, alu, multiplier, etc.) and 14 primitive cells (nand, nor, dff, latch, mux, etc.)
introduction to STD80/stdm80 < input/output cells > sec asic 1-3 STD80/stdm80 < input/output cells > there are about one thousand different i/o buffers. each i/o cell is implemented solely on the basic i/o cell architecture which forms the periphery of the masterslice. a test logic is provided to enable the ef?cient parametric (threshold voltage) testing on input buffers including cmos and ttl level converters, schmitt trigger input buffers, clock drivers and oscillator buffers. pull-up and pull-down resistors are optional features. three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1ma to 24ma for 5v drive and 1ma to 16ma for 3.3v drive.two levels of slew rate controls are provided for each buffer type (except 1ma and 2ma buffers) to reduce output power/ground bus noise and signal ringing, especially in simultaneous switching outputs. bi-directional buffers are combinations of input buffers and output buffers (tri-state or open drain) in a single unit. the i/o structure has been fully characterized for esd protection and latch-up resistance. for users convenience, STD80/stdm80 library provides with three options of pull-down and pull-up resistances respectively. they are 50k w , 100k w , and 200k w (the default value is 100k w ). i/o cell drive options to provide designers with the greater ?exibility, each i/o buffer can be selected among various current levels (e.g., 1ma, 2ma, ..., 24ma). the choice of current-level for i/o buffers affects their propagation delay and current noise. the slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. the output edge rate can be slowed down by selecting the high slew rate control cells. STD80/stdm80 provides three different sets of output slew rate controls. only one i/o slot is required for any slew rate control options. 5v/3.3v mixed i/o cells when designers intend to make transitions from 5v supplies to low voltage system, STD80 offers a solution of interfacing problems encountered in mixed 5v/3v environment. this solution provides great ?exibility to different devices communicating each other. pci and pcmcia buffers are also available in this solution. you can see this in the following ?gure. figure 1-1. 5v/3.3v mixed i/o cells in STD80 in stdm80, level shifters are available to provide internal 3v core with great ?exibility when it interfaces with a 5v device. refer to the ?gure below. figure 1-2. 5v/3.3v mixed i/o cells in stdm80 pci buffers in addition to input, output, bi-directional, slew rate controlled and schmitt trigger i/o buffers, sec asic now offers pci (peripheral component interconnect) i/o buffers. pci is expected to be better suited to the more complex and feature-rich design than the existing local bus standards. 5v, 3.3v and universal pci buffers are included in the library. 3.3v level shifter 5v internal 5v STD80 i/o cells 3.3v level shifter 5v STD80 i/o cells operation 3.3v 5v internal 3.3v stdm80 i/o cells 3.3v 5v stdm80 i/o cells level shifter level shifter operation
< input/output cells > introduction to STD80/stdm80 STD80/stdm80 1-4 sec asic pecl sec asics pecl (positive emitter coupled logic) buffer having 155mhz operating frequency is suited to atm interface. it supports two voltage source modes; 5v and 3.3v. the voltage swing level is about 0.8v, being similar to that of ecl, and the external terminator is needed. its main features are the same as ecl; low noise, high speed and single ended/differential function. in case of differential transmission, the external terminator is shown in the following ?gure. figure 1-3. twisted pair termination techniques gtl (gunning transceiver logic) gtl and gtl+ interface i/os are useful for implementing highly reliable system, satisfying fast and low-powered signal transfers and reducing noise in a switching circuitry. in all 0.5 m m cell libraries in sec asic, gtl interface is fully supported. figure 1-4. gtl interface lvds lvds (low voltage differential signals) buffer for sci (scalable coherent interface) system, shown in the following ?gure, enables high speed i/o interface with sec asics high frequency pll. this structure is designed for high speed point-to-point unidirectional interface. its main characteristics are much the same as ecls differential mode; low noise generation, high noise immunity and low level signalling. figure 1-5. lvds interface r pd r pd r 1 v ee v ee z o r 1 = z o standard twisted pair termination r 1 r 1 v tt v tt z o r 1 = z o /2 parallel twisted pair termination r 1 r 2 v ee z o r 1 = z o /2 thevenin twisted pair termination r 3 v t v t logic rcvr vref logic rcvr vref logic rcvr vref r t r t 100 w a v oa v ob b a? b? v ia v ib v gpd receiver interconnect driver
introduction to STD80/stdm80 < input/output cells > sec asic 1-5 STD80/stdm80 lvttl/lvcmos low voltage ttl and low voltage cmos i/o buffers have various kinds of applications as normal ttl and cmos i/o sets. their key features are low voltage swing and low noise. input voltage level is 5v compatible. output high voltage is 2.4v ~ 3.5v in lvttl and vddC0.2v in lvcmos. scsi scsi is widely used to extend peripherals, requires external terminator. sec asic supports scsi-3 fast-20 parallel interface and scsi-3 parallel interface only in STD80. both of them have fail-safe function. scsi buffer is two times as big as normal buffers. pcmcia pcmcia (personnel computer memory card industry association) buffers guarantees an accurate logic level even when the internal or external voltage source level of a chip changes between 5v and 3.3v. this buffers are designed for 16-bit external extension card of notebook pc. cardbus buffers cardbus i/o buffers have 3.3v 32-bit bus width and 33mhz of transmission speed. they are for external cardbus type of extension card of notebook pc. usb speci?cation established late in 1995 is a good solution for this problem, providing facile method of an expansion. sec asic offers usb interfaced buffers in the 0.5 m m technology. usb is applicable only in std cells. usb (universal serial bus) various kinds of peripheral equipments such as mouse, joy stick, keyboard, modem, scanner and printer improve the power of a computer. however, it is not easy to connect and use them properly in the computer. figure 1-6. full speed device cable and resistor connections figure 1-7. low speed device cable and resistor connections r1 r1 d+ dC f.s./l.s. usb transceiver twisted pair shielded host or hub port r2 d+ dC f.s. usb transceiver hub port or full speed function 5 meters max. z0 = 90 w 15% r1 = 15k w r2 = 1.5k w r1 r1 d+ de f.s./l.s. usb transceiver untwisted, unshielded host or hub port r2 d+ de l.s. usb transceiver low speed function 3 meters max. r1 = 15k w r2 = 1.5k w slow slew rate buffer
vdd/vss rules and guidelines introduction to STD80/stdm80 STD80/stdm80 1-6 sec asic v dd /v ss rules and guidelines there are three types of v dd and v ss in STD80/stdm80, each with its related bus and pad cells. to support the use of mixed voltage, two different v dd types are needed for 5v and 3.3v respectively. (1) core logic C vssi, vdd5i (for 5v) (2) input buffers (usable when requested) C vssp, vdd5p (for 5v), vdd3p (for 3.3v) (3) output buffers C vsso, vdd5o (for 5v), vdd3o (for 3.3v) the number of v dd and v ss pads required for a speci?c design depends on the following factors: ? number of input and output buffers ? number of simultaneous switching inputs ? number of simultaneous switching outputs ? number of used gates and simultaneous switching gates ? operating frequency of the design. core logic v ss bus and vssi pad allocation guidelines the purpose of these guidelines is to ensure that v dd /v ss bounce caused by a simultaneous gate switching is kept to minimum. the voltage bounce on the power bus can have a negative impact on a gate-switching speed and even on the functionality of macrocells like ?ip-?ops and latches in an extreme case. because of variations in package inductance, the number of v dd /v ss pads required for a speci?c design is the function of the operating frequency of a chip, i.e., designs operating at high frequency should use more v dd /v ss pads. ?v dd bus width and pad requirements are half of v ss . ?v dd /v ss buses and pads should be distributed evenly in the core and on all sides of the chip. ? whenever possible, at least one vssi pad should be used on each side of the chip. ? the total number of core logic v dd pads required is half of vssi. the number of vssi pads required for a design can be calculated from the following expression: g x s x f x 2.00eC5 ,where g = total number of used gates, s = % of simultaneous switching gates, f = switching frequency in mhz. input buffer v dd /v ss pad allocation guidelines these guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. ? one vssp is required to support 32 input buffers, and one input buffer v dd can support up to 64 inputs. ? for simultaneous switching inputs, one vssp pad is required for every 20 inputs, and one input buffer v dd pad for every 40 inputs. ? input buffer v ss /v dd pads should be placed in such a way that they equally divide the input buffers on either side. output buffer v dd /v ss pad allocation guidelines the number of vsso pads required for a device can be calculated from the following expressions. in 5v ? (i ol simultaneous switching outputs ) / 40 + ? (i ol normal outputs ) / 64 in 3.3v ? (i ol simultaneous switching outputs ) / 50 + ? (i ol normal outputs ) / 80 the total number of output buffer v dd pads required is half of vsso. output buffer v ss /v dd pads should be placed in such a way that output buffers are equally divided on either side.
introduction to STD80/stdm80 power dissipation sec asic 1-7 STD80/stdm80 power dissipation estimation of power dissipation in cmos circuit cmos circuits have been traditionally considered to consume low power since they draw very small amount of current in a steady state. however, the recent revolution in a cmos technology that allows very high gate density has changed the way the power dissipation should be understood. the power dissipation in a cmos circuit is affected by various factors such as the number of gates, a switching frequency, the loading on the output of a gate, and so on. power dissipation is important when designers decide the amount of necessary power supply current for the device to operate in safety. propagation delays and a reliability of the device also depend on the power dissipation which determines the temperature at which the die operates. to obtain a high speed and a reliability, designers must estimate the power dissipation of the device accurately and determine the appropriate environments including packages and system cooling methods. this section describes the concept of two types of power dissipation (static and dynamic) in a cmos circuit, the method of calculating them in the sec STD80/stdm80 library, and ?nally their relationship with a temperature. static (dc) power dissipation there are two types of static or dc current contributing to the total static power dissipation in cmos circuits. one is the leakage current of the gates resulted by a reverse bias between a well and a substrate region. there is no dc current path from power to ground in a cmos because one of the transistor pair is always off, therefore, no static current except the leakage current ?ows through the internal gates of the device. the amount of this leakage current is, however, in the range of tens of nano amperes, which is negligible. the other is dc current that ?ows through the input and output buffers when the circuit is interfaced with other devices, especially ttl. the current of pull-up/pull-down transistor included in the input buffers is about 50 m a typically, which is also negligible. therefore, only dc current that the output buffers source or sink has to be counted to estimate the total static power dissipation. dc power dissipation of ttl output and bi-directional buffers is determined by the following formula: p dc_ttl_ output = ? (v ol x i ol x t l ) + ? ((v dd e v oh ) x i oh x t h ) ,where t h = t high / t, t l + t h = 1. dynamic (ac) power dissipation when a cmos gate changes its state, it draws switching current as a result of charging or discharging of a node capacitance, c l . the energy associated with the switching current for a node capacitance, c l , is 1 / 2 x (c l x v dd 2 ) ,where v dd is a power supply voltage. the switching occurs twice per cycle for periodic signals: once for charging a capacitance and once for discharging it. hence, the dynamic power dissipation due to the switching current is the energy divided by the clock period and multiplied by the factor of two, or c l x v dd x v dd / t ,where t is a clock period. as shown above, it is quite straight forward to calculate the dynamic power dissipation for a single gate. the dynamic power dissipation for an entire chip is, however, much more complicated to estimate since it depends on the degree of switching activity of the circuit. sec has found that the degree of switching activity is 20% on the average and recommends to use this number to estimate the total dynamic power dissipation.
power dissipation introduction to STD80/stdm80 STD80/stdm80 1-8 sec asic power dissipation in STD80/stdm80 this section describes the equations on how to estimate the power dissipation in STD80/stdm80. as explained in the previous section, the total power dissipation (p total ) consists of static power dissipation (p dc ) and dynamic power dissipation (p ac ). p total = p dc + p ac since only output buffers contribute to the static power dissipation, p dc = p dc_output ,where p dc output is the static power dissipated when output buffers source or sink. the dynamic power dissipation is caused by three components: input buffers (p ac_input ), output buffers (p ac_output ), and internal cells (p ac_internal ). p ac = p ac_ input + p ac_output + p ac_internal each term mentioned above is characterized by the following equations: in STD80, p dc_output = 150 x i ol x n_output [ m w] p ac_input = 23 x n_input x f x s [ m w] p ac_output = 25 x n_output x f x s x c [ m w] p ac_internal = 2.3 x n_internal x f x s [ m w] in stdm80, p dc_output = 150 x i ol x n_output [ m w] p ac_input = 9.8 x n_input x f x s [ m w] p ac_output = 25 x n_output x f x s x c [ m w] p ac_internal = 1.2 x n_internal x f x s [ m w] ,where i ol is source and sink current of output buffers in ma, n_output is the number of output buffers used, n_input is the number of input buffers used, n_internal is the number of internal cells used, f is the maximum operation frequency in mhz, s is the estimated degree of a switching activity (typically 0.2), c is the output load capacitance in pf. temperature and power dissipation the total power dissipation, p total can be used to ?nd out the device temperature by the following equation: q ja = (t j e t a ) / p total ,where q ja is the thermal impedance, t j is the junction temperature of the device, t a is the ambient temperature. thermal impedances of the sec packages are given in the following table. the junction temperature, obtained by multiplying p total by the appropriate q ja and adding t a , determines the derating factor for the propagation delays and also indicates the reliability measures. hence, designers can achieve the desired derating factor and reliability targets by choosing appropriate packages and system cooling methods. table 1-1. thermal impedances of sec packages maximum junction temperature (t j ) the allowable maximum junction temperatures for plastic and ceramic packages are as follows: junction temperature for plastic package 125 c junction temperature for ceramic package 150 c. qfp pin number 64 80 100 120 160 208 240 q ja [ c/w] 60 60 60 50 50 40 40
introduction to STD80/stdm80 propagation delays sec asic 1-9 STD80/stdm80 propagation delays interconnection wire length, temperature and supply voltage are the chief factors affecting propagation delays. wire length load the loading due to interconnection wire length can be estimated with the following expression. the result is given in terms of number of equivalent standard loads. c wl = c fo ,where c fo = number of fanouts in a standard load, a = area of block size in mm 2 , c wl = number of equivalent standard loads due to an interconnection, e.g., c fo = 7 (standard load), a = 25mm 2 , c wl = 5.8 (standard load). temperature and supply voltage the next ?gure describes propagation delay correction factors (k t , k v ) as a function of on-chip junction temperature (t j ) as well as supply voltage (v dd ). as a result of increasing cmos power dissipation, ambient and junction temperature are generally not the same. the temperature of the die inside the package (junction temperature, t j ), is calculated using chip power dissipation and the thermal resistance to ambient temperature ( q ja ) of the package. information on package thermal performance can be obtained from sec application engineers. figure 1-8. effect of temperature and supply voltage on propagation delay 0.049 a 0.48 + () 0.079 a 0.33 + + temperature (t j ) k t 1.10 1.08 1.00 0.96 0.90 C40 0 70 25 85 1.18 125 ( c) supply voltage (v dd ) 1.07 1.00 0.94 4.5 5.0 5.5 (volt) k v 1.04 0.97 4.75 5.25 1.19 1.00 3.0 3.6 (volt) k v 1.08 0.94 2.7 3.3 1.12 1.09 1.00 0.95 0.87 1.21 STD80 stdm80 STD80 stdm80
propagation delays introduction to STD80/stdm80 STD80/stdm80 1-10 sec asic best and worst case conditions a circuit should be designed to operate properly within a given speci?cation level, either commercial or industrial. it is recommended that circuits be simulated for best case, normal case, and worst case conditions at each speci?cation level. the following expressions also allow for the effect of process variation on circuit performance. best case: t bc = k pbc x k t x k v x t nom = k bc x t nom worst case: t wc = k pwc x k t x k v x t nom = k wc x t nom ,where t bc = best case propagation delay t wc = worst case propagation delay t nom = normal propagation delay (t j = 25 o c, v dd = 5v and typical process) k pwc = worst case process correction factor k pbc = best case process correction factor with above equations, we can calculate the multipliers of k wc and k bc as follows. table 1-2. STD80 best case delay table 1-3. STD80 worst case delay table 1-4. stdm80 best case delay table 1-5. stdm80 worst case delay derating factors of STD80/stdm80 the multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. nominal data are provided for conditions of v dd = 5v, t a = 25 c and typical process. the derating factors of STD80/stdm80 are as follows. table 1-6. STD80/stdm80 process derating factor table 1-7. STD80 temperature derating factor table 1-8. stdm80 temperature derating factor table 1-9. STD80 voltage derating factor (k v ) table 1-10. stdm80 voltage derating factor (k v ) application best case delay parameter k bc v dd t j proc. industrial 5.5v C40 o c min. 0.51 commercial 5.25v 0 o c min. 0.56 application worst case delay parameter k wc v dd t j proc. industrial 4.5v 125 o c max. 1.77 commercial 4.75v 115 o c max. 1.69 application best case delay parameter k bc v dd t j proc. industrial 3.6v C40 o c min. 0.49 commercial 3.6v 0 o c max. 0.52 application worst case delay parameter k wc v dd t j proc. industrial 2.7v 125 o c max. 1.97 commercial 3.0v 115 o c max. 1.77 process factor (k p ) slow typ. fast 1.40 1.00 0.60 temp. ( o c) 125 85 70 25 0 C40 k t 1.21 1.12 1.09 1.00 0.95 0.87 temp. ( o c) 125 85 70 25 0 C40 k t 1.18 1.10 1.08 1.00 0.96 0.90 voltage (v) 5.5 5.25 5 4.75 4.5 k v 0.94 0.97 1.00 1.04 1.07 voltage (v) 3.6 3.3 3.0 2.7 k v 0.94 1.00 1.08 1.19
introduction to STD80/stdm80 propagation delays sec asic 1-11 STD80/stdm80 timing parameters this section discusses issues involving timing parameters for primitive cells. rise / fall times the de?nition of rise time (t r ) and fall time (t f ) is shown in the following ?gure. figure 1-9. rise and fall times setup / hold times setup time (t su ) is a minimum period in which the input data to a ?ip-?op or a latch must be stable before the active edge of the clock occurs. hold time (t hd ) is a minimum period in which the input data to a ?ip-?op or a latch must remain stable after the active edge of the clock has occurred. the next ?gure shows the relationship between setup and hold times for a standard ?ip-?op triggered on the rising edge of the clock. figure 1-10. setup and hold times minimum pulse widths minimum clock pulse widths (t pwh , t pwl ) are the time intervals during a clock signal is high or low, so that it ensures proper operation of a ?ip-?op or a latch. figure 1-11. minimum pulse width recovery times recovery time (t rc ) is the minimum time after an asynchronous pin is disabled that an active clock edge will propagate data from input to output. if the active edge or clock occurs before the speci?ed recovery time, the input data will not propagate. figure 1-12. recovery time t r t f 10% 90% 90% 10% v dd d ck t su t hd d ck q t pwh d rb ck q t rc
propagation delays introduction to STD80/stdm80 STD80/stdm80 1-12 sec asic propagation delays a delay for a macrocell is considered to be a rising delay (t plh ) if the signal on the output pin is rising. for a rising input and a rising output, the rising delay is the interval between the times the input becomes 50% of supply voltage (v dd ) and the output becomes 50% of v dd . if the input is falling and the output is rising, the rising delay is the interval between the times the input falls to 50% of v dd and the output rises to 50% of v dd . the converse is true for a falling delay (t phl ). figure 1-13. propagation delay proper use of buffers figure 1-14. average gate delay in STD80 shows the average propagation delays of an internal inverter (iv), an 8x inverter (ivd8), a normal clock driver (ck2), and a high clock driver (ck12) in STD80. note that transistors uses in i/o slots are larger and have on channel resistance about one order of magnitude lower than those of the n and p channel transistors in primitive cells. this makes them likely candidates for use as buffers for high fanout signals. for example, ck2 and ck12 buffers require one i/o slot location. both can be used as high fanout internal buffers. figure 1-14. average gate delay in STD80 one caution, emphasized in figure 1-15. use of i/o slot for an internal buffer, shows that if you route to a buffer that uses an i/o slot from an internal element and back into internal logic, the additional wiring needed could increase propagation delays materially. higher drive strength internal cells may be more appropriate than i/o slot buffers. realize also that using i/o slot cells for internal buffering removes those locations for use as external i/os and uses two wiring channels, thereby increasing routability congestion on masterslice products. figure 1-15. use of i/o slot for an internal buffer 50% 50% t plh 50% 50% t plh 50% 50% t phl 50% 50% t phl v dd 1.5 1.0 0.5 0 10 40 80 160 320 fanout [number] iv ivd8 ck2 ck12 average delay [ns] clock driver using i/o slot high fanout long wire
introduction to STD80/stdm80 delay model sec asic 1-13 STD80/stdm80 delay model the asic timing characteristics consist of the following components: ? cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. ? interconnection wire delay across the metal lines. ? timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. ? derating factors for junction temperature, power supply voltage, and process variations. timing model for STD80/stdm80 focuses on how to characterize cell propagation delay time accurately. to accomplish this goal, 2-dimensional table look-up delay model has been adopted. the index variables of this table are input waveform slope and output load capacitance. see the ?gure below. sec asic design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.5 m m cell-based products. figure 1-16. 2-dimensional table delay model the table 1-11. table delay model example shows an example of this model for 2-input nand cell. the data in this table are high-to-low transition delay times from one of the two input pins to output pin. the number of points and values of the index variables can differ for each cell. table 1-11. table delay model example notice that 4-by-4 table is used. delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. this general table delay model provides great ?exibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. the other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. the delay time due to the interconnection wire can be separated into two components. one is the signal propagation delay time across the metal lines. this delay time component is computed through conventional rc analysis based on ? -model. the other is an additional delay on the driving cell due to the wire load. the traditional way to compute this is based on the lumped capacitance model, ignoring wire resistance. for sub-micron technology, this approximation cannot be accepted any more. the wire resistance has a shielding effect on the driving cell from load capacitances. an effective capacitance c eff , a single capacitance approximating distributed interconnection wire resistance and capacitance, is derived, as illustrated in the following tgure. the compensation factor k, extracted for each cell, is a function of the length of interconnection wires and the layout topology. all these effects are merged to determine the effective capacitance and this value is used as an index of the table delay model. figure 1-17. concept of effect capacitance propagation delay [ns] input waveform slope [ns] load cap [pf] 1.5 1.0 0.5 1.0 2.0 3.0 0.4 0.8 1.2 0.03 0.13 0.53 1.32 0.10 0.07 0.14 0.42 0.97 0.30 0.08 0.17 0.45 1.02 0.80 0.06 0.18 0.51 1.07 1.60 0.01 0.18 0.60 1.18 c eff = f (k, cload) cap. slope
testability design methodology introduction to STD80/stdm80 STD80/stdm80 1-14 sec asic the ?gure below summarizes the features of sec asics delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used. the slopes (t r , t f ) and delay times (t plh , t phl ) of all cell instances are calculated recursively. the input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. a pin to pin delays of cells and interconnection wires are supported. ? the effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. figure 1-18. features of delay model testability design methodology scan design ? multiplexed scan ?ip-?op that minimizes the area or delay overhead needed to implement scan design ? automated design rules checking, scan insertion, and test pattern generation ? high fault coverage on synchronous designs boundary-scan ? ieee std 1149.1 ? 5 types of jtag boundary-scan cells ? boundary-scan description language (bsdl) description for board testing ? combination with internal scan design s1 s3 s2 co1 co2 co3 ck q d a_y b_y ? ? a mux scannable register device identity register bypass register instruction register ta p controller system logic tdi tms tck tdo test access port mux boundary scan path
introduction to STD80/stdm80 maximum fanouts sec asic 1-15 STD80/stdm80 maximum fanouts internal macrocells the maximum fanouts for STD80/stdm80 primitive cells are as follows. note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.44ns (STD80)/0.39ns (stdm80). depending on the rise and fall times, the maximum fanout limitations can be varied case by case. in the following table the maximum fanout values for all pins of STD80/stdm80 internal macrocells are listed. table 1-12. maximum fanouts of internal macrocells (when t r /t f = 0.44ns (STD80)/0.39ns (stdm80)) cell name output pin maximum fanout STD80 stdm80 logic cells ad2 y 49 28 ad2d2 y 106 59 ad3 y 49 28 ad3d3 y 161 84 ad4 y 49 28 ad4d2 y 105 58 ad5 y 38 17 ad5d2 y 78 34 nd2 y 45 23 nd2d2 y 95 48 nd3 y 30 15 nd3d2 y 63 30 nd4 y 23 11 nd4d2 y 47 22 nd5 y 18 7 nd5d2 y 36 16 nd6 y 49 28 nd6d2 y 104 55 nd8 y 49 28 nd8d2 y 105 56 nr2 y 40 17 nr2d2 y 87 37 nr3 y 25 11 nr3d2 y 54 23 nr4 y 18 7 nr4d2 y 38 15 nr5 y 49 28 nr5d2 y 104 59 nr6 y 49 28 nr6d2 y 104 58 nr8 y 49 28 nr8d2 y 104 58 or2 y 49 28 or2d2 y 104 55 or3 y 49 26 or3d3 y 147 71 or4 y 43 22 or4d2 y 89 44 or5 y 40 21 or5d2 y 89 45 xn2 y 49 27 xn2d2 y 103 54 xn3 y 47 25 xn3d3 y 134 65 xo2 y 49 28 xo2d2 y 102 55 xo3 y 47 25 xo3d3 y 134 65 ao21 y 30 15 ao21d2 y 64 31 ao211 y 22 9 ao211d2 y 44 18 ao22 y 28 13 ao22d2 y 57 27 ao22a y 27 13 ao22d2a y 55 27 ao222 y 21 8 ao222d2 y 105 59 ao222a y 26 10 ao222d2a y 52 21 ao33 y 18 7 ao33d2 y 106 58 ao333 y 15 4 ao333d2 y 107 60 oa21 y 29 15 oa21d2 y 61 31 oa211 y 20 9 oa211d2 y 40 19 oa22 y 28 14 oa22d2 y 59 29 cell name output pin maximum fanout STD80 stdm80
maximum fanouts introduction to STD80/stdm80 STD80/stdm80 1-16 sec asic oa22a y 29 15 oa22d2a y 59 31 oa2222 y 49 28 oa2222d2 y 104 55 dl1d2 y 105 60 dl1d4 y 222 113 dl2d2 y 108 60 dl2d4 y 219 114 dl3d2 y 109 61 dl3d4 y 226 111 dl4d2 y 110 61 dl4d4 y 228 110 dl5d2 y 110 60 dl5d4 y 228 109 dl10d2 y 105 53 dl10d4 y 207 97 iv y 53 29 ivd2 y 114 65 ivd3 y 175 101 ivd4 y 231 144 ivd6 y 324 190 ivd8 y 403 234 iva y 53 29 ivd2a y 114 65 ivd3a y 175 101 ivd4a y 231 144 ivcd11 y 51 27 yn 53 29 ivcd13 y 47 24 yn 175 100 ivcd22 y 117 62 yn 114 65 ivcd26 y 101 53 yn 324 190 ivcd44 y 259 162 yn 231 144 ivt y 43 23 ivtd2 y 93 48 ivtd4 y 177 90 ivtd8 y 323 179 ivtn y 43 22 ivtnd2 y 87 46 ivtnd4 y 173 85 cell name output pin maximum fanout STD80 stdm80 ivtnd8 y 336 158 nid y 49 28 nid2 y 106 59 nid3 y 161 90 nid4 y 222 121 nid6 y 331 163 nid8 y 438 209 nit y 43 23 nitd2 y 91 47 nitd4 y 180 96 nitd8 y 323 203 nitn y 43 23 nitnd2 y 88 46 nitnd4 y 176 88 nitnd8 y 324 158 flip-flops fd1 all pins 49 28 fd1d2 q 105 58 qn 107 60 fd1cs q 49 28 qn 49 27 fd1csd2 q 105 58 qn 104 55 fd1s all pins 49 28 fd1sd2 q 105 58 qn 106 60 fd1q q 49 28 fd1qd2 q 107 59 fd1x2 all pins 49 28 fd1x4 all pins 49 28 yfd1 q 49 26 qn 43 24 yfd1d2 q 105 53 qn 90 49 fd2 all pins 49 28 fd2d2 q 106 58 qn 109 60 fd2cs all pins 49 27 fd2csd2 q 105 58 qn 106 55 fd2s all pins 49 28 fd2sd2 q 106 58 qn 108 60 cell name output pin maximum fanout STD80 stdm80
introduction to STD80/stdm80 maximum fanouts sec asic 1-17 STD80/stdm80 fd2q q 49 28 fd2qd2 q 107 58 fd2x2 all pins 49 28 fd2x4 all pins 49 28 yfd2 q 48 26 qn 40 21 yfd2d2 q 103 51 qn 80 42 fd2t q 49 27 z2815 fd2td2 q 106 58 z5226 fd2tcs q 48 27 z2812 fd2tcsd2 q 104 57 z5226 fd2ts q 49 27 z2812 fd2tsd2 q 106 58 z5226 fd3 all pins 49 28 fd3d2 q 107 58 qn 107 59 fd3cs q 49 28 qn 49 27 fd3csd2 q 106 59 qn 105 55 fd3s all pins 49 28 fd3sd2 q 106 59 qn 106 58 fd3q q 49 28 fd3qd2 q 106 59 fd3x2 all pins 49 28 fd3x4 all pins 49 28 yfd3 q 43 22 qn 43 24 yfd3d2 q 89 42 qn 89 49 fd4 q 49 27 qn 49 28 fd4d2 all pins 106 58 fd4cs all pins 49 27 cell name output pin maximum fanout STD80 stdm80 fd4csd2 q 106 58 qn 106 55 fd4s all pins 49 28 fd4sd2 all pins 106 58 fd4q q 49 28 fd4qd2 q 106 59 fd4x2 all pins 49 28 fd4x4 qn 49 27 qnn 49 28 yfd4 q 43 22 qn 39 20 yfd4d2 q 88 41 qn 80 42 fd5 all pins 49 28 fd5d2 q 105 60 qn 106 59 fd5s all pins 49 28 fd5sd2 q 105 58 qn 106 59 fd5x4 all pins 49 28 fd6 all pins 49 28 fd6d2 q 105 58 qn 106 61 fd6s all pins 49 28 fd6sd2 q 106 58 qn 108 60 fd7 all pins 49 28 fd7d2 q 106 59 qn 106 58 fd7s all pins 49 28 fd7sd2 all pins 106 58 fd8 q 49 27 qn 49 28 fd8d2 q 106 58 qn 105 58 fd8s all pins 49 28 fd8sd2 q 106 59 qn 106 58 fds2 all pins 59 28 fds2d2 q 105 58 qn 106 60 fds2cs q 49 28 qn 49 27 cell name output pin maximum fanout STD80 stdm80
maximum fanouts introduction to STD80/stdm80 STD80/stdm80 1-18 sec asic fds2csd2 q 105 58 qn 105 55 fds2s all pins 49 28 fds2sd2 q 106 60 qn 105 59 fds3 all pins 49 28 fds3d2 q 106 60 qn 105 59 fg1 all pins 49 28 fg1x4 all pins 49 28 fg2 all pins 49 28 fg2x4 all pins 49 28 fj1 all pins 49 28 fj1d2 q 105 56 fj1d2 qn 104 58 fj1s q 50 28 qn 49 28 fj1sd2 q 105 56 qn 107 59 fj2 q 50 28 qn 49 28 fj2d2 q 105 57 qn 106 59 fj2s q 50 28 qn 49 28 fj2sd2 q 106 56 qn 109 61 fj4 q 50 28 qn 49 27 fj4d2 q 105 56 qn 106 58 fj4s q 50 28 qn 49 28 fj4sd2 q 106 56 qn 106 58 ft2 all pins 49 28 ft2d2 q 106 57 qn 108 60 ft3 all pins 49 28 ft3d2 q 107 59 qn 106 58 latches ld1 all pins 49 28 cell name output pin maximum fanout STD80 stdm80 ld1d2 q 106 60 qn 105 58 ld1s all pins 49 28 ld1sd2 q 106 60 qn 106 58 ld1q q 49 28 ld1qd2 q 104 59 ld1x4 all pins 49 28 ld1x4d2 qn 106 59 qnn 106 58 yld1 q 43 24 qn 51 28 yld1d2 q 89 50 qn 114 61 ld1a q 43 23 ld1b qn 15 5 zn 43 23 ld2 all pins 49 28 ld2d2 q 105 58 qn 108 60 ld2q q 49 28 ld2qd2 q 107 59 yld2 q 42 22 qn 44 22 yld2d2 q 44 23 qn 96 47 ld3 all pins 49 28 ld3d2 q 108 60 qn 106 58 ld4 q 49 28 qn 49 27 ld4d2 q 107 58 qn 105 58 ld5 all pins 49 28 ld5d2 q 106 59 qn 105 58 ld5s all pins 49 28 ld5sd2 q 106 59 qn 105 58 ld5x4 all pins 49 28 ld5x4d2 qn 106 59 qnn 106 58 ld6 all pins 49 28 cell name output pin maximum fanout STD80 stdm80
introduction to STD80/stdm80 maximum fanouts sec asic 1-19 STD80/stdm80 ld6d2 q 106 58 qn 108 60 ld7 all pins 49 28 ld7d2 q 108 60 qn 106 58 ld8 q 49 28 qn 49 27 ld8d2 q 107 58 qn 105 58 lds2 all pins 49 28 lds6 all pins 49 28 ls0 all pins 39 20 ls0d2 all pins 78 40 ls1 all pins 18 8 ls2 all pins 39 20 bus holder busholder y 10,000 10,000 internal clock drivers ck2 y fig 1-19 (a) fig 1-20 (a) ck4 y fig 1-19 (b) fig 1-20 (b) ck6 y C fig 1-20 (c) ck8 y fig 1-19 (c) fig 1-20 (d) ck12 y fig 1-19 (d) C decoders dc4 all pins 49 28 dc4i yn(0/2) 43 23 yn(1/3) 45 23 dc8i all pins 30 15 adders fa s 49 28 co 49 27 fad2 s 103 55 co 103 54 ha s 49 27 co 49 28 had2 s 103 54 co 106 59 multiplexers mx2 y 49 28 mx2d3 y 152 76 mx2x4 all pins 49 28 ymx2 y 49 28 ymx2d2 y 102 59 cell name output pin maximum fanout STD80 stdm80 mx2i yn 28 13 mx2id2 yn 104 59 mx2ia yn 28 13 mx2id2a yn 104 59 mx2ix4 all pins 28 13 mx3i yn 49 28 mx3id2 yn 104 59 mx4 y 48 26 mx4d2 y 96 48 ymx4 y 49 27 ymx4d2 y 102 33 mx5 y 49 27 mx5d2 y 102 55 mx8 y 45 22 mx8d2 y 86 41 ymx8 y 49 27 ymx8d2 y 102 53 cell name output pin maximum fanout STD80 stdm80
maximum fanouts introduction to STD80/stdm80 STD80/stdm80 1-20 sec asic i/o cells the maximum fanouts for 5v and 3.3v i/o cells are as follows when the rise and fall times of the input signal is 0.40ns. the graphs for fanout vs. frequency curve of STD80/stdm80 internal/input clock drivers are shown in the next page. table 1-13. maximum fanouts of i/o cells (when t r /t f = 0.40ns) cell name output pin maximum fanouts STD80 stdm80 pic po 91 42 y 231 137 picd po 92 42 y 237 141 picu po 91 42 y 240 130 pil pild po 91 C y 277 C pilu po 91 C y 281 C pis po 91 42 y 182 181 pisd po 91 42 y 179 150 pisu po 91 42 y 179 206 pitb po 91 C y 180 C plic po 69 C y 293 C plicd po 69 C y 317 C plicu po 69 C y 302 C plis po 69 C y 348 C plisd po 69 C y 361 C plisu po 69 C y 246 C phic po C 34 y C 141 phicd po C 34 y C 143 phicu po C 34 y C 137 phil po C 34 y C 136 phild po C 34 y C 156 philu po C 34 y C 135 phis po C 34 y C 131 phisd po C 34 y C 144 phisu po C 34 y C 145 phit phitd po C 34 y C 144 phitu po C 34 y C 148 psckdab2 y fig 1-19 (a) fig 1-20 (a) psckdab4 y fig 1-19 (b) fig 1-20 (b) psckdab6 y C fig 1-20 (c) psckdab8 y fig 1-19 (c) fig 1-20 (d) psckdab12 y fig 1-19 (d) C psosck1 psosck16 pa dy 9 6 yn 36 25 psosck2 psosck26 pady 94 62 yn 319 225 psoscm1 psoscm16 pady 1097 778 yn 888 633 psoscm2 psoscm26 pady 1097 778 yn 888 633 psoscm3 psoscm36 pady 2194 1548 yn 1596 1136 psoscm4 psoscm46 pady 4356 3010 yn 2389 1699 psoscm5 psoscm56 pady 6592 4508 yn 1257 894 psoscm6 psoscm66 pady 8923 6054 yn 4750 3369 cell name output pin maximum fanouts STD80 stdm80
introduction to STD80/stdm80 maximum fanouts sec asic 1-21 STD80/stdm80 figure 1-19. fanout (sl) vs. frequency curve of STD80 clock drivers figure 1-20. fanout (sl) vs. frequency curve of stdm80 clock drivers (a) psckdab2 ck2 (b) psckdab4 ck4 (c) psckdab8 ck8 (d) psckdab12 ck12 (a) psckdab2 ck2 (b) psckdab4 ck4 (c) psckdab6 ck6 (d) psckdab8 ck8
product line-up introduction to STD80/stdm80 STD80/stdm80 1-22 sec asic product line-up table 1-14. optimum gates vs. pad numbers on STD80/stdm80 note : chip size can be changed depending on the circuit design. packages note : the selection of a package type and pin count is dependent on the size of a chip. ref. no estimated gates total pads maximum i/o pads tlm (70%) dlm (40%) tlm dlm 01 10,000 57 75 41 59 02 15,000 70 93 54 77 03 20,000 81 107 65 91 04 30,000 99 131 83 115 05 40,000 114 151 98 135 06 50,000 128 169 112 153 07 60,000 140 186 124 170 08 70,000 151 201 135 185 09 80,000 162 214 146 198 10 90,000 172 227 156 211 11 100,000 181 240 175 224 12 120,000 198 263 182 247 13 140,000 214 284 198 268 14 160,000 229 303 213 287 15 180,000 243 322 227 306 16 200,000 256 339 240 323 17 250,000 287 379 271 363 18 300,000 314 416 298 400 19 350,000 339 449 323 433 20 400,000 363 480 347 464 21 450,000 385 509 369 493 22 500,000 406 537 390 521 type dip sdip sop plcc qfp pin count 24 28 40 42 24 28 30 32 40 42 48 54 56 64 28 32 28 32 44 68 84 44 48 60 64 80 100 128 132 160 208 240
introduction to STD80/stdm80 dedicated corner vdd/vss pads sec asic 1-23 STD80/stdm80 dedicated corner v dd /v ss pads the corner pads shown in the following ?gure are well-suited for double bonding purposes. pad 1 and pad 2 can be bonded to the same package pin. unlike normal i/o pads, these pads can only be used for v dd /v ss listed in table 1-15. use of corner pads. figure 1-21. v dd /v ss corner pads notes: 1. there is no dedicated corner vssi pad. therefore, internal v ss must be supplied using i/o pad type cell. 2. corner pads are used to reduce the power/ground noise when some parts of the design cause noise problem especially while the other parts keep quiet. table 1-15. use of corner pads external design interface considerations this section brie?y describes what you should consider when chips interface with outside world especially for a noise protection. input buffer figure 1-22. effect of schmitt trigger input buffer 1 vsso 9 vdd3o 2 vsso 10 vdd3o 3 vssi 11 vssi 4 vssi 12 vssi 5 vddi 13 vddi 6 vddi 14 vddi 7 vdd5o 15 vsso 8 vdd5o 16 vsso 1 2 3 4 8 7 6 5 9 10 11 12 16 15 14 13 (a) input signal with heavy noise (b) after ttl input buffer of which logic (c) after schmitt trigger of which positive- and v t v t v t vin vout vin vout vt+ vtC vt unwanted signal caused by noise noise spike noise spike threshold is vt negative-going threshold voltages are vt+ and vtC
external design interface considerations introduction to STD80/stdm80 STD80/stdm80 1-24 sec asic usually there are three types of input receivers in asic libraries; ttl input buffer, cmos input buffer, and various schmitt trigger input buffers. ttl input buffer has relatively poor noise characteristics because of its shifted logic threshold voltage. cmos input buffer is better than ttl against a noise because the logic threshold voltage is near 2.5volt. if an input signal has relatively large noise spikes, it could cause an unwanted input signal. when an input signal is very noisy, the noise can be ?ltered by using a schmitt trigger input buffer. as shown in figure 1-22. effect of schmitt trigger input buffer, schmitt trigger input buffers have two different input thresholds for positive- and negative-going signals. this hysteresis between positive- and negative-going voltage signals can ?lter a noisy signal to a wanted one. according to applications, the most suitable one can be chosen among the various schmitt trigger input buffers having different levels of threshold voltage. output pad cell as incoming signals to a chip have a noise, the noise can also be induced by the operation of the chip itself. there are several sources of a noise, but the greatest singular source of a noise is the switching of an output with high capacitive load. figure 1-23. simple model of output pad cell figure 1-23. simple model of output pad cell shows the simple model of an output driver considering the external interface. l1 and l2 are parasitic inductances of the package and c l is an output load. vout will fall as vin rises and the current i ?ows through n-transistor discharging the loaded charge (v dd c l ). the details of this operations are described in figure 1-24. ground bounce phenomenon. the important phenomenon which can be observed in this tgure is that the voltage level vn shifts relative to the system ground. vn is the ground of the chip. this phenomenon is called as a ground bounce that is the chip reference shift caused by the external inductance and the transient current ?ow to the ground. the amount of voltage level shifted by the ground bounce is vn = -l (di / dt) when the output driver makes a low-to-high transition, the similar noise problem is generated on the power. figure 1-24. ground bounce phenomenon i c l : bonding pad l2 l1 vin system ground system power supply vout r l (a) vin (b) vout (c) i (d) vn t t t t i = C c l (dvout / dt) vn = l1 (di / dt)
introduction to STD80/stdm80 external design interface considerations sec asic 1-25 STD80/stdm80 the following graphs show typical ac characteristics of non-slew and slew-rate output drives in STD80/stdm80. using the slew-rate control, you can reduce the switching noise. figure 1-25. ac characteristics of non-slew and slew rate output drives ground bouncing voltage vs. time 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -13.81m 0.000 12.50m 25.00m 37.50m 50.00m 62.50m 75.00m 86.43m pob8 pob8sm 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n -36.43m -25.00m 0.000 25.00m 50.00m 75.00m 100.0m 125.0m 140.7m pob12 pob12sm pob12sh 1 w input v dd 2nh 1 w 2nh pa d 2nh 1 w < test condition >
external design interface considerations introduction to STD80/stdm80 STD80/stdm80 1-26 sec asic ground bouncing voltage vs. time 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -88.49m -50.00m 0.000 50.00m 100.0m 150.0m 200.0m 220.4m pob16 pob16sm pob16sh 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n -225.7m -100.0m 0.000 100.0m 200.0m 300.0m 370.7m pob24 pob24sm pob24sh 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n -168.0m -100.0m -50.00m -7.451n 50.00m 100.0m 150.0m 200.0m 250.0m 317.2m pob20 pob20sm pob20sh
introduction to STD80/stdm80 external design interface considerations sec asic 1-27 STD80/stdm80 simultaneous switching outputs (ssos) if several output drivers switch from high to low simultaneously, the ground bouncing level becomes quite large because the current ?owing through the inductance l is the total sum of the transient current of each output driver. the amount of total current and the level of ground bounce are proportional to the number of ssos. this ground bounce can cause two types of problems, a noise margin reduction and a generation of noise spike on the output pad. noise margin reduction the ground bounce can cause a noise margin reduction when the same ground bus is used for both input buffers and output drivers as shown in figure 1-27. the figure of ssos. the noise margin reduction can be explained using the circuit in the same ?gure. as you can see, if outputs switch from high to low simultaneously, it results in a ground bounce or the rise of the chip ground level relative to system ground. the rise appears as the input voltage vin_a is below v ih causing false triggering of the input buffer. vin is, in this case, not the same as vin_a. note that vin is measured relative to the system ground, while vin_a is measured relative to the local device ground. this phenomenon is shown in figure 1-26. noise margin reduction due to ssos. for a low-to-high transition, it is the low input levels (v il ) that are affected. figure 1-26. noise margin reduction due to ssos noise spike generation on stable output if input and output power buses are separated, the problem of a noise margin reduction in the input buffer can be solved. however, ground bounce can cause another problem in spite of using separated power and ground bus. the figure 1-28. noise spike induced by ground bounce shows a common octal driver application where ground bounce spikes will be observable on the one stable output. if the spike is considered as high by another chip, this ground bounce may upset that operation of interfacing device or cause system logic errors. vin_a v ih v il v ss 2.0v 0.8v figure 1-27. the figure of ssos i c l i c l i c l i c l nxi vin vin_a system ground input receiver ssos chip ground (vn) chip power internal logic
external design interface considerations introduction to STD80/stdm80 STD80/stdm80 1-28 sec asic for example, suppose c l = 100pf, v dd = 3.3volt, t f = 5ns. from figure 1-24. ground bounce phenomenon, the maximum current ?ow occurs at time 0.5 t f . then approximately, i = c l (dv / dt) @ c l ( d v / d t), and i (max) = 100 10 -12 {5 / (2.5 10 -9 )} = 200 [ma]. if the number of ssos is 5, and l is 4nh, vn = l (di / dt) n @ l ( d i / d t) n by approximation, vn (max) = 4 10 -9 {0.200 / (2.5 10 -9 )} 5 = 1.60 [volt]. from this calculation, 1.60v of noise spike is expected. this is about logic threshold voltage of ttl. this numerical estimate clearly shows that power bus noise control is one of the fundamental problems in a high-speed cmos vlsi design. it is an important design consideration to prevent the noise from affecting the integrity of the logic operation of a chip. figure 1-28. noise spike induced by ground bounce how to protect ground bounce? the fundamental solution to the ground bounce problem is to reduce the inductance of the package. however, in the boundary of a given packaging technology, the following guidelines can be used for reducing ground bounce: (1) if possible, use separate power and ground buses for input buffers and output drivers. (2) the number of ground and power pads should not be less than the required number of pads. (3) if the design is not so much sensitive to speed, use slew rate control, i.e., increase switching time, to reduce the value of di / dt of an output driver. sec supports two levels of slew rate controlled output buffers, sm and sh. you can see this effect in the following ?gure. figure 1-29. effect on reducing peak current with slew-rate control (4) if you cannot use a slew rate cell because of the speed requirement, you can stagger the output driver as shown in figure 1-30. effect on reducing peak current with staggering output drivers. this is not a general-purpose solution. it makes sense only when special relief in timing requirements exists from a system architecture. noise spike l i t t t t 3 ssos 3 ssos v i v i
introduction to STD80/stdm80 crystal oscillator considerations sec asic 1-29 STD80/stdm80 figure 1-30. effect on reducing peak current with staggering output drivers (5) high-drive outputs should be close to v ss pins. ssos should be placed particularly close to v ss pins. (6) ssos should be appropriately placed in groups belonging to given v ss pins. (7) noise-sensitive signals such as clock, asynchronous clear and preset should be located away from ssos and high-drive outputs. also, assign them to pins with low inductance and resistance, preferably near v ss , if one is available away from ssos or high-drive outputs. (8) place ssos on low inductance pins, such as those located on the inner rows or middle positions of pgas. (9) clock, preset and clear inputs must not be placed on the corners of a package, especially when the array is packaged in dip. (10)output signals to be used as clock, preset or clear for other devices must be kept away from ssos and close to v ss pin. these guidelines assist you in choosing the best package(s) for the application. furthermore, the recommendations about pinout results in reliable and predictable devices that minimizes harmful dc and ac effects on the system. crystal oscillator considerations overview STD80/stdm80 contains a circuit commonly referred to as an on-chip oscillator. the on-chip circuit itself is not an oscillator but an ampli?er which is suitable for being used as the ampli?er part of a feedback oscillator. with proper selection of off-chip components, this oscillator circuit performs better than any other types of clock oscillators. it is very important to select suitable off-chip components to work with the on-chip oscillator circuitry. it should be noted, however, that sec cannot assume the responsibility of writing speci?cations for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of the ?nished design in production, anymore than a transistor manufacturer, whose data sheets show a number of suggested ampli?er circuits, can assume responsibility for the operation, in production, of any of them. we are often asked why we dont publish a list of required crystal or ceramic resonator speci?cations, and recommend values for the other off-chip components. this has been done in the past, but sometimes with consequences that were not intended. suppose we suggest a maximum crystal resistance of 30ohms for some given frequency. then your crystal supplier tells you the 30ohm crystals are going to cost twice as much as 50ohm crystals. fearing that sec will not guarantee operation with 50ohm crystals, you order the expensive ones. in fact, sec guarantees only what is embodied within an sec product. besides, there is no reason why 50ohm crystals couldnt be used, if the other off-chip components are suitably adjusted. should we recommend values for the other off-chip components? should we do for 50ohm crystals or 30ohm crystals? with respect to what should we optimize their selection? should we minimize start-up time or maximize frequency stability? in many applications, neither start-up time nor frequency stability is particularly critical, and our recommendations are only restricting your system to unnecessary tolerances. it all depends on the application. t t t t 3 ssos v i v i
crystal oscillator considerations introduction to STD80/stdm80 STD80/stdm80 1-30 sec asic oscillator design considerations asic designers have a number of options for clocking the system. the main decision is whether to use the on-chip oscillator or an external oscillator. if the choice is to use the on-chip oscillator, what kinds of external components are to use an external oscillator, what type of oscillator would it be? the decisions have to be based on both economic and technical requirements. in this section we will discuss some of the factors that should be considered. on-chip oscillator in most cases, the on-chip ampli?er with the appropriate external components provides the most economical solution to the clocking problem. exceptions may arise in server environments when frequency tolerances are tighter than about 0.01%. the external components that commonly used for cmos gate oscillator are a positive reactance (normal crystal oscillator), two capacitors, c1 and c2, and two resistor rf and rx as shown in the ?gure below. figure 1-31. cmos oscillator crystal specifications speci?cations for an appropriate crystal are not very critical, unless the frequency is. any fundamental-mode crystal of medium or better quality can be used. we are often asked what maximum crystal resistance should be speci?ed. the best answer to that question is the lower the better, but use what is available. the crystal resistance will have some effect on start-up time and steady-state amplitude, but not so much that it cant be compensated for by appropriate selection of the capacitances, c1 and c2. similar questions are asked about speci?cations of load capacitance and shunt capacitance. the best advice we can give is to understand what these parameters mean and how they affect the operation of the circuit (that being the purpose of this application note), and then to decide for yourself if such speci?cations are meaningful in your frequency tolerances are tighter than about 0.1%. part of the problem is that crystal manufacturers are accustomed to talking ppm tolerances with radio engineers and simply wont take your order until youve ?lled out their list of frequency tolerance requirements, both for yourself and to the crystal manufacturer. dont pay for 0.003% crystals if your actual frequency tolerance is 1%. oscillation frequency the oscillation frequency is determined 99.5% by the crystal and up to about 0.5% by the circuit external to the crystal. the on-chip ampli?er has little effect on the frequency, which is as it should be, since the ampli?er parameterizes temperature and process dependent. the in?uence of the on-chip ampli?er on the frequency is by means of its input and output (pin-to-ground) capacitances, which parallel c1 and c2, and the pada-to-pady (pin-to-pin) capacitance, which parallels the crystal. the input and pin-to-pin capacitances are about 7pf each. internal phase deviations capacitance of 25 to 30pf. these deviations from the ideal have less effect in the positive reactance oscillator (with the inverting ampli?er) than in a comparable series resonant oscillator (with the non-inverting ampli?er) for two reasons: ?rst, the effect of the output capacitor; second, the positive reactance oscillator is less sensitive, frequency-wise, to such phase errors. c1 c2 rx rf pada pady feedback inside of a chip amplifier
introduction to STD80/stdm80 crystal oscillator considerations sec asic 1-31 STD80/stdm80 c1 / c2 selection optimal values for the capacitors c1 and c2 depend on whether a quartz crystal or ceramic resonator is being used, and also on application-speci?c requirements on start-up time and frequency tolerance. start-up time is sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements. less commonly, accuracy of the oscillator frequency is also critical, for example, when the oscillator is being used as a time base. as a general rule, fast start-up and stable frequency tend to pull the oscillator design in opposite directions. considerations of both start-up time and frequency stability over temperature suggest that c1 and c2 should be about equal and at least 20pf. (but they dont have to be either.) increasing the value of these capacitances above some 40 or 50pf improves frequency stability. it also tends to increase the start-up time. these is a maximum value (several hundred ph, depending on the value of r1 of the quartz or ceramic resonator) above which the oscillator wont start up at all. if the on-chip ampli?er is a simple inverter, the user can select values for c1 and c2 between some 20 and 100pf, depending on whether start-up time or frequency stability is the more critical parameter in a speci?c application. rf / rx selection a cmos inverter might work better in this application since a large rf (1mega-ohm) can be used to hold the inverter in its linear region. logic gates tend to have a fairly low output resistance, which testabilizes the oscillator. for that reason a resistor rx (several k-ohm) is often added to the feedback network, as shown in figure 1-31. cmos oscillator. at higher frequencies a 20 or 30pf capacitor is sometimes used in the rx position, to compensate for some of the internal propagation delay. pin capacitance internal pin-to-ground and pin-to-pin capacitances, and pada and pady have some effect on the oscillator. these capacitances are normally taken to be in the range of 5 to 10pf, but they are extremely dif?cult to evaluate. any measurement of one such capacitance necessarily include effects from the others. one advantage of the positive reactance oscillator is that the pin-to ground cap. is paralleled by an external bulk capacitance, so a precise determination of their value is unnecessary. we would suggest that there is little justi?cation for more precision than to assign them a value of 7pf (pada-to-ground and pada-to-pady). this value is probably not in error by more than 3 or 4pf. the pady-to-ground cap. is not entirely a pin capacitance, but more like an equivalent output capacitance of some 25 to 30pf, having to include the effect of internal phase delays. this value varies to some extent with temperature, process, and frequency. placement of components noise glitches arising at pada or pady pins at the wrong time can cause a miscount in the internal clock-generating circuitry. these kinds of glitches can be produced through capacitive coupling between the oscillator components and pcb traces carrying digital signals with fast rise and fall times. for this reason, the oscillator components should be mounted close to the chip and have short, direct traces to the pada, pady, and v ss pins. if possible, use dedicated v ss and v dd pin for only crystal feedback ampli?er.
crystal oscillator considerations introduction to STD80/stdm80 STD80/stdm80 1-32 sec asic troubleshooting oscillator problems the ?rst thing to consider in case of dif?culty is that there may be signi?cant differences in stray caps between the test jig and the actual application, particularly if the actual application is on a multi-layer board. noise glitches, that are not present in the test jig but are in the application board, are another possibility. capacitive coupling between the oscillator circuitry and other signal has already been mentioned as a source of miscounts in the internal clocking circuitry. inductive coupling is also doubtful, if there is strong current nearby. these problems are a function of the pcb layout. surrounding oscillator components with quit traces (for example, vcc and ground) will alleviate capacitive coupling to signals having fast transition time. to minimize inductive coupling, the pcb layout should minimize the areas of the loops formed by oscillator components. the loops demanding to be checked are as follows: pada through the resonator to pady; pada through c1 to the v ss pin; pady through c2 to the v ss pin. it is not unusual to ?nd that the ground ends of c1 and c2 eventually connect up to the v ss pin only after looping around the farthest ends of the board. not good. finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting oscillator or incorrect frequency. never underestimate the perversity of a software problem.
electrical characteristics output drive capabilities sec asic 2-5 STD80/stdm80 output drive capabilities iv characteristics v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process 0.0 vout [v] 1.0 2.0 3.0 4.0 5.0 ioh [ma] 0.0 25 50 75 100 125 150 157 pob1 pob2 pob4 pob8 pob12 pob16 pob20 pob24 p-tr characteristics 0.0 vout [v] 1.0 2.0 3.0 4.0 5.0 iol [ma] 0.0 25 50 75 100 125 150 175 185 pob1 pob2 pob4 pob8 pob12 pob16 pob20 pob24 n-tr characteristics 0.0 vout [v] 1.0 2.0 3.0 3.3 ioh [ma] 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 75.8 plob1 plob2 plob4 plob6 plob8 plob12 plob16 p-tr characteristics 0.0 vout [v] 1.0 2.0 3.0 3.3 iol [ma] 0.0 12.5 25.0 37.5 50.0 62.5 75.0 87.5 100 109 plob1 plob2 plob4 plob6 plob8 plob12 plob16 n-tr characteristics
input buffer dc curves electrical characteristics STD80/stdm80 2-4 sec asic input buffer pull-down/pull-up characteristics v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 ids [ua] 0.0 10.0 20.0 30.0 40.0 51.1 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 ids [ua] 0.0 10.0 20.0 30.0 40.0 50.1 pull-down pull-up 0.0 vin [v] 1.0 2.0 3.0 3.3 ids [ua] 0.0 2.5 5.0 7.5 10.0 12.5 15.0 18.1 0.0 vin [v] 1.0 2.0 3.0 3.3 ids [ua] 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 19.0 pull-down pull-up
electrical characteristics input buffer dc curves sec asic 2-3 STD80/stdm80 input buffer dc curves input buffer transfer curves v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process input clock drivers transfer curves v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 cmos 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 ttl 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 cmos schmitt trigger 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 ttl schmitt trigger cmos cmos schmitt trigger 0.0 vin [v] 1.0 2.0 3.0 3.3 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 3.300 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 cmos ttl cmos schmitt trigger ttl schmitt trigger cmos cmos schmitt trigger 0.0 vin [v] 0.5 1.0 1.5 2.0 2.5 3.0 3.3 vout [v] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 0.0 vin [v] 0.5 1.0 1.5 2.0 2.5 3.0 3.3 vout [v] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3
dc electrical characteristics electrical characteristics STD80/stdm80 2-2 sec asic v dd = 3.3v 10%, t a = 0 to 70 c symbol parameter condition min max unit v ih high level input voltage v cmos interface 0.7v dd cmos schmitt trigger 2.1 v il low level input voltage v cmos interface 0.3v dd cmos schmitt trigger 0.8 i ih high level input current m a input buffer v in = v dd e10 10 input buffer with pull-down 10 200 i il low level input current m a input buffer v in = v ss e10 10 input buffer with pull-up e200 e10 v oh high level output voltage v type b1 to b16 i oh = e1 m av dd e 0.05 type b1 i oh = e0.5ma 2.4 type b2 i oh = e1ma type b4 i oh = e2ma type b6 i oh = e3ma type b8 i oh = e4ma type b10 i oh = e5ma type b12 i oh = e6ma type b16 i oh = e8ma v ol low level output voltage v type b1 to b16 i ol = 1 m a 0.05 type b1 i ol = 1ma 0.4 type b2 i ol = 2ma type b4 i ol = 4ma type b6 i ol = 6ma type b8 i ol = 8ma type b10 i ol = 10ma type b12 i ol = 12ma type b16 i ol = 16ma absolute maximum ratings recommended operating conditions symbol parameter ratingtd unit v dd dc supply voltage C0.3 to 7 v v in dc input voltage C0.3 to v dd + 0.3 i in dc input current 10 ma t stg storage temperature e40 to 125 c symbol parameter rating unit v dd dc supply voltage 5v 4.75 to 5.25 v 3.3v 3.0 to 3.6 t a commercial temperature 0 to 70 c industrial temperature e40 to 85
electrical characteristics dc electrical characteristics sec asic 2-1 STD80/stdm80 dc electrical characteristics v dd = 5v 5%, t a = 0 to 70 c notes: 1. type b1 means 1ma output driver cells, and type b24 means 24ma output driver cells. 2. this value depends on the customer design. symbol parameter condition min max unit v ih high level input voltage v ttl interface 2.0 ttl schmitt trigger 2.1 cmos interface 0.7v dd cmos schmitt trigger 4.0 v il low level input voltage v ttl interface 0.8 ttl schmitt trigger 0.8 cmos interface 0.3v dd cmos schmitt trigger 1.0 i ih high level input current m a input buffer v in = v dd e10 10 input buffer with pull-down 10 200 i il low level input current m a input buffer v in = v ss e10 10 input buffer with pull-up e200 e10 v oh high level output voltage v type b1 to b24 note1 i oh = e1 m av dd e 0.05 type b1 i oh = e1ma 2.4 type b2 i oh = e2ma type b4 i oh = e4ma type b8 i oh = e8ma type b12 i oh = e12ma type b16 i oh = e16ma type b20 i oh = e20ma type b24 i oh = e24ma v ol low level output voltage v type b1 to b24 i ol = 1 m a 0.05 type b1 i ol = 1ma 0.4 type b2 i ol = 2ma type b4 i ol = 4ma type b8 i ol = 8ma type b12 i ol = 12ma type b16 i ol = 16ma type b20 i ol = 20ma type b24 i ol = 24ma i oz tri-state output leakage current v out =v ss or v dd e10 10 m a i dd quiescent supply current v in = v ss or v dd 100 note2 m a
contents dc electrical characteristics ......................................................................................... 2-1 input buffer dc curves.................................................................................................. 2-3 output drive capabilities ............................................................................................... 2-5
electrical characteristics 2
internal macrocells 3
contents overview ............................................................................................................................ 3-1 summary tables................................................................................................................. 3-2 logic cells.......................................................................................................................... 3-7 flip-flops............................................................................................................................ 3-169 latches............................................................................................................................... 3-358 bus holder.......................................................................................................................... 3-458 internal clock drivers ......................................................................................................... 3-459 decoders ............................................................................................................................ 3-462 adders ................................................................................................................................ 3-476 multiplexers ........................................................................................................................ 3-485
internal macrocells overview sec asic 3-1 STD80/stdm80 overview the third chapter contains data sheets of logic cells, ?ip-?ops, latches, bus holder, internal clock drivers, decoders, adders and multiplexers. the electrical characteristics of each cell follows its basic cell data. summary tables in the following pages list the whole STD80/stdm80 internal macrocells by the type and show their reference page numbers for your convenience. moreover, you can ?nd the more detailed description tables on the leading pages of each category.
summary tables internal macrocells STD80/stdm80 3-2 sec asic summary tables logic cells cell type cell name page and cell ad2/ad2d2 3-11 ad3/ad3d3 3-13 ad4/ad4d2 3-16 ad5/ad5d2 3-19 nand cell nd2/nd2d2 3-22 nd3/nd3d2 3-24 nd4/nd4d2 3-27 nd5/nd5d2 3-30 nd6/nd6d2 3-33 nd8/nd8d2 3-38 nor cell nr2/nr2d2 3-43 nr3/nr3d2 3-45 nr4/nr4d2 3-48 nr5/nr5d2 3-51 nr6/nr6d2 3-54 nr8/nr8d2 3-59 or cell or2/or2d2 3-64 or3/or3d3 3-66 or4/or4d2 3-69 or5/or5d2 3-72 exclusive-nor cell xn2/xn2d2 3-75 xn3/xn3d3 3-77 exclusive-or cell xo2/xo2d2 3-80 xo3/xo3d3 3-82 combinational cell of and and nor ao21/ao21d2 3-85 ao211/ao211d2 3-88 ao22/ao22d2 3-91 ao22a/ao22d2a 3-94 ao222/ao222d2 3-97 ao222a/ao222d2a 3-102 ao33/ao33d2 3-105 ao333/ao333d2 3-110
internal macrocells summary tables sec asic 3-3 STD80/stdm80 flip-flops combinational cell of or and nand oa21/oa21d2 3-115 oa211/oa211d2 3-118 oa22/oa22d2 3-121 oa22a/oa22d2a 3-124 oa2222/oa2222d2 3-127 delay cell dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 3-132 inverter iv/ivd2/ivd3/ivd4/ivd6/ivd8 3-138 iva/ivd2a/ivd3a/ivd4a 3-142 ivcd(11/13)/ivcd(22/26)/ivcd44 3-145 inverting tri-state buffer ivt/ivtd2/ivtd4/ivtd8 3-149 ivtn/ivtnd2/ivtnd4/ivtnd8 3-153 non-inverting buffer nid/nid2/nid3/nid4/nid6/nid8 3-157 nit/nitd2/nitd4/nitd8 3-161 nitn/nitnd2/nitnd4/nitnd8 3-165 cell type cell name page d flip-flop fd1/fd1d2 3-172 fd1cs/fd1csd2 3-175 fd1s/fd1sd2 3-179 fd1q/fd1qd2 3-182 fd1x2 3-184 fd1x4 3-186 yfd1/yfd1d2 3-189 d flip-flop with reset fd2/fd2d2 3-192 fd2cs/fd2csd2 3-195 fd2s/fd2sd2 3-199 fd2q/fd2qd2 3-202 fd2x2 3-204 fd2x4 3-207 yfd2/yfd2d2 3-210 d flip-flop with reset, tri-state output fd2t/fd2td2 3-213 fd2tcs/fd2tcsd2 3-216 fd2ts/fd2tsd2 3-221 cell type cell name page
summary tables internal macrocells STD80/stdm80 3-4 sec asic d flip-flop with set fd3/fd3d2 3-225 fd3cs/fd3csd2 3-228 fd3s/fd3sd2 3-232 fd3q/fd3qd2 3-235 fd3x2 3-237 fd3x4 3-240 yfd3/yfd3d2 3-243 d flip-flop with reset, set fd4/fd4d2 3-246 fd4cs/fd4csd2 3-250 fd4s/fd4sd2 3-256 fd4q/fd4qd2 3-260 fd4x2 3-263 fd4x4 3-266 yfd4/yfd4d2 3-271 d flip-flop with negative edge trigger fd5/fd5d2 3-274 fd5s/fd5sd2 3-277 fd5x4 3-280 fd6/fd6d2 3-283 fd6s/fd6sd2 3-286 fd7/fd7d2 3-289 fd7s/fd7sd2 3-292 fd8/fd8d2 3-295 fd8s/fd8sd2 3-299 d flip-flop with synchronous clear fds2/fds2d2 3-303 fds2cs/fds2csd2 3-306 fds2s/fds2sd2 3-310 fds3/fds3d2 3-313 d flip-flop with ck enable fg1 3-316 fg1x4 3-318 fg2 3-323 fg2x4 3-326 cell type cell name page
internal macrocells summary tables sec asic 3-5 STD80/stdm80 latches jk flip-flop fj1/fj1d2 3-331 fj1s/fj1sd2 3-334 fj2/fj2d2 3-337 fj2s/fj2sd2 3-340 fj4/fj4d2 3-344 fj4s/fj4sd2 3-348 toggle flip-flop ft2/ft2d2 3-352 ft3/ft3d2 3-355 cell type cell name page d latch with active high ld1/ld1d2 3-360 ld1s/ld1sd2 3-363 ld1q/ld1qd2 3-368 ld1x4/ld1x4d2 3-371 yld1/yld1d2 3-380 ld1a 3-383 ld1b 3-385 d latch with active high, reset ld2/ld2d2 3-388 ld2q/ld2qd2 3-393 yld2/yld2d2 3-396 ld3/ld3d2 3-401 ld4/ld4d2 3-406 d latch with active low ld5/ld5d2 3-411 ld5s/ld5sd2 3-414 ld5x4/ld5x4d2 3-419 ld6/ld6d2 3-428 ld7/ld7d2 3-433 ld8/ld8d2 3-438 d latch with synchronous clear lds2 3-443 lds6 3-446 sr latch ls0/ls0d2 3-449 ls1 3-452 ls2 3-455 cell type cell name page
summary tables internal macrocells STD80/stdm80 3-6 sec asic bus holder internal clock drivers decoders adders multiplexers cell type cell name page bus holder busholder 3-458 cell type cell name page STD80 stdm80 internal clock driver ck(2/4/8/12) ck(2/4/6/8) 3-459 cell type cell name page non-inverting decoder dc4 3-463 inverting decoder dc4i 3-466 dc8i 3-469 cell type cell name page full adder fa/fad2 3-477 half adder ha/had2 3-482 cell type cell name page 2 > 1 non-inverting mux mx2/mx2d3 3-486 mx2x4 3-489 ymx2/ymx2d2 3-494 2 > 1 inverting mux mx2i/mx2id2 3-497 mx2ia/mx2id2a 3-500 mx2ix4 3-503 3 > 1 inverting mux mx3i/mx3id2 3-508 4 > 1 non-inverting mux mx4/mx4d2 3-511 ymx4/ymx4d2 3-516 5 > 1 non-inverting mux mx5/mx5d2 3-521 8 > 1 non-inverting mux mx8/mx8d2 3-526 ymx8/ymx8d2 3-532
sec asic 3-7 STD80/stdm80 logic cells cell list cell name function description ad2 2-input and ad2d2 2-input and with 2x drive ad3 3-input and ad3d3 3-input and with 3x drive ad4 4-input and ad4d2 4-input and with 2x drive ad5 5-input and ad5d2 5-input and with 2x drive nd2 2-input nand nd2d2 2-input nand with 2x drive nd3 3-input nand nd3d2 3-input nand with 2x drive nd4 4-input nand nd4d2 4-input nand with 2x drive nd5 5-input nand nd5d2 5-input nand with 2x drive nd6 6-input nand nd6d2 6-input nand with 2x drive nd8 8-input nand nd8d2 8-input nand with 2x drive nr2 2-input nor nr2d2 2-input nor with 2x drive nr3 3-input nor nr3d2 3-input nor with 2x drive nr4 4-input nor nr4d2 4-input nor with 2x drive nr5 5-input nor nr5d2 5-input nor with 2x drive nr6 6-input nor nr6d2 6-input nor with 2x drive nr8 8-input nor nr8d2 8-input nor with 2x drive or2 2-input or or2d2 2-input or with 2x drive
STD80/stdm80 3-8 sec asic or3 3-input or or3d3 3-input or with 3x drive or4 4-input or or4d2 4-input or with 2x drive or5 5-input or or5d2 5-input or with 2x drive xn2 2-input exclusive-nor xn2d2 2-input exclusive-nor with 2x drive xn3 3-input exclusive-nor xn3d3 3-input exclusive-nor with 3x drive xo2 2-input exclusive-or xo2d2 2-input exclusive-or with 2x drive xo3 3-input exclusive-or xo3d3 3-input exclusive-or with 3x drive ao21 2-and into 2-nor ao21d2 2-and into 2-nor with 2x drive ao211 2-and into 3-nor ao211d2 2-and into 3-nor with 2x drive ao22 two 2-ands into 2-nor ao22d2 two 2-ands into 2-nor with 2x drive ao22a 2-and and 2-nor into 2-nor ao22d2a 2-and and 2-nor into 2-nor with 2x drive ao222 three 2-ands into 3-nor ao222d2 three 2-ands into 3-nor with 2x drive ao222a inverting 2-of-3 majority ao222d2a inverting 2-of-3 majority with 2x drive ao33 two 3-ands into 2-nor ao33d2 two 3-ands into 2-nor with 2x drive ao333 three 3-ands into 3-nor ao333d2 three 3-ands into 3-nor with 2x drive oa21 2-or into 2-nand oa21d2 2-or into 2-nand with 2x drive oa211 2-or into 3-nand oa211d2 2-or into 3-nand with 2x drive cell name function description logic cells cell list (continued)
sec asic 3-9 STD80/stdm80 oa22 two 2-ors into 2-nand oa22d2 two 2-ors into 2-nand with 2x drive oa22a 2-or and 2-nand into 2-nand oa22d2a 2-or and 2-nand into 2-nand with 2x drive oa2222 four 2-ors into 4-nand oa2222d2 four 2-ors into 4-nand with 2x drive dl1d2 1ns delay cell with 2x drive dl1d4 1 ns delay cell with 4x drive dl2d2 2 ns delay cell with 2x drive dl2d4 2 ns delay cell with 4x drive dl3d2 3 ns delay cell with 2x drive dl3d4 3 ns delay cell with 4x drive dl4d2 4 ns delay cell with 2x drive dl4d4 4 ns delay cell with 4x drive dl5d2 5 ns delay cell with 2x drive dl5d4 5 ns delay cell with 4x drive dl10d2 10 ns delay cell with 2x drive dl10d4 10 ns delay cell with 4x drive iv inverter ivd2 inverter with 2x drive ivd3 inverter with 3x drive ivd4 inverter with 4x drive ivd6 inverter with 6x drive ivd8 inverter with 8x drive iva inverter with 2x p-transistor, 1x n-transistor ivd2a inverter with 4x p-transistor, 2x n-transistor ivd3a inverter with 6x p-transistor, 3x n-transistor ivd4a inverter with 8x p-transistor, 4x n-transistor ivcd11 1x inverter into 1x inverter ivcd13 1x inverter into 3x inverter ivcd22 2x inverter into 2x inverter ivcd26 2x inverter into 6x inverter ivcd44 4x inverter into 4x inverter ivt inverting tri-state buffer with enable high cell name function description logic cells cell list (continued)
STD80/stdm80 3-10 sec asic ivtd2 inverting tri-state buffer with enable high, 2x drive ivtd4 inverting tri-state buffer with enable high, 4x drive ivtd8 inverting tri-state buffer with enable high, 8x drive ivtn inverting tri-state buffer with enable low ivtnd2 inverting tri-state buffer with enable low, 2x drive ivtnd4 inverting tri-state buffer with enable low, 4x drive ivtnd8 inverting tri-state buffer with enable low, 8x drive nid non-inverting buffer nid2 non-inverting buffer with 2x drive nid3 non-inverting buffer with 3x drive nid4 non-inverting buffer with 4x drive nid6 non-inverting buffer with 6x drive nid8 non-inverting buffer with 8x drive nit non-inverting tri-state buffer with enable high nitd2 non-inverting tri-state buffer with enable high, 2x drive nitd4 non-inverting tri-state buffer with enable high, 4x drive nitd8 non-inverting tri-state buffer with enable high, 8x drive nitn non-inverting tri-state buffer with enable low nitnd2 non-inverting tri-state buffer with enable low, 2x drive nitnd4 non-inverting tri-state buffer with enable low, 4x drive nitnd8 non-inverting tri-state buffer with enable low, 8x drive cell name function description logic cells cell list (continued)
sec asic 3-11 STD80/stdm80 ad2/ad2d2 2-input and with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ad2 STD80 ad2d2 input load (sl) gate count STD80 ad2 ad2d2 ad2 ad2d2 abab 0.7 0.6 0.7 0.6 1.3 1.7 stdm80 ad2/ad2d2 ad2d2 ad2 ad2d2 abab 0.8 0.8 0.7 0.8 1.3 1.7 a b y [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.20 + 0.029*sl 0.21 + 0.024*sl 0.22 + 0.024*sl t phl 0.30 0.22 + 0.039*sl 0.23 + 0.037*sl 0.23 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl b to y t plh 0.24 0.19 + 0.029*sl 0.19 + 0.024*sl 0.20 + 0.024*sl t phl 0.32 0.24 + 0.039*sl 0.25 + 0.037*sl 0.25 + 0.037*sl t r 0.20 0.10 + 0.048*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.25 + 0.018*sl 0.26 + 0.014*sl 0.28 + 0.012*sl t phl 0.30 0.26 + 0.022*sl 0.27 + 0.019*sl 0.27 + 0.018*sl t r 0.17 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.15 0.09 + 0.029*sl 0.09 + 0.031*sl 0.06 + 0.034*sl b to y t plh 0.26 0.23 + 0.018*sl 0.23 + 0.014*sl 0.25 + 0.012*sl t phl 0.32 0.28 + 0.022*sl 0.28 + 0.019*sl 0.29 + 0.018*sl t r 0.17 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.09 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aby 000 010 100 111
STD80/stdm80 3-12 sec asic ad2/ad2d2 2-input and with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ad2 stdm80 ad2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.37 0.29 + 0.039*sl 0.30 + 0.035*sl 0.31 + 0.033*sl t phl 0.41 0.31 + 0.048*sl 0.32 + 0.045*sl 0.33 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl b to y t plh 0.36 0.28 + 0.039*sl 0.29 + 0.035*sl 0.30 + 0.034*sl t phl 0.43 0.34 + 0.048*sl 0.34 + 0.045*sl 0.35 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.082*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.34 + 0.025*sl 0.35 + 0.021*sl 0.37 + 0.018*sl t phl 0.41 0.35 + 0.029*sl 0.37 + 0.024*sl 0.38 + 0.022*sl t r 0.22 0.15 + 0.034*sl 0.15 + 0.035*sl 0.15 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.12 + 0.038*sl 0.12 + 0.039*sl b to y t plh 0.38 0.33 + 0.025*sl 0.34 + 0.021*sl 0.36 + 0.018*sl t phl 0.43 0.37 + 0.029*sl 0.39 + 0.024*sl 0.40 + 0.022*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.034*sl 0.15 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.12 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-13 STD80/stdm80 ad3/ad3d3 3-input and with 1x/3x drive logic symbol cell data input load (sl) gate count STD80 ad3 ad3d3 ad3 ad3d3 abcabc 0.7 0.6 0.6 0.7 0.6 0.6 1.7 2.3 stdm80 ad3 ad3d3 ad3 ad3d3 abcabc 0.8 0.8 0.8 0.8 0.8 0.8 1.7 2.3 a b c y truth table abcy 0xx0 x0x0 xx00 1111
STD80/stdm80 3-14 sec asic ad3/ad3d3 3-input and with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ad3 STD80 ad3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.34 0.28 + 0.030*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t phl 0.32 0.24 + 0.039*sl 0.24 + 0.037*sl 0.24 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.22 0.10 + 0.061*sl 0.09 + 0.067*sl 0.06 + 0.069*sl b to y t plh 0.33 0.26 + 0.033*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t phl 0.34 0.26 + 0.039*sl 0.26 + 0.037*sl 0.26 + 0.037*sl t r 0.23 0.13 + 0.046*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.22 0.10 + 0.060*sl 0.09 + 0.067*sl 0.06 + 0.069*sl c to y t plh 0.32 0.25 + 0.032*sl 0.26 + 0.026*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.037*sl 0.28 + 0.037*sl t r 0.23 0.15 + 0.039*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.23 0.10 + 0.062*sl 0.09 + 0.066*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.41 0.38 + 0.016*sl 0.39 + 0.012*sl 0.43 + 0.008*sl t phl 0.35 0.32 + 0.015*sl 0.33 + 0.013*sl 0.34 + 0.012*sl t r 0.23 0.19 + 0.019*sl 0.20 + 0.015*sl 0.19 + 0.017*sl t f 0.16 0.12 + 0.019*sl 0.12 + 0.020*sl 0.10 + 0.022*sl b to y t plh 0.41 0.37 + 0.017*sl 0.38 + 0.012*sl 0.42 + 0.008*sl t phl 0.37 0.34 + 0.016*sl 0.34 + 0.013*sl 0.36 + 0.012*sl t r 0.23 0.20 + 0.014*sl 0.20 + 0.016*sl 0.19 + 0.017*sl t f 0.17 0.12 + 0.021*sl 0.13 + 0.020*sl 0.10 + 0.022*sl c to y t plh 0.39 0.36 + 0.016*sl 0.37 + 0.012*sl 0.41 + 0.008*sl t phl 0.38 0.35 + 0.016*sl 0.36 + 0.014*sl 0.37 + 0.012*sl t r 0.23 0.20 + 0.014*sl 0.20 + 0.016*sl 0.19 + 0.017*sl t f 0.17 0.13 + 0.020*sl 0.13 + 0.020*sl 0.11 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-15 STD80/stdm80 ad3/ad3d3 3-input and with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ad3 stdm80 ad3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.40 + 0.045*sl 0.42 + 0.038*sl 0.44 + 0.034*sl t phl 0.44 0.34 + 0.050*sl 0.35 + 0.046*sl 0.36 + 0.044*sl t r 0.32 0.18 + 0.071*sl 0.19 + 0.068*sl 0.18 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.080*sl 0.11 + 0.082*sl b to y t plh 0.49 0.40 + 0.045*sl 0.42 + 0.038*sl 0.45 + 0.035*sl t phl 0.46 0.36 + 0.050*sl 0.38 + 0.046*sl 0.38 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.19 + 0.068*sl 0.18 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.080*sl 0.12 + 0.082*sl c to y t plh 0.49 0.40 + 0.045*sl 0.43 + 0.038*sl 0.45 + 0.034*sl t phl 0.48 0.38 + 0.050*sl 0.40 + 0.046*sl 0.41 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.19 + 0.069*sl 0.18 + 0.070*sl t f 0.30 0.14 + 0.078*sl 0.14 + 0.079*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.60 0.56 + 0.023*sl 0.57 + 0.018*sl 0.59 + 0.016*sl t phl 0.49 0.45 + 0.022*sl 0.46 + 0.019*sl 0.47 + 0.016*sl t r 0.30 0.25 + 0.024*sl 0.26 + 0.024*sl 0.26 + 0.024*sl t f 0.21 0.16 + 0.028*sl 0.16 + 0.027*sl 0.17 + 0.025*sl b to y t plh 0.61 0.57 + 0.022*sl 0.58 + 0.019*sl 0.60 + 0.016*sl t phl 0.51 0.47 + 0.022*sl 0.48 + 0.019*sl 0.49 + 0.017*sl t r 0.30 0.26 + 0.024*sl 0.26 + 0.024*sl 0.26 + 0.024*sl t f 0.22 0.16 + 0.027*sl 0.17 + 0.026*sl 0.18 + 0.025*sl c to y t plh 0.61 0.57 + 0.022*sl 0.58 + 0.019*sl 0.60 + 0.016*sl t phl 0.53 0.49 + 0.022*sl 0.50 + 0.019*sl 0.51 + 0.017*sl t r 0.30 0.25 + 0.025*sl 0.26 + 0.024*sl 0.26 + 0.023*sl t f 0.23 0.17 + 0.029*sl 0.18 + 0.025*sl 0.18 + 0.024*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-16 sec asic ad4/ad4d2 4-input and with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ad4 ad4d2 ad4 ad4d2 abcdabcd 0.6 0.6 0.6 0.7 0.7 0.6 0.6 0.6 2.0 2.3 stdm80 ad4 ad4d2 ad4 ad4d2 abcdabcd 0.7 0.8 0.8 0.8 0.7 0.8 0.8 0.8 2.0 2.3 a b c y d truth table abcdy 0xxx0 x0xx0 xx0x0 xxx00 11111
sec asic 3-17 STD80/stdm80 ad4/ad4d2 4-input and with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ad4 STD80 ad4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.32 + 0.035*sl 0.33 + 0.027*sl 0.37 + 0.024*sl t phl 0.32 0.24 + 0.040*sl 0.24 + 0.037*sl 0.24 + 0.037*sl t r 0.25 0.16 + 0.047*sl 0.15 + 0.049*sl 0.13 + 0.051*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.06 + 0.069*sl b to y t plh 0.39 0.31 + 0.037*sl 0.33 + 0.027*sl 0.37 + 0.024*sl t phl 0.34 0.26 + 0.039*sl 0.26 + 0.037*sl 0.26 + 0.037*sl t r 0.25 0.17 + 0.044*sl 0.16 + 0.048*sl 0.13 + 0.051*sl t f 0.23 0.10 + 0.064*sl 0.09 + 0.066*sl 0.07 + 0.069*sl c to y t plh 0.38 0.31 + 0.035*sl 0.33 + 0.027*sl 0.37 + 0.024*sl t phl 0.35 0.27 + 0.039*sl 0.28 + 0.037*sl 0.28 + 0.037*sl t r 0.26 0.16 + 0.048*sl 0.16 + 0.048*sl 0.13 + 0.051*sl t f 0.23 0.10 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl d to y t plh 0.38 0.31 + 0.035*sl 0.33 + 0.027*sl 0.36 + 0.024*sl t phl 0.37 0.29 + 0.040*sl 0.29 + 0.037*sl 0.29 + 0.037*sl t r 0.25 0.16 + 0.046*sl 0.16 + 0.048*sl 0.13 + 0.051*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.45 0.40 + 0.025*sl 0.42 + 0.018*sl 0.47 + 0.012*sl t phl 0.34 0.29 + 0.023*sl 0.30 + 0.019*sl 0.31 + 0.018*sl t r 0.26 0.20 + 0.028*sl 0.21 + 0.024*sl 0.20 + 0.025*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl b to y t plh 0.46 0.41 + 0.025*sl 0.42 + 0.018*sl 0.48 + 0.012*sl t phl 0.35 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.26 0.20 + 0.028*sl 0.21 + 0.024*sl 0.20 + 0.025*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl c to y t plh 0.45 0.40 + 0.025*sl 0.42 + 0.018*sl 0.47 + 0.012*sl t phl 0.37 0.32 + 0.023*sl 0.33 + 0.019*sl 0.34 + 0.018*sl t r 0.26 0.20 + 0.029*sl 0.21 + 0.024*sl 0.20 + 0.025*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.031*sl 0.08 + 0.034*sl d to y t plh 0.45 0.40 + 0.025*sl 0.41 + 0.018*sl 0.47 + 0.012*sl t phl 0.38 0.33 + 0.023*sl 0.34 + 0.020*sl 0.36 + 0.018*sl t r 0.26 0.20 + 0.029*sl 0.21 + 0.024*sl 0.20 + 0.025*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.031*sl 0.09 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-18 sec asic ad4/ad4d2 4-input and with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ad4 stdm80 ad4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.47 + 0.050*sl 0.49 + 0.041*sl 0.53 + 0.036*sl t phl 0.45 0.35 + 0.050*sl 0.36 + 0.046*sl 0.37 + 0.044*sl t r 0.36 0.22 + 0.072*sl 0.23 + 0.070*sl 0.23 + 0.069*sl t f 0.29 0.13 + 0.079*sl 0.13 + 0.080*sl 0.12 + 0.082*sl b to y t plh 0.59 0.49 + 0.050*sl 0.52 + 0.041*sl 0.55 + 0.036*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.046*sl 0.39 + 0.044*sl t r 0.36 0.22 + 0.073*sl 0.23 + 0.070*sl 0.23 + 0.069*sl t f 0.29 0.14 + 0.078*sl 0.13 + 0.080*sl 0.12 + 0.082*sl c to y t plh 0.60 0.50 + 0.050*sl 0.53 + 0.041*sl 0.56 + 0.036*sl t phl 0.49 0.39 + 0.050*sl 0.40 + 0.046*sl 0.41 + 0.044*sl t r 0.36 0.22 + 0.072*sl 0.23 + 0.069*sl 0.23 + 0.069*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.079*sl 0.12 + 0.082*sl d to y t plh 0.61 0.51 + 0.050*sl 0.54 + 0.041*sl 0.57 + 0.036*sl t phl 0.51 0.40 + 0.052*sl 0.42 + 0.046*sl 0.43 + 0.045*sl t r 0.36 0.22 + 0.071*sl 0.23 + 0.069*sl 0.23 + 0.069*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.080*sl 0.13 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.62 0.56 + 0.033*sl 0.58 + 0.026*sl 0.61 + 0.022*sl t phl 0.44 0.38 + 0.030*sl 0.40 + 0.025*sl 0.41 + 0.023*sl t r 0.32 0.24 + 0.039*sl 0.25 + 0.037*sl 0.26 + 0.035*sl t f 0.21 0.13 + 0.039*sl 0.13 + 0.039*sl 0.14 + 0.038*sl b to y t plh 0.65 0.58 + 0.033*sl 0.60 + 0.026*sl 0.63 + 0.022*sl t phl 0.47 0.40 + 0.030*sl 0.42 + 0.026*sl 0.44 + 0.023*sl t r 0.32 0.25 + 0.038*sl 0.25 + 0.037*sl 0.26 + 0.035*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.038*sl c to y t plh 0.66 0.60 + 0.033*sl 0.62 + 0.026*sl 0.65 + 0.022*sl t phl 0.48 0.42 + 0.031*sl 0.44 + 0.026*sl 0.46 + 0.023*sl t r 0.32 0.24 + 0.039*sl 0.25 + 0.037*sl 0.26 + 0.035*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl d to y t plh 0.67 0.60 + 0.033*sl 0.63 + 0.026*sl 0.65 + 0.022*sl t phl 0.50 0.44 + 0.031*sl 0.45 + 0.026*sl 0.47 + 0.023*sl t r 0.32 0.24 + 0.039*sl 0.25 + 0.037*sl 0.26 + 0.035*sl t f 0.23 0.15 + 0.039*sl 0.15 + 0.038*sl 0.15 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-19 STD80/stdm80 ad5/ad5d2 5-input and with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ad5 ad5d2 ad5 ad5d2 abcdeabcde 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 3.0 3.7 stdm80 ad5 ad5d2 ad5 ad5d2 abcdeabcde 0.7 0.8 0.8 0.8 0.8 0.7 0.8 0.8 0.8 0.8 3.0 3.7 b c d y e a truth table abcdey 0xxxx0 x0xxx0 xx0xx0 xxx0x0 xxxx00 111111
STD80/stdm80 3-20 sec asic ad5/ad5d2 5-input and with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ad5 STD80 ad5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.30 + 0.044*sl 0.31 + 0.039*sl 0.32 + 0.038*sl t phl 0.38 0.30 + 0.040*sl 0.31 + 0.038*sl 0.31 + 0.037*sl t r 0.35 0.19 + 0.080*sl 0.19 + 0.083*sl 0.15 + 0.086*sl t f 0.24 0.12 + 0.061*sl 0.11 + 0.066*sl 0.08 + 0.069*sl b to y t plh 0.40 0.31 + 0.044*sl 0.33 + 0.039*sl 0.33 + 0.038*sl t phl 0.37 0.29 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.35 0.19 + 0.080*sl 0.19 + 0.083*sl 0.15 + 0.086*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl c to y t plh 0.41 0.32 + 0.045*sl 0.33 + 0.039*sl 0.34 + 0.038*sl t phl 0.35 0.27 + 0.040*sl 0.27 + 0.038*sl 0.28 + 0.037*sl t r 0.35 0.19 + 0.081*sl 0.19 + 0.083*sl 0.15 + 0.086*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl d to y t plh 0.34 0.25 + 0.042*sl 0.26 + 0.039*sl 0.27 + 0.038*sl t phl 0.39 0.31 + 0.039*sl 0.31 + 0.037*sl 0.32 + 0.037*sl t r 0.33 0.17 + 0.081*sl 0.17 + 0.084*sl 0.15 + 0.086*sl t f 0.30 0.18 + 0.062*sl 0.17 + 0.067*sl 0.14 + 0.069*sl e to y t plh 0.36 0.27 + 0.042*sl 0.28 + 0.039*sl 0.29 + 0.038*sl t phl 0.37 0.29 + 0.039*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.33 0.17 + 0.081*sl 0.17 + 0.084*sl 0.15 + 0.086*sl t f 0.30 0.17 + 0.063*sl 0.16 + 0.067*sl 0.14 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.41 0.36 + 0.025*sl 0.37 + 0.021*sl 0.39 + 0.019*sl t phl 0.38 0.34 + 0.023*sl 0.34 + 0.020*sl 0.36 + 0.018*sl t r 0.29 0.22 + 0.035*sl 0.21 + 0.039*sl 0.18 + 0.043*sl t f 0.19 0.13 + 0.030*sl 0.13 + 0.031*sl 0.09 + 0.034*sl b to y t plh 0.42 0.37 + 0.026*sl 0.38 + 0.021*sl 0.41 + 0.019*sl t phl 0.37 0.32 + 0.023*sl 0.33 + 0.020*sl 0.34 + 0.018*sl t r 0.29 0.22 + 0.035*sl 0.21 + 0.039*sl 0.18 + 0.043*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.031*sl 0.09 + 0.034*sl c to y t plh 0.43 0.38 + 0.026*sl 0.39 + 0.021*sl 0.41 + 0.019*sl t phl 0.35 0.31 + 0.023*sl 0.31 + 0.020*sl 0.33 + 0.018*sl t r 0.29 0.22 + 0.036*sl 0.21 + 0.039*sl 0.18 + 0.043*sl t f 0.18 0.11 + 0.031*sl 0.11 + 0.031*sl 0.09 + 0.034*sl d to y t plh 0.35 0.30 + 0.023*sl 0.31 + 0.021*sl 0.33 + 0.019*sl t phl 0.39 0.35 + 0.020*sl 0.35 + 0.019*sl 0.36 + 0.018*sl t r 0.26 0.18 + 0.041*sl 0.18 + 0.041*sl 0.16 + 0.043*sl t f 0.25 0.19 + 0.029*sl 0.18 + 0.031*sl 0.15 + 0.034*sl e to y t plh 0.37 0.32 + 0.027*sl 0.33 + 0.021*sl 0.35 + 0.019*sl t phl 0.37 0.33 + 0.020*sl 0.33 + 0.019*sl 0.34 + 0.018*sl t r 0.26 0.19 + 0.034*sl 0.17 + 0.041*sl 0.16 + 0.043*sl t f 0.24 0.19 + 0.029*sl 0.18 + 0.031*sl 0.15 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-21 STD80/stdm80 ad5/ad5d2 5-input and with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ad5 stdm80 ad5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.44 + 0.065*sl 0.46 + 0.059*sl 0.47 + 0.057*sl t phl 0.50 0.40 + 0.051*sl 0.42 + 0.046*sl 0.43 + 0.044*sl t r 0.51 0.27 + 0.121*sl 0.26 + 0.122*sl 0.25 + 0.124*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl b to y t plh 0.57 0.44 + 0.065*sl 0.46 + 0.059*sl 0.47 + 0.057*sl t phl 0.48 0.38 + 0.050*sl 0.40 + 0.046*sl 0.40 + 0.045*sl t r 0.51 0.27 + 0.121*sl 0.26 + 0.122*sl 0.25 + 0.124*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.081*sl 0.13 + 0.082*sl c to y t plh 0.57 0.44 + 0.065*sl 0.45 + 0.059*sl 0.47 + 0.057*sl t phl 0.46 0.36 + 0.050*sl 0.37 + 0.046*sl 0.38 + 0.044*sl t r 0.51 0.27 + 0.121*sl 0.26 + 0.122*sl 0.25 + 0.124*sl t f 0.30 0.14 + 0.080*sl 0.13 + 0.081*sl 0.13 + 0.082*sl d to y t plh 0.49 0.37 + 0.062*sl 0.38 + 0.059*sl 0.39 + 0.057*sl t phl 0.50 0.41 + 0.048*sl 0.41 + 0.046*sl 0.42 + 0.044*sl t r 0.48 0.24 + 0.122*sl 0.24 + 0.124*sl 0.23 + 0.125*sl t f 0.36 0.20 + 0.080*sl 0.20 + 0.081*sl 0.19 + 0.082*sl e to y t plh 0.50 0.38 + 0.063*sl 0.39 + 0.059*sl 0.40 + 0.057*sl t phl 0.48 0.38 + 0.048*sl 0.39 + 0.045*sl 0.39 + 0.045*sl t r 0.49 0.24 + 0.122*sl 0.24 + 0.124*sl 0.23 + 0.125*sl t f 0.36 0.20 + 0.080*sl 0.20 + 0.081*sl 0.19 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.59 0.52 + 0.037*sl 0.53 + 0.033*sl 0.55 + 0.030*sl t phl 0.50 0.44 + 0.030*sl 0.46 + 0.026*sl 0.48 + 0.023*sl t r 0.38 0.26 + 0.062*sl 0.26 + 0.061*sl 0.26 + 0.061*sl t f 0.23 0.15 + 0.040*sl 0.16 + 0.038*sl 0.15 + 0.038*sl b to y t plh 0.60 0.52 + 0.037*sl 0.53 + 0.033*sl 0.55 + 0.030*sl t phl 0.49 0.43 + 0.030*sl 0.44 + 0.026*sl 0.46 + 0.023*sl t r 0.38 0.26 + 0.061*sl 0.26 + 0.061*sl 0.26 + 0.061*sl t f 0.22 0.15 + 0.038*sl 0.15 + 0.039*sl 0.15 + 0.038*sl c to y t plh 0.59 0.51 + 0.037*sl 0.53 + 0.033*sl 0.54 + 0.031*sl t phl 0.46 0.40 + 0.030*sl 0.42 + 0.025*sl 0.43 + 0.023*sl t r 0.38 0.26 + 0.060*sl 0.26 + 0.062*sl 0.27 + 0.060*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.039*sl d to y t plh 0.50 0.42 + 0.037*sl 0.43 + 0.033*sl 0.45 + 0.030*sl t phl 0.51 0.45 + 0.027*sl 0.46 + 0.024*sl 0.47 + 0.022*sl t r 0.35 0.23 + 0.064*sl 0.23 + 0.062*sl 0.23 + 0.062*sl t f 0.29 0.22 + 0.037*sl 0.22 + 0.037*sl 0.21 + 0.038*sl e to y t plh 0.50 0.43 + 0.038*sl 0.44 + 0.033*sl 0.46 + 0.031*sl t phl 0.48 0.43 + 0.026*sl 0.44 + 0.024*sl 0.45 + 0.022*sl t r 0.35 0.23 + 0.064*sl 0.23 + 0.062*sl 0.23 + 0.062*sl t f 0.29 0.21 + 0.037*sl 0.21 + 0.037*sl 0.21 + 0.038*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-22 sec asic nd2/nd2d2 2-input nand with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd2 STD80 nd2d2 input load (sl) gate count STD80 nd2 nd2d2 nd2 nd2d2 abab 1.1 1.1 2.0 2.0 1.0 1.7 stdm80 nd2 nd2d2 nd2 nd2d2 abab 1.1 1.1 2.2 2.2 1.0 1.7 a b y [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.11 + 0.033*sl 0.13 + 0.025*sl 0.13 + 0.025*sl t phl 0.18 0.10 + 0.041*sl 0.11 + 0.038*sl 0.10 + 0.038*sl t r 0.30 0.22 + 0.041*sl 0.21 + 0.046*sl 0.13 + 0.054*sl t f 0.31 0.18 + 0.065*sl 0.17 + 0.071*sl 0.10 + 0.078*sl b to y t plh 0.16 0.09 + 0.037*sl 0.11 + 0.026*sl 0.12 + 0.025*sl t phl 0.21 0.12 + 0.044*sl 0.13 + 0.038*sl 0.13 + 0.038*sl t r 0.28 0.19 + 0.044*sl 0.19 + 0.046*sl 0.11 + 0.054*sl t f 0.32 0.19 + 0.065*sl 0.18 + 0.071*sl 0.11 + 0.078*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.13 0.09 + 0.020*sl 0.10 + 0.015*sl 0.13 + 0.012*sl t phl 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.019*sl t r 0.24 0.20 + 0.022*sl 0.20 + 0.022*sl 0.15 + 0.027*sl t f 0.24 0.17 + 0.033*sl 0.17 + 0.034*sl 0.13 + 0.039*sl b to y t plh 0.13 0.09 + 0.020*sl 0.10 + 0.015*sl 0.13 + 0.012*sl t phl 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.019*sl t r 0.25 0.20 + 0.023*sl 0.20 + 0.021*sl 0.15 + 0.027*sl t f 0.24 0.17 + 0.033*sl 0.17 + 0.034*sl 0.13 + 0.039*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aby 001 011 101 110
sec asic 3-23 STD80/stdm80 nd2/nd2d2 2-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd2 stdm80 nd2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.15 + 0.037*sl 0.16 + 0.034*sl 0.16 + 0.035*sl t phl 0.24 0.13 + 0.052*sl 0.14 + 0.050*sl 0.14 + 0.050*sl t r 0.33 0.21 + 0.063*sl 0.19 + 0.070*sl 0.16 + 0.073*sl t f 0.35 0.17 + 0.091*sl 0.15 + 0.096*sl 0.14 + 0.098*sl b to y t plh 0.21 0.13 + 0.040*sl 0.14 + 0.035*sl 0.14 + 0.035*sl t phl 0.25 0.15 + 0.052*sl 0.15 + 0.050*sl 0.15 + 0.050*sl t r 0.31 0.18 + 0.064*sl 0.16 + 0.070*sl 0.14 + 0.073*sl t f 0.36 0.18 + 0.089*sl 0.16 + 0.095*sl 0.14 + 0.098*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.17 0.12 + 0.023*sl 0.14 + 0.019*sl 0.15 + 0.017*sl t phl 0.18 0.12 + 0.029*sl 0.14 + 0.025*sl 0.14 + 0.025*sl t r 0.25 0.19 + 0.029*sl 0.18 + 0.032*sl 0.16 + 0.035*sl t f 0.25 0.17 + 0.043*sl 0.16 + 0.046*sl 0.15 + 0.048*sl b to y t plh 0.17 0.12 + 0.023*sl 0.14 + 0.018*sl 0.15 + 0.017*sl t phl 0.18 0.13 + 0.029*sl 0.14 + 0.025*sl 0.14 + 0.025*sl t r 0.25 0.19 + 0.029*sl 0.18 + 0.032*sl 0.16 + 0.035*sl t f 0.26 0.17 + 0.042*sl 0.16 + 0.046*sl 0.15 + 0.048*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-24 sec asic nd3/nd3d2 3-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nd3 nd3d2 nd3 nd3d2 abcabc 1.0 1.0 1.0 2.0 2.0 2.0 1.3 2.3 stdm80 nd3 nd3d2 nd3 nd3d2 abcabc 1.1 1.1 1.1 2.2 2.2 2.3 1.3 2.3 a b c y truth table abcy 0xx1 x0x1 xx01 1110
sec asic 3-25 STD80/stdm80 nd3/nd3d2 3-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd3 STD80 nd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.25 0.15 + 0.050*sl 0.15 + 0.050*sl 0.14 + 0.051*sl t r 0.35 0.27 + 0.039*sl 0.26 + 0.046*sl 0.18 + 0.054*sl t f 0.43 0.24 + 0.096*sl 0.22 + 0.103*sl 0.19 + 0.107*sl b to y t plh 0.17 0.10 + 0.035*sl 0.12 + 0.026*sl 0.13 + 0.025*sl t phl 0.28 0.18 + 0.051*sl 0.18 + 0.050*sl 0.17 + 0.051*sl t r 0.30 0.22 + 0.040*sl 0.21 + 0.046*sl 0.14 + 0.054*sl t f 0.45 0.26 + 0.095*sl 0.24 + 0.102*sl 0.19 + 0.107*sl c to y t plh 0.19 0.12 + 0.033*sl 0.14 + 0.025*sl 0.14 + 0.025*sl t phl 0.27 0.17 + 0.051*sl 0.17 + 0.050*sl 0.16 + 0.051*sl t r 0.32 0.24 + 0.040*sl 0.23 + 0.046*sl 0.16 + 0.054*sl t f 0.44 0.25 + 0.093*sl 0.23 + 0.103*sl 0.19 + 0.107*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.13 0.09 + 0.021*sl 0.10 + 0.015*sl 0.13 + 0.012*sl t phl 0.22 0.17 + 0.027*sl 0.18 + 0.025*sl 0.17 + 0.025*sl t r 0.26 0.22 + 0.023*sl 0.22 + 0.022*sl 0.17 + 0.027*sl t f 0.34 0.25 + 0.046*sl 0.24 + 0.049*sl 0.20 + 0.053*sl b to y t plh 0.17 0.13 + 0.018*sl 0.14 + 0.014*sl 0.16 + 0.012*sl t phl 0.20 0.15 + 0.026*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t r 0.31 0.27 + 0.018*sl 0.26 + 0.021*sl 0.21 + 0.027*sl t f 0.33 0.24 + 0.046*sl 0.23 + 0.050*sl 0.19 + 0.053*sl c to y t plh 0.15 0.12 + 0.018*sl 0.12 + 0.014*sl 0.15 + 0.012*sl t phl 0.21 0.16 + 0.027*sl 0.16 + 0.025*sl 0.16 + 0.025*sl t r 0.28 0.24 + 0.020*sl 0.24 + 0.022*sl 0.19 + 0.027*sl t f 0.34 0.25 + 0.046*sl 0.24 + 0.049*sl 0.20 + 0.053*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-26 sec asic nd3/nd3d2 3-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd3 stdm80 nd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t phl 0.36 0.22 + 0.069*sl 0.22 + 0.069*sl 0.22 + 0.069*sl t r 0.40 0.27 + 0.065*sl 0.25 + 0.070*sl 0.23 + 0.073*sl t f 0.56 0.28 + 0.137*sl 0.28 + 0.139*sl 0.27 + 0.140*sl b to y t plh 0.23 0.15 + 0.038*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t phl 0.35 0.22 + 0.069*sl 0.22 + 0.068*sl 0.22 + 0.068*sl t r 0.35 0.22 + 0.065*sl 0.20 + 0.071*sl 0.18 + 0.073*sl t f 0.56 0.30 + 0.134*sl 0.28 + 0.138*sl 0.26 + 0.141*sl c to y t plh 0.25 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.36 0.22 + 0.069*sl 0.22 + 0.069*sl 0.23 + 0.068*sl t r 0.37 0.24 + 0.064*sl 0.22 + 0.071*sl 0.21 + 0.073*sl t f 0.56 0.29 + 0.135*sl 0.28 + 0.138*sl 0.27 + 0.140*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.14 + 0.022*sl 0.15 + 0.018*sl 0.16 + 0.017*sl t phl 0.28 0.21 + 0.034*sl 0.21 + 0.034*sl 0.21 + 0.034*sl t r 0.28 0.22 + 0.030*sl 0.21 + 0.033*sl 0.20 + 0.035*sl t f 0.42 0.29 + 0.064*sl 0.28 + 0.068*sl 0.27 + 0.069*sl b to y t plh 0.22 0.18 + 0.020*sl 0.19 + 0.017*sl 0.19 + 0.017*sl t phl 0.28 0.21 + 0.035*sl 0.22 + 0.035*sl 0.22 + 0.034*sl t r 0.33 0.27 + 0.031*sl 0.26 + 0.033*sl 0.25 + 0.034*sl t f 0.41 0.27 + 0.067*sl 0.27 + 0.069*sl 0.26 + 0.069*sl c to y t plh 0.21 0.16 + 0.021*sl 0.17 + 0.017*sl 0.18 + 0.017*sl t phl 0.29 0.22 + 0.035*sl 0.22 + 0.034*sl 0.22 + 0.034*sl t r 0.30 0.24 + 0.030*sl 0.23 + 0.033*sl 0.22 + 0.035*sl t f 0.41 0.28 + 0.066*sl 0.28 + 0.068*sl 0.27 + 0.069*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-27 STD80/stdm80 nd4/nd4d2 4-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nd4 nd4d2 nd4 nd4d2 abcdabcd 1.1 1.1 1.1 1.1 2.0 2.0 2.0 2.0 1.7 3.0 stdm80 nd4 nd4d2 nd4 nd4d2 abcdabcd 1.1 1.1 1.1 1.1 2.4 2.2 2.3 2.3 1.7 3.0 a b c y d truth table abcdy 0xxx1 x0xx1 xx0x1 xxx01 11110
STD80/stdm80 3-28 sec asic nd4/nd4d2 4-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd4 STD80 nd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.14 + 0.032*sl 0.16 + 0.025*sl 0.16 + 0.025*sl t phl 0.32 0.20 + 0.062*sl 0.19 + 0.063*sl 0.19 + 0.063*sl t r 0.37 0.29 + 0.041*sl 0.28 + 0.046*sl 0.21 + 0.054*sl t f 0.56 0.30 + 0.127*sl 0.29 + 0.134*sl 0.27 + 0.136*sl b to y t plh 0.19 0.12 + 0.033*sl 0.14 + 0.025*sl 0.15 + 0.025*sl t phl 0.33 0.21 + 0.061*sl 0.21 + 0.062*sl 0.20 + 0.063*sl t r 0.33 0.25 + 0.039*sl 0.23 + 0.047*sl 0.16 + 0.054*sl t f 0.57 0.32 + 0.127*sl 0.30 + 0.133*sl 0.27 + 0.136*sl c to y t plh 0.20 0.14 + 0.032*sl 0.15 + 0.025*sl 0.16 + 0.025*sl t phl 0.33 0.20 + 0.062*sl 0.20 + 0.063*sl 0.20 + 0.063*sl t r 0.35 0.27 + 0.040*sl 0.26 + 0.046*sl 0.19 + 0.054*sl t f 0.57 0.31 + 0.128*sl 0.30 + 0.133*sl 0.27 + 0.136*sl d to y t plh 0.17 0.10 + 0.035*sl 0.12 + 0.026*sl 0.14 + 0.025*sl t phl 0.33 0.21 + 0.060*sl 0.21 + 0.062*sl 0.19 + 0.063*sl t r 0.31 0.23 + 0.040*sl 0.21 + 0.047*sl 0.15 + 0.054*sl t f 0.57 0.32 + 0.125*sl 0.30 + 0.132*sl 0.27 + 0.136*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.14 + 0.018*sl 0.15 + 0.014*sl 0.17 + 0.012*sl t phl 0.26 0.19 + 0.033*sl 0.20 + 0.031*sl 0.19 + 0.032*sl t r 0.33 0.29 + 0.020*sl 0.29 + 0.022*sl 0.24 + 0.027*sl t f 0.43 0.30 + 0.065*sl 0.30 + 0.065*sl 0.27 + 0.068*sl b to y t plh 0.14 0.10 + 0.020*sl 0.11 + 0.015*sl 0.14 + 0.012*sl t phl 0.27 0.21 + 0.031*sl 0.21 + 0.031*sl 0.20 + 0.032*sl t r 0.27 0.22 + 0.023*sl 0.22 + 0.022*sl 0.18 + 0.027*sl t f 0.44 0.32 + 0.061*sl 0.31 + 0.064*sl 0.27 + 0.068*sl c to y t plh 0.17 0.13 + 0.018*sl 0.14 + 0.014*sl 0.16 + 0.012*sl t phl 0.26 0.20 + 0.032*sl 0.20 + 0.031*sl 0.20 + 0.032*sl t r 0.31 0.27 + 0.018*sl 0.27 + 0.022*sl 0.22 + 0.027*sl t f 0.43 0.31 + 0.060*sl 0.30 + 0.065*sl 0.27 + 0.068*sl d to y t plh 0.15 0.12 + 0.018*sl 0.13 + 0.015*sl 0.15 + 0.012*sl t phl 0.27 0.20 + 0.032*sl 0.21 + 0.031*sl 0.20 + 0.032*sl t r 0.29 0.25 + 0.021*sl 0.25 + 0.022*sl 0.20 + 0.027*sl t f 0.44 0.31 + 0.061*sl 0.31 + 0.065*sl 0.27 + 0.068*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-29 STD80/stdm80 nd4/nd4d2 4-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd4 stdm80 nd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.20 + 0.036*sl 0.20 + 0.036*sl 0.21 + 0.035*sl t phl 0.47 0.29 + 0.089*sl 0.30 + 0.088*sl 0.30 + 0.087*sl t r 0.43 0.30 + 0.065*sl 0.29 + 0.070*sl 0.27 + 0.073*sl t f 0.75 0.39 + 0.180*sl 0.39 + 0.181*sl 0.38 + 0.182*sl b to y t plh 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.45 0.28 + 0.088*sl 0.28 + 0.088*sl 0.28 + 0.087*sl t r 0.38 0.25 + 0.067*sl 0.23 + 0.071*sl 0.21 + 0.073*sl t f 0.76 0.40 + 0.177*sl 0.40 + 0.180*sl 0.38 + 0.182*sl c to y t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.20 + 0.035*sl t phl 0.47 0.29 + 0.089*sl 0.29 + 0.088*sl 0.30 + 0.087*sl t r 0.40 0.27 + 0.065*sl 0.26 + 0.070*sl 0.24 + 0.073*sl t f 0.76 0.40 + 0.178*sl 0.39 + 0.181*sl 0.38 + 0.182*sl d to y t plh 0.23 0.16 + 0.037*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t phl 0.43 0.26 + 0.088*sl 0.26 + 0.087*sl 0.26 + 0.087*sl t r 0.36 0.23 + 0.066*sl 0.21 + 0.071*sl 0.19 + 0.073*sl t f 0.75 0.40 + 0.177*sl 0.39 + 0.181*sl 0.38 + 0.182*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.20 + 0.019*sl 0.20 + 0.018*sl 0.20 + 0.018*sl t phl 0.38 0.29 + 0.045*sl 0.30 + 0.045*sl 0.30 + 0.044*sl t r 0.36 0.30 + 0.032*sl 0.29 + 0.033*sl 0.28 + 0.035*sl t f 0.56 0.39 + 0.089*sl 0.38 + 0.090*sl 0.38 + 0.091*sl b to y t plh 0.19 0.15 + 0.022*sl 0.16 + 0.018*sl 0.17 + 0.017*sl t phl 0.34 0.25 + 0.044*sl 0.26 + 0.044*sl 0.26 + 0.044*sl t r 0.29 0.23 + 0.031*sl 0.22 + 0.033*sl 0.21 + 0.035*sl t f 0.57 0.39 + 0.088*sl 0.39 + 0.089*sl 0.38 + 0.090*sl c to y t plh 0.23 0.19 + 0.019*sl 0.19 + 0.017*sl 0.19 + 0.018*sl t phl 0.38 0.29 + 0.044*sl 0.29 + 0.044*sl 0.29 + 0.044*sl t r 0.34 0.28 + 0.030*sl 0.27 + 0.033*sl 0.25 + 0.035*sl t f 0.57 0.39 + 0.088*sl 0.39 + 0.089*sl 0.38 + 0.090*sl d to y t plh 0.21 0.17 + 0.020*sl 0.18 + 0.017*sl 0.18 + 0.017*sl t phl 0.36 0.28 + 0.044*sl 0.27 + 0.044*sl 0.28 + 0.044*sl t r 0.31 0.25 + 0.030*sl 0.24 + 0.033*sl 0.23 + 0.035*sl t f 0.57 0.40 + 0.088*sl 0.39 + 0.089*sl 0.39 + 0.090*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-30 sec asic nd5/nd5d2 5-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nd5 nd5d2 nd5 nd5d2 abcdeabcde 1.0 1.0 1.0 1.0 1.0 2.0 2.0 2.0 2.0 2.0 2.0 3.7 stdm80 nd5 nd5d2 nd5 nd5d2 abcdeabcde 1.1 1.1 1.1 1.1 1.1 2.5 2.5 2.2 2.3 2.3 2.0 3.7 b c d y e a truth table abcdey 0xxxx1 x0xxx1 xx0xx1 xxx0x1 xxxx01 111110
sec asic 3-31 STD80/stdm80 nd5/nd5d2 5-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd5 STD80 nd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.17 + 0.030*sl 0.18 + 0.025*sl 0.18 + 0.025*sl t phl 0.44 0.29 + 0.076*sl 0.29 + 0.076*sl 0.29 + 0.076*sl t r 0.42 0.33 + 0.042*sl 0.32 + 0.047*sl 0.26 + 0.054*sl t f 0.77 0.45 + 0.160*sl 0.44 + 0.164*sl 0.43 + 0.165*sl b to y t plh 0.22 0.16 + 0.030*sl 0.17 + 0.025*sl 0.18 + 0.025*sl t phl 0.44 0.29 + 0.076*sl 0.29 + 0.076*sl 0.29 + 0.076*sl t r 0.40 0.31 + 0.042*sl 0.30 + 0.047*sl 0.24 + 0.054*sl t f 0.77 0.46 + 0.159*sl 0.45 + 0.164*sl 0.43 + 0.165*sl c to y t plh 0.21 0.15 + 0.031*sl 0.16 + 0.025*sl 0.17 + 0.025*sl t phl 0.44 0.29 + 0.074*sl 0.28 + 0.075*sl 0.28 + 0.076*sl t r 0.38 0.29 + 0.041*sl 0.28 + 0.047*sl 0.21 + 0.054*sl t f 0.78 0.46 + 0.160*sl 0.45 + 0.163*sl 0.43 + 0.165*sl d to y t plh 0.20 0.14 + 0.032*sl 0.15 + 0.025*sl 0.16 + 0.025*sl t phl 0.43 0.28 + 0.073*sl 0.28 + 0.075*sl 0.27 + 0.076*sl t r 0.35 0.27 + 0.041*sl 0.26 + 0.047*sl 0.19 + 0.054*sl t f 0.78 0.46 + 0.159*sl 0.45 + 0.163*sl 0.43 + 0.165*sl e to y t plh 0.19 0.12 + 0.034*sl 0.14 + 0.025*sl 0.15 + 0.025*sl t phl 0.42 0.27 + 0.073*sl 0.27 + 0.075*sl 0.26 + 0.076*sl t r 0.34 0.25 + 0.043*sl 0.24 + 0.047*sl 0.18 + 0.054*sl t f 0.77 0.46 + 0.159*sl 0.45 + 0.163*sl 0.43 + 0.165*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.15 + 0.018*sl 0.16 + 0.014*sl 0.18 + 0.012*sl t phl 0.34 0.27 + 0.037*sl 0.26 + 0.038*sl 0.26 + 0.038*sl t r 0.37 0.32 + 0.021*sl 0.32 + 0.022*sl 0.28 + 0.027*sl t f 0.57 0.41 + 0.080*sl 0.40 + 0.081*sl 0.39 + 0.083*sl b to y t plh 0.19 0.15 + 0.017*sl 0.16 + 0.014*sl 0.17 + 0.012*sl t phl 0.35 0.27 + 0.037*sl 0.27 + 0.038*sl 0.27 + 0.038*sl t r 0.34 0.30 + 0.021*sl 0.30 + 0.022*sl 0.25 + 0.027*sl t f 0.57 0.42 + 0.079*sl 0.41 + 0.081*sl 0.39 + 0.083*sl c to y t plh 0.15 0.11 + 0.019*sl 0.12 + 0.015*sl 0.14 + 0.012*sl t phl 0.32 0.25 + 0.035*sl 0.25 + 0.037*sl 0.24 + 0.038*sl t r 0.28 0.24 + 0.021*sl 0.24 + 0.022*sl 0.19 + 0.027*sl t f 0.57 0.42 + 0.076*sl 0.41 + 0.080*sl 0.39 + 0.083*sl d to y t plh 0.18 0.14 + 0.017*sl 0.15 + 0.014*sl 0.16 + 0.012*sl t phl 0.34 0.27 + 0.038*sl 0.27 + 0.037*sl 0.26 + 0.038*sl t r 0.32 0.28 + 0.020*sl 0.28 + 0.022*sl 0.23 + 0.027*sl t f 0.58 0.42 + 0.077*sl 0.41 + 0.081*sl 0.39 + 0.083*sl e to y t plh 0.16 0.13 + 0.018*sl 0.13 + 0.014*sl 0.16 + 0.012*sl t phl 0.34 0.26 + 0.037*sl 0.26 + 0.037*sl 0.25 + 0.038*sl t r 0.30 0.26 + 0.022*sl 0.26 + 0.022*sl 0.21 + 0.027*sl t f 0.58 0.42 + 0.077*sl 0.42 + 0.080*sl 0.39 + 0.083*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
STD80/stdm80 3-32 sec asic nd5/nd5d2 5-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd5 stdm80 nd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.23 + 0.037*sl 0.23 + 0.036*sl 0.23 + 0.035*sl t phl 0.66 0.45 + 0.107*sl 0.45 + 0.107*sl 0.46 + 0.106*sl t r 0.50 0.37 + 0.068*sl 0.36 + 0.071*sl 0.34 + 0.073*sl t f 1.08 0.63 + 0.222*sl 0.63 + 0.223*sl 0.63 + 0.223*sl b to y t plh 0.29 0.22 + 0.036*sl 0.22 + 0.036*sl 0.23 + 0.035*sl t phl 0.66 0.44 + 0.107*sl 0.44 + 0.107*sl 0.45 + 0.106*sl t r 0.48 0.34 + 0.067*sl 0.33 + 0.071*sl 0.31 + 0.073*sl t f 1.08 0.63 + 0.222*sl 0.63 + 0.223*sl 0.63 + 0.223*sl c to y t plh 0.29 0.22 + 0.035*sl 0.22 + 0.035*sl 0.22 + 0.035*sl t phl 0.64 0.42 + 0.107*sl 0.42 + 0.107*sl 0.43 + 0.106*sl t r 0.45 0.32 + 0.067*sl 0.30 + 0.071*sl 0.28 + 0.074*sl t f 1.08 0.64 + 0.220*sl 0.63 + 0.223*sl 0.63 + 0.223*sl d to y t plh 0.27 0.20 + 0.035*sl 0.20 + 0.035*sl 0.20 + 0.035*sl t phl 0.61 0.39 + 0.107*sl 0.40 + 0.106*sl 0.40 + 0.106*sl t r 0.42 0.29 + 0.067*sl 0.28 + 0.071*sl 0.26 + 0.074*sl t f 1.08 0.64 + 0.220*sl 0.63 + 0.223*sl 0.63 + 0.223*sl e to y t plh 0.26 0.18 + 0.036*sl 0.19 + 0.035*sl 0.19 + 0.034*sl t phl 0.57 0.36 + 0.106*sl 0.36 + 0.106*sl 0.36 + 0.106*sl t r 0.40 0.27 + 0.067*sl 0.25 + 0.071*sl 0.24 + 0.074*sl t f 1.07 0.63 + 0.221*sl 0.62 + 0.224*sl 0.62 + 0.223*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.22 + 0.018*sl 0.22 + 0.018*sl 0.22 + 0.018*sl t phl 0.52 0.41 + 0.054*sl 0.41 + 0.054*sl 0.41 + 0.054*sl t r 0.41 0.35 + 0.033*sl 0.34 + 0.034*sl 0.33 + 0.035*sl t f 0.79 0.57 + 0.110*sl 0.56 + 0.111*sl 0.56 + 0.111*sl b to y t plh 0.25 0.21 + 0.018*sl 0.22 + 0.018*sl 0.22 + 0.018*sl t phl 0.52 0.41 + 0.054*sl 0.41 + 0.054*sl 0.41 + 0.054*sl t r 0.39 0.32 + 0.033*sl 0.32 + 0.034*sl 0.31 + 0.035*sl t f 0.79 0.57 + 0.109*sl 0.56 + 0.111*sl 0.56 + 0.111*sl c to y t plh 0.21 0.17 + 0.020*sl 0.18 + 0.017*sl 0.18 + 0.017*sl t phl 0.43 0.32 + 0.053*sl 0.32 + 0.053*sl 0.33 + 0.053*sl t r 0.31 0.25 + 0.033*sl 0.24 + 0.034*sl 0.23 + 0.036*sl t f 0.78 0.56 + 0.109*sl 0.56 + 0.111*sl 0.55 + 0.112*sl d to y t plh 0.24 0.20 + 0.018*sl 0.21 + 0.018*sl 0.21 + 0.017*sl t phl 0.49 0.38 + 0.054*sl 0.39 + 0.053*sl 0.39 + 0.054*sl t r 0.36 0.30 + 0.032*sl 0.29 + 0.033*sl 0.28 + 0.035*sl t f 0.79 0.57 + 0.109*sl 0.57 + 0.110*sl 0.56 + 0.111*sl e to y t plh 0.23 0.19 + 0.019*sl 0.19 + 0.017*sl 0.19 + 0.017*sl t phl 0.46 0.36 + 0.054*sl 0.36 + 0.053*sl 0.36 + 0.053*sl t r 0.34 0.27 + 0.031*sl 0.27 + 0.033*sl 0.25 + 0.035*sl t f 0.79 0.57 + 0.109*sl 0.57 + 0.110*sl 0.56 + 0.111*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-33 STD80/stdm80 nd6/nd6d2 6-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nd6 nd6d2 nd6 nd6d2 abcdefabcdef 0.6 0.4 0.5 0.6 0.6 0.6 0.6 0.4 0.6 0.6 0.6 0.6 4.0 4.3 stdm80 nd6 nd6d2 nd6 nd6d2 abcdefabcdef 0.7 0.8 0.8 0.8 0.7 0.7 0.7 0.8 0.8 0.8 0.7 0.7 4.0 4.3 b c d y e a f truth table abcdefy 0xxxxx1 x0xxxx1 xx0xxx1 xxx0xx1 xxxx0x1 xxxxx01 1111110
STD80/stdm80 3-34 sec asic nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.34 + 0.026*sl 0.34 + 0.024*sl 0.34 + 0.024*sl t phl 0.56 0.47 + 0.043*sl 0.48 + 0.038*sl 0.49 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.25 0.13 + 0.062*sl 0.12 + 0.066*sl 0.09 + 0.069*sl b to y t plh 0.35 0.30 + 0.026*sl 0.30 + 0.024*sl 0.30 + 0.024*sl t phl 0.58 0.50 + 0.043*sl 0.51 + 0.038*sl 0.52 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl c to y t plh 0.37 0.32 + 0.026*sl 0.32 + 0.024*sl 0.32 + 0.024*sl t phl 0.57 0.49 + 0.042*sl 0.50 + 0.038*sl 0.51 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl d to y t plh 0.38 0.33 + 0.027*sl 0.33 + 0.024*sl 0.33 + 0.024*sl t phl 0.61 0.52 + 0.043*sl 0.53 + 0.038*sl 0.54 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.25 0.13 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl e to y t plh 0.40 0.35 + 0.026*sl 0.35 + 0.024*sl 0.35 + 0.024*sl t phl 0.60 0.51 + 0.043*sl 0.52 + 0.038*sl 0.53 + 0.037*sl t r 0.19 0.10 + 0.047*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl f to y t plh 0.42 0.37 + 0.025*sl 0.37 + 0.024*sl 0.37 + 0.024*sl t phl 0.58 0.50 + 0.043*sl 0.51 + 0.038*sl 0.52 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-35 STD80/stdm80 nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.37 + 0.016*sl 0.37 + 0.013*sl 0.38 + 0.012*sl t phl 0.59 0.54 + 0.024*sl 0.54 + 0.021*sl 0.57 + 0.018*sl t r 0.14 0.10 + 0.019*sl 0.09 + 0.024*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.032*sl 0.15 + 0.031*sl 0.12 + 0.034*sl b to y t plh 0.36 0.33 + 0.016*sl 0.34 + 0.013*sl 0.34 + 0.012*sl t phl 0.61 0.56 + 0.025*sl 0.57 + 0.021*sl 0.59 + 0.018*sl t r 0.14 0.10 + 0.023*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.029*sl 0.15 + 0.031*sl 0.12 + 0.034*sl c to y t plh 0.38 0.35 + 0.016*sl 0.36 + 0.013*sl 0.36 + 0.012*sl t phl 0.60 0.55 + 0.025*sl 0.56 + 0.021*sl 0.58 + 0.018*sl t r 0.14 0.10 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.14 + 0.033*sl 0.15 + 0.031*sl 0.12 + 0.034*sl d to y t plh 0.39 0.36 + 0.017*sl 0.36 + 0.013*sl 0.38 + 0.012*sl t phl 0.63 0.58 + 0.025*sl 0.59 + 0.021*sl 0.62 + 0.018*sl t r 0.15 0.11 + 0.018*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.033*sl 0.15 + 0.031*sl 0.12 + 0.034*sl e to y t plh 0.41 0.38 + 0.017*sl 0.38 + 0.013*sl 0.39 + 0.012*sl t phl 0.62 0.57 + 0.025*sl 0.58 + 0.021*sl 0.61 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.12 + 0.034*sl f to y t plh 0.43 0.39 + 0.017*sl 0.40 + 0.013*sl 0.41 + 0.012*sl t phl 0.61 0.56 + 0.026*sl 0.57 + 0.021*sl 0.60 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.12 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-36 sec asic nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.53 0.46 + 0.035*sl 0.46 + 0.034*sl 0.46 + 0.033*sl t phl 0.81 0.70 + 0.055*sl 0.72 + 0.048*sl 0.74 + 0.045*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.082*sl 0.17 + 0.080*sl 0.17 + 0.081*sl b to y t plh 0.49 0.42 + 0.035*sl 0.42 + 0.034*sl 0.42 + 0.033*sl t phl 0.81 0.70 + 0.055*sl 0.72 + 0.048*sl 0.74 + 0.045*sl t r 0.25 0.12 + 0.067*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.082*sl 0.17 + 0.079*sl 0.17 + 0.081*sl c to y t plh 0.51 0.44 + 0.035*sl 0.44 + 0.034*sl 0.45 + 0.033*sl t phl 0.81 0.70 + 0.055*sl 0.73 + 0.048*sl 0.75 + 0.045*sl t r 0.25 0.12 + 0.069*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.082*sl 0.17 + 0.079*sl 0.17 + 0.081*sl d to y t plh 0.53 0.45 + 0.036*sl 0.46 + 0.034*sl 0.46 + 0.033*sl t phl 0.85 0.74 + 0.055*sl 0.76 + 0.048*sl 0.79 + 0.045*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.081*sl 0.17 + 0.080*sl 0.17 + 0.081*sl e to y t plh 0.55 0.48 + 0.036*sl 0.48 + 0.034*sl 0.49 + 0.033*sl t phl 0.86 0.75 + 0.055*sl 0.77 + 0.048*sl 0.79 + 0.045*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.34 0.18 + 0.081*sl 0.18 + 0.079*sl 0.17 + 0.080*sl f to y t plh 0.57 0.49 + 0.036*sl 0.50 + 0.034*sl 0.50 + 0.033*sl t phl 0.86 0.75 + 0.055*sl 0.77 + 0.048*sl 0.79 + 0.045*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.083*sl 0.18 + 0.079*sl 0.17 + 0.081*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-37 STD80/stdm80 nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.53 0.49 + 0.022*sl 0.50 + 0.018*sl 0.51 + 0.017*sl t phl 0.86 0.79 + 0.034*sl 0.81 + 0.028*sl 0.83 + 0.025*sl t r 0.18 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.27 0.19 + 0.042*sl 0.19 + 0.040*sl 0.21 + 0.038*sl b to y t plh 0.49 0.45 + 0.022*sl 0.46 + 0.018*sl 0.47 + 0.017*sl t phl 0.86 0.79 + 0.034*sl 0.81 + 0.028*sl 0.83 + 0.025*sl t r 0.18 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.27 0.18 + 0.044*sl 0.20 + 0.039*sl 0.20 + 0.038*sl c to y t plh 0.52 0.47 + 0.022*sl 0.48 + 0.018*sl 0.49 + 0.017*sl t phl 0.86 0.80 + 0.034*sl 0.81 + 0.028*sl 0.84 + 0.025*sl t r 0.18 0.12 + 0.032*sl 0.11 + 0.033*sl 0.11 + 0.034*sl t f 0.27 0.19 + 0.042*sl 0.19 + 0.040*sl 0.20 + 0.038*sl d to y t plh 0.53 0.49 + 0.022*sl 0.50 + 0.019*sl 0.51 + 0.017*sl t phl 0.91 0.84 + 0.034*sl 0.85 + 0.028*sl 0.88 + 0.025*sl t r 0.19 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.27 0.19 + 0.042*sl 0.20 + 0.039*sl 0.20 + 0.038*sl e to y t plh 0.55 0.51 + 0.022*sl 0.52 + 0.019*sl 0.53 + 0.017*sl t phl 0.91 0.84 + 0.034*sl 0.86 + 0.028*sl 0.88 + 0.025*sl t r 0.19 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.27 0.18 + 0.043*sl 0.20 + 0.039*sl 0.20 + 0.038*sl f to y t plh 0.57 0.53 + 0.022*sl 0.54 + 0.019*sl 0.55 + 0.017*sl t phl 0.91 0.84 + 0.034*sl 0.86 + 0.028*sl 0.88 + 0.025*sl t r 0.19 0.13 + 0.032*sl 0.12 + 0.033*sl 0.12 + 0.034*sl t f 0.27 0.19 + 0.044*sl 0.20 + 0.039*sl 0.21 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-38 sec asic nd8/nd8d2 8-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nd8 nd8d2 nd8 nd8d2 abcdefghabcdefgh 0.6 0.4 0.6 0.4 0.4 0.4 0.5 0.6 0.6 0.4 0.6 0.4 0.6 0.5 0.6 0.4 4.7 4.7 stdm80 nd8 nd8d2 nd8 nd8d2 abcdefghabcdefgh 0.7 0.5 0.7 0.7 0.6 0.6 0.6 0.7 0.7 0.8 0.8 0.8 0.7 0.6 0.7 0.6 4.7 4.7 c d e y f b g a h truth table abcdefghy 0xxxxxxx1 x0xxxxxx1 xx0xxxxx1 xxx0xxxx1 xxxx0xxx1 xxxxx0xx1 xxxxxx0x1 xxxxxxx01 111111110
sec asic 3-39 STD80/stdm80 nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.35 + 0.026*sl 0.35 + 0.024*sl 0.35 + 0.024*sl t phl 0.64 0.55 + 0.043*sl 0.56 + 0.038*sl 0.57 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.25 0.13 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl b to y t plh 0.37 0.32 + 0.025*sl 0.33 + 0.024*sl 0.33 + 0.024*sl t phl 0.65 0.56 + 0.042*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.25 0.13 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl c to y t plh 0.39 0.34 + 0.025*sl 0.34 + 0.024*sl 0.34 + 0.024*sl t phl 0.64 0.56 + 0.043*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.18 0.09 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.26 0.12 + 0.066*sl 0.13 + 0.066*sl 0.09 + 0.069*sl d to y t plh 0.35 0.30 + 0.026*sl 0.30 + 0.024*sl 0.31 + 0.024*sl t phl 0.64 0.56 + 0.043*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.25 0.13 + 0.063*sl 0.12 + 0.066*sl 0.09 + 0.069*sl e to y t plh 0.38 0.33 + 0.026*sl 0.34 + 0.024*sl 0.34 + 0.024*sl t phl 0.67 0.58 + 0.043*sl 0.59 + 0.038*sl 0.60 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl f to y t plh 0.40 0.35 + 0.026*sl 0.36 + 0.024*sl 0.36 + 0.024*sl t phl 0.67 0.58 + 0.043*sl 0.59 + 0.038*sl 0.61 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl g to y t plh 0.42 0.37 + 0.027*sl 0.37 + 0.024*sl 0.37 + 0.024*sl t phl 0.67 0.58 + 0.043*sl 0.59 + 0.038*sl 0.60 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl h to y t plh 0.43 0.38 + 0.027*sl 0.38 + 0.024*sl 0.38 + 0.024*sl t phl 0.66 0.57 + 0.043*sl 0.58 + 0.038*sl 0.60 + 0.037*sl t r 0.19 0.10 + 0.046*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.26 0.13 + 0.062*sl 0.12 + 0.066*sl 0.09 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-40 sec asic nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.41 0.38 + 0.016*sl 0.39 + 0.013*sl 0.39 + 0.012*sl t phl 0.67 0.62 + 0.025*sl 0.63 + 0.021*sl 0.65 + 0.018*sl t r 0.14 0.10 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.032*sl 0.15 + 0.031*sl 0.12 + 0.034*sl b to y t plh 0.38 0.35 + 0.016*sl 0.36 + 0.013*sl 0.37 + 0.012*sl t phl 0.68 0.63 + 0.025*sl 0.64 + 0.021*sl 0.66 + 0.018*sl t r 0.14 0.10 + 0.023*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.13 + 0.034*sl c to y t plh 0.40 0.37 + 0.016*sl 0.37 + 0.013*sl 0.38 + 0.012*sl t phl 0.67 0.62 + 0.025*sl 0.63 + 0.021*sl 0.66 + 0.018*sl t r 0.14 0.10 + 0.020*sl 0.09 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.13 + 0.034*sl d to y t plh 0.36 0.33 + 0.016*sl 0.34 + 0.013*sl 0.35 + 0.012*sl t phl 0.68 0.63 + 0.025*sl 0.64 + 0.021*sl 0.66 + 0.018*sl t r 0.14 0.10 + 0.019*sl 0.09 + 0.024*sl 0.07 + 0.026*sl t f 0.21 0.15 + 0.032*sl 0.15 + 0.031*sl 0.13 + 0.034*sl e to y t plh 0.44 0.41 + 0.017*sl 0.42 + 0.013*sl 0.43 + 0.012*sl t phl 0.69 0.64 + 0.025*sl 0.65 + 0.021*sl 0.68 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.22 0.16 + 0.030*sl 0.15 + 0.031*sl 0.13 + 0.034*sl f to y t plh 0.42 0.38 + 0.017*sl 0.39 + 0.013*sl 0.40 + 0.012*sl t phl 0.70 0.65 + 0.025*sl 0.66 + 0.021*sl 0.69 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.22 0.15 + 0.031*sl 0.15 + 0.031*sl 0.13 + 0.034*sl g to y t plh 0.43 0.40 + 0.017*sl 0.41 + 0.013*sl 0.42 + 0.012*sl t phl 0.70 0.65 + 0.026*sl 0.66 + 0.021*sl 0.69 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.08 + 0.026*sl t f 0.22 0.16 + 0.030*sl 0.15 + 0.031*sl 0.13 + 0.034*sl h to y t plh 0.40 0.36 + 0.017*sl 0.37 + 0.013*sl 0.38 + 0.012*sl t phl 0.70 0.65 + 0.026*sl 0.66 + 0.021*sl 0.69 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.22 0.15 + 0.031*sl 0.15 + 0.031*sl 0.13 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-41 STD80/stdm80 nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.55 0.48 + 0.035*sl 0.48 + 0.034*sl 0.49 + 0.033*sl t phl 0.94 0.83 + 0.055*sl 0.85 + 0.048*sl 0.87 + 0.045*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.082*sl 0.18 + 0.079*sl 0.17 + 0.080*sl b to y t plh 0.52 0.45 + 0.035*sl 0.45 + 0.034*sl 0.45 + 0.033*sl t phl 0.92 0.81 + 0.056*sl 0.83 + 0.048*sl 0.85 + 0.045*sl t r 0.25 0.12 + 0.067*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.082*sl 0.18 + 0.079*sl 0.17 + 0.080*sl c to y t plh 0.54 0.47 + 0.035*sl 0.47 + 0.034*sl 0.47 + 0.033*sl t phl 0.93 0.82 + 0.056*sl 0.85 + 0.048*sl 0.87 + 0.045*sl t r 0.25 0.12 + 0.068*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.082*sl 0.18 + 0.079*sl 0.17 + 0.080*sl d to y t plh 0.50 0.43 + 0.035*sl 0.43 + 0.034*sl 0.43 + 0.033*sl t phl 0.90 0.79 + 0.055*sl 0.81 + 0.048*sl 0.83 + 0.045*sl t r 0.25 0.12 + 0.068*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.33 0.17 + 0.082*sl 0.18 + 0.079*sl 0.17 + 0.080*sl e to y t plh 0.54 0.46 + 0.036*sl 0.47 + 0.034*sl 0.47 + 0.033*sl t phl 0.94 0.83 + 0.055*sl 0.85 + 0.048*sl 0.87 + 0.045*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.34 0.17 + 0.081*sl 0.18 + 0.079*sl 0.17 + 0.080*sl f to y t plh 0.56 0.49 + 0.036*sl 0.49 + 0.034*sl 0.50 + 0.033*sl t phl 0.96 0.85 + 0.056*sl 0.87 + 0.048*sl 0.90 + 0.045*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.34 0.17 + 0.081*sl 0.18 + 0.079*sl 0.17 + 0.080*sl g to y t plh 0.58 0.51 + 0.036*sl 0.51 + 0.034*sl 0.51 + 0.033*sl t phl 0.98 0.87 + 0.056*sl 0.89 + 0.048*sl 0.91 + 0.045*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.34 0.18 + 0.080*sl 0.18 + 0.079*sl 0.18 + 0.080*sl h to y t plh 0.59 0.52 + 0.036*sl 0.53 + 0.034*sl 0.53 + 0.033*sl t phl 0.98 0.87 + 0.056*sl 0.89 + 0.048*sl 0.91 + 0.045*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.34 0.17 + 0.082*sl 0.18 + 0.079*sl 0.17 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-42 sec asic nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.56 0.51 + 0.022*sl 0.52 + 0.019*sl 0.54 + 0.017*sl t phl 0.99 0.92 + 0.034*sl 0.94 + 0.028*sl 0.97 + 0.025*sl t r 0.18 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.28 0.19 + 0.043*sl 0.20 + 0.039*sl 0.21 + 0.038*sl b to y t plh 0.52 0.48 + 0.022*sl 0.49 + 0.018*sl 0.50 + 0.017*sl t phl 0.97 0.91 + 0.034*sl 0.92 + 0.028*sl 0.95 + 0.025*sl t r 0.18 0.12 + 0.032*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t f 0.28 0.19 + 0.042*sl 0.20 + 0.039*sl 0.21 + 0.038*sl c to y t plh 0.55 0.50 + 0.021*sl 0.51 + 0.018*sl 0.52 + 0.017*sl t phl 0.99 0.92 + 0.034*sl 0.94 + 0.029*sl 0.96 + 0.025*sl t r 0.18 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.035*sl t f 0.28 0.19 + 0.043*sl 0.20 + 0.039*sl 0.21 + 0.038*sl d to y t plh 0.50 0.46 + 0.021*sl 0.47 + 0.018*sl 0.48 + 0.017*sl t phl 0.95 0.89 + 0.034*sl 0.90 + 0.028*sl 0.93 + 0.025*sl t r 0.18 0.12 + 0.033*sl 0.11 + 0.033*sl 0.11 + 0.034*sl t f 0.28 0.19 + 0.043*sl 0.20 + 0.039*sl 0.21 + 0.038*sl e to y t plh 0.60 0.56 + 0.022*sl 0.57 + 0.019*sl 0.58 + 0.017*sl t phl 1.05 0.98 + 0.034*sl 0.99 + 0.028*sl 1.02 + 0.025*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.28 0.20 + 0.042*sl 0.20 + 0.039*sl 0.21 + 0.038*sl f to y t plh 0.57 0.52 + 0.022*sl 0.53 + 0.019*sl 0.55 + 0.017*sl t phl 1.03 0.96 + 0.034*sl 0.98 + 0.028*sl 1.00 + 0.025*sl t r 0.19 0.13 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.28 0.20 + 0.042*sl 0.21 + 0.039*sl 0.21 + 0.038*sl g to y t plh 0.59 0.54 + 0.022*sl 0.55 + 0.019*sl 0.57 + 0.017*sl t phl 1.04 0.97 + 0.034*sl 0.99 + 0.029*sl 1.02 + 0.025*sl t r 0.19 0.12 + 0.033*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.28 0.19 + 0.043*sl 0.21 + 0.039*sl 0.21 + 0.038*sl h to y t plh 0.55 0.50 + 0.022*sl 0.51 + 0.018*sl 0.52 + 0.017*sl t phl 1.00 0.94 + 0.034*sl 0.95 + 0.029*sl 0.98 + 0.025*sl t r 0.19 0.12 + 0.033*sl 0.13 + 0.033*sl 0.11 + 0.034*sl t f 0.28 0.20 + 0.042*sl 0.21 + 0.039*sl 0.21 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-43 STD80/stdm80 nr2/nr2d2 2-input nor with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr2 STD80 nr2d2 input load (sl) gate count STD80 nr2 nr2d2 nr2 nr2d2 abab 0.9 0.6 1.3 1.3 1.0 1.7 stdm80 nr2 nr2d2 nr2 nr2d2 abab 1.1 1.1 2.2 2.2 1.0 1.7 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.11 + 0.042*sl 0.12 + 0.037*sl 0.12 + 0.038*sl t phl 0.24 0.17 + 0.039*sl 0.17 + 0.036*sl 0.16 + 0.037*sl t r 0.36 0.22 + 0.070*sl 0.20 + 0.080*sl 0.14 + 0.086*sl t f 0.34 0.25 + 0.050*sl 0.22 + 0.062*sl 0.15 + 0.069*sl b to y t plh 0.20 0.11 + 0.045*sl 0.13 + 0.037*sl 0.13 + 0.038*sl t phl 0.21 0.12 + 0.044*sl 0.13 + 0.037*sl 0.13 + 0.037*sl t r 0.37 0.24 + 0.069*sl 0.21 + 0.079*sl 0.14 + 0.086*sl t f 0.28 0.17 + 0.054*sl 0.15 + 0.062*sl 0.09 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.15 0.10 + 0.025*sl 0.11 + 0.020*sl 0.12 + 0.019*sl t phl 0.16 0.12 + 0.024*sl 0.13 + 0.019*sl 0.14 + 0.018*sl t r 0.28 0.21 + 0.035*sl 0.21 + 0.037*sl 0.15 + 0.043*sl t f 0.24 0.19 + 0.029*sl 0.19 + 0.028*sl 0.13 + 0.034*sl b to y t plh 0.15 0.10 + 0.025*sl 0.11 + 0.020*sl 0.12 + 0.019*sl t phl 0.16 0.12 + 0.024*sl 0.13 + 0.019*sl 0.14 + 0.018*sl t r 0.28 0.21 + 0.035*sl 0.21 + 0.037*sl 0.15 + 0.043*sl t f 0.24 0.19 + 0.029*sl 0.19 + 0.028*sl 0.13 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aby 001 010 100 110
STD80/stdm80 3-44 sec asic nr2/nr2d2 2-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nr2 stdm80 nr2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.17 + 0.059*sl 0.18 + 0.057*sl 0.18 + 0.057*sl t phl 0.29 0.20 + 0.045*sl 0.20 + 0.045*sl 0.20 + 0.044*sl t r 0.47 0.23 + 0.117*sl 0.22 + 0.122*sl 0.20 + 0.125*sl t f 0.36 0.21 + 0.075*sl 0.20 + 0.079*sl 0.18 + 0.082*sl b to y t plh 0.27 0.15 + 0.059*sl 0.16 + 0.057*sl 0.16 + 0.057*sl t phl 0.24 0.15 + 0.047*sl 0.16 + 0.045*sl 0.16 + 0.044*sl t r 0.47 0.24 + 0.115*sl 0.22 + 0.121*sl 0.20 + 0.125*sl t f 0.29 0.15 + 0.074*sl 0.13 + 0.079*sl 0.11 + 0.082*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.14 + 0.033*sl 0.15 + 0.029*sl 0.15 + 0.028*sl t phl 0.19 0.14 + 0.027*sl 0.15 + 0.022*sl 0.16 + 0.021*sl t r 0.32 0.21 + 0.054*sl 0.20 + 0.059*sl 0.19 + 0.060*sl t f 0.23 0.17 + 0.033*sl 0.16 + 0.036*sl 0.14 + 0.038*sl b to y t plh 0.20 0.14 + 0.033*sl 0.15 + 0.029*sl 0.15 + 0.028*sl t phl 0.19 0.14 + 0.027*sl 0.15 + 0.022*sl 0.16 + 0.021*sl t r 0.32 0.21 + 0.054*sl 0.20 + 0.059*sl 0.19 + 0.060*sl t f 0.23 0.17 + 0.033*sl 0.16 + 0.036*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-45 STD80/stdm80 nr3/nr3d2 3-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nr3 nr3d2 nr3 nr3d2 abcabc 0.9 0.7 0.5 1.6 0.9 1.6 1.3 2.3 stdm80 nr3 nr3d2 nr3 nr3d2 abcabc 1.1 1.1 1.1 2.3 2.2 2.2 1.3 2.3 y a b c truth table abcy 0001 1xx0 x1x0 xx10
STD80/stdm80 3-46 sec asic nr3/nr3d2 3-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr3 STD80 nr3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.17 + 0.056*sl 0.18 + 0.054*sl 0.17 + 0.054*sl t phl 0.27 0.19 + 0.040*sl 0.20 + 0.038*sl 0.20 + 0.037*sl t r 0.52 0.29 + 0.113*sl 0.27 + 0.122*sl 0.23 + 0.125*sl t f 0.41 0.29 + 0.059*sl 0.28 + 0.063*sl 0.22 + 0.069*sl b to y t plh 0.28 0.17 + 0.057*sl 0.18 + 0.053*sl 0.17 + 0.054*sl t phl 0.25 0.17 + 0.040*sl 0.18 + 0.037*sl 0.18 + 0.037*sl t r 0.53 0.31 + 0.111*sl 0.29 + 0.120*sl 0.24 + 0.125*sl t f 0.35 0.25 + 0.050*sl 0.22 + 0.063*sl 0.16 + 0.069*sl c to y t plh 0.26 0.15 + 0.056*sl 0.16 + 0.053*sl 0.14 + 0.054*sl t phl 0.21 0.12 + 0.044*sl 0.14 + 0.037*sl 0.14 + 0.037*sl t r 0.53 0.31 + 0.110*sl 0.29 + 0.120*sl 0.23 + 0.125*sl t f 0.28 0.17 + 0.057*sl 0.16 + 0.063*sl 0.10 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.16 + 0.029*sl 0.16 + 0.027*sl 0.16 + 0.027*sl t phl 0.20 0.16 + 0.023*sl 0.17 + 0.019*sl 0.17 + 0.018*sl t r 0.38 0.27 + 0.051*sl 0.26 + 0.058*sl 0.22 + 0.063*sl t f 0.31 0.26 + 0.025*sl 0.25 + 0.029*sl 0.20 + 0.034*sl b to y t plh 0.19 0.13 + 0.031*sl 0.14 + 0.027*sl 0.14 + 0.027*sl t phl 0.15 0.09 + 0.027*sl 0.11 + 0.020*sl 0.13 + 0.018*sl t r 0.39 0.28 + 0.053*sl 0.27 + 0.057*sl 0.22 + 0.063*sl t f 0.21 0.16 + 0.029*sl 0.16 + 0.028*sl 0.11 + 0.034*sl c to y t plh 0.21 0.16 + 0.029*sl 0.16 + 0.027*sl 0.16 + 0.027*sl t phl 0.20 0.16 + 0.023*sl 0.17 + 0.019*sl 0.17 + 0.018*sl t r 0.38 0.28 + 0.050*sl 0.26 + 0.058*sl 0.22 + 0.063*sl t f 0.31 0.25 + 0.026*sl 0.25 + 0.029*sl 0.20 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-47 STD80/stdm80 nr3/nr3d2 3-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nr3 stdm80 nr3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.45 0.28 + 0.086*sl 0.28 + 0.085*sl 0.29 + 0.085*sl t phl 0.32 0.23 + 0.048*sl 0.23 + 0.046*sl 0.24 + 0.045*sl t r 0.74 0.38 + 0.180*sl 0.37 + 0.185*sl 0.35 + 0.186*sl t f 0.44 0.29 + 0.077*sl 0.28 + 0.080*sl 0.26 + 0.082*sl b to y t plh 0.42 0.25 + 0.086*sl 0.25 + 0.085*sl 0.25 + 0.085*sl t phl 0.30 0.21 + 0.045*sl 0.21 + 0.045*sl 0.22 + 0.044*sl t r 0.75 0.39 + 0.178*sl 0.38 + 0.183*sl 0.36 + 0.186*sl t f 0.37 0.22 + 0.076*sl 0.21 + 0.080*sl 0.19 + 0.082*sl c to y t plh 0.35 0.19 + 0.083*sl 0.18 + 0.084*sl 0.18 + 0.084*sl t phl 0.25 0.16 + 0.046*sl 0.17 + 0.044*sl 0.17 + 0.044*sl t r 0.74 0.38 + 0.179*sl 0.36 + 0.184*sl 0.34 + 0.187*sl t f 0.31 0.15 + 0.076*sl 0.14 + 0.079*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.33 0.24 + 0.044*sl 0.24 + 0.043*sl 0.24 + 0.043*sl t phl 0.24 0.19 + 0.024*sl 0.20 + 0.023*sl 0.20 + 0.022*sl t r 0.51 0.33 + 0.087*sl 0.32 + 0.090*sl 0.31 + 0.092*sl t f 0.30 0.23 + 0.036*sl 0.23 + 0.037*sl 0.22 + 0.039*sl b to y t plh 0.24 0.16 + 0.042*sl 0.16 + 0.042*sl 0.16 + 0.042*sl t phl 0.18 0.12 + 0.028*sl 0.14 + 0.022*sl 0.15 + 0.021*sl t r 0.50 0.32 + 0.087*sl 0.32 + 0.090*sl 0.30 + 0.092*sl t f 0.21 0.14 + 0.033*sl 0.13 + 0.037*sl 0.12 + 0.038*sl c to y t plh 0.32 0.24 + 0.044*sl 0.24 + 0.043*sl 0.24 + 0.043*sl t phl 0.24 0.19 + 0.024*sl 0.19 + 0.023*sl 0.20 + 0.022*sl t r 0.51 0.34 + 0.086*sl 0.32 + 0.090*sl 0.31 + 0.092*sl t f 0.30 0.23 + 0.035*sl 0.22 + 0.038*sl 0.22 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-48 sec asic nr4/nr4d2 4-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nr4 nr4d2 nr4 nr4d2 abcdabcd 0.6 0.8 0.9 0.9 1.6 1.3 1.3 1.6 1.7 2.3 stdm80 nr4 nr4d2 nr4 nr4d2 abcdabcd 1.1 1.1 1.1 1.0 2.2 2.1 2.2 2.1 1.7 2.3 y a b c d truth table abcdy 00001 1xxx0 x1xx0 xx1x0 xxx10
sec asic 3-49 STD80/stdm80 nr4/nr4d2 4-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr4 STD80 nr4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.17 + 0.067*sl 0.17 + 0.069*sl 0.15 + 0.071*sl t phl 0.21 0.13 + 0.044*sl 0.14 + 0.037*sl 0.14 + 0.037*sl t r 0.71 0.40 + 0.153*sl 0.39 + 0.161*sl 0.34 + 0.165*sl t f 0.29 0.17 + 0.055*sl 0.16 + 0.063*sl 0.10 + 0.069*sl b to y t plh 0.35 0.21 + 0.070*sl 0.21 + 0.070*sl 0.20 + 0.071*sl t phl 0.25 0.17 + 0.040*sl 0.18 + 0.037*sl 0.18 + 0.037*sl t r 0.73 0.42 + 0.152*sl 0.40 + 0.161*sl 0.36 + 0.165*sl t f 0.35 0.23 + 0.056*sl 0.22 + 0.063*sl 0.16 + 0.069*sl c to y t plh 0.38 0.24 + 0.072*sl 0.24 + 0.071*sl 0.24 + 0.071*sl t phl 0.28 0.20 + 0.040*sl 0.20 + 0.038*sl 0.21 + 0.037*sl t r 0.72 0.41 + 0.154*sl 0.40 + 0.161*sl 0.36 + 0.165*sl t f 0.41 0.29 + 0.060*sl 0.28 + 0.063*sl 0.22 + 0.069*sl d to y t plh 0.39 0.25 + 0.072*sl 0.25 + 0.071*sl 0.25 + 0.071*sl t phl 0.29 0.21 + 0.040*sl 0.21 + 0.039*sl 0.23 + 0.037*sl t r 0.71 0.40 + 0.155*sl 0.38 + 0.162*sl 0.36 + 0.165*sl t f 0.46 0.33 + 0.062*sl 0.33 + 0.065*sl 0.29 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.21 + 0.037*sl 0.22 + 0.035*sl 0.21 + 0.035*sl t phl 0.21 0.17 + 0.023*sl 0.17 + 0.019*sl 0.19 + 0.018*sl t r 0.52 0.38 + 0.073*sl 0.37 + 0.079*sl 0.33 + 0.082*sl t f 0.33 0.27 + 0.027*sl 0.27 + 0.030*sl 0.23 + 0.034*sl b to y t plh 0.26 0.19 + 0.037*sl 0.19 + 0.035*sl 0.18 + 0.035*sl t phl 0.19 0.14 + 0.024*sl 0.15 + 0.020*sl 0.16 + 0.018*sl t r 0.52 0.37 + 0.073*sl 0.36 + 0.079*sl 0.32 + 0.082*sl t f 0.27 0.22 + 0.029*sl 0.22 + 0.029*sl 0.17 + 0.034*sl c to y t plh 0.26 0.19 + 0.037*sl 0.19 + 0.035*sl 0.18 + 0.035*sl t phl 0.19 0.14 + 0.024*sl 0.15 + 0.020*sl 0.16 + 0.018*sl t r 0.52 0.37 + 0.074*sl 0.36 + 0.079*sl 0.32 + 0.082*sl t f 0.28 0.22 + 0.029*sl 0.22 + 0.029*sl 0.18 + 0.034*sl d to y t plh 0.29 0.21 + 0.037*sl 0.22 + 0.035*sl 0.21 + 0.035*sl t phl 0.21 0.17 + 0.023*sl 0.17 + 0.019*sl 0.19 + 0.018*sl t r 0.52 0.38 + 0.074*sl 0.37 + 0.079*sl 0.33 + 0.082*sl t f 0.33 0.27 + 0.028*sl 0.27 + 0.030*sl 0.23 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-50 sec asic nr4/nr4d2 4-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nr4 stdm80 nr4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.41 0.20 + 0.109*sl 0.19 + 0.112*sl 0.19 + 0.112*sl t phl 0.26 0.17 + 0.046*sl 0.17 + 0.044*sl 0.17 + 0.044*sl t r 1.02 0.53 + 0.243*sl 0.52 + 0.248*sl 0.50 + 0.250*sl t f 0.31 0.16 + 0.075*sl 0.15 + 0.079*sl 0.12 + 0.082*sl b to y t plh 0.53 0.30 + 0.114*sl 0.30 + 0.113*sl 0.30 + 0.112*sl t phl 0.31 0.21 + 0.046*sl 0.22 + 0.045*sl 0.22 + 0.044*sl t r 1.06 0.58 + 0.239*sl 0.56 + 0.245*sl 0.55 + 0.247*sl t f 0.37 0.22 + 0.076*sl 0.21 + 0.080*sl 0.19 + 0.082*sl c to y t plh 0.61 0.38 + 0.114*sl 0.38 + 0.113*sl 0.39 + 0.112*sl t phl 0.33 0.24 + 0.048*sl 0.24 + 0.047*sl 0.25 + 0.045*sl t r 1.06 0.58 + 0.240*sl 0.56 + 0.245*sl 0.55 + 0.247*sl t f 0.44 0.28 + 0.079*sl 0.28 + 0.080*sl 0.26 + 0.083*sl d to y t plh 0.64 0.41 + 0.114*sl 0.42 + 0.113*sl 0.42 + 0.112*sl t phl 0.34 0.24 + 0.051*sl 0.25 + 0.048*sl 0.26 + 0.047*sl t r 1.05 0.57 + 0.241*sl 0.56 + 0.245*sl 0.55 + 0.247*sl t f 0.50 0.33 + 0.082*sl 0.33 + 0.082*sl 0.33 + 0.083*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.32 + 0.058*sl 0.33 + 0.057*sl 0.33 + 0.057*sl t phl 0.25 0.20 + 0.024*sl 0.20 + 0.023*sl 0.21 + 0.023*sl t r 0.76 0.53 + 0.113*sl 0.51 + 0.119*sl 0.49 + 0.122*sl t f 0.33 0.25 + 0.038*sl 0.25 + 0.038*sl 0.25 + 0.039*sl b to y t plh 0.37 0.25 + 0.057*sl 0.26 + 0.056*sl 0.26 + 0.056*sl t phl 0.22 0.17 + 0.025*sl 0.18 + 0.023*sl 0.18 + 0.022*sl t r 0.75 0.52 + 0.115*sl 0.50 + 0.120*sl 0.49 + 0.123*sl t f 0.27 0.20 + 0.038*sl 0.20 + 0.038*sl 0.19 + 0.039*sl c to y t plh 0.37 0.26 + 0.057*sl 0.26 + 0.056*sl 0.26 + 0.056*sl t phl 0.22 0.17 + 0.025*sl 0.18 + 0.023*sl 0.18 + 0.022*sl t r 0.75 0.52 + 0.116*sl 0.51 + 0.120*sl 0.49 + 0.123*sl t f 0.28 0.20 + 0.037*sl 0.20 + 0.038*sl 0.19 + 0.039*sl d to y t plh 0.44 0.33 + 0.059*sl 0.33 + 0.057*sl 0.33 + 0.057*sl t phl 0.25 0.20 + 0.024*sl 0.20 + 0.023*sl 0.21 + 0.023*sl t r 0.76 0.53 + 0.113*sl 0.52 + 0.119*sl 0.50 + 0.122*sl t f 0.33 0.25 + 0.038*sl 0.25 + 0.039*sl 0.25 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-51 STD80/stdm80 nr5/nr5d2 5-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nr5 nr5d2 nr5 nr5d2 abcdeabcde 0.6 0.4 0.5 0.4 0.4 0.6 0.4 0.5 0.4 0.4 3.7 3.7 stdm80 nr5 nr5d2 nr5 nr5d2 abcdeabcde 0.7 0.8 0.8 0.8 0.7 0.7 0.8 0.8 0.8 0.7 3.7 3.7 y b c d e a truth table abcdey 000001 1xxxx0 x1xxx0 xx1xx0 xxx1x0 xxxx10
STD80/stdm80 3-52 sec asic nr5/nr5d2 5-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr5 STD80 nr5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.56 0.50 + 0.029*sl 0.51 + 0.025*sl 0.52 + 0.024*sl t phl 0.42 0.34 + 0.039*sl 0.35 + 0.037*sl 0.35 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.068*sl 0.07 + 0.069*sl b to y t plh 0.54 0.48 + 0.029*sl 0.49 + 0.025*sl 0.50 + 0.024*sl t phl 0.37 0.29 + 0.039*sl 0.30 + 0.037*sl 0.30 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl c to y t plh 0.56 0.50 + 0.029*sl 0.51 + 0.025*sl 0.52 + 0.024*sl t phl 0.40 0.33 + 0.039*sl 0.33 + 0.037*sl 0.33 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.08 + 0.066*sl 0.08 + 0.068*sl 0.07 + 0.069*sl d to y t plh 0.47 0.41 + 0.029*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.39 0.31 + 0.039*sl 0.31 + 0.037*sl 0.31 + 0.037*sl t r 0.20 0.11 + 0.048*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl e to y t plh 0.46 0.40 + 0.029*sl 0.41 + 0.025*sl 0.42 + 0.024*sl t phl 0.42 0.34 + 0.039*sl 0.34 + 0.037*sl 0.34 + 0.037*sl t r 0.20 0.11 + 0.048*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.58 0.55 + 0.019*sl 0.56 + 0.014*sl 0.58 + 0.012*sl t phl 0.42 0.37 + 0.022*sl 0.38 + 0.019*sl 0.39 + 0.018*sl t r 0.18 0.14 + 0.021*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl b to y t plh 0.57 0.53 + 0.019*sl 0.54 + 0.014*sl 0.56 + 0.012*sl t phl 0.37 0.32 + 0.022*sl 0.33 + 0.019*sl 0.34 + 0.018*sl t r 0.18 0.14 + 0.022*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.15 0.09 + 0.032*sl 0.09 + 0.032*sl 0.07 + 0.034*sl c to y t plh 0.59 0.55 + 0.019*sl 0.56 + 0.014*sl 0.58 + 0.012*sl t phl 0.40 0.36 + 0.022*sl 0.36 + 0.019*sl 0.37 + 0.018*sl t r 0.18 0.13 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.09 + 0.031*sl 0.07 + 0.034*sl d to y t plh 0.49 0.45 + 0.018*sl 0.46 + 0.014*sl 0.49 + 0.012*sl t phl 0.38 0.34 + 0.023*sl 0.34 + 0.019*sl 0.35 + 0.018*sl t r 0.18 0.13 + 0.022*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl e to y t plh 0.48 0.44 + 0.019*sl 0.45 + 0.014*sl 0.48 + 0.012*sl t phl 0.41 0.37 + 0.022*sl 0.37 + 0.019*sl 0.39 + 0.018*sl t r 0.18 0.13 + 0.022*sl 0.13 + 0.023*sl 0.10 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-53 STD80/stdm80 nr5/nr5d2 5-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) stdm80 nr5 stdm80 nr5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.85 0.77 + 0.040*sl 0.79 + 0.035*sl 0.80 + 0.034*sl t phl 0.56 0.47 + 0.048*sl 0.48 + 0.045*sl 0.48 + 0.044*sl t r 0.29 0.16 + 0.066*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl b to y t plh 0.76 0.68 + 0.040*sl 0.69 + 0.035*sl 0.70 + 0.034*sl t phl 0.51 0.42 + 0.049*sl 0.43 + 0.045*sl 0.43 + 0.044*sl t r 0.29 0.16 + 0.068*sl 0.16 + 0.068*sl 0.14 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl c to y t plh 0.82 0.74 + 0.040*sl 0.75 + 0.035*sl 0.77 + 0.034*sl t phl 0.55 0.45 + 0.048*sl 0.46 + 0.045*sl 0.46 + 0.044*sl t r 0.29 0.16 + 0.067*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.11 + 0.081*sl 0.10 + 0.083*sl d to y t plh 0.64 0.56 + 0.040*sl 0.57 + 0.035*sl 0.58 + 0.033*sl t phl 0.53 0.43 + 0.048*sl 0.44 + 0.045*sl 0.45 + 0.044*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.13 + 0.078*sl 0.12 + 0.081*sl 0.10 + 0.083*sl e to y t plh 0.65 0.57 + 0.040*sl 0.59 + 0.035*sl 0.60 + 0.033*sl t phl 0.56 0.46 + 0.048*sl 0.47 + 0.045*sl 0.48 + 0.044*sl t r 0.28 0.15 + 0.068*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.081*sl 0.11 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.89 0.84 + 0.026*sl 0.85 + 0.021*sl 0.87 + 0.019*sl t phl 0.56 0.50 + 0.029*sl 0.52 + 0.025*sl 0.53 + 0.022*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.033*sl 0.17 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.12 + 0.038*sl 0.12 + 0.039*sl b to y t plh 0.79 0.74 + 0.026*sl 0.76 + 0.021*sl 0.78 + 0.019*sl t phl 0.51 0.46 + 0.029*sl 0.47 + 0.024*sl 0.48 + 0.022*sl t r 0.24 0.17 + 0.033*sl 0.17 + 0.034*sl 0.17 + 0.033*sl t f 0.20 0.12 + 0.041*sl 0.13 + 0.037*sl 0.12 + 0.039*sl c to y t plh 0.86 0.80 + 0.026*sl 0.82 + 0.021*sl 0.84 + 0.019*sl t phl 0.55 0.49 + 0.029*sl 0.50 + 0.024*sl 0.52 + 0.022*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.033*sl 0.17 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.12 + 0.038*sl 0.12 + 0.039*sl d to y t plh 0.67 0.62 + 0.025*sl 0.63 + 0.021*sl 0.65 + 0.019*sl t phl 0.53 0.47 + 0.029*sl 0.48 + 0.024*sl 0.50 + 0.022*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.20 0.12 + 0.038*sl 0.12 + 0.038*sl 0.12 + 0.039*sl e to y t plh 0.68 0.63 + 0.025*sl 0.65 + 0.021*sl 0.66 + 0.019*sl t phl 0.56 0.50 + 0.029*sl 0.51 + 0.024*sl 0.53 + 0.022*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.20 0.13 + 0.037*sl 0.12 + 0.038*sl 0.12 + 0.038*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-54 sec asic nr6/nr6d2 6-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nr6 nr6d2 nr6 nr6d2 abcdefabcdef 0.6 0.4 0.4 0.6 0.6 0.4 0.6 0.4 0.4 0.6 0.6 0.4 4.3 4.7 stdm80 nr6 nr6d2 nr6 nr6d2 abcdefabcdef 0.7 0.8 0.8 0.7 0.8 0.8 0.7 0.8 0.8 0.7 0.7 0.8 4.3 4.7 y b c d e a f truth table abcdefy 0000001 1xxxxx0 x1xxxx0 xx1xxx0 xxx1xx0 xxxx1x0 xxxxx10
sec asic 3-55 STD80/stdm80 nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.55 0.48 + 0.034*sl 0.49 + 0.026*sl 0.52 + 0.024*sl t phl 0.45 0.37 + 0.041*sl 0.37 + 0.038*sl 0.38 + 0.037*sl t r 0.24 0.15 + 0.047*sl 0.14 + 0.048*sl 0.11 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl b to y t plh 0.55 0.49 + 0.033*sl 0.50 + 0.026*sl 0.53 + 0.024*sl t phl 0.42 0.33 + 0.041*sl 0.34 + 0.038*sl 0.35 + 0.037*sl t r 0.24 0.15 + 0.044*sl 0.14 + 0.048*sl 0.11 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl c to y t plh 0.55 0.48 + 0.033*sl 0.50 + 0.026*sl 0.52 + 0.024*sl t phl 0.40 0.32 + 0.040*sl 0.33 + 0.038*sl 0.33 + 0.037*sl t r 0.24 0.15 + 0.047*sl 0.14 + 0.048*sl 0.11 + 0.052*sl t f 0.23 0.10 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d to y t plh 0.54 0.48 + 0.033*sl 0.49 + 0.026*sl 0.52 + 0.024*sl t phl 0.43 0.35 + 0.040*sl 0.36 + 0.038*sl 0.36 + 0.037*sl t r 0.24 0.15 + 0.047*sl 0.14 + 0.048*sl 0.11 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.07 + 0.069*sl e to y t plh 0.55 0.48 + 0.033*sl 0.50 + 0.026*sl 0.52 + 0.024*sl t phl 0.42 0.34 + 0.040*sl 0.35 + 0.038*sl 0.35 + 0.037*sl t r 0.24 0.15 + 0.046*sl 0.14 + 0.048*sl 0.11 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl f to y t plh 0.55 0.49 + 0.033*sl 0.50 + 0.026*sl 0.53 + 0.024*sl t phl 0.39 0.31 + 0.040*sl 0.32 + 0.038*sl 0.32 + 0.037*sl t r 0.24 0.15 + 0.046*sl 0.14 + 0.049*sl 0.11 + 0.052*sl t f 0.23 0.09 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-56 sec asic nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.53 + 0.022*sl 0.54 + 0.016*sl 0.58 + 0.012*sl t phl 0.44 0.39 + 0.023*sl 0.40 + 0.020*sl 0.41 + 0.018*sl t r 0.22 0.17 + 0.023*sl 0.17 + 0.023*sl 0.15 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl b to y t plh 0.58 0.53 + 0.022*sl 0.55 + 0.016*sl 0.59 + 0.012*sl t phl 0.41 0.36 + 0.023*sl 0.37 + 0.020*sl 0.38 + 0.018*sl t r 0.22 0.17 + 0.025*sl 0.17 + 0.023*sl 0.15 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl c to y t plh 0.57 0.53 + 0.023*sl 0.54 + 0.016*sl 0.58 + 0.012*sl t phl 0.39 0.35 + 0.023*sl 0.35 + 0.020*sl 0.37 + 0.018*sl t r 0.22 0.17 + 0.025*sl 0.17 + 0.023*sl 0.15 + 0.026*sl t f 0.17 0.10 + 0.033*sl 0.10 + 0.031*sl 0.08 + 0.034*sl d to y t plh 0.57 0.52 + 0.022*sl 0.54 + 0.016*sl 0.58 + 0.012*sl t phl 0.42 0.38 + 0.023*sl 0.38 + 0.020*sl 0.40 + 0.018*sl t r 0.22 0.17 + 0.026*sl 0.17 + 0.023*sl 0.15 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl e to y t plh 0.58 0.53 + 0.022*sl 0.54 + 0.016*sl 0.59 + 0.012*sl t phl 0.42 0.37 + 0.023*sl 0.38 + 0.020*sl 0.39 + 0.018*sl t r 0.22 0.17 + 0.023*sl 0.17 + 0.024*sl 0.15 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.08 + 0.034*sl f to y t plh 0.58 0.54 + 0.022*sl 0.55 + 0.016*sl 0.59 + 0.012*sl t phl 0.39 0.34 + 0.023*sl 0.35 + 0.019*sl 0.36 + 0.018*sl t r 0.22 0.17 + 0.023*sl 0.17 + 0.024*sl 0.15 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.032*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-57 STD80/stdm80 nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nr6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.79 0.70 + 0.046*sl 0.72 + 0.038*sl 0.75 + 0.035*sl t phl 0.61 0.51 + 0.051*sl 0.52 + 0.046*sl 0.54 + 0.044*sl t r 0.33 0.19 + 0.070*sl 0.20 + 0.068*sl 0.19 + 0.069*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.080*sl 0.13 + 0.082*sl b to y t plh 0.78 0.68 + 0.046*sl 0.71 + 0.038*sl 0.73 + 0.035*sl t phl 0.58 0.48 + 0.051*sl 0.49 + 0.046*sl 0.50 + 0.044*sl t r 0.33 0.19 + 0.071*sl 0.20 + 0.068*sl 0.19 + 0.069*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.080*sl 0.13 + 0.082*sl c to y t plh 0.77 0.68 + 0.046*sl 0.70 + 0.038*sl 0.72 + 0.035*sl t phl 0.56 0.46 + 0.050*sl 0.47 + 0.046*sl 0.48 + 0.044*sl t r 0.33 0.19 + 0.071*sl 0.20 + 0.068*sl 0.19 + 0.070*sl t f 0.30 0.14 + 0.079*sl 0.13 + 0.080*sl 0.12 + 0.082*sl d to y t plh 0.79 0.70 + 0.045*sl 0.72 + 0.038*sl 0.74 + 0.035*sl t phl 0.59 0.49 + 0.050*sl 0.50 + 0.046*sl 0.51 + 0.044*sl t r 0.33 0.19 + 0.071*sl 0.20 + 0.069*sl 0.19 + 0.069*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.12 + 0.082*sl e to y t plh 0.80 0.70 + 0.045*sl 0.73 + 0.038*sl 0.75 + 0.035*sl t phl 0.58 0.48 + 0.050*sl 0.49 + 0.046*sl 0.50 + 0.044*sl t r 0.33 0.19 + 0.071*sl 0.20 + 0.068*sl 0.19 + 0.070*sl t f 0.29 0.13 + 0.081*sl 0.13 + 0.080*sl 0.12 + 0.082*sl f to y t plh 0.78 0.69 + 0.046*sl 0.71 + 0.038*sl 0.73 + 0.035*sl t phl 0.55 0.45 + 0.050*sl 0.46 + 0.046*sl 0.47 + 0.044*sl t r 0.34 0.20 + 0.070*sl 0.20 + 0.068*sl 0.19 + 0.069*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-58 sec asic nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nr6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.82 0.76 + 0.030*sl 0.78 + 0.024*sl 0.81 + 0.021*sl t phl 0.60 0.54 + 0.031*sl 0.55 + 0.026*sl 0.57 + 0.023*sl t r 0.28 0.20 + 0.036*sl 0.21 + 0.036*sl 0.21 + 0.035*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.038*sl b to y t plh 0.81 0.75 + 0.030*sl 0.77 + 0.024*sl 0.79 + 0.020*sl t phl 0.57 0.51 + 0.030*sl 0.52 + 0.026*sl 0.54 + 0.023*sl t r 0.28 0.20 + 0.037*sl 0.21 + 0.035*sl 0.22 + 0.034*sl t f 0.22 0.13 + 0.042*sl 0.15 + 0.038*sl 0.14 + 0.038*sl c to y t plh 0.80 0.74 + 0.030*sl 0.76 + 0.024*sl 0.78 + 0.020*sl t phl 0.55 0.48 + 0.031*sl 0.50 + 0.025*sl 0.52 + 0.023*sl t r 0.28 0.20 + 0.037*sl 0.21 + 0.035*sl 0.22 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.13 + 0.039*sl 0.14 + 0.038*sl d to y t plh 0.82 0.76 + 0.030*sl 0.78 + 0.024*sl 0.80 + 0.020*sl t phl 0.58 0.52 + 0.030*sl 0.53 + 0.025*sl 0.55 + 0.023*sl t r 0.28 0.20 + 0.037*sl 0.21 + 0.036*sl 0.22 + 0.034*sl t f 0.21 0.13 + 0.039*sl 0.13 + 0.039*sl 0.14 + 0.038*sl e to y t plh 0.83 0.77 + 0.029*sl 0.79 + 0.024*sl 0.81 + 0.020*sl t phl 0.57 0.51 + 0.030*sl 0.52 + 0.025*sl 0.54 + 0.023*sl t r 0.28 0.20 + 0.038*sl 0.21 + 0.036*sl 0.22 + 0.034*sl t f 0.21 0.12 + 0.042*sl 0.13 + 0.038*sl 0.13 + 0.038*sl f to y t plh 0.82 0.75 + 0.030*sl 0.77 + 0.024*sl 0.80 + 0.020*sl t phl 0.54 0.48 + 0.030*sl 0.49 + 0.025*sl 0.51 + 0.023*sl t r 0.28 0.20 + 0.038*sl 0.21 + 0.036*sl 0.22 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.13 + 0.039*sl 0.13 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-59 STD80/stdm80 nr8/nr8d2 8-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 nr8 nr8d2 nr8 nr8 d2 abcde fghabcde fgh 0.6 0.5 0.5 0.4 0.4 0.6 0.6 0.6 0.6 0.5 0.5 0.4 0.4 0.6 0.6 0.6 4.3 4.7 stdm80 nr8 nr8d2 nr8 nr8 d2 abcde fghabcde fgh 0.7 0.7 0.7 0.8 0.8 0.7 0.7 0.7 0.7 0.8 0.7 0.8 0.8 0.7 0.7 0.7 4.3 4.7 y c d e f b g a h truth table abcdefghy 000000001 1xxxxxxx0 x1xxxxxx0 xx1xxxxx0 xxx1xxxx0 xxxx1xxx0 xxxxx1xx0 xxxxxx1x0 xxxxxxx10
STD80/stdm80 3-60 sec asic nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.60 + 0.029*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t phl 0.45 0.37 + 0.039*sl 0.38 + 0.037*sl 0.38 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl b to y t plh 0.65 0.59 + 0.029*sl 0.60 + 0.025*sl 0.61 + 0.024*sl t phl 0.44 0.36 + 0.040*sl 0.37 + 0.037*sl 0.37 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.10 + 0.060*sl 0.09 + 0.068*sl 0.07 + 0.069*sl c to y t plh 0.63 0.57 + 0.030*sl 0.58 + 0.025*sl 0.59 + 0.024*sl t phl 0.42 0.35 + 0.039*sl 0.35 + 0.037*sl 0.35 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d to y t plh 0.59 0.53 + 0.030*sl 0.54 + 0.025*sl 0.55 + 0.024*sl t phl 0.39 0.31 + 0.039*sl 0.32 + 0.037*sl 0.32 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.068*sl 0.07 + 0.069*sl e to y t plh 0.62 0.56 + 0.029*sl 0.57 + 0.025*sl 0.58 + 0.024*sl t phl 0.38 0.30 + 0.040*sl 0.31 + 0.037*sl 0.31 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl f to y t plh 0.68 0.62 + 0.029*sl 0.63 + 0.025*sl 0.64 + 0.024*sl t phl 0.43 0.35 + 0.039*sl 0.36 + 0.037*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.09 + 0.066*sl 0.08 + 0.068*sl 0.07 + 0.069*sl g to y t plh 0.66 0.60 + 0.029*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t phl 0.42 0.34 + 0.039*sl 0.34 + 0.037*sl 0.34 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl h to y t plh 0.69 0.63 + 0.029*sl 0.64 + 0.025*sl 0.65 + 0.024*sl t phl 0.44 0.36 + 0.039*sl 0.37 + 0.037*sl 0.37 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.09 + 0.066*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-61 STD80/stdm80 nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nr8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.68 0.64 + 0.019*sl 0.65 + 0.015*sl 0.68 + 0.012*sl t phl 0.44 0.40 + 0.022*sl 0.41 + 0.019*sl 0.42 + 0.018*sl t r 0.19 0.14 + 0.022*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.07 + 0.034*sl b to y t plh 0.67 0.63 + 0.019*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t phl 0.44 0.39 + 0.023*sl 0.40 + 0.019*sl 0.41 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl c to y t plh 0.65 0.61 + 0.019*sl 0.62 + 0.015*sl 0.64 + 0.012*sl t phl 0.42 0.37 + 0.022*sl 0.38 + 0.019*sl 0.39 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.09 + 0.031*sl 0.07 + 0.034*sl d to y t plh 0.61 0.57 + 0.019*sl 0.58 + 0.015*sl 0.61 + 0.012*sl t phl 0.39 0.34 + 0.022*sl 0.35 + 0.019*sl 0.36 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.09 + 0.031*sl 0.07 + 0.034*sl e to y t plh 0.65 0.61 + 0.020*sl 0.62 + 0.014*sl 0.65 + 0.012*sl t phl 0.38 0.33 + 0.022*sl 0.34 + 0.019*sl 0.35 + 0.018*sl t r 0.19 0.15 + 0.021*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.15 0.09 + 0.032*sl 0.09 + 0.032*sl 0.07 + 0.034*sl f to y t plh 0.71 0.68 + 0.019*sl 0.69 + 0.014*sl 0.71 + 0.012*sl t phl 0.43 0.38 + 0.022*sl 0.39 + 0.019*sl 0.40 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.022*sl 0.12 + 0.026*sl t f 0.15 0.09 + 0.029*sl 0.09 + 0.032*sl 0.07 + 0.034*sl g to y t plh 0.69 0.65 + 0.019*sl 0.66 + 0.014*sl 0.69 + 0.012*sl t phl 0.41 0.37 + 0.022*sl 0.37 + 0.019*sl 0.38 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.022*sl 0.12 + 0.026*sl t f 0.15 0.09 + 0.029*sl 0.09 + 0.032*sl 0.07 + 0.034*sl h to y t plh 0.72 0.68 + 0.019*sl 0.69 + 0.014*sl 0.72 + 0.012*sl t phl 0.44 0.39 + 0.023*sl 0.40 + 0.019*sl 0.41 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.09 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-62 sec asic nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nr8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.05 0.97 + 0.041*sl 0.98 + 0.035*sl 1.00 + 0.034*sl t phl 0.60 0.50 + 0.049*sl 0.51 + 0.045*sl 0.52 + 0.044*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl b to y t plh 1.01 0.93 + 0.041*sl 0.95 + 0.036*sl 0.96 + 0.034*sl t phl 0.59 0.50 + 0.048*sl 0.51 + 0.045*sl 0.51 + 0.044*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.28 0.13 + 0.078*sl 0.12 + 0.081*sl 0.11 + 0.082*sl c to y t plh 0.93 0.85 + 0.041*sl 0.87 + 0.035*sl 0.88 + 0.034*sl t phl 0.58 0.48 + 0.048*sl 0.49 + 0.045*sl 0.49 + 0.044*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d to y t plh 0.83 0.75 + 0.041*sl 0.76 + 0.036*sl 0.78 + 0.034*sl t phl 0.54 0.45 + 0.048*sl 0.46 + 0.045*sl 0.46 + 0.044*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.15 + 0.071*sl t f 0.28 0.12 + 0.081*sl 0.12 + 0.081*sl 0.11 + 0.083*sl e to y t plh 0.88 0.80 + 0.041*sl 0.81 + 0.035*sl 0.82 + 0.034*sl t phl 0.53 0.43 + 0.048*sl 0.44 + 0.045*sl 0.45 + 0.044*sl t r 0.30 0.17 + 0.066*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl f to y t plh 1.07 0.98 + 0.041*sl 1.00 + 0.035*sl 1.01 + 0.034*sl t phl 0.58 0.48 + 0.048*sl 0.49 + 0.045*sl 0.50 + 0.044*sl t r 0.30 0.17 + 0.066*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.11 + 0.083*sl g to y t plh 0.98 0.90 + 0.041*sl 0.92 + 0.035*sl 0.93 + 0.034*sl t phl 0.56 0.46 + 0.048*sl 0.47 + 0.045*sl 0.48 + 0.044*sl t r 0.30 0.17 + 0.066*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.28 0.12 + 0.079*sl 0.11 + 0.081*sl 0.10 + 0.083*sl h to y t plh 1.10 1.02 + 0.041*sl 1.04 + 0.035*sl 1.05 + 0.034*sl t phl 0.58 0.49 + 0.048*sl 0.50 + 0.045*sl 0.50 + 0.044*sl t r 0.30 0.17 + 0.066*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.28 0.13 + 0.078*sl 0.12 + 0.081*sl 0.10 + 0.083*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-63 STD80/stdm80 nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nr8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.08 1.02 + 0.026*sl 1.04 + 0.022*sl 1.06 + 0.019*sl t phl 0.60 0.54 + 0.029*sl 0.55 + 0.025*sl 0.57 + 0.022*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.034*sl 0.18 + 0.033*sl t f 0.21 0.12 + 0.040*sl 0.14 + 0.037*sl 0.12 + 0.038*sl b to y t plh 1.04 0.99 + 0.026*sl 1.00 + 0.021*sl 1.02 + 0.019*sl t phl 0.59 0.53 + 0.029*sl 0.54 + 0.025*sl 0.56 + 0.022*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.20 0.12 + 0.041*sl 0.13 + 0.037*sl 0.13 + 0.038*sl c to y t plh 0.96 0.90 + 0.026*sl 0.92 + 0.022*sl 0.94 + 0.019*sl t phl 0.57 0.51 + 0.029*sl 0.53 + 0.024*sl 0.54 + 0.022*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.20 0.12 + 0.041*sl 0.13 + 0.037*sl 0.12 + 0.039*sl d to y t plh 0.86 0.80 + 0.027*sl 0.82 + 0.021*sl 0.84 + 0.019*sl t phl 0.54 0.48 + 0.029*sl 0.49 + 0.025*sl 0.51 + 0.022*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.037*sl 0.12 + 0.038*sl e to y t plh 0.92 0.87 + 0.027*sl 0.88 + 0.021*sl 0.90 + 0.019*sl t phl 0.52 0.47 + 0.029*sl 0.48 + 0.024*sl 0.49 + 0.022*sl t r 0.25 0.18 + 0.033*sl 0.18 + 0.033*sl 0.18 + 0.034*sl t f 0.20 0.12 + 0.037*sl 0.12 + 0.039*sl 0.12 + 0.038*sl f to y t plh 1.11 1.06 + 0.026*sl 1.07 + 0.021*sl 1.09 + 0.019*sl t phl 0.58 0.52 + 0.029*sl 0.53 + 0.024*sl 0.54 + 0.022*sl t r 0.25 0.19 + 0.032*sl 0.18 + 0.034*sl 0.18 + 0.033*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.038*sl 0.11 + 0.039*sl g to y t plh 1.03 0.98 + 0.026*sl 0.99 + 0.021*sl 1.01 + 0.019*sl t phl 0.56 0.50 + 0.029*sl 0.51 + 0.024*sl 0.53 + 0.022*sl t r 0.25 0.18 + 0.034*sl 0.19 + 0.033*sl 0.18 + 0.033*sl t f 0.19 0.11 + 0.039*sl 0.12 + 0.038*sl 0.11 + 0.039*sl h to y t plh 1.15 1.09 + 0.026*sl 1.11 + 0.021*sl 1.13 + 0.019*sl t phl 0.58 0.53 + 0.029*sl 0.54 + 0.024*sl 0.55 + 0.022*sl t r 0.25 0.18 + 0.032*sl 0.18 + 0.033*sl 0.18 + 0.033*sl t f 0.20 0.12 + 0.038*sl 0.12 + 0.038*sl 0.12 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-64 sec asic or2/or2d2 2-input or with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 or2 STD80 or2d2 input load (sl) gate count STD80 or2 or2d2 or2 or2d2 abab 0.4 0.7 0.4 0.7 1.3 1.7 stdm80 or2 or2d2 or2 or2d2 abab 0.8 0.8 0.8 0.8 1.3 1.7 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.17 + 0.026*sl 0.17 + 0.024*sl 0.17 + 0.024*sl t phl 0.41 0.33 + 0.042*sl 0.33 + 0.038*sl 0.35 + 0.037*sl t r 0.19 0.10 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl b to y t plh 0.25 0.20 + 0.027*sl 0.20 + 0.024*sl 0.20 + 0.024*sl t phl 0.40 0.32 + 0.042*sl 0.33 + 0.038*sl 0.34 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.20 + 0.017*sl 0.21 + 0.013*sl 0.22 + 0.012*sl t phl 0.43 0.38 + 0.025*sl 0.39 + 0.021*sl 0.42 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.14 + 0.032*sl 0.15 + 0.031*sl 0.12 + 0.034*sl b to y t plh 0.26 0.23 + 0.018*sl 0.24 + 0.013*sl 0.25 + 0.012*sl t phl 0.43 0.38 + 0.025*sl 0.39 + 0.021*sl 0.41 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.12 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aby 000 011 101 111
sec asic 3-65 STD80/stdm80 or2/or2d2 2-input or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 or2 stdm80 or2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.23 + 0.036*sl 0.24 + 0.033*sl 0.24 + 0.033*sl t phl 0.54 0.43 + 0.055*sl 0.45 + 0.048*sl 0.47 + 0.045*sl t r 0.25 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.33 0.16 + 0.082*sl 0.17 + 0.079*sl 0.16 + 0.081*sl b to y t plh 0.33 0.26 + 0.036*sl 0.27 + 0.034*sl 0.27 + 0.033*sl t phl 0.56 0.45 + 0.055*sl 0.47 + 0.048*sl 0.49 + 0.045*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.33 0.16 + 0.081*sl 0.17 + 0.079*sl 0.16 + 0.081*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.26 + 0.022*sl 0.27 + 0.018*sl 0.28 + 0.017*sl t phl 0.58 0.51 + 0.034*sl 0.53 + 0.029*sl 0.56 + 0.025*sl t r 0.18 0.12 + 0.032*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t f 0.27 0.18 + 0.042*sl 0.19 + 0.039*sl 0.20 + 0.038*sl b to y t plh 0.33 0.29 + 0.023*sl 0.30 + 0.018*sl 0.31 + 0.017*sl t phl 0.61 0.54 + 0.034*sl 0.55 + 0.028*sl 0.58 + 0.025*sl t r 0.19 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.040*sl 0.20 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-66 sec asic or3/or3d3 3-input or with 1x/3x drive logic symbol cell data input load (sl) gate count STD80 or3 or3d3 or3 or3d3 abcabc 0.4 0.6 0.7 0.4 0.6 0.6 1.7 2.3 stdm80 or3 or3d3 or3 or3d3 abcabc 0.8 0.7 0.7 0.8 0.7 0.7 1.7 2.3 y a b c truth table abcy 0000 1xx1 x1x1 xx11
sec asic 3-67 STD80/stdm80 or3/or3d3 3-input or with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 or3 STD80 or3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.17 + 0.027*sl 0.18 + 0.024*sl 0.18 + 0.024*sl t phl 0.50 0.41 + 0.046*sl 0.42 + 0.040*sl 0.45 + 0.037*sl t r 0.19 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.30 0.16 + 0.066*sl 0.17 + 0.065*sl 0.13 + 0.069*sl b to y t plh 0.26 0.20 + 0.027*sl 0.21 + 0.024*sl 0.21 + 0.024*sl t phl 0.52 0.43 + 0.047*sl 0.44 + 0.040*sl 0.47 + 0.037*sl t r 0.20 0.12 + 0.040*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.30 0.17 + 0.065*sl 0.17 + 0.065*sl 0.13 + 0.069*sl c to y t plh 0.27 0.22 + 0.027*sl 0.23 + 0.024*sl 0.23 + 0.024*sl t phl 0.52 0.43 + 0.047*sl 0.44 + 0.040*sl 0.47 + 0.037*sl t r 0.21 0.12 + 0.041*sl 0.11 + 0.048*sl 0.07 + 0.052*sl t f 0.30 0.17 + 0.065*sl 0.17 + 0.065*sl 0.13 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.25 + 0.013*sl 0.26 + 0.010*sl 0.28 + 0.008*sl t phl 0.65 0.61 + 0.021*sl 0.62 + 0.017*sl 0.66 + 0.012*sl t r 0.16 0.13 + 0.013*sl 0.13 + 0.015*sl 0.11 + 0.017*sl t f 0.32 0.28 + 0.022*sl 0.28 + 0.021*sl 0.27 + 0.021*sl b to y t plh 0.30 0.28 + 0.013*sl 0.28 + 0.010*sl 0.30 + 0.008*sl t phl 0.67 0.63 + 0.021*sl 0.64 + 0.017*sl 0.69 + 0.012*sl t r 0.17 0.14 + 0.013*sl 0.14 + 0.014*sl 0.11 + 0.017*sl t f 0.32 0.27 + 0.023*sl 0.28 + 0.021*sl 0.27 + 0.021*sl c to y t plh 0.32 0.29 + 0.011*sl 0.29 + 0.010*sl 0.32 + 0.008*sl t phl 0.68 0.63 + 0.022*sl 0.64 + 0.017*sl 0.69 + 0.012*sl t r 0.17 0.15 + 0.013*sl 0.15 + 0.014*sl 0.12 + 0.017*sl t f 0.32 0.27 + 0.023*sl 0.28 + 0.021*sl 0.27 + 0.021*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-68 sec asic or3/or3d3 3-input or with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 or3 stdm80 or3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.24 + 0.036*sl 0.25 + 0.034*sl 0.25 + 0.033*sl t phl 0.69 0.57 + 0.063*sl 0.60 + 0.053*sl 0.63 + 0.048*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.39 0.22 + 0.085*sl 0.24 + 0.081*sl 0.24 + 0.080*sl b to y t plh 0.35 0.27 + 0.037*sl 0.28 + 0.034*sl 0.28 + 0.033*sl t phl 0.75 0.63 + 0.063*sl 0.66 + 0.053*sl 0.69 + 0.048*sl t r 0.26 0.12 + 0.070*sl 0.13 + 0.069*sl 0.10 + 0.072*sl t f 0.40 0.22 + 0.086*sl 0.24 + 0.080*sl 0.25 + 0.079*sl c to y t plh 0.36 0.29 + 0.037*sl 0.30 + 0.034*sl 0.30 + 0.034*sl t phl 0.79 0.66 + 0.063*sl 0.69 + 0.053*sl 0.73 + 0.048*sl t r 0.27 0.13 + 0.068*sl 0.13 + 0.070*sl 0.11 + 0.072*sl t f 0.40 0.22 + 0.086*sl 0.24 + 0.080*sl 0.25 + 0.079*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.36 0.32 + 0.016*sl 0.33 + 0.014*sl 0.34 + 0.012*sl t phl 0.95 0.89 + 0.029*sl 0.90 + 0.024*sl 0.92 + 0.021*sl t r 0.19 0.14 + 0.022*sl 0.14 + 0.022*sl 0.14 + 0.022*sl t f 0.41 0.35 + 0.032*sl 0.36 + 0.029*sl 0.37 + 0.027*sl b to y t plh 0.38 0.35 + 0.017*sl 0.36 + 0.014*sl 0.37 + 0.012*sl t phl 1.01 0.95 + 0.029*sl 0.97 + 0.024*sl 0.99 + 0.021*sl t r 0.20 0.15 + 0.020*sl 0.15 + 0.022*sl 0.15 + 0.022*sl t f 0.41 0.35 + 0.032*sl 0.36 + 0.028*sl 0.37 + 0.027*sl c to y t plh 0.40 0.36 + 0.017*sl 0.37 + 0.014*sl 0.38 + 0.013*sl t phl 1.05 0.99 + 0.029*sl 1.00 + 0.024*sl 1.02 + 0.021*sl t r 0.20 0.16 + 0.022*sl 0.16 + 0.022*sl 0.16 + 0.022*sl t f 0.41 0.35 + 0.032*sl 0.36 + 0.029*sl 0.37 + 0.027*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-69 STD80/stdm80 or4/or4d2 4-input or with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 or4 or4d2 or4 or4d2 abcdabcd 0.4 0.7 0.7 0.5 0.4 0.7 0.7 0.4 2.7 3.0 stdm80 or4 or4d2 or4 or4d2 abcdabcd 0.8 0.8 0.7 0.8 0.8 0.8 0.8 0.8 2.7 3.0 y a b c d truth table abcdy 00000 1xxx1 x1xx1 xx1x1 xxx11
STD80/stdm80 3-70 sec asic or4/or4d2 4-input or with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 or4 STD80 or4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.19 + 0.025*sl 0.19 + 0.025*sl 0.19 + 0.025*sl t phl 0.41 0.32 + 0.041*sl 0.33 + 0.039*sl 0.34 + 0.039*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.051*sl 0.09 + 0.054*sl t f 0.28 0.14 + 0.071*sl 0.13 + 0.075*sl 0.11 + 0.078*sl b to y t plh 0.27 0.22 + 0.026*sl 0.22 + 0.025*sl 0.22 + 0.025*sl t phl 0.40 0.32 + 0.041*sl 0.32 + 0.039*sl 0.33 + 0.039*sl t r 0.23 0.14 + 0.044*sl 0.13 + 0.051*sl 0.10 + 0.054*sl t f 0.29 0.14 + 0.072*sl 0.14 + 0.075*sl 0.11 + 0.078*sl c to y t plh 0.27 0.21 + 0.027*sl 0.22 + 0.025*sl 0.22 + 0.025*sl t phl 0.41 0.33 + 0.043*sl 0.33 + 0.039*sl 0.34 + 0.039*sl t r 0.21 0.12 + 0.046*sl 0.11 + 0.051*sl 0.08 + 0.054*sl t f 0.29 0.15 + 0.072*sl 0.14 + 0.075*sl 0.12 + 0.078*sl d to y t plh 0.24 0.18 + 0.027*sl 0.19 + 0.025*sl 0.19 + 0.025*sl t phl 0.42 0.33 + 0.043*sl 0.34 + 0.039*sl 0.35 + 0.039*sl t r 0.20 0.11 + 0.047*sl 0.10 + 0.052*sl 0.08 + 0.054*sl t f 0.29 0.15 + 0.073*sl 0.14 + 0.075*sl 0.12 + 0.078*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.24 + 0.014*sl 0.25 + 0.013*sl 0.25 + 0.012*sl t phl 0.45 0.40 + 0.023*sl 0.41 + 0.020*sl 0.42 + 0.019*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.023*sl 0.11 + 0.027*sl t f 0.25 0.18 + 0.034*sl 0.17 + 0.035*sl 0.14 + 0.039*sl b to y t plh 0.30 0.27 + 0.013*sl 0.27 + 0.013*sl 0.28 + 0.012*sl t phl 0.44 0.40 + 0.023*sl 0.40 + 0.020*sl 0.41 + 0.019*sl t r 0.20 0.16 + 0.022*sl 0.16 + 0.023*sl 0.12 + 0.027*sl t f 0.25 0.18 + 0.033*sl 0.17 + 0.036*sl 0.15 + 0.039*sl c to y t plh 0.29 0.25 + 0.017*sl 0.26 + 0.013*sl 0.27 + 0.012*sl t phl 0.45 0.40 + 0.024*sl 0.41 + 0.021*sl 0.42 + 0.019*sl t r 0.18 0.13 + 0.023*sl 0.13 + 0.023*sl 0.10 + 0.027*sl t f 0.25 0.18 + 0.034*sl 0.17 + 0.036*sl 0.15 + 0.038*sl d to y t plh 0.26 0.23 + 0.015*sl 0.23 + 0.013*sl 0.24 + 0.012*sl t phl 0.45 0.40 + 0.024*sl 0.41 + 0.021*sl 0.43 + 0.019*sl t r 0.17 0.13 + 0.020*sl 0.12 + 0.024*sl 0.09 + 0.027*sl t f 0.25 0.18 + 0.035*sl 0.18 + 0.036*sl 0.15 + 0.038*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-71 STD80/stdm80 or4/or4d2 4-input or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 or4 stdm80 or4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.33 0.26 + 0.036*sl 0.26 + 0.035*sl 0.26 + 0.035*sl t phl 0.54 0.43 + 0.057*sl 0.45 + 0.052*sl 0.46 + 0.051*sl t r 0.30 0.16 + 0.071*sl 0.15 + 0.074*sl 0.14 + 0.075*sl t f 0.38 0.19 + 0.096*sl 0.19 + 0.097*sl 0.18 + 0.098*sl b to y t plh 0.37 0.29 + 0.036*sl 0.30 + 0.035*sl 0.30 + 0.035*sl t phl 0.57 0.45 + 0.056*sl 0.47 + 0.052*sl 0.48 + 0.050*sl t r 0.30 0.16 + 0.070*sl 0.15 + 0.074*sl 0.14 + 0.075*sl t f 0.38 0.19 + 0.096*sl 0.19 + 0.097*sl 0.18 + 0.098*sl c to y t plh 0.35 0.28 + 0.037*sl 0.28 + 0.035*sl 0.28 + 0.035*sl t phl 0.58 0.46 + 0.059*sl 0.48 + 0.052*sl 0.50 + 0.050*sl t r 0.28 0.13 + 0.072*sl 0.13 + 0.074*sl 0.12 + 0.075*sl t f 0.39 0.20 + 0.097*sl 0.20 + 0.096*sl 0.19 + 0.097*sl d to y t plh 0.32 0.25 + 0.036*sl 0.25 + 0.035*sl 0.25 + 0.035*sl t phl 0.56 0.44 + 0.059*sl 0.46 + 0.052*sl 0.48 + 0.050*sl t r 0.28 0.13 + 0.071*sl 0.12 + 0.074*sl 0.12 + 0.075*sl t f 0.39 0.20 + 0.096*sl 0.20 + 0.096*sl 0.19 + 0.097*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.31 + 0.020*sl 0.32 + 0.018*sl 0.33 + 0.018*sl t phl 0.62 0.55 + 0.032*sl 0.56 + 0.029*sl 0.57 + 0.027*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.035*sl 0.16 + 0.036*sl t f 0.32 0.22 + 0.047*sl 0.22 + 0.048*sl 0.22 + 0.048*sl b to y t plh 0.38 0.34 + 0.020*sl 0.35 + 0.019*sl 0.36 + 0.018*sl t phl 0.64 0.57 + 0.032*sl 0.58 + 0.029*sl 0.60 + 0.027*sl t r 0.24 0.18 + 0.033*sl 0.17 + 0.035*sl 0.17 + 0.036*sl t f 0.32 0.22 + 0.048*sl 0.22 + 0.047*sl 0.22 + 0.048*sl c to y t plh 0.36 0.32 + 0.022*sl 0.33 + 0.019*sl 0.34 + 0.018*sl t phl 0.64 0.57 + 0.034*sl 0.59 + 0.030*sl 0.61 + 0.027*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.035*sl 0.14 + 0.036*sl t f 0.33 0.23 + 0.049*sl 0.24 + 0.048*sl 0.24 + 0.047*sl d to y t plh 0.33 0.29 + 0.022*sl 0.30 + 0.019*sl 0.31 + 0.018*sl t phl 0.62 0.55 + 0.034*sl 0.57 + 0.030*sl 0.59 + 0.027*sl t r 0.21 0.14 + 0.035*sl 0.14 + 0.035*sl 0.13 + 0.036*sl t f 0.33 0.23 + 0.048*sl 0.23 + 0.048*sl 0.24 + 0.047*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-72 sec asic or5/or5d2 5-input or with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 or5 or5d2 or5 or5d2 abcdeabcde 0.4 0.6 0.7 0.7 0.5 0.4 0.6 0.7 0.7 0.4 3.0 3.3 stdm80 or5 or5d2 or5 or5d2 abcdeabcde 0.8 0.8 0.8 0.7 0.8 0.8 0.8 0.8 0.8 0.8 3.0 3.3 y b c d e a truth table abcdey 000000 1xxxx1 x1xxx1 xx1xx1 xxx1x1 xxxx11
sec asic 3-73 STD80/stdm80 or5/or5d2 5-input or with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 or5 STD80 or5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.20 + 0.026*sl 0.21 + 0.025*sl 0.20 + 0.025*sl t phl 0.51 0.41 + 0.045*sl 0.42 + 0.042*sl 0.43 + 0.041*sl t r 0.23 0.14 + 0.044*sl 0.12 + 0.051*sl 0.09 + 0.054*sl t f 0.34 0.19 + 0.075*sl 0.18 + 0.077*sl 0.14 + 0.082*sl b to y t plh 0.28 0.23 + 0.027*sl 0.24 + 0.025*sl 0.23 + 0.025*sl t phl 0.52 0.43 + 0.045*sl 0.44 + 0.042*sl 0.45 + 0.041*sl t r 0.23 0.14 + 0.045*sl 0.13 + 0.050*sl 0.10 + 0.054*sl t f 0.34 0.20 + 0.070*sl 0.18 + 0.078*sl 0.14 + 0.082*sl c to y t plh 0.30 0.25 + 0.027*sl 0.25 + 0.025*sl 0.25 + 0.025*sl t phl 0.53 0.43 + 0.045*sl 0.44 + 0.042*sl 0.45 + 0.041*sl t r 0.24 0.15 + 0.044*sl 0.14 + 0.050*sl 0.10 + 0.054*sl t f 0.34 0.19 + 0.074*sl 0.18 + 0.077*sl 0.14 + 0.082*sl d to y t plh 0.26 0.21 + 0.027*sl 0.21 + 0.025*sl 0.21 + 0.025*sl t phl 0.42 0.33 + 0.045*sl 0.33 + 0.041*sl 0.34 + 0.041*sl t r 0.21 0.11 + 0.048*sl 0.11 + 0.051*sl 0.08 + 0.054*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.12 + 0.082*sl e to y t plh 0.23 0.18 + 0.026*sl 0.18 + 0.025*sl 0.18 + 0.025*sl t phl 0.42 0.33 + 0.045*sl 0.34 + 0.041*sl 0.35 + 0.041*sl t r 0.20 0.11 + 0.048*sl 0.10 + 0.051*sl 0.08 + 0.054*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.080*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.25 + 0.014*sl 0.26 + 0.013*sl 0.26 + 0.012*sl t phl 0.57 0.51 + 0.026*sl 0.52 + 0.022*sl 0.55 + 0.019*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.024*sl 0.12 + 0.027*sl t f 0.32 0.26 + 0.031*sl 0.25 + 0.033*sl 0.20 + 0.038*sl b to y t plh 0.31 0.28 + 0.014*sl 0.28 + 0.013*sl 0.29 + 0.012*sl t phl 0.59 0.54 + 0.025*sl 0.54 + 0.022*sl 0.57 + 0.019*sl t r 0.20 0.17 + 0.018*sl 0.16 + 0.023*sl 0.12 + 0.027*sl t f 0.32 0.25 + 0.032*sl 0.25 + 0.033*sl 0.20 + 0.038*sl c to y t plh 0.32 0.30 + 0.013*sl 0.30 + 0.013*sl 0.31 + 0.012*sl t phl 0.59 0.54 + 0.026*sl 0.55 + 0.022*sl 0.57 + 0.019*sl t r 0.21 0.17 + 0.020*sl 0.17 + 0.023*sl 0.13 + 0.027*sl t f 0.32 0.26 + 0.030*sl 0.25 + 0.034*sl 0.20 + 0.038*sl d to y t plh 0.29 0.25 + 0.017*sl 0.26 + 0.013*sl 0.27 + 0.012*sl t phl 0.45 0.40 + 0.023*sl 0.41 + 0.021*sl 0.42 + 0.019*sl t r 0.18 0.14 + 0.022*sl 0.13 + 0.023*sl 0.10 + 0.027*sl t f 0.25 0.18 + 0.034*sl 0.18 + 0.036*sl 0.15 + 0.039*sl e to y t plh 0.26 0.23 + 0.015*sl 0.23 + 0.013*sl 0.24 + 0.012*sl t phl 0.45 0.41 + 0.023*sl 0.41 + 0.021*sl 0.43 + 0.019*sl t r 0.17 0.13 + 0.021*sl 0.12 + 0.024*sl 0.09 + 0.027*sl t f 0.25 0.18 + 0.035*sl 0.18 + 0.036*sl 0.15 + 0.039*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
STD80/stdm80 3-74 sec asic or5/or5d2 5-input or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 or5 stdm80 or5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.28 + 0.036*sl 0.28 + 0.035*sl 0.28 + 0.035*sl t phl 0.70 0.57 + 0.063*sl 0.59 + 0.057*sl 0.61 + 0.054*sl t r 0.30 0.17 + 0.068*sl 0.15 + 0.074*sl 0.14 + 0.075*sl t f 0.45 0.25 + 0.100*sl 0.25 + 0.101*sl 0.24 + 0.102*sl b to y t plh 0.38 0.31 + 0.036*sl 0.31 + 0.035*sl 0.32 + 0.035*sl t phl 0.76 0.64 + 0.062*sl 0.65 + 0.057*sl 0.68 + 0.054*sl t r 0.30 0.16 + 0.071*sl 0.15 + 0.073*sl 0.14 + 0.075*sl t f 0.45 0.25 + 0.099*sl 0.25 + 0.101*sl 0.24 + 0.102*sl c to y t plh 0.40 0.32 + 0.038*sl 0.33 + 0.036*sl 0.33 + 0.035*sl t phl 0.80 0.67 + 0.062*sl 0.69 + 0.057*sl 0.71 + 0.054*sl t r 0.31 0.17 + 0.071*sl 0.16 + 0.073*sl 0.15 + 0.075*sl t f 0.45 0.25 + 0.100*sl 0.25 + 0.101*sl 0.24 + 0.102*sl d to y t plh 0.35 0.27 + 0.036*sl 0.28 + 0.035*sl 0.28 + 0.035*sl t phl 0.58 0.46 + 0.061*sl 0.48 + 0.055*sl 0.49 + 0.053*sl t r 0.28 0.13 + 0.072*sl 0.13 + 0.074*sl 0.12 + 0.075*sl t f 0.41 0.20 + 0.103*sl 0.20 + 0.102*sl 0.20 + 0.103*sl e to y t plh 0.32 0.24 + 0.036*sl 0.25 + 0.035*sl 0.25 + 0.035*sl t phl 0.57 0.44 + 0.061*sl 0.46 + 0.055*sl 0.48 + 0.053*sl t r 0.28 0.14 + 0.068*sl 0.12 + 0.074*sl 0.11 + 0.075*sl t f 0.41 0.21 + 0.101*sl 0.20 + 0.102*sl 0.20 + 0.103*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.37 0.33 + 0.021*sl 0.34 + 0.018*sl 0.34 + 0.018*sl t phl 0.81 0.74 + 0.035*sl 0.76 + 0.031*sl 0.78 + 0.028*sl t r 0.24 0.18 + 0.033*sl 0.17 + 0.035*sl 0.16 + 0.036*sl t f 0.41 0.32 + 0.045*sl 0.32 + 0.046*sl 0.31 + 0.047*sl b to y t plh 0.40 0.36 + 0.021*sl 0.36 + 0.019*sl 0.37 + 0.018*sl t phl 0.88 0.81 + 0.035*sl 0.82 + 0.031*sl 0.84 + 0.028*sl t r 0.25 0.18 + 0.034*sl 0.18 + 0.034*sl 0.17 + 0.036*sl t f 0.41 0.32 + 0.044*sl 0.31 + 0.046*sl 0.31 + 0.047*sl c to y t plh 0.42 0.37 + 0.021*sl 0.38 + 0.019*sl 0.39 + 0.018*sl t phl 0.92 0.85 + 0.035*sl 0.86 + 0.031*sl 0.88 + 0.028*sl t r 0.26 0.19 + 0.033*sl 0.19 + 0.035*sl 0.18 + 0.035*sl t f 0.41 0.32 + 0.044*sl 0.31 + 0.046*sl 0.31 + 0.047*sl d to y t plh 0.37 0.32 + 0.021*sl 0.33 + 0.019*sl 0.34 + 0.018*sl t phl 0.65 0.58 + 0.034*sl 0.59 + 0.030*sl 0.61 + 0.027*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.035*sl 0.14 + 0.036*sl t f 0.33 0.23 + 0.050*sl 0.24 + 0.047*sl 0.24 + 0.048*sl e to y t plh 0.34 0.29 + 0.022*sl 0.30 + 0.019*sl 0.31 + 0.018*sl t phl 0.62 0.56 + 0.034*sl 0.57 + 0.030*sl 0.59 + 0.027*sl t r 0.21 0.14 + 0.035*sl 0.14 + 0.035*sl 0.13 + 0.036*sl t f 0.33 0.24 + 0.049*sl 0.24 + 0.047*sl 0.24 + 0.048*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-75 STD80/stdm80 xn2/xn2d2 2-input exclusive-nor with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 xn2 STD80 xn2d2 input load (sl) gate count STD80 xn2 xn2d2 xn2 xn2d2 abab 0.8 1.5 0.8 1.5 2.7 3.0 stdm80 xn2 xn2d2 xn2 xn2d2 abab 0.8 1.5 0.8 1.5 2.7 3.0 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.47 0.41 + 0.029*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.50 0.41 + 0.044*sl 0.42 + 0.039*sl 0.44 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.29 0.16 + 0.062*sl 0.16 + 0.064*sl 0.11 + 0.069*sl b to y t plh 0.34 0.28 + 0.029*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.40 0.30 + 0.045*sl 0.32 + 0.039*sl 0.34 + 0.037*sl t r 0.21 0.11 + 0.048*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.26 0.12 + 0.068*sl 0.13 + 0.066*sl 0.10 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.48 0.44 + 0.020*sl 0.45 + 0.015*sl 0.48 + 0.012*sl t phl 0.51 0.46 + 0.027*sl 0.47 + 0.021*sl 0.50 + 0.018*sl t r 0.18 0.14 + 0.022*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.21 0.14 + 0.034*sl 0.15 + 0.031*sl 0.13 + 0.034*sl b to y t plh 0.34 0.30 + 0.022*sl 0.31 + 0.015*sl 0.34 + 0.012*sl t phl 0.39 0.34 + 0.026*sl 0.35 + 0.021*sl 0.38 + 0.018*sl t r 0.18 0.14 + 0.018*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.21 0.14 + 0.034*sl 0.14 + 0.032*sl 0.12 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aby 001 010 100 111
STD80/stdm80 3-76 sec asic xn2/xn2d2 2-input exclusive-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 xn2 stdm80 xn2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.64 0.56 + 0.040*sl 0.57 + 0.035*sl 0.59 + 0.034*sl t phl 0.71 0.60 + 0.057*sl 0.62 + 0.049*sl 0.64 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.081*sl 0.18 + 0.079*sl 0.18 + 0.080*sl b to y t plh 0.46 0.38 + 0.041*sl 0.40 + 0.035*sl 0.41 + 0.034*sl t phl 0.54 0.42 + 0.059*sl 0.45 + 0.050*sl 0.47 + 0.046*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.084*sl 0.19 + 0.080*sl 0.19 + 0.080*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.65 0.60 + 0.026*sl 0.61 + 0.021*sl 0.63 + 0.019*sl t phl 0.72 0.65 + 0.035*sl 0.66 + 0.029*sl 0.69 + 0.025*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.28 0.19 + 0.042*sl 0.20 + 0.040*sl 0.21 + 0.038*sl b to y t plh 0.46 0.41 + 0.026*sl 0.43 + 0.021*sl 0.44 + 0.019*sl t phl 0.53 0.46 + 0.037*sl 0.48 + 0.030*sl 0.51 + 0.026*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.28 0.19 + 0.045*sl 0.20 + 0.041*sl 0.22 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-77 STD80/stdm80 xn3/xn3d3 3-input exclusive-nor with 1x/3x drive logic symbol cell data input load (sl) gate count STD80 xn3 xn3d3 xn3 xn3d3 abcabc 1.0 0.8 1.5 1.0 0.8 1.5 4.3 5.0 stdm80 xn3 xn3d3 xn3 xn3d3 abcabc 1.5 0.8 1.5 1.5 0.8 1.5 4.3 5.0 y a b c truth table abcy 0001 0010 0100 0111 1000 1011 1101 1110
STD80/stdm80 3-78 sec asic xn3/xn3d3 3-input exclusive-nor with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 xn3 STD80 xn3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.36 0.29 + 0.035*sl 0.31 + 0.028*sl 0.35 + 0.024*sl t phl 0.42 0.32 + 0.050*sl 0.33 + 0.042*sl 0.38 + 0.037*sl t r 0.24 0.14 + 0.047*sl 0.14 + 0.050*sl 0.12 + 0.052*sl t f 0.29 0.15 + 0.070*sl 0.16 + 0.068*sl 0.15 + 0.069*sl b to y t plh 0.66 0.60 + 0.030*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t phl 0.77 0.68 + 0.044*sl 0.69 + 0.039*sl 0.71 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.066*sl 0.13 + 0.065*sl 0.09 + 0.069*sl c to y t plh 0.54 0.48 + 0.030*sl 0.49 + 0.025*sl 0.50 + 0.024*sl t phl 0.64 0.55 + 0.044*sl 0.56 + 0.039*sl 0.57 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.065*sl 0.09 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.36 + 0.018*sl 0.37 + 0.014*sl 0.43 + 0.008*sl t phl 0.49 0.44 + 0.024*sl 0.45 + 0.019*sl 0.51 + 0.013*sl t r 0.24 0.21 + 0.019*sl 0.21 + 0.017*sl 0.22 + 0.017*sl t f 0.30 0.25 + 0.027*sl 0.26 + 0.023*sl 0.27 + 0.022*sl b to y t plh 0.70 0.66 + 0.019*sl 0.67 + 0.014*sl 0.73 + 0.008*sl t phl 0.83 0.79 + 0.018*sl 0.79 + 0.016*sl 0.83 + 0.012*sl t r 0.29 0.25 + 0.018*sl 0.25 + 0.016*sl 0.25 + 0.016*sl t f 0.23 0.19 + 0.023*sl 0.19 + 0.020*sl 0.18 + 0.022*sl c to y t plh 0.59 0.56 + 0.015*sl 0.57 + 0.012*sl 0.60 + 0.008*sl t phl 0.69 0.65 + 0.019*sl 0.66 + 0.016*sl 0.70 + 0.012*sl t r 0.21 0.17 + 0.017*sl 0.18 + 0.015*sl 0.16 + 0.017*sl t f 0.23 0.19 + 0.023*sl 0.19 + 0.021*sl 0.18 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-79 STD80/stdm80 xn3/xn3d3 3-input exclusive-nor with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 xn3 stdm80 xn3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.50 0.40 + 0.047*sl 0.43 + 0.040*sl 0.46 + 0.036*sl t phl 0.56 0.42 + 0.066*sl 0.45 + 0.056*sl 0.50 + 0.050*sl t r 0.33 0.18 + 0.075*sl 0.19 + 0.070*sl 0.20 + 0.070*sl t f 0.38 0.19 + 0.095*sl 0.22 + 0.085*sl 0.25 + 0.082*sl b to y t plh 0.95 0.87 + 0.041*sl 0.89 + 0.036*sl 0.90 + 0.034*sl t phl 1.07 0.93 + 0.071*sl 0.97 + 0.057*sl 1.02 + 0.051*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.50 0.33 + 0.086*sl 0.35 + 0.079*sl 0.35 + 0.078*sl c to y t plh 0.78 0.70 + 0.041*sl 0.71 + 0.036*sl 0.73 + 0.034*sl t phl 0.89 0.75 + 0.071*sl 0.79 + 0.058*sl 0.84 + 0.051*sl t r 0.30 0.16 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.50 0.33 + 0.085*sl 0.34 + 0.079*sl 0.35 + 0.078*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.52 + 0.024*sl 0.53 + 0.020*sl 0.55 + 0.017*sl t phl 0.70 0.63 + 0.033*sl 0.65 + 0.027*sl 0.68 + 0.023*sl t r 0.31 0.25 + 0.027*sl 0.26 + 0.025*sl 0.27 + 0.024*sl t f 0.41 0.34 + 0.036*sl 0.36 + 0.031*sl 0.37 + 0.029*sl b to y t plh 1.02 0.98 + 0.020*sl 0.99 + 0.016*sl 1.01 + 0.014*sl t phl 1.19 1.13 + 0.033*sl 1.15 + 0.027*sl 1.17 + 0.023*sl t r 0.25 0.21 + 0.023*sl 0.21 + 0.023*sl 0.21 + 0.022*sl t f 0.49 0.42 + 0.035*sl 0.43 + 0.030*sl 0.45 + 0.027*sl c to y t plh 0.85 0.81 + 0.020*sl 0.82 + 0.017*sl 0.84 + 0.014*sl t phl 1.01 0.95 + 0.033*sl 0.97 + 0.027*sl 0.99 + 0.023*sl t r 0.25 0.20 + 0.026*sl 0.21 + 0.022*sl 0.21 + 0.023*sl t f 0.49 0.42 + 0.035*sl 0.43 + 0.029*sl 0.45 + 0.027*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-80 sec asic xo2/xo2d2 2-input exclusive-or with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 xo2 STD80 xo2d2 input load (sl) gate count STD80 xo2 xo2d2 xo2 xo2d2 abab 0.7 1.0 0.7 1.0 2.7 3.0 stdm80 xo2 xo2d2 xo2 xo2d2 abab 0.8 1.5 0.8 1.5 2.7 3.0 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.47 0.41 + 0.030*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.51 0.42 + 0.044*sl 0.43 + 0.038*sl 0.45 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.066*sl 0.09 + 0.069*sl b to y t plh 0.34 0.28 + 0.029*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.40 0.31 + 0.044*sl 0.32 + 0.039*sl 0.34 + 0.037*sl t r 0.21 0.12 + 0.047*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.47 0.44 + 0.019*sl 0.44 + 0.015*sl 0.47 + 0.012*sl t phl 0.51 0.46 + 0.026*sl 0.47 + 0.021*sl 0.50 + 0.018*sl t r 0.18 0.14 + 0.021*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.21 0.14 + 0.034*sl 0.15 + 0.031*sl 0.13 + 0.033*sl b to y t plh 0.34 0.30 + 0.020*sl 0.31 + 0.015*sl 0.34 + 0.012*sl t phl 0.39 0.34 + 0.026*sl 0.35 + 0.021*sl 0.38 + 0.018*sl t r 0.18 0.13 + 0.022*sl 0.13 + 0.024*sl 0.11 + 0.026*sl t f 0.20 0.14 + 0.034*sl 0.14 + 0.032*sl 0.12 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aby 000 011 101 110
sec asic 3-81 STD80/stdm80 xo2/xo2d2 2-input exclusive-or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 xo2 stdm80 xo2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.64 0.55 + 0.041*sl 0.57 + 0.035*sl 0.58 + 0.033*sl t phl 0.71 0.60 + 0.057*sl 0.62 + 0.049*sl 0.65 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.068*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.081*sl 0.19 + 0.079*sl 0.17 + 0.080*sl b to y t plh 0.46 0.38 + 0.042*sl 0.39 + 0.036*sl 0.41 + 0.034*sl t phl 0.54 0.43 + 0.057*sl 0.45 + 0.048*sl 0.47 + 0.045*sl t r 0.29 0.16 + 0.069*sl 0.16 + 0.068*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.081*sl 0.18 + 0.079*sl 0.17 + 0.080*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.65 0.59 + 0.026*sl 0.61 + 0.021*sl 0.62 + 0.019*sl t phl 0.72 0.65 + 0.036*sl 0.67 + 0.029*sl 0.70 + 0.025*sl t r 0.23 0.16 + 0.036*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.28 0.19 + 0.043*sl 0.20 + 0.040*sl 0.21 + 0.038*sl b to y t plh 0.46 0.41 + 0.027*sl 0.42 + 0.022*sl 0.44 + 0.019*sl t phl 0.54 0.47 + 0.036*sl 0.49 + 0.029*sl 0.51 + 0.025*sl t r 0.23 0.16 + 0.036*sl 0.16 + 0.035*sl 0.17 + 0.034*sl t f 0.27 0.19 + 0.044*sl 0.20 + 0.040*sl 0.21 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-82 sec asic xo3/xo3d3 3-input exclusive-or with 1x/3x drive logic symbol cell data input load (sl) gate count STD80 xo3 xo3d3 xo3 xo3d3 abcabc 1.5 0.8 1.5 1.5 0.7 1.5 4.3 5.0 stdm80 xo3 xo3d3 xo3 xo3d3 abcabc 1.5 0.8 1.5 1.5 0.8 1.5 4.3 5.0 y a b c truth table abcy 0000 0011 0101 0110 1001 1010 1100 1111
sec asic 3-83 STD80/stdm80 xo3/xo3d3 3-input exclusive-or with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 xo3 STD80 xo3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.34 0.28 + 0.029*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.44 0.34 + 0.052*sl 0.36 + 0.043*sl 0.41 + 0.037*sl t r 0.21 0.12 + 0.046*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.31 0.16 + 0.071*sl 0.17 + 0.067*sl 0.16 + 0.069*sl b to y t plh 0.66 0.60 + 0.031*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t phl 0.77 0.68 + 0.044*sl 0.69 + 0.039*sl 0.71 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.065*sl 0.09 + 0.069*sl c to y t plh 0.54 0.48 + 0.031*sl 0.49 + 0.025*sl 0.51 + 0.024*sl t phl 0.63 0.55 + 0.044*sl 0.56 + 0.039*sl 0.57 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.066*sl 0.09 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.37 0.34 + 0.015*sl 0.35 + 0.011*sl 0.38 + 0.008*sl t phl 0.50 0.45 + 0.024*sl 0.46 + 0.019*sl 0.53 + 0.013*sl t r 0.19 0.16 + 0.016*sl 0.16 + 0.016*sl 0.15 + 0.017*sl t f 0.32 0.27 + 0.026*sl 0.27 + 0.023*sl 0.29 + 0.021*sl b to y t plh 0.71 0.68 + 0.015*sl 0.69 + 0.012*sl 0.72 + 0.008*sl t phl 0.83 0.79 + 0.019*sl 0.80 + 0.016*sl 0.83 + 0.012*sl t r 0.20 0.17 + 0.015*sl 0.17 + 0.016*sl 0.16 + 0.017*sl t f 0.23 0.19 + 0.022*sl 0.19 + 0.021*sl 0.18 + 0.022*sl c to y t plh 0.59 0.56 + 0.015*sl 0.57 + 0.012*sl 0.61 + 0.008*sl t phl 0.69 0.65 + 0.019*sl 0.66 + 0.016*sl 0.70 + 0.012*sl t r 0.21 0.17 + 0.017*sl 0.18 + 0.015*sl 0.16 + 0.017*sl t f 0.23 0.19 + 0.023*sl 0.19 + 0.021*sl 0.18 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-84 sec asic xo3/xo3d3 3-input exclusive-or with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 xo3 stdm80 xo3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.46 0.38 + 0.041*sl 0.40 + 0.035*sl 0.41 + 0.033*sl t phl 0.61 0.47 + 0.069*sl 0.51 + 0.057*sl 0.55 + 0.051*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.42 0.23 + 0.093*sl 0.26 + 0.084*sl 0.28 + 0.081*sl b to y t plh 0.96 0.87 + 0.042*sl 0.89 + 0.036*sl 0.91 + 0.034*sl t phl 1.07 0.93 + 0.071*sl 0.97 + 0.058*sl 1.02 + 0.051*sl t r 0.30 0.16 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.50 0.32 + 0.087*sl 0.35 + 0.079*sl 0.36 + 0.078*sl c to y t plh 0.78 0.70 + 0.042*sl 0.72 + 0.036*sl 0.73 + 0.034*sl t phl 0.89 0.75 + 0.071*sl 0.79 + 0.058*sl 0.84 + 0.051*sl t r 0.30 0.17 + 0.066*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.49 0.32 + 0.086*sl 0.34 + 0.079*sl 0.35 + 0.078*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.51 0.47 + 0.020*sl 0.48 + 0.016*sl 0.49 + 0.014*sl t phl 0.73 0.66 + 0.033*sl 0.68 + 0.027*sl 0.71 + 0.023*sl t r 0.24 0.20 + 0.024*sl 0.20 + 0.024*sl 0.20 + 0.022*sl t f 0.44 0.37 + 0.036*sl 0.39 + 0.030*sl 0.41 + 0.028*sl b to y t plh 1.03 0.99 + 0.020*sl 1.00 + 0.017*sl 1.02 + 0.014*sl t phl 1.20 1.13 + 0.033*sl 1.15 + 0.027*sl 1.18 + 0.023*sl t r 0.25 0.21 + 0.024*sl 0.21 + 0.023*sl 0.21 + 0.023*sl t f 0.49 0.42 + 0.035*sl 0.43 + 0.030*sl 0.45 + 0.027*sl c to y t plh 0.86 0.82 + 0.020*sl 0.83 + 0.017*sl 0.84 + 0.014*sl t phl 1.02 0.95 + 0.033*sl 0.97 + 0.027*sl 1.00 + 0.023*sl t r 0.26 0.21 + 0.024*sl 0.21 + 0.023*sl 0.21 + 0.023*sl t f 0.49 0.42 + 0.036*sl 0.44 + 0.030*sl 0.45 + 0.027*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-85 STD80/stdm80 ao21/ao21d2 2-and into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao21 ao21d2 ao21 ao21d2 abcabc 0.5 0.5 0.8 0.9 0.9 1.6 1.3 2.7 stdm80 ao21 ao21d2 ao21 ao21d2 abcabc 1.0 1.0 1.0 2.0 2.1 1.9 1.3 2.7 a b y c truth table abcy xx10 0x01 x001 11x0
STD80/stdm80 3-86 sec asic ao21/ao21d2 2-and into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao21 STD80 ao21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.14 + 0.046*sl 0.15 + 0.041*sl 0.14 + 0.041*sl t phl 0.25 0.14 + 0.057*sl 0.14 + 0.054*sl 0.14 + 0.055*sl t r 0.44 0.29 + 0.075*sl 0.26 + 0.087*sl 0.19 + 0.095*sl t f 0.38 0.19 + 0.097*sl 0.17 + 0.106*sl 0.13 + 0.111*sl b to y t plh 0.21 0.11 + 0.050*sl 0.13 + 0.041*sl 0.13 + 0.041*sl t phl 0.27 0.16 + 0.057*sl 0.16 + 0.054*sl 0.16 + 0.055*sl t r 0.41 0.26 + 0.077*sl 0.24 + 0.087*sl 0.17 + 0.095*sl t f 0.39 0.20 + 0.095*sl 0.18 + 0.105*sl 0.12 + 0.111*sl c to y t plh 0.25 0.16 + 0.044*sl 0.17 + 0.041*sl 0.16 + 0.041*sl t phl 0.29 0.21 + 0.037*sl 0.21 + 0.037*sl 0.21 + 0.037*sl t r 0.41 0.25 + 0.081*sl 0.23 + 0.090*sl 0.18 + 0.095*sl t f 0.39 0.26 + 0.060*sl 0.26 + 0.064*sl 0.21 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.14 + 0.025*sl 0.15 + 0.021*sl 0.15 + 0.021*sl t phl 0.19 0.13 + 0.029*sl 0.14 + 0.027*sl 0.14 + 0.027*sl t r 0.38 0.30 + 0.037*sl 0.29 + 0.042*sl 0.23 + 0.048*sl t f 0.28 0.19 + 0.046*sl 0.18 + 0.050*sl 0.14 + 0.054*sl b to y t plh 0.17 0.11 + 0.029*sl 0.12 + 0.022*sl 0.13 + 0.021*sl t phl 0.21 0.15 + 0.031*sl 0.16 + 0.027*sl 0.16 + 0.027*sl t r 0.34 0.27 + 0.037*sl 0.26 + 0.042*sl 0.20 + 0.048*sl t f 0.29 0.20 + 0.048*sl 0.20 + 0.049*sl 0.14 + 0.054*sl c to y t plh 0.21 0.17 + 0.023*sl 0.17 + 0.022*sl 0.17 + 0.021*sl t phl 0.25 0.21 + 0.020*sl 0.21 + 0.018*sl 0.21 + 0.018*sl t r 0.34 0.26 + 0.040*sl 0.25 + 0.044*sl 0.21 + 0.048*sl t f 0.32 0.27 + 0.028*sl 0.26 + 0.030*sl 0.23 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-87 STD80/stdm80 ao21/ao21d2 2-and into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao21 stdm80 ao21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.18 + 0.062*sl 0.18 + 0.063*sl 0.18 + 0.063*sl t phl 0.33 0.18 + 0.073*sl 0.18 + 0.072*sl 0.19 + 0.072*sl t r 0.56 0.30 + 0.129*sl 0.28 + 0.135*sl 0.26 + 0.139*sl t f 0.47 0.19 + 0.137*sl 0.19 + 0.140*sl 0.17 + 0.142*sl b to y t plh 0.28 0.16 + 0.063*sl 0.16 + 0.063*sl 0.16 + 0.063*sl t phl 0.34 0.19 + 0.072*sl 0.19 + 0.072*sl 0.20 + 0.072*sl t r 0.53 0.27 + 0.129*sl 0.26 + 0.135*sl 0.23 + 0.139*sl t f 0.47 0.20 + 0.135*sl 0.19 + 0.140*sl 0.17 + 0.142*sl c to y t plh 0.37 0.24 + 0.064*sl 0.25 + 0.063*sl 0.25 + 0.063*sl t phl 0.34 0.25 + 0.047*sl 0.25 + 0.045*sl 0.26 + 0.045*sl t r 0.56 0.29 + 0.131*sl 0.28 + 0.136*sl 0.26 + 0.139*sl t f 0.42 0.26 + 0.078*sl 0.26 + 0.081*sl 0.24 + 0.083*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.19 + 0.031*sl 0.19 + 0.032*sl 0.19 + 0.031*sl t phl 0.25 0.18 + 0.037*sl 0.18 + 0.035*sl 0.19 + 0.035*sl t r 0.44 0.32 + 0.062*sl 0.31 + 0.065*sl 0.29 + 0.068*sl t f 0.32 0.19 + 0.066*sl 0.19 + 0.067*sl 0.18 + 0.068*sl b to y t plh 0.22 0.15 + 0.034*sl 0.16 + 0.031*sl 0.16 + 0.031*sl t phl 0.26 0.18 + 0.036*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t r 0.40 0.28 + 0.061*sl 0.27 + 0.066*sl 0.25 + 0.068*sl t f 0.33 0.20 + 0.064*sl 0.20 + 0.066*sl 0.19 + 0.068*sl c to y t plh 0.32 0.25 + 0.033*sl 0.26 + 0.032*sl 0.26 + 0.032*sl t phl 0.29 0.24 + 0.023*sl 0.24 + 0.022*sl 0.25 + 0.022*sl t r 0.44 0.31 + 0.064*sl 0.30 + 0.067*sl 0.29 + 0.068*sl t f 0.34 0.26 + 0.037*sl 0.26 + 0.039*sl 0.26 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-88 sec asic ao211/ao211d2 2-and into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao211 ao211d2 ao211 ao211d2 abcdabcd 0.5 0.5 0.8 0.9 0.9 0.9 1.3 1.6 1.7 3.3 stdm80 ao211 ao211d2 ao211 ao211d2 abcdabcd 1.0 1.0 1.0 1.1 2.0 2.1 2.0 2.0 1.7 3.3 a b y c d truth table abcdy 11xx0 xx1x0 xxx10 x0001 0x001
sec asic 3-89 STD80/stdm80 ao211/ao211d2 2-and into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao211 STD80 ao211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.18 + 0.056*sl 0.17 + 0.058*sl 0.16 + 0.060*sl t phl 0.26 0.15 + 0.057*sl 0.15 + 0.054*sl 0.15 + 0.055*sl t r 0.64 0.40 + 0.123*sl 0.38 + 0.132*sl 0.31 + 0.138*sl t f 0.40 0.21 + 0.098*sl 0.19 + 0.107*sl 0.15 + 0.111*sl b to y t plh 0.27 0.15 + 0.060*sl 0.15 + 0.058*sl 0.14 + 0.060*sl t phl 0.28 0.17 + 0.056*sl 0.18 + 0.054*sl 0.17 + 0.055*sl t r 0.61 0.36 + 0.124*sl 0.34 + 0.132*sl 0.28 + 0.138*sl t f 0.41 0.22 + 0.097*sl 0.20 + 0.106*sl 0.15 + 0.111*sl c to y t plh 0.35 0.23 + 0.060*sl 0.24 + 0.059*sl 0.23 + 0.060*sl t phl 0.30 0.22 + 0.038*sl 0.22 + 0.037*sl 0.22 + 0.037*sl t r 0.63 0.38 + 0.128*sl 0.37 + 0.134*sl 0.33 + 0.138*sl t f 0.39 0.27 + 0.060*sl 0.26 + 0.064*sl 0.22 + 0.069*sl d to y t plh 0.36 0.24 + 0.060*sl 0.24 + 0.059*sl 0.24 + 0.060*sl t phl 0.32 0.24 + 0.039*sl 0.25 + 0.038*sl 0.25 + 0.037*sl t r 0.62 0.37 + 0.128*sl 0.35 + 0.135*sl 0.32 + 0.138*sl t f 0.45 0.32 + 0.063*sl 0.32 + 0.064*sl 0.28 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.17 + 0.030*sl 0.17 + 0.029*sl 0.16 + 0.031*sl t phl 0.19 0.13 + 0.029*sl 0.14 + 0.027*sl 0.14 + 0.027*sl t r 0.52 0.40 + 0.060*sl 0.39 + 0.065*sl 0.33 + 0.071*sl t f 0.28 0.19 + 0.046*sl 0.18 + 0.050*sl 0.14 + 0.054*sl b to y t plh 0.20 0.13 + 0.033*sl 0.14 + 0.030*sl 0.13 + 0.031*sl t phl 0.21 0.14 + 0.032*sl 0.16 + 0.027*sl 0.16 + 0.027*sl t r 0.48 0.35 + 0.061*sl 0.34 + 0.065*sl 0.29 + 0.071*sl t f 0.29 0.20 + 0.046*sl 0.19 + 0.049*sl 0.14 + 0.054*sl c to y t plh 0.29 0.23 + 0.033*sl 0.23 + 0.031*sl 0.23 + 0.031*sl t phl 0.25 0.21 + 0.020*sl 0.21 + 0.018*sl 0.21 + 0.018*sl t r 0.51 0.38 + 0.064*sl 0.37 + 0.067*sl 0.34 + 0.071*sl t f 0.32 0.26 + 0.029*sl 0.26 + 0.030*sl 0.23 + 0.034*sl d to y t plh 0.31 0.25 + 0.033*sl 0.25 + 0.031*sl 0.25 + 0.031*sl t phl 0.28 0.24 + 0.020*sl 0.24 + 0.019*sl 0.24 + 0.018*sl t r 0.50 0.37 + 0.065*sl 0.36 + 0.068*sl 0.33 + 0.071*sl t f 0.39 0.33 + 0.032*sl 0.33 + 0.031*sl 0.30 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-90 sec asic ao211/ao211d2 2-and into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao211 stdm80 ao211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.21 + 0.092*sl 0.21 + 0.093*sl 0.21 + 0.093*sl t phl 0.35 0.20 + 0.073*sl 0.20 + 0.072*sl 0.21 + 0.071*sl t r 0.89 0.49 + 0.201*sl 0.47 + 0.206*sl 0.45 + 0.209*sl t f 0.50 0.22 + 0.138*sl 0.22 + 0.141*sl 0.20 + 0.142*sl b to y t plh 0.37 0.19 + 0.091*sl 0.18 + 0.094*sl 0.18 + 0.093*sl t phl 0.36 0.21 + 0.072*sl 0.21 + 0.072*sl 0.22 + 0.071*sl t r 0.85 0.44 + 0.201*sl 0.43 + 0.206*sl 0.41 + 0.209*sl t f 0.50 0.23 + 0.136*sl 0.22 + 0.140*sl 0.20 + 0.143*sl c to y t plh 0.54 0.35 + 0.095*sl 0.36 + 0.094*sl 0.36 + 0.094*sl t phl 0.36 0.26 + 0.046*sl 0.27 + 0.045*sl 0.27 + 0.044*sl t r 0.92 0.52 + 0.199*sl 0.51 + 0.204*sl 0.49 + 0.206*sl t f 0.43 0.28 + 0.079*sl 0.27 + 0.081*sl 0.26 + 0.083*sl d to y t plh 0.58 0.39 + 0.095*sl 0.39 + 0.094*sl 0.39 + 0.094*sl t phl 0.38 0.29 + 0.048*sl 0.29 + 0.046*sl 0.30 + 0.045*sl t r 0.91 0.51 + 0.201*sl 0.50 + 0.205*sl 0.49 + 0.206*sl t f 0.50 0.34 + 0.080*sl 0.33 + 0.081*sl 0.32 + 0.083*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.22 + 0.043*sl 0.21 + 0.047*sl 0.21 + 0.047*sl t phl 0.27 0.19 + 0.036*sl 0.20 + 0.035*sl 0.20 + 0.035*sl t r 0.70 0.50 + 0.099*sl 0.49 + 0.101*sl 0.48 + 0.103*sl t f 0.34 0.21 + 0.066*sl 0.21 + 0.067*sl 0.20 + 0.068*sl b to y t plh 0.27 0.19 + 0.042*sl 0.17 + 0.046*sl 0.17 + 0.047*sl t phl 0.27 0.20 + 0.035*sl 0.20 + 0.035*sl 0.20 + 0.035*sl t r 0.63 0.43 + 0.100*sl 0.43 + 0.101*sl 0.42 + 0.103*sl t f 0.35 0.22 + 0.064*sl 0.21 + 0.067*sl 0.20 + 0.068*sl c to y t plh 0.45 0.36 + 0.048*sl 0.36 + 0.048*sl 0.36 + 0.047*sl t phl 0.30 0.25 + 0.023*sl 0.25 + 0.022*sl 0.26 + 0.022*sl t r 0.73 0.53 + 0.098*sl 0.53 + 0.100*sl 0.51 + 0.102*sl t f 0.34 0.27 + 0.038*sl 0.27 + 0.038*sl 0.26 + 0.039*sl d to y t plh 0.51 0.41 + 0.049*sl 0.42 + 0.048*sl 0.42 + 0.047*sl t phl 0.33 0.28 + 0.024*sl 0.28 + 0.024*sl 0.29 + 0.023*sl t r 0.73 0.53 + 0.098*sl 0.52 + 0.101*sl 0.51 + 0.102*sl t f 0.42 0.34 + 0.039*sl 0.34 + 0.039*sl 0.34 + 0.040*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-91 STD80/stdm80 ao22/ao22d2 two 2-ands into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao22 ao22d2 ao22 ao22d2 abcdabcd 0.5 0.5 0.9 0.9 0.9 0.9 1.6 1.6 1.7 3.0 stdm80 ao22 ao22d2 ao22 ao22d2 abcdabcd 1.0 1.0 1.0 1.0 2.1 2.0 2.1 2.1 1.7 3.0 c d a b y truth table abcdy 11xx0 xx110 0x0x1 0xx01 x0x01 x00x1
STD80/stdm80 3-92 sec asic ao22/ao22d2 two 2-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao22 STD80 ao22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.13 + 0.047*sl 0.14 + 0.041*sl 0.14 + 0.041*sl t phl 0.28 0.17 + 0.057*sl 0.17 + 0.054*sl 0.16 + 0.055*sl t r 0.43 0.27 + 0.081*sl 0.26 + 0.088*sl 0.19 + 0.095*sl t f 0.42 0.23 + 0.095*sl 0.21 + 0.105*sl 0.16 + 0.111*sl b to y t plh 0.24 0.15 + 0.044*sl 0.16 + 0.040*sl 0.15 + 0.041*sl t phl 0.26 0.14 + 0.057*sl 0.15 + 0.054*sl 0.14 + 0.055*sl t r 0.46 0.30 + 0.078*sl 0.28 + 0.088*sl 0.21 + 0.095*sl t f 0.41 0.22 + 0.096*sl 0.20 + 0.106*sl 0.16 + 0.111*sl c to y t plh 0.26 0.17 + 0.046*sl 0.18 + 0.041*sl 0.18 + 0.041*sl t phl 0.42 0.31 + 0.055*sl 0.31 + 0.055*sl 0.31 + 0.055*sl t r 0.42 0.26 + 0.081*sl 0.24 + 0.090*sl 0.19 + 0.095*sl t f 0.59 0.39 + 0.103*sl 0.38 + 0.107*sl 0.35 + 0.111*sl d to y t plh 0.28 0.19 + 0.044*sl 0.20 + 0.041*sl 0.19 + 0.041*sl t phl 0.40 0.29 + 0.055*sl 0.29 + 0.055*sl 0.29 + 0.055*sl t r 0.44 0.28 + 0.081*sl 0.26 + 0.090*sl 0.21 + 0.095*sl t f 0.59 0.38 + 0.106*sl 0.38 + 0.108*sl 0.35 + 0.111*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.14 + 0.021*sl t phl 0.22 0.16 + 0.030*sl 0.17 + 0.027*sl 0.17 + 0.027*sl t r 0.36 0.28 + 0.039*sl 0.27 + 0.043*sl 0.22 + 0.048*sl t f 0.33 0.23 + 0.047*sl 0.23 + 0.050*sl 0.18 + 0.055*sl b to y t plh 0.20 0.15 + 0.024*sl 0.16 + 0.021*sl 0.16 + 0.021*sl t phl 0.20 0.14 + 0.029*sl 0.15 + 0.028*sl 0.15 + 0.027*sl t r 0.38 0.31 + 0.039*sl 0.30 + 0.043*sl 0.24 + 0.048*sl t f 0.32 0.22 + 0.046*sl 0.21 + 0.051*sl 0.17 + 0.055*sl c to y t plh 0.21 0.17 + 0.024*sl 0.17 + 0.022*sl 0.18 + 0.021*sl t phl 0.35 0.30 + 0.028*sl 0.30 + 0.028*sl 0.30 + 0.027*sl t r 0.34 0.26 + 0.040*sl 0.25 + 0.044*sl 0.21 + 0.048*sl t f 0.48 0.37 + 0.051*sl 0.37 + 0.052*sl 0.35 + 0.055*sl d to y t plh 0.23 0.18 + 0.023*sl 0.19 + 0.022*sl 0.19 + 0.021*sl t phl 0.33 0.27 + 0.029*sl 0.28 + 0.028*sl 0.28 + 0.027*sl t r 0.36 0.28 + 0.041*sl 0.27 + 0.044*sl 0.23 + 0.048*sl t f 0.47 0.37 + 0.051*sl 0.37 + 0.053*sl 0.35 + 0.055*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-93 STD80/stdm80 ao22a/ao22d2a 2-and and 2-nor into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao22a stdm80 ao22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.18 + 0.062*sl 0.17 + 0.063*sl 0.17 + 0.063*sl t phl 0.34 0.20 + 0.073*sl 0.20 + 0.072*sl 0.20 + 0.071*sl t r 0.56 0.30 + 0.132*sl 0.29 + 0.136*sl 0.26 + 0.139*sl t f 0.51 0.25 + 0.134*sl 0.23 + 0.140*sl 0.21 + 0.142*sl b to y t plh 0.32 0.20 + 0.062*sl 0.19 + 0.063*sl 0.19 + 0.063*sl t phl 0.33 0.18 + 0.073*sl 0.19 + 0.072*sl 0.19 + 0.072*sl t r 0.59 0.33 + 0.131*sl 0.32 + 0.136*sl 0.29 + 0.139*sl t f 0.51 0.24 + 0.137*sl 0.23 + 0.140*sl 0.21 + 0.142*sl c to y t plh 0.51 0.38 + 0.065*sl 0.39 + 0.064*sl 0.39 + 0.063*sl t phl 0.73 0.57 + 0.076*sl 0.58 + 0.073*sl 0.59 + 0.072*sl t r 0.56 0.29 + 0.135*sl 0.29 + 0.137*sl 0.27 + 0.139*sl t f 0.74 0.46 + 0.142*sl 0.46 + 0.142*sl 0.46 + 0.142*sl d to y t plh 0.53 0.40 + 0.065*sl 0.41 + 0.063*sl 0.41 + 0.063*sl t phl 0.72 0.57 + 0.076*sl 0.58 + 0.073*sl 0.59 + 0.072*sl t r 0.59 0.32 + 0.135*sl 0.31 + 0.138*sl 0.30 + 0.139*sl t f 0.74 0.46 + 0.142*sl 0.46 + 0.142*sl 0.46 + 0.142*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.17 + 0.032*sl 0.18 + 0.031*sl 0.17 + 0.032*sl t phl 0.27 0.19 + 0.037*sl 0.20 + 0.036*sl 0.20 + 0.036*sl t r 0.43 0.30 + 0.064*sl 0.30 + 0.066*sl 0.28 + 0.068*sl t f 0.38 0.25 + 0.066*sl 0.24 + 0.068*sl 0.23 + 0.070*sl b to y t plh 0.26 0.20 + 0.031*sl 0.20 + 0.031*sl 0.20 + 0.032*sl t phl 0.26 0.18 + 0.038*sl 0.19 + 0.037*sl 0.19 + 0.036*sl t r 0.46 0.33 + 0.063*sl 0.32 + 0.066*sl 0.31 + 0.068*sl t f 0.37 0.24 + 0.067*sl 0.23 + 0.069*sl 0.23 + 0.070*sl c to y t plh 0.52 0.46 + 0.033*sl 0.46 + 0.032*sl 0.46 + 0.032*sl t phl 0.71 0.64 + 0.039*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.46 0.32 + 0.066*sl 0.32 + 0.068*sl 0.31 + 0.069*sl t f 0.59 0.45 + 0.070*sl 0.45 + 0.071*sl 0.45 + 0.071*sl d to y t plh 0.50 0.44 + 0.033*sl 0.44 + 0.033*sl 0.44 + 0.032*sl t phl 0.72 0.64 + 0.038*sl 0.65 + 0.037*sl 0.65 + 0.037*sl t r 0.43 0.30 + 0.066*sl 0.29 + 0.067*sl 0.28 + 0.069*sl t f 0.59 0.45 + 0.071*sl 0.45 + 0.071*sl 0.45 + 0.070*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-94 sec asic ao22a/ao22d2a 2-and and 2-nor into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao22a ao22d2a ao22a ao22d2a abcdabcd 0.9 0.9 0.6 0.6 1.4 1.8 0.7 0.7 2.7 4.0 stdm80 ao22a ao22d2a ao22a ao22d2a abcdabcd 1.0 1.0 0.7 0.7 2.1 2.0 0.7 0.7 2.7 4.0 c d a b y truth table abcdy 11xx0 xx000 other states 1
sec asic 3-95 STD80/stdm80 ao22a/ao22d2a 2-and and 2-nor into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao22a STD80 ao22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.13 + 0.047*sl 0.14 + 0.041*sl 0.14 + 0.041*sl t phl 0.28 0.17 + 0.056*sl 0.17 + 0.054*sl 0.16 + 0.055*sl t r 0.43 0.28 + 0.080*sl 0.26 + 0.088*sl 0.19 + 0.095*sl t f 0.42 0.23 + 0.096*sl 0.21 + 0.105*sl 0.16 + 0.111*sl b to y t plh 0.24 0.15 + 0.044*sl 0.16 + 0.040*sl 0.15 + 0.041*sl t phl 0.26 0.14 + 0.056*sl 0.15 + 0.054*sl 0.14 + 0.055*sl t r 0.46 0.30 + 0.079*sl 0.28 + 0.088*sl 0.21 + 0.095*sl t f 0.41 0.22 + 0.097*sl 0.20 + 0.106*sl 0.16 + 0.111*sl c to y t plh 0.35 0.26 + 0.044*sl 0.27 + 0.042*sl 0.27 + 0.042*sl t phl 0.55 0.43 + 0.058*sl 0.44 + 0.056*sl 0.44 + 0.055*sl t r 0.38 0.21 + 0.088*sl 0.20 + 0.093*sl 0.18 + 0.095*sl t f 0.58 0.36 + 0.109*sl 0.36 + 0.110*sl 0.35 + 0.111*sl d to y t plh 0.36 0.27 + 0.044*sl 0.28 + 0.042*sl 0.28 + 0.041*sl t phl 0.54 0.43 + 0.058*sl 0.43 + 0.056*sl 0.44 + 0.055*sl t r 0.40 0.22 + 0.090*sl 0.22 + 0.093*sl 0.20 + 0.095*sl t f 0.58 0.36 + 0.110*sl 0.36 + 0.110*sl 0.35 + 0.111*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.14 + 0.021*sl t phl 0.22 0.16 + 0.031*sl 0.17 + 0.027*sl 0.17 + 0.027*sl t r 0.36 0.28 + 0.039*sl 0.27 + 0.043*sl 0.22 + 0.048*sl t f 0.32 0.23 + 0.047*sl 0.22 + 0.050*sl 0.18 + 0.055*sl b to y t plh 0.20 0.15 + 0.024*sl 0.16 + 0.021*sl 0.16 + 0.021*sl t phl 0.20 0.14 + 0.029*sl 0.15 + 0.027*sl 0.15 + 0.027*sl t r 0.38 0.31 + 0.039*sl 0.30 + 0.043*sl 0.24 + 0.048*sl t f 0.32 0.22 + 0.047*sl 0.21 + 0.051*sl 0.17 + 0.055*sl c to y t plh 0.37 0.32 + 0.024*sl 0.33 + 0.021*sl 0.33 + 0.021*sl t phl 0.53 0.47 + 0.029*sl 0.48 + 0.028*sl 0.48 + 0.028*sl t r 0.33 0.23 + 0.047*sl 0.24 + 0.046*sl 0.21 + 0.049*sl t f 0.46 0.35 + 0.055*sl 0.35 + 0.054*sl 0.34 + 0.055*sl d to y t plh 0.36 0.31 + 0.023*sl 0.32 + 0.022*sl 0.32 + 0.021*sl t phl 0.54 0.48 + 0.029*sl 0.48 + 0.028*sl 0.49 + 0.028*sl t r 0.30 0.21 + 0.044*sl 0.21 + 0.046*sl 0.19 + 0.049*sl t f 0.46 0.35 + 0.055*sl 0.35 + 0.055*sl 0.34 + 0.055*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-96 sec asic ao22a/ao22d2a 2-and and 2-nor into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao22a stdm80 ao22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.18 + 0.062*sl 0.17 + 0.063*sl 0.17 + 0.063*sl t phl 0.34 0.20 + 0.073*sl 0.20 + 0.072*sl 0.20 + 0.071*sl t r 0.56 0.30 + 0.132*sl 0.29 + 0.136*sl 0.26 + 0.139*sl t f 0.51 0.25 + 0.134*sl 0.23 + 0.140*sl 0.21 + 0.142*sl b to y t plh 0.32 0.20 + 0.062*sl 0.19 + 0.063*sl 0.19 + 0.063*sl t phl 0.33 0.18 + 0.073*sl 0.19 + 0.072*sl 0.19 + 0.072*sl t r 0.59 0.33 + 0.131*sl 0.32 + 0.136*sl 0.29 + 0.139*sl t f 0.51 0.24 + 0.137*sl 0.23 + 0.140*sl 0.21 + 0.142*sl c to y t plh 0.51 0.38 + 0.065*sl 0.39 + 0.064*sl 0.39 + 0.063*sl t phl 0.73 0.57 + 0.076*sl 0.58 + 0.073*sl 0.59 + 0.072*sl t r 0.56 0.29 + 0.135*sl 0.29 + 0.137*sl 0.27 + 0.139*sl t f 0.74 0.46 + 0.142*sl 0.46 + 0.142*sl 0.46 + 0.142*sl d to y t plh 0.53 0.40 + 0.065*sl 0.41 + 0.063*sl 0.41 + 0.063*sl t phl 0.72 0.57 + 0.076*sl 0.58 + 0.073*sl 0.59 + 0.072*sl t r 0.59 0.32 + 0.135*sl 0.31 + 0.138*sl 0.30 + 0.139*sl t f 0.74 0.46 + 0.142*sl 0.46 + 0.142*sl 0.46 + 0.142*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.17 + 0.032*sl 0.18 + 0.031*sl 0.17 + 0.032*sl t phl 0.27 0.19 + 0.037*sl 0.20 + 0.036*sl 0.20 + 0.036*sl t r 0.43 0.30 + 0.064*sl 0.30 + 0.066*sl 0.28 + 0.068*sl t f 0.38 0.25 + 0.066*sl 0.24 + 0.068*sl 0.23 + 0.070*sl b to y t plh 0.26 0.20 + 0.031*sl 0.20 + 0.031*sl 0.20 + 0.032*sl t phl 0.26 0.18 + 0.038*sl 0.19 + 0.037*sl 0.19 + 0.036*sl t r 0.46 0.33 + 0.063*sl 0.32 + 0.066*sl 0.31 + 0.068*sl t f 0.37 0.24 + 0.067*sl 0.23 + 0.069*sl 0.23 + 0.070*sl c to y t plh 0.52 0.46 + 0.033*sl 0.46 + 0.032*sl 0.46 + 0.032*sl t phl 0.71 0.64 + 0.039*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.46 0.32 + 0.066*sl 0.32 + 0.068*sl 0.31 + 0.069*sl t f 0.59 0.45 + 0.070*sl 0.45 + 0.071*sl 0.45 + 0.071*sl d to y t plh 0.50 0.44 + 0.033*sl 0.44 + 0.033*sl 0.44 + 0.032*sl t phl 0.72 0.64 + 0.038*sl 0.65 + 0.037*sl 0.65 + 0.037*sl t r 0.43 0.30 + 0.066*sl 0.29 + 0.067*sl 0.28 + 0.069*sl t f 0.59 0.45 + 0.071*sl 0.45 + 0.071*sl 0.45 + 0.070*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-97 STD80/stdm80 ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao222 ao222d2 ao222 ao222d2 abcdefabcdef 0.4 0.5 0.5 0.5 0.8 0.8 0.4 0.4 0.4 0.4 0.6 0.6 2.7 4.0 stdm80 ao222 ao222d2 ao222 ao222d2 abcdefabcdef 1.1 1.0 1.0 1.0 1.0 1.0 0.8 0.8 0.7 0.7 0.7 0.7 2.7 4.0 c d a b y e f truth table abcdefy 11xxxx0 xx11xx0 xxxx110 other states 1
STD80/stdm80 3-98 sec asic ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.18 + 0.055*sl 0.18 + 0.058*sl 0.16 + 0.060*sl t phl 0.30 0.19 + 0.055*sl 0.19 + 0.054*sl 0.19 + 0.055*sl t r 0.68 0.42 + 0.129*sl 0.41 + 0.134*sl 0.37 + 0.138*sl t f 0.47 0.28 + 0.098*sl 0.26 + 0.106*sl 0.21 + 0.111*sl b to y t plh 0.31 0.20 + 0.053*sl 0.19 + 0.058*sl 0.18 + 0.060*sl t phl 0.28 0.17 + 0.056*sl 0.17 + 0.055*sl 0.17 + 0.055*sl t r 0.72 0.46 + 0.128*sl 0.45 + 0.133*sl 0.40 + 0.138*sl t f 0.47 0.27 + 0.100*sl 0.25 + 0.106*sl 0.21 + 0.111*sl c to y t plh 0.39 0.27 + 0.061*sl 0.27 + 0.060*sl 0.27 + 0.060*sl t phl 0.45 0.33 + 0.056*sl 0.33 + 0.055*sl 0.34 + 0.055*sl t r 0.70 0.45 + 0.128*sl 0.43 + 0.134*sl 0.40 + 0.138*sl t f 0.65 0.44 + 0.104*sl 0.43 + 0.108*sl 0.41 + 0.111*sl d to y t plh 0.41 0.29 + 0.060*sl 0.29 + 0.060*sl 0.29 + 0.060*sl t phl 0.42 0.31 + 0.056*sl 0.31 + 0.055*sl 0.32 + 0.055*sl t r 0.73 0.47 + 0.129*sl 0.46 + 0.134*sl 0.43 + 0.138*sl t f 0.65 0.44 + 0.105*sl 0.43 + 0.108*sl 0.41 + 0.111*sl e to y t plh 0.45 0.32 + 0.062*sl 0.32 + 0.060*sl 0.33 + 0.060*sl t phl 0.56 0.44 + 0.060*sl 0.45 + 0.057*sl 0.47 + 0.055*sl t r 0.70 0.44 + 0.130*sl 0.43 + 0.135*sl 0.40 + 0.138*sl t f 0.84 0.62 + 0.107*sl 0.62 + 0.109*sl 0.61 + 0.110*sl f to y t plh 0.46 0.34 + 0.061*sl 0.34 + 0.060*sl 0.35 + 0.060*sl t phl 0.54 0.42 + 0.060*sl 0.42 + 0.057*sl 0.44 + 0.055*sl t r 0.73 0.47 + 0.130*sl 0.46 + 0.135*sl 0.43 + 0.138*sl t f 0.84 0.62 + 0.109*sl 0.62 + 0.109*sl 0.61 + 0.110*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-99 STD80/stdm80 ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.56 0.53 + 0.017*sl 0.54 + 0.013*sl 0.55 + 0.012*sl t phl 0.48 0.44 + 0.022*sl 0.44 + 0.019*sl 0.45 + 0.018*sl t r 0.16 0.13 + 0.018*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.16 0.09 + 0.031*sl 0.09 + 0.031*sl 0.07 + 0.034*sl b to y t plh 0.60 0.57 + 0.017*sl 0.57 + 0.013*sl 0.59 + 0.012*sl t phl 0.46 0.42 + 0.021*sl 0.42 + 0.019*sl 0.43 + 0.018*sl t r 0.17 0.12 + 0.021*sl 0.12 + 0.022*sl 0.09 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.09 + 0.031*sl 0.07 + 0.034*sl c to y t plh 0.66 0.62 + 0.018*sl 0.63 + 0.013*sl 0.64 + 0.012*sl t phl 0.58 0.54 + 0.022*sl 0.54 + 0.019*sl 0.55 + 0.018*sl t r 0.16 0.13 + 0.019*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d to y t plh 0.69 0.66 + 0.017*sl 0.67 + 0.013*sl 0.68 + 0.012*sl t phl 0.56 0.51 + 0.022*sl 0.52 + 0.019*sl 0.53 + 0.018*sl t r 0.17 0.13 + 0.022*sl 0.13 + 0.022*sl 0.09 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.10 + 0.031*sl 0.07 + 0.034*sl e to y t plh 0.71 0.68 + 0.017*sl 0.69 + 0.013*sl 0.70 + 0.012*sl t phl 0.65 0.60 + 0.022*sl 0.61 + 0.019*sl 0.62 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.10 + 0.031*sl 0.07 + 0.034*sl f to y t plh 0.75 0.72 + 0.018*sl 0.73 + 0.013*sl 0.74 + 0.012*sl t phl 0.63 0.58 + 0.022*sl 0.59 + 0.019*sl 0.60 + 0.018*sl t r 0.17 0.13 + 0.022*sl 0.13 + 0.022*sl 0.09 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-100 sec asic ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.23 + 0.089*sl 0.21 + 0.094*sl 0.21 + 0.094*sl t phl 0.37 0.22 + 0.074*sl 0.23 + 0.072*sl 0.23 + 0.072*sl t r 0.95 0.54 + 0.205*sl 0.54 + 0.208*sl 0.52 + 0.210*sl t f 0.59 0.32 + 0.136*sl 0.30 + 0.140*sl 0.28 + 0.143*sl b to y t plh 0.43 0.25 + 0.091*sl 0.24 + 0.093*sl 0.24 + 0.093*sl t phl 0.36 0.21 + 0.073*sl 0.21 + 0.073*sl 0.22 + 0.072*sl t r 1.00 0.59 + 0.205*sl 0.58 + 0.208*sl 0.56 + 0.210*sl t f 0.58 0.31 + 0.137*sl 0.30 + 0.141*sl 0.29 + 0.142*sl c to y t plh 0.61 0.42 + 0.096*sl 0.42 + 0.094*sl 0.43 + 0.094*sl t phl 0.58 0.43 + 0.075*sl 0.43 + 0.073*sl 0.44 + 0.072*sl t r 1.02 0.62 + 0.200*sl 0.61 + 0.204*sl 0.60 + 0.206*sl t f 0.81 0.53 + 0.140*sl 0.53 + 0.142*sl 0.53 + 0.142*sl d to y t plh 0.64 0.45 + 0.095*sl 0.46 + 0.094*sl 0.46 + 0.094*sl t phl 0.57 0.42 + 0.075*sl 0.42 + 0.073*sl 0.43 + 0.072*sl t r 1.06 0.66 + 0.201*sl 0.65 + 0.204*sl 0.64 + 0.206*sl t f 0.82 0.53 + 0.141*sl 0.53 + 0.141*sl 0.53 + 0.142*sl e to y t plh 0.72 0.53 + 0.097*sl 0.53 + 0.095*sl 0.54 + 0.094*sl t phl 0.73 0.57 + 0.081*sl 0.58 + 0.077*sl 0.60 + 0.074*sl t r 1.03 0.63 + 0.199*sl 0.62 + 0.204*sl 0.60 + 0.206*sl t f 1.05 0.76 + 0.145*sl 0.76 + 0.144*sl 0.77 + 0.142*sl f to y t plh 0.75 0.56 + 0.095*sl 0.57 + 0.094*sl 0.57 + 0.094*sl t phl 0.72 0.56 + 0.081*sl 0.57 + 0.077*sl 0.59 + 0.074*sl t r 1.07 0.67 + 0.200*sl 0.66 + 0.204*sl 0.64 + 0.206*sl t f 1.05 0.76 + 0.144*sl 0.77 + 0.143*sl 0.77 + 0.142*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-101 STD80/stdm80 ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.80 0.75 + 0.023*sl 0.76 + 0.019*sl 0.78 + 0.017*sl t phl 0.64 0.59 + 0.029*sl 0.60 + 0.024*sl 0.61 + 0.022*sl t r 0.21 0.15 + 0.031*sl 0.15 + 0.032*sl 0.13 + 0.033*sl t f 0.20 0.12 + 0.041*sl 0.13 + 0.037*sl 0.13 + 0.038*sl b to y t plh 0.86 0.81 + 0.023*sl 0.82 + 0.019*sl 0.84 + 0.017*sl t phl 0.63 0.58 + 0.029*sl 0.59 + 0.024*sl 0.60 + 0.022*sl t r 0.21 0.15 + 0.030*sl 0.15 + 0.032*sl 0.14 + 0.033*sl t f 0.20 0.12 + 0.039*sl 0.12 + 0.038*sl 0.12 + 0.039*sl c to y t plh 1.01 0.97 + 0.023*sl 0.98 + 0.019*sl 0.99 + 0.017*sl t phl 0.78 0.72 + 0.028*sl 0.73 + 0.024*sl 0.75 + 0.022*sl t r 0.21 0.15 + 0.032*sl 0.15 + 0.032*sl 0.14 + 0.033*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.12 + 0.038*sl d to y t plh 1.08 1.03 + 0.023*sl 1.04 + 0.019*sl 1.06 + 0.017*sl t phl 0.77 0.71 + 0.029*sl 0.72 + 0.024*sl 0.74 + 0.022*sl t r 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.14 + 0.033*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.12 + 0.038*sl e to y t plh 1.13 1.09 + 0.023*sl 1.10 + 0.019*sl 1.11 + 0.017*sl t phl 0.86 0.80 + 0.029*sl 0.82 + 0.024*sl 0.83 + 0.022*sl t r 0.21 0.15 + 0.031*sl 0.15 + 0.032*sl 0.14 + 0.033*sl t f 0.21 0.13 + 0.038*sl 0.13 + 0.038*sl 0.13 + 0.038*sl f to y t plh 1.19 1.15 + 0.023*sl 1.16 + 0.019*sl 1.17 + 0.017*sl t phl 0.85 0.79 + 0.029*sl 0.81 + 0.024*sl 0.82 + 0.022*sl t r 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-102 sec asic ao222a/ao222d2a inverting 2-of-3 majority with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao222a ao222d2a ao222a ao222d2a abcabc 0.9 1.2 1.6 1.7 2.5 3.2 2.7 5.0 stdm80 ao222a ao222d2a ao222a ao222d2a abcabc 2.2 2.2 2.1 4.5 4.4 4.2 2.7 5.0 a b y c truth table abcy 11x0 1x10 x110 00x1 0x01 x001
sec asic 3-103 STD80/stdm80 ao222a/ao222d2a inverting 2-of-3 majority with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao222a STD80 ao222d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.24 + 0.053*sl 0.24 + 0.051*sl 0.25 + 0.050*sl t phl 0.45 0.33 + 0.059*sl 0.34 + 0.057*sl 0.35 + 0.055*sl t r 0.64 0.42 + 0.107*sl 0.41 + 0.112*sl 0.38 + 0.116*sl t f 0.60 0.39 + 0.105*sl 0.39 + 0.108*sl 0.37 + 0.111*sl b to y t plh 0.39 0.28 + 0.055*sl 0.28 + 0.051*sl 0.29 + 0.050*sl t phl 0.52 0.39 + 0.065*sl 0.40 + 0.060*sl 0.44 + 0.055*sl t r 0.63 0.42 + 0.106*sl 0.41 + 0.113*sl 0.38 + 0.116*sl t f 0.76 0.54 + 0.108*sl 0.54 + 0.109*sl 0.53 + 0.110*sl c to y t plh 0.41 0.30 + 0.054*sl 0.31 + 0.051*sl 0.31 + 0.050*sl t phl 0.49 0.36 + 0.065*sl 0.37 + 0.059*sl 0.41 + 0.055*sl t r 0.59 0.38 + 0.103*sl 0.36 + 0.111*sl 0.32 + 0.116*sl t f 0.78 0.57 + 0.107*sl 0.57 + 0.108*sl 0.54 + 0.110*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.25 + 0.029*sl 0.25 + 0.027*sl 0.26 + 0.026*sl t phl 0.39 0.33 + 0.030*sl 0.34 + 0.029*sl 0.35 + 0.028*sl t r 0.54 0.44 + 0.052*sl 0.43 + 0.056*sl 0.40 + 0.059*sl t f 0.51 0.40 + 0.052*sl 0.40 + 0.053*sl 0.38 + 0.055*sl b to y t plh 0.34 0.28 + 0.029*sl 0.28 + 0.027*sl 0.29 + 0.026*sl t phl 0.45 0.38 + 0.034*sl 0.38 + 0.031*sl 0.42 + 0.028*sl t r 0.54 0.43 + 0.053*sl 0.43 + 0.056*sl 0.40 + 0.059*sl t f 0.64 0.53 + 0.055*sl 0.53 + 0.055*sl 0.52 + 0.055*sl c to y t plh 0.36 0.30 + 0.029*sl 0.31 + 0.027*sl 0.31 + 0.026*sl t phl 0.42 0.35 + 0.034*sl 0.36 + 0.031*sl 0.39 + 0.028*sl t r 0.49 0.39 + 0.051*sl 0.38 + 0.056*sl 0.34 + 0.059*sl t f 0.66 0.56 + 0.053*sl 0.56 + 0.054*sl 0.54 + 0.055*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-104 sec asic ao222a/ao222d2a inverting 2-of-3 majority with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stm80 ao222a stdm80 ao222d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.52 0.35 + 0.085*sl 0.36 + 0.082*sl 0.37 + 0.080*sl t phl 0.58 0.42 + 0.079*sl 0.43 + 0.075*sl 0.45 + 0.073*sl t r 0.92 0.58 + 0.170*sl 0.58 + 0.172*sl 0.57 + 0.173*sl t f 0.77 0.49 + 0.141*sl 0.49 + 0.142*sl 0.49 + 0.142*sl b to y t plh 0.61 0.44 + 0.083*sl 0.45 + 0.081*sl 0.46 + 0.080*sl t phl 0.67 0.50 + 0.087*sl 0.52 + 0.080*sl 0.54 + 0.076*sl t r 0.94 0.60 + 0.166*sl 0.59 + 0.171*sl 0.58 + 0.172*sl t f 0.97 0.68 + 0.144*sl 0.69 + 0.143*sl 0.69 + 0.142*sl c to y t plh 0.64 0.47 + 0.082*sl 0.48 + 0.079*sl 0.49 + 0.078*sl t phl 0.65 0.48 + 0.087*sl 0.50 + 0.080*sl 0.53 + 0.076*sl t r 0.85 0.52 + 0.164*sl 0.50 + 0.169*sl 0.49 + 0.171*sl t f 0.99 0.71 + 0.141*sl 0.70 + 0.142*sl 0.71 + 0.141*sl *g 1 sl 3 *g 2 3 sl 7 *g 3 7 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.36 + 0.044*sl 0.36 + 0.042*sl 0.37 + 0.041*sl t phl 0.51 0.43 + 0.041*sl 0.43 + 0.039*sl 0.44 + 0.038*sl t r 0.76 0.59 + 0.084*sl 0.59 + 0.085*sl 0.58 + 0.086*sl t f 0.64 0.50 + 0.071*sl 0.50 + 0.071*sl 0.50 + 0.071*sl b to y t plh 0.52 0.44 + 0.043*sl 0.44 + 0.041*sl 0.45 + 0.040*sl t phl 0.58 0.49 + 0.045*sl 0.50 + 0.042*sl 0.52 + 0.040*sl t r 0.77 0.61 + 0.082*sl 0.60 + 0.084*sl 0.59 + 0.085*sl t f 0.81 0.67 + 0.072*sl 0.67 + 0.072*sl 0.67 + 0.072*sl c to y t plh 0.55 0.47 + 0.042*sl 0.47 + 0.041*sl 0.48 + 0.039*sl t phl 0.56 0.47 + 0.045*sl 0.48 + 0.042*sl 0.50 + 0.039*sl t r 0.68 0.52 + 0.080*sl 0.51 + 0.083*sl 0.50 + 0.085*sl t f 0.83 0.69 + 0.071*sl 0.69 + 0.071*sl 0.69 + 0.071*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-105 STD80/stdm80 ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao33 ao33d2 ao33 ao33d2 abcdefabcdef 0.5 0.6 0.6 1.0 1.0 1.0 0.4 0.4 0.4 0.6 0.6 0.6 2.3 3.7 stdm80 ao33 ao33d2 ao33 ao33d2 abcdefabcdef 1.0 1.1 1.0 1.0 1.0 1.0 0.8 0.8 0.8 0.7 0.7 0.7 2.3 3.7 y a b c d e f truth table abcdefy 111xxx0 xxx1110 other states 1
STD80/stdm80 3-106 sec asic ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.17 + 0.044*sl 0.17 + 0.041*sl 0.17 + 0.041*sl t phl 0.40 0.25 + 0.073*sl 0.25 + 0.073*sl 0.25 + 0.073*sl t r 0.51 0.35 + 0.082*sl 0.33 + 0.089*sl 0.27 + 0.095*sl t f 0.68 0.39 + 0.143*sl 0.38 + 0.149*sl 0.35 + 0.152*sl b to y t plh 0.27 0.19 + 0.043*sl 0.19 + 0.041*sl 0.19 + 0.041*sl t phl 0.39 0.25 + 0.074*sl 0.25 + 0.073*sl 0.25 + 0.073*sl t r 0.53 0.37 + 0.081*sl 0.35 + 0.089*sl 0.29 + 0.095*sl t f 0.68 0.39 + 0.144*sl 0.38 + 0.149*sl 0.35 + 0.152*sl c to y t plh 0.28 0.20 + 0.042*sl 0.20 + 0.041*sl 0.19 + 0.041*sl t phl 0.38 0.23 + 0.074*sl 0.23 + 0.073*sl 0.23 + 0.073*sl t r 0.56 0.40 + 0.081*sl 0.38 + 0.088*sl 0.32 + 0.095*sl t f 0.68 0.39 + 0.143*sl 0.38 + 0.150*sl 0.35 + 0.152*sl d to y t plh 0.31 0.22 + 0.044*sl 0.22 + 0.042*sl 0.22 + 0.041*sl t phl 0.64 0.49 + 0.073*sl 0.49 + 0.073*sl 0.50 + 0.073*sl t r 0.49 0.33 + 0.084*sl 0.31 + 0.091*sl 0.27 + 0.095*sl t f 0.96 0.66 + 0.151*sl 0.65 + 0.151*sl 0.65 + 0.152*sl e to y t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.24 + 0.041*sl t phl 0.63 0.49 + 0.074*sl 0.49 + 0.073*sl 0.49 + 0.073*sl t r 0.52 0.35 + 0.084*sl 0.33 + 0.091*sl 0.29 + 0.095*sl t f 0.96 0.66 + 0.149*sl 0.66 + 0.151*sl 0.65 + 0.152*sl f to y t plh 0.33 0.25 + 0.043*sl 0.25 + 0.041*sl 0.25 + 0.041*sl t phl 0.62 0.47 + 0.074*sl 0.47 + 0.073*sl 0.48 + 0.073*sl t r 0.54 0.37 + 0.085*sl 0.36 + 0.090*sl 0.32 + 0.095*sl t f 0.96 0.66 + 0.152*sl 0.66 + 0.151*sl 0.65 + 0.152*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-107 STD80/stdm80 ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao33d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.50 0.46 + 0.017*sl 0.47 + 0.013*sl 0.48 + 0.012*sl t phl 0.56 0.52 + 0.022*sl 0.52 + 0.019*sl 0.53 + 0.018*sl t r 0.15 0.10 + 0.024*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl b to y t plh 0.53 0.49 + 0.017*sl 0.50 + 0.013*sl 0.51 + 0.012*sl t phl 0.56 0.51 + 0.022*sl 0.52 + 0.019*sl 0.53 + 0.018*sl t r 0.15 0.11 + 0.024*sl 0.11 + 0.022*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl c to y t plh 0.55 0.52 + 0.016*sl 0.52 + 0.013*sl 0.53 + 0.012*sl t phl 0.54 0.50 + 0.022*sl 0.50 + 0.019*sl 0.51 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d to y t plh 0.55 0.51 + 0.017*sl 0.52 + 0.013*sl 0.53 + 0.012*sl t phl 0.72 0.67 + 0.023*sl 0.68 + 0.019*sl 0.69 + 0.018*sl t r 0.15 0.11 + 0.024*sl 0.11 + 0.022*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl e to y t plh 0.57 0.54 + 0.017*sl 0.55 + 0.013*sl 0.56 + 0.012*sl t phl 0.71 0.67 + 0.022*sl 0.67 + 0.019*sl 0.68 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.030*sl 0.07 + 0.034*sl f to y t plh 0.60 0.56 + 0.017*sl 0.57 + 0.013*sl 0.58 + 0.012*sl t phl 0.70 0.65 + 0.022*sl 0.66 + 0.019*sl 0.67 + 0.018*sl t r 0.15 0.12 + 0.019*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-108 sec asic ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.36 0.23 + 0.063*sl 0.23 + 0.063*sl 0.23 + 0.063*sl t phl 0.51 0.31 + 0.101*sl 0.32 + 0.100*sl 0.32 + 0.099*sl t r 0.69 0.42 + 0.133*sl 0.41 + 0.137*sl 0.39 + 0.140*sl t f 0.91 0.51 + 0.197*sl 0.50 + 0.201*sl 0.50 + 0.201*sl b to y t plh 0.38 0.25 + 0.064*sl 0.25 + 0.064*sl 0.26 + 0.063*sl t phl 0.53 0.32 + 0.102*sl 0.33 + 0.100*sl 0.34 + 0.099*sl t r 0.71 0.45 + 0.133*sl 0.43 + 0.137*sl 0.42 + 0.140*sl t f 0.91 0.52 + 0.196*sl 0.51 + 0.201*sl 0.50 + 0.201*sl c to y t plh 0.39 0.27 + 0.064*sl 0.27 + 0.063*sl 0.27 + 0.063*sl t phl 0.52 0.32 + 0.102*sl 0.32 + 0.101*sl 0.33 + 0.099*sl t r 0.74 0.48 + 0.133*sl 0.47 + 0.137*sl 0.45 + 0.139*sl t f 0.91 0.51 + 0.198*sl 0.51 + 0.201*sl 0.50 + 0.201*sl d to y t plh 0.47 0.34 + 0.065*sl 0.34 + 0.064*sl 0.35 + 0.063*sl t phl 0.88 0.68 + 0.101*sl 0.68 + 0.100*sl 0.69 + 0.099*sl t r 0.70 0.43 + 0.132*sl 0.42 + 0.137*sl 0.41 + 0.139*sl t f 1.26 0.86 + 0.202*sl 0.86 + 0.201*sl 0.86 + 0.201*sl e to y t plh 0.49 0.36 + 0.064*sl 0.37 + 0.064*sl 0.37 + 0.063*sl t phl 0.89 0.69 + 0.101*sl 0.69 + 0.100*sl 0.70 + 0.099*sl t r 0.72 0.46 + 0.133*sl 0.44 + 0.137*sl 0.43 + 0.139*sl t f 1.26 0.86 + 0.202*sl 0.86 + 0.201*sl 0.86 + 0.201*sl f to y t plh 0.51 0.38 + 0.065*sl 0.39 + 0.064*sl 0.39 + 0.063*sl t phl 0.89 0.69 + 0.101*sl 0.69 + 0.100*sl 0.70 + 0.099*sl t r 0.75 0.49 + 0.133*sl 0.47 + 0.137*sl 0.46 + 0.139*sl t f 1.26 0.86 + 0.201*sl 0.86 + 0.201*sl 0.86 + 0.201*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-109 STD80/stdm80 ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao33d2 [y ypp , , , , ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.70 0.66 + 0.022*sl 0.67 + 0.019*sl 0.68 + 0.017*sl t phl 0.76 0.70 + 0.029*sl 0.72 + 0.024*sl 0.73 + 0.022*sl t r 0.20 0.14 + 0.030*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.039*sl 0.14 + 0.037*sl 0.13 + 0.038*sl b to y t plh 0.75 0.70 + 0.022*sl 0.71 + 0.019*sl 0.73 + 0.017*sl t phl 0.77 0.71 + 0.029*sl 0.73 + 0.024*sl 0.74 + 0.022*sl t r 0.20 0.14 + 0.031*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.038*sl 0.13 + 0.038*sl 0.13 + 0.038*sl c to y t plh 0.78 0.74 + 0.022*sl 0.75 + 0.019*sl 0.76 + 0.017*sl t phl 0.77 0.71 + 0.029*sl 0.72 + 0.025*sl 0.74 + 0.022*sl t r 0.20 0.14 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.038*sl 0.13 + 0.039*sl 0.14 + 0.038*sl d to y t plh 0.82 0.78 + 0.022*sl 0.79 + 0.019*sl 0.80 + 0.017*sl t phl 0.98 0.92 + 0.029*sl 0.94 + 0.024*sl 0.95 + 0.022*sl t r 0.20 0.14 + 0.030*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl e to y t plh 0.86 0.82 + 0.023*sl 0.83 + 0.019*sl 0.84 + 0.017*sl t phl 0.99 0.93 + 0.029*sl 0.94 + 0.024*sl 0.96 + 0.022*sl t r 0.20 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl f to y t plh 0.90 0.86 + 0.022*sl 0.87 + 0.019*sl 0.88 + 0.017*sl t phl 0.99 0.93 + 0.029*sl 0.94 + 0.024*sl 0.96 + 0.022*sl t r 0.20 0.14 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-110 sec asic ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ao333 ao333 abcdefgh i 0.5 0.5 0.5 0.9 0.9 0.9 0.7 0.7 0.8 3.3 ao333d2 ao333d2 abcdefgh i 0.4 0.4 0.4 0.6 0.6 0.6 0.4 0.5 0.6 4.7 stdm80 ao333 ao333 abcdefgh i 1.1 1.0 1.0 1.0 1.0 1.0 0.9 0.8 0.9 3.3 ao333d2 ao333d2 abcdefgh i 0.5 0.5 0.5 0.7 0.7 0.7 0.5 0.6 0.7 4.7 d f a c y g i e b h truth table abcdefgh i y 111xxxxxx0 xxx111xxx0 xxxxxx 1110 other states 1
sec asic 3-111 STD80/stdm80 ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao333 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.24 + 0.055*sl 0.23 + 0.059*sl 0.23 + 0.060*sl t phl 0.43 0.29 + 0.074*sl 0.29 + 0.073*sl 0.29 + 0.073*sl t r 0.82 0.56 + 0.129*sl 0.55 + 0.135*sl 0.52 + 0.138*sl t f 0.80 0.51 + 0.143*sl 0.50 + 0.149*sl 0.47 + 0.152*sl b to y t plh 0.37 0.25 + 0.056*sl 0.25 + 0.059*sl 0.24 + 0.060*sl t phl 0.43 0.28 + 0.075*sl 0.28 + 0.073*sl 0.28 + 0.073*sl t r 0.86 0.59 + 0.130*sl 0.59 + 0.135*sl 0.55 + 0.138*sl t f 0.80 0.51 + 0.143*sl 0.50 + 0.150*sl 0.47 + 0.152*sl c to y t plh 0.38 0.27 + 0.056*sl 0.26 + 0.059*sl 0.26 + 0.060*sl t phl 0.41 0.26 + 0.075*sl 0.27 + 0.073*sl 0.27 + 0.073*sl t r 0.89 0.64 + 0.127*sl 0.62 + 0.134*sl 0.58 + 0.138*sl t f 0.79 0.51 + 0.143*sl 0.49 + 0.150*sl 0.47 + 0.152*sl d to y t plh 0.47 0.34 + 0.061*sl 0.35 + 0.060*sl 0.35 + 0.060*sl t phl 0.61 0.46 + 0.075*sl 0.46 + 0.074*sl 0.47 + 0.073*sl t r 0.85 0.59 + 0.131*sl 0.58 + 0.135*sl 0.55 + 0.138*sl t f 1.08 0.79 + 0.145*sl 0.78 + 0.150*sl 0.75 + 0.152*sl e to y t plh 0.49 0.37 + 0.060*sl 0.37 + 0.060*sl 0.37 + 0.060*sl t phl 0.60 0.45 + 0.076*sl 0.46 + 0.074*sl 0.47 + 0.073*sl t r 0.88 0.62 + 0.130*sl 0.61 + 0.135*sl 0.58 + 0.138*sl t f 1.08 0.79 + 0.145*sl 0.78 + 0.149*sl 0.75 + 0.152*sl f to y t plh 0.50 0.38 + 0.061*sl 0.38 + 0.060*sl 0.39 + 0.060*sl t phl 0.59 0.44 + 0.076*sl 0.44 + 0.074*sl 0.45 + 0.073*sl t r 0.91 0.65 + 0.130*sl 0.64 + 0.135*sl 0.61 + 0.138*sl t f 1.08 0.79 + 0.145*sl 0.78 + 0.149*sl 0.75 + 0.152*sl g to y t plh 0.54 0.41 + 0.062*sl 0.41 + 0.061*sl 0.42 + 0.060*sl t phl 0.75 0.59 + 0.079*sl 0.60 + 0.076*sl 0.63 + 0.073*sl t r 0.85 0.59 + 0.130*sl 0.57 + 0.135*sl 0.55 + 0.138*sl t f 1.37 1.08 + 0.145*sl 1.07 + 0.150*sl 1.05 + 0.152*sl h to y t plh 0.56 0.43 + 0.062*sl 0.43 + 0.060*sl 0.44 + 0.060*sl t phl 0.74 0.58 + 0.080*sl 0.59 + 0.076*sl 0.62 + 0.073*sl t r 0.87 0.61 + 0.131*sl 0.60 + 0.135*sl 0.58 + 0.138*sl t f 1.37 1.08 + 0.148*sl 1.07 + 0.149*sl 1.05 + 0.152*sl i to y t plh 0.57 0.45 + 0.062*sl 0.45 + 0.060*sl 0.46 + 0.060*sl t phl 0.73 0.57 + 0.080*sl 0.58 + 0.076*sl 0.61 + 0.073*sl t r 0.91 0.64 + 0.131*sl 0.63 + 0.135*sl 0.61 + 0.138*sl t f 1.37 1.08 + 0.149*sl 1.07 + 0.150*sl 1.05 + 0.152*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-112 sec asic ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ao333d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.63 + 0.017*sl 0.64 + 0.013*sl 0.65 + 0.012*sl t phl 0.62 0.58 + 0.022*sl 0.59 + 0.019*sl 0.59 + 0.018*sl t r 0.18 0.14 + 0.019*sl 0.13 + 0.022*sl 0.09 + 0.026*sl t f 0.17 0.12 + 0.027*sl 0.11 + 0.031*sl 0.08 + 0.034*sl b to y t plh 0.70 0.66 + 0.018*sl 0.67 + 0.013*sl 0.69 + 0.012*sl t phl 0.62 0.57 + 0.022*sl 0.58 + 0.019*sl 0.59 + 0.018*sl t r 0.18 0.14 + 0.019*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.17 0.12 + 0.027*sl 0.11 + 0.031*sl 0.08 + 0.034*sl c to y t plh 0.73 0.69 + 0.018*sl 0.70 + 0.014*sl 0.72 + 0.012*sl t phl 0.60 0.56 + 0.022*sl 0.56 + 0.019*sl 0.57 + 0.018*sl t r 0.18 0.14 + 0.019*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.030*sl 0.08 + 0.034*sl d to y t plh 0.78 0.74 + 0.018*sl 0.75 + 0.013*sl 0.77 + 0.012*sl t phl 0.75 0.71 + 0.022*sl 0.72 + 0.019*sl 0.72 + 0.018*sl t r 0.18 0.14 + 0.020*sl 0.13 + 0.022*sl 0.09 + 0.026*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.030*sl 0.08 + 0.034*sl e to y t plh 0.81 0.78 + 0.018*sl 0.79 + 0.013*sl 0.80 + 0.012*sl t phl 0.75 0.70 + 0.022*sl 0.71 + 0.019*sl 0.72 + 0.018*sl t r 0.18 0.14 + 0.019*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.030*sl 0.08 + 0.034*sl f to y t plh 0.85 0.81 + 0.018*sl 0.82 + 0.014*sl 0.84 + 0.012*sl t phl 0.73 0.69 + 0.023*sl 0.70 + 0.019*sl 0.70 + 0.018*sl t r 0.18 0.14 + 0.021*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.030*sl 0.08 + 0.034*sl g to y t plh 0.85 0.81 + 0.018*sl 0.82 + 0.013*sl 0.84 + 0.012*sl t phl 0.85 0.80 + 0.023*sl 0.81 + 0.019*sl 0.82 + 0.018*sl t r 0.18 0.14 + 0.019*sl 0.13 + 0.022*sl 0.09 + 0.026*sl t f 0.19 0.12 + 0.031*sl 0.13 + 0.030*sl 0.09 + 0.034*sl h to y t plh 0.88 0.85 + 0.018*sl 0.86 + 0.013*sl 0.87 + 0.012*sl t phl 0.84 0.80 + 0.023*sl 0.80 + 0.019*sl 0.81 + 0.018*sl t r 0.18 0.14 + 0.018*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.19 0.13 + 0.030*sl 0.13 + 0.030*sl 0.09 + 0.034*sl i to y t plh 0.92 0.88 + 0.018*sl 0.89 + 0.014*sl 0.91 + 0.012*sl t phl 0.83 0.78 + 0.023*sl 0.79 + 0.019*sl 0.80 + 0.018*sl t r 0.18 0.14 + 0.019*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.18 0.13 + 0.027*sl 0.12 + 0.030*sl 0.09 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-113 STD80/stdm80 ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao333 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.51 0.33 + 0.094*sl 0.32 + 0.094*sl 0.33 + 0.094*sl t phl 0.55 0.35 + 0.103*sl 0.35 + 0.101*sl 0.36 + 0.099*sl t r 1.18 0.77 + 0.206*sl 0.76 + 0.209*sl 0.75 + 0.210*sl t f 1.07 0.68 + 0.197*sl 0.66 + 0.201*sl 0.66 + 0.201*sl b to y t plh 0.54 0.35 + 0.094*sl 0.35 + 0.094*sl 0.36 + 0.094*sl t phl 0.56 0.35 + 0.103*sl 0.36 + 0.102*sl 0.37 + 0.099*sl t r 1.22 0.81 + 0.206*sl 0.80 + 0.209*sl 0.79 + 0.210*sl t f 1.07 0.68 + 0.197*sl 0.67 + 0.201*sl 0.66 + 0.201*sl c to y t plh 0.57 0.38 + 0.094*sl 0.38 + 0.094*sl 0.38 + 0.094*sl t phl 0.56 0.35 + 0.103*sl 0.35 + 0.102*sl 0.37 + 0.100*sl t r 1.27 0.85 + 0.205*sl 0.84 + 0.209*sl 0.83 + 0.210*sl t f 1.07 0.67 + 0.198*sl 0.67 + 0.201*sl 0.66 + 0.201*sl d to y t plh 0.75 0.55 + 0.096*sl 0.56 + 0.095*sl 0.56 + 0.094*sl t phl 0.82 0.61 + 0.105*sl 0.61 + 0.102*sl 0.63 + 0.100*sl t r 1.26 0.85 + 0.201*sl 0.85 + 0.204*sl 0.84 + 0.206*sl t f 1.43 1.03 + 0.199*sl 1.03 + 0.200*sl 1.03 + 0.200*sl e to y t plh 0.78 0.59 + 0.096*sl 0.59 + 0.094*sl 0.60 + 0.094*sl t phl 0.83 0.61 + 0.105*sl 0.63 + 0.102*sl 0.64 + 0.100*sl t r 1.30 0.89 + 0.202*sl 0.89 + 0.204*sl 0.87 + 0.206*sl t f 1.43 1.04 + 0.198*sl 1.03 + 0.200*sl 1.02 + 0.201*sl f to y t plh 0.81 0.62 + 0.095*sl 0.62 + 0.095*sl 0.63 + 0.094*sl t phl 0.82 0.61 + 0.105*sl 0.62 + 0.102*sl 0.64 + 0.100*sl t r 1.34 0.93 + 0.202*sl 0.93 + 0.204*sl 0.92 + 0.206*sl t f 1.43 1.04 + 0.198*sl 1.03 + 0.200*sl 1.03 + 0.200*sl g to y t plh 0.87 0.68 + 0.096*sl 0.68 + 0.095*sl 0.69 + 0.094*sl t phl 1.01 0.78 + 0.111*sl 0.80 + 0.106*sl 0.82 + 0.102*sl t r 1.26 0.86 + 0.200*sl 0.85 + 0.204*sl 0.84 + 0.205*sl t f 1.81 1.41 + 0.201*sl 1.41 + 0.200*sl 1.41 + 0.200*sl h to y t plh 0.90 0.71 + 0.095*sl 0.72 + 0.094*sl 0.72 + 0.094*sl t phl 1.02 0.79 + 0.111*sl 0.81 + 0.106*sl 0.83 + 0.102*sl t r 1.30 0.90 + 0.201*sl 0.89 + 0.204*sl 0.88 + 0.206*sl t f 1.81 1.41 + 0.199*sl 1.41 + 0.200*sl 1.41 + 0.200*sl i to y t plh 0.93 0.74 + 0.096*sl 0.75 + 0.094*sl 0.75 + 0.094*sl t phl 1.01 0.79 + 0.111*sl 0.81 + 0.106*sl 0.83 + 0.102*sl t r 1.34 0.94 + 0.201*sl 0.93 + 0.204*sl 0.92 + 0.206*sl t f 1.81 1.42 + 0.199*sl 1.42 + 0.199*sl 1.41 + 0.200*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-114 sec asic ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ao333d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.99 0.94 + 0.024*sl 0.95 + 0.019*sl 0.97 + 0.017*sl t phl 0.84 0.78 + 0.030*sl 0.80 + 0.025*sl 0.81 + 0.022*sl t r 0.22 0.16 + 0.031*sl 0.16 + 0.032*sl 0.15 + 0.033*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.037*sl 0.14 + 0.038*sl b to y t plh 1.05 1.00 + 0.024*sl 1.01 + 0.019*sl 1.03 + 0.017*sl t phl 0.85 0.79 + 0.030*sl 0.80 + 0.025*sl 0.82 + 0.022*sl t r 0.23 0.17 + 0.031*sl 0.17 + 0.031*sl 0.16 + 0.032*sl t f 0.22 0.14 + 0.039*sl 0.15 + 0.037*sl 0.14 + 0.038*sl c to y t plh 1.10 1.05 + 0.024*sl 1.07 + 0.019*sl 1.08 + 0.017*sl t phl 0.85 0.79 + 0.029*sl 0.80 + 0.025*sl 0.82 + 0.022*sl t r 0.23 0.17 + 0.029*sl 0.16 + 0.031*sl 0.16 + 0.033*sl t f 0.22 0.14 + 0.038*sl 0.15 + 0.037*sl 0.14 + 0.038*sl d to y t plh 1.23 1.18 + 0.024*sl 1.20 + 0.019*sl 1.21 + 0.017*sl t phl 1.02 0.97 + 0.030*sl 0.98 + 0.025*sl 1.00 + 0.022*sl t r 0.22 0.16 + 0.031*sl 0.16 + 0.031*sl 0.15 + 0.033*sl t f 0.22 0.15 + 0.039*sl 0.15 + 0.037*sl 0.15 + 0.037*sl e to y t plh 1.29 1.24 + 0.024*sl 1.26 + 0.019*sl 1.27 + 0.017*sl t phl 1.03 0.97 + 0.030*sl 0.99 + 0.025*sl 1.01 + 0.022*sl t r 0.23 0.17 + 0.029*sl 0.16 + 0.031*sl 0.15 + 0.033*sl t f 0.22 0.15 + 0.039*sl 0.15 + 0.037*sl 0.15 + 0.037*sl f to y t plh 1.35 1.30 + 0.024*sl 1.32 + 0.019*sl 1.33 + 0.017*sl t phl 1.03 0.97 + 0.030*sl 0.99 + 0.025*sl 1.01 + 0.022*sl t r 0.23 0.16 + 0.032*sl 0.17 + 0.031*sl 0.16 + 0.033*sl t f 0.22 0.15 + 0.039*sl 0.15 + 0.037*sl 0.15 + 0.038*sl g to y t plh 1.36 1.31 + 0.024*sl 1.33 + 0.019*sl 1.34 + 0.017*sl t phl 1.15 1.08 + 0.030*sl 1.10 + 0.025*sl 1.12 + 0.023*sl t r 0.22 0.16 + 0.030*sl 0.16 + 0.031*sl 0.15 + 0.033*sl t f 0.23 0.15 + 0.038*sl 0.16 + 0.037*sl 0.15 + 0.037*sl h to y t plh 1.42 1.38 + 0.023*sl 1.39 + 0.019*sl 1.40 + 0.017*sl t phl 1.15 1.09 + 0.030*sl 1.11 + 0.025*sl 1.13 + 0.023*sl t r 0.23 0.16 + 0.032*sl 0.17 + 0.031*sl 0.15 + 0.033*sl t f 0.23 0.15 + 0.039*sl 0.16 + 0.037*sl 0.16 + 0.037*sl i to y t plh 1.48 1.43 + 0.024*sl 1.45 + 0.019*sl 1.46 + 0.017*sl t phl 1.15 1.09 + 0.030*sl 1.11 + 0.025*sl 1.13 + 0.023*sl t r 0.23 0.17 + 0.031*sl 0.17 + 0.031*sl 0.15 + 0.033*sl t f 0.23 0.15 + 0.038*sl 0.15 + 0.037*sl 0.15 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-115 STD80/stdm80 oa21/oa21d2 2-or into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 oa21 oa21d2 oa21 oa21d2 abcabc 0.8 0.4 0.9 1.6 0.9 1.9 1.3 2.3 stdm80 oa21 oa21d2 oa21 oa21d2 abcabc 1.1 1.0 1.0 2.0 2.1 2.1 1.3 2.3 y c a b truth table abcy 1x10 x110 00x1 xx01
STD80/stdm80 3-116 sec asic oa21/oa21d2 2-or into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 oa21 STD80 oa21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.13 + 0.041*sl t phl 0.32 0.21 + 0.053*sl 0.21 + 0.054*sl 0.20 + 0.055*sl t r 0.39 0.23 + 0.080*sl 0.21 + 0.089*sl 0.15 + 0.095*sl t f 0.48 0.29 + 0.095*sl 0.27 + 0.105*sl 0.21 + 0.111*sl b to y t plh 0.22 0.12 + 0.050*sl 0.14 + 0.041*sl 0.13 + 0.041*sl t phl 0.27 0.16 + 0.057*sl 0.16 + 0.054*sl 0.15 + 0.055*sl t r 0.40 0.25 + 0.076*sl 0.23 + 0.087*sl 0.16 + 0.095*sl t f 0.39 0.20 + 0.095*sl 0.18 + 0.105*sl 0.13 + 0.111*sl c to y t plh 0.18 0.11 + 0.032*sl 0.13 + 0.025*sl 0.14 + 0.024*sl t phl 0.31 0.21 + 0.054*sl 0.20 + 0.055*sl 0.20 + 0.055*sl t r 0.36 0.29 + 0.034*sl 0.27 + 0.044*sl 0.19 + 0.052*sl t f 0.46 0.25 + 0.102*sl 0.24 + 0.107*sl 0.21 + 0.111*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.17 0.12 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl t phl 0.26 0.20 + 0.028*sl 0.21 + 0.026*sl 0.20 + 0.027*sl t r 0.31 0.24 + 0.035*sl 0.23 + 0.042*sl 0.18 + 0.047*sl t f 0.38 0.29 + 0.045*sl 0.28 + 0.049*sl 0.23 + 0.054*sl b to y t plh 0.17 0.11 + 0.029*sl 0.13 + 0.022*sl 0.14 + 0.021*sl t phl 0.21 0.15 + 0.030*sl 0.15 + 0.027*sl 0.15 + 0.027*sl t r 0.33 0.26 + 0.034*sl 0.25 + 0.041*sl 0.18 + 0.047*sl t f 0.30 0.21 + 0.044*sl 0.20 + 0.049*sl 0.14 + 0.054*sl c to y t plh 0.15 0.11 + 0.018*sl 0.12 + 0.014*sl 0.14 + 0.012*sl t phl 0.25 0.19 + 0.028*sl 0.20 + 0.026*sl 0.19 + 0.027*sl t r 0.32 0.29 + 0.016*sl 0.28 + 0.020*sl 0.22 + 0.025*sl t f 0.35 0.25 + 0.049*sl 0.25 + 0.051*sl 0.22 + 0.054*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-117 STD80/stdm80 oa21/oa21d2 2-or into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 oa21 stdm80 oa21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.19 + 0.065*sl 0.19 + 0.063*sl 0.19 + 0.063*sl t phl 0.40 0.26 + 0.073*sl 0.26 + 0.072*sl 0.26 + 0.071*sl t r 0.52 0.25 + 0.131*sl 0.24 + 0.136*sl 0.22 + 0.138*sl t f 0.58 0.31 + 0.135*sl 0.29 + 0.140*sl 0.27 + 0.142*sl b to y t plh 0.29 0.17 + 0.064*sl 0.17 + 0.063*sl 0.17 + 0.063*sl t phl 0.34 0.19 + 0.072*sl 0.19 + 0.072*sl 0.20 + 0.071*sl t r 0.52 0.26 + 0.129*sl 0.25 + 0.135*sl 0.22 + 0.138*sl t f 0.48 0.21 + 0.134*sl 0.19 + 0.140*sl 0.17 + 0.143*sl c to y t plh 0.23 0.16 + 0.036*sl 0.17 + 0.033*sl 0.16 + 0.033*sl t phl 0.41 0.27 + 0.074*sl 0.27 + 0.073*sl 0.27 + 0.072*sl t r 0.33 0.21 + 0.061*sl 0.20 + 0.067*sl 0.17 + 0.070*sl t f 0.57 0.29 + 0.139*sl 0.29 + 0.141*sl 0.28 + 0.142*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.18 + 0.034*sl 0.19 + 0.032*sl 0.19 + 0.032*sl t phl 0.32 0.25 + 0.036*sl 0.25 + 0.035*sl 0.25 + 0.035*sl t r 0.39 0.26 + 0.064*sl 0.25 + 0.066*sl 0.24 + 0.068*sl t f 0.43 0.31 + 0.064*sl 0.30 + 0.066*sl 0.29 + 0.068*sl b to y t plh 0.23 0.16 + 0.035*sl 0.17 + 0.031*sl 0.17 + 0.031*sl t phl 0.25 0.18 + 0.036*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t r 0.39 0.27 + 0.060*sl 0.26 + 0.065*sl 0.24 + 0.067*sl t f 0.33 0.20 + 0.064*sl 0.20 + 0.066*sl 0.19 + 0.068*sl c to y t plh 0.19 0.15 + 0.021*sl 0.16 + 0.017*sl 0.16 + 0.017*sl t phl 0.32 0.25 + 0.036*sl 0.25 + 0.035*sl 0.25 + 0.035*sl t r 0.27 0.21 + 0.028*sl 0.21 + 0.031*sl 0.19 + 0.033*sl t f 0.42 0.29 + 0.066*sl 0.28 + 0.067*sl 0.28 + 0.068*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-118 sec asic oa211/oa211d2 2-or into 3-nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 oa211 oa211d2 oa211 oa211d2 abcdabcd 0.9 0.5 1.0 1.0 1.6 0.9 1.9 1.8 1.7 3.0 stdm80 oa211 oa211d2 oa211 oa211d2 abcdabcd 1.1 1.0 1.0 1.0 2.0 2.2 2.1 2.2 1.7 3.0 y c a b d truth table abcdy 1x110 x1110 00xx1 xx0x1 xxx01
sec asic 3-119 STD80/stdm80 oa211/oa211d2 2-or into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 oa211 STD80 oa211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.14 + 0.045*sl 0.15 + 0.041*sl 0.15 + 0.041*sl t phl 0.44 0.30 + 0.071*sl 0.29 + 0.072*sl 0.29 + 0.073*sl t r 0.44 0.28 + 0.081*sl 0.26 + 0.089*sl 0.21 + 0.095*sl t f 0.71 0.43 + 0.141*sl 0.41 + 0.149*sl 0.38 + 0.152*sl b to y t plh 0.24 0.14 + 0.049*sl 0.16 + 0.041*sl 0.15 + 0.041*sl t phl 0.37 0.23 + 0.070*sl 0.23 + 0.072*sl 0.22 + 0.073*sl t r 0.46 0.30 + 0.079*sl 0.28 + 0.088*sl 0.21 + 0.095*sl t f 0.59 0.31 + 0.141*sl 0.29 + 0.149*sl 0.26 + 0.152*sl c to y t plh 0.19 0.13 + 0.032*sl 0.14 + 0.025*sl 0.15 + 0.024*sl t phl 0.45 0.31 + 0.072*sl 0.31 + 0.073*sl 0.31 + 0.073*sl t r 0.38 0.30 + 0.039*sl 0.29 + 0.044*sl 0.22 + 0.052*sl t f 0.70 0.41 + 0.146*sl 0.40 + 0.150*sl 0.38 + 0.152*sl d to y t plh 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.16 + 0.024*sl t phl 0.44 0.29 + 0.072*sl 0.29 + 0.073*sl 0.29 + 0.073*sl t r 0.40 0.32 + 0.036*sl 0.31 + 0.044*sl 0.23 + 0.052*sl t f 0.70 0.40 + 0.148*sl 0.40 + 0.150*sl 0.38 + 0.152*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.14 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.021*sl t phl 0.36 0.29 + 0.034*sl 0.29 + 0.035*sl 0.28 + 0.036*sl t r 0.36 0.28 + 0.039*sl 0.27 + 0.043*sl 0.23 + 0.047*sl t f 0.56 0.42 + 0.069*sl 0.42 + 0.071*sl 0.38 + 0.075*sl b to y t plh 0.19 0.13 + 0.027*sl 0.15 + 0.022*sl 0.16 + 0.021*sl t phl 0.30 0.23 + 0.034*sl 0.23 + 0.035*sl 0.22 + 0.036*sl t r 0.38 0.30 + 0.038*sl 0.29 + 0.041*sl 0.24 + 0.047*sl t f 0.44 0.31 + 0.068*sl 0.30 + 0.072*sl 0.27 + 0.075*sl c to y t plh 0.16 0.12 + 0.018*sl 0.13 + 0.014*sl 0.15 + 0.012*sl t phl 0.37 0.30 + 0.036*sl 0.30 + 0.035*sl 0.30 + 0.036*sl t r 0.34 0.31 + 0.018*sl 0.30 + 0.020*sl 0.25 + 0.026*sl t f 0.54 0.40 + 0.072*sl 0.40 + 0.073*sl 0.38 + 0.075*sl d to y t plh 0.17 0.13 + 0.017*sl 0.14 + 0.014*sl 0.16 + 0.012*sl t phl 0.36 0.29 + 0.035*sl 0.29 + 0.036*sl 0.28 + 0.036*sl t r 0.36 0.32 + 0.018*sl 0.32 + 0.020*sl 0.27 + 0.025*sl t f 0.54 0.39 + 0.072*sl 0.39 + 0.074*sl 0.38 + 0.075*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-120 sec asic oa211/oa211d2 2-or into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) stdm80 oa211 stdm80 oa211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.36 0.23 + 0.063*sl 0.23 + 0.063*sl 0.23 + 0.063*sl t phl 0.59 0.39 + 0.100*sl 0.39 + 0.099*sl 0.40 + 0.098*sl t r 0.60 0.34 + 0.132*sl 0.33 + 0.136*sl 0.31 + 0.139*sl t f 0.93 0.53 + 0.198*sl 0.53 + 0.201*sl 0.53 + 0.201*sl b to y t plh 0.33 0.20 + 0.063*sl 0.20 + 0.063*sl 0.21 + 0.063*sl t phl 0.49 0.29 + 0.099*sl 0.29 + 0.099*sl 0.30 + 0.098*sl t r 0.61 0.35 + 0.131*sl 0.33 + 0.136*sl 0.31 + 0.139*sl t f 0.79 0.39 + 0.198*sl 0.38 + 0.201*sl 0.38 + 0.202*sl c to y t plh 0.25 0.18 + 0.034*sl 0.18 + 0.033*sl 0.18 + 0.033*sl t phl 0.63 0.42 + 0.101*sl 0.43 + 0.100*sl 0.44 + 0.099*sl t r 0.37 0.25 + 0.062*sl 0.23 + 0.068*sl 0.22 + 0.070*sl t f 0.93 0.53 + 0.198*sl 0.53 + 0.201*sl 0.53 + 0.201*sl d to y t plh 0.26 0.19 + 0.034*sl 0.19 + 0.033*sl 0.19 + 0.033*sl t phl 0.62 0.42 + 0.101*sl 0.43 + 0.100*sl 0.43 + 0.099*sl t r 0.39 0.27 + 0.062*sl 0.25 + 0.067*sl 0.23 + 0.070*sl t f 0.93 0.53 + 0.199*sl 0.53 + 0.201*sl 0.53 + 0.201*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.22 + 0.033*sl 0.23 + 0.032*sl 0.23 + 0.032*sl t phl 0.48 0.38 + 0.049*sl 0.38 + 0.048*sl 0.38 + 0.048*sl t r 0.47 0.34 + 0.066*sl 0.34 + 0.067*sl 0.32 + 0.068*sl t f 0.72 0.53 + 0.096*sl 0.52 + 0.098*sl 0.51 + 0.099*sl b to y t plh 0.27 0.20 + 0.032*sl 0.20 + 0.032*sl 0.21 + 0.031*sl t phl 0.38 0.29 + 0.049*sl 0.29 + 0.048*sl 0.29 + 0.049*sl t r 0.48 0.35 + 0.064*sl 0.34 + 0.066*sl 0.33 + 0.068*sl t f 0.58 0.39 + 0.096*sl 0.38 + 0.098*sl 0.37 + 0.099*sl c to y t plh 0.21 0.17 + 0.020*sl 0.18 + 0.017*sl 0.18 + 0.017*sl t phl 0.51 0.41 + 0.050*sl 0.41 + 0.049*sl 0.42 + 0.049*sl t r 0.31 0.25 + 0.029*sl 0.24 + 0.033*sl 0.24 + 0.033*sl t f 0.72 0.52 + 0.097*sl 0.52 + 0.098*sl 0.51 + 0.099*sl d to y t plh 0.22 0.18 + 0.019*sl 0.19 + 0.017*sl 0.19 + 0.017*sl t phl 0.51 0.41 + 0.050*sl 0.41 + 0.049*sl 0.41 + 0.049*sl t r 0.33 0.27 + 0.030*sl 0.26 + 0.032*sl 0.25 + 0.033*sl t f 0.71 0.52 + 0.097*sl 0.52 + 0.098*sl 0.51 + 0.099*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-121 STD80/stdm80 oa22/oa22d2 two 2-ors into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 oa22 oa22d2 oa22 oa22d2 abcdabcd 1.1 0.5 0.5 0.9 1.8 1.1 1.2 1.9 1.7 3.0 stdm80 oa22 oa22d2 oa22 oa22d2 abcdabcd 1.1 1.0 1.0 1.0 2.0 2.1 2.2 2.2 1.7 3.0 c d y a b truth table abcdy 00xx1 xx001 1xx10 x1x10 1x1x0 x11x0
STD80/stdm80 3-122 sec asic oa22/oa22d2 two 2-ors into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 oa22 STD80 oa22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.14 + 0.045*sl 0.15 + 0.042*sl 0.15 + 0.041*sl t phl 0.37 0.27 + 0.054*sl 0.27 + 0.055*sl 0.26 + 0.055*sl t r 0.49 0.33 + 0.078*sl 0.31 + 0.089*sl 0.25 + 0.095*sl t f 0.55 0.35 + 0.102*sl 0.34 + 0.106*sl 0.30 + 0.111*sl b to y t plh 0.24 0.14 + 0.048*sl 0.16 + 0.041*sl 0.16 + 0.041*sl t phl 0.33 0.22 + 0.055*sl 0.22 + 0.055*sl 0.21 + 0.055*sl t r 0.50 0.35 + 0.076*sl 0.32 + 0.087*sl 0.25 + 0.095*sl t f 0.46 0.26 + 0.102*sl 0.25 + 0.107*sl 0.21 + 0.111*sl c to y t plh 0.27 0.18 + 0.044*sl 0.19 + 0.041*sl 0.18 + 0.041*sl t phl 0.32 0.21 + 0.056*sl 0.21 + 0.055*sl 0.22 + 0.055*sl t r 0.55 0.40 + 0.076*sl 0.37 + 0.087*sl 0.30 + 0.095*sl t f 0.45 0.25 + 0.104*sl 0.24 + 0.108*sl 0.21 + 0.111*sl d to y t plh 0.26 0.18 + 0.043*sl 0.18 + 0.041*sl 0.18 + 0.041*sl t phl 0.37 0.26 + 0.055*sl 0.26 + 0.055*sl 0.26 + 0.055*sl t r 0.53 0.37 + 0.081*sl 0.36 + 0.088*sl 0.30 + 0.095*sl t f 0.54 0.34 + 0.103*sl 0.33 + 0.108*sl 0.30 + 0.111*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.14 + 0.024*sl 0.15 + 0.021*sl 0.15 + 0.021*sl t phl 0.31 0.26 + 0.026*sl 0.26 + 0.026*sl 0.26 + 0.027*sl t r 0.41 0.34 + 0.037*sl 0.32 + 0.042*sl 0.27 + 0.047*sl t f 0.45 0.35 + 0.048*sl 0.35 + 0.051*sl 0.31 + 0.054*sl b to y t plh 0.19 0.14 + 0.026*sl 0.15 + 0.022*sl 0.16 + 0.021*sl t phl 0.27 0.21 + 0.028*sl 0.22 + 0.027*sl 0.21 + 0.027*sl t r 0.43 0.35 + 0.037*sl 0.34 + 0.041*sl 0.28 + 0.047*sl t f 0.36 0.27 + 0.048*sl 0.26 + 0.051*sl 0.23 + 0.054*sl c to y t plh 0.23 0.18 + 0.023*sl 0.19 + 0.021*sl 0.19 + 0.021*sl t phl 0.26 0.21 + 0.028*sl 0.21 + 0.027*sl 0.21 + 0.027*sl t r 0.47 0.40 + 0.036*sl 0.39 + 0.041*sl 0.33 + 0.047*sl t f 0.35 0.25 + 0.050*sl 0.25 + 0.052*sl 0.22 + 0.054*sl d to y t plh 0.22 0.18 + 0.023*sl 0.18 + 0.021*sl 0.18 + 0.021*sl t phl 0.31 0.26 + 0.027*sl 0.26 + 0.027*sl 0.26 + 0.027*sl t r 0.46 0.38 + 0.038*sl 0.37 + 0.042*sl 0.32 + 0.047*sl t f 0.44 0.34 + 0.051*sl 0.34 + 0.051*sl 0.31 + 0.054*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-123 STD80/stdm80 oa22/oa22d2 two 2-ors into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 oa22 stdm80 oa22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.33 0.20 + 0.065*sl 0.21 + 0.064*sl 0.21 + 0.064*sl t phl 0.48 0.33 + 0.073*sl 0.34 + 0.072*sl 0.34 + 0.072*sl t r 0.66 0.40 + 0.130*sl 0.38 + 0.135*sl 0.36 + 0.138*sl t f 0.67 0.40 + 0.137*sl 0.39 + 0.141*sl 0.38 + 0.142*sl b to y t plh 0.31 0.18 + 0.064*sl 0.18 + 0.064*sl 0.18 + 0.064*sl t phl 0.41 0.26 + 0.074*sl 0.27 + 0.072*sl 0.27 + 0.072*sl t r 0.66 0.41 + 0.128*sl 0.39 + 0.134*sl 0.36 + 0.138*sl t f 0.57 0.30 + 0.137*sl 0.29 + 0.141*sl 0.27 + 0.143*sl c to y t plh 0.36 0.23 + 0.065*sl 0.23 + 0.064*sl 0.23 + 0.064*sl t phl 0.43 0.29 + 0.075*sl 0.29 + 0.073*sl 0.30 + 0.072*sl t r 0.73 0.47 + 0.128*sl 0.45 + 0.135*sl 0.42 + 0.138*sl t f 0.57 0.29 + 0.139*sl 0.29 + 0.141*sl 0.28 + 0.142*sl d to y t plh 0.38 0.25 + 0.066*sl 0.25 + 0.064*sl 0.26 + 0.064*sl t phl 0.50 0.35 + 0.074*sl 0.36 + 0.072*sl 0.36 + 0.072*sl t r 0.72 0.46 + 0.130*sl 0.45 + 0.136*sl 0.43 + 0.138*sl t f 0.67 0.39 + 0.140*sl 0.38 + 0.142*sl 0.38 + 0.142*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.20 + 0.033*sl 0.21 + 0.032*sl 0.21 + 0.032*sl t phl 0.39 0.32 + 0.036*sl 0.32 + 0.035*sl 0.33 + 0.035*sl t r 0.53 0.41 + 0.064*sl 0.40 + 0.066*sl 0.39 + 0.067*sl t f 0.53 0.39 + 0.066*sl 0.39 + 0.068*sl 0.38 + 0.069*sl b to y t plh 0.25 0.18 + 0.033*sl 0.18 + 0.032*sl 0.18 + 0.032*sl t phl 0.33 0.26 + 0.036*sl 0.26 + 0.036*sl 0.26 + 0.035*sl t r 0.54 0.42 + 0.060*sl 0.41 + 0.065*sl 0.39 + 0.067*sl t f 0.43 0.30 + 0.067*sl 0.29 + 0.067*sl 0.29 + 0.068*sl c to y t plh 0.29 0.23 + 0.032*sl 0.23 + 0.032*sl 0.23 + 0.032*sl t phl 0.35 0.27 + 0.036*sl 0.27 + 0.036*sl 0.28 + 0.035*sl t r 0.60 0.48 + 0.061*sl 0.47 + 0.065*sl 0.45 + 0.067*sl t f 0.42 0.29 + 0.067*sl 0.29 + 0.068*sl 0.28 + 0.068*sl d to y t plh 0.32 0.25 + 0.033*sl 0.25 + 0.033*sl 0.26 + 0.032*sl t phl 0.42 0.34 + 0.037*sl 0.35 + 0.036*sl 0.35 + 0.035*sl t r 0.59 0.47 + 0.064*sl 0.46 + 0.066*sl 0.45 + 0.068*sl t f 0.52 0.38 + 0.068*sl 0.38 + 0.068*sl 0.38 + 0.068*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-124 sec asic oa22a/oa22d2a 2-or and 2-nand into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 oa22a oa22d2a oa22a oa22d2a abcdabcd 0.8 0.8 0.7 0.7 1.6 1.6 0.8 0.8 2.0 3.0 stdm80 oa22a oa22d2a oa22a oa22d2a abcdabcd 1.1 1.0 0.7 0.7 2.1 2.0 0.8 0.8 2.0 3.0 c d y a b truth table abcdy 00xx1 xx111 1x0x0 1xx00 x10x0 x1x00
sec asic 3-125 STD80/stdm80 oa22a/oa22d2a 2-or and 2-nand into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 oa22a STD80 oa22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.13 + 0.041*sl t phl 0.32 0.21 + 0.054*sl 0.21 + 0.054*sl 0.20 + 0.055*sl t r 0.39 0.23 + 0.080*sl 0.21 + 0.089*sl 0.15 + 0.095*sl t f 0.48 0.29 + 0.096*sl 0.27 + 0.105*sl 0.21 + 0.111*sl b to y t plh 0.22 0.12 + 0.050*sl 0.14 + 0.041*sl 0.13 + 0.041*sl t phl 0.27 0.16 + 0.058*sl 0.16 + 0.054*sl 0.15 + 0.055*sl t r 0.40 0.25 + 0.076*sl 0.23 + 0.087*sl 0.16 + 0.095*sl t f 0.39 0.20 + 0.095*sl 0.18 + 0.105*sl 0.13 + 0.111*sl c to y t plh 0.29 0.24 + 0.027*sl 0.24 + 0.025*sl 0.25 + 0.024*sl t phl 0.47 0.36 + 0.056*sl 0.36 + 0.056*sl 0.36 + 0.055*sl t r 0.29 0.21 + 0.044*sl 0.20 + 0.048*sl 0.16 + 0.052*sl t f 0.44 0.22 + 0.109*sl 0.22 + 0.110*sl 0.21 + 0.111*sl d to y t plh 0.31 0.25 + 0.028*sl 0.26 + 0.025*sl 0.27 + 0.024*sl t phl 0.45 0.33 + 0.057*sl 0.34 + 0.056*sl 0.34 + 0.055*sl t r 0.29 0.21 + 0.043*sl 0.20 + 0.048*sl 0.16 + 0.052*sl t f 0.44 0.22 + 0.108*sl 0.22 + 0.110*sl 0.21 + 0.111*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.17 0.11 + 0.028*sl 0.13 + 0.022*sl 0.14 + 0.021*sl t phl 0.21 0.15 + 0.031*sl 0.16 + 0.027*sl 0.16 + 0.027*sl t r 0.33 0.26 + 0.034*sl 0.25 + 0.041*sl 0.19 + 0.047*sl t f 0.30 0.21 + 0.044*sl 0.20 + 0.049*sl 0.15 + 0.054*sl b to y t plh 0.17 0.12 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl t phl 0.26 0.20 + 0.028*sl 0.21 + 0.026*sl 0.20 + 0.027*sl t r 0.31 0.24 + 0.035*sl 0.23 + 0.042*sl 0.18 + 0.047*sl t f 0.38 0.30 + 0.044*sl 0.29 + 0.049*sl 0.23 + 0.054*sl c to y t plh 0.33 0.30 + 0.016*sl 0.30 + 0.014*sl 0.32 + 0.012*sl t phl 0.46 0.40 + 0.028*sl 0.40 + 0.027*sl 0.41 + 0.027*sl t r 0.28 0.24 + 0.020*sl 0.24 + 0.022*sl 0.20 + 0.026*sl t f 0.33 0.23 + 0.053*sl 0.23 + 0.053*sl 0.21 + 0.054*sl d to y t plh 0.35 0.32 + 0.015*sl 0.32 + 0.014*sl 0.34 + 0.012*sl t phl 0.44 0.39 + 0.028*sl 0.39 + 0.027*sl 0.39 + 0.027*sl t r 0.29 0.23 + 0.028*sl 0.25 + 0.021*sl 0.20 + 0.026*sl t f 0.33 0.23 + 0.052*sl 0.22 + 0.053*sl 0.21 + 0.054*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-126 sec asic oa22a/oa22d2a 2-or and 2-nand into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 oa22a stdm80 oa22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.19 + 0.064*sl 0.19 + 0.063*sl 0.19 + 0.063*sl t phl 0.40 0.26 + 0.073*sl 0.26 + 0.072*sl 0.26 + 0.071*sl t r 0.52 0.25 + 0.131*sl 0.24 + 0.136*sl 0.22 + 0.138*sl t f 0.58 0.31 + 0.135*sl 0.29 + 0.140*sl 0.28 + 0.142*sl b to y t plh 0.29 0.17 + 0.064*sl 0.17 + 0.063*sl 0.17 + 0.063*sl t phl 0.34 0.19 + 0.072*sl 0.19 + 0.072*sl 0.20 + 0.071*sl t r 0.52 0.26 + 0.129*sl 0.25 + 0.135*sl 0.22 + 0.138*sl t f 0.48 0.21 + 0.135*sl 0.19 + 0.140*sl 0.17 + 0.143*sl c to y t plh 0.40 0.32 + 0.037*sl 0.33 + 0.034*sl 0.34 + 0.034*sl t phl 0.63 0.48 + 0.075*sl 0.48 + 0.073*sl 0.49 + 0.072*sl t r 0.32 0.19 + 0.068*sl 0.18 + 0.070*sl 0.17 + 0.071*sl t f 0.57 0.29 + 0.140*sl 0.28 + 0.142*sl 0.28 + 0.142*sl d to y t plh 0.41 0.33 + 0.038*sl 0.34 + 0.035*sl 0.35 + 0.034*sl t phl 0.60 0.45 + 0.075*sl 0.46 + 0.073*sl 0.47 + 0.072*sl t r 0.40 0.27 + 0.066*sl 0.26 + 0.069*sl 0.24 + 0.071*sl t f 0.57 0.29 + 0.141*sl 0.28 + 0.142*sl 0.28 + 0.142*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.16 + 0.035*sl 0.17 + 0.032*sl 0.17 + 0.031*sl t phl 0.26 0.18 + 0.036*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t r 0.39 0.27 + 0.061*sl 0.26 + 0.065*sl 0.24 + 0.068*sl t f 0.34 0.21 + 0.063*sl 0.20 + 0.066*sl 0.19 + 0.068*sl b to y t plh 0.25 0.18 + 0.034*sl 0.19 + 0.032*sl 0.19 + 0.032*sl t phl 0.32 0.25 + 0.036*sl 0.25 + 0.035*sl 0.25 + 0.035*sl t r 0.39 0.26 + 0.064*sl 0.25 + 0.066*sl 0.24 + 0.068*sl t f 0.44 0.31 + 0.064*sl 0.30 + 0.066*sl 0.29 + 0.068*sl c to y t plh 0.45 0.40 + 0.022*sl 0.41 + 0.019*sl 0.42 + 0.018*sl t phl 0.61 0.54 + 0.037*sl 0.54 + 0.036*sl 0.55 + 0.035*sl t r 0.29 0.22 + 0.034*sl 0.22 + 0.034*sl 0.22 + 0.034*sl t f 0.43 0.29 + 0.068*sl 0.29 + 0.067*sl 0.29 + 0.068*sl d to y t plh 0.46 0.41 + 0.022*sl 0.42 + 0.019*sl 0.43 + 0.018*sl t phl 0.59 0.51 + 0.037*sl 0.52 + 0.036*sl 0.53 + 0.035*sl t r 0.29 0.22 + 0.033*sl 0.22 + 0.034*sl 0.22 + 0.034*sl t f 0.43 0.29 + 0.068*sl 0.29 + 0.068*sl 0.29 + 0.068*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-127 STD80/stdm80 oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 oa2222 oa2222d2 oa2222 oa2222 d2 abcdefghabcdefgh 0.6 0.4 0.5 0.7 0.6 0.7 0.8 0.8 0.6 0.4 0.5 0.7 0.6 0.6 0.8 0.8 4.7 5.0 stdm80 oa2222 oa2222d2 oa2222 oa2222 d2 abcdefghabcdefgh 0.7 0.7 0.8 0.8 0.7 0.7 0.8 0.8 0.7 0.7 0.8 0.8 0.7 0.7 0.8 0.8 4.7 5.0 e f y c d g h a b truth table abcdefghy 00xxxxxx1 xx00xxxx1 xxxx00xx1 xxxxxx001 other states 0
STD80/stdm80 3-128 sec asic oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 oa2222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.50 0.45 + 0.026*sl 0.45 + 0.024*sl 0.45 + 0.024*sl t phl 0.59 0.50 + 0.043*sl 0.51 + 0.038*sl 0.52 + 0.037*sl t r 0.19 0.11 + 0.042*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl b to y t plh 0.50 0.45 + 0.026*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.55 0.46 + 0.043*sl 0.47 + 0.038*sl 0.48 + 0.037*sl t r 0.19 0.11 + 0.044*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.063*sl 0.11 + 0.067*sl 0.09 + 0.069*sl c to y t plh 0.45 0.40 + 0.026*sl 0.40 + 0.024*sl 0.40 + 0.024*sl t phl 0.55 0.46 + 0.043*sl 0.47 + 0.038*sl 0.48 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl d to y t plh 0.44 0.39 + 0.026*sl 0.40 + 0.024*sl 0.40 + 0.024*sl t phl 0.59 0.50 + 0.043*sl 0.51 + 0.038*sl 0.53 + 0.037*sl t r 0.19 0.10 + 0.043*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl e to y t plh 0.53 0.48 + 0.027*sl 0.49 + 0.024*sl 0.49 + 0.024*sl t phl 0.60 0.52 + 0.043*sl 0.53 + 0.038*sl 0.54 + 0.037*sl t r 0.20 0.12 + 0.042*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.063*sl 0.12 + 0.066*sl 0.09 + 0.069*sl f to y t plh 0.54 0.49 + 0.026*sl 0.49 + 0.024*sl 0.49 + 0.024*sl t phl 0.57 0.48 + 0.043*sl 0.49 + 0.038*sl 0.50 + 0.037*sl t r 0.20 0.11 + 0.043*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl g to y t plh 0.48 0.43 + 0.027*sl 0.43 + 0.024*sl 0.43 + 0.024*sl t phl 0.57 0.48 + 0.043*sl 0.49 + 0.038*sl 0.50 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl h to y t plh 0.48 0.42 + 0.026*sl 0.43 + 0.024*sl 0.43 + 0.024*sl t phl 0.61 0.52 + 0.042*sl 0.53 + 0.038*sl 0.54 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-129 STD80/stdm80 oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 oa2222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.52 0.48 + 0.016*sl 0.49 + 0.013*sl 0.50 + 0.012*sl t phl 0.61 0.56 + 0.025*sl 0.57 + 0.021*sl 0.60 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.12 + 0.034*sl b to y t plh 0.52 0.49 + 0.017*sl 0.50 + 0.013*sl 0.51 + 0.012*sl t phl 0.57 0.52 + 0.025*sl 0.53 + 0.021*sl 0.56 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.21 0.15 + 0.030*sl 0.15 + 0.031*sl 0.12 + 0.034*sl c to y t plh 0.46 0.43 + 0.018*sl 0.44 + 0.013*sl 0.45 + 0.012*sl t phl 0.57 0.52 + 0.025*sl 0.53 + 0.021*sl 0.56 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.21 0.14 + 0.032*sl 0.14 + 0.031*sl 0.12 + 0.034*sl d to y t plh 0.46 0.43 + 0.017*sl 0.43 + 0.013*sl 0.45 + 0.012*sl t phl 0.61 0.57 + 0.024*sl 0.57 + 0.021*sl 0.60 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.08 + 0.026*sl t f 0.21 0.14 + 0.032*sl 0.15 + 0.031*sl 0.12 + 0.034*sl e to y t plh 0.55 0.52 + 0.018*sl 0.53 + 0.013*sl 0.54 + 0.012*sl t phl 0.63 0.58 + 0.025*sl 0.59 + 0.021*sl 0.62 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.21 0.15 + 0.032*sl 0.15 + 0.031*sl 0.12 + 0.034*sl f to y t plh 0.56 0.52 + 0.017*sl 0.53 + 0.013*sl 0.54 + 0.012*sl t phl 0.60 0.55 + 0.025*sl 0.56 + 0.021*sl 0.58 + 0.018*sl t r 0.16 0.12 + 0.019*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.21 0.15 + 0.029*sl 0.14 + 0.031*sl 0.12 + 0.034*sl g to y t plh 0.50 0.46 + 0.017*sl 0.47 + 0.013*sl 0.48 + 0.012*sl t phl 0.60 0.55 + 0.025*sl 0.56 + 0.021*sl 0.58 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.21 0.14 + 0.032*sl 0.15 + 0.031*sl 0.12 + 0.034*sl h to y t plh 0.49 0.46 + 0.017*sl 0.47 + 0.013*sl 0.48 + 0.012*sl t phl 0.63 0.58 + 0.025*sl 0.59 + 0.021*sl 0.62 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.21 0.14 + 0.033*sl 0.15 + 0.031*sl 0.12 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-130 sec asic oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 oa2222 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.73 0.66 + 0.036*sl 0.67 + 0.034*sl 0.67 + 0.033*sl t phl 0.83 0.72 + 0.055*sl 0.74 + 0.048*sl 0.76 + 0.045*sl t r 0.27 0.14 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.33 0.16 + 0.082*sl 0.17 + 0.080*sl 0.16 + 0.081*sl b to y t plh 0.71 0.64 + 0.036*sl 0.64 + 0.034*sl 0.65 + 0.033*sl t phl 0.78 0.67 + 0.055*sl 0.69 + 0.048*sl 0.71 + 0.045*sl t r 0.27 0.14 + 0.066*sl 0.12 + 0.069*sl 0.11 + 0.072*sl t f 0.33 0.16 + 0.081*sl 0.17 + 0.080*sl 0.16 + 0.081*sl c to y t plh 0.62 0.54 + 0.036*sl 0.55 + 0.034*sl 0.55 + 0.033*sl t phl 0.76 0.65 + 0.055*sl 0.67 + 0.048*sl 0.69 + 0.045*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.33 0.16 + 0.082*sl 0.17 + 0.080*sl 0.16 + 0.081*sl d to y t plh 0.64 0.57 + 0.036*sl 0.57 + 0.034*sl 0.58 + 0.033*sl t phl 0.81 0.70 + 0.055*sl 0.72 + 0.048*sl 0.74 + 0.045*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.33 0.17 + 0.081*sl 0.17 + 0.080*sl 0.16 + 0.081*sl e to y t plh 0.78 0.71 + 0.037*sl 0.72 + 0.034*sl 0.72 + 0.033*sl t phl 0.87 0.76 + 0.055*sl 0.78 + 0.048*sl 0.80 + 0.045*sl t r 0.27 0.14 + 0.065*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.33 0.16 + 0.082*sl 0.17 + 0.080*sl 0.16 + 0.081*sl f to y t plh 0.76 0.69 + 0.037*sl 0.70 + 0.034*sl 0.70 + 0.033*sl t phl 0.82 0.71 + 0.055*sl 0.73 + 0.048*sl 0.75 + 0.045*sl t r 0.27 0.14 + 0.065*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.33 0.16 + 0.082*sl 0.17 + 0.080*sl 0.16 + 0.081*sl g to y t plh 0.66 0.59 + 0.037*sl 0.60 + 0.034*sl 0.60 + 0.033*sl t phl 0.80 0.69 + 0.055*sl 0.71 + 0.048*sl 0.73 + 0.045*sl t r 0.27 0.14 + 0.065*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.33 0.16 + 0.081*sl 0.17 + 0.080*sl 0.16 + 0.081*sl h to y t plh 0.69 0.61 + 0.036*sl 0.62 + 0.034*sl 0.62 + 0.033*sl t phl 0.85 0.74 + 0.055*sl 0.76 + 0.048*sl 0.78 + 0.045*sl t r 0.27 0.14 + 0.065*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.33 0.16 + 0.083*sl 0.17 + 0.079*sl 0.17 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-131 STD80/stdm80 oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 oa2222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.75 0.71 + 0.023*sl 0.72 + 0.019*sl 0.73 + 0.017*sl t phl 0.88 0.81 + 0.034*sl 0.83 + 0.028*sl 0.85 + 0.025*sl t r 0.20 0.14 + 0.032*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.039*sl 0.20 + 0.038*sl b to y t plh 0.73 0.68 + 0.023*sl 0.70 + 0.019*sl 0.71 + 0.017*sl t phl 0.83 0.76 + 0.034*sl 0.78 + 0.028*sl 0.80 + 0.025*sl t r 0.20 0.13 + 0.033*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.27 0.18 + 0.042*sl 0.19 + 0.039*sl 0.20 + 0.038*sl c to y t plh 0.63 0.59 + 0.022*sl 0.60 + 0.019*sl 0.61 + 0.017*sl t phl 0.81 0.74 + 0.034*sl 0.75 + 0.028*sl 0.78 + 0.025*sl t r 0.20 0.14 + 0.031*sl 0.13 + 0.033*sl 0.13 + 0.034*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.040*sl 0.20 + 0.038*sl d to y t plh 0.66 0.61 + 0.023*sl 0.62 + 0.019*sl 0.64 + 0.017*sl t phl 0.86 0.79 + 0.034*sl 0.81 + 0.028*sl 0.83 + 0.025*sl t r 0.20 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.27 0.18 + 0.042*sl 0.19 + 0.040*sl 0.20 + 0.038*sl e to y t plh 0.80 0.76 + 0.023*sl 0.77 + 0.019*sl 0.78 + 0.017*sl t phl 0.92 0.85 + 0.034*sl 0.87 + 0.028*sl 0.89 + 0.025*sl t r 0.21 0.15 + 0.031*sl 0.14 + 0.032*sl 0.13 + 0.033*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.039*sl 0.20 + 0.038*sl f to y t plh 0.78 0.73 + 0.023*sl 0.75 + 0.019*sl 0.76 + 0.017*sl t phl 0.87 0.81 + 0.034*sl 0.82 + 0.028*sl 0.85 + 0.025*sl t r 0.21 0.14 + 0.031*sl 0.14 + 0.032*sl 0.13 + 0.033*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.039*sl 0.20 + 0.038*sl g to y t plh 0.68 0.64 + 0.023*sl 0.65 + 0.019*sl 0.66 + 0.017*sl t phl 0.85 0.78 + 0.034*sl 0.80 + 0.028*sl 0.82 + 0.025*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.27 0.18 + 0.042*sl 0.19 + 0.039*sl 0.20 + 0.038*sl h to y t plh 0.71 0.66 + 0.023*sl 0.67 + 0.019*sl 0.68 + 0.017*sl t phl 0.90 0.83 + 0.033*sl 0.85 + 0.028*sl 0.87 + 0.025*sl t r 0.20 0.14 + 0.031*sl 0.14 + 0.033*sl 0.13 + 0.033*sl t f 0.27 0.18 + 0.043*sl 0.20 + 0.039*sl 0.20 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-132 sec asic dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 dl1d2 STD80 dl1d4 input load (sl) STD80 dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4 aaaaaaaaaaaa 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.7 0.6 0.6 0.6 stdm80 dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4 aaaaaaaaaaaa 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 gate count STD80/stdm80 dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4 3.7 4.3 4.3 5.0 4.7 5.3 5.3 6.0 5.7 6.3 7.3 8.0 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.87 0.84 + 0.016*sl 0.85 + 0.013*sl 0.86 + 0.012*sl t phl 0.98 0.94 + 0.022*sl 0.94 + 0.019*sl 0.95 + 0.018*sl t r 0.14 0.10 + 0.019*sl 0.09 + 0.024*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.09 + 0.031*sl 0.07 + 0.034*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.93 0.91 + 0.010*sl 0.92 + 0.008*sl 0.94 + 0.006*sl t phl 1.06 1.03 + 0.013*sl 1.04 + 0.011*sl 1.06 + 0.009*sl t r 0.16 0.14 + 0.009*sl 0.14 + 0.010*sl 0.12 + 0.013*sl t f 0.18 0.15 + 0.015*sl 0.15 + 0.015*sl 0.13 + 0.016*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table ay 00 11
sec asic 3-133 STD80/stdm80 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 dl2d2 STD80 dl2d4 STD80 dl3d2 STD80 dl3d4 STD80 dl4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.48 1.45 + 0.017*sl 1.46 + 0.013*sl 1.46 + 0.012*sl t phl 1.84 1.80 + 0.023*sl 1.81 + 0.019*sl 1.81 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.18 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.55 1.53 + 0.011*sl 1.53 + 0.008*sl 1.55 + 0.006*sl t phl 1.93 1.90 + 0.013*sl 1.91 + 0.011*sl 1.93 + 0.009*sl t r 0.17 0.16 + 0.008*sl 0.15 + 0.011*sl 0.13 + 0.012*sl t f 0.19 0.17 + 0.013*sl 0.16 + 0.015*sl 0.15 + 0.016*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.07 2.04 + 0.018*sl 2.05 + 0.013*sl 2.06 + 0.012*sl t phl 2.67 2.63 + 0.023*sl 2.63 + 0.019*sl 2.64 + 0.018*sl t r 0.17 0.12 + 0.021*sl 0.12 + 0.022*sl 0.09 + 0.026*sl t f 0.20 0.14 + 0.029*sl 0.14 + 0.030*sl 0.10 + 0.034*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.14 2.12 + 0.012*sl 2.13 + 0.008*sl 2.15 + 0.006*sl t phl 2.76 2.74 + 0.013*sl 2.74 + 0.011*sl 2.76 + 0.009*sl t r 0.19 0.17 + 0.009*sl 0.17 + 0.010*sl 0.14 + 0.012*sl t f 0.21 0.18 + 0.015*sl 0.18 + 0.014*sl 0.16 + 0.016*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.60 2.56 + 0.018*sl 2.57 + 0.013*sl 2.59 + 0.012*sl t phl 3.57 3.52 + 0.023*sl 3.53 + 0.019*sl 3.55 + 0.018*sl t r 0.17 0.14 + 0.019*sl 0.13 + 0.022*sl 0.09 + 0.026*sl t f 0.22 0.16 + 0.029*sl 0.16 + 0.029*sl 0.12 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-134 sec asic dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 dl4d4 STD80 dl5d2 STD80 dl5d4 STD80 dl10d2 STD80 dl10d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.67 2.65 + 0.012*sl 2.66 + 0.009*sl 2.68 + 0.006*sl t phl 3.68 3.65 + 0.014*sl 3.65 + 0.011*sl 3.68 + 0.009*sl t r 0.20 0.18 + 0.009*sl 0.18 + 0.010*sl 0.16 + 0.012*sl t f 0.23 0.20 + 0.016*sl 0.21 + 0.014*sl 0.19 + 0.016*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.20 3.16 + 0.019*sl 3.17 + 0.014*sl 3.19 + 0.012*sl t phl 4.78 4.73 + 0.025*sl 4.75 + 0.020*sl 4.76 + 0.018*sl t r 0.19 0.15 + 0.019*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.25 0.20 + 0.027*sl 0.19 + 0.029*sl 0.15 + 0.033*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.28 3.26 + 0.012*sl 3.26 + 0.009*sl 3.29 + 0.006*sl t phl 4.91 4.88 + 0.014*sl 4.88 + 0.011*sl 4.91 + 0.009*sl t r 0.21 0.20 + 0.008*sl 0.19 + 0.010*sl 0.17 + 0.012*sl t f 0.27 0.24 + 0.016*sl 0.24 + 0.014*sl 0.22 + 0.016*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 5.98 5.94 + 0.022*sl 5.95 + 0.015*sl 5.98 + 0.012*sl t phl 10.71 10.65 + 0.030*sl 10.66 + 0.023*sl 10.71 + 0.018*sl t r 0.24 0.20 + 0.019*sl 0.20 + 0.021*sl 0.15 + 0.025*sl t f 0.39 0.32 + 0.033*sl 0.33 + 0.029*sl 0.30 + 0.032*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 6.09 6.06 + 0.013*sl 6.07 + 0.010*sl 6.11 + 0.006*sl t phl 10.89 10.86 + 0.018*sl 10.87 + 0.013*sl 10.91 + 0.009*sl t r 0.28 0.26 + 0.009*sl 0.26 + 0.009*sl 0.23 + 0.012*sl t f 0.42 0.39 + 0.015*sl 0.39 + 0.014*sl 0.39 + 0.015*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-135 STD80/stdm80 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 dl1d2 stdm80 dl1d4 stdm80 dl2d2 stdm80 dl2d4 stdm80 dl3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.29 1.24 + 0.021*sl 1.25 + 0.018*sl 1.26 + 0.017*sl t phl 1.50 1.44 + 0.029*sl 1.45 + 0.024*sl 1.47 + 0.022*sl t r 0.18 0.12 + 0.032*sl 0.11 + 0.033*sl 0.11 + 0.035*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.12 + 0.038*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.36 1.33 + 0.014*sl 1.34 + 0.011*sl 1.35 + 0.010*sl t phl 1.61 1.57 + 0.017*sl 1.58 + 0.015*sl 1.59 + 0.013*sl t r 0.19 0.15 + 0.017*sl 0.15 + 0.016*sl 0.15 + 0.017*sl t f 0.21 0.17 + 0.020*sl 0.17 + 0.020*sl 0.18 + 0.019*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.23 2.19 + 0.022*sl 2.20 + 0.019*sl 2.21 + 0.017*sl t phl 3.04 2.98 + 0.029*sl 2.99 + 0.025*sl 3.01 + 0.022*sl t r 0.20 0.13 + 0.031*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.22 0.14 + 0.039*sl 0.15 + 0.037*sl 0.14 + 0.038*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.32 2.29 + 0.015*sl 2.30 + 0.012*sl 2.31 + 0.010*sl t phl 3.16 3.13 + 0.018*sl 3.14 + 0.015*sl 3.15 + 0.014*sl t r 0.20 0.18 + 0.012*sl 0.17 + 0.016*sl 0.17 + 0.016*sl t f 0.24 0.19 + 0.022*sl 0.20 + 0.019*sl 0.20 + 0.019*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.21 3.17 + 0.023*sl 3.18 + 0.019*sl 3.19 + 0.017*sl t phl 4.51 4.45 + 0.030*sl 4.46 + 0.025*sl 4.48 + 0.023*sl t r 0.21 0.15 + 0.029*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.24 0.16 + 0.039*sl 0.17 + 0.036*sl 0.17 + 0.037*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-136 sec asic dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 dl3d4 stdm80 dl4d2 stdm80 dl4d4 stdm80 dl5d2 stdm80 dl5d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.31 3.28 + 0.014*sl 3.29 + 0.012*sl 3.30 + 0.010*sl t phl 4.65 4.61 + 0.018*sl 4.62 + 0.016*sl 4.63 + 0.014*sl t r 0.22 0.19 + 0.015*sl 0.19 + 0.015*sl 0.18 + 0.016*sl t f 0.25 0.21 + 0.020*sl 0.21 + 0.020*sl 0.23 + 0.018*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 4.04 4.00 + 0.023*sl 4.01 + 0.019*sl 4.02 + 0.017*sl t phl 6.16 6.09 + 0.031*sl 6.11 + 0.026*sl 6.13 + 0.023*sl t r 0.22 0.16 + 0.031*sl 0.15 + 0.032*sl 0.14 + 0.033*sl t f 0.26 0.18 + 0.040*sl 0.19 + 0.036*sl 0.19 + 0.036*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 4.14 4.12 + 0.015*sl 4.12 + 0.012*sl 4.14 + 0.010*sl t phl 6.31 6.27 + 0.019*sl 6.28 + 0.016*sl 6.30 + 0.014*sl t r 0.23 0.20 + 0.015*sl 0.20 + 0.015*sl 0.20 + 0.016*sl t f 0.28 0.24 + 0.021*sl 0.24 + 0.020*sl 0.25 + 0.018*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 4.95 4.91 + 0.024*sl 4.92 + 0.020*sl 4.94 + 0.017*sl t phl 8.44 8.38 + 0.033*sl 8.39 + 0.027*sl 8.42 + 0.023*sl t r 0.23 0.17 + 0.031*sl 0.16 + 0.031*sl 0.16 + 0.032*sl t f 0.29 0.21 + 0.040*sl 0.23 + 0.036*sl 0.23 + 0.036*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 5.06 5.03 + 0.015*sl 5.04 + 0.012*sl 5.05 + 0.011*sl t phl 8.61 8.58 + 0.019*sl 8.59 + 0.016*sl 8.60 + 0.014*sl t r 0.24 0.21 + 0.013*sl 0.21 + 0.016*sl 0.21 + 0.015*sl t f 0.31 0.27 + 0.020*sl 0.27 + 0.019*sl 0.28 + 0.018*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-137 STD80/stdm80 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 dl10d2 stdm80 dl10d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 9.35 9.29 + 0.027*sl 9.31 + 0.021*sl 9.33 + 0.018*sl t phl 19.69 19.61 + 0.038*sl 19.63 + 0.031*sl 19.66 + 0.027*sl t r 0.27 0.21 + 0.030*sl 0.21 + 0.031*sl 0.20 + 0.031*sl t f 0.42 0.34 + 0.042*sl 0.35 + 0.038*sl 0.36 + 0.036*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 9.48 9.45 + 0.017*sl 9.46 + 0.014*sl 9.48 + 0.011*sl t phl 19.94 19.90 + 0.023*sl 19.91 + 0.019*sl 19.93 + 0.016*sl t r 0.29 0.26 + 0.015*sl 0.26 + 0.015*sl 0.26 + 0.016*sl t f 0.45 0.41 + 0.021*sl 0.41 + 0.020*sl 0.42 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-138 sec asic iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 iv STD80 ivd2 STD80 ivd3 input load (sl) gate count STD80 iv ivd2 ivd3 ivd4 ivd6 ivd8 iv ivd2 ivd3 ivd4 ivd6 ivd8 aaaaaa 1.0 1.9 2.8 3.7 5.6 7.5 0.7 1.0 1.3 1.7 2.3 3.0 stdm80 iv ivd2 ivd3 ivd4 ivd6 ivd8 iv ivd2 ivd3 ivd4 ivd6 ivd8 aaaaaa 1.0 2.1 3.0 4.0 6.0 8.0 0.7 1.0 1.3 1.7 2.3 3.0 a y path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.14 0.07 + 0.037*sl 0.10 + 0.026*sl 0.11 + 0.024*sl t phl 0.20 0.11 + 0.044*sl 0.13 + 0.036*sl 0.12 + 0.037*sl t r 0.27 0.18 + 0.043*sl 0.18 + 0.044*sl 0.11 + 0.052*sl t f 0.28 0.16 + 0.063*sl 0.16 + 0.061*sl 0.08 + 0.069*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.10 0.05 + 0.024*sl 0.07 + 0.016*sl 0.11 + 0.012*sl t phl 0.14 0.08 + 0.026*sl 0.10 + 0.020*sl 0.11 + 0.018*sl t r 0.21 0.16 + 0.024*sl 0.17 + 0.021*sl 0.13 + 0.026*sl t f 0.21 0.14 + 0.032*sl 0.15 + 0.028*sl 0.10 + 0.034*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.09 0.06 + 0.017*sl 0.07 + 0.012*sl 0.11 + 0.008*sl t phl 0.12 0.09 + 0.018*sl 0.10 + 0.014*sl 0.12 + 0.012*sl t r 0.20 0.17 + 0.016*sl 0.17 + 0.015*sl 0.15 + 0.017*sl t f 0.19 0.14 + 0.023*sl 0.15 + 0.019*sl 0.12 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table ay 01 10
sec asic 3-139 STD80/stdm80 iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ivd4 STD80 ivd6 STD80 ivd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.08 0.05 + 0.014*sl 0.06 + 0.010*sl 0.10 + 0.006*sl t phl 0.11 0.08 + 0.014*sl 0.09 + 0.011*sl 0.11 + 0.009*sl t r 0.19 0.16 + 0.011*sl 0.16 + 0.011*sl 0.15 + 0.012*sl t f 0.17 0.14 + 0.018*sl 0.15 + 0.014*sl 0.13 + 0.016*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.07 0.05 + 0.010*sl 0.05 + 0.007*sl 0.09 + 0.004*sl t phl 0.10 0.08 + 0.011*sl 0.08 + 0.008*sl 0.11 + 0.006*sl t r 0.18 0.16 + 0.008*sl 0.16 + 0.008*sl 0.16 + 0.008*sl t f 0.16 0.14 + 0.012*sl 0.14 + 0.010*sl 0.14 + 0.010*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.06 0.05 + 0.008*sl 0.05 + 0.006*sl 0.08 + 0.003*sl t phl 0.09 0.08 + 0.008*sl 0.08 + 0.007*sl 0.10 + 0.004*sl t r 0.17 0.16 + 0.008*sl 0.16 + 0.006*sl 0.17 + 0.006*sl t f 0.16 0.14 + 0.009*sl 0.14 + 0.008*sl 0.14 + 0.008*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-140 sec asic iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 iv stdm80 ivd2 stdm80 ivd3 stdm80 ivd4 stdm80 ivd6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.11 + 0.041*sl 0.13 + 0.033*sl 0.13 + 0.033*sl t phl 0.23 0.13 + 0.048*sl 0.15 + 0.044*sl 0.14 + 0.044*sl t r 0.29 0.17 + 0.060*sl 0.16 + 0.066*sl 0.13 + 0.069*sl t f 0.30 0.16 + 0.067*sl 0.13 + 0.078*sl 0.10 + 0.082*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.13 0.08 + 0.026*sl 0.10 + 0.020*sl 0.12 + 0.017*sl t phl 0.15 0.09 + 0.030*sl 0.11 + 0.023*sl 0.13 + 0.021*sl t r 0.21 0.15 + 0.030*sl 0.15 + 0.030*sl 0.13 + 0.033*sl t f 0.20 0.12 + 0.037*sl 0.13 + 0.035*sl 0.11 + 0.038*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.12 0.09 + 0.018*sl 0.10 + 0.015*sl 0.12 + 0.012*sl t phl 0.14 0.10 + 0.021*sl 0.11 + 0.017*sl 0.13 + 0.014*sl t r 0.20 0.16 + 0.021*sl 0.16 + 0.019*sl 0.15 + 0.021*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.022*sl 0.13 + 0.024*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.11 0.08 + 0.015*sl 0.09 + 0.012*sl 0.10 + 0.010*sl t phl 0.12 0.09 + 0.016*sl 0.10 + 0.014*sl 0.11 + 0.012*sl t r 0.18 0.14 + 0.018*sl 0.15 + 0.015*sl 0.16 + 0.014*sl t f 0.16 0.11 + 0.023*sl 0.14 + 0.016*sl 0.12 + 0.018*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.10 0.08 + 0.011*sl 0.08 + 0.009*sl 0.09 + 0.008*sl t phl 0.11 0.09 + 0.012*sl 0.09 + 0.010*sl 0.10 + 0.009*sl t r 0.17 0.15 + 0.011*sl 0.15 + 0.010*sl 0.15 + 0.010*sl t f 0.15 0.11 + 0.016*sl 0.13 + 0.012*sl 0.14 + 0.011*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-141 STD80/stdm80 iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ivd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.09 0.07 + 0.009*sl 0.08 + 0.007*sl 0.09 + 0.006*sl t phl 0.10 0.09 + 0.009*sl 0.09 + 0.008*sl 0.10 + 0.007*sl t r 0.16 0.14 + 0.009*sl 0.15 + 0.008*sl 0.16 + 0.007*sl t f 0.14 0.11 + 0.013*sl 0.12 + 0.010*sl 0.13 + 0.008*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-142 sec asic iva/ivd2a/ivd3a/ivd4a inverter with (2x/4x/6x/8x) p-transistor, (1x/2x/3x/4x) n-transistor logic symbol cell data input load (sl) gate count STD80 iva ivd2a ivd3a ivd4a iva ivd2a ivd3a ivd4a aaaa 0.9 1.9 2.8 3.7 0.7 1.0 1.3 1.7 stdm80 iva ivd2a ivd3a ivd4a iva ivd2a ivd3a ivd4a aaaa 1.0 2.0 3.0 4.0 0.7 1.0 1.3 1.7 a y truth table ay 01 10
sec asic 3-143 STD80/stdm80 iva/ivd2a/ivd3a/ivd4a inverter with (2x/4x/6x/8x) p-transistor, (1x/2x/3x/4x) n-transistor switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 iva STD80 ivd2a STD80 ivd3a STD80 ivd4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.14 0.07 + 0.037*sl 0.10 + 0.026*sl 0.11 + 0.024*sl t phl 0.20 0.11 + 0.044*sl 0.13 + 0.036*sl 0.12 + 0.037*sl t r 0.27 0.18 + 0.043*sl 0.18 + 0.044*sl 0.11 + 0.052*sl t f 0.28 0.16 + 0.063*sl 0.16 + 0.061*sl 0.08 + 0.069*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.10 0.05 + 0.024*sl 0.07 + 0.016*sl 0.11 + 0.012*sl t phl 0.14 0.08 + 0.026*sl 0.10 + 0.020*sl 0.11 + 0.018*sl t r 0.21 0.16 + 0.024*sl 0.17 + 0.021*sl 0.13 + 0.026*sl t f 0.21 0.14 + 0.032*sl 0.15 + 0.028*sl 0.10 + 0.034*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.09 0.06 + 0.017*sl 0.07 + 0.012*sl 0.11 + 0.008*sl t phl 0.12 0.09 + 0.018*sl 0.10 + 0.014*sl 0.12 + 0.012*sl t r 0.20 0.17 + 0.016*sl 0.17 + 0.015*sl 0.15 + 0.017*sl t f 0.19 0.14 + 0.023*sl 0.15 + 0.019*sl 0.12 + 0.022*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.08 0.05 + 0.014*sl 0.06 + 0.010*sl 0.10 + 0.006*sl t phl 0.11 0.08 + 0.014*sl 0.09 + 0.011*sl 0.11 + 0.009*sl t r 0.19 0.16 + 0.011*sl 0.16 + 0.011*sl 0.15 + 0.012*sl t f 0.17 0.14 + 0.018*sl 0.15 + 0.014*sl 0.13 + 0.016*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-144 sec asic iva/ivd2a/ivd3a/ivd4a inverter with (2x/4x/6x/8x) p-transistor, (1x/2x/3x/4x) n-transistor switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 iva stdm80 ivd2a std5m80 ivd3a stdm80 ivd4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.11 + 0.041*sl 0.13 + 0.033*sl 0.13 + 0.033*sl t phl 0.23 0.13 + 0.048*sl 0.15 + 0.044*sl 0.14 + 0.044*sl t r 0.29 0.17 + 0.060*sl 0.16 + 0.066*sl 0.13 + 0.069*sl t f 0.30 0.16 + 0.067*sl 0.13 + 0.078*sl 0.10 + 0.082*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.13 0.08 + 0.026*sl 0.10 + 0.020*sl 0.12 + 0.017*sl t phl 0.15 0.09 + 0.030*sl 0.11 + 0.023*sl 0.13 + 0.021*sl t r 0.21 0.15 + 0.030*sl 0.15 + 0.030*sl 0.13 + 0.033*sl t f 0.20 0.12 + 0.037*sl 0.13 + 0.035*sl 0.11 + 0.038*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.12 0.09 + 0.018*sl 0.10 + 0.015*sl 0.12 + 0.012*sl t phl 0.14 0.10 + 0.021*sl 0.11 + 0.017*sl 0.13 + 0.014*sl t r 0.20 0.16 + 0.021*sl 0.16 + 0.019*sl 0.15 + 0.021*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.022*sl 0.13 + 0.024*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.11 0.08 + 0.015*sl 0.09 + 0.012*sl 0.10 + 0.010*sl t phl 0.12 0.09 + 0.016*sl 0.10 + 0.014*sl 0.11 + 0.012*sl t r 0.18 0.14 + 0.018*sl 0.15 + 0.015*sl 0.16 + 0.014*sl t f 0.16 0.11 + 0.023*sl 0.14 + 0.016*sl 0.12 + 0.018*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-145 STD80/stdm80 ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ivcd11 STD80 ivcd13 input load (sl) gate count STD80 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 aaaaa 1.0 0.9 1.9 1.9 3.8 1.0 1.7 1.7 3.0 3.0 stdm80 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 aaaaa 1.0 1.0 2.0 2.0 4.0 1.0 1.7 1.7 3.0 3.0 a y yn path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.11 + 0.032*sl 0.13 + 0.024*sl 0.14 + 0.024*sl t phl 0.23 0.15 + 0.040*sl 0.16 + 0.036*sl 0.15 + 0.037*sl t r 0.31 0.23 + 0.037*sl 0.22 + 0.045*sl 0.15 + 0.052*sl t f 0.34 0.23 + 0.053*sl 0.21 + 0.062*sl 0.15 + 0.069*sl y to yn t plh 0.14 0.07 + 0.037*sl 0.10 + 0.026*sl 0.11 + 0.024*sl t phl 0.20 0.11 + 0.044*sl 0.13 + 0.036*sl 0.12 + 0.037*sl t r 0.27 0.18 + 0.043*sl 0.18 + 0.044*sl 0.11 + 0.052*sl t f 0.28 0.16 + 0.064*sl 0.16 + 0.061*sl 0.08 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.18 + 0.027*sl 0.19 + 0.023*sl 0.18 + 0.024*sl t phl 0.29 0.22 + 0.034*sl 0.22 + 0.036*sl 0.21 + 0.037*sl t r 0.42 0.33 + 0.045*sl 0.32 + 0.046*sl 0.27 + 0.052*sl t f 0.49 0.37 + 0.059*sl 0.36 + 0.065*sl 0.31 + 0.069*sl y to yn t plh 0.09 0.06 + 0.017*sl 0.07 + 0.012*sl 0.11 + 0.008*sl t phl 0.12 0.09 + 0.018*sl 0.10 + 0.014*sl 0.12 + 0.012*sl t r 0.20 0.17 + 0.017*sl 0.17 + 0.014*sl 0.15 + 0.017*sl t f 0.19 0.15 + 0.022*sl 0.15 + 0.019*sl 0.12 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table ayyn 101 010
STD80/stdm80 3-146 sec asic ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ivcd22 STD80 ivcd26 STD80 ivcd44 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.14 0.10 + 0.018*sl 0.11 + 0.014*sl 0.13 + 0.012*sl t phl 0.17 0.13 + 0.022*sl 0.14 + 0.018*sl 0.14 + 0.018*sl t r 0.26 0.23 + 0.018*sl 0.22 + 0.020*sl 0.17 + 0.026*sl t f 0.28 0.23 + 0.025*sl 0.22 + 0.027*sl 0.16 + 0.034*sl y to yn t plh 0.10 0.05 + 0.024*sl 0.07 + 0.016*sl 0.11 + 0.012*sl t phl 0.14 0.08 + 0.026*sl 0.10 + 0.020*sl 0.11 + 0.018*sl t r 0.21 0.16 + 0.024*sl 0.17 + 0.021*sl 0.13 + 0.026*sl t f 0.21 0.14 + 0.032*sl 0.15 + 0.028*sl 0.10 + 0.034*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.17 + 0.013*sl 0.18 + 0.012*sl 0.18 + 0.012*sl t phl 0.24 0.20 + 0.018*sl 0.21 + 0.017*sl 0.20 + 0.018*sl t r 0.36 0.31 + 0.023*sl 0.31 + 0.023*sl 0.29 + 0.026*sl t f 0.41 0.35 + 0.030*sl 0.35 + 0.030*sl 0.31 + 0.034*sl y to yn t plh 0.07 0.05 + 0.010*sl 0.05 + 0.007*sl 0.09 + 0.004*sl t phl 0.10 0.08 + 0.010*sl 0.08 + 0.008*sl 0.11 + 0.006*sl t r 0.18 0.16 + 0.008*sl 0.16 + 0.008*sl 0.16 + 0.008*sl t f 0.16 0.14 + 0.012*sl 0.14 + 0.010*sl 0.14 + 0.010*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.12 0.10 + 0.009*sl 0.10 + 0.008*sl 0.13 + 0.006*sl t phl 0.15 0.13 + 0.011*sl 0.13 + 0.010*sl 0.14 + 0.009*sl t r 0.24 0.22 + 0.010*sl 0.23 + 0.009*sl 0.19 + 0.012*sl t f 0.25 0.22 + 0.013*sl 0.23 + 0.012*sl 0.19 + 0.016*sl y to yn t plh 0.08 0.05 + 0.014*sl 0.06 + 0.010*sl 0.10 + 0.006*sl t phl 0.11 0.08 + 0.014*sl 0.09 + 0.011*sl 0.11 + 0.009*sl t r 0.19 0.16 + 0.011*sl 0.16 + 0.011*sl 0.15 + 0.012*sl t f 0.17 0.14 + 0.018*sl 0.15 + 0.014*sl 0.13 + 0.016*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-147 STD80/stdm80 ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ivcd11 stdm80 ivcd13 stdm80 ivcd22 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.15 + 0.036*sl 0.16 + 0.033*sl 0.16 + 0.033*sl t phl 0.27 0.18 + 0.045*sl 0.18 + 0.044*sl 0.18 + 0.044*sl t r 0.35 0.23 + 0.062*sl 0.21 + 0.067*sl 0.19 + 0.070*sl t f 0.36 0.22 + 0.072*sl 0.20 + 0.079*sl 0.18 + 0.082*sl y to yn t plh 0.19 0.11 + 0.041*sl 0.13 + 0.033*sl 0.13 + 0.033*sl t phl 0.23 0.13 + 0.048*sl 0.14 + 0.044*sl 0.14 + 0.044*sl t r 0.29 0.17 + 0.061*sl 0.16 + 0.066*sl 0.13 + 0.069*sl t f 0.30 0.16 + 0.067*sl 0.13 + 0.078*sl 0.11 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.23 + 0.033*sl 0.23 + 0.033*sl 0.23 + 0.033*sl t phl 0.33 0.25 + 0.044*sl 0.25 + 0.044*sl 0.24 + 0.044*sl t r 0.51 0.37 + 0.067*sl 0.37 + 0.069*sl 0.36 + 0.070*sl t f 0.56 0.40 + 0.078*sl 0.39 + 0.081*sl 0.38 + 0.082*sl y to yn t plh 0.12 0.09 + 0.018*sl 0.10 + 0.015*sl 0.12 + 0.012*sl t phl 0.14 0.10 + 0.020*sl 0.11 + 0.017*sl 0.13 + 0.014*sl t r 0.20 0.16 + 0.021*sl 0.16 + 0.019*sl 0.15 + 0.021*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.023*sl 0.13 + 0.023*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.14 + 0.021*sl 0.15 + 0.018*sl 0.15 + 0.017*sl t phl 0.20 0.14 + 0.025*sl 0.16 + 0.022*sl 0.16 + 0.021*sl t r 0.27 0.22 + 0.025*sl 0.20 + 0.032*sl 0.19 + 0.033*sl t f 0.27 0.21 + 0.029*sl 0.19 + 0.036*sl 0.18 + 0.038*sl y to yn t plh 0.13 0.08 + 0.026*sl 0.10 + 0.020*sl 0.12 + 0.017*sl t phl 0.15 0.09 + 0.030*sl 0.11 + 0.023*sl 0.13 + 0.021*sl t r 0.21 0.15 + 0.030*sl 0.15 + 0.030*sl 0.13 + 0.033*sl t f 0.20 0.12 + 0.038*sl 0.13 + 0.035*sl 0.11 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-148 sec asic ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ivcd26 stdm80 ivcd44 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.22 + 0.016*sl 0.22 + 0.016*sl 0.22 + 0.017*sl t phl 0.27 0.22 + 0.021*sl 0.22 + 0.021*sl 0.22 + 0.021*sl t r 0.41 0.34 + 0.034*sl 0.35 + 0.034*sl 0.35 + 0.034*sl t f 0.45 0.37 + 0.038*sl 0.37 + 0.038*sl 0.36 + 0.039*sl y to yn t plh 0.10 0.08 + 0.011*sl 0.08 + 0.009*sl 0.09 + 0.008*sl t phl 0.11 0.09 + 0.012*sl 0.09 + 0.010*sl 0.10 + 0.009*sl t r 0.17 0.15 + 0.011*sl 0.15 + 0.010*sl 0.15 + 0.010*sl t f 0.15 0.11 + 0.016*sl 0.13 + 0.012*sl 0.14 + 0.011*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.16 0.13 + 0.011*sl 0.14 + 0.010*sl 0.15 + 0.009*sl t phl 0.17 0.14 + 0.014*sl 0.15 + 0.012*sl 0.15 + 0.011*sl t r 0.25 0.23 + 0.009*sl 0.22 + 0.013*sl 0.20 + 0.016*sl t f 0.24 0.21 + 0.015*sl 0.22 + 0.013*sl 0.19 + 0.018*sl y to yn t plh 0.11 0.08 + 0.015*sl 0.09 + 0.012*sl 0.10 + 0.010*sl t phl 0.12 0.09 + 0.016*sl 0.10 + 0.014*sl 0.11 + 0.012*sl t r 0.18 0.14 + 0.018*sl 0.15 + 0.015*sl 0.16 + 0.014*sl t f 0.16 0.11 + 0.023*sl 0.14 + 0.016*sl 0.12 + 0.018*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-149 STD80/stdm80 ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ivt input load (sl) output load (sl) gate count STD80 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 aeaeaeae y y y y 0.7 1.1 0.7 1.4 0.7 2.2 0.7 3.7 0.9 1.7 4.8 9.7 2.3 3.0 4.3 7.0 stdm80 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 aeaeaeae y y y y 0.7 1.1 0.7 1.4 0.7 2.3 0.7 3.9 1.0 1.9 5.2 10.5 2.3 3.0 4.3 7.0 a y e path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.35 + 0.019*sl 0.36 + 0.015*sl 0.39 + 0.012*sl t phl 0.42 0.34 + 0.039*sl 0.34 + 0.039*sl 0.35 + 0.039*sl t r 0.18 0.13 + 0.023*sl 0.13 + 0.025*sl 0.10 + 0.027*sl t f 0.26 0.11 + 0.074*sl 0.10 + 0.076*sl 0.09 + 0.078*sl e to y t plh 0.26 0.22 + 0.020*sl 0.23 + 0.015*sl 0.26 + 0.012*sl t phl 0.17 0.05 + 0.057*sl 0.09 + 0.041*sl 0.11 + 0.039*sl t r 0.19 0.15 + 0.021*sl 0.14 + 0.024*sl 0.11 + 0.027*sl t f 0.31 0.17 + 0.070*sl 0.17 + 0.071*sl 0.11 + 0.078*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.36 0.36 + 0.000*sl 0.36 + 0.000*sl 0.36 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aey x 0 hi-z 011 110
STD80/stdm80 3-150 sec asic ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ivtd2 STD80 ivtd4 STD80 ivtd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.46 0.43 + 0.013*sl 0.44 + 0.010*sl 0.47 + 0.006*sl t phl 0.47 0.43 + 0.020*sl 0.43 + 0.019*sl 0.43 + 0.019*sl t r 0.21 0.18 + 0.013*sl 0.19 + 0.012*sl 0.17 + 0.013*sl t f 0.21 0.14 + 0.035*sl 0.14 + 0.035*sl 0.11 + 0.039*sl e to y t plh 0.33 0.30 + 0.013*sl 0.31 + 0.010*sl 0.34 + 0.006*sl t phl 0.10 0.04 + 0.034*sl 0.06 + 0.024*sl 0.10 + 0.019*sl t r 0.22 0.19 + 0.013*sl 0.20 + 0.012*sl 0.18 + 0.013*sl t f 0.24 0.16 + 0.040*sl 0.17 + 0.035*sl 0.13 + 0.039*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.51 0.51 + 0.001*sl 0.51 + 0.000*sl 0.51 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.58 0.56 + 0.010*sl 0.57 + 0.008*sl 0.60 + 0.004*sl t phl 0.66 0.63 + 0.013*sl 0.64 + 0.011*sl 0.65 + 0.010*sl t r 0.29 0.28 + 0.006*sl 0.28 + 0.007*sl 0.28 + 0.006*sl t f 0.27 0.24 + 0.013*sl 0.23 + 0.016*sl 0.21 + 0.019*sl e to y t plh 0.46 0.44 + 0.010*sl 0.44 + 0.008*sl 0.48 + 0.004*sl t phl 0.06 0.02 + 0.017*sl 0.03 + 0.013*sl 0.06 + 0.010*sl t r 0.29 0.28 + 0.007*sl 0.28 + 0.007*sl 0.28 + 0.006*sl t f 0.19 0.15 + 0.019*sl 0.15 + 0.018*sl 0.15 + 0.019*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.73 0.73 + 0.000*sl 0.73 + 0.000*sl 0.73 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.87 0.86 + 0.006*sl 0.86 + 0.006*sl 0.88 + 0.003*sl t phl 1.04 1.03 + 0.007*sl 1.03 + 0.007*sl 1.05 + 0.005*sl t r 0.51 0.51 + 0.001*sl 0.51 + 0.002*sl 0.50 + 0.003*sl t f 0.45 0.44 + 0.005*sl 0.44 + 0.006*sl 0.42 + 0.008*sl e to y t plh 0.75 0.74 + 0.006*sl 0.74 + 0.005*sl 0.76 + 0.003*sl t phl 0.04 0.02 + 0.009*sl 0.02 + 0.008*sl 0.05 + 0.005*sl t r 0.51 0.51 + 0.001*sl 0.51 + 0.002*sl 0.50 + 0.003*sl t f 0.18 0.16 + 0.008*sl 0.16 + 0.010*sl 0.16 + 0.009*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 1.26 1.26 + 0.001*sl 1.26 + 0.000*sl 1.26 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-151 STD80/stdm80 ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ivt stdm80 ivtd2 stdm80 ivtd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.53 0.48 + 0.025*sl 0.49 + 0.021*sl 0.51 + 0.019*sl t phl 0.57 0.47 + 0.053*sl 0.47 + 0.051*sl 0.48 + 0.050*sl t r 0.23 0.16 + 0.034*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t f 0.34 0.16 + 0.095*sl 0.15 + 0.097*sl 0.14 + 0.099*sl e to y t plh 0.37 0.32 + 0.025*sl 0.33 + 0.021*sl 0.35 + 0.019*sl t phl 0.25 0.14 + 0.055*sl 0.15 + 0.051*sl 0.15 + 0.050*sl t r 0.24 0.16 + 0.036*sl 0.17 + 0.034*sl 0.16 + 0.035*sl t f 0.35 0.18 + 0.089*sl 0.16 + 0.095*sl 0.13 + 0.099*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.46 0.46 + 0.000*sl 0.46 + 0.000*sl 0.46 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.62 0.59 + 0.017*sl 0.60 + 0.014*sl 0.61 + 0.012*sl t phl 0.64 0.59 + 0.028*sl 0.59 + 0.027*sl 0.60 + 0.025*sl t r 0.25 0.21 + 0.019*sl 0.22 + 0.018*sl 0.22 + 0.018*sl t f 0.27 0.18 + 0.046*sl 0.18 + 0.046*sl 0.17 + 0.048*sl e to y t plh 0.46 0.42 + 0.017*sl 0.43 + 0.014*sl 0.45 + 0.012*sl t phl 0.18 0.12 + 0.032*sl 0.13 + 0.026*sl 0.14 + 0.026*sl t r 0.25 0.22 + 0.018*sl 0.22 + 0.018*sl 0.22 + 0.018*sl t f 0.26 0.17 + 0.044*sl 0.17 + 0.046*sl 0.15 + 0.047*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.67 0.67 + 0.000*sl 0.67 + 0.000*sl 0.67 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.79 0.77 + 0.013*sl 0.77 + 0.011*sl 0.79 + 0.009*sl t phl 0.89 0.86 + 0.017*sl 0.86 + 0.016*sl 0.87 + 0.015*sl t r 0.33 0.31 + 0.010*sl 0.31 + 0.010*sl 0.32 + 0.010*sl t f 0.32 0.27 + 0.024*sl 0.28 + 0.023*sl 0.27 + 0.024*sl e to y t plh 0.64 0.61 + 0.013*sl 0.62 + 0.011*sl 0.63 + 0.009*sl t phl 0.13 0.10 + 0.018*sl 0.10 + 0.015*sl 0.11 + 0.014*sl t r 0.33 0.31 + 0.010*sl 0.31 + 0.010*sl 0.32 + 0.010*sl t f 0.21 0.17 + 0.024*sl 0.16 + 0.025*sl 0.17 + 0.024*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.97 0.97 + 0.000*sl 0.97 + 0.000*sl 0.97 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-152 sec asic ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ivtd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.19 1.17 + 0.008*sl 1.17 + 0.008*sl 1.18 + 0.007*sl t phl 1.40 1.38 + 0.010*sl 1.38 + 0.009*sl 1.39 + 0.009*sl t r 0.56 0.55 + 0.004*sl 0.55 + 0.005*sl 0.55 + 0.005*sl t f 0.50 0.48 + 0.010*sl 0.48 + 0.011*sl 0.48 + 0.011*sl e to y t plh 1.05 1.03 + 0.008*sl 1.03 + 0.008*sl 1.04 + 0.007*sl t phl 0.11 0.09 + 0.009*sl 0.10 + 0.009*sl 0.10 + 0.008*sl t r 0.56 0.55 + 0.003*sl 0.54 + 0.005*sl 0.55 + 0.005*sl t f 0.19 0.17 + 0.013*sl 0.17 + 0.012*sl 0.17 + 0.013*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 1.69 1.69 + 0.000*sl 1.69 + 0.000*sl 1.69 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-153 STD80/stdm80 ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ivtn input load (sl) output load (sl) STD80 ivtn ivtnd2 ivtnd4 ivtnd8 ivtn ivtnd2 ivtnd4 ivtnd8 aenaenaenaenyyyy 0.8 0.7 0.8 0.7 0.8 0.7 0.8 0.7 1.3 2.4 4.8 9.8 stdm80 ivtn ivtnd2 ivtnd4 ivtnd8 ivtn ivtnd2 ivtnd4 ivtnd8 aenaenaenaenyyyy 0.8 0.7 0.8 0.7 0.8 0.7 0.8 0.7 1.4 2.6 5.2 10.6 STD80/stdm80 gate count ivtn ivtnd2 ivtnd4 ivtnd8 2.7 3.3 4.7 7.3 ay en path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.38 0.34 + 0.020*sl 0.35 + 0.015*sl 0.38 + 0.012*sl t phl 0.44 0.36 + 0.040*sl 0.36 + 0.039*sl 0.36 + 0.039*sl t r 0.17 0.12 + 0.023*sl 0.12 + 0.025*sl 0.09 + 0.027*sl t f 0.27 0.12 + 0.072*sl 0.11 + 0.076*sl 0.10 + 0.078*sl en to y t plh 0.41 0.37 + 0.020*sl 0.38 + 0.015*sl 0.40 + 0.012*sl t phl 0.31 0.22 + 0.044*sl 0.23 + 0.040*sl 0.25 + 0.039*sl t r 0.17 0.12 + 0.026*sl 0.12 + 0.024*sl 0.09 + 0.027*sl t f 0.26 0.11 + 0.074*sl 0.11 + 0.077*sl 0.10 + 0.078*sl t plz 0.16 0.16 + 0.000*sl 0.16 + 0.000*sl 0.17 + 0.000*sl t phz 0.38 0.38 + 0.001*sl 0.38 + 0.000*sl 0.38 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aeny x 1 hi-z 001 100
STD80/stdm80 3-154 sec asic ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ivtnd2 STD80 ivtnd4 STD80 ivtnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.41 + 0.015*sl 0.42 + 0.011*sl 0.46 + 0.006*sl t phl 0.49 0.45 + 0.022*sl 0.45 + 0.020*sl 0.45 + 0.019*sl t r 0.19 0.16 + 0.014*sl 0.17 + 0.012*sl 0.16 + 0.013*sl t f 0.22 0.15 + 0.036*sl 0.15 + 0.036*sl 0.12 + 0.039*sl en to y t plh 0.49 0.46 + 0.015*sl 0.47 + 0.010*sl 0.50 + 0.006*sl t phl 0.28 0.23 + 0.023*sl 0.23 + 0.021*sl 0.25 + 0.019*sl t r 0.19 0.17 + 0.011*sl 0.17 + 0.013*sl 0.16 + 0.013*sl t f 0.18 0.11 + 0.036*sl 0.11 + 0.038*sl 0.10 + 0.039*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.53 0.53 + 0.001*sl 0.53 + 0.000*sl 0.54 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.55 + 0.010*sl 0.56 + 0.008*sl 0.60 + 0.004*sl t phl 0.66 0.64 + 0.013*sl 0.64 + 0.011*sl 0.66 + 0.009*sl t r 0.29 0.27 + 0.007*sl 0.28 + 0.006*sl 0.28 + 0.006*sl t f 0.27 0.24 + 0.013*sl 0.24 + 0.016*sl 0.21 + 0.019*sl en to y t plh 0.67 0.65 + 0.009*sl 0.65 + 0.008*sl 0.69 + 0.004*sl t phl 0.28 0.25 + 0.014*sl 0.26 + 0.012*sl 0.28 + 0.010*sl t r 0.29 0.28 + 0.006*sl 0.28 + 0.007*sl 0.28 + 0.006*sl t f 0.16 0.12 + 0.018*sl 0.12 + 0.019*sl 0.12 + 0.019*sl t plz 0.29 0.29 + 0.000*sl 0.29 + 0.000*sl 0.29 + 0.000*sl t phz 0.84 0.84 + 0.001*sl 0.84 + 0.000*sl 0.84 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.87 0.86 + 0.006*sl 0.86 + 0.005*sl 0.88 + 0.003*sl t phl 1.05 1.04 + 0.008*sl 1.04 + 0.007*sl 1.06 + 0.005*sl t r 0.51 0.51 + 0.001*sl 0.51 + 0.002*sl 0.50 + 0.003*sl t f 0.46 0.45 + 0.004*sl 0.45 + 0.006*sl 0.43 + 0.008*sl en to y t plh 1.06 1.05 + 0.006*sl 1.05 + 0.005*sl 1.07 + 0.003*sl t phl 0.32 0.30 + 0.008*sl 0.31 + 0.007*sl 0.33 + 0.005*sl t r 0.52 0.52 + 0.001*sl 0.51 + 0.002*sl 0.50 + 0.003*sl t f 0.17 0.15 + 0.011*sl 0.15 + 0.010*sl 0.15 + 0.010*sl t plz 0.41 0.41 + 0.000*sl 0.41 + 0.000*sl 0.41 + 0.000*sl t phz 1.47 1.47 + 0.000*sl 1.47 + 0.000*sl 1.47 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-155 STD80/stdm80 ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ivtn stdm80 ivtnd2 stdm80 ivtnd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.52 0.46 + 0.027*sl 0.48 + 0.022*sl 0.50 + 0.019*sl t phl 0.60 0.49 + 0.054*sl 0.50 + 0.051*sl 0.51 + 0.050*sl t r 0.22 0.15 + 0.036*sl 0.15 + 0.036*sl 0.15 + 0.036*sl t f 0.36 0.17 + 0.095*sl 0.16 + 0.097*sl 0.15 + 0.099*sl en to y t plh 0.55 0.49 + 0.027*sl 0.51 + 0.022*sl 0.53 + 0.019*sl t phl 0.42 0.31 + 0.055*sl 0.32 + 0.052*sl 0.32 + 0.051*sl t r 0.22 0.15 + 0.036*sl 0.15 + 0.035*sl 0.15 + 0.035*sl t f 0.34 0.15 + 0.096*sl 0.14 + 0.099*sl 0.14 + 0.099*sl t plz 0.25 0.25 + 0.000*sl 0.25 + 0.000*sl 0.25 + 0.000*sl t phz 0.52 0.52 + 0.000*sl 0.52 + 0.000*sl 0.51 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.60 0.56 + 0.019*sl 0.57 + 0.015*sl 0.59 + 0.013*sl t phl 0.67 0.61 + 0.030*sl 0.62 + 0.027*sl 0.63 + 0.026*sl t r 0.23 0.19 + 0.020*sl 0.20 + 0.018*sl 0.20 + 0.018*sl t f 0.28 0.18 + 0.050*sl 0.19 + 0.047*sl 0.19 + 0.048*sl en to y t plh 0.66 0.62 + 0.019*sl 0.63 + 0.015*sl 0.65 + 0.012*sl t phl 0.37 0.31 + 0.030*sl 0.32 + 0.028*sl 0.33 + 0.026*sl t r 0.24 0.19 + 0.020*sl 0.20 + 0.018*sl 0.20 + 0.018*sl t f 0.24 0.14 + 0.049*sl 0.15 + 0.049*sl 0.14 + 0.049*sl t plz 0.28 0.28 + 0.001*sl 0.28 + 0.000*sl 0.28 + 0.000*sl t phz 0.72 0.72 + 0.000*sl 0.72 + 0.000*sl 0.72 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.78 0.76 + 0.013*sl 0.76 + 0.011*sl 0.78 + 0.009*sl t phl 0.90 0.87 + 0.017*sl 0.87 + 0.016*sl 0.88 + 0.015*sl t r 0.33 0.31 + 0.010*sl 0.31 + 0.010*sl 0.32 + 0.009*sl t f 0.33 0.28 + 0.023*sl 0.28 + 0.024*sl 0.28 + 0.023*sl en to y t plh 0.91 0.88 + 0.013*sl 0.89 + 0.011*sl 0.90 + 0.009*sl t phl 0.38 0.35 + 0.017*sl 0.35 + 0.016*sl 0.36 + 0.015*sl t r 0.33 0.31 + 0.009*sl 0.31 + 0.010*sl 0.31 + 0.010*sl t f 0.21 0.16 + 0.025*sl 0.16 + 0.026*sl 0.16 + 0.025*sl t plz 0.34 0.34 + 0.000*sl 0.34 + 0.000*sl 0.34 + 0.000*sl t phz 1.13 1.13 + 0.000*sl 1.13 + 0.000*sl 1.13 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-156 sec asic ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ivtnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.19 1.17 + 0.009*sl 1.17 + 0.008*sl 1.18 + 0.007*sl t phl 1.42 1.40 + 0.011*sl 1.40 + 0.009*sl 1.41 + 0.009*sl t r 0.56 0.55 + 0.004*sl 0.55 + 0.005*sl 0.55 + 0.005*sl t f 0.52 0.50 + 0.009*sl 0.49 + 0.011*sl 0.50 + 0.010*sl en to y t plh 1.46 1.44 + 0.009*sl 1.44 + 0.007*sl 1.45 + 0.007*sl t phl 0.45 0.43 + 0.010*sl 0.43 + 0.009*sl 0.43 + 0.009*sl t r 0.57 0.56 + 0.004*sl 0.56 + 0.005*sl 0.55 + 0.005*sl t f 0.22 0.19 + 0.014*sl 0.19 + 0.014*sl 0.20 + 0.014*sl t plz 0.49 0.49 + 0.000*sl 0.49 + 0.000*sl 0.49 + 0.000*sl t phz 1.98 1.98 + 0.000*sl 1.98 + 0.000*sl 1.98 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-157 STD80/stdm80 nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nid STD80 nid2 STD80 nid3 input load (sl) gate count STD80 nid nid2 nid3 nid4 nid6 nid8 nid nid2 nid3 nid4 nid6 nid8 aaaaaa 0.7 0.6 0.7 1.3 1.3 1.3 1.0 1.3 1.7 2.3 3.0 3.7 stdm80 nid nid2 nid3 nid4 nid6 nid8 nid nid2 nid3 nid4 nid6 nid8 aaaaaa 0.8 0.8 0.8 1.5 1.5 1.5 1.0 1.3 1.7 2.3 3.0 3.7 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.17 + 0.026*sl 0.17 + 0.024*sl 0.17 + 0.024*sl t phl 0.32 0.24 + 0.039*sl 0.24 + 0.037*sl 0.24 + 0.037*sl t r 0.19 0.10 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.067*sl 0.06 + 0.069*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.20 + 0.017*sl 0.21 + 0.013*sl 0.22 + 0.012*sl t phl 0.32 0.28 + 0.021*sl 0.28 + 0.019*sl 0.29 + 0.018*sl t r 0.15 0.10 + 0.024*sl 0.11 + 0.022*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.25 + 0.012*sl 0.25 + 0.009*sl 0.27 + 0.008*sl t phl 0.36 0.33 + 0.015*sl 0.34 + 0.013*sl 0.35 + 0.012*sl t r 0.16 0.13 + 0.012*sl 0.13 + 0.015*sl 0.10 + 0.017*sl t f 0.16 0.12 + 0.020*sl 0.12 + 0.020*sl 0.10 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table ay 00 11
STD80/stdm80 3-158 sec asic nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nid4 STD80 nid6 STD80 nid8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.18 + 0.009*sl 0.19 + 0.007*sl 0.20 + 0.006*sl t phl 0.29 0.27 + 0.011*sl 0.27 + 0.010*sl 0.28 + 0.009*sl t r 0.13 0.11 + 0.010*sl 0.10 + 0.011*sl 0.08 + 0.013*sl t f 0.12 0.10 + 0.011*sl 0.09 + 0.015*sl 0.08 + 0.017*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.22 + 0.008*sl 0.23 + 0.005*sl 0.24 + 0.004*sl t phl 0.33 0.32 + 0.008*sl 0.32 + 0.007*sl 0.33 + 0.006*sl t r 0.14 0.12 + 0.008*sl 0.13 + 0.007*sl 0.11 + 0.008*sl t f 0.13 0.11 + 0.010*sl 0.11 + 0.010*sl 0.10 + 0.011*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.26 + 0.006*sl 0.26 + 0.004*sl 0.28 + 0.003*sl t phl 0.38 0.36 + 0.007*sl 0.37 + 0.006*sl 0.38 + 0.005*sl t r 0.15 0.15 + 0.002*sl 0.14 + 0.005*sl 0.13 + 0.006*sl t f 0.15 0.14 + 0.008*sl 0.14 + 0.007*sl 0.13 + 0.008*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-159 STD80/stdm80 nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nid stdm80 nid2 stdm80 nid3 stdm80 nid4 stdm80 nid6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.22 + 0.035*sl 0.22 + 0.034*sl 0.23 + 0.033*sl t phl 0.40 0.31 + 0.048*sl 0.31 + 0.045*sl 0.32 + 0.044*sl t r 0.25 0.12 + 0.066*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.27 0.12 + 0.079*sl 0.11 + 0.082*sl 0.10 + 0.083*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.26 + 0.021*sl 0.27 + 0.018*sl 0.27 + 0.017*sl t phl 0.40 0.35 + 0.028*sl 0.36 + 0.024*sl 0.37 + 0.022*sl t r 0.18 0.11 + 0.033*sl 0.11 + 0.033*sl 0.10 + 0.035*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.039*sl 0.12 + 0.038*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.34 0.30 + 0.016*sl 0.31 + 0.013*sl 0.32 + 0.012*sl t phl 0.46 0.42 + 0.021*sl 0.43 + 0.018*sl 0.44 + 0.016*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.022*sl 0.14 + 0.022*sl t f 0.20 0.15 + 0.027*sl 0.16 + 0.025*sl 0.16 + 0.024*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.23 + 0.012*sl 0.24 + 0.010*sl 0.24 + 0.009*sl t phl 0.35 0.32 + 0.015*sl 0.33 + 0.013*sl 0.34 + 0.012*sl t r 0.14 0.11 + 0.017*sl 0.11 + 0.016*sl 0.11 + 0.017*sl t f 0.15 0.10 + 0.022*sl 0.11 + 0.019*sl 0.11 + 0.019*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.27 + 0.009*sl 0.28 + 0.007*sl 0.28 + 0.007*sl t phl 0.41 0.39 + 0.011*sl 0.39 + 0.010*sl 0.40 + 0.009*sl t r 0.15 0.13 + 0.008*sl 0.12 + 0.011*sl 0.12 + 0.011*sl t f 0.16 0.13 + 0.013*sl 0.13 + 0.014*sl 0.14 + 0.013*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-160 sec asic nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nid8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.33 0.32 + 0.007*sl 0.32 + 0.006*sl 0.32 + 0.006*sl t phl 0.47 0.46 + 0.009*sl 0.46 + 0.008*sl 0.46 + 0.008*sl t r 0.16 0.14 + 0.009*sl 0.15 + 0.008*sl 0.14 + 0.009*sl t f 0.18 0.16 + 0.011*sl 0.16 + 0.011*sl 0.17 + 0.010*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-161 STD80/stdm80 nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nit input load (sl) output load (sl) gate count STD80 nit nitd2 nitd4 nitd8 nit nitd2 nitd4 nitd 8 nit nitd2 nitd4 nitd8 aeaeaeae yyyy 0.8 0.9 0.7 1.0 0.8 1.8 0.8 2.9 0.9 1.7 4.1 8.2 1.7 2.3 3.7 6.3 stdm80 nit nitd2 nitd4 nitd8 nit nitd2 nitd4 nitd 8 nit nitd2 nitd4 nitd8 aeaeaeae yyyy 0.6 1.1 0.5 1.4 0.6 2.2 0.6 3.7 1.0 1.9 4.5 9.0 1.7 2.3 3.7 6.3 ay e path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.25 + 0.019*sl 0.26 + 0.015*sl 0.28 + 0.012*sl t phl 0.38 0.30 + 0.039*sl 0.30 + 0.038*sl 0.30 + 0.039*sl t r 0.19 0.14 + 0.024*sl 0.14 + 0.023*sl 0.11 + 0.027*sl t f 0.26 0.12 + 0.071*sl 0.11 + 0.076*sl 0.09 + 0.078*sl e to y t plh 0.26 0.22 + 0.020*sl 0.23 + 0.015*sl 0.26 + 0.012*sl t phl 0.17 0.06 + 0.057*sl 0.09 + 0.041*sl 0.12 + 0.039*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.11 + 0.027*sl t f 0.31 0.17 + 0.070*sl 0.17 + 0.072*sl 0.11 + 0.078*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.36 0.36 + -0.002*sl 0.36 + 0.000*sl 0.36 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aey x 0 hi-z 010 111
STD80/stdm80 3-162 sec asic nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nitd2 STD80 nitd4 STD80 nitd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.33 + 0.013*sl 0.34 + 0.010*sl 0.37 + 0.006*sl t phl 0.43 0.40 + 0.019*sl 0.40 + 0.019*sl 0.39 + 0.019*sl t r 0.22 0.19 + 0.012*sl 0.19 + 0.011*sl 0.18 + 0.013*sl t f 0.21 0.15 + 0.032*sl 0.14 + 0.035*sl 0.11 + 0.039*sl e to y t plh 0.33 0.30 + 0.013*sl 0.31 + 0.010*sl 0.35 + 0.006*sl t phl 0.10 0.04 + 0.034*sl 0.06 + 0.024*sl 0.10 + 0.019*sl t r 0.22 0.19 + 0.014*sl 0.20 + 0.011*sl 0.19 + 0.013*sl t f 0.24 0.15 + 0.041*sl 0.17 + 0.035*sl 0.13 + 0.039*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.52 0.52 + 0.001*sl 0.52 + 0.000*sl 0.52 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.48 0.47 + 0.009*sl 0.47 + 0.007*sl 0.50 + 0.004*sl t phl 0.61 0.58 + 0.012*sl 0.59 + 0.010*sl 0.59 + 0.009*sl t r 0.30 0.29 + 0.005*sl 0.29 + 0.006*sl 0.29 + 0.006*sl t f 0.27 0.24 + 0.013*sl 0.24 + 0.015*sl 0.20 + 0.019*sl e to y t plh 0.47 0.45 + 0.009*sl 0.45 + 0.007*sl 0.49 + 0.004*sl t phl 0.06 0.02 + 0.018*sl 0.03 + 0.014*sl 0.07 + 0.010*sl t r 0.30 0.29 + 0.004*sl 0.29 + 0.007*sl 0.29 + 0.006*sl t f 0.20 0.15 + 0.022*sl 0.16 + 0.018*sl 0.15 + 0.019*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.40 0.40 + 0.000*sl 0.40 + 0.000*sl 0.40 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.77 0.76 + 0.006*sl 0.76 + 0.005*sl 0.78 + 0.003*sl t phl 0.98 0.96 + 0.008*sl 0.97 + 0.006*sl 0.98 + 0.005*sl t r 0.53 0.53 + 0.000*sl 0.53 + 0.002*sl 0.51 + 0.003*sl t f 0.46 0.45 + 0.003*sl 0.45 + 0.006*sl 0.42 + 0.008*sl e to y t plh 0.76 0.75 + 0.006*sl 0.75 + 0.005*sl 0.77 + 0.003*sl t phl 0.04 0.02 + 0.009*sl 0.02 + 0.008*sl 0.05 + 0.005*sl t r 0.53 0.53 + 0.001*sl 0.53 + 0.002*sl 0.51 + 0.003*sl t f 0.18 0.15 + 0.013*sl 0.16 + 0.010*sl 0.16 + 0.009*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 1.34 1.34 + 0.000*sl 1.34 + 0.000*sl 1.34 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-163 STD80/stdm80 nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nit stdm80 nitd2 stdm80 nitd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.38 0.33 + 0.025*sl 0.34 + 0.021*sl 0.36 + 0.019*sl t phl 0.49 0.39 + 0.053*sl 0.39 + 0.051*sl 0.40 + 0.050*sl t r 0.23 0.16 + 0.037*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t f 0.34 0.15 + 0.095*sl 0.15 + 0.097*sl 0.14 + 0.099*sl e to y t plh 0.37 0.31 + 0.026*sl 0.33 + 0.021*sl 0.34 + 0.019*sl t phl 0.25 0.14 + 0.055*sl 0.15 + 0.051*sl 0.15 + 0.051*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t f 0.35 0.18 + 0.089*sl 0.16 + 0.095*sl 0.13 + 0.099*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.46 0.46 + 0.000*sl 0.46 + 0.000*sl 0.46 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.47 0.44 + 0.017*sl 0.45 + 0.014*sl 0.46 + 0.012*sl t phl 0.56 0.51 + 0.028*sl 0.51 + 0.027*sl 0.52 + 0.025*sl t r 0.25 0.21 + 0.019*sl 0.22 + 0.018*sl 0.22 + 0.018*sl t f 0.28 0.19 + 0.043*sl 0.18 + 0.047*sl 0.17 + 0.048*sl e to y t plh 0.46 0.43 + 0.017*sl 0.44 + 0.014*sl 0.45 + 0.012*sl t phl 0.18 0.12 + 0.032*sl 0.13 + 0.026*sl 0.14 + 0.026*sl t r 0.26 0.22 + 0.018*sl 0.22 + 0.018*sl 0.22 + 0.018*sl t f 0.26 0.17 + 0.043*sl 0.17 + 0.045*sl 0.15 + 0.048*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.68 0.68 + 0.000*sl 0.68 + 0.000*sl 0.68 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.65 0.63 + 0.012*sl 0.63 + 0.011*sl 0.64 + 0.009*sl t phl 0.80 0.76 + 0.016*sl 0.77 + 0.015*sl 0.77 + 0.014*sl t r 0.34 0.32 + 0.010*sl 0.32 + 0.010*sl 0.32 + 0.010*sl t f 0.32 0.28 + 0.022*sl 0.28 + 0.022*sl 0.27 + 0.023*sl e to y t plh 0.65 0.62 + 0.012*sl 0.63 + 0.010*sl 0.64 + 0.009*sl t phl 0.14 0.10 + 0.018*sl 0.11 + 0.015*sl 0.12 + 0.013*sl t r 0.34 0.32 + 0.010*sl 0.32 + 0.010*sl 0.32 + 0.010*sl t f 0.22 0.17 + 0.023*sl 0.17 + 0.023*sl 0.16 + 0.024*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 1.03 1.03 + 0.000*sl 1.03 + 0.000*sl 1.03 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-164 sec asic nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nitd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.05 1.03 + 0.007*sl 1.03 + 0.007*sl 1.04 + 0.007*sl t phl 1.30 1.28 + 0.010*sl 1.28 + 0.009*sl 1.29 + 0.008*sl t r 0.57 0.56 + 0.004*sl 0.56 + 0.005*sl 0.56 + 0.005*sl t f 0.51 0.49 + 0.009*sl 0.49 + 0.009*sl 0.49 + 0.010*sl e to y t plh 1.06 1.04 + 0.008*sl 1.05 + 0.007*sl 1.05 + 0.007*sl t phl 0.12 0.10 + 0.009*sl 0.10 + 0.009*sl 0.11 + 0.008*sl t r 0.57 0.56 + 0.004*sl 0.55 + 0.005*sl 0.56 + 0.005*sl t f 0.20 0.17 + 0.014*sl 0.18 + 0.011*sl 0.17 + 0.012*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 1.81 1.81 + 0.000*sl 1.81 + 0.000*sl 1.81 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-165 STD80/stdm80 nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nitn input load (sl) output load (sl) STD80 nitn nitnd2 nitnd4 nitnd8 nitn nitnd2 nitnd4 nitnd 8 aenaenaenaenyyyy 0.6 0.7 0.6 0.7 0.6 0.8 0.5 0.8 1.3 2.0 4.1 8.2 stdm80 nitn nitnd2 nitnd4 nitnd8 nitn nitnd2 nitnd4 nitnd 8 aenaenaenaenyyyy 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 1.4 2.2 4.5 9.0 STD80/stdm80 gate count nitn nitnd2 nitnd4 nitnd8 2.3 2.7 4.0 6.7 ay en path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.24 + 0.021*sl 0.25 + 0.015*sl 0.28 + 0.012*sl t phl 0.39 0.31 + 0.039*sl 0.31 + 0.039*sl 0.31 + 0.039*sl t r 0.18 0.13 + 0.023*sl 0.13 + 0.024*sl 0.10 + 0.027*sl t f 0.27 0.12 + 0.072*sl 0.12 + 0.076*sl 0.10 + 0.078*sl en to y t plh 0.40 0.36 + 0.021*sl 0.37 + 0.015*sl 0.40 + 0.012*sl t phl 0.32 0.23 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.039*sl t r 0.17 0.12 + 0.023*sl 0.12 + 0.025*sl 0.09 + 0.027*sl t f 0.26 0.11 + 0.074*sl 0.11 + 0.076*sl 0.09 + 0.078*sl t plz 0.21 0.21 + 0.001*sl 0.21 + 0.000*sl 0.21 + 0.000*sl t phz 0.40 0.40 + 0.000*sl 0.40 + 0.000*sl 0.40 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table aeny x 1 hi-z 000 101
STD80/stdm80 3-166 sec asic nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 nitnd2 STD80 nitnd4 STD80 nitnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.31 + 0.016*sl 0.33 + 0.010*sl 0.36 + 0.006*sl t phl 0.43 0.39 + 0.020*sl 0.40 + 0.019*sl 0.40 + 0.019*sl t r 0.21 0.18 + 0.012*sl 0.18 + 0.012*sl 0.17 + 0.013*sl t f 0.21 0.14 + 0.036*sl 0.14 + 0.036*sl 0.12 + 0.039*sl en to y t plh 0.48 0.45 + 0.014*sl 0.46 + 0.010*sl 0.50 + 0.006*sl t phl 0.28 0.24 + 0.024*sl 0.24 + 0.021*sl 0.26 + 0.019*sl t r 0.20 0.18 + 0.011*sl 0.18 + 0.012*sl 0.17 + 0.013*sl t f 0.19 0.14 + 0.027*sl 0.11 + 0.037*sl 0.10 + 0.039*sl t plz 0.23 0.23 + 0.000*sl 0.23 + 0.000*sl 0.23 + 0.000*sl t phz 0.56 0.56 + 0.001*sl 0.56 + 0.000*sl 0.57 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.48 0.47 + 0.008*sl 0.47 + 0.007*sl 0.50 + 0.004*sl t phl 0.60 0.58 + 0.012*sl 0.58 + 0.010*sl 0.59 + 0.009*sl t r 0.30 0.29 + 0.005*sl 0.29 + 0.006*sl 0.29 + 0.006*sl t f 0.27 0.24 + 0.016*sl 0.24 + 0.015*sl 0.21 + 0.019*sl en to y t plh 0.66 0.64 + 0.009*sl 0.65 + 0.007*sl 0.68 + 0.004*sl t phl 0.29 0.26 + 0.014*sl 0.26 + 0.012*sl 0.28 + 0.010*sl t r 0.30 0.29 + 0.005*sl 0.29 + 0.006*sl 0.29 + 0.006*sl t f 0.16 0.12 + 0.020*sl 0.13 + 0.019*sl 0.12 + 0.019*sl t plz 0.30 0.30 + 0.000*sl 0.30 + 0.000*sl 0.30 + 0.000*sl t phz 0.88 0.88 + 0.000*sl 0.88 + 0.000*sl 0.88 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.77 0.76 + 0.005*sl 0.76 + 0.005*sl 0.78 + 0.003*sl t phl 0.98 0.97 + 0.007*sl 0.97 + 0.007*sl 0.98 + 0.005*sl t r 0.53 0.53 + 0.001*sl 0.53 + 0.002*sl 0.51 + 0.003*sl t f 0.46 0.45 + 0.004*sl 0.45 + 0.006*sl 0.43 + 0.008*sl en to y t plh 1.04 1.03 + 0.006*sl 1.03 + 0.005*sl 1.05 + 0.003*sl t phl 0.32 0.30 + 0.008*sl 0.31 + 0.008*sl 0.33 + 0.005*sl t r 0.53 0.53 + 0.000*sl 0.53 + 0.002*sl 0.52 + 0.003*sl t f 0.16 0.14 + 0.010*sl 0.14 + 0.010*sl 0.15 + 0.010*sl t plz 0.42 0.42 + 0.001*sl 0.42 + 0.000*sl 0.42 + 0.000*sl t phz 1.53 1.53 + 0.000*sl 1.53 + 0.000*sl 1.54 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-167 STD80/stdm80 nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nitn stdm80 nitnd2 stdm80 nitnd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.37 0.32 + 0.027*sl 0.33 + 0.022*sl 0.35 + 0.019*sl t phl 0.50 0.40 + 0.054*sl 0.41 + 0.051*sl 0.41 + 0.050*sl t r 0.22 0.14 + 0.037*sl 0.15 + 0.035*sl 0.14 + 0.036*sl t f 0.36 0.17 + 0.095*sl 0.16 + 0.097*sl 0.15 + 0.099*sl en to y t plh 0.54 0.49 + 0.027*sl 0.51 + 0.022*sl 0.53 + 0.019*sl t phl 0.42 0.31 + 0.055*sl 0.32 + 0.052*sl 0.33 + 0.051*sl t r 0.22 0.14 + 0.036*sl 0.15 + 0.035*sl 0.14 + 0.036*sl t f 0.34 0.15 + 0.097*sl 0.14 + 0.098*sl 0.14 + 0.099*sl t plz 0.26 0.26 + 0.000*sl 0.26 + 0.000*sl 0.26 + 0.000*sl t phz 0.55 0.55 + 0.000*sl 0.55 + 0.000*sl 0.55 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.46 0.42 + 0.018*sl 0.43 + 0.014*sl 0.45 + 0.012*sl t phl 0.57 0.51 + 0.029*sl 0.51 + 0.027*sl 0.52 + 0.026*sl t r 0.24 0.20 + 0.018*sl 0.21 + 0.018*sl 0.21 + 0.018*sl t f 0.28 0.18 + 0.047*sl 0.18 + 0.048*sl 0.18 + 0.048*sl en to y t plh 0.66 0.62 + 0.018*sl 0.63 + 0.014*sl 0.65 + 0.012*sl t phl 0.38 0.32 + 0.030*sl 0.33 + 0.028*sl 0.34 + 0.026*sl t r 0.24 0.21 + 0.019*sl 0.21 + 0.018*sl 0.21 + 0.018*sl t f 0.24 0.15 + 0.049*sl 0.15 + 0.048*sl 0.14 + 0.049*sl t plz 0.29 0.29 + 0.000*sl 0.29 + 0.000*sl 0.29 + 0.000*sl t phz 0.76 0.76 + 0.000*sl 0.76 + 0.000*sl 0.76 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.65 0.62 + 0.012*sl 0.63 + 0.010*sl 0.64 + 0.009*sl t phl 0.79 0.76 + 0.016*sl 0.77 + 0.015*sl 0.77 + 0.014*sl t r 0.34 0.32 + 0.010*sl 0.32 + 0.010*sl 0.32 + 0.009*sl t f 0.32 0.28 + 0.021*sl 0.27 + 0.023*sl 0.27 + 0.023*sl en to y t plh 0.90 0.88 + 0.012*sl 0.89 + 0.010*sl 0.90 + 0.009*sl t phl 0.39 0.35 + 0.017*sl 0.36 + 0.016*sl 0.37 + 0.014*sl t r 0.34 0.32 + 0.010*sl 0.32 + 0.010*sl 0.32 + 0.010*sl t f 0.21 0.16 + 0.025*sl 0.16 + 0.025*sl 0.17 + 0.024*sl t plz 0.36 0.35 + 0.000*sl 0.35 + 0.000*sl 0.35 + 0.000*sl t phz 1.19 1.19 + 0.000*sl 1.19 + 0.000*sl 1.19 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-168 sec asic nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 nitnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.05 1.03 + 0.008*sl 1.04 + 0.007*sl 1.04 + 0.006*sl t phl 1.30 1.28 + 0.010*sl 1.28 + 0.009*sl 1.29 + 0.008*sl t r 0.56 0.55 + 0.005*sl 0.55 + 0.005*sl 0.55 + 0.005*sl t f 0.51 0.50 + 0.008*sl 0.49 + 0.009*sl 0.49 + 0.010*sl en to y t plh 1.43 1.42 + 0.007*sl 1.42 + 0.007*sl 1.43 + 0.006*sl t phl 0.45 0.43 + 0.011*sl 0.43 + 0.010*sl 0.44 + 0.009*sl t r 0.57 0.56 + 0.004*sl 0.56 + 0.005*sl 0.56 + 0.005*sl t f 0.22 0.19 + 0.014*sl 0.19 + 0.014*sl 0.20 + 0.013*sl t plz 0.50 0.50 + 0.000*sl 0.50 + 0.000*sl 0.50 + 0.000*sl t phz 2.07 2.07 + 0.001*sl 2.07 + 0.000*sl 2.07 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-169 STD80/stdm80 flip-flops cell list cell name function description fd1 d flip-flop fd1d2 d flip-flop with 2x drive fd1cs d flip-flop with scan clock fd1csd2 d flip-flop with scan clock, 2x drive fd1s d flip-flop with scan fd1sd2 d flip-flop with scan, 2x drive fd1q d flip-flop with q output only fd1qd2 d flip-flop with q output only, 2x drive fd1x2 2-bit d flip-flop fd1x4 4-bit d flip-flop yfd1 fast d flip-flop yfd1d2 fast d flip-flop with 2x drive fd2 d flip-flop with reset fd2d2 d flip-flop with reset, 2x drive fd2cs d flip-flop with reset, scan clock fd2csd2 d flip-flop with reset, scan clock, 2x drive fd2s d flip-flop with reset, scan fd2sd2 d flip-flop with reset, scan, 2x drive fd2q d flip-flop with reset, q output only fd2qd2 d flip-flop with reset, q output only, 2x drive fd2x2 2-bit d flip-flop with reset fd2x4 4-bit d flip-flop with reset yfd2 fast d flip-flop with reset yfd2d2 fast d flip-flop with reset, 2x drive fd2t d flip-flop with reset, tri-state output fd2td2 d flip-flop with reset, tri-state output, 2x drive fd2tcs d flip-flop with reset, scan clock, tri-state output fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 2x drive fd2ts d flip-flop with reset, scan, tri-state output fd2tsd2 d flip-flop with reset, scan, tri-state output, 2x drive fd3 d flip-flop with set fd3d2 d flip-flop with set, 2x drive fd3cs d flip-flop with set, scan clock fd3csd2 d flip-flop with set, scan clock, 2x drive
STD80/stdm80 3-170 sec asic fd3s d flip-flop with set, scan fd3sd2 d flip-flop with set, scan, 2x drive fd3q d flip-flop with set, q output only fd3qd2 d flip-flop with set, q output only, 2x drive fd3x2 2-bit d flip-flop with set fd3x4 4-bit d flip-flop with set yfd3 fast d flip-flop with set yfd3d2 fast d flip-flop with set, 2x drive fd4 d flip-flop with reset, set fd4d2 d flip-flop with reset, set, 2x drive fd4cs d flip-flop with reset, set, scan clock fd4csd2 d flip-flop with reset, set, scan clock, 2x drive fd4s d flip-flop with reset, set, scan fd4sd2 d flip-flop with reset, set, scan, 2x drive fd4q d flip-flop with reset, set, q output only fd4qd2 d flip-flop with reset, set, q output only, 2x drive fd4x2 2-bit d flip-flop with reset, set fd4x4 4-bit d flip-flop with reset, set yfd4 fast d flip-flop with reset, set yfd4d2 fast d flip-flop with reset, set, 2x drive fd5 d flip-flop with negative edge trigger fd5d2 d flip-flop with negative edge trigger, 2x drive fd5s d flip-flop with negative edge trigger, scan fd5sd2 d flip-flop with negative edge trigger, scan, 2x drive fd5x4 4-bit flip-flop with negative edge trigger fd6 d flip-flop with negative edge trigger, reset fd6d2 d flip-flop with negative edge trigger, reset, 2x drive fd6s d flip-flop with negative edge trigger, reset, scan fd6sd2 d flip-flop with negative edge trigger, reset, scan, 2x drive fd7 d flip-flop with negative edge trigger, set fd7d2 d flip-flop with negative edge trigger, set, 2x drive fd7s d flip-flop with negative edge trigger, set, scan fd7sd2 d flip-flop with negative edge trigger, set, scan, 2x drive fd8 d flip-flop with negative edge trigger, reset, set cell name function description flip-flops cell list (continued)
sec asic 3-171 STD80/stdm80 fd8d2 d flip-flop with negative edge trigger, reset, set, 2x drive fd8s d flip-flop with negative edge trigger, reset, set, scan fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 2x drive fds2 d flip-flop with synchronous clear fds2d2 d flip-flop with synchronous clear, 2x drive fds2cs d flip-flop with synchronous clear, scan clock fds2csd2 d flip-flop with synchronous clear, scan clock, 2x drive fds2s d flip-flop with synchronous clear, scan fds2sd2 d flip-flop with synchronous clear, scan, 2x drive fds3 d flip-flop with synchronous set fds3d2 d flip-flop with synchronous set, 2x drive fg1 d flip-flop with ck enable fg1x4 4-bit d flip-flop with ck enable fg2 d flip-flop with ck enable, reset fg2x4 4-bit d flip-flop with ck enable, reset fj1 jk flip-flop fj1d2 jk flip-flop with 2x drive fj1s jk flip-flop with scan fj1sd2 jk flip-flop with scan, 2x drive fj2 jk flip-flop with reset fj2d2 jk flip-flop with reset, 2x drive fj2s jk flip-flop with reset, scan fj2sd2 jk flip-flop with reset, scan, 2x drive fj4 jk flip-flop with reset, set fj4d2 jk flip-flop with reset, set, 2x drive fj4s jk flip-flop with reset, set, scan fj4sd2 jk flip-flop with reset, set, scan, 2x drive ft2 toggle flip-flop with reset ft2d2 toggle flip-flop with reset, 2x drive ft3 toggle flip-flop with set ft3d2 toggle flip-flop with set, 2x drive cell name function description flip-flops cell list (continued)
STD80/stdm80 3-172 sec asic fd1/fd1d2 d flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd1 fd1d2 fd1 fd1d2 dckdck 0.5 0.5 0.5 0.5 5.3 6.0 stdm80 fd1 fd1d2 fd1 fd1d2 dckdck 0.6 0.6 0.6 0.6 5.3 6.0 parameter symbol STD80 stdm80 fd1 fd1d2 fd1 fd1d2 pulse width low (ck) t pwl 0.87 0.87 0.87 0.87 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.46 0.46 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 d ck q qn d ck cl clb q cl clb clb cl clb cl cl clb qn truth table d ck q (n+1) qn (n+1) 001 110 x q (n) qn (n)
sec asic 3-173 STD80/stdm80 fd1/fd1d2 d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44, sl: standard load) STD80 fd1 STD80 fd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.52 + 0.028*sl 0.52 + 0.024*sl 0.53 + 0.024*sl t phl 0.66 0.57 + 0.042*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn t plh 0.70 0.65 + 0.024*sl 0.65 + 0.024*sl 0.65 + 0.024*sl t phl 0.74 0.66 + 0.038*sl 0.67 + 0.037*sl 0.67 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.54 + 0.018*sl 0.55 + 0.014*sl 0.57 + 0.012*sl t phl 0.65 0.60 + 0.023*sl 0.61 + 0.020*sl 0.62 + 0.018*sl t r 0.16 0.12 + 0.023*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl ck to qn t plh 0.76 0.73 + 0.013*sl 0.74 + 0.012*sl 0.74 + 0.012*sl t phl 0.80 0.76 + 0.018*sl 0.76 + 0.018*sl 0.76 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.033*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-174 sec asic fd1/fd1d2 d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40, sl: standard load) stdm80 fd1 stdm80 fd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.74 + 0.038*sl 0.75 + 0.035*sl 0.76 + 0.034*sl t phl 0.93 0.83 + 0.052*sl 0.84 + 0.046*sl 0.86 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ck to qn t plh 1.00 0.93 + 0.035*sl 0.93 + 0.033*sl 0.94 + 0.033*sl t phl 1.05 0.95 + 0.047*sl 0.96 + 0.045*sl 0.96 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.77 + 0.024*sl 0.79 + 0.020*sl 0.80 + 0.018*sl t phl 0.92 0.86 + 0.031*sl 0.87 + 0.026*sl 0.89 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl ck to qn t plh 1.09 1.05 + 0.019*sl 1.06 + 0.017*sl 1.06 + 0.017*sl t phl 1.12 1.07 + 0.026*sl 1.08 + 0.023*sl 1.09 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-175 STD80/stdm80 fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd1cs fd1csd2 fd1cs fd1csd2 si sck d ck si sck d ck 0.6 1.8 0.6 0.6 0.6 1.8 0.6 0.6 8.7 9.0 stdm80 fd1cs fd1csd2 fd1cs fd1csd2 si sck d ck si sck d ck 0.6 2.0 0.6 0.6 0.6 2.0 0.6 0.6 8.7 9.0 q qn si sck d ck cl clb q cl clb clb cl clb cl cl clb qn sck sckb sck sckb sckb sck sckb sck sck sck sckb d si ck truth table si sck d ck q (n+1) qn (n+1) x00 01 x01 10 0 x001 1 x010
STD80/stdm80 3-176 sec asic fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd1cs fd1csd2 fd1cs fd1csd2 pulse width low (ck) t pwl 0.87 0.87 0.87 0.87 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sck) t pwl 0.87 0.87 0.82 0.82 pulse width high (sck) t pwh 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.46 0.46 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (si to sck) t su 0.68 0.68 0.82 0.82 input hold time (si to sck) t hd 0.33 0.33 0.33 0.33
sec asic 3-177 STD80/stdm80 fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd1cs STD80 fd1csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.52 + 0.028*sl 0.53 + 0.024*sl 0.54 + 0.024*sl t phl 0.65 0.57 + 0.041*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.10 + 0.066*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sck to q t plh 0.65 0.59 + 0.029*sl 0.60 + 0.025*sl 0.61 + 0.024*sl t phl 0.59 0.50 + 0.042*sl 0.51 + 0.038*sl 0.52 + 0.037*sl t r 0.23 0.14 + 0.044*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.75 0.69 + 0.029*sl 0.70 + 0.025*sl 0.71 + 0.024*sl t phl 0.82 0.73 + 0.041*sl 0.74 + 0.038*sl 0.75 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.11 + 0.067*sl 0.09 + 0.069*sl sck to qn t plh 0.62 0.57 + 0.025*sl 0.57 + 0.023*sl 0.57 + 0.024*sl t phl 0.82 0.74 + 0.037*sl 0.74 + 0.037*sl 0.74 + 0.037*sl t r 0.19 0.09 + 0.048*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.068*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.59 0.55 + 0.018*sl 0.56 + 0.014*sl 0.58 + 0.012*sl t phl 0.65 0.60 + 0.023*sl 0.61 + 0.020*sl 0.62 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sck to q t plh 0.66 0.63 + 0.019*sl 0.64 + 0.014*sl 0.66 + 0.012*sl t phl 0.58 0.54 + 0.023*sl 0.55 + 0.020*sl 0.56 + 0.018*sl t r 0.19 0.15 + 0.020*sl 0.15 + 0.022*sl 0.11 + 0.026*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.031*sl 0.09 + 0.034*sl ck to qn t plh 0.82 0.78 + 0.017*sl 0.79 + 0.014*sl 0.81 + 0.012*sl t phl 0.87 0.83 + 0.021*sl 0.83 + 0.019*sl 0.84 + 0.018*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.022*sl 0.10 + 0.026*sl t f 0.19 0.13 + 0.030*sl 0.12 + 0.031*sl 0.10 + 0.034*sl sck to qn t plh 0.69 0.66 + 0.014*sl 0.67 + 0.012*sl 0.67 + 0.012*sl t phl 0.89 0.85 + 0.017*sl 0.85 + 0.017*sl 0.84 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-178 sec asic fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd1cs stdm80 fd1csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.83 0.75 + 0.038*sl 0.76 + 0.035*sl 0.77 + 0.034*sl t phl 0.92 0.82 + 0.052*sl 0.84 + 0.047*sl 0.85 + 0.045*sl t r 0.28 0.15 + 0.068*sl 0.14 + 0.070*sl 0.13 + 0.071*sl t f 0.31 0.14 + 0.081*sl 0.14 + 0.081*sl 0.14 + 0.082*sl sck to q t plh 0.98 0.90 + 0.041*sl 0.91 + 0.036*sl 0.93 + 0.034*sl t phl 0.82 0.72 + 0.053*sl 0.74 + 0.046*sl 0.75 + 0.044*sl t r 0.32 0.19 + 0.065*sl 0.18 + 0.067*sl 0.16 + 0.070*sl t f 0.32 0.16 + 0.078*sl 0.16 + 0.079*sl 0.14 + 0.081*sl ck to qn t plh 1.07 0.99 + 0.042*sl 1.01 + 0.036*sl 1.02 + 0.033*sl t phl 1.16 1.05 + 0.053*sl 1.07 + 0.048*sl 1.09 + 0.046*sl t r 0.30 0.17 + 0.069*sl 0.17 + 0.069*sl 0.15 + 0.070*sl t f 0.32 0.15 + 0.084*sl 0.16 + 0.082*sl 0.16 + 0.082*sl sck to qn t plh 0.89 0.82 + 0.034*sl 0.82 + 0.033*sl 0.82 + 0.033*sl t phl 1.21 1.11 + 0.046*sl 1.12 + 0.044*sl 1.12 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.071*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.84 0.79 + 0.024*sl 0.80 + 0.020*sl 0.82 + 0.018*sl t phl 0.92 0.86 + 0.030*sl 0.87 + 0.026*sl 0.89 + 0.023*sl t r 0.21 0.15 + 0.032*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.039*sl sck to q t plh 1.00 0.95 + 0.026*sl 0.97 + 0.021*sl 0.99 + 0.018*sl t phl 0.82 0.76 + 0.031*sl 0.77 + 0.026*sl 0.79 + 0.023*sl t r 0.25 0.18 + 0.032*sl 0.18 + 0.032*sl 0.18 + 0.033*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl ck to qn t plh 1.16 1.11 + 0.023*sl 1.12 + 0.020*sl 1.13 + 0.018*sl t phl 1.23 1.17 + 0.029*sl 1.18 + 0.025*sl 1.19 + 0.023*sl t r 0.23 0.16 + 0.037*sl 0.17 + 0.033*sl 0.17 + 0.033*sl t f 0.23 0.15 + 0.041*sl 0.15 + 0.040*sl 0.16 + 0.039*sl sck to qn t plh 0.98 0.95 + 0.018*sl 0.95 + 0.017*sl 0.95 + 0.017*sl t phl 1.31 1.26 + 0.024*sl 1.27 + 0.022*sl 1.27 + 0.021*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-179 STD80/stdm80 fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd1s fd1sd2 fd1s fd1sd2 d ti te ck d ti te ck 0.3 0.5 0.9 0.5 0.3 0.5 0.9 0.5 7.0 7.7 stdm80 fd1s fd1sd2 fd1s fd1sd2 d ti te ck d ti te ck 0.6 0.6 1.1 0.6 0.6 0.6 1.1 0.6 7.0 7.7 parameter symbol STD80 stdm80 fd1s fd1sd2 fd1s fd1sd2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.57 0.57 0.76 0.79 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.60 0.60 0.85 0.85 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.68 0.68 0.87 0.87 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 q qn d ti te ck d te ti cl clb q clb cl clb cl cl clb qn cl clb ck truth table dtiteck q (n+1) qn (n+1) 0x0 01 1x0 10 x01 01 x11 10
STD80/stdm80 3-180 sec asic fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd1s STD80 fd1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.53 + 0.028*sl 0.53 + 0.024*sl 0.54 + 0.024*sl t phl 0.68 0.59 + 0.042*sl 0.60 + 0.038*sl 0.61 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn t plh 0.71 0.66 + 0.025*sl 0.67 + 0.024*sl 0.67 + 0.024*sl t phl 0.75 0.67 + 0.038*sl 0.68 + 0.037*sl 0.68 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.59 0.55 + 0.018*sl 0.56 + 0.013*sl 0.58 + 0.012*sl t phl 0.66 0.62 + 0.023*sl 0.63 + 0.020*sl 0.64 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl ck to qn t plh 0.78 0.75 + 0.013*sl 0.75 + 0.012*sl 0.76 + 0.012*sl t phl 0.81 0.77 + 0.018*sl 0.77 + 0.018*sl 0.77 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-181 STD80/stdm80 fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd1s stdm80 fd1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.83 0.75 + 0.038*sl 0.77 + 0.035*sl 0.77 + 0.034*sl t phl 0.95 0.85 + 0.052*sl 0.86 + 0.046*sl 0.88 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ck to qn t plh 1.02 0.95 + 0.035*sl 0.96 + 0.033*sl 0.96 + 0.033*sl t phl 1.06 0.96 + 0.047*sl 0.97 + 0.045*sl 0.97 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.83 0.79 + 0.023*sl 0.80 + 0.020*sl 0.81 + 0.018*sl t phl 0.94 0.88 + 0.030*sl 0.89 + 0.026*sl 0.91 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.039*sl ck to qn t plh 1.11 1.07 + 0.018*sl 1.08 + 0.017*sl 1.08 + 0.017*sl t phl 1.13 1.08 + 0.025*sl 1.09 + 0.023*sl 1.10 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-182 sec asic fd1q/fd1qd2 d flip-flop with q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80/stdm80 fd1q fd1qd2 fd1q fd1qd2 dckdck 0.6 0.6 0.6 0.6 5.0 5.3 parameter symbol STD80 stdm80 fd1q fd1qd2 fd1q fd1qd2 pulse width low (ck) t pwl 0.87 0.87 0.87 0.87 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.46 0.00 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 d ck q d ck cl clb q cl clb clb cl clb cl cl clb truth table d ck q (n+1) 00 11 x q (n)
sec asic 3-183 STD80/stdm80 fd1q/fd1qd2 d flip-flop with q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd1q STD80 fd1qd2 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd1q stdm80 fd1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.51 + 0.028*sl 0.52 + 0.024*sl 0.52 + 0.024*sl t phl 0.65 0.57 + 0.040*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.54 + 0.018*sl 0.55 + 0.014*sl 0.56 + 0.012*sl t phl 0.64 0.59 + 0.023*sl 0.60 + 0.019*sl 0.61 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.17 0.10 + 0.034*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.74 + 0.038*sl 0.75 + 0.034*sl 0.76 + 0.033*sl t phl 0.91 0.81 + 0.051*sl 0.83 + 0.045*sl 0.83 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.078*sl 0.14 + 0.080*sl 0.12 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.77 + 0.024*sl 0.78 + 0.020*sl 0.80 + 0.018*sl t phl 0.90 0.84 + 0.031*sl 0.86 + 0.025*sl 0.88 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.038*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-184 sec asic fd1x2 2-bit d flip-flop logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd1x2 parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.90 1.07 pulse width high (ck) t pwh 0.90 0.82 input setup time (d0 to ck) t su 0.36 0.46 input hold time (d0 to ck) t hd 0.33 0.38 input setup time (d1 to ck) t su 0.36 0.46 input hold time (d1 to ck) t hd 0.33 0.38 q0 qn1 d0 d1 ck q1 qn0 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.65 0.59 + 0.028*sl 0.60 + 0.024*sl 0.61 + 0.024*sl t phl 0.81 0.72 + 0.042*sl 0.73 + 0.038*sl 0.74 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to q1 t plh 0.65 0.59 + 0.028*sl 0.60 + 0.025*sl 0.61 + 0.024*sl t phl 0.81 0.73 + 0.041*sl 0.73 + 0.038*sl 0.74 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn0 t plh 0.85 0.80 + 0.025*sl 0.80 + 0.024*sl 0.80 + 0.024*sl t phl 0.82 0.74 + 0.037*sl 0.74 + 0.037*sl 0.74 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ck to qn1 t plh 0.85 0.80 + 0.025*sl 0.80 + 0.024*sl 0.80 + 0.024*sl t phl 0.82 0.74 + 0.037*sl 0.74 + 0.037*sl 0.74 + 0.037*sl t r 0.18 0.09 + 0.048*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = truth table cell data dn ck qn (n+1) qnn (n+1) 001 110 x qn (n) qnn (n) input load (sl) gate count STD80 dn ck 9.7 0.5 0.5 stdm80 dn ck 9.7 0.6 0.6
sec asic 3-185 STD80/stdm80 fd1x2 2-bit d flip-flop switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd1x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.91 0.84 + 0.038*sl 0.85 + 0.035*sl 0.85 + 0.034*sl t phl 1.14 1.04 + 0.052*sl 1.05 + 0.046*sl 1.07 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ck to q1 t plh 0.91 0.83 + 0.038*sl 0.85 + 0.035*sl 0.85 + 0.034*sl t phl 1.14 1.04 + 0.052*sl 1.05 + 0.046*sl 1.06 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ck to qn0 t plh 1.21 1.14 + 0.035*sl 1.15 + 0.033*sl 1.15 + 0.033*sl t phl 1.14 1.05 + 0.047*sl 1.05 + 0.044*sl 1.05 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl ck to qn1 t plh 1.21 1.14 + 0.035*sl 1.14 + 0.033*sl 1.14 + 0.033*sl t phl 1.14 1.04 + 0.047*sl 1.05 + 0.045*sl 1.05 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.080*sl 0.11 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-186 sec asic fd1x4 4-bit d flip-flop logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.90 1.67 pulse width high (ck) t pwh 0.87 1.09 input setup time (d0 to ck) t su 0.33 0.36 input hold time (d0 to ck) t hd 0.66 0.63 input setup time (d1 to ck) t su 0.33 0.36 input hold time (d1 to ck) t hd 0.66 0.63 input setup time (d2 to ck) t su 0.33 0.36 input hold time (d2 to ck) t hd 0.66 0.63 input setup time (d3 to ck) t su 0.33 0.36 input hold time (d3 to ck) t hd 0.66 0.63 d0 d1 d2 d3 ck q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table cell data dn ck qn (n+1) qnn (n+1) 001 110 x qn (n) qnn (n) input load (sl) gate count STD80 dn ck 18.3 0.5 0.5 stdm80 dn ck 18.3 0.6 0.6
sec asic 3-187 STD80/stdm80 fd1x4 4-bit d flip-flop switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.79 0.74 + 0.028*sl 0.74 + 0.024*sl 0.75 + 0.024*sl t phl 1.08 1.00 + 0.041*sl 1.01 + 0.038*sl 1.01 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to q1 t plh 0.79 0.74 + 0.028*sl 0.74 + 0.024*sl 0.75 + 0.024*sl t phl 1.08 1.00 + 0.041*sl 1.01 + 0.038*sl 1.01 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to q2 t plh 0.79 0.74 + 0.028*sl 0.74 + 0.024*sl 0.75 + 0.024*sl t phl 1.08 1.00 + 0.041*sl 1.01 + 0.038*sl 1.01 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to q3 t plh 0.79 0.74 + 0.028*sl 0.74 + 0.024*sl 0.75 + 0.024*sl t phl 1.08 1.00 + 0.041*sl 1.01 + 0.038*sl 1.01 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn0 t plh 1.12 1.07 + 0.025*sl 1.07 + 0.024*sl 1.07 + 0.024*sl t phl 0.96 0.88 + 0.038*sl 0.88 + 0.037*sl 0.88 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ck to qn1 t plh 1.12 1.07 + 0.025*sl 1.07 + 0.024*sl 1.07 + 0.024*sl t phl 0.96 0.88 + 0.037*sl 0.88 + 0.037*sl 0.88 + 0.037*sl t r 0.19 0.10 + 0.043*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl ck to qn2 t plh 1.12 1.07 + 0.025*sl 1.07 + 0.024*sl 1.07 + 0.024*sl t phl 0.96 0.88 + 0.038*sl 0.88 + 0.037*sl 0.88 + 0.037*sl t r 0.19 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ck to qn3 t plh 1.12 1.07 + 0.025*sl 1.07 + 0.024*sl 1.07 + 0.024*sl t phl 0.96 0.88 + 0.038*sl 0.88 + 0.037*sl 0.88 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.068*sl 0.06 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-188 sec asic fd1x4 4-bit d flip-flop switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.08 1.00 + 0.038*sl 1.01 + 0.035*sl 1.02 + 0.034*sl t phl 1.53 1.43 + 0.052*sl 1.45 + 0.046*sl 1.46 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.078*sl 0.14 + 0.080*sl 0.13 + 0.081*sl ck to q1 t plh 1.08 1.00 + 0.038*sl 1.01 + 0.035*sl 1.02 + 0.034*sl t phl 1.53 1.43 + 0.052*sl 1.44 + 0.046*sl 1.46 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.082*sl ck to q2 t plh 1.08 1.00 + 0.038*sl 1.01 + 0.035*sl 1.02 + 0.034*sl t phl 1.53 1.43 + 0.052*sl 1.45 + 0.046*sl 1.46 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.082*sl ck to q3 t plh 1.08 1.00 + 0.038*sl 1.01 + 0.035*sl 1.02 + 0.033*sl t phl 1.53 1.43 + 0.052*sl 1.44 + 0.046*sl 1.46 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.15 + 0.079*sl 0.14 + 0.080*sl 0.13 + 0.081*sl ck to qn0 t plh 1.60 1.53 + 0.035*sl 1.54 + 0.033*sl 1.54 + 0.033*sl t phl 1.31 1.21 + 0.046*sl 1.22 + 0.045*sl 1.22 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl ck to qn1 t plh 1.60 1.53 + 0.035*sl 1.54 + 0.033*sl 1.54 + 0.033*sl t phl 1.31 1.21 + 0.047*sl 1.22 + 0.045*sl 1.22 + 0.044*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl ck to qn2 t plh 1.60 1.53 + 0.035*sl 1.54 + 0.033*sl 1.54 + 0.033*sl t phl 1.31 1.21 + 0.046*sl 1.22 + 0.045*sl 1.22 + 0.044*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl ck to qn3 t plh 1.60 1.53 + 0.035*sl 1.54 + 0.033*sl 1.53 + 0.033*sl t phl 1.30 1.21 + 0.047*sl 1.22 + 0.044*sl 1.22 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-189 STD80/stdm80 yfd1/yfd1d2 fast d flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 yfd1 yfd1d2 yfd1 yfd1d2 dckdck 1.7 0.5 1.7 0.5 4.0 5.0 stdm80 yfd1 yfd1d2 yfd1 yfd1d2 dckdck 2.0 0.6 2.0 0.6 4.0 5.0 parameter symbol STD80 stdm80 yfd1 yfd1d2 yfd1 yfd1d2 pulse width low (ck) t pwl 0.87 0.87 0.82 0.82 pulse width high (ck) t pwh 0.87 0.87 0.87 0.96 input setup time (d to ck) t su 0.38 0.38 0.41 0.38 input hold time (d to ck) t hd 0.46 0.46 0.49 0.49 d ck q qn d ck cl clb q cl clb clb cl clb cl cl clb qn truth table d ck q (n+1) qn (n+1) 001 110 x q (n) qn (n)
STD80/stdm80 3-190 sec asic yfd1/yfd1d2 fast d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44, sl: standard load) STD80 yfd1 STD80 yfd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.48 0.43 + 0.027*sl 0.44 + 0.025*sl 0.44 + 0.024*sl t phl 0.58 0.49 + 0.043*sl 0.50 + 0.039*sl 0.52 + 0.037*sl t r 0.26 0.17 + 0.044*sl 0.16 + 0.049*sl 0.13 + 0.052*sl t f 0.35 0.23 + 0.061*sl 0.22 + 0.065*sl 0.18 + 0.069*sl ck to qn t plh 0.71 0.55 + 0.081*sl 0.56 + 0.077*sl 0.57 + 0.075*sl t phl 0.66 0.51 + 0.075*sl 0.51 + 0.072*sl 0.52 + 0.072*sl t r 0.23 0.11 + 0.063*sl 0.10 + 0.064*sl 0.09 + 0.065*sl t f 0.24 0.08 + 0.076*sl 0.08 + 0.076*sl 0.08 + 0.076*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.50 0.47 + 0.017*sl 0.48 + 0.014*sl 0.49 + 0.012*sl t phl 0.62 0.57 + 0.025*sl 0.58 + 0.022*sl 0.61 + 0.018*sl t r 0.23 0.19 + 0.019*sl 0.18 + 0.023*sl 0.16 + 0.026*sl t f 0.34 0.28 + 0.029*sl 0.28 + 0.030*sl 0.24 + 0.033*sl ck to qn t plh 0.71 0.62 + 0.045*sl 0.63 + 0.041*sl 0.66 + 0.037*sl t phl 0.62 0.54 + 0.039*sl 0.54 + 0.037*sl 0.56 + 0.036*sl t r 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.10 + 0.032*sl t f 0.15 0.08 + 0.038*sl 0.08 + 0.037*sl 0.07 + 0.038*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-191 STD80/stdm80 yfd1/yfd1d2 fast d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40, sl: standard load) stdm80 yfd1 stdm80 yfd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.70 0.62 + 0.038*sl 0.63 + 0.035*sl 0.64 + 0.034*sl t phl 0.83 0.71 + 0.057*sl 0.73 + 0.050*sl 0.76 + 0.046*sl t r 0.36 0.22 + 0.066*sl 0.22 + 0.069*sl 0.20 + 0.071*sl t f 0.46 0.31 + 0.078*sl 0.30 + 0.079*sl 0.30 + 0.079*sl ck to qn t plh 1.02 0.80 + 0.112*sl 0.82 + 0.104*sl 0.85 + 0.101*sl t phl 0.93 0.73 + 0.100*sl 0.74 + 0.097*sl 0.74 + 0.096*sl t r 0.32 0.15 + 0.085*sl 0.15 + 0.085*sl 0.14 + 0.086*sl t f 0.30 0.12 + 0.094*sl 0.11 + 0.094*sl 0.11 + 0.095*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.72 0.67 + 0.022*sl 0.68 + 0.020*sl 0.69 + 0.018*sl t phl 0.91 0.84 + 0.034*sl 0.85 + 0.031*sl 0.88 + 0.027*sl t r 0.30 0.24 + 0.030*sl 0.23 + 0.033*sl 0.23 + 0.034*sl t f 0.45 0.38 + 0.037*sl 0.38 + 0.038*sl 0.38 + 0.038*sl ck to qn t plh 1.05 0.92 + 0.063*sl 0.94 + 0.058*sl 0.97 + 0.054*sl t phl 0.87 0.76 + 0.054*sl 0.78 + 0.050*sl 0.79 + 0.049*sl t r 0.22 0.14 + 0.041*sl 0.14 + 0.042*sl 0.14 + 0.042*sl t f 0.19 0.10 + 0.045*sl 0.10 + 0.046*sl 0.10 + 0.046*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-192 sec asic fd2/fd2d2 d flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd2 fd2d2 fd2 fd2d2 d ck rn d ck rn 0.5 0.5 0.7 0.5 0.5 0.7 6.3 7.0 stdm80 fd2 fd2d2 fd2 fd2d2 d ck rn d ck rn 0.6 0.6 1.4 0.6 0.6 1.4 6.3 7.0 parameter symbol STD80 stdm80 fd2 fd2d2 fd2 fd2d2 pulse width low (ck) t pwl 0.87 0.87 0.90 0.90 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.46 0.46 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76 d ck q qn rn d ck cl clb q cl clb cl clb cl cl clb qn clb rn rn rn rn truth table d ck rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
sec asic 3-193 STD80/stdm80 fd2/fd2d2 d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2 STD80 fd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.63 0.57 + 0.032*sl 0.58 + 0.026*sl 0.60 + 0.024*sl t phl 0.68 0.60 + 0.042*sl 0.61 + 0.038*sl 0.62 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.066*sl 0.08 + 0.069*sl rn to q t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.72 0.67 + 0.026*sl 0.68 + 0.024*sl 0.68 + 0.024*sl t phl 0.81 0.73 + 0.037*sl 0.73 + 0.037*sl 0.73 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.40 0.35 + 0.025*sl 0.36 + 0.024*sl 0.36 + 0.023*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.64 0.60 + 0.021*sl 0.61 + 0.016*sl 0.65 + 0.012*sl t phl 0.67 0.63 + 0.023*sl 0.63 + 0.020*sl 0.65 + 0.018*sl t r 0.20 0.14 + 0.026*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.11 + 0.031*sl 0.11 + 0.031*sl 0.09 + 0.034*sl rn to q t phl 0.36 0.31 + 0.023*sl 0.32 + 0.020*sl 0.33 + 0.018*sl t f 0.18 0.11 + 0.033*sl 0.11 + 0.031*sl 0.09 + 0.034*sl ck to qn t plh 0.79 0.76 + 0.014*sl 0.76 + 0.012*sl 0.77 + 0.012*sl t phl 0.89 0.85 + 0.017*sl 0.85 + 0.017*sl 0.84 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.47 0.44 + 0.015*sl 0.45 + 0.012*sl 0.45 + 0.012*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-194 sec asic fd2/fd2d2 d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2 stdm80 fd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.90 0.81 + 0.044*sl 0.83 + 0.037*sl 0.85 + 0.035*sl t phl 0.97 0.86 + 0.052*sl 0.88 + 0.046*sl 0.89 + 0.044*sl t r 0.32 0.18 + 0.071*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl rn to q t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ck to qn t plh 1.04 0.97 + 0.035*sl 0.98 + 0.033*sl 0.98 + 0.033*sl t phl 1.14 1.04 + 0.047*sl 1.05 + 0.044*sl 1.05 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn t plh 0.55 0.48 + 0.035*sl 0.48 + 0.033*sl 0.48 + 0.033*sl t r 0.26 0.12 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.91 0.86 + 0.028*sl 0.87 + 0.023*sl 0.90 + 0.019*sl t phl 0.96 0.89 + 0.031*sl 0.91 + 0.026*sl 0.93 + 0.023*sl t r 0.25 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl rn to q t phl 0.46 0.40 + 0.031*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t f 0.22 0.13 + 0.041*sl 0.14 + 0.039*sl 0.15 + 0.038*sl ck to qn t plh 1.13 1.09 + 0.019*sl 1.10 + 0.017*sl 1.10 + 0.017*sl t phl 1.25 1.20 + 0.024*sl 1.21 + 0.022*sl 1.21 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.63 0.60 + 0.019*sl 0.60 + 0.017*sl 0.61 + 0.017*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-195 STD80/stdm80 fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd2cs fd2csd2 fd2cs fd2csd2 si sck d ck rn si sck d ck rn 0.6 1.8 0.6 0.6 1.8 0.6 1.8 0.6 0.6 1.8 10.3 10.7 stdm80 fd2cs fd2csd2 fd2cs fd2csd2 si sck d ck rn si sck d ck rn 0.6 1.8 0.6 0.6 1.9 0.6 1.8 0.6 0.6 1.9 10.3 10.7 q qn si sck d ck rn d cl clb q cl clb cl cl clb qn clb sck sckb sck sckb sckb sck sckb sck si rn rn rn cl clb sck sck sckb ck rn rn truth table si sck d ck rn q (n+1) qn (n+1) x00 101 x01 110 0 x0101 1 x0110 xxxx001
STD80/stdm80 3-196 sec asic fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd2cs fd2csd2 fd2cs fd2csd2 pulse width low (ck) t pwl 0.87 0.87 0.90 0.90 pulse width high (ck) t pwh 0.87 0.97 0.82 0.85 pulse width low (sck) t pwl 0.87 0.87 0.82 0.82 pulse width high (sck) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.46 0.46 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (si to sck) t su 0.64 0.64 0.85 0.85 input hold time (si to sck) t hd 0.33 0.33 0.33 0.33 recovery time (rn to ck) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76 recovery time (rn to sck) t rc 0.33 0.33 0.33 0.33 input hold time (rn to sck) t hd 0.49 0.49 0.55 0.49
sec asic 3-197 STD80/stdm80 fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2cs STD80 fd2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.62 + 0.024*sl t phl 0.66 0.58 + 0.041*sl 0.59 + 0.038*sl 0.60 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.049*sl 0.11 + 0.052*sl t f 0.24 0.11 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sck to q t plh 0.74 0.67 + 0.033*sl 0.68 + 0.026*sl 0.71 + 0.024*sl t phl 0.59 0.51 + 0.042*sl 0.52 + 0.038*sl 0.53 + 0.037*sl t r 0.26 0.16 + 0.047*sl 0.16 + 0.047*sl 0.12 + 0.052*sl t f 0.25 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q t phl 0.38 0.30 + 0.040*sl 0.31 + 0.038*sl 0.32 + 0.037*sl t f 0.25 0.12 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.76 0.70 + 0.029*sl 0.71 + 0.025*sl 0.72 + 0.024*sl t phl 0.90 0.82 + 0.040*sl 0.83 + 0.038*sl 0.84 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.25 0.12 + 0.064*sl 0.12 + 0.067*sl 0.09 + 0.069*sl sck to qn t plh 0.62 0.58 + 0.024*sl 0.58 + 0.023*sl 0.58 + 0.024*sl t phl 0.91 0.84 + 0.037*sl 0.84 + 0.037*sl 0.84 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.22 0.10 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.49 0.43 + 0.029*sl 0.44 + 0.025*sl 0.45 + 0.024*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.63 + 0.021*sl 0.65 + 0.016*sl 0.68 + 0.012*sl t phl 0.66 0.62 + 0.023*sl 0.62 + 0.020*sl 0.64 + 0.018*sl t r 0.20 0.16 + 0.023*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sck to q t plh 0.77 0.72 + 0.022*sl 0.74 + 0.016*sl 0.77 + 0.012*sl t phl 0.59 0.55 + 0.023*sl 0.55 + 0.020*sl 0.57 + 0.018*sl t r 0.22 0.18 + 0.022*sl 0.18 + 0.023*sl 0.15 + 0.025*sl t f 0.18 0.12 + 0.032*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to q t phl 0.38 0.33 + 0.023*sl 0.34 + 0.020*sl 0.35 + 0.018*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.031*sl 0.09 + 0.034*sl ck to qn t plh 0.83 0.80 + 0.017*sl 0.80 + 0.014*sl 0.82 + 0.012*sl t phl 0.99 0.95 + 0.020*sl 0.96 + 0.018*sl 0.96 + 0.018*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.022*sl 0.11 + 0.026*sl t f 0.20 0.14 + 0.031*sl 0.14 + 0.031*sl 0.11 + 0.034*sl sck to qn t plh 0.70 0.67 + 0.013*sl 0.68 + 0.012*sl 0.68 + 0.012*sl t phl 1.01 0.98 + 0.016*sl 0.98 + 0.017*sl 0.97 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.11 + 0.022*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.55 0.51 + 0.017*sl 0.52 + 0.014*sl 0.54 + 0.012*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.023*sl 0.10 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-198 sec asic fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2cs stdm80 fd2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.94 0.85 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.035*sl t phl 0.94 0.84 + 0.051*sl 0.85 + 0.047*sl 0.87 + 0.045*sl t r 0.32 0.18 + 0.069*sl 0.18 + 0.069*sl 0.18 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.14 + 0.082*sl sck to q t plh 1.11 1.02 + 0.045*sl 1.04 + 0.038*sl 1.07 + 0.035*sl t phl 0.83 0.73 + 0.053*sl 0.75 + 0.047*sl 0.76 + 0.044*sl t r 0.35 0.21 + 0.069*sl 0.22 + 0.067*sl 0.20 + 0.069*sl t f 0.32 0.16 + 0.079*sl 0.16 + 0.079*sl 0.14 + 0.081*sl rn to q t phl 0.50 0.39 + 0.052*sl 0.41 + 0.047*sl 0.42 + 0.045*sl t f 0.31 0.15 + 0.081*sl 0.15 + 0.081*sl 0.14 + 0.081*sl ck to qn t plh 1.09 1.01 + 0.042*sl 1.02 + 0.036*sl 1.04 + 0.034*sl t phl 1.29 1.18 + 0.052*sl 1.20 + 0.048*sl 1.21 + 0.046*sl t r 0.30 0.16 + 0.070*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.33 0.16 + 0.084*sl 0.17 + 0.082*sl 0.17 + 0.081*sl sck to qn t plh 0.90 0.83 + 0.034*sl 0.83 + 0.033*sl 0.83 + 0.033*sl t phl 1.35 1.25 + 0.046*sl 1.26 + 0.044*sl 1.26 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.071*sl 0.11 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.13 + 0.081*sl 0.11 + 0.082*sl rn to qn t plh 0.65 0.56 + 0.042*sl 0.58 + 0.036*sl 0.60 + 0.033*sl t r 0.30 0.16 + 0.070*sl 0.17 + 0.068*sl 0.16 + 0.070*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.97 0.92 + 0.028*sl 0.93 + 0.023*sl 0.96 + 0.020*sl t phl 0.94 0.88 + 0.031*sl 0.89 + 0.026*sl 0.91 + 0.023*sl t r 0.26 0.19 + 0.035*sl 0.19 + 0.034*sl 0.19 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.039*sl sck to q t plh 1.16 1.10 + 0.029*sl 1.12 + 0.023*sl 1.14 + 0.020*sl t phl 0.84 0.77 + 0.031*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.29 0.22 + 0.034*sl 0.22 + 0.034*sl 0.22 + 0.033*sl t f 0.23 0.15 + 0.039*sl 0.15 + 0.039*sl 0.15 + 0.038*sl rn to q t phl 0.49 0.42 + 0.031*sl 0.44 + 0.026*sl 0.46 + 0.023*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.039*sl 0.15 + 0.038*sl ck to qn t plh 1.18 1.13 + 0.023*sl 1.14 + 0.020*sl 1.16 + 0.018*sl t phl 1.41 1.36 + 0.027*sl 1.37 + 0.024*sl 1.37 + 0.023*sl t r 0.23 0.16 + 0.035*sl 0.17 + 0.033*sl 0.17 + 0.033*sl t f 0.24 0.16 + 0.042*sl 0.17 + 0.040*sl 0.18 + 0.038*sl sck to qn t plh 1.00 0.96 + 0.018*sl 0.97 + 0.017*sl 0.97 + 0.017*sl t phl 1.49 1.45 + 0.022*sl 1.45 + 0.021*sl 1.45 + 0.021*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.73 0.69 + 0.023*sl 0.69 + 0.020*sl 0.71 + 0.018*sl t r 0.23 0.16 + 0.037*sl 0.17 + 0.033*sl 0.17 + 0.033*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-199 STD80/stdm80 fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd2s fd2sd2 fd2s fd2sd2 d ti te ck rn d ti te ck rn 0.3 0.5 0.9 0.5 0.7 0.3 0.5 0.9 0.5 0.7 8.0 8.7 stdm80 fd2s fd2sd2 fd2s fd2sd2 d ti te ck rn d ti te ck rn 0.6 0.6 1.1 0.6 1.4 0.6 0.6 1.1 0.6 1.4 8.0 8.7 q qn d ti te ck rn ck cl clb q cl clb cl clb cl cl clb qn clb rn rn rn rn d te ti truth table dtiteckrn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx001
STD80/stdm80 3-200 sec asic fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2s STD80 fd2sd2 parameter symbol STD80 stdm80 fd2s fd2sd2 fd2s fd2sd2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.60 0.60 0.79 0.79 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.63 0.63 0.85 0.85 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.68 0.68 0.90 0.90 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.64 0.58 + 0.032*sl 0.59 + 0.026*sl 0.61 + 0.024*sl t phl 0.70 0.62 + 0.042*sl 0.63 + 0.038*sl 0.63 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl rn to q t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.74 0.69 + 0.025*sl 0.70 + 0.024*sl 0.69 + 0.024*sl t phl 0.82 0.74 + 0.037*sl 0.74 + 0.037*sl 0.74 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.40 0.35 + 0.025*sl 0.36 + 0.024*sl 0.36 + 0.023*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.61 + 0.021*sl 0.62 + 0.015*sl 0.66 + 0.012*sl t phl 0.69 0.65 + 0.023*sl 0.65 + 0.020*sl 0.67 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to q t phl 0.36 0.31 + 0.023*sl 0.32 + 0.020*sl 0.33 + 0.018*sl t f 0.18 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl ck to qn t plh 0.81 0.78 + 0.014*sl 0.78 + 0.012*sl 0.79 + 0.012*sl t phl 0.90 0.86 + 0.018*sl 0.87 + 0.017*sl 0.86 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.47 0.44 + 0.015*sl 0.45 + 0.012*sl 0.45 + 0.012*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-201 STD80/stdm80 fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2s stdm80 fd2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.91 0.83 + 0.044*sl 0.84 + 0.038*sl 0.87 + 0.035*sl t phl 0.99 0.89 + 0.052*sl 0.91 + 0.046*sl 0.92 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.081*sl rn to q t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ck to qn t plh 1.07 1.00 + 0.035*sl 1.00 + 0.033*sl 1.00 + 0.033*sl t phl 1.15 1.06 + 0.047*sl 1.07 + 0.044*sl 1.07 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn t plh 0.55 0.48 + 0.035*sl 0.48 + 0.033*sl 0.48 + 0.033*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.87 + 0.028*sl 0.89 + 0.023*sl 0.91 + 0.020*sl t phl 0.98 0.92 + 0.031*sl 0.93 + 0.026*sl 0.95 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl rn to q t phl 0.46 0.40 + 0.031*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t f 0.22 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl ck to qn t plh 1.15 1.12 + 0.019*sl 1.12 + 0.017*sl 1.13 + 0.017*sl t phl 1.26 1.21 + 0.024*sl 1.22 + 0.022*sl 1.22 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.22 0.13 + 0.041*sl 0.15 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.63 0.60 + 0.019*sl 0.60 + 0.017*sl 0.61 + 0.017*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-202 sec asic fd2q/fd2qd2 d flip-flop with reset, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd2q fd2qd2 fd2q fd2qd2 d ck rn d ck rn 0.6 0.6 1.1 0.6 0.6 1.1 6.0 6.3 stdm80 fd2q fd2qd2 fd2q fd2qd2 d ck rn d ck rn 0.6 0.6 1.2 0.6 0.6 1.2 6.0 6.3 parameter symbol STD80 stdm80 fd2q fd2qd2 fd2q fd2qd2 pulse width low (ck) t pwl 0.87 0.87 0.90 0.90 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.46 0.46 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76 d ck q rn d ck cl clb q cl clb cl clb cl cl clb clb rn rn rn rn truth table d ck rn q (n+1) 010 111 xx00 x x q (n)
sec asic 3-203 STD80/stdm80 fd2q/fd2qd2 d flip-flop with reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2q STD80 fd2qd2 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2q stdm80 fd2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.62 0.56 + 0.031*sl 0.57 + 0.026*sl 0.59 + 0.024*sl t phl 0.67 0.59 + 0.041*sl 0.60 + 0.037*sl 0.60 + 0.037*sl t r 0.22 0.13 + 0.048*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to q t phl 0.36 0.28 + 0.040*sl 0.28 + 0.037*sl 0.29 + 0.037*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.64 0.60 + 0.020*sl 0.61 + 0.015*sl 0.64 + 0.012*sl t phl 0.66 0.62 + 0.023*sl 0.63 + 0.019*sl 0.64 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.12 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl rn to q t phl 0.35 0.30 + 0.023*sl 0.31 + 0.019*sl 0.33 + 0.018*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.90 0.81 + 0.043*sl 0.83 + 0.037*sl 0.85 + 0.034*sl t phl 0.95 0.85 + 0.051*sl 0.86 + 0.046*sl 0.88 + 0.044*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.078*sl 0.14 + 0.080*sl 0.13 + 0.082*sl rn to q t phl 0.46 0.36 + 0.050*sl 0.37 + 0.046*sl 0.38 + 0.045*sl t f 0.30 0.14 + 0.079*sl 0.13 + 0.081*sl 0.13 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.91 0.86 + 0.027*sl 0.87 + 0.023*sl 0.89 + 0.019*sl t phl 0.94 0.88 + 0.031*sl 0.90 + 0.026*sl 0.92 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.18 + 0.035*sl 0.19 + 0.034*sl t f 0.22 0.14 + 0.039*sl 0.15 + 0.038*sl 0.14 + 0.038*sl rn to q t phl 0.45 0.39 + 0.031*sl 0.40 + 0.026*sl 0.42 + 0.023*sl t f 0.21 0.13 + 0.039*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-204 sec asic fd2x2 2-bit d flip-flop with reset logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.87 1.09 pulse width high (ck) t pwh 0.96 0.85 pulse width low (rn) t pwl 0.87 0.82 input setup time (d0 to ck) t su 0.36 0.46 input hold time (d0 to ck) t hd 0.41 0.41 input setup time (d1 to ck) t su 0.36 0.46 input hold time (d1 to ck) t hd 0.41 0.41 recovery time (rn) t rc 0.33 0.33 input hold time (rn to ck) t hd 0.76 0.87 q0 qn1 d0 d1 ck q1 qn0 rn truth table cell data dn ck rn qn (n+1) qnn (n+1) 0101 1110 xx0 0 1 x 1 qn (n) qnn (n) input load (sl) gate count STD80 dn ck rn 11.7 0.5 0.5 1.5 stdm80 dn ck rn 11.7 0.6 0.6 2.4
sec asic 3-205 STD80/stdm80 fd2x2 2-bit d flip-flop with reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.72 0.65 + 0.032*sl 0.66 + 0.026*sl 0.69 + 0.024*sl t phl 0.85 0.77 + 0.041*sl 0.78 + 0.038*sl 0.78 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q0 t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to q1 t plh 0.71 0.65 + 0.032*sl 0.66 + 0.026*sl 0.68 + 0.024*sl t phl 0.85 0.77 + 0.042*sl 0.78 + 0.038*sl 0.78 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q1 t phl 0.37 0.28 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn0 t plh 0.89 0.84 + 0.025*sl 0.85 + 0.023*sl 0.84 + 0.024*sl t phl 0.89 0.82 + 0.037*sl 0.82 + 0.037*sl 0.82 + 0.037*sl t r 0.19 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn0 t plh 0.41 0.36 + 0.025*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.19 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl ck to qn1 t plh 0.89 0.84 + 0.025*sl 0.84 + 0.024*sl 0.84 + 0.024*sl t phl 0.89 0.82 + 0.037*sl 0.82 + 0.037*sl 0.81 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn1 t plh 0.41 0.35 + 0.026*sl 0.36 + 0.023*sl 0.36 + 0.023*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-206 sec asic fd2x2 2-bit d flip-flop with reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.00 0.92 + 0.044*sl 0.94 + 0.038*sl 0.96 + 0.035*sl t phl 1.20 1.10 + 0.052*sl 1.12 + 0.046*sl 1.13 + 0.044*sl t r 0.32 0.18 + 0.071*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to q0 t phl 0.48 0.37 + 0.052*sl 0.39 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.14 + 0.081*sl ck to q1 t plh 1.00 0.91 + 0.044*sl 0.93 + 0.038*sl 0.95 + 0.035*sl t phl 1.20 1.10 + 0.052*sl 1.11 + 0.046*sl 1.13 + 0.045*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to q1 t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ck to qn0 t plh 1.28 1.21 + 0.035*sl 1.22 + 0.033*sl 1.22 + 0.033*sl t phl 1.25 1.15 + 0.046*sl 1.16 + 0.045*sl 1.16 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.14 + 0.076*sl 0.13 + 0.080*sl 0.11 + 0.082*sl rn to qn0 t plh 0.56 0.48 + 0.035*sl 0.49 + 0.033*sl 0.49 + 0.033*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl ck to qn1 t plh 1.27 1.21 + 0.035*sl 1.21 + 0.033*sl 1.21 + 0.033*sl t phl 1.24 1.14 + 0.047*sl 1.15 + 0.045*sl 1.15 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn1 t plh 0.55 0.48 + 0.035*sl 0.48 + 0.033*sl 0.48 + 0.033*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-207 STD80/stdm80 fd2x4 4-bit d flip-flop with reset logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.87 1.80 pulse width high (ck) t pwh 0.87 1.15 pulse width low (rn) t pwl 0.87 0.82 input setup time (d0 to ck) t su 0.33 0.36 input hold time (d0 to ck) t hd 0.63 0.68 input setup time (d1 to ck) t su 0.33 0.36 input hold time (d1 to ck) t hd 0.63 0.68 input setup time (d2 to ck) t su 0.33 0.36 input hold time (d2 to ck) t hd 0.63 0.68 input setup time (d3 to ck) t su 0.33 0.36 input hold time (d3 to ck) t hd 0.63 0.68 recovery time (rn) t rc 0.33 0.33 input hold time (rn to ck) t hd 0.93 1.04 d0 d1 d2 d3 ck q0 q1 q2 q3 qn0 qn1 qn2 qn3 rn truth table cell data dn ck rn qn (n+1) qnn (n+1) 0101 1110 xx0 0 1 x 1 qn (n) qnn (n) input load (sl) gate count STD80 dn ck rn 22.3 0.5 0.5 3.0 stdm80 dn ck rn 22.3 0.6 0.6 5.1
STD80/stdm80 3-208 sec asic fd2x4 4-bit d flip-flop with reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.87 0.81 + 0.032*sl 0.82 + 0.026*sl 0.84 + 0.024*sl t phl 1.15 1.07 + 0.041*sl 1.07 + 0.038*sl 1.08 + 0.037*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q0 t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to q1 t plh 0.87 0.81 + 0.032*sl 0.82 + 0.026*sl 0.84 + 0.024*sl t phl 1.15 1.07 + 0.041*sl 1.07 + 0.038*sl 1.08 + 0.037*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q1 t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.062*sl 0.11 + 0.067*sl 0.08 + 0.069*sl ck to q2 t plh 0.87 0.81 + 0.032*sl 0.82 + 0.026*sl 0.84 + 0.024*sl t phl 1.15 1.07 + 0.041*sl 1.07 + 0.038*sl 1.08 + 0.037*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q2 t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to q3 t plh 0.87 0.80 + 0.032*sl 0.81 + 0.026*sl 0.84 + 0.024*sl t phl 1.15 1.06 + 0.041*sl 1.07 + 0.038*sl 1.08 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q3 t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn0 t plh 1.19 1.14 + 0.026*sl 1.14 + 0.023*sl 1.14 + 0.024*sl t phl 1.04 0.97 + 0.037*sl 0.97 + 0.037*sl 0.96 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn0 t plh 0.41 0.36 + 0.025*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.19 0.10 + 0.046*sl 0.09 + 0.049*sl 0.06 + 0.052*sl ck to qn1 t plh 1.19 1.14 + 0.026*sl 1.14 + 0.024*sl 1.14 + 0.024*sl t phl 1.04 0.97 + 0.037*sl 0.97 + 0.037*sl 0.97 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn1 t plh 0.41 0.36 + 0.024*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.19 0.10 + 0.046*sl 0.09 + 0.049*sl 0.06 + 0.052*sl ck to qn2 t plh 1.19 1.14 + 0.026*sl 1.14 + 0.023*sl 1.14 + 0.024*sl t phl 1.04 0.97 + 0.036*sl 0.97 + 0.037*sl 0.96 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-209 STD80/stdm80 fd2x4 4-bit d flip-flop with reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.19 1.10 + 0.044*sl 1.12 + 0.038*sl 1.14 + 0.035*sl t phl 1.63 1.53 + 0.052*sl 1.55 + 0.046*sl 1.56 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q0 t phl 0.48 0.37 + 0.052*sl 0.39 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ck to q1 t plh 1.19 1.10 + 0.044*sl 1.12 + 0.038*sl 1.14 + 0.035*sl t phl 1.63 1.53 + 0.052*sl 1.54 + 0.047*sl 1.56 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q1 t phl 0.48 0.37 + 0.052*sl 0.39 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ck to q2 t plh 1.19 1.10 + 0.044*sl 1.12 + 0.038*sl 1.14 + 0.035*sl t phl 1.63 1.53 + 0.052*sl 1.55 + 0.046*sl 1.56 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q2 t phl 0.48 0.37 + 0.052*sl 0.39 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ck to q3 t plh 1.18 1.09 + 0.044*sl 1.11 + 0.038*sl 1.13 + 0.035*sl t phl 1.63 1.52 + 0.052*sl 1.54 + 0.046*sl 1.55 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.18 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to q3 t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.14 + 0.081*sl ck to qn0 t plh 1.71 1.64 + 0.035*sl 1.64 + 0.033*sl 1.64 + 0.033*sl t phl 1.42 1.33 + 0.047*sl 1.34 + 0.044*sl 1.34 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.13 + 0.080*sl 0.11 + 0.082*sl rn to qn0 t plh 0.56 0.49 + 0.035*sl 0.49 + 0.033*sl 0.49 + 0.033*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.070*sl 0.10 + 0.072*sl ck to qn1 t plh 1.71 1.64 + 0.035*sl 1.64 + 0.034*sl 1.64 + 0.033*sl t phl 1.42 1.33 + 0.047*sl 1.34 + 0.044*sl 1.34 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.13 + 0.080*sl 0.11 + 0.082*sl rn to qn1 t plh 0.56 0.49 + 0.035*sl 0.49 + 0.033*sl 0.49 + 0.033*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl ck to qn2 t plh 1.71 1.64 + 0.035*sl 1.64 + 0.033*sl 1.64 + 0.033*sl t phl 1.42 1.33 + 0.047*sl 1.34 + 0.044*sl 1.34 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.13 + 0.080*sl 0.11 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-210 sec asic yfd2/yfd2d2 fast d flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 yfd2 yfd2d2 yfd2 yfd2d2 d ck rn d ck rn 1.7 0.5 1.2 1.7 0.5 2.2 5.3 6.3 stdm80 yfd2 yfd2d2 yfd2 yfd2d2 d ck rn d ck rn 0.5 0.6 1.3 1.9 0.6 2.4 5.3 6.3 parameter symbol STD80 stdm80 yfd2 yfd2d2 yfd2 yfd2d2 pulse width low (ck) t pwl 0.87 0.87 0.85 0.85 pulse width high (ck) t pwh 0.87 0.87 0.87 0.96 pulse width low (rn) t pwl 0.87 0.87 1.01 1.15 input setup time (d to ck) t su 0.38 0.38 0.46 0.44 input hold time (d to ck) t hd 0.46 0.46 0.49 0.49 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.38 0.38 0.44 0.44 d ck q qn rn d ck cl clb q cl clb cl clb cl cl clb qn clb rn rn rn rn truth table d ck rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
sec asic 3-211 STD80/stdm80 yfd2/yfd2d2 fast d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 yfd2 STD80 yfd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.53 0.47 + 0.030*sl 0.47 + 0.026*sl 0.50 + 0.024*sl t phl 0.59 0.50 + 0.044*sl 0.51 + 0.039*sl 0.53 + 0.037*sl t r 0.29 0.20 + 0.047*sl 0.19 + 0.049*sl 0.16 + 0.052*sl t f 0.35 0.22 + 0.064*sl 0.22 + 0.065*sl 0.19 + 0.069*sl rn to q t phl 0.61 0.53 + 0.042*sl 0.54 + 0.038*sl 0.55 + 0.037*sl t f 0.37 0.25 + 0.058*sl 0.24 + 0.063*sl 0.18 + 0.069*sl ck to qn t plh 0.75 0.58 + 0.083*sl 0.59 + 0.079*sl 0.61 + 0.077*sl t phl 0.71 0.56 + 0.074*sl 0.57 + 0.069*sl 0.60 + 0.067*sl t r 0.28 0.15 + 0.065*sl 0.15 + 0.067*sl 0.14 + 0.067*sl t f 0.29 0.13 + 0.081*sl 0.13 + 0.081*sl 0.13 + 0.082*sl rn to qn t plh 0.17 0.10 + 0.034*sl 0.12 + 0.025*sl 0.13 + 0.024*sl t r 0.30 0.21 + 0.041*sl 0.20 + 0.045*sl 0.21 + 0.044*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.55 0.51 + 0.019*sl 0.52 + 0.016*sl 0.56 + 0.012*sl t phl 0.63 0.58 + 0.025*sl 0.59 + 0.022*sl 0.62 + 0.018*sl t r 0.27 0.23 + 0.021*sl 0.22 + 0.024*sl 0.21 + 0.026*sl t f 0.34 0.29 + 0.028*sl 0.28 + 0.030*sl 0.25 + 0.033*sl rn to q t phl 0.65 0.60 + 0.023*sl 0.61 + 0.021*sl 0.63 + 0.018*sl t f 0.34 0.28 + 0.028*sl 0.28 + 0.028*sl 0.23 + 0.033*sl ck to qn t plh 0.75 0.66 + 0.045*sl 0.66 + 0.041*sl 0.69 + 0.038*sl t phl 0.69 0.60 + 0.042*sl 0.61 + 0.038*sl 0.64 + 0.035*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.14 0.10 + 0.019*sl 0.11 + 0.015*sl 0.14 + 0.012*sl t r 0.26 0.21 + 0.023*sl 0.21 + 0.022*sl 0.21 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-212 sec asic yfd2/yfd2d2 fast d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 yfd2 stdm80 yfd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.76 0.67 + 0.043*sl 0.69 + 0.038*sl 0.71 + 0.035*sl t phl 0.83 0.71 + 0.058*sl 0.74 + 0.051*sl 0.76 + 0.047*sl t r 0.40 0.26 + 0.070*sl 0.26 + 0.069*sl 0.26 + 0.070*sl t f 0.47 0.30 + 0.081*sl 0.31 + 0.080*sl 0.31 + 0.080*sl rn to q t phl 0.86 0.75 + 0.056*sl 0.77 + 0.049*sl 0.80 + 0.045*sl t f 0.49 0.35 + 0.071*sl 0.34 + 0.074*sl 0.32 + 0.078*sl ck to qn t plh 1.08 0.85 + 0.114*sl 0.87 + 0.107*sl 0.90 + 0.103*sl t phl 1.02 0.82 + 0.101*sl 0.83 + 0.096*sl 0.85 + 0.093*sl t r 0.38 0.20 + 0.088*sl 0.21 + 0.088*sl 0.20 + 0.089*sl t f 0.39 0.18 + 0.105*sl 0.18 + 0.105*sl 0.18 + 0.105*sl rn to qn t plh 0.22 0.15 + 0.038*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t r 0.34 0.21 + 0.065*sl 0.19 + 0.071*sl 0.19 + 0.070*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.79 0.74 + 0.025*sl 0.75 + 0.023*sl 0.77 + 0.020*sl t phl 0.92 0.85 + 0.035*sl 0.86 + 0.031*sl 0.89 + 0.027*sl t r 0.35 0.28 + 0.034*sl 0.28 + 0.035*sl 0.28 + 0.034*sl t f 0.46 0.38 + 0.039*sl 0.38 + 0.039*sl 0.38 + 0.038*sl rn to q t phl 0.92 0.85 + 0.033*sl 0.87 + 0.029*sl 0.89 + 0.026*sl t f 0.46 0.39 + 0.036*sl 0.39 + 0.034*sl 0.39 + 0.035*sl ck to qn t plh 1.10 0.97 + 0.064*sl 0.99 + 0.059*sl 1.01 + 0.055*sl t phl 0.99 0.87 + 0.057*sl 0.88 + 0.053*sl 0.90 + 0.051*sl t r 0.27 0.18 + 0.043*sl 0.18 + 0.043*sl 0.18 + 0.043*sl t f 0.27 0.16 + 0.054*sl 0.16 + 0.053*sl 0.16 + 0.053*sl rn to qn t plh 0.18 0.14 + 0.022*sl 0.15 + 0.018*sl 0.16 + 0.017*sl t r 0.27 0.21 + 0.029*sl 0.20 + 0.033*sl 0.18 + 0.035*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-213 STD80/stdm80 fd2t/fd2td2 d flip-flop with reset, tri-state output, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) output load (sl) gate count STD80 fd2t fd2td2 fd2t fd2td2 fd2t fd2td2 d rd ck rn d rd ck rn z z 0.6 1.1 0.6 1.1 0.6 1.2 0.6 1.1 1.3 2.2 7.3 8.3 stdm80 fd2t fd2td2 fd2t fd2td2 fd2t fd2td2 d rd ck rn d rd ck rn z z 0.6 0.9 0.6 1.2 0.6 1.3 0.6 1.2 1.4 2.5 7.3 8.3 parameter symbol STD80 stdm80 fd2t fd2td2 fd2t fd2td2 pulse width low (ck) t pwl 0.87 0.87 0.90 0.90 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.85 input setup time (d to ck) t su 0.46 0.46 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76 d ck rd q z rn q z d ck cl clb cl clb cl clb cl cl clb clb rn rn rn rn rd truth table * rd is a tri-state enable pin. d rd* ck rn q (n+1) z (n+1) 01 100 11 111 x1x000 x 0 x 1 x hi-z x 1 1 q (n) z (n)
STD80/stdm80 3-214 sec asic fd2t/fd2td2 d flip-flop with reset, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2t STD80 fd2td2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.62 + 0.032*sl 0.63 + 0.026*sl 0.66 + 0.024*sl t phl 0.73 0.65 + 0.040*sl 0.65 + 0.037*sl 0.66 + 0.037*sl t r 0.28 0.18 + 0.048*sl 0.18 + 0.048*sl 0.15 + 0.052*sl t f 0.29 0.16 + 0.063*sl 0.16 + 0.066*sl 0.12 + 0.069*sl rn to q t phl 0.41 0.33 + 0.039*sl 0.33 + 0.038*sl 0.34 + 0.037*sl t f 0.29 0.16 + 0.062*sl 0.15 + 0.066*sl 0.13 + 0.069*sl ck to z t plh 0.89 0.78 + 0.057*sl 0.81 + 0.045*sl 0.88 + 0.038*sl t phl 1.01 0.85 + 0.081*sl 0.86 + 0.075*sl 0.92 + 0.070*sl t r 0.15 0.09 + 0.029*sl 0.10 + 0.027*sl 0.09 + 0.028*sl t f 0.43 0.18 + 0.128*sl 0.22 + 0.111*sl 0.31 + 0.101*sl rn to z t phl 0.69 0.53 + 0.081*sl 0.55 + 0.075*sl 0.60 + 0.069*sl t f 0.43 0.18 + 0.127*sl 0.22 + 0.110*sl 0.31 + 0.100*sl rd to z t plh 0.25 0.20 + 0.025*sl 0.22 + 0.015*sl 0.25 + 0.012*sl t phl 0.14 0.04 + 0.050*sl 0.06 + 0.040*sl 0.07 + 0.039*sl t r 0.16 0.11 + 0.023*sl 0.10 + 0.025*sl 0.09 + 0.027*sl t f 0.32 0.18 + 0.068*sl 0.17 + 0.072*sl 0.11 + 0.078*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.31 0.30 + 0.002*sl 0.31 + 0.000*sl 0.31 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.71 0.67 + 0.021*sl 0.68 + 0.016*sl 0.72 + 0.012*sl t phl 0.72 0.68 + 0.023*sl 0.68 + 0.020*sl 0.70 + 0.018*sl t r 0.24 0.19 + 0.023*sl 0.19 + 0.024*sl 0.17 + 0.025*sl t f 0.22 0.16 + 0.029*sl 0.15 + 0.030*sl 0.12 + 0.034*sl rn to q t phl 0.41 0.36 + 0.023*sl 0.37 + 0.019*sl 0.38 + 0.018*sl t f 0.21 0.15 + 0.030*sl 0.15 + 0.030*sl 0.12 + 0.034*sl ck to z t plh 0.95 0.88 + 0.037*sl 0.89 + 0.029*sl 0.98 + 0.020*sl t phl 1.03 0.94 + 0.044*sl 0.95 + 0.040*sl 0.99 + 0.036*sl t r 0.16 0.12 + 0.017*sl 0.13 + 0.015*sl 0.14 + 0.014*sl t f 0.33 0.21 + 0.057*sl 0.21 + 0.061*sl 0.30 + 0.051*sl rn to z t phl 0.71 0.62 + 0.044*sl 0.63 + 0.039*sl 0.67 + 0.035*sl t f 0.33 0.22 + 0.059*sl 0.21 + 0.060*sl 0.30 + 0.051*sl rd to z t plh 0.28 0.24 + 0.016*sl 0.26 + 0.011*sl 0.30 + 0.006*sl t phl 0.09 0.03 + 0.031*sl 0.04 + 0.023*sl 0.08 + 0.019*sl t r 0.17 0.14 + 0.016*sl 0.14 + 0.013*sl 0.15 + 0.013*sl t f 0.26 0.18 + 0.037*sl 0.19 + 0.034*sl 0.15 + 0.038*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.42 0.42 + 0.001*sl 0.42 + 0.000*sl 0.42 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-215 STD80/stdm80 fd2t/fd2td2 d flip-flop with reset, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2t stdm80 fd2td2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.98 0.89 + 0.045*sl 0.91 + 0.037*sl 0.93 + 0.034*sl t phl 1.03 0.93 + 0.050*sl 0.94 + 0.046*sl 0.95 + 0.044*sl t r 0.38 0.24 + 0.069*sl 0.24 + 0.067*sl 0.23 + 0.069*sl t f 0.37 0.21 + 0.078*sl 0.21 + 0.079*sl 0.19 + 0.081*sl rn to q t phl 0.53 0.43 + 0.050*sl 0.44 + 0.046*sl 0.45 + 0.045*sl t f 0.36 0.20 + 0.080*sl 0.20 + 0.080*sl 0.19 + 0.081*sl ck to z t plh 1.30 1.14 + 0.077*sl 1.18 + 0.064*sl 1.22 + 0.058*sl t phl 1.40 1.20 + 0.101*sl 1.22 + 0.094*sl 1.24 + 0.090*sl t r 0.21 0.13 + 0.041*sl 0.14 + 0.036*sl 0.14 + 0.037*sl t f 0.58 0.27 + 0.154*sl 0.31 + 0.139*sl 0.35 + 0.133*sl rn to z t phl 0.90 0.70 + 0.101*sl 0.72 + 0.094*sl 0.75 + 0.090*sl t f 0.58 0.27 + 0.154*sl 0.32 + 0.138*sl 0.36 + 0.133*sl rd to z t plh 0.33 0.27 + 0.028*sl 0.29 + 0.021*sl 0.31 + 0.019*sl t phl 0.21 0.11 + 0.054*sl 0.12 + 0.050*sl 0.12 + 0.050*sl t r 0.21 0.14 + 0.036*sl 0.14 + 0.036*sl 0.14 + 0.035*sl t f 0.37 0.19 + 0.091*sl 0.17 + 0.095*sl 0.15 + 0.098*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.39 0.39 + 0.000*sl 0.39 + 0.000*sl 0.39 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.01 0.96 + 0.029*sl 0.97 + 0.024*sl 0.99 + 0.020*sl t phl 1.03 0.96 + 0.031*sl 0.98 + 0.026*sl 1.00 + 0.023*sl t r 0.30 0.22 + 0.038*sl 0.23 + 0.035*sl 0.24 + 0.033*sl t f 0.27 0.19 + 0.040*sl 0.20 + 0.038*sl 0.20 + 0.038*sl rn to q t phl 0.53 0.47 + 0.032*sl 0.48 + 0.026*sl 0.51 + 0.023*sl t f 0.26 0.19 + 0.039*sl 0.19 + 0.038*sl 0.19 + 0.037*sl ck to z t plh 1.37 1.27 + 0.052*sl 1.30 + 0.042*sl 1.34 + 0.036*sl t phl 1.42 1.31 + 0.058*sl 1.33 + 0.052*sl 1.35 + 0.048*sl t r 0.21 0.16 + 0.024*sl 0.17 + 0.020*sl 0.18 + 0.019*sl t f 0.44 0.28 + 0.081*sl 0.28 + 0.080*sl 0.34 + 0.071*sl rn to z t phl 0.93 0.81 + 0.058*sl 0.83 + 0.051*sl 0.85 + 0.048*sl t f 0.44 0.27 + 0.083*sl 0.28 + 0.079*sl 0.34 + 0.071*sl rd to z t plh 0.37 0.33 + 0.019*sl 0.35 + 0.015*sl 0.37 + 0.012*sl t phl 0.16 0.10 + 0.031*sl 0.12 + 0.026*sl 0.12 + 0.025*sl t r 0.24 0.20 + 0.018*sl 0.20 + 0.018*sl 0.20 + 0.018*sl t f 0.28 0.20 + 0.043*sl 0.19 + 0.045*sl 0.18 + 0.047*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.54 0.54 + 0.000*sl 0.54 + 0.000*sl 0.54 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-216 sec asic fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive logic symbol cell data schematic diagram input load (sl) output load (sl) gate count STD80 fd2tcs fd2tcsd2 fd2tcs fd2tcs d2 fd2tcs fd2tcs d2 si sck d rd ck rn si sck d rd ck rn z z 0.6 2.0 0.6 1.1 0.6 1.7 0.6 2.0 0.6 1.5 0.6 1.9 1.3 2.4 11.3 12.0 stdm80 fd2tcs fd2tcsd2 fd2tcs fd2tcs d2 fd2tcs fd2tcs d2 si sck d rd ck rn si sck d rd ck rn z z 0.6 1.8 0.6 0.9 0.6 1.8 0.6 1.8 0.6 1.3 0.6 1.9 1.4 2.6 11.3 12.0 q z si rd ck sck d rn d cl clb cl clb cl cl clb clb sck sckb sck sckb sckb sck sckb sck si rn rn rn cl clb sck sck sckb ck rn rn q z rd truth table * rd is a tri-state enable pin. si sck d rd ck rn q (n+1) z (n+1) x001 100 x011 111 0 x10100 1 x10111 xxx1x000 x x x 0 x 1 x hi-z
sec asic 3-217 STD80/stdm80 fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2tcs parameter symbol STD80 stdm80 fd2tcs fd2tcsd2 fd2tcs fd2tcsd2 pulse width low (ck) t pwl 0.87 0.87 0.90 0.90 pulse width high (ck) t pwh 0.87 0.87 0.82 0.87 pulse width low (sck) t pwl 0.87 0.87 0.82 0.82 pulse width high (sck) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.87 input setup time (d to ck) t su 0.46 0.46 0.55 0.55 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (si to sck) t su 0.68 0.68 0.85 0.85 input hold time (si to sck) t hd 0.33 0.33 0.33 0.33 recovery time (rn to ck) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76 recovery time (rn to sck) t rc 0.33 0.33 0.33 0.33 input hold time (rn to sck) t hd 0.49 0.49 0.55 0.49 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.63 + 0.031*sl 0.64 + 0.026*sl 0.66 + 0.024*sl t phl 0.72 0.64 + 0.040*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.28 0.18 + 0.049*sl 0.18 + 0.049*sl 0.15 + 0.052*sl t f 0.28 0.16 + 0.063*sl 0.15 + 0.067*sl 0.13 + 0.069*sl sck to q t plh 0.76 0.69 + 0.033*sl 0.71 + 0.026*sl 0.73 + 0.024*sl t phl 0.65 0.57 + 0.040*sl 0.58 + 0.037*sl 0.58 + 0.037*sl t r 0.30 0.21 + 0.046*sl 0.20 + 0.047*sl 0.16 + 0.052*sl t f 0.29 0.17 + 0.063*sl 0.16 + 0.066*sl 0.13 + 0.069*sl rn to q t phl 0.41 0.33 + 0.040*sl 0.34 + 0.038*sl 0.34 + 0.037*sl t f 0.29 0.16 + 0.065*sl 0.15 + 0.068*sl 0.14 + 0.069*sl ck to z t plh 0.90 0.79 + 0.056*sl 0.81 + 0.045*sl 0.88 + 0.038*sl t phl 1.01 0.84 + 0.081*sl 0.86 + 0.076*sl 0.91 + 0.070*sl t r 0.15 0.10 + 0.029*sl 0.10 + 0.027*sl 0.09 + 0.028*sl t f 0.44 0.18 + 0.130*sl 0.22 + 0.110*sl 0.32 + 0.101*sl sck to z t plh 0.97 0.85 + 0.058*sl 0.88 + 0.045*sl 0.95 + 0.038*sl t phl 0.94 0.78 + 0.081*sl 0.79 + 0.075*sl 0.85 + 0.070*sl t r 0.15 0.10 + 0.029*sl 0.10 + 0.027*sl 0.09 + 0.028*sl t f 0.43 0.17 + 0.128*sl 0.21 + 0.111*sl 0.31 + 0.101*sl rn to z t phl 0.69 0.53 + 0.081*sl 0.54 + 0.075*sl 0.60 + 0.070*sl t f 0.44 0.18 + 0.129*sl 0.22 + 0.110*sl 0.31 + 0.101*sl rd to z t plh 0.25 0.20 + 0.026*sl 0.22 + 0.015*sl 0.25 + 0.012*sl t phl 0.14 0.04 + 0.050*sl 0.06 + 0.040*sl 0.07 + 0.039*sl t r 0.16 0.11 + 0.023*sl 0.10 + 0.025*sl 0.09 + 0.027*sl t f 0.32 0.18 + 0.067*sl 0.17 + 0.072*sl 0.11 + 0.078*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.31 0.31 + 0.001*sl 0.31 + 0.000*sl 0.31 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-218 sec asic fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2tcsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.74 0.69 + 0.021*sl 0.71 + 0.016*sl 0.74 + 0.012*sl t phl 0.69 0.65 + 0.022*sl 0.65 + 0.020*sl 0.67 + 0.018*sl t r 0.24 0.19 + 0.023*sl 0.19 + 0.024*sl 0.17 + 0.025*sl t f 0.20 0.14 + 0.029*sl 0.14 + 0.031*sl 0.11 + 0.034*sl sck to q t plh 0.84 0.80 + 0.021*sl 0.81 + 0.017*sl 0.86 + 0.012*sl t phl 0.63 0.59 + 0.023*sl 0.60 + 0.020*sl 0.61 + 0.018*sl t r 0.26 0.21 + 0.025*sl 0.22 + 0.023*sl 0.19 + 0.025*sl t f 0.21 0.15 + 0.030*sl 0.15 + 0.030*sl 0.12 + 0.034*sl rn to q t phl 0.42 0.38 + 0.023*sl 0.38 + 0.019*sl 0.40 + 0.018*sl t f 0.21 0.15 + 0.030*sl 0.15 + 0.030*sl 0.12 + 0.034*sl ck to z t plh 0.96 0.89 + 0.039*sl 0.91 + 0.029*sl 1.00 + 0.020*sl t phl 1.00 0.92 + 0.044*sl 0.92 + 0.040*sl 0.97 + 0.036*sl t r 0.15 0.11 + 0.019*sl 0.12 + 0.015*sl 0.13 + 0.014*sl t f 0.30 0.20 + 0.049*sl 0.18 + 0.061*sl 0.27 + 0.052*sl sck to z t plh 1.07 0.99 + 0.039*sl 1.01 + 0.029*sl 1.11 + 0.020*sl t phl 0.95 0.86 + 0.044*sl 0.87 + 0.040*sl 0.91 + 0.036*sl t r 0.15 0.11 + 0.018*sl 0.12 + 0.015*sl 0.13 + 0.014*sl t f 0.30 0.20 + 0.049*sl 0.18 + 0.061*sl 0.27 + 0.052*sl rn to z t phl 0.72 0.63 + 0.044*sl 0.64 + 0.039*sl 0.68 + 0.035*sl t f 0.31 0.20 + 0.051*sl 0.18 + 0.060*sl 0.27 + 0.052*sl rd to z t plh 0.27 0.23 + 0.020*sl 0.25 + 0.012*sl 0.30 + 0.006*sl t phl 0.07 0.01 + 0.030*sl 0.03 + 0.023*sl 0.06 + 0.019*sl t r 0.15 0.12 + 0.013*sl 0.12 + 0.014*sl 0.13 + 0.013*sl t f 0.25 0.17 + 0.038*sl 0.18 + 0.034*sl 0.13 + 0.039*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.42 0.42 + 0.001*sl 0.42 + 0.000*sl 0.42 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-219 STD80/stdm80 fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2tcs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.99 0.90 + 0.044*sl 0.92 + 0.038*sl 0.94 + 0.034*sl t phl 1.02 0.92 + 0.050*sl 0.93 + 0.046*sl 0.94 + 0.045*sl t r 0.37 0.24 + 0.070*sl 0.24 + 0.068*sl 0.23 + 0.069*sl t f 0.37 0.21 + 0.080*sl 0.21 + 0.079*sl 0.19 + 0.081*sl sck to q t plh 1.14 1.05 + 0.046*sl 1.07 + 0.038*sl 1.10 + 0.034*sl t phl 0.92 0.82 + 0.051*sl 0.83 + 0.046*sl 0.84 + 0.044*sl t r 0.40 0.27 + 0.068*sl 0.27 + 0.066*sl 0.26 + 0.068*sl t f 0.37 0.22 + 0.078*sl 0.22 + 0.079*sl 0.20 + 0.081*sl rn to q t phl 0.53 0.43 + 0.050*sl 0.44 + 0.047*sl 0.45 + 0.045*sl t f 0.36 0.20 + 0.080*sl 0.20 + 0.080*sl 0.19 + 0.081*sl ck to z t plh 1.31 1.16 + 0.076*sl 1.19 + 0.064*sl 1.23 + 0.059*sl t phl 1.39 1.19 + 0.101*sl 1.21 + 0.094*sl 1.24 + 0.090*sl t r 0.21 0.13 + 0.039*sl 0.13 + 0.037*sl 0.14 + 0.037*sl t f 0.58 0.28 + 0.153*sl 0.32 + 0.138*sl 0.36 + 0.133*sl sck to z t plh 1.46 1.30 + 0.078*sl 1.34 + 0.065*sl 1.39 + 0.058*sl t phl 1.29 1.09 + 0.101*sl 1.11 + 0.094*sl 1.14 + 0.090*sl t r 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.037*sl t f 0.57 0.26 + 0.156*sl 0.31 + 0.139*sl 0.35 + 0.134*sl rn to z t phl 0.90 0.70 + 0.102*sl 0.72 + 0.094*sl 0.75 + 0.090*sl t f 0.59 0.28 + 0.153*sl 0.33 + 0.137*sl 0.37 + 0.132*sl rd to z t plh 0.34 0.31 + 0.017*sl 0.24 + 0.040*sl -2.59 + 0.441*sl t phl 0.20 0.13 + 0.034*sl -0.06 + 0.098*sl -8.16 + 1.249*sl t r 0.19 0.14 + 0.024*sl -0.00 + 0.070*sl -6.17 + 0.946*sl t f 0.34 0.23 + 0.053*sl -0.17 + 0.186*sl -16.54 + 2.513*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.39 0.39 + 0.001*sl 0.39 + 0.000*sl 0.39 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-220 sec asic fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2tcsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.05 1.00 + 0.029*sl 1.01 + 0.024*sl 1.03 + 0.021*sl t phl 0.99 0.93 + 0.030*sl 0.94 + 0.026*sl 0.96 + 0.023*sl t r 0.30 0.22 + 0.037*sl 0.23 + 0.035*sl 0.24 + 0.034*sl t f 0.26 0.17 + 0.042*sl 0.18 + 0.039*sl 0.19 + 0.038*sl sck to q t plh 1.26 1.20 + 0.031*sl 1.22 + 0.025*sl 1.25 + 0.021*sl t phl 0.90 0.83 + 0.031*sl 0.85 + 0.026*sl 0.87 + 0.023*sl t r 0.33 0.26 + 0.037*sl 0.27 + 0.034*sl 0.28 + 0.032*sl t f 0.27 0.19 + 0.040*sl 0.19 + 0.038*sl 0.19 + 0.038*sl rn to q t phl 0.54 0.48 + 0.031*sl 0.49 + 0.026*sl 0.51 + 0.023*sl t f 0.26 0.18 + 0.041*sl 0.19 + 0.038*sl 0.19 + 0.037*sl ck to z t plh 1.41 1.30 + 0.053*sl 1.33 + 0.043*sl 1.38 + 0.036*sl t phl 1.39 1.27 + 0.058*sl 1.29 + 0.052*sl 1.32 + 0.049*sl t r 0.20 0.15 + 0.024*sl 0.17 + 0.020*sl 0.17 + 0.019*sl t f 0.40 0.26 + 0.071*sl 0.23 + 0.082*sl 0.29 + 0.072*sl sck to z t plh 1.62 1.51 + 0.054*sl 1.54 + 0.043*sl 1.59 + 0.036*sl t phl 1.30 1.19 + 0.058*sl 1.20 + 0.052*sl 1.23 + 0.048*sl t r 0.20 0.16 + 0.022*sl 0.16 + 0.020*sl 0.17 + 0.019*sl t f 0.40 0.26 + 0.070*sl 0.22 + 0.081*sl 0.28 + 0.072*sl rn to z t phl 0.94 0.82 + 0.057*sl 0.84 + 0.051*sl 0.87 + 0.048*sl t f 0.40 0.26 + 0.070*sl 0.22 + 0.080*sl 0.28 + 0.072*sl rd to z t plh 0.39 0.36 + 0.014*sl 0.32 + 0.027*sl -1.07 + 0.225*sl t phl 0.14 0.10 + 0.019*sl 0.01 + 0.052*sl -4.03 + 0.625*sl t r 0.18 0.15 + 0.013*sl 0.08 + 0.039*sl -2.90 + 0.462*sl t f 0.26 0.20 + 0.027*sl 0.01 + 0.090*sl -8.17 + 1.252*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.54 0.54 + 0.000*sl 0.55 + 0.000*sl 0.55 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-221 STD80/stdm80 fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive logic symbol cell data schematic diagram input load (sl) output load (sl) gate count STD80 fd2ts fd2tsd2 fd2ts fd2tsd2 fd2ts fd2tsd2 drdti teckrn d rd ti teckrn z z 0.4 1.1 0.6 1.1 0.6 1.4 0.4 1.2 0.6 1.1 0.6 1.4 1.3 2.2 9.0 10.0 stdm80 fd2ts fd2tsd2 fd2ts fd2tsd2 fd2ts fd2tsd2 drdti teckrn d rd ti teckrn z z 0.6 0.9 0.4 1.1 0.6 1.2 0.6 1.3 0.4 1.1 0.6 1.2 1.4 2.5 9.0 10.0 q z d te ck rd ti rn ck cl clb cl clb cl clb cl cl clb clb rn rn rn rn d te ti q z rd truth table * rd is a tri-state enable pin. drdtiteckrn q (n+1) z (n+1) 01x0 100 11x0 111 x101 100 x111 111 x1xxx000 x 0 x x x 1 x hi-z x 1 x x 1 q (n) z (n)
STD80/stdm80 3-222 sec asic fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd2ts fd2tsd2 fd2ts fd2tsd2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.85 input setup time (d to ck) t su 0.60 0.60 0.79 0.79 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.63 0.63 0.85 0.85 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.33 0.33 0.90 0.90 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76
sec asic 3-223 STD80/stdm80 fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd2ts STD80 fd2tsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.70 0.63 + 0.033*sl 0.64 + 0.026*sl 0.67 + 0.024*sl t phl 0.75 0.67 + 0.040*sl 0.67 + 0.037*sl 0.67 + 0.037*sl t r 0.28 0.18 + 0.047*sl 0.18 + 0.048*sl 0.15 + 0.052*sl t f 0.29 0.16 + 0.062*sl 0.16 + 0.066*sl 0.12 + 0.069*sl rn to q t phl 0.41 0.33 + 0.041*sl 0.33 + 0.037*sl 0.34 + 0.037*sl t f 0.29 0.16 + 0.063*sl 0.16 + 0.066*sl 0.13 + 0.069*sl ck to z t plh 0.91 0.79 + 0.057*sl 0.82 + 0.045*sl 0.89 + 0.038*sl t phl 1.03 0.87 + 0.081*sl 0.88 + 0.075*sl 0.94 + 0.070*sl t r 0.15 0.09 + 0.029*sl 0.10 + 0.027*sl 0.09 + 0.028*sl t f 0.44 0.18 + 0.128*sl 0.22 + 0.110*sl 0.31 + 0.101*sl rn to z t phl 0.69 0.53 + 0.081*sl 0.55 + 0.075*sl 0.60 + 0.069*sl t f 0.44 0.18 + 0.129*sl 0.22 + 0.109*sl 0.31 + 0.100*sl rd to z t plh 0.25 0.20 + 0.025*sl 0.22 + 0.015*sl 0.25 + 0.012*sl t phl 0.14 0.04 + 0.050*sl 0.06 + 0.040*sl 0.07 + 0.039*sl t r 0.16 0.11 + 0.022*sl 0.10 + 0.025*sl 0.09 + 0.027*sl t f 0.32 0.18 + 0.069*sl 0.17 + 0.072*sl 0.11 + 0.078*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.31 0.31 + 0.001*sl 0.31 + 0.000*sl 0.31 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.72 0.68 + 0.021*sl 0.69 + 0.016*sl 0.73 + 0.012*sl t phl 0.74 0.70 + 0.023*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t r 0.24 0.19 + 0.026*sl 0.19 + 0.023*sl 0.17 + 0.025*sl t f 0.22 0.16 + 0.030*sl 0.15 + 0.030*sl 0.12 + 0.034*sl rn to q t phl 0.41 0.36 + 0.023*sl 0.37 + 0.019*sl 0.38 + 0.018*sl t f 0.21 0.15 + 0.030*sl 0.15 + 0.030*sl 0.12 + 0.034*sl ck to z t plh 0.96 0.89 + 0.037*sl 0.90 + 0.029*sl 0.99 + 0.020*sl t phl 1.05 0.96 + 0.044*sl 0.97 + 0.040*sl 1.01 + 0.036*sl t r 0.16 0.12 + 0.017*sl 0.13 + 0.015*sl 0.14 + 0.014*sl t f 0.33 0.22 + 0.056*sl 0.21 + 0.061*sl 0.30 + 0.051*sl rn to z t phl 0.71 0.62 + 0.044*sl 0.63 + 0.040*sl 0.67 + 0.035*sl t f 0.34 0.22 + 0.060*sl 0.22 + 0.060*sl 0.30 + 0.051*sl rd to z t plh 0.28 0.24 + 0.016*sl 0.26 + 0.011*sl 0.30 + 0.006*sl t phl 0.09 0.03 + 0.031*sl 0.04 + 0.023*sl 0.08 + 0.019*sl t r 0.17 0.14 + 0.015*sl 0.14 + 0.013*sl 0.15 + 0.013*sl t f 0.26 0.18 + 0.039*sl 0.19 + 0.034*sl 0.15 + 0.038*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.42 0.42 + 0.001*sl 0.42 + 0.000*sl 0.42 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-224 sec asic fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd2ts stdm80 fd2tsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.99 0.90 + 0.045*sl 0.92 + 0.038*sl 0.95 + 0.034*sl t phl 1.05 0.95 + 0.050*sl 0.96 + 0.046*sl 0.97 + 0.044*sl t r 0.38 0.24 + 0.068*sl 0.24 + 0.067*sl 0.23 + 0.069*sl t f 0.37 0.21 + 0.078*sl 0.21 + 0.079*sl 0.19 + 0.081*sl rn to q t phl 0.53 0.43 + 0.050*sl 0.44 + 0.046*sl 0.45 + 0.045*sl t f 0.36 0.20 + 0.080*sl 0.20 + 0.080*sl 0.19 + 0.081*sl ck to z t plh 1.31 1.16 + 0.077*sl 1.19 + 0.064*sl 1.24 + 0.058*sl t phl 1.42 1.22 + 0.101*sl 1.24 + 0.094*sl 1.27 + 0.090*sl t r 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.037*sl t f 0.58 0.27 + 0.155*sl 0.32 + 0.139*sl 0.35 + 0.134*sl rn to z t phl 0.90 0.70 + 0.101*sl 0.72 + 0.094*sl 0.75 + 0.090*sl t f 0.58 0.28 + 0.153*sl 0.32 + 0.138*sl 0.36 + 0.133*sl rd to z t plh 0.34 0.28 + 0.027*sl 0.30 + 0.022*sl 0.32 + 0.019*sl t phl 0.20 0.13 + 0.035*sl -0.06 + 0.098*sl -8.16 + 1.249*sl t r 0.22 0.14 + 0.037*sl 0.15 + 0.035*sl 0.14 + 0.035*sl t f 0.34 0.23 + 0.053*sl -0.17 + 0.186*sl -16.54 + 2.513*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.39 0.39 + 0.001*sl 0.39 + 0.000*sl 0.39 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.03 0.97 + 0.028*sl 0.98 + 0.024*sl 1.01 + 0.020*sl t phl 1.05 0.99 + 0.031*sl 1.00 + 0.026*sl 1.02 + 0.023*sl t r 0.30 0.22 + 0.038*sl 0.24 + 0.034*sl 0.24 + 0.033*sl t f 0.27 0.19 + 0.040*sl 0.20 + 0.038*sl 0.20 + 0.038*sl rn to q t phl 0.53 0.47 + 0.031*sl 0.48 + 0.026*sl 0.51 + 0.023*sl t f 0.27 0.19 + 0.039*sl 0.19 + 0.038*sl 0.19 + 0.037*sl ck to z t plh 1.38 1.28 + 0.051*sl 1.31 + 0.042*sl 1.35 + 0.036*sl t phl 1.45 1.33 + 0.058*sl 1.35 + 0.052*sl 1.37 + 0.049*sl t r 0.21 0.16 + 0.023*sl 0.17 + 0.020*sl 0.18 + 0.019*sl t f 0.44 0.27 + 0.082*sl 0.28 + 0.079*sl 0.34 + 0.071*sl rn to z t phl 0.93 0.81 + 0.058*sl 0.83 + 0.052*sl 0.85 + 0.048*sl t f 0.44 0.27 + 0.082*sl 0.28 + 0.079*sl 0.34 + 0.071*sl rd to z t plh 0.37 0.35 + 0.012*sl 0.30 + 0.028*sl -1.08 + 0.225*sl t phl 0.16 0.10 + 0.033*sl 0.12 + 0.027*sl 0.13 + 0.025*sl t r 0.23 0.21 + 0.010*sl 0.14 + 0.034*sl -2.85 + 0.458*sl t f 0.30 0.21 + 0.043*sl 0.20 + 0.045*sl 0.19 + 0.046*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.54 0.54 + 0.000*sl 0.54 + 0.000*sl 0.54 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-225 STD80/stdm80 fd3/fd3d2 d flip-flop with set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd3 fd3d2 fd3 fd3d2 d ck sn d ck sn 0.5 0.5 0.7 0.5 0.5 0.7 6.7 7.3 stdm80 fd3 fd3d2 fd3 fd3d2 d ck sn d ck sn 0.6 0.6 1.3 0.6 0.6 1.3 6.7 7.3 parameter symbol STD80 stdm80 fd3 fd3d2 fd3 fd3d2 pulse width low (ck) t pwl 0.87 0.87 0.93 0.93 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.93 0.93 input setup time (d to ck) t su 0.49 0.49 0.60 0.60 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.44 0.44 d ck q qn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn sn sn truth table d ck sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
STD80/stdm80 3-226 sec asic fd3/fd3d2 d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd3 STD80 fd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.52 + 0.028*sl 0.53 + 0.024*sl 0.53 + 0.024*sl t phl 0.70 0.62 + 0.041*sl 0.63 + 0.038*sl 0.63 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.065*sl 0.10 + 0.066*sl 0.08 + 0.069*sl sn to q t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to qn t plh 0.81 0.75 + 0.030*sl 0.76 + 0.025*sl 0.77 + 0.024*sl t phl 0.78 0.71 + 0.038*sl 0.71 + 0.037*sl 0.71 + 0.037*sl t r 0.21 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl sn to qn t phl 0.35 0.27 + 0.040*sl 0.27 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.55 + 0.018*sl 0.56 + 0.014*sl 0.57 + 0.012*sl t phl 0.69 0.65 + 0.023*sl 0.65 + 0.020*sl 0.67 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.18 0.11 + 0.032*sl 0.12 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.61 0.58 + 0.018*sl 0.59 + 0.013*sl 0.60 + 0.012*sl t r 0.17 0.12 + 0.021*sl 0.12 + 0.022*sl 0.09 + 0.026*sl ck to qn t plh 0.88 0.84 + 0.018*sl 0.85 + 0.014*sl 0.87 + 0.012*sl t phl 0.83 0.80 + 0.019*sl 0.80 + 0.018*sl 0.80 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to qn t phl 0.35 0.30 + 0.023*sl 0.31 + 0.019*sl 0.32 + 0.018*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-227 STD80/stdm80 fd3/fd3d2 d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd3 stdm80 fd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.75 + 0.038*sl 0.76 + 0.035*sl 0.76 + 0.034*sl t phl 0.99 0.89 + 0.051*sl 0.90 + 0.046*sl 0.91 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.081*sl sn to q t plh 0.87 0.79 + 0.038*sl 0.81 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.15 + 0.068*sl 0.13 + 0.071*sl ck to qn t plh 1.17 1.09 + 0.041*sl 1.10 + 0.036*sl 1.12 + 0.034*sl t phl 1.11 1.01 + 0.048*sl 1.02 + 0.045*sl 1.03 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.080*sl 0.12 + 0.082*sl sn to qn t phl 0.45 0.35 + 0.050*sl 0.36 + 0.046*sl 0.37 + 0.045*sl t f 0.29 0.13 + 0.081*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.78 + 0.024*sl 0.79 + 0.020*sl 0.80 + 0.018*sl t phl 0.98 0.92 + 0.031*sl 0.93 + 0.026*sl 0.96 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.039*sl 0.15 + 0.038*sl sn to q t plh 0.87 0.83 + 0.024*sl 0.84 + 0.020*sl 0.85 + 0.018*sl t r 0.21 0.15 + 0.032*sl 0.15 + 0.033*sl 0.15 + 0.033*sl ck to qn t plh 1.27 1.22 + 0.024*sl 1.23 + 0.021*sl 1.24 + 0.019*sl t phl 1.18 1.13 + 0.027*sl 1.14 + 0.024*sl 1.15 + 0.022*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.038*sl sn to qn t phl 0.45 0.39 + 0.030*sl 0.40 + 0.025*sl 0.42 + 0.023*sl t f 0.21 0.12 + 0.042*sl 0.13 + 0.038*sl 0.13 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-228 sec asic fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd3cs fd3csd2 fd3cs fd3cs d2 si sck d ck sn si sck d ck sn 0.6 1.8 0.6 0.6 1.7 0.6 1.8 0.6 0.6 1.7 10.7 11.0 stdm80 fd3cs fd3csd2 fd3cs fd3cs d2 si sck d ck sn si sck d ck sn 0.6 2.0 0.6 0.6 2.2 0.6 2.0 0.6 0.6 2.2 10.7 11.0 q qn si sck d ck sn d cl clb q cl clb cl cl clb qn clb sn sn sck sckb sck sckb sck sckb sn sckb sck si cl clb sck sck sckb ck sn sn truth table si sck d ck sn q (n+1) qn (n+1) x00 101 x01 110 0 x0101 1 x0110 xxxx010
sec asic 3-229 STD80/stdm80 fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd3cs fd3csd2 fd3cs fd3csd2 pulse width low (ck) t pwl 0.87 0.87 0.93 0.93 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sck) t pwl 0.87 0.87 0.82 0.82 pulse width high (sck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.90 0.90 0.93 0.93 input setup time (d to ck) t su 0.42 0.42 0.60 0.60 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (si to sck) t su 0.74 0.74 0.90 0.90 input hold time (si to sck) t hd 0.33 0.33 0.33 0.33 recovery time (sn to ck) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.44 0.44 recovery time (sn to sck) t rc 0.41 0.41 0.52 0.52 input hold time (sn to sck) t hd 0.33 0.33 0.33 0.33
STD80/stdm80 3-230 sec asic fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd3cs STD80 fd3csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.52 + 0.028*sl 0.53 + 0.024*sl 0.53 + 0.024*sl t phl 0.69 0.61 + 0.041*sl 0.61 + 0.038*sl 0.62 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sck to q t plh 0.64 0.58 + 0.030*sl 0.59 + 0.025*sl 0.60 + 0.024*sl t phl 0.65 0.57 + 0.041*sl 0.58 + 0.038*sl 0.58 + 0.037*sl t r 0.23 0.14 + 0.044*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.25 0.12 + 0.062*sl 0.12 + 0.066*sl 0.09 + 0.069*sl sn to q t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.56 + 0.023*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl ck to qn t plh 0.89 0.82 + 0.036*sl 0.83 + 0.027*sl 0.87 + 0.024*sl t phl 0.85 0.77 + 0.042*sl 0.78 + 0.038*sl 0.79 + 0.037*sl t r 0.27 0.17 + 0.048*sl 0.17 + 0.048*sl 0.14 + 0.051*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.066*sl 0.10 + 0.069*sl sck to qn t plh 0.75 0.69 + 0.029*sl 0.70 + 0.025*sl 0.71 + 0.024*sl t phl 0.85 0.78 + 0.038*sl 0.78 + 0.037*sl 0.78 + 0.037*sl t r 0.21 0.12 + 0.047*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to qn t phl 0.42 0.33 + 0.043*sl 0.34 + 0.039*sl 0.36 + 0.037*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.066*sl 0.10 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.55 + 0.018*sl 0.56 + 0.014*sl 0.58 + 0.012*sl t phl 0.69 0.64 + 0.023*sl 0.65 + 0.020*sl 0.66 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.18 0.11 + 0.032*sl 0.12 + 0.031*sl 0.09 + 0.034*sl sck to q t plh 0.66 0.62 + 0.020*sl 0.64 + 0.014*sl 0.66 + 0.012*sl t phl 0.65 0.61 + 0.023*sl 0.62 + 0.020*sl 0.63 + 0.018*sl t r 0.19 0.15 + 0.020*sl 0.15 + 0.022*sl 0.11 + 0.026*sl t f 0.19 0.13 + 0.029*sl 0.13 + 0.030*sl 0.09 + 0.034*sl sn to q t plh 0.62 0.58 + 0.018*sl 0.59 + 0.014*sl 0.61 + 0.012*sl t r 0.17 0.13 + 0.018*sl 0.12 + 0.023*sl 0.09 + 0.026*sl ck to qn t plh 0.95 0.91 + 0.022*sl 0.92 + 0.016*sl 0.97 + 0.012*sl t phl 0.91 0.86 + 0.023*sl 0.87 + 0.019*sl 0.88 + 0.018*sl t r 0.24 0.19 + 0.025*sl 0.19 + 0.023*sl 0.17 + 0.025*sl t f 0.20 0.14 + 0.032*sl 0.14 + 0.031*sl 0.12 + 0.034*sl sck to qn t plh 0.83 0.80 + 0.017*sl 0.80 + 0.014*sl 0.83 + 0.012*sl t phl 0.92 0.89 + 0.018*sl 0.89 + 0.018*sl 0.88 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to qn t phl 0.41 0.36 + 0.025*sl 0.37 + 0.020*sl 0.39 + 0.018*sl t f 0.19 0.13 + 0.031*sl 0.13 + 0.031*sl 0.11 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-231 STD80/stdm80 fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd3cs stdm80 fd3csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.75 + 0.038*sl 0.76 + 0.034*sl 0.76 + 0.034*sl t phl 0.98 0.87 + 0.051*sl 0.89 + 0.046*sl 0.90 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.070*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.14 + 0.082*sl sck to q t plh 0.98 0.89 + 0.041*sl 0.91 + 0.035*sl 0.92 + 0.034*sl t phl 0.92 0.81 + 0.052*sl 0.83 + 0.047*sl 0.84 + 0.045*sl t r 0.32 0.19 + 0.065*sl 0.18 + 0.067*sl 0.16 + 0.070*sl t f 0.32 0.16 + 0.078*sl 0.16 + 0.079*sl 0.15 + 0.081*sl sn to q t plh 0.87 0.79 + 0.039*sl 0.80 + 0.034*sl 0.81 + 0.033*sl t r 0.28 0.16 + 0.064*sl 0.14 + 0.069*sl 0.13 + 0.071*sl ck to qn t plh 1.28 1.18 + 0.051*sl 1.20 + 0.041*sl 1.24 + 0.036*sl t phl 1.22 1.11 + 0.055*sl 1.12 + 0.049*sl 1.15 + 0.046*sl t r 0.37 0.22 + 0.074*sl 0.24 + 0.068*sl 0.24 + 0.068*sl t f 0.34 0.17 + 0.084*sl 0.18 + 0.081*sl 0.18 + 0.081*sl sck to qn t plh 1.09 1.01 + 0.040*sl 1.02 + 0.035*sl 1.03 + 0.034*sl t phl 1.27 1.17 + 0.048*sl 1.18 + 0.045*sl 1.19 + 0.044*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.080*sl 0.12 + 0.082*sl sn to qn t phl 0.55 0.43 + 0.056*sl 0.45 + 0.050*sl 0.48 + 0.046*sl t f 0.33 0.16 + 0.086*sl 0.17 + 0.081*sl 0.18 + 0.081*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.83 0.78 + 0.024*sl 0.80 + 0.020*sl 0.81 + 0.018*sl t phl 0.98 0.91 + 0.031*sl 0.93 + 0.026*sl 0.95 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.23 0.15 + 0.040*sl 0.15 + 0.037*sl 0.14 + 0.039*sl sck to q t plh 1.01 0.95 + 0.027*sl 0.97 + 0.021*sl 0.99 + 0.018*sl t phl 0.92 0.86 + 0.031*sl 0.88 + 0.026*sl 0.90 + 0.023*sl t r 0.25 0.18 + 0.033*sl 0.19 + 0.031*sl 0.18 + 0.033*sl t f 0.24 0.16 + 0.040*sl 0.17 + 0.038*sl 0.17 + 0.038*sl sn to q t plh 0.88 0.83 + 0.024*sl 0.84 + 0.020*sl 0.86 + 0.018*sl t r 0.22 0.15 + 0.032*sl 0.15 + 0.032*sl 0.15 + 0.033*sl ck to qn t plh 1.37 1.31 + 0.031*sl 1.33 + 0.024*sl 1.35 + 0.021*sl t phl 1.28 1.22 + 0.030*sl 1.24 + 0.026*sl 1.25 + 0.024*sl t r 0.30 0.22 + 0.039*sl 0.24 + 0.035*sl 0.25 + 0.034*sl t f 0.25 0.16 + 0.043*sl 0.17 + 0.040*sl 0.18 + 0.039*sl sck to qn t plh 1.20 1.15 + 0.023*sl 1.16 + 0.021*sl 1.18 + 0.019*sl t phl 1.37 1.32 + 0.026*sl 1.33 + 0.023*sl 1.34 + 0.022*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.14 + 0.038*sl sn to qn t phl 0.53 0.47 + 0.033*sl 0.48 + 0.028*sl 0.50 + 0.025*sl t f 0.24 0.15 + 0.043*sl 0.16 + 0.040*sl 0.17 + 0.039*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-232 sec asic fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd3s fd3sd2 fd3s fd3sd 2 d ti te ck sn d ti te ck sn 0.3 0.5 0.9 0.5 0.7 0.3 0.5 0.9 0.5 0.7 8.3 9.0 stdm80 fd3s fd3sd2 fd3s fd3sd 2 d ti te ck sn d ti te ck sn 0.6 0.6 1.1 0.6 1.3 0.6 0.6 1.1 0.6 1.3 8.3 9.0 q qn d ti te ck sn cl clb q cl clb cl cl clb qn clb sn sn ck cl clb sn sn d te ti truth table dtitecksn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx010 x x x 1 q (n) qn (n)
sec asic 3-233 STD80/stdm80 fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd3s STD80 fd3sd2 parameter symbol STD80 stdm80 fd3s fd3sd2 fd3s fd3sd2 pulse width low (ck) t pwl 0.87 0.87 0.98 1.01 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.93 0.93 input setup time (d to ck) t su 0.63 0.63 0.85 0.85 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.66 0.66 0.90 0.90 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.71 0.71 0.98 0.98 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.49 0.49 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.59 0.53 + 0.028*sl 0.54 + 0.024*sl 0.55 + 0.024*sl t phl 0.72 0.64 + 0.041*sl 0.65 + 0.038*sl 0.65 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to qn t plh 0.83 0.77 + 0.029*sl 0.78 + 0.025*sl 0.79 + 0.024*sl t phl 0.79 0.72 + 0.039*sl 0.72 + 0.037*sl 0.72 + 0.037*sl t r 0.21 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.07 + 0.069*sl sn to qn t phl 0.35 0.27 + 0.040*sl 0.27 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.59 0.56 + 0.018*sl 0.57 + 0.014*sl 0.58 + 0.012*sl t phl 0.71 0.67 + 0.023*sl 0.67 + 0.020*sl 0.69 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.031*sl 0.09 + 0.034*sl sn to q t plh 0.61 0.58 + 0.018*sl 0.59 + 0.013*sl 0.60 + 0.012*sl t r 0.17 0.12 + 0.021*sl 0.12 + 0.022*sl 0.09 + 0.026*sl ck to qn t plh 0.90 0.86 + 0.018*sl 0.87 + 0.014*sl 0.89 + 0.012*sl t phl 0.85 0.81 + 0.020*sl 0.81 + 0.018*sl 0.81 + 0.018*sl t r 0.19 0.14 + 0.025*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to qn t phl 0.35 0.30 + 0.023*sl 0.31 + 0.019*sl 0.32 + 0.018*sl t f 0.17 0.10 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-234 sec asic fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd3s stdm80 fd3sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.84 0.76 + 0.038*sl 0.77 + 0.034*sl 0.78 + 0.034*sl t phl 1.02 0.91 + 0.052*sl 0.93 + 0.046*sl 0.94 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.081*sl sn to q t plh 0.87 0.79 + 0.039*sl 0.81 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.065*sl 0.15 + 0.068*sl 0.13 + 0.071*sl ck to qn t plh 1.19 1.11 + 0.041*sl 1.13 + 0.036*sl 1.14 + 0.034*sl t phl 1.12 1.03 + 0.048*sl 1.04 + 0.045*sl 1.04 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.080*sl 0.12 + 0.082*sl sn to qn t phl 0.45 0.35 + 0.050*sl 0.36 + 0.046*sl 0.37 + 0.045*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.84 0.79 + 0.024*sl 0.80 + 0.020*sl 0.82 + 0.018*sl t phl 1.01 0.94 + 0.031*sl 0.96 + 0.026*sl 0.98 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.039*sl 0.15 + 0.038*sl 0.15 + 0.038*sl sn to q t plh 0.87 0.83 + 0.024*sl 0.84 + 0.020*sl 0.85 + 0.018*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.032*sl 0.14 + 0.033*sl ck to qn t plh 1.29 1.24 + 0.024*sl 1.25 + 0.021*sl 1.27 + 0.019*sl t phl 1.20 1.14 + 0.027*sl 1.15 + 0.024*sl 1.16 + 0.022*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.038*sl sn to qn t phl 0.45 0.39 + 0.030*sl 0.40 + 0.025*sl 0.42 + 0.023*sl t f 0.21 0.12 + 0.042*sl 0.13 + 0.038*sl 0.13 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-235 STD80/stdm80 fd3q/fd3qd2 d flip-flop with set, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd3q fd3q fd3q fd3qd2 d ck sn d ck sn 0.6 0.6 1.0 0.6 0.6 1.0 6.3 6.7 stdm80 fd3q fd3q fd3q fd3qd2 d ck sn d ck sn 0.6 0.6 1.2 0.6 0.6 1.2 6.3 6.7 parameter symbol STD80 stdm80 fd3q fd3qd2 fd3q fd3qd2 pulse width low (ck) t pwl 0.87 0.87 0.93 0.93 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.93 0.93 input setup time (d to ck) t su 0.49 0.49 0.60 0.60 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.44 0.44 d ck q sn d ck cl clb q cl clb cl clb cl cl clb clb sn sn sn sn truth table d ck sn q (n+1) 010 111 xx01 x x q (n)
STD80/stdm80 3-236 sec asic fd3q/fd3qd2 d flip-flop with set, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd3q STD80 fd3qd2 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd3q stdm80 fd3qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.52 + 0.027*sl 0.52 + 0.024*sl 0.53 + 0.024*sl t phl 0.69 0.60 + 0.041*sl 0.61 + 0.038*sl 0.62 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.07 + 0.069*sl sn to q t plh 0.60 0.54 + 0.028*sl 0.55 + 0.024*sl 0.55 + 0.024*sl t r 0.21 0.11 + 0.047*sl 0.11 + 0.048*sl 0.07 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.54 + 0.018*sl 0.55 + 0.014*sl 0.57 + 0.012*sl t phl 0.68 0.63 + 0.023*sl 0.64 + 0.020*sl 0.65 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.60 0.57 + 0.018*sl 0.58 + 0.013*sl 0.59 + 0.012*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.022*sl 0.09 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.74 + 0.038*sl 0.75 + 0.034*sl 0.76 + 0.034*sl t phl 0.97 0.87 + 0.052*sl 0.88 + 0.046*sl 0.89 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.082*sl sn to q t plh 0.86 0.78 + 0.038*sl 0.79 + 0.034*sl 0.80 + 0.033*sl t r 0.28 0.15 + 0.064*sl 0.14 + 0.068*sl 0.12 + 0.071*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.78 + 0.023*sl 0.79 + 0.020*sl 0.80 + 0.018*sl t phl 0.96 0.90 + 0.031*sl 0.92 + 0.026*sl 0.94 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.033*sl t f 0.22 0.14 + 0.039*sl 0.14 + 0.038*sl 0.14 + 0.038*sl sn to q t plh 0.86 0.82 + 0.024*sl 0.83 + 0.019*sl 0.85 + 0.017*sl t r 0.21 0.15 + 0.031*sl 0.15 + 0.033*sl 0.14 + 0.033*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-237 STD80/stdm80 fd3x2 2-bit d flip-flop with set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.90 0.98 pulse width high (ck) t pwh 0.87 0.79 pulse width low (sn) t pwl 0.87 0.85 input setup time (d0 to ck) t su 0.38 0.46 input hold time (d0 to ck) t hd 0.41 0.33 input setup time (d1 to ck) t su 0.38 0.45 input hold time (d1 to ck) t hd 0.41 0.33 recovery time (sn) t rc 0.33 0.33 input hold time (sn to ck) t hd 0.55 0.60 q0 qn1 d0 d1 ck q1 qn0 sn truth table cell data dn ck sn qn (n+1) qnn (n+1) 0101 1110 xx0 1 0 x 1 qn (n) qnn (n) input load (sl) gate count STD80 dn ck sn 12.3 0.5 0.5 1.5 stdm80 dn ck sn 12.3 0.6 0.6 2.9
STD80/stdm80 3-238 sec asic fd3x2 2-bit d flip-flop with set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd3x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.66 0.61 + 0.028*sl 0.62 + 0.024*sl 0.62 + 0.024*sl t phl 0.88 0.80 + 0.040*sl 0.80 + 0.038*sl 0.81 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl sn to q0 t plh 0.61 0.55 + 0.028*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.042*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to q1 t plh 0.66 0.61 + 0.028*sl 0.61 + 0.024*sl 0.62 + 0.024*sl t phl 0.87 0.79 + 0.041*sl 0.80 + 0.038*sl 0.81 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.066*sl 0.08 + 0.069*sl sn to q1 t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to qn0 t plh 0.99 0.93 + 0.030*sl 0.94 + 0.025*sl 0.95 + 0.024*sl t phl 0.87 0.79 + 0.039*sl 0.80 + 0.037*sl 0.80 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.064*sl 0.10 + 0.067*sl 0.07 + 0.069*sl sn to qn0 t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl ck to qn1 t plh 0.98 0.92 + 0.029*sl 0.93 + 0.025*sl 0.94 + 0.024*sl t phl 0.87 0.79 + 0.038*sl 0.79 + 0.037*sl 0.79 + 0.037*sl t r 0.21 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl sn to qn1 t phl 0.35 0.27 + 0.040*sl 0.27 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-239 STD80/stdm80 fd3x2 2-bit d flip-flop with set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd3x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.93 0.85 + 0.038*sl 0.87 + 0.034*sl 0.87 + 0.034*sl t phl 1.23 1.13 + 0.051*sl 1.15 + 0.046*sl 1.16 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl sn to q0 t plh 0.87 0.79 + 0.039*sl 0.81 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.14 + 0.068*sl 0.13 + 0.071*sl ck to q1 t plh 0.93 0.85 + 0.038*sl 0.86 + 0.035*sl 0.87 + 0.034*sl t phl 1.23 1.13 + 0.051*sl 1.14 + 0.046*sl 1.15 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.080*sl 0.13 + 0.082*sl sn to q1 t plh 0.87 0.79 + 0.039*sl 0.81 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.14 + 0.068*sl 0.13 + 0.071*sl ck to qn0 t plh 1.42 1.34 + 0.040*sl 1.35 + 0.036*sl 1.36 + 0.034*sl t phl 1.22 1.12 + 0.048*sl 1.13 + 0.045*sl 1.14 + 0.044*sl t r 0.30 0.17 + 0.066*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.081*sl sn to qn0 t phl 0.46 0.36 + 0.050*sl 0.37 + 0.046*sl 0.38 + 0.045*sl t f 0.29 0.13 + 0.081*sl 0.13 + 0.081*sl 0.12 + 0.082*sl ck to qn1 t plh 1.41 1.33 + 0.041*sl 1.34 + 0.036*sl 1.36 + 0.034*sl t phl 1.21 1.12 + 0.048*sl 1.13 + 0.045*sl 1.13 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.079*sl 0.13 + 0.080*sl 0.12 + 0.082*sl sn to qn1 t phl 0.45 0.35 + 0.050*sl 0.36 + 0.046*sl 0.37 + 0.045*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-240 sec asic fd3x4 4-bit d flip-flop with set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.90 1.80 pulse width high (ck) t pwh 0.87 1.20 pulse width low (sn) t pwl 0.90 0.93 input setup time (d0 to ck) t su 0.33 0.41 input hold time (d0 to ck) t hd 0.60 0.66 input setup time (d1 to ck) t su 0.33 0.41 input hold time (d1 to ck) t hd 0.60 0.66 input setup time (d2 to ck) t su 0.33 0.41 input hold time (d2 to ck) t hd 0.60 0.66 input setup time (d3 to ck) t su 0.33 0.41 input hold time (d3 to ck) t hd 0.60 0.66 recovery time (sn) t rc 0.33 0.33 input hold time (sn to ck) t hd 0.76 0.98 d0 d1 d2 d3 ck q0 q1 q2 q3 qn0 qn1 qn2 qn3 sn truth table cell data dn ck sn qn (n+1) qnn (n+1) 0101 1110 xx0 1 0 x 1 qn (n) qnn (n) input load (sl) gate count STD80 dn ck sn 23.7 0.5 0.5 3.0 stdm80 dn ck sn 23.7 0.6 0.6 5.9
sec asic 3-241 STD80/stdm80 fd3x4 4-bit d flip-flop with set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd3x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.82 0.76 + 0.029*sl 0.77 + 0.024*sl 0.77 + 0.024*sl t phl 1.19 1.11 + 0.040*sl 1.11 + 0.038*sl 1.12 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl sn to q0 t plh 0.61 0.55 + 0.028*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to q1 t plh 0.82 0.76 + 0.029*sl 0.77 + 0.024*sl 0.77 + 0.024*sl t phl 1.19 1.11 + 0.040*sl 1.11 + 0.038*sl 1.12 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl sn to q1 t plh 0.61 0.55 + 0.028*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to q2 t plh 0.82 0.76 + 0.029*sl 0.77 + 0.024*sl 0.77 + 0.024*sl t phl 1.19 1.11 + 0.040*sl 1.11 + 0.038*sl 1.12 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl sn to q2 t plh 0.61 0.55 + 0.028*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to q3 t plh 0.81 0.76 + 0.028*sl 0.77 + 0.024*sl 0.77 + 0.024*sl t phl 1.19 1.10 + 0.041*sl 1.11 + 0.038*sl 1.12 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl sn to q3 t plh 0.60 0.55 + 0.028*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ck to qn0 t plh 1.29 1.24 + 0.029*sl 1.24 + 0.025*sl 1.26 + 0.024*sl t phl 1.02 0.94 + 0.038*sl 0.94 + 0.037*sl 0.94 + 0.037*sl t r 0.22 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl sn to qn0 t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl ck to qn1 t plh 1.29 1.23 + 0.030*sl 1.25 + 0.025*sl 1.26 + 0.024*sl t phl 1.02 0.94 + 0.038*sl 0.94 + 0.037*sl 0.94 + 0.037*sl t r 0.22 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl sn to qn1 t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl ck to qn2 t plh 1.29 1.23 + 0.030*sl 1.25 + 0.025*sl 1.26 + 0.024*sl t phl 1.02 0.94 + 0.038*sl 0.94 + 0.037*sl 0.94 + 0.037*sl t r 0.22 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-242 sec asic fd3x4 4-bit d flip-flop with set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd3x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.11 1.04 + 0.038*sl 1.05 + 0.035*sl 1.05 + 0.034*sl t phl 1.67 1.57 + 0.051*sl 1.58 + 0.046*sl 1.60 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.14 + 0.081*sl sn to q0 t plh 0.87 0.79 + 0.039*sl 0.80 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.15 + 0.068*sl 0.13 + 0.071*sl ck to q1 t plh 1.11 1.04 + 0.038*sl 1.05 + 0.035*sl 1.05 + 0.034*sl t phl 1.67 1.57 + 0.051*sl 1.58 + 0.046*sl 1.60 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.14 + 0.081*sl sn to q1 t plh 0.87 0.79 + 0.039*sl 0.80 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.15 + 0.068*sl 0.13 + 0.071*sl ck to q2 t plh 1.11 1.04 + 0.038*sl 1.05 + 0.035*sl 1.05 + 0.034*sl t phl 1.67 1.57 + 0.051*sl 1.58 + 0.046*sl 1.60 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.14 + 0.081*sl sn to q2 t plh 0.87 0.79 + 0.039*sl 0.80 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.15 + 0.068*sl 0.13 + 0.071*sl ck to q3 t plh 1.11 1.03 + 0.038*sl 1.04 + 0.034*sl 1.05 + 0.034*sl t phl 1.67 1.57 + 0.051*sl 1.58 + 0.046*sl 1.59 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.14 + 0.081*sl sn to q3 t plh 0.86 0.79 + 0.038*sl 0.80 + 0.034*sl 0.80 + 0.033*sl t r 0.29 0.16 + 0.065*sl 0.15 + 0.068*sl 0.13 + 0.071*sl ck to qn0 t plh 1.85 1.77 + 0.041*sl 1.79 + 0.036*sl 1.80 + 0.034*sl t phl 1.40 1.30 + 0.048*sl 1.31 + 0.045*sl 1.32 + 0.044*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.080*sl 0.12 + 0.082*sl sn to qn0 t phl 0.46 0.36 + 0.051*sl 0.37 + 0.046*sl 0.38 + 0.045*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.13 + 0.082*sl ck to qn1 t plh 1.85 1.77 + 0.041*sl 1.79 + 0.036*sl 1.80 + 0.034*sl t phl 1.40 1.30 + 0.048*sl 1.31 + 0.045*sl 1.32 + 0.044*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.079*sl 0.12 + 0.082*sl sn to qn1 t phl 0.46 0.36 + 0.051*sl 0.37 + 0.046*sl 0.38 + 0.045*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.13 + 0.082*sl ck to qn2 t plh 1.85 1.77 + 0.041*sl 1.79 + 0.036*sl 1.80 + 0.034*sl t phl 1.40 1.30 + 0.048*sl 1.31 + 0.045*sl 1.32 + 0.044*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.079*sl 0.12 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-243 STD80/stdm80 yfd3/yfd3d2 fast d flip-flop with set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 yfd3 yfd3d2 yfd3 yfd3d2 dcksndcksn 1.8 0.5 1.2 1.8 0.5 2.4 5.0 6.3 stdm80 yfd3 yfd3d2 yfd3 yfd3d2 dcksndcksn 2.0 0.6 1.6 2.0 0.6 2.8 5.0 6.3 parameter symbol STD80 stdm80 yfd3 yfd3d2 yfd3 yfd3d2 pulse width low (ck) t pwl 0.87 0.87 0.85 0.85 pulse width high (ck) t pwh 0.87 0.87 0.85 0.98 pulse width low (sn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.38 0.38 0.41 0.41 input hold time (d to ck) t hd 0.46 0.49 0.49 0.49 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.66 0.60 0.71 0.71 d ck q qn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn sn sn truth table d ck sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
STD80/stdm80 3-244 sec asic yfd3/yfd3d2 fast d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 yfd3 STD80 yfd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.52 0.47 + 0.027*sl 0.47 + 0.025*sl 0.48 + 0.025*sl t phl 0.58 0.50 + 0.040*sl 0.50 + 0.039*sl 0.50 + 0.039*sl t r 0.29 0.20 + 0.046*sl 0.19 + 0.051*sl 0.16 + 0.054*sl t f 0.39 0.25 + 0.068*sl 0.24 + 0.073*sl 0.20 + 0.078*sl sn to q t plh 0.19 0.13 + 0.032*sl 0.14 + 0.025*sl 0.26 + 0.013*sl t r 0.32 0.24 + 0.040*sl 0.26 + 0.031*sl 0.31 + 0.025*sl ck to qn t plh 0.71 0.55 + 0.081*sl 0.55 + 0.079*sl 0.56 + 0.078*sl t phl 0.70 0.55 + 0.076*sl 0.55 + 0.073*sl 0.56 + 0.073*sl t r 0.24 0.11 + 0.065*sl 0.11 + 0.067*sl 0.10 + 0.068*sl t f 0.24 0.09 + 0.075*sl 0.09 + 0.076*sl 0.09 + 0.077*sl sn to qn t phl 0.37 0.21 + 0.078*sl 0.23 + 0.068*sl 0.36 + 0.056*sl t f 0.24 0.10 + 0.071*sl 0.10 + 0.071*sl 0.09 + 0.071*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.54 0.51 + 0.016*sl 0.51 + 0.014*sl 0.53 + 0.012*sl t phl 0.65 0.61 + 0.024*sl 0.61 + 0.022*sl 0.64 + 0.019*sl t r 0.26 0.22 + 0.021*sl 0.21 + 0.024*sl 0.18 + 0.027*sl t f 0.40 0.33 + 0.034*sl 0.33 + 0.034*sl 0.29 + 0.038*sl sn to q t plh 0.17 0.14 + 0.016*sl 0.15 + 0.014*sl 0.20 + 0.008*sl t r 0.30 0.27 + 0.016*sl 0.26 + 0.021*sl 0.35 + 0.012*sl ck to qn t plh 0.75 0.66 + 0.046*sl 0.67 + 0.042*sl 0.69 + 0.039*sl t phl 0.65 0.57 + 0.040*sl 0.58 + 0.038*sl 0.60 + 0.036*sl t r 0.18 0.12 + 0.030*sl 0.11 + 0.033*sl 0.10 + 0.034*sl t f 0.16 0.08 + 0.038*sl 0.08 + 0.037*sl 0.07 + 0.038*sl sn to qn t phl 0.29 0.21 + 0.040*sl 0.22 + 0.037*sl 0.30 + 0.028*sl t f 0.16 0.09 + 0.037*sl 0.09 + 0.037*sl 0.10 + 0.035*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-245 STD80/stdm80 yfd3/yfd3d2 fast d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 yfd3 stdm80 yfd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.75 0.68 + 0.038*sl 0.68 + 0.036*sl 0.69 + 0.035*sl t phl 0.83 0.72 + 0.056*sl 0.73 + 0.052*sl 0.74 + 0.051*sl t r 0.40 0.26 + 0.069*sl 0.26 + 0.072*sl 0.24 + 0.074*sl t f 0.52 0.34 + 0.088*sl 0.32 + 0.094*sl 0.30 + 0.096*sl sn to q t plh 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t r 0.37 0.24 + 0.067*sl 0.26 + 0.059*sl 0.42 + 0.036*sl ck to qn t plh 1.03 0.81 + 0.114*sl 0.82 + 0.110*sl 0.83 + 0.108*sl t phl 0.99 0.79 + 0.101*sl 0.79 + 0.099*sl 0.80 + 0.098*sl t r 0.33 0.15 + 0.091*sl 0.15 + 0.090*sl 0.15 + 0.091*sl t f 0.31 0.12 + 0.094*sl 0.12 + 0.095*sl 0.12 + 0.095*sl sn to qn t phl 0.48 0.28 + 0.099*sl 0.29 + 0.096*sl 0.36 + 0.085*sl t f 0.30 0.12 + 0.094*sl 0.12 + 0.091*sl 0.18 + 0.083*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.77 0.72 + 0.022*sl 0.73 + 0.020*sl 0.74 + 0.019*sl t phl 0.97 0.90 + 0.036*sl 0.91 + 0.032*sl 0.93 + 0.029*sl t r 0.34 0.28 + 0.031*sl 0.27 + 0.034*sl 0.26 + 0.035*sl t f 0.54 0.45 + 0.046*sl 0.45 + 0.046*sl 0.45 + 0.046*sl sn to q t plh 0.22 0.18 + 0.019*sl 0.19 + 0.017*sl 0.18 + 0.017*sl t r 0.33 0.27 + 0.028*sl 0.25 + 0.034*sl 0.25 + 0.034*sl ck to qn t plh 1.12 0.99 + 0.066*sl 1.00 + 0.062*sl 1.03 + 0.058*sl t phl 0.93 0.82 + 0.054*sl 0.83 + 0.051*sl 0.84 + 0.049*sl t r 0.24 0.15 + 0.045*sl 0.15 + 0.045*sl 0.15 + 0.045*sl t f 0.20 0.11 + 0.045*sl 0.11 + 0.047*sl 0.11 + 0.046*sl sn to qn t phl 0.37 0.27 + 0.050*sl 0.28 + 0.049*sl 0.28 + 0.048*sl t f 0.19 0.10 + 0.047*sl 0.10 + 0.047*sl 0.11 + 0.046*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-246 sec asic fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd4 fd4d2 fd4 fd4d2 d ck rn sn d ck rn sn 0.5 0.5 1.1 0.7 0.6 0.6 1.2 1.1 7.7 8.3 stdm80 fd4 fd4d2 fd4 fd4d2 d ck rn sn d ck rn sn 0.6 0.6 1.6 1.6 0.6 0.6 1.6 1.6 7.7 8.3 d ck q qn rn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn rn rn rn rn sn sn truth table dckrnsn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0000 x 1 1 q (n) qn (n)
sec asic 3-247 STD80/stdm80 fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd4 fd4d2 fd4 fd4d2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.96 0.96 input setup time (d to ck) t su 0.52 0.52 0.63 0.63 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.71 0.71 0.82 0.82 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.44 0.44
STD80/stdm80 3-248 sec asic fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4 STD80 fd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.64 0.57 + 0.032*sl 0.59 + 0.026*sl 0.61 + 0.024*sl t phl 0.73 0.64 + 0.041*sl 0.65 + 0.038*sl 0.66 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q t plh 0.33 0.27 + 0.032*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.62 + 0.023*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl ck to qn t plh 0.84 0.78 + 0.030*sl 0.79 + 0.025*sl 0.81 + 0.024*sl t phl 0.86 0.78 + 0.038*sl 0.79 + 0.037*sl 0.78 + 0.037*sl t r 0.22 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.45 + 0.023*sl t r 0.22 0.12 + 0.047*sl 0.12 + 0.048*sl 0.09 + 0.052*sl sn to qn t plh 0.33 0.26 + 0.031*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.61 + 0.021*sl 0.62 + 0.015*sl 0.65 + 0.012*sl t phl 0.72 0.67 + 0.023*sl 0.68 + 0.020*sl 0.70 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.032*sl 0.12 + 0.030*sl 0.09 + 0.034*sl rn to q t plh 0.34 0.31 + 0.018*sl 0.31 + 0.015*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.67 0.63 + 0.021*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.023*sl 0.13 + 0.026*sl ck to qn t plh 0.91 0.87 + 0.018*sl 0.88 + 0.014*sl 0.91 + 0.012*sl t phl 0.94 0.90 + 0.019*sl 0.90 + 0.017*sl 0.90 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.19 0.12 + 0.032*sl 0.13 + 0.030*sl 0.09 + 0.034*sl rn to qn t plh 0.55 0.51 + 0.018*sl 0.52 + 0.014*sl 0.55 + 0.012*sl t r 0.19 0.14 + 0.024*sl 0.14 + 0.023*sl 0.12 + 0.026*sl sn to qn t plh 0.34 0.30 + 0.022*sl 0.31 + 0.015*sl 0.35 + 0.012*sl t phl 0.35 0.31 + 0.023*sl 0.31 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-249 STD80/stdm80 fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4 stdm80 fd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.91 0.82 + 0.043*sl 0.84 + 0.037*sl 0.86 + 0.035*sl t phl 1.03 0.92 + 0.052*sl 0.94 + 0.047*sl 0.95 + 0.045*sl t r 0.31 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.39 + 0.045*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl sn to q t plh 0.94 0.85 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.18 + 0.067*sl 0.18 + 0.067*sl 0.17 + 0.069*sl ck to qn t plh 1.22 1.14 + 0.041*sl 1.15 + 0.036*sl 1.17 + 0.034*sl t phl 1.22 1.12 + 0.049*sl 1.14 + 0.045*sl 1.14 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.081*sl rn to qn t plh 0.67 0.58 + 0.042*sl 0.60 + 0.036*sl 0.62 + 0.034*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl sn to qn t plh 0.44 0.35 + 0.042*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.38 + 0.046*sl 0.38 + 0.045*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.92 0.87 + 0.028*sl 0.88 + 0.023*sl 0.91 + 0.019*sl t phl 1.02 0.96 + 0.031*sl 0.98 + 0.026*sl 0.99 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.034*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.038*sl 0.16 + 0.038*sl rn to q t plh 0.45 0.39 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.18 + 0.034*sl t f 0.21 0.13 + 0.042*sl 0.14 + 0.039*sl 0.14 + 0.038*sl sn to q t plh 0.95 0.90 + 0.028*sl 0.92 + 0.022*sl 0.94 + 0.019*sl t r 0.25 0.18 + 0.035*sl 0.19 + 0.034*sl 0.19 + 0.033*sl ck to qn t plh 1.32 1.27 + 0.024*sl 1.28 + 0.021*sl 1.30 + 0.019*sl t phl 1.33 1.27 + 0.026*sl 1.28 + 0.023*sl 1.29 + 0.022*sl t r 0.24 0.17 + 0.037*sl 0.17 + 0.035*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.040*sl 0.16 + 0.038*sl 0.16 + 0.037*sl rn to qn t plh 0.76 0.71 + 0.025*sl 0.72 + 0.021*sl 0.73 + 0.019*sl t r 0.24 0.17 + 0.037*sl 0.18 + 0.034*sl 0.18 + 0.034*sl sn to qn t plh 0.45 0.40 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.16 + 0.037*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.21 0.12 + 0.042*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-250 sec asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd4cs fd4csd2 fd4cs fd4csd2 si sck d ck rn sn si sck d ck rn sn 0.6 2.1 0.6 0.6 1.8 1.8 0.6 2.1 0.6 0.6 1.9 1.8 12.3 12.7 stdm80 fd4cs fd4csd2 fd4cs fd4csd2 si sck d ck rn sn si sck d ck rn sn 0.6 1.9 0.6 0.6 2.4 2.5 0.6 1.9 0.6 0.6 2.4 2.5 12.3 12.7 q qn si sck d ck rn sn d cl clb q cl clb cl cl clb qn clb sn sn rn rn sck sckb si sck sckb sck sckb sn rn sckb sck cl clb sck sck sckb ck rn rn sn sn truth table si sck d ck rn sn q (n+1) qn (n+1) x00 11 0 1 x01 11 1 0 0x01101 1x01110 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0
sec asic 3-251 STD80/stdm80 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd4cs fd4csd2 fd4cs fd4csd2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sck) t pwl 0.87 0.87 0.82 0.82 pulse width high (sck) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.96 0.96 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.98 1.01 input setup time (d to ck) t su 0.52 0.52 0.63 0.63 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (si to sck) t su 0.74 0.74 0.93 0.93 input hold time (si to sck) t hd 0.33 0.33 0.33 0.33 recovery time (rn to ck) t rc 0.44 0.44 0.33 0.33 input hold time (rn to ck) t hd 0.71 0.71 0.82 0.82 recovery time (rn to sck) t rc 0.33 0.33 0.33 0.33 input hold time (rn to sck) t hd 0.55 0.55 0.60 0.60 recovery time (sn to ck) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.44 0.44 recovery time (sn to sck) t rc 0.33 0.33 0.52 0.52 input hold time (sn to sck) t hd 0.33 0.33 0.33 0.33
STD80/stdm80 3-252 sec asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4cs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.62 + 0.024*sl t phl 0.70 0.62 + 0.041*sl 0.63 + 0.038*sl 0.64 + 0.037*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.065*sl 0.11 + 0.067*sl 0.08 + 0.069*sl sck to q t plh 0.74 0.67 + 0.033*sl 0.68 + 0.026*sl 0.71 + 0.024*sl t phl 0.65 0.57 + 0.042*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.26 0.16 + 0.046*sl 0.16 + 0.047*sl 0.12 + 0.052*sl t f 0.25 0.13 + 0.062*sl 0.12 + 0.066*sl 0.09 + 0.069*sl sn to q t plh 0.68 0.62 + 0.033*sl 0.63 + 0.026*sl 0.65 + 0.024*sl t r 0.23 0.14 + 0.044*sl 0.14 + 0.048*sl 0.10 + 0.052*sl rn to q t plh 0.31 0.25 + 0.031*sl 0.26 + 0.025*sl 0.28 + 0.024*sl t phl 0.38 0.30 + 0.040*sl 0.31 + 0.038*sl 0.32 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.11 + 0.067*sl 0.09 + 0.069*sl ck to qn t plh 0.90 0.83 + 0.037*sl 0.85 + 0.027*sl 0.88 + 0.024*sl t phl 0.94 0.86 + 0.041*sl 0.87 + 0.038*sl 0.88 + 0.037*sl t r 0.27 0.17 + 0.049*sl 0.17 + 0.048*sl 0.14 + 0.051*sl t f 0.26 0.14 + 0.065*sl 0.13 + 0.066*sl 0.10 + 0.069*sl sck to qn t plh 0.76 0.70 + 0.029*sl 0.71 + 0.025*sl 0.72 + 0.024*sl t phl 0.96 0.88 + 0.038*sl 0.88 + 0.037*sl 0.88 + 0.037*sl t r 0.21 0.12 + 0.047*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.08 + 0.069*sl sn to qn t plh 0.41 0.33 + 0.037*sl 0.36 + 0.027*sl 0.39 + 0.024*sl t phl 0.42 0.33 + 0.043*sl 0.34 + 0.039*sl 0.36 + 0.037*sl t r 0.27 0.17 + 0.047*sl 0.17 + 0.047*sl 0.13 + 0.051*sl t f 0.26 0.13 + 0.064*sl 0.12 + 0.066*sl 0.10 + 0.069*sl rn to qn t plh 0.49 0.43 + 0.029*sl 0.44 + 0.025*sl 0.45 + 0.023*sl t r 0.21 0.12 + 0.047*sl 0.12 + 0.049*sl 0.09 + 0.052*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-253 STD80/stdm80 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.67 0.63 + 0.021*sl 0.64 + 0.016*sl 0.67 + 0.012*sl t phl 0.70 0.65 + 0.023*sl 0.66 + 0.020*sl 0.68 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl sck to q t plh 0.77 0.72 + 0.023*sl 0.73 + 0.016*sl 0.77 + 0.012*sl t phl 0.66 0.61 + 0.023*sl 0.62 + 0.020*sl 0.63 + 0.018*sl t r 0.22 0.18 + 0.022*sl 0.18 + 0.023*sl 0.15 + 0.025*sl t f 0.19 0.13 + 0.029*sl 0.13 + 0.030*sl 0.10 + 0.034*sl sn to q t plh 0.70 0.66 + 0.021*sl 0.67 + 0.015*sl 0.71 + 0.012*sl t r 0.20 0.15 + 0.025*sl 0.16 + 0.023*sl 0.13 + 0.026*sl rn to q t plh 0.33 0.29 + 0.019*sl 0.30 + 0.016*sl 0.33 + 0.012*sl t phl 0.38 0.33 + 0.023*sl 0.34 + 0.020*sl 0.35 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl ck to qn t plh 0.97 0.92 + 0.022*sl 0.93 + 0.017*sl 0.98 + 0.012*sl t phl 1.03 0.98 + 0.022*sl 0.99 + 0.018*sl 0.99 + 0.018*sl t r 0.24 0.19 + 0.026*sl 0.19 + 0.023*sl 0.17 + 0.025*sl t f 0.21 0.15 + 0.033*sl 0.15 + 0.031*sl 0.12 + 0.033*sl sck to qn t plh 0.83 0.80 + 0.017*sl 0.81 + 0.014*sl 0.83 + 0.012*sl t phl 1.05 1.01 + 0.018*sl 1.02 + 0.017*sl 1.00 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.19 0.12 + 0.032*sl 0.13 + 0.030*sl 0.09 + 0.034*sl sn to qn t plh 0.42 0.37 + 0.023*sl 0.38 + 0.017*sl 0.43 + 0.012*sl t phl 0.41 0.36 + 0.025*sl 0.37 + 0.020*sl 0.39 + 0.018*sl t r 0.23 0.18 + 0.025*sl 0.19 + 0.024*sl 0.17 + 0.025*sl t f 0.20 0.13 + 0.034*sl 0.13 + 0.031*sl 0.11 + 0.034*sl rn to qn t plh 0.55 0.52 + 0.018*sl 0.53 + 0.014*sl 0.55 + 0.012*sl t r 0.19 0.14 + 0.024*sl 0.14 + 0.023*sl 0.11 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-254 sec asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4cs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.94 0.85 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.035*sl t phl 1.00 0.90 + 0.052*sl 0.91 + 0.046*sl 0.92 + 0.045*sl t r 0.32 0.18 + 0.068*sl 0.18 + 0.070*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.14 + 0.082*sl sck to q t plh 1.11 1.02 + 0.045*sl 1.05 + 0.038*sl 1.07 + 0.035*sl t phl 0.93 0.82 + 0.053*sl 0.84 + 0.047*sl 0.86 + 0.045*sl t r 0.35 0.22 + 0.067*sl 0.21 + 0.068*sl 0.21 + 0.069*sl t f 0.33 0.17 + 0.080*sl 0.17 + 0.079*sl 0.15 + 0.081*sl sn to q t plh 0.98 0.89 + 0.044*sl 0.92 + 0.037*sl 0.93 + 0.034*sl t r 0.32 0.19 + 0.066*sl 0.18 + 0.068*sl 0.17 + 0.070*sl rn to q t plh 0.43 0.35 + 0.043*sl 0.37 + 0.036*sl 0.38 + 0.034*sl t phl 0.49 0.39 + 0.051*sl 0.41 + 0.047*sl 0.41 + 0.045*sl t r 0.31 0.17 + 0.068*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.31 0.14 + 0.082*sl 0.14 + 0.081*sl 0.14 + 0.082*sl ck to qn t plh 1.30 1.20 + 0.051*sl 1.23 + 0.041*sl 1.26 + 0.036*sl t phl 1.35 1.24 + 0.054*sl 1.26 + 0.048*sl 1.28 + 0.046*sl t r 0.37 0.22 + 0.073*sl 0.24 + 0.068*sl 0.24 + 0.068*sl t f 0.34 0.17 + 0.085*sl 0.18 + 0.081*sl 0.19 + 0.080*sl sck to qn t plh 1.10 1.02 + 0.041*sl 1.04 + 0.035*sl 1.05 + 0.034*sl t phl 1.42 1.32 + 0.048*sl 1.33 + 0.045*sl 1.34 + 0.044*sl t r 0.30 0.16 + 0.071*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.082*sl sn to qn t plh 0.54 0.44 + 0.051*sl 0.47 + 0.041*sl 0.50 + 0.036*sl t phl 0.55 0.44 + 0.056*sl 0.46 + 0.050*sl 0.48 + 0.046*sl t r 0.37 0.22 + 0.073*sl 0.24 + 0.068*sl 0.23 + 0.068*sl t f 0.33 0.16 + 0.085*sl 0.17 + 0.082*sl 0.18 + 0.081*sl rn to qn t plh 0.80 0.70 + 0.051*sl 0.73 + 0.041*sl 0.76 + 0.036*sl t r 0.37 0.23 + 0.071*sl 0.24 + 0.068*sl 0.23 + 0.068*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-255 STD80/stdm80 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.96 0.91 + 0.028*sl 0.92 + 0.023*sl 0.94 + 0.020*sl t phl 1.00 0.93 + 0.031*sl 0.95 + 0.026*sl 0.97 + 0.023*sl t r 0.26 0.19 + 0.035*sl 0.19 + 0.034*sl 0.19 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl sck to q t plh 1.16 1.10 + 0.029*sl 1.12 + 0.023*sl 1.14 + 0.020*sl t phl 0.93 0.87 + 0.032*sl 0.89 + 0.027*sl 0.91 + 0.023*sl t r 0.29 0.22 + 0.034*sl 0.22 + 0.033*sl 0.22 + 0.034*sl t f 0.24 0.16 + 0.040*sl 0.17 + 0.038*sl 0.17 + 0.038*sl sn to q t plh 1.01 0.95 + 0.028*sl 0.97 + 0.023*sl 0.99 + 0.019*sl t r 0.26 0.19 + 0.035*sl 0.19 + 0.034*sl 0.20 + 0.033*sl rn to q t plh 0.45 0.40 + 0.028*sl 0.41 + 0.023*sl 0.43 + 0.019*sl t phl 0.49 0.42 + 0.031*sl 0.44 + 0.026*sl 0.46 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.039*sl 0.15 + 0.038*sl ck to qn t plh 1.39 1.33 + 0.031*sl 1.35 + 0.025*sl 1.37 + 0.021*sl t phl 1.46 1.40 + 0.029*sl 1.41 + 0.025*sl 1.43 + 0.023*sl t r 0.30 0.22 + 0.039*sl 0.23 + 0.036*sl 0.25 + 0.034*sl t f 0.26 0.17 + 0.043*sl 0.18 + 0.040*sl 0.19 + 0.039*sl sck to qn t plh 1.21 1.16 + 0.024*sl 1.17 + 0.021*sl 1.19 + 0.019*sl t phl 1.56 1.51 + 0.024*sl 1.52 + 0.022*sl 1.52 + 0.021*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.23 0.15 + 0.043*sl 0.17 + 0.036*sl 0.16 + 0.037*sl sn to qn t plh 0.55 0.48 + 0.033*sl 0.50 + 0.026*sl 0.53 + 0.022*sl t phl 0.53 0.47 + 0.033*sl 0.48 + 0.028*sl 0.50 + 0.025*sl t r 0.30 0.22 + 0.038*sl 0.23 + 0.036*sl 0.24 + 0.034*sl t f 0.24 0.16 + 0.042*sl 0.16 + 0.040*sl 0.17 + 0.039*sl rn to qn t plh 0.88 0.82 + 0.030*sl 0.84 + 0.025*sl 0.86 + 0.021*sl t r 0.30 0.22 + 0.039*sl 0.23 + 0.036*sl 0.24 + 0.034*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-256 sec asic fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd4s fd4sd2 fd4s fd4sd2 d ti te ck rn sn d ti te ck rn sn 0.3 0.5 1.0 0.5 0.9 0.7 0.3 0.5 0.9 0.5 0.9 0.7 9.3 10.0 stdm80 fd4s fd4sd2 fd4s fd4sd2 d ti te ck rn sn d ti te ck rn sn 0.6 0.6 1.1 0.6 1.6 1.6 0.6 0.6 1.1 0.6 1.6 1.6 9.3 10.0 q qn d ti te ck rn sn cl clb q cl clb cl cl clb qn clb sn sn rn rn d ti ck cl clb rn rn sn sn te truth table dtiteckrnsn q (n+1) qn (n+1) 0x0 11 0 1 1x0 11 1 0 x01 11 0 1 x11 11 1 0 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0 x x x 1 1 q (n) qn (n)
sec asic 3-257 STD80/stdm80 fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd4s fd4sd2 fd4s fd4sd2 pulse width low (ck) t pwl 0.87 0.87 1.01 1.01 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.96 0.96 input setup time (d to ck) t su 0.63 0.63 0.85 0.85 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.66 0.66 0.93 0.93 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.71 0.71 1.01 1.01 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.71 0.71 0.82 0.82 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.44 0.44 0.49 0.49
STD80/stdm80 3-258 sec asic fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4s STD80 fd4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.62 + 0.024*sl t phl 0.74 0.66 + 0.041*sl 0.67 + 0.038*sl 0.68 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q t plh 0.33 0.27 + 0.030*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.66 0.59 + 0.031*sl 0.61 + 0.026*sl 0.62 + 0.024*sl t r 0.23 0.14 + 0.049*sl 0.14 + 0.047*sl 0.10 + 0.052*sl ck to qn t plh 0.86 0.80 + 0.030*sl 0.81 + 0.025*sl 0.83 + 0.024*sl t phl 0.87 0.80 + 0.038*sl 0.80 + 0.037*sl 0.80 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.45 + 0.023*sl t r 0.22 0.12 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl sn to qn t plh 0.33 0.27 + 0.030*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.28 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.66 0.62 + 0.021*sl 0.63 + 0.015*sl 0.67 + 0.012*sl t phl 0.74 0.69 + 0.023*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to q t plh 0.35 0.30 + 0.022*sl 0.32 + 0.015*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.020*sl 0.33 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.67 0.63 + 0.021*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.023*sl 0.13 + 0.026*sl ck to qn t plh 0.93 0.89 + 0.018*sl 0.90 + 0.014*sl 0.93 + 0.012*sl t phl 0.95 0.91 + 0.018*sl 0.92 + 0.017*sl 0.91 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.19 0.12 + 0.031*sl 0.13 + 0.030*sl 0.09 + 0.034*sl rn to qn t plh 0.55 0.51 + 0.018*sl 0.52 + 0.014*sl 0.55 + 0.012*sl t r 0.19 0.14 + 0.025*sl 0.14 + 0.023*sl 0.12 + 0.026*sl sn to qn t plh 0.34 0.30 + 0.021*sl 0.32 + 0.015*sl 0.35 + 0.012*sl t phl 0.35 0.31 + 0.023*sl 0.31 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.14 + 0.022*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-259 STD80/stdm80 fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4s stdm80 fd4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.92 0.84 + 0.044*sl 0.86 + 0.037*sl 0.87 + 0.035*sl t phl 1.05 0.95 + 0.052*sl 0.97 + 0.046*sl 0.98 + 0.045*sl t r 0.31 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.39 + 0.045*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl sn to q t plh 0.94 0.85 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.19 + 0.067*sl 0.18 + 0.068*sl 0.17 + 0.069*sl ck to qn t plh 1.24 1.16 + 0.042*sl 1.18 + 0.036*sl 1.20 + 0.034*sl t phl 1.24 1.14 + 0.048*sl 1.15 + 0.045*sl 1.16 + 0.044*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn t plh 0.67 0.58 + 0.042*sl 0.60 + 0.036*sl 0.62 + 0.034*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl sn to qn t plh 0.44 0.35 + 0.042*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.38 + 0.046*sl 0.38 + 0.045*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.94 0.88 + 0.028*sl 0.90 + 0.023*sl 0.92 + 0.019*sl t phl 1.05 0.98 + 0.031*sl 1.00 + 0.026*sl 1.02 + 0.023*sl t r 0.25 0.18 + 0.035*sl 0.18 + 0.034*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.037*sl 0.16 + 0.038*sl rn to q t plh 0.45 0.39 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.18 + 0.034*sl t f 0.21 0.13 + 0.042*sl 0.14 + 0.039*sl 0.14 + 0.038*sl sn to q t plh 0.96 0.90 + 0.028*sl 0.92 + 0.022*sl 0.94 + 0.019*sl t r 0.25 0.18 + 0.037*sl 0.19 + 0.034*sl 0.19 + 0.033*sl ck to qn t plh 1.34 1.29 + 0.024*sl 1.30 + 0.021*sl 1.32 + 0.019*sl t phl 1.34 1.29 + 0.026*sl 1.30 + 0.023*sl 1.31 + 0.022*sl t r 0.24 0.17 + 0.038*sl 0.18 + 0.034*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.042*sl 0.16 + 0.037*sl 0.16 + 0.038*sl rn to qn t plh 0.76 0.71 + 0.025*sl 0.72 + 0.021*sl 0.74 + 0.019*sl t r 0.24 0.17 + 0.036*sl 0.18 + 0.034*sl 0.18 + 0.034*sl sn to qn t plh 0.45 0.40 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.16 + 0.037*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.13 + 0.039*sl 0.14 + 0.038*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-260 sec asic fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd4q fd4qd2 fd4q fd4qd2 d ck rn sn d ck rn sn 0.6 0.6 1.6 1.0 0.6 0.6 1.2 1.0 7.3 7.7 stdm80 fd4q fd4qd2 fd4q fd4qd2 d ck rn sn d ck rn sn 0.6 0.6 1.6 1.4 0.6 0.6 1.6 1.4 7.3 7.7 d ck q sn rn d ck cl clb q cl clb cl clb cl cl clb clb sn sn rn rn rn rn sn sn truth table d ck rn sn q (n+1) 0110 1111 xx101 xx010 xx000 x 1 1 q (n)
sec asic 3-261 STD80/stdm80 fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4q STD80 fd4qd2 parameter symbol STD80 stdm80 fd4q fd4qd2 fd4q fd4qd2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.96 0.96 input setup time (d to ck) t su 0.52 0.52 0.63 0.63 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.71 0.71 0.82 0.82 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.44 0.44 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.63 0.56 + 0.032*sl 0.58 + 0.026*sl 0.59 + 0.024*sl t phl 0.71 0.63 + 0.041*sl 0.64 + 0.037*sl 0.64 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.13 + 0.049*sl 0.09 + 0.052*sl t f 0.24 0.12 + 0.061*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q t plh 0.32 0.26 + 0.030*sl 0.27 + 0.025*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.65 0.58 + 0.032*sl 0.60 + 0.025*sl 0.61 + 0.024*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.64 0.60 + 0.020*sl 0.61 + 0.015*sl 0.64 + 0.012*sl t phl 0.71 0.66 + 0.023*sl 0.67 + 0.020*sl 0.68 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to q t plh 0.34 0.30 + 0.018*sl 0.31 + 0.015*sl 0.34 + 0.012*sl t phl 0.35 0.30 + 0.023*sl 0.31 + 0.019*sl 0.32 + 0.018*sl t r 0.19 0.14 + 0.022*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.66 0.62 + 0.021*sl 0.63 + 0.015*sl 0.66 + 0.012*sl t r 0.19 0.14 + 0.025*sl 0.15 + 0.023*sl 0.12 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-262 sec asic fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4q stdm80 fd4qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.90 0.81 + 0.043*sl 0.83 + 0.037*sl 0.85 + 0.034*sl t phl 1.01 0.91 + 0.052*sl 0.92 + 0.046*sl 0.94 + 0.044*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.31 0.16 + 0.077*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to q t plh 0.43 0.34 + 0.042*sl 0.36 + 0.036*sl 0.38 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.37 + 0.046*sl 0.38 + 0.045*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.081*sl 0.13 + 0.081*sl 0.13 + 0.082*sl sn to q t plh 0.92 0.84 + 0.043*sl 0.86 + 0.036*sl 0.87 + 0.034*sl t r 0.31 0.18 + 0.067*sl 0.18 + 0.068*sl 0.16 + 0.070*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.91 0.86 + 0.028*sl 0.87 + 0.022*sl 0.89 + 0.019*sl t phl 1.00 0.94 + 0.031*sl 0.96 + 0.026*sl 0.98 + 0.023*sl t r 0.25 0.18 + 0.034*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.040*sl 0.15 + 0.038*sl 0.16 + 0.037*sl rn to q t plh 0.44 0.38 + 0.027*sl 0.40 + 0.022*sl 0.42 + 0.019*sl t phl 0.45 0.39 + 0.030*sl 0.40 + 0.026*sl 0.42 + 0.023*sl t r 0.23 0.16 + 0.037*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.042*sl 0.14 + 0.038*sl 0.14 + 0.038*sl sn to q t plh 0.94 0.89 + 0.027*sl 0.90 + 0.022*sl 0.92 + 0.019*sl t r 0.25 0.18 + 0.036*sl 0.19 + 0.033*sl 0.19 + 0.033*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-263 STD80/stdm80 fd4x2 2-bit d flip-flop with reset, set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.90 1.09 pulse width high (ck) t pwh 0.85 0.85 pulse width low (rn) t pwl 0.87 0.82 pulse width low (sn) t pwl 0.87 0.96 input setup time (d0 to ck) t su 0.41 0.57 input hold time (d0 to ck) t hd 0.38 0.38 input setup time (d1 to ck) t su 0.41 0.57 input hold time (d1 to ck) t hd 0.38 0.38 recovery time (rn) t rc 0.33 0.33 input hold time (rn to ck) t hd 0.76 0.87 recovery time (sn) t rc 0.33 0.33 input hold time (sn to ck) t hd 0.49 0.60 q0 qn1 d0 d1 ck rn sn q1 qn0 truth table cell data dn ck rn sn qn (n+1) qnn (n+1) 01101 11110 xx10 1 0 xx01 0 1 xx00 0 0 x 1 1 qn (n) qnn (n) input load (sl) gate count STD80 dn ck rn sn 14.3 0.5 0.5 1.5 1.5 stdm80 dn ck rn sn 14.3 0.6 0.6 3.5 3.6
STD80/stdm80 3-264 sec asic fd4x2 2-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.71 0.65 + 0.031*sl 0.66 + 0.026*sl 0.68 + 0.024*sl t phl 0.88 0.79 + 0.041*sl 0.80 + 0.038*sl 0.81 + 0.037*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.065*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q0 t plh 0.34 0.27 + 0.033*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.37 0.29 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.067*sl 0.08 + 0.069*sl sn to q0 t plh 0.66 0.59 + 0.032*sl 0.61 + 0.026*sl 0.63 + 0.023*sl t r 0.23 0.14 + 0.046*sl 0.14 + 0.048*sl 0.10 + 0.052*sl ck to q1 t plh 0.71 0.64 + 0.032*sl 0.65 + 0.026*sl 0.68 + 0.024*sl t phl 0.87 0.79 + 0.041*sl 0.80 + 0.038*sl 0.80 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q1 t plh 0.33 0.27 + 0.032*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q1 t plh 0.65 0.59 + 0.032*sl 0.60 + 0.026*sl 0.62 + 0.023*sl t r 0.23 0.14 + 0.045*sl 0.13 + 0.048*sl 0.10 + 0.052*sl ck to qn0 t plh 1.00 0.94 + 0.030*sl 0.95 + 0.025*sl 0.96 + 0.024*sl t phl 0.93 0.86 + 0.038*sl 0.86 + 0.037*sl 0.86 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn0 t plh 0.49 0.43 + 0.030*sl 0.44 + 0.025*sl 0.46 + 0.023*sl t r 0.22 0.12 + 0.047*sl 0.12 + 0.048*sl 0.09 + 0.052*sl sn to qn0 t plh 0.33 0.27 + 0.032*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn1 t plh 0.99 0.93 + 0.030*sl 0.94 + 0.025*sl 0.95 + 0.024*sl t phl 0.93 0.85 + 0.037*sl 0.85 + 0.037*sl 0.85 + 0.037*sl t r 0.22 0.12 + 0.048*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn1 t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.45 + 0.023*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl sn to qn1 t plh 0.33 0.26 + 0.031*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.064*sl 0.10 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-265 STD80/stdm80 fd4x2 2-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.00 0.91 + 0.044*sl 0.93 + 0.037*sl 0.95 + 0.035*sl t phl 1.24 1.13 + 0.052*sl 1.15 + 0.046*sl 1.16 + 0.045*sl t r 0.32 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q0 t plh 0.45 0.36 + 0.043*sl 0.38 + 0.036*sl 0.40 + 0.034*sl t phl 0.48 0.37 + 0.051*sl 0.39 + 0.046*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl sn to q0 t plh 0.94 0.85 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.19 + 0.068*sl 0.19 + 0.067*sl 0.17 + 0.069*sl ck to q1 t plh 0.99 0.91 + 0.044*sl 0.93 + 0.037*sl 0.94 + 0.035*sl t phl 1.23 1.13 + 0.052*sl 1.14 + 0.046*sl 1.16 + 0.045*sl t r 0.31 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q1 t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.39 + 0.045*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl sn to q1 t plh 0.93 0.85 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.19 + 0.067*sl 0.18 + 0.067*sl 0.17 + 0.069*sl ck to qn0 t plh 1.43 1.35 + 0.042*sl 1.37 + 0.036*sl 1.38 + 0.034*sl t phl 1.31 1.22 + 0.049*sl 1.23 + 0.045*sl 1.23 + 0.044*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn0 t plh 0.68 0.60 + 0.042*sl 0.61 + 0.036*sl 0.63 + 0.034*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.15 + 0.070*sl sn to qn0 t plh 0.44 0.36 + 0.043*sl 0.38 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.046*sl 0.39 + 0.045*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.13 + 0.081*sl 0.13 + 0.082*sl ck to qn1 t plh 1.42 1.34 + 0.042*sl 1.36 + 0.036*sl 1.37 + 0.034*sl t phl 1.30 1.21 + 0.048*sl 1.22 + 0.045*sl 1.22 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.15 + 0.079*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn1 t plh 0.67 0.58 + 0.042*sl 0.60 + 0.036*sl 0.62 + 0.034*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.068*sl 0.15 + 0.070*sl sn to qn1 t plh 0.44 0.35 + 0.042*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.38 + 0.046*sl 0.38 + 0.045*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-266 sec asic fd4x4 4-bit d flip-flop with reset, set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.93 1.72 pulse width high (ck) t pwh 0.87 1.15 pulse width low (rn) t pwl 0.93 0.82 pulse width low (sn) t pwl 0.93 0.96 input setup time (d0 to ck) t su 0.33 0.44 input hold time (d0 to ck) t hd 0.60 0.63 input setup time (d1 to ck) t su 0.33 0.44 input hold time (d1 to ck) t hd 0.60 0.63 input setup time (d2 to ck) t su 0.33 0.44 input hold time (d2 to ck) t hd 0.60 0.63 input setup time (d3 to ck) t su 0.33 0.44 input hold time (d3 to ck) t hd 0.60 0.63 recovery time (rn) t rc 0.33 0.33 input hold time (rn to ck) t hd 0.93 1.04 recovery time (sn) t rc 0.33 0.33 input hold time (sn to ck) t hd 0.76 0.93 q0 q1 q2 q3 d0 d1 d2 d3 ck rn qn0 qn1 qn2 qn3 sn truth table cell data dn ck rn sn qn (n+1) qnn (n+1) 01101 11110 xx10 1 0 xx01 0 1 xx00 0 0 x 1 1 qn (n) qnn (n) input load (sl) gate count STD80 dn ck rn sn 27.7 0.5 0.5 4.6 4.6 stdm80 dn ck rn sn 27.7 0.6 0.6 7.1 7.5
sec asic 3-267 STD80/stdm80 fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.85 0.79 + 0.032*sl 0.80 + 0.026*sl 0.82 + 0.024*sl t phl 1.17 1.09 + 0.041*sl 1.10 + 0.038*sl 1.10 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.25 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q0 t plh 0.34 0.27 + 0.032*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl sn to q0 t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.63 + 0.023*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl ck to q1 t plh 0.85 0.79 + 0.032*sl 0.80 + 0.026*sl 0.82 + 0.024*sl t phl 1.17 1.09 + 0.041*sl 1.10 + 0.038*sl 1.10 + 0.037*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.25 0.12 + 0.060*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q1 t plh 0.34 0.27 + 0.032*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl sn to q1 t plh 0.65 0.59 + 0.032*sl 0.60 + 0.026*sl 0.63 + 0.023*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl ck to q2 t plh 0.85 0.79 + 0.031*sl 0.80 + 0.026*sl 0.83 + 0.024*sl t phl 1.17 1.09 + 0.041*sl 1.10 + 0.038*sl 1.10 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.25 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q2 t plh 0.34 0.27 + 0.032*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl sn to q2 t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.63 + 0.023*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl ck to q3 t plh 0.85 0.79 + 0.031*sl 0.80 + 0.026*sl 0.82 + 0.024*sl t phl 1.17 1.09 + 0.041*sl 1.09 + 0.038*sl 1.10 + 0.037*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q3 t plh 0.33 0.27 + 0.032*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q3 t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.62 + 0.023*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.048*sl 0.10 + 0.052*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-268 sec asic fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd4x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.29 1.23 + 0.030*sl 1.24 + 0.025*sl 1.25 + 0.024*sl t phl 1.07 1.00 + 0.038*sl 1.00 + 0.037*sl 1.00 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.11 + 0.066*sl 0.07 + 0.069*sl rn to qn0 t plh 0.49 0.43 + 0.030*sl 0.44 + 0.025*sl 0.46 + 0.023*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl sn to qn0 t plh 0.33 0.27 + 0.031*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn1 t plh 1.29 1.23 + 0.030*sl 1.24 + 0.025*sl 1.25 + 0.024*sl t phl 1.07 1.00 + 0.038*sl 1.00 + 0.037*sl 1.00 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.12 + 0.060*sl 0.11 + 0.066*sl 0.07 + 0.069*sl rn to qn1 t plh 0.49 0.43 + 0.030*sl 0.44 + 0.025*sl 0.46 + 0.023*sl t r 0.22 0.12 + 0.047*sl 0.12 + 0.048*sl 0.09 + 0.052*sl sn to qn1 t plh 0.33 0.27 + 0.032*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn2 t plh 1.29 1.23 + 0.030*sl 1.24 + 0.025*sl 1.25 + 0.024*sl t phl 1.07 1.00 + 0.037*sl 1.00 + 0.037*sl 1.00 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn2 t plh 0.49 0.43 + 0.030*sl 0.44 + 0.025*sl 0.46 + 0.023*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl sn to qn2 t plh 0.33 0.27 + 0.031*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn3 t plh 1.28 1.22 + 0.030*sl 1.23 + 0.025*sl 1.24 + 0.024*sl t phl 1.07 0.99 + 0.038*sl 0.99 + 0.037*sl 0.99 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn3 t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.45 + 0.023*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.049*sl 0.09 + 0.052*sl sn to qn3 t plh 0.33 0.26 + 0.031*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-269 STD80/stdm80 fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.17 1.08 + 0.044*sl 1.10 + 0.037*sl 1.12 + 0.035*sl t phl 1.65 1.55 + 0.052*sl 1.56 + 0.047*sl 1.58 + 0.045*sl t r 0.32 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.16 + 0.077*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q0 t plh 0.45 0.36 + 0.043*sl 0.38 + 0.036*sl 0.40 + 0.034*sl t phl 0.48 0.37 + 0.051*sl 0.39 + 0.046*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.13 + 0.081*sl 0.13 + 0.082*sl sn to q0 t plh 0.93 0.84 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.19 + 0.067*sl 0.19 + 0.067*sl 0.17 + 0.069*sl ck to q1 t plh 1.17 1.08 + 0.044*sl 1.10 + 0.037*sl 1.12 + 0.035*sl t phl 1.65 1.55 + 0.052*sl 1.57 + 0.046*sl 1.58 + 0.045*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.32 0.16 + 0.078*sl 0.16 + 0.079*sl 0.14 + 0.081*sl rn to q1 t plh 0.45 0.36 + 0.043*sl 0.38 + 0.036*sl 0.40 + 0.034*sl t phl 0.48 0.37 + 0.051*sl 0.39 + 0.046*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.070*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.13 + 0.081*sl 0.13 + 0.082*sl sn to q1 t plh 0.93 0.84 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.19 + 0.067*sl 0.19 + 0.067*sl 0.17 + 0.069*sl ck to q2 t plh 1.17 1.08 + 0.044*sl 1.10 + 0.037*sl 1.12 + 0.035*sl t phl 1.65 1.55 + 0.052*sl 1.57 + 0.046*sl 1.58 + 0.045*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.16 + 0.077*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q2 t plh 0.45 0.36 + 0.043*sl 0.38 + 0.036*sl 0.40 + 0.034*sl t phl 0.48 0.37 + 0.051*sl 0.39 + 0.046*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.070*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.13 + 0.081*sl 0.13 + 0.082*sl sn to q2 t plh 0.93 0.84 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.19 + 0.067*sl 0.19 + 0.067*sl 0.17 + 0.069*sl ck to q3 t plh 1.17 1.08 + 0.043*sl 1.10 + 0.037*sl 1.12 + 0.035*sl t phl 1.65 1.54 + 0.052*sl 1.56 + 0.046*sl 1.57 + 0.045*sl t r 0.32 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.16 + 0.078*sl 0.16 + 0.079*sl 0.14 + 0.081*sl rn to q3 t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.39 + 0.045*sl t r 0.30 0.17 + 0.068*sl 0.16 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.082*sl 0.14 + 0.081*sl 0.13 + 0.082*sl sn to q3 t plh 0.93 0.84 + 0.043*sl 0.86 + 0.037*sl 0.88 + 0.034*sl t r 0.32 0.19 + 0.067*sl 0.18 + 0.067*sl 0.17 + 0.069*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-270 sec asic fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd4x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.85 1.76 + 0.042*sl 1.78 + 0.036*sl 1.80 + 0.034*sl t phl 1.49 1.39 + 0.048*sl 1.40 + 0.045*sl 1.41 + 0.044*sl t r 0.31 0.17 + 0.068*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn0 t plh 0.68 0.60 + 0.042*sl 0.61 + 0.036*sl 0.63 + 0.034*sl t r 0.30 0.17 + 0.067*sl 0.17 + 0.068*sl 0.15 + 0.070*sl sn to qn0 t plh 0.44 0.36 + 0.042*sl 0.38 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.046*sl 0.39 + 0.045*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl ck to qn1 t plh 1.85 1.76 + 0.042*sl 1.78 + 0.036*sl 1.80 + 0.034*sl t phl 1.49 1.39 + 0.048*sl 1.40 + 0.045*sl 1.41 + 0.044*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn1 t plh 0.68 0.60 + 0.042*sl 0.61 + 0.036*sl 0.63 + 0.034*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.15 + 0.070*sl sn to qn1 t plh 0.44 0.36 + 0.042*sl 0.38 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.046*sl 0.39 + 0.045*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl ck to qn2 t plh 1.85 1.76 + 0.042*sl 1.78 + 0.036*sl 1.80 + 0.034*sl t phl 1.49 1.39 + 0.048*sl 1.40 + 0.045*sl 1.41 + 0.044*sl t r 0.31 0.17 + 0.068*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn2 t plh 0.68 0.59 + 0.042*sl 0.61 + 0.036*sl 0.63 + 0.034*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.068*sl 0.15 + 0.070*sl sn to qn2 t plh 0.44 0.36 + 0.042*sl 0.38 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.046*sl 0.39 + 0.045*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl ck to qn3 t plh 1.84 1.75 + 0.042*sl 1.77 + 0.036*sl 1.79 + 0.034*sl t phl 1.48 1.38 + 0.048*sl 1.39 + 0.045*sl 1.40 + 0.044*sl t r 0.30 0.17 + 0.068*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn3 t plh 0.67 0.58 + 0.042*sl 0.60 + 0.036*sl 0.62 + 0.034*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl sn to qn3 t plh 0.44 0.35 + 0.042*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.38 + 0.046*sl 0.38 + 0.045*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-271 STD80/stdm80 yfd4/yfd4d2 fast d flip-flop with reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 yfd4 yfd4d2 yfd4 yfd4d2 d ck rn sn d ck rn sn 1.8 0.5 1.2 1.3 1.7 0.5 2.0 2.4 6.3 7.7 stdm80 yfd4 yfd4d2 yfd4 yfd4d2 d ck rn sn d ck rn sn 2.0 0.6 1.7 2.0 2.0 0.6 2.8 3.1 6.3 7.7 parameter symbol STD80 stdm80 yfd4 yfd4d2 yfd4 yfd4d2 pulse width low (ck) t pwl 0.87 0.87 0.87 0.87 pulse width high (ck) t pwh 0.87 0.87 0.85 1.01 pulse width low (rn) t pwl 0.87 0.93 1.01 1.20 pulse width low (sn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.41 0.41 0.49 0.49 input hold time (d to ck) t hd 0.46 0.49 0.49 0.49 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.38 0.38 0.44 0.44 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.66 0.66 0.76 0.71 d ck q qn rn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn rn rn rn rn sn sn truth table dckrnsn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0011 x 1 1 q (n) qn (n)
STD80/stdm80 3-272 sec asic yfd4/yfd4d2 fast d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 yfd4 STD80 yfd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.51 + 0.030*sl 0.52 + 0.027*sl 0.54 + 0.025*sl t phl 0.58 0.50 + 0.041*sl 0.50 + 0.039*sl 0.51 + 0.039*sl t r 0.33 0.23 + 0.050*sl 0.23 + 0.050*sl 0.20 + 0.054*sl t f 0.39 0.25 + 0.069*sl 0.24 + 0.074*sl 0.20 + 0.078*sl rn to q t phl 0.60 0.52 + 0.041*sl 0.52 + 0.039*sl 0.52 + 0.038*sl t f 0.41 0.28 + 0.065*sl 0.26 + 0.072*sl 0.20 + 0.078*sl sn to q t plh 0.19 0.13 + 0.031*sl 0.14 + 0.025*sl 0.26 + 0.013*sl t phl 0.24 0.16 + 0.041*sl 0.17 + 0.038*sl 0.16 + 0.038*sl t r 0.33 0.24 + 0.041*sl 0.26 + 0.035*sl 0.35 + 0.025*sl t f 0.39 0.26 + 0.065*sl 0.24 + 0.072*sl 0.19 + 0.078*sl ck to qn t plh 0.76 0.59 + 0.082*sl 0.60 + 0.080*sl 0.60 + 0.080*sl t phl 0.76 0.61 + 0.073*sl 0.62 + 0.070*sl 0.64 + 0.068*sl t r 0.30 0.16 + 0.070*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.082*sl 0.14 + 0.082*sl rn to qn t plh 0.17 0.11 + 0.034*sl 0.12 + 0.026*sl 0.14 + 0.024*sl t phl 0.22 0.14 + 0.042*sl 0.15 + 0.038*sl 0.14 + 0.038*sl t r 0.30 0.21 + 0.043*sl 0.21 + 0.045*sl 0.21 + 0.045*sl t f 0.35 0.22 + 0.065*sl 0.20 + 0.071*sl 0.14 + 0.078*sl sn to qn t phl 0.38 0.23 + 0.074*sl 0.25 + 0.067*sl 0.37 + 0.054*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.080*sl 0.15 + 0.079*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.60 0.56 + 0.018*sl 0.56 + 0.016*sl 0.60 + 0.013*sl t phl 0.66 0.61 + 0.025*sl 0.62 + 0.022*sl 0.65 + 0.019*sl t r 0.31 0.27 + 0.020*sl 0.26 + 0.025*sl 0.24 + 0.027*sl t f 0.40 0.34 + 0.032*sl 0.33 + 0.035*sl 0.30 + 0.038*sl rn to q t phl 0.68 0.63 + 0.023*sl 0.64 + 0.021*sl 0.66 + 0.019*sl t f 0.40 0.34 + 0.032*sl 0.33 + 0.033*sl 0.29 + 0.038*sl sn to q t plh 0.18 0.14 + 0.016*sl 0.15 + 0.013*sl 0.20 + 0.008*sl t phl 0.18 0.14 + 0.022*sl 0.14 + 0.020*sl 0.15 + 0.019*sl t r 0.31 0.27 + 0.018*sl 0.26 + 0.022*sl 0.35 + 0.013*sl t f 0.31 0.25 + 0.034*sl 0.24 + 0.036*sl 0.21 + 0.039*sl ck to qn t plh 0.79 0.70 + 0.046*sl 0.71 + 0.043*sl 0.73 + 0.040*sl t phl 0.73 0.65 + 0.041*sl 0.66 + 0.037*sl 0.69 + 0.034*sl t r 0.23 0.16 + 0.033*sl 0.16 + 0.034*sl 0.15 + 0.035*sl t f 0.20 0.13 + 0.038*sl 0.12 + 0.041*sl 0.12 + 0.041*sl rn to qn t plh 0.13 0.09 + 0.020*sl 0.10 + 0.015*sl 0.13 + 0.012*sl t phl 0.17 0.12 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.019*sl t r 0.24 0.20 + 0.023*sl 0.20 + 0.022*sl 0.19 + 0.023*sl t f 0.26 0.20 + 0.032*sl 0.19 + 0.034*sl 0.14 + 0.039*sl sn to qn t phl 0.31 0.23 + 0.038*sl 0.24 + 0.035*sl 0.30 + 0.028*sl t f 0.20 0.12 + 0.038*sl 0.12 + 0.040*sl 0.13 + 0.039*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-273 STD80/stdm80 yfd4/yfd4d2 fast d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 yfd4 stdm80 yfd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.73 + 0.042*sl 0.74 + 0.038*sl 0.76 + 0.036*sl t phl 0.83 0.72 + 0.056*sl 0.73 + 0.052*sl 0.74 + 0.051*sl t r 0.45 0.31 + 0.071*sl 0.30 + 0.072*sl 0.29 + 0.073*sl t f 0.51 0.33 + 0.092*sl 0.32 + 0.094*sl 0.31 + 0.097*sl rn to q t phl 0.85 0.73 + 0.057*sl 0.75 + 0.053*sl 0.76 + 0.050*sl t f 0.55 0.38 + 0.086*sl 0.36 + 0.091*sl 0.33 + 0.095*sl sn to q t plh 0.25 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.30 0.20 + 0.050*sl 0.20 + 0.050*sl 0.19 + 0.050*sl t r 0.38 0.24 + 0.067*sl 0.24 + 0.066*sl 0.41 + 0.043*sl t f 0.45 0.27 + 0.093*sl 0.26 + 0.096*sl 0.24 + 0.098*sl ck to qn t plh 1.09 0.86 + 0.115*sl 0.87 + 0.112*sl 0.88 + 0.111*sl t phl 1.09 0.88 + 0.101*sl 0.90 + 0.097*sl 0.91 + 0.095*sl t r 0.40 0.22 + 0.093*sl 0.22 + 0.093*sl 0.21 + 0.094*sl t f 0.40 0.20 + 0.103*sl 0.19 + 0.106*sl 0.19 + 0.105*sl rn to qn t plh 0.23 0.15 + 0.038*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t phl 0.28 0.18 + 0.050*sl 0.18 + 0.049*sl 0.17 + 0.050*sl t r 0.34 0.21 + 0.066*sl 0.19 + 0.071*sl 0.20 + 0.070*sl t f 0.40 0.22 + 0.091*sl 0.21 + 0.095*sl 0.19 + 0.098*sl sn to qn t phl 0.51 0.32 + 0.095*sl 0.32 + 0.093*sl 0.35 + 0.090*sl t f 0.39 0.18 + 0.104*sl 0.18 + 0.104*sl 0.21 + 0.101*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.85 0.80 + 0.025*sl 0.81 + 0.023*sl 0.83 + 0.021*sl t phl 0.98 0.91 + 0.035*sl 0.92 + 0.032*sl 0.94 + 0.029*sl t r 0.40 0.33 + 0.036*sl 0.33 + 0.036*sl 0.33 + 0.036*sl t f 0.54 0.45 + 0.045*sl 0.45 + 0.047*sl 0.45 + 0.047*sl rn to q t phl 0.98 0.91 + 0.034*sl 0.92 + 0.031*sl 0.94 + 0.028*sl t f 0.55 0.46 + 0.045*sl 0.47 + 0.044*sl 0.47 + 0.044*sl sn to q t plh 0.22 0.18 + 0.019*sl 0.19 + 0.017*sl 0.19 + 0.017*sl t phl 0.24 0.18 + 0.028*sl 0.18 + 0.027*sl 0.19 + 0.026*sl t r 0.33 0.27 + 0.030*sl 0.26 + 0.034*sl 0.25 + 0.035*sl t f 0.36 0.26 + 0.049*sl 0.26 + 0.050*sl 0.26 + 0.050*sl ck to qn t plh 1.18 1.05 + 0.066*sl 1.06 + 0.062*sl 1.08 + 0.059*sl t phl 1.04 0.93 + 0.055*sl 0.94 + 0.052*sl 0.96 + 0.050*sl t r 0.30 0.21 + 0.045*sl 0.21 + 0.046*sl 0.21 + 0.046*sl t f 0.27 0.16 + 0.053*sl 0.16 + 0.052*sl 0.16 + 0.052*sl rn to qn t plh 0.17 0.13 + 0.023*sl 0.14 + 0.019*sl 0.15 + 0.017*sl t phl 0.21 0.15 + 0.028*sl 0.16 + 0.025*sl 0.16 + 0.025*sl t r 0.25 0.20 + 0.029*sl 0.19 + 0.033*sl 0.17 + 0.035*sl t f 0.28 0.19 + 0.044*sl 0.19 + 0.046*sl 0.18 + 0.047*sl sn to qn t phl 0.41 0.31 + 0.049*sl 0.31 + 0.047*sl 0.32 + 0.047*sl t f 0.26 0.15 + 0.053*sl 0.15 + 0.052*sl 0.15 + 0.053*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-274 sec asic fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd5 fd5d2 fd5 fd5d2 d ckn d ckn 0.5 0.5 0.5 0.5 5.3 6.0 stdm80 fd5 fd5d2 fd5 fd5d2 d ckn d ckn 0.6 0.6 0.6 0.6 5.3 6.0 parameter symbol STD80 stdm80 fd5 fd5d2 fd5 fd5d2 pulse width low (ckn) t pwl 0.87 0.87 0.85 0.85 pulse width high (ckn) t pwh 0.79 0.79 0.79 0.79 input setup time (d to ckn) t su 0.41 0.41 0.41 0.41 input hold time (d to ckn) t hd 0.44 0.44 0.55 0.55 d ckn q qn d ckn clbn cln q cln clbn cln clbn cln clbn clbn cln qn truth table d ckn q (n+1) qn (n+1) 001 110 x q (n) qn (n)
sec asic 3-275 STD80/stdm80 fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd5 STD80 fd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.73 0.68 + 0.028*sl 0.68 + 0.024*sl 0.69 + 0.024*sl t phl 0.68 0.60 + 0.041*sl 0.61 + 0.038*sl 0.62 + 0.037*sl t r 0.20 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ckn to qn t plh 0.72 0.67 + 0.025*sl 0.68 + 0.024*sl 0.67 + 0.024*sl t phl 0.90 0.82 + 0.038*sl 0.83 + 0.037*sl 0.82 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.74 0.70 + 0.018*sl 0.71 + 0.014*sl 0.73 + 0.012*sl t phl 0.67 0.63 + 0.023*sl 0.64 + 0.020*sl 0.65 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl ckn to qn t plh 0.79 0.76 + 0.013*sl 0.76 + 0.012*sl 0.77 + 0.012*sl t phl 0.96 0.92 + 0.018*sl 0.92 + 0.018*sl 0.92 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-276 sec asic fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd5 stdm80 fd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.04 0.96 + 0.038*sl 0.97 + 0.035*sl 0.98 + 0.034*sl t phl 0.94 0.83 + 0.052*sl 0.85 + 0.046*sl 0.86 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ckn to qn t plh 1.01 0.94 + 0.035*sl 0.94 + 0.033*sl 0.94 + 0.033*sl t phl 1.27 1.17 + 0.047*sl 1.18 + 0.045*sl 1.18 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.04 1.00 + 0.024*sl 1.01 + 0.020*sl 1.02 + 0.018*sl t phl 0.92 0.86 + 0.030*sl 0.88 + 0.026*sl 0.89 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.13 + 0.042*sl 0.15 + 0.038*sl 0.14 + 0.039*sl ckn to qn t plh 1.10 1.06 + 0.019*sl 1.06 + 0.017*sl 1.07 + 0.017*sl t phl 1.34 1.29 + 0.026*sl 1.30 + 0.023*sl 1.31 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-277 STD80/stdm80 fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd5s fd5sd2 fd5s fd5sd2 d ti te ckn d ti te ckn 0.3 0.5 0.9 0.5 0.3 0.5 0.9 0.5 7.0 7.7 stdm80 fd5s fd5sd2 fd5s fd5sd2 d ti te ckn d ti te ckn 0.6 0.4 1.1 0.6 0.6 0.4 1.1 0.6 7.0 7.7 parameter symbol STD80 stdm80 fd5s fd5sd2 fd5s fd5sd2 pulse width low (ckn) t pwl 0.87 0.87 0.96 0.98 pulse width high (ckn) t pwh 0.79 0.79 0.82 0.82 input setup time (d to ckn) t su 0.52 0.52 0.71 0.71 input hold time (d to ckn) t hd 0.38 0.38 0.41 0.41 input setup time (ti to ckn) t su 0.52 0.52 0.76 0.76 input hold time (ti to ckn) t hd 0.33 0.33 0.33 0.33 input setup time (te to ckn) t su 0.55 0.71 0.74 0.74 input hold time (te to ckn) t hd 0.33 0.33 0.33 0.33 q qn d ti te ckn d te ti clbn cln q cln clbn cln clbn clbn cln qn cln clbn ckn truth table d ti te ckn q (n+1) qn (n+1) 0x0 01 1x0 10 x01 01 x11 10 x x x q (n) qn (n)
STD80/stdm80 3-278 sec asic fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd5s STD80 fd5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.74 0.69 + 0.028*sl 0.69 + 0.024*sl 0.70 + 0.024*sl t phl 0.70 0.61 + 0.042*sl 0.62 + 0.038*sl 0.63 + 0.037*sl t r 0.20 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ckn to qn t plh 0.73 0.68 + 0.025*sl 0.69 + 0.024*sl 0.69 + 0.024*sl t phl 0.91 0.84 + 0.037*sl 0.84 + 0.037*sl 0.84 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.75 0.71 + 0.018*sl 0.72 + 0.013*sl 0.74 + 0.012*sl t phl 0.69 0.64 + 0.023*sl 0.65 + 0.020*sl 0.66 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl ckn to qn t plh 0.80 0.77 + 0.014*sl 0.78 + 0.012*sl 0.78 + 0.012*sl t phl 0.97 0.93 + 0.018*sl 0.93 + 0.018*sl 0.93 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-279 STD80/stdm80 fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd5s stdm80 fd5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.06 0.98 + 0.038*sl 0.99 + 0.035*sl 1.00 + 0.034*sl t phl 0.95 0.85 + 0.052*sl 0.87 + 0.046*sl 0.88 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ckn to qn t plh 1.02 0.96 + 0.035*sl 0.96 + 0.033*sl 0.96 + 0.033*sl t phl 1.29 1.19 + 0.047*sl 1.20 + 0.045*sl 1.20 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.06 1.01 + 0.024*sl 1.03 + 0.020*sl 1.04 + 0.018*sl t phl 0.94 0.88 + 0.030*sl 0.90 + 0.026*sl 0.91 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl ckn to qn t plh 1.11 1.08 + 0.018*sl 1.08 + 0.017*sl 1.09 + 0.017*sl t phl 1.36 1.31 + 0.025*sl 1.32 + 0.023*sl 1.33 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-280 sec asic fd5x4 4-bit d flip-flop with negative edge trigger logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ckn) t pwl 0.90 1.50 pulse width high (ckn) t pwh 1.01 1.42 input setup time (d0 to ckn) t su 0.33 0.33 input hold time (d0 to ckn) t hd 0.68 1.04 input setup time (d1 to ckn) t su 0.33 0.33 input hold time (d1 to ckn) t hd 0.68 1.04 input setup time (d2 to ckn) t su 0.33 0.33 input hold time (d2 to ckn) t hd 0.68 1.04 input setup time (d3 to ckn) t su 0.33 0.33 input hold time (d3 to ckn) t hd 0.68 1.04 d0 d1 d2 d3 ckn q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table cell data dn ckn qn (n+1) qnn (n+1) 001 110 x qn (n) qnn (n) input load (sl) gate count STD80 dn ckn 18.3 0.5 0.5 stdm80 dn ckn 18.3 0.6 0.6
sec asic 3-281 STD80/stdm80 fd5x4 4-bit d flip-flop with negative edge trigger switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q0 t plh 1.20 1.15 + 0.028*sl 1.15 + 0.024*sl 1.16 + 0.024*sl t phl 0.95 0.87 + 0.041*sl 0.88 + 0.038*sl 0.88 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ckn to q1 t plh 1.20 1.15 + 0.028*sl 1.15 + 0.024*sl 1.16 + 0.024*sl t phl 0.95 0.87 + 0.041*sl 0.88 + 0.038*sl 0.88 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ckn to q2 t plh 1.20 1.15 + 0.028*sl 1.15 + 0.024*sl 1.16 + 0.024*sl t phl 0.95 0.87 + 0.041*sl 0.88 + 0.038*sl 0.88 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ckn to q3 t plh 1.20 1.15 + 0.028*sl 1.15 + 0.024*sl 1.16 + 0.024*sl t phl 0.95 0.87 + 0.042*sl 0.88 + 0.038*sl 0.88 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.12 + 0.061*sl 0.10 + 0.066*sl 0.08 + 0.069*sl ckn to qn0 t plh 0.96 0.91 + 0.025*sl 0.92 + 0.024*sl 0.92 + 0.024*sl t phl 1.37 1.30 + 0.038*sl 1.30 + 0.037*sl 1.30 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ckn to qn1 t plh 0.96 0.91 + 0.025*sl 0.92 + 0.024*sl 0.92 + 0.024*sl t phl 1.37 1.30 + 0.038*sl 1.30 + 0.037*sl 1.30 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ckn to qn2 t plh 0.96 0.91 + 0.025*sl 0.92 + 0.024*sl 0.92 + 0.024*sl t phl 1.37 1.30 + 0.038*sl 1.30 + 0.037*sl 1.30 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ckn to qn3 t plh 0.96 0.91 + 0.025*sl 0.91 + 0.023*sl 0.91 + 0.024*sl t phl 1.37 1.30 + 0.038*sl 1.30 + 0.037*sl 1.30 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-282 sec asic fd5x4 4-bit d flip-flop with negative edge trigger switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q0 t plh 1.75 1.67 + 0.039*sl 1.68 + 0.035*sl 1.69 + 0.034*sl t phl 1.34 1.23 + 0.052*sl 1.25 + 0.046*sl 1.26 + 0.044*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl ckn to q1 t plh 1.75 1.67 + 0.039*sl 1.68 + 0.035*sl 1.69 + 0.034*sl t phl 1.34 1.23 + 0.052*sl 1.25 + 0.046*sl 1.26 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl ckn to q2 t plh 1.75 1.67 + 0.039*sl 1.68 + 0.035*sl 1.69 + 0.034*sl t phl 1.34 1.23 + 0.052*sl 1.25 + 0.046*sl 1.26 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl ckn to q3 t plh 1.75 1.67 + 0.038*sl 1.68 + 0.035*sl 1.69 + 0.034*sl t phl 1.34 1.23 + 0.052*sl 1.25 + 0.046*sl 1.26 + 0.044*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.081*sl ckn to qn0 t plh 1.38 1.31 + 0.035*sl 1.32 + 0.033*sl 1.32 + 0.033*sl t phl 1.98 1.88 + 0.046*sl 1.89 + 0.045*sl 1.89 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl ckn to qn1 t plh 1.38 1.31 + 0.035*sl 1.32 + 0.033*sl 1.32 + 0.033*sl t phl 1.98 1.88 + 0.046*sl 1.89 + 0.045*sl 1.89 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl ckn to qn2 t plh 1.38 1.31 + 0.035*sl 1.32 + 0.033*sl 1.32 + 0.033*sl t phl 1.98 1.88 + 0.046*sl 1.89 + 0.045*sl 1.89 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl ckn to qn3 t plh 1.38 1.31 + 0.035*sl 1.32 + 0.033*sl 1.31 + 0.033*sl t phl 1.97 1.88 + 0.047*sl 1.89 + 0.045*sl 1.89 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-283 STD80/stdm80 fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd6 fd6d2 fd6 fd6d2 d ckn rn d ckn rn 0.5 0.5 0.9 0.5 0.5 0.9 6.3 7.0 stdm80 fd6 fd6d2 fd6 fd6d2 d ckn rn d ckn rn 0.6 0.6 1.2 0.6 0.6 1.2 6.3 7.0 parameter symbol STD80 stdm80 fd6 fd6d2 fd6 fd6d2 pulse width low (ckn) t pwl 0.87 0.87 0.96 0.98 pulse width high (ckn) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ckn) t su 0.49 0.49 0.52 0.52 input hold time (d to ckn) t hd 0.52 0.52 0.52 0.52 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ckn) t hd 0.82 0.82 0.93 0.93 d ckn q qn rn d ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln rn rn rn rn truth table d ckn rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
STD80/stdm80 3-284 sec asic fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd6 STD80 fd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.79 0.73 + 0.031*sl 0.74 + 0.026*sl 0.77 + 0.024*sl t phl 0.71 0.63 + 0.042*sl 0.64 + 0.038*sl 0.64 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.066*sl 0.08 + 0.069*sl rn to q t phl 0.37 0.28 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ckn to qn t plh 0.75 0.70 + 0.026*sl 0.70 + 0.024*sl 0.70 + 0.024*sl t phl 0.97 0.90 + 0.036*sl 0.90 + 0.037*sl 0.90 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.41 0.35 + 0.026*sl 0.36 + 0.023*sl 0.36 + 0.024*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.06 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.81 0.77 + 0.021*sl 0.78 + 0.015*sl 0.81 + 0.012*sl t phl 0.70 0.65 + 0.023*sl 0.66 + 0.020*sl 0.68 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.11 + 0.031*sl 0.09 + 0.034*sl rn to q t phl 0.36 0.31 + 0.023*sl 0.32 + 0.020*sl 0.33 + 0.018*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.09 + 0.034*sl ckn to qn t plh 0.82 0.79 + 0.014*sl 0.79 + 0.012*sl 0.80 + 0.012*sl t phl 1.05 1.02 + 0.017*sl 1.02 + 0.017*sl 1.01 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.47 0.44 + 0.014*sl 0.45 + 0.012*sl 0.45 + 0.012*sl t r 0.15 0.11 + 0.019*sl 0.10 + 0.023*sl 0.07 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-285 STD80/stdm80 fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd6 stdm80 fd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.14 1.05 + 0.044*sl 1.07 + 0.038*sl 1.09 + 0.035*sl t phl 0.98 0.87 + 0.052*sl 0.89 + 0.046*sl 0.90 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl rn to q t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.14 + 0.081*sl ckn to qn t plh 1.05 0.98 + 0.035*sl 0.99 + 0.033*sl 0.99 + 0.033*sl t phl 1.37 1.28 + 0.047*sl 1.29 + 0.044*sl 1.29 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn t plh 0.55 0.48 + 0.035*sl 0.48 + 0.033*sl 0.48 + 0.033*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.15 1.09 + 0.028*sl 1.11 + 0.023*sl 1.13 + 0.019*sl t phl 0.97 0.90 + 0.031*sl 0.92 + 0.026*sl 0.94 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl rn to q t phl 0.46 0.40 + 0.031*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t f 0.22 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl ckn to qn t plh 1.14 1.10 + 0.019*sl 1.11 + 0.017*sl 1.11 + 0.017*sl t phl 1.48 1.44 + 0.024*sl 1.44 + 0.022*sl 1.45 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.63 0.60 + 0.019*sl 0.60 + 0.017*sl 0.61 + 0.017*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-286 sec asic fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd6s fd6sd2 fd6s fd6sd2 d ti te ckn rn d ti te ckn rn 0.3 0.5 0.9 0.5 0.9 0.3 0.5 0.9 0.5 0.9 8.0 8.7 stdm80 fd6s fd6sd2 fd6s fd6sd2 d ti te ckn rn d ti te ckn rn 0.6 0.4 1.1 0.6 1.2 0.6 0.4 1.1 0.6 1.2 8.0 8.7 q qn d ti te ckn rn ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln rn rn rn rn d te ti truth table d ti te ckn rn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx001 x x x 1 q (n) qn (n)
sec asic 3-287 STD80/stdm80 fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd6s STD80 fd6sd2 parameter symbol STD80 stdm80 fd6s fd6sd2 fd6s fd6sd2 pulse width low (ckn) t pwl 0.87 0.87 0.98 1.01 pulse width high (ckn) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to ckn) t su 0.71 0.71 0.74 0.74 input hold time (d to ckn) t hd 0.44 0.44 0.41 0.41 input setup time (ti to ckn) t su 0.79 0.79 0.79 0.79 input hold time (ti to ckn) t hd 0.36 0.36 0.33 0.33 input setup time (te to ckn) t su 0.74 0.74 0.74 0.74 input hold time (te to ckn) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ckn) t hd 0.82 0.82 0.93 0.93 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.80 0.74 + 0.032*sl 0.75 + 0.026*sl 0.77 + 0.024*sl t phl 0.72 0.64 + 0.042*sl 0.65 + 0.038*sl 0.65 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl rn to q t phl 0.37 0.28 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ckn to qn t plh 0.76 0.71 + 0.026*sl 0.72 + 0.024*sl 0.71 + 0.024*sl t phl 0.98 0.91 + 0.037*sl 0.91 + 0.037*sl 0.90 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.41 0.35 + 0.026*sl 0.36 + 0.023*sl 0.36 + 0.024*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.82 0.77 + 0.021*sl 0.79 + 0.015*sl 0.82 + 0.012*sl t phl 0.71 0.67 + 0.023*sl 0.67 + 0.020*sl 0.69 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.11 + 0.031*sl 0.09 + 0.034*sl rn to q t phl 0.36 0.31 + 0.023*sl 0.32 + 0.020*sl 0.33 + 0.018*sl t f 0.18 0.11 + 0.033*sl 0.11 + 0.031*sl 0.09 + 0.034*sl ckn to qn t plh 0.83 0.80 + 0.014*sl 0.80 + 0.012*sl 0.81 + 0.012*sl t phl 1.06 1.03 + 0.018*sl 1.03 + 0.017*sl 1.02 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.47 0.44 + 0.014*sl 0.45 + 0.012*sl 0.45 + 0.012*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-288 sec asic fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd6s stdm80 fd6sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.15 1.06 + 0.044*sl 1.08 + 0.038*sl 1.10 + 0.034*sl t phl 0.99 0.89 + 0.052*sl 0.91 + 0.046*sl 0.92 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl rn to q t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ckn to qn t plh 1.07 1.00 + 0.035*sl 1.00 + 0.033*sl 1.00 + 0.033*sl t phl 1.38 1.29 + 0.047*sl 1.30 + 0.045*sl 1.30 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn t plh 0.55 0.48 + 0.035*sl 0.48 + 0.033*sl 0.48 + 0.033*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.16 1.11 + 0.028*sl 1.12 + 0.023*sl 1.14 + 0.019*sl t phl 0.98 0.92 + 0.031*sl 0.94 + 0.026*sl 0.96 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl rn to q t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t f 0.22 0.13 + 0.042*sl 0.14 + 0.039*sl 0.15 + 0.038*sl ckn to qn t plh 1.16 1.12 + 0.019*sl 1.12 + 0.017*sl 1.13 + 0.017*sl t phl 1.50 1.45 + 0.024*sl 1.45 + 0.022*sl 1.46 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.63 0.60 + 0.019*sl 0.60 + 0.017*sl 0.61 + 0.017*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-289 STD80/stdm80 fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fd7 fd7d2 fd7 fd7d2 d ckn sn d ckn sn 0.5 0.5 0.7 0.5 0.5 0.7 6.7 7.3 stdm80 fd7 fd7d2 fd7 fd7d2 d ckn sn d ckn sn 0.6 0.6 1.1 0.6 0.6 1.1 6.7 7.3 parameter symbol STD80 stdm80 fd7 fd7d2 fd7 fd7d2 pulse width low (ckn) t pwl 0.87 0.87 0.96 0.96 pulse width high (ckn) t pwh 0.79 0.79 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.96 0.96 input setup time (d to ckn) t su 0.55 0.55 0.57 0.57 input hold time (d to ckn) t hd 0.52 0.52 0.52 0.52 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ckn) t hd 0.49 0.49 0.55 0.55 d ckn q qn sn d ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln sn sn sn sn truth table d ckn sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
STD80/stdm80 3-290 sec asic fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd7 STD80 fd7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.74 0.68 + 0.028*sl 0.69 + 0.024*sl 0.70 + 0.024*sl t phl 0.73 0.64 + 0.041*sl 0.65 + 0.038*sl 0.66 + 0.037*sl t r 0.20 0.12 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.56 + 0.024*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ckn to qn t plh 0.83 0.77 + 0.030*sl 0.78 + 0.025*sl 0.80 + 0.024*sl t phl 0.94 0.87 + 0.038*sl 0.87 + 0.037*sl 0.87 + 0.037*sl t r 0.21 0.12 + 0.046*sl 0.12 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl sn to qn t phl 0.35 0.27 + 0.040*sl 0.27 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.10 + 0.064*sl 0.10 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.75 0.71 + 0.018*sl 0.72 + 0.014*sl 0.74 + 0.012*sl t phl 0.72 0.67 + 0.023*sl 0.68 + 0.020*sl 0.69 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.61 0.58 + 0.018*sl 0.59 + 0.013*sl 0.60 + 0.012*sl t r 0.17 0.12 + 0.022*sl 0.12 + 0.022*sl 0.09 + 0.026*sl ckn to qn t plh 0.90 0.87 + 0.018*sl 0.88 + 0.014*sl 0.90 + 0.012*sl t phl 1.00 0.96 + 0.019*sl 0.96 + 0.018*sl 0.96 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to qn t phl 0.35 0.30 + 0.023*sl 0.31 + 0.019*sl 0.32 + 0.018*sl t f 0.17 0.10 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-291 STD80/stdm80 fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd7 stdm80 fd7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.06 0.98 + 0.038*sl 0.99 + 0.035*sl 1.00 + 0.034*sl t phl 1.00 0.90 + 0.051*sl 0.91 + 0.046*sl 0.92 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.082*sl sn to q t plh 0.87 0.79 + 0.039*sl 0.81 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.063*sl 0.15 + 0.068*sl 0.13 + 0.071*sl ckn to qn t plh 1.18 1.09 + 0.041*sl 1.11 + 0.036*sl 1.13 + 0.034*sl t phl 1.34 1.25 + 0.048*sl 1.26 + 0.045*sl 1.26 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.14 + 0.080*sl 0.13 + 0.080*sl 0.12 + 0.082*sl sn to qn t phl 0.45 0.35 + 0.051*sl 0.37 + 0.046*sl 0.37 + 0.045*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.06 1.01 + 0.024*sl 1.03 + 0.020*sl 1.04 + 0.018*sl t phl 0.99 0.93 + 0.031*sl 0.94 + 0.026*sl 0.96 + 0.023*sl t r 0.21 0.15 + 0.032*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.14 + 0.038*sl sn to q t plh 0.87 0.83 + 0.024*sl 0.84 + 0.020*sl 0.86 + 0.017*sl t r 0.22 0.15 + 0.032*sl 0.15 + 0.032*sl 0.14 + 0.033*sl ckn to qn t plh 1.27 1.23 + 0.024*sl 1.24 + 0.021*sl 1.25 + 0.019*sl t phl 1.42 1.36 + 0.027*sl 1.37 + 0.024*sl 1.39 + 0.022*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.038*sl 0.14 + 0.038*sl sn to qn t phl 0.45 0.39 + 0.030*sl 0.40 + 0.025*sl 0.42 + 0.023*sl t f 0.21 0.12 + 0.042*sl 0.13 + 0.039*sl 0.13 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-292 sec asic fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd7s fd7sd2 fd7s fd7sd2 d ti te ckn sn d ti te ckn sn 0.3 0.5 0.9 0.5 0.7 0.3 0.5 0.9 0.5 0.7 8.3 9.0 stdm80 fd7s fd7sd2 fd7s fd7sd2 d ti te ckn sn d ti te ckn sn 0.6 0.4 1.1 0.6 1.1 0.6 0.4 1.1 0.6 1.1 8.3 9.0 q qn d ti te ckn sn clbn cln q clbn cln clbn clbn cln qn cln sn sn ckn cln clbn sn sn d te ti truth table d ti te ckn sn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx010 x x x 1 q (n) qn (n)
sec asic 3-293 STD80/stdm80 fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd7s STD80 fd7sd2 parameter symbol STD80 stdm80 fd7s fd7sd2 fd7s fd7sd2 pulse width low (ckn) t pwl 0.87 0.87 0.96 0.98 pulse width high (ckn) t pwh 0.79 0.79 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.96 0.96 input setup time (d to ckn) t su 0.79 0.79 0.79 0.79 input hold time (d to ckn) t hd 0.44 0.44 0.41 0.41 input setup time (ti to ckn) t su 0.85 0.85 0.85 0.85 input hold time (ti to ckn) t hd 0.36 0.36 0.33 0.33 input setup time (te to ckn) t su 0.79 0.79 0.82 0.82 input hold time (te to ckn) t hd 0.33 0.33 0.33 0.33 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ckn) t hd 0.55 0.55 0.60 0.60 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.75 0.69 + 0.028*sl 0.70 + 0.024*sl 0.71 + 0.024*sl t phl 0.74 0.65 + 0.041*sl 0.66 + 0.038*sl 0.67 + 0.037*sl t r 0.20 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.56 + 0.023*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl ckn to qn t plh 0.84 0.79 + 0.029*sl 0.80 + 0.025*sl 0.81 + 0.024*sl t phl 0.95 0.88 + 0.038*sl 0.88 + 0.037*sl 0.88 + 0.037*sl t r 0.21 0.12 + 0.046*sl 0.12 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl sn to qn t phl 0.35 0.27 + 0.040*sl 0.27 + 0.038*sl 0.28 + 0.037*sl t f 0.23 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.75 0.72 + 0.018*sl 0.73 + 0.014*sl 0.74 + 0.012*sl t phl 0.73 0.68 + 0.023*sl 0.69 + 0.020*sl 0.71 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.18 0.11 + 0.032*sl 0.12 + 0.031*sl 0.09 + 0.034*sl sn to q t plh 0.61 0.58 + 0.018*sl 0.59 + 0.013*sl 0.60 + 0.012*sl t r 0.17 0.12 + 0.022*sl 0.12 + 0.022*sl 0.09 + 0.026*sl ckn to qn t plh 0.91 0.88 + 0.018*sl 0.89 + 0.014*sl 0.91 + 0.012*sl t phl 1.01 0.97 + 0.020*sl 0.97 + 0.018*sl 0.97 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to qn t phl 0.35 0.30 + 0.023*sl 0.31 + 0.019*sl 0.32 + 0.018*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-294 sec asic fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd7s stdm80 fd7sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.07 0.99 + 0.038*sl 1.01 + 0.035*sl 1.01 + 0.034*sl t phl 1.02 0.91 + 0.052*sl 0.93 + 0.046*sl 0.94 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.082*sl sn to q t plh 0.87 0.79 + 0.039*sl 0.81 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.14 + 0.068*sl 0.13 + 0.071*sl ckn to qn t plh 1.19 1.11 + 0.041*sl 1.13 + 0.036*sl 1.14 + 0.034*sl t phl 1.36 1.26 + 0.048*sl 1.27 + 0.045*sl 1.28 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.12 + 0.082*sl sn to qn t phl 0.45 0.35 + 0.051*sl 0.37 + 0.046*sl 0.37 + 0.045*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.08 1.03 + 0.024*sl 1.04 + 0.020*sl 1.06 + 0.018*sl t phl 1.01 0.94 + 0.031*sl 0.96 + 0.026*sl 0.98 + 0.023*sl t r 0.21 0.15 + 0.031*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.039*sl 0.15 + 0.038*sl 0.15 + 0.038*sl sn to q t plh 0.87 0.83 + 0.024*sl 0.84 + 0.020*sl 0.85 + 0.018*sl t r 0.21 0.15 + 0.033*sl 0.15 + 0.032*sl 0.14 + 0.033*sl ckn to qn t plh 1.29 1.24 + 0.024*sl 1.25 + 0.021*sl 1.27 + 0.019*sl t phl 1.43 1.38 + 0.027*sl 1.39 + 0.024*sl 1.40 + 0.022*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.034*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.038*sl 0.14 + 0.038*sl sn to qn t phl 0.45 0.39 + 0.030*sl 0.40 + 0.025*sl 0.42 + 0.023*sl t f 0.21 0.12 + 0.041*sl 0.13 + 0.039*sl 0.13 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-295 STD80/stdm80 fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd8 fd8d2 fd8 fd8d2 d ckn rn sn d ckn rn sn 0.5 0.5 0.9 0.7 0.5 0.5 0.9 0.7 7.7 8.3 stdm80 fd8 fd8d2 fd8 fd8d2 d ckn rn sn d ckn rn sn 0.6 0.6 1.6 1.6 0.6 0.6 1.6 1.6 7.7 8.3 d ckn q qn rn sn d ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln sn sn rn rn rn rn sn sn truth table d ckn rn sn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0000 x 1 1 q (n) qn (n)
STD80/stdm80 3-296 sec asic fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd8 fd8d2 fd8 fd8d2 pulse width low (ckn) t pwl 0.87 0.87 0.93 0.98 pulse width high (ckn) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.96 0.98 input setup time (d to ckn) t su 0.60 0.60 0.60 0.60 input hold time (d to ckn) t hd 0.49 0.49 0.49 0.49 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ckn) t hd 0.82 0.82 0.93 0.93 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ckn) t hd 0.49 0.49 0.55 0.55
sec asic 3-297 STD80/stdm80 fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd8 STD80 fd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.76 0.70 + 0.032*sl 0.71 + 0.026*sl 0.73 + 0.024*sl t phl 0.73 0.65 + 0.041*sl 0.66 + 0.038*sl 0.67 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q t plh 0.33 0.27 + 0.030*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.14 + 0.045*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.66 0.59 + 0.032*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl ckn to qn t plh 0.85 0.79 + 0.030*sl 0.80 + 0.025*sl 0.82 + 0.024*sl t phl 0.99 0.91 + 0.038*sl 0.91 + 0.037*sl 0.91 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.45 + 0.024*sl t r 0.22 0.12 + 0.047*sl 0.12 + 0.049*sl 0.09 + 0.052*sl sn to qn t plh 0.33 0.26 + 0.031*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.28 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.78 0.74 + 0.021*sl 0.75 + 0.015*sl 0.78 + 0.012*sl t phl 0.73 0.68 + 0.023*sl 0.69 + 0.020*sl 0.70 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to q t plh 0.34 0.31 + 0.019*sl 0.31 + 0.016*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.67 0.63 + 0.021*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t r 0.20 0.15 + 0.024*sl 0.15 + 0.023*sl 0.13 + 0.026*sl ckn to qn t plh 0.92 0.89 + 0.018*sl 0.89 + 0.015*sl 0.92 + 0.012*sl t phl 1.07 1.03 + 0.019*sl 1.03 + 0.017*sl 1.03 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.19 0.12 + 0.032*sl 0.13 + 0.030*sl 0.09 + 0.034*sl rn to qn t plh 0.55 0.51 + 0.018*sl 0.52 + 0.014*sl 0.55 + 0.012*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl sn to qn t plh 0.34 0.30 + 0.020*sl 0.32 + 0.015*sl 0.35 + 0.012*sl t phl 0.35 0.31 + 0.023*sl 0.31 + 0.020*sl 0.33 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
STD80/stdm80 3-298 sec asic fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd8 stdm80 fd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.09 1.00 + 0.044*sl 1.02 + 0.037*sl 1.04 + 0.035*sl t phl 1.01 0.91 + 0.052*sl 0.92 + 0.047*sl 0.94 + 0.045*sl t r 0.32 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.046*sl 0.39 + 0.045*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl sn to q t plh 0.94 0.85 + 0.044*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.18 + 0.067*sl 0.18 + 0.068*sl 0.17 + 0.069*sl ckn to qn t plh 1.21 1.12 + 0.042*sl 1.14 + 0.036*sl 1.15 + 0.034*sl t phl 1.40 1.31 + 0.048*sl 1.32 + 0.045*sl 1.32 + 0.044*sl t r 0.30 0.17 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.081*sl rn to qn t plh 0.67 0.59 + 0.042*sl 0.60 + 0.036*sl 0.62 + 0.033*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl sn to qn t plh 0.44 0.35 + 0.042*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.38 + 0.046*sl 0.38 + 0.045*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.11 1.05 + 0.028*sl 1.07 + 0.023*sl 1.09 + 0.019*sl t phl 1.00 0.94 + 0.032*sl 0.96 + 0.026*sl 0.98 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.040*sl 0.16 + 0.038*sl 0.16 + 0.038*sl rn to q t plh 0.45 0.39 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.031*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.18 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.039*sl sn to q t plh 0.96 0.90 + 0.028*sl 0.92 + 0.022*sl 0.94 + 0.019*sl t r 0.25 0.18 + 0.034*sl 0.18 + 0.035*sl 0.19 + 0.033*sl ckn to qn t plh 1.30 1.25 + 0.025*sl 1.26 + 0.021*sl 1.28 + 0.019*sl t phl 1.51 1.46 + 0.026*sl 1.47 + 0.023*sl 1.48 + 0.022*sl t r 0.24 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.033*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.038*sl 0.16 + 0.037*sl rn to qn t plh 0.76 0.71 + 0.025*sl 0.72 + 0.021*sl 0.74 + 0.019*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.18 + 0.034*sl sn to qn t plh 0.45 0.40 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.13 + 0.039*sl 0.14 + 0.038*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-299 STD80/stdm80 fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fd8s fd8sd2 fd8s fd8sd2 d ti te ckn rn sn d ti te ckn rn sn 0.3 0.5 0.9 0.5 0.7 0.7 0.3 0.5 0.9 0.5 0.7 0.7 9.3 10.0 stdm80 fd8s fd8sd2 fd8s fd8sd2 d ti te ckn rn sn d ti te ckn rn sn 0.6 0.4 1.1 0.6 1.6 1.6 0.6 0.4 1.1 0.6 1.6 1.6 9.3 10.0 q qn d ti te ckn rn sn clbn cln q clbn cln clbn clbn cln qn cln sn sn rn rn d ti ckn cln clbn rn rn sn sn te truth table d ti te ckn rn sn q (n+1) qn (n+1) 0x0 11 0 1 1x0 11 1 0 x01 11 0 1 x11 11 1 0 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0 x x x 1 1 q (n) qn (n)
STD80/stdm80 3-300 sec asic fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fd8s fd8sd2 fd8s fd8sd2 pulse width low (ckn) t pwl 0.87 0.87 0.96 0.98 pulse width high (ckn) t pwh 0.82 0.82 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.96 0.98 input setup time (d to ckn) t su 0.82 0.82 0.85 0.85 input hold time (d to ckn) t hd 0.41 0.41 0.38 0.38 input setup time (ti to ckn) t su 0.87 0.87 0.90 0.90 input hold time (ti to ckn) t hd 0.33 0.33 0.33 0.33 input setup time (te to ckn) t su 0.85 0.85 0.85 0.85 input hold time (te to ckn) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ckn) t hd 0.82 0.82 0.98 0.98 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ckn) t hd 0.49 0.49 0.55 0.55
sec asic 3-301 STD80/stdm80 fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fd8s STD80 fd8sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.78 0.71 + 0.032*sl 0.72 + 0.026*sl 0.75 + 0.024*sl t phl 0.74 0.66 + 0.041*sl 0.67 + 0.038*sl 0.67 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q t plh 0.33 0.27 + 0.031*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to q t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.62 + 0.023*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.048*sl 0.10 + 0.052*sl ckn to qn t plh 0.86 0.80 + 0.030*sl 0.81 + 0.025*sl 0.82 + 0.024*sl t phl 1.00 0.92 + 0.037*sl 0.92 + 0.037*sl 0.92 + 0.037*sl t r 0.22 0.12 + 0.047*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.45 + 0.024*sl t r 0.22 0.12 + 0.046*sl 0.12 + 0.049*sl 0.09 + 0.052*sl sn to qn t plh 0.33 0.26 + 0.031*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.061*sl 0.10 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.79 0.75 + 0.021*sl 0.76 + 0.015*sl 0.79 + 0.012*sl t phl 0.74 0.69 + 0.023*sl 0.70 + 0.020*sl 0.71 + 0.018*sl t r 0.20 0.15 + 0.024*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to q t plh 0.34 0.31 + 0.019*sl 0.31 + 0.016*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to q t plh 0.67 0.63 + 0.021*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t r 0.20 0.15 + 0.025*sl 0.15 + 0.023*sl 0.13 + 0.026*sl ckn to qn t plh 0.93 0.89 + 0.018*sl 0.90 + 0.014*sl 0.93 + 0.012*sl t phl 1.08 1.04 + 0.019*sl 1.04 + 0.017*sl 1.04 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.19 0.12 + 0.032*sl 0.13 + 0.030*sl 0.09 + 0.034*sl rn to qn t plh 0.55 0.51 + 0.018*sl 0.52 + 0.014*sl 0.55 + 0.012*sl t r 0.19 0.15 + 0.022*sl 0.14 + 0.023*sl 0.12 + 0.026*sl sn to qn t plh 0.34 0.30 + 0.020*sl 0.32 + 0.015*sl 0.35 + 0.012*sl t phl 0.35 0.31 + 0.023*sl 0.31 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
STD80/stdm80 3-302 sec asic fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fd8s stdm80 fd8sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.11 1.02 + 0.044*sl 1.04 + 0.037*sl 1.06 + 0.035*sl t phl 1.03 0.92 + 0.052*sl 0.94 + 0.046*sl 0.95 + 0.045*sl t r 0.32 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.39 + 0.045*sl t r 0.30 0.17 + 0.068*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl sn to q t plh 0.94 0.85 + 0.043*sl 0.87 + 0.037*sl 0.89 + 0.034*sl t r 0.32 0.18 + 0.067*sl 0.18 + 0.067*sl 0.17 + 0.070*sl ckn to qn t plh 1.22 1.13 + 0.042*sl 1.15 + 0.036*sl 1.17 + 0.034*sl t phl 1.42 1.32 + 0.048*sl 1.33 + 0.045*sl 1.34 + 0.044*sl t r 0.30 0.17 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.30 0.15 + 0.079*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn t plh 0.67 0.59 + 0.042*sl 0.60 + 0.036*sl 0.62 + 0.034*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl sn to qn t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.38 + 0.046*sl 0.38 + 0.045*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.12 1.07 + 0.028*sl 1.08 + 0.023*sl 1.11 + 0.019*sl t phl 1.02 0.96 + 0.031*sl 0.97 + 0.026*sl 0.99 + 0.023*sl t r 0.25 0.18 + 0.037*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.037*sl 0.15 + 0.038*sl rn to q t plh 0.45 0.39 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.16 + 0.037*sl 0.17 + 0.035*sl 0.18 + 0.033*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.039*sl sn to q t plh 0.95 0.90 + 0.028*sl 0.91 + 0.023*sl 0.94 + 0.019*sl t r 0.25 0.18 + 0.035*sl 0.19 + 0.034*sl 0.19 + 0.033*sl ckn to qn t plh 1.32 1.26 + 0.025*sl 1.28 + 0.021*sl 1.29 + 0.019*sl t phl 1.53 1.47 + 0.027*sl 1.49 + 0.023*sl 1.50 + 0.021*sl t r 0.24 0.17 + 0.037*sl 0.17 + 0.035*sl 0.18 + 0.034*sl t f 0.23 0.15 + 0.040*sl 0.16 + 0.038*sl 0.16 + 0.037*sl rn to qn t plh 0.76 0.71 + 0.025*sl 0.72 + 0.021*sl 0.73 + 0.019*sl t r 0.24 0.17 + 0.037*sl 0.18 + 0.034*sl 0.18 + 0.034*sl sn to qn t plh 0.45 0.40 + 0.027*sl 0.41 + 0.022*sl 0.44 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.13 + 0.039*sl 0.14 + 0.038*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-303 STD80/stdm80 fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fds2 fds2d2 fds2 fds2d2 d crn ck d crn ck 0.5 0.5 0.5 0.5 0.5 0.5 6.0 6.7 stdm80 fds2 fds2d2 fds2 fds2d2 d crn ck d crn ck 0.4 0.5 0.6 0.4 0.5 0.6 6.0 6.7 parameter symbol STD80 stdm80 fds2 fds2d2 fds2 fds2d2 pulse width low (ck) t pwl 0.87 0.87 0.90 0.90 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 input setup time (d to ck) t su 0.68 0.68 0.68 0.68 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (crn to ck) t su 0.68 0.68 0.68 0.68 input hold time (crn to ck) t hd 0.33 0.33 0.33 0.33 d crn ck q qn d ck cl clb q cl clb clb cl clb cl cl clb qn crn truth table d crn ck q (n+1) qn (n+1) 01 01 11 10 x0 01 x x q (n) qn (n)
STD80/stdm80 3-304 sec asic fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fds2 STD80 fds2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.52 + 0.028*sl 0.53 + 0.024*sl 0.53 + 0.024*sl t phl 0.66 0.58 + 0.041*sl 0.59 + 0.038*sl 0.60 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn t plh 0.70 0.65 + 0.025*sl 0.66 + 0.024*sl 0.65 + 0.024*sl t phl 0.74 0.67 + 0.037*sl 0.67 + 0.037*sl 0.67 + 0.037*sl t r 0.19 0.09 + 0.045*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.54 + 0.018*sl 0.55 + 0.014*sl 0.57 + 0.012*sl t phl 0.65 0.61 + 0.023*sl 0.61 + 0.020*sl 0.63 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl ck to qn t plh 0.77 0.74 + 0.013*sl 0.74 + 0.012*sl 0.75 + 0.012*sl t phl 0.80 0.76 + 0.018*sl 0.76 + 0.018*sl 0.76 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-305 STD80/stdm80 fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fds2 stdm80 fds2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.75 + 0.038*sl 0.76 + 0.035*sl 0.77 + 0.034*sl t phl 0.94 0.84 + 0.052*sl 0.85 + 0.046*sl 0.86 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ck to qn t plh 1.01 0.94 + 0.034*sl 0.94 + 0.033*sl 0.94 + 0.033*sl t phl 1.05 0.96 + 0.047*sl 0.96 + 0.045*sl 0.97 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.78 + 0.024*sl 0.79 + 0.020*sl 0.80 + 0.018*sl t phl 0.92 0.86 + 0.031*sl 0.88 + 0.026*sl 0.90 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl ck to qn t plh 1.10 1.06 + 0.019*sl 1.06 + 0.017*sl 1.07 + 0.017*sl t phl 1.12 1.07 + 0.026*sl 1.08 + 0.023*sl 1.09 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-306 sec asic fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fds2cs fds2csd2 fds2cs fds2csd2 si sck d crn ck si sck d crn ck 0.7 1.8 0.7 0.6 0.6 0.6 1.8 0.7 0.6 0.6 9.3 9.7 stdm80 fds2cs fds2csd2 fds2cs fds2csd2 si sck d crn ck si sck d crn ck 0.6 2.0 0.4 0.5 0.6 0.6 2.0 0.4 0.5 0.6 9.3 9.7 q qn si crn ck sck d d cl clb q clb cl clb cl cl clb qn crn sck sckb sck sckb sckb sck sckb sck si cl clb sck sck sckb ck truth table si sck d crn ck q (n+1) qn (n+1) x001 01 x011 10 0 x1001 1 x1010 xxx0 01
sec asic 3-307 STD80/stdm80 fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fds2cs fds2csd2 fds2cs fds2csd2 pulse width low (ck) t pwl 0.87 0.87 0.87 0.87 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 pulse width low (sck) t pwl 0.87 0.87 0.82 0.82 pulse width high (sck) t pwh 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.55 0.37 0.68 0.68 input hold time (d to ck) t hd 0.36 0.36 0.33 0.33 input setup time (si to sck) t su 0.68 0.68 0.82 0.82 input hold time (si to sck) t hd 0.33 0.33 0.33 0.33 input setup time (crn to ck) t su 0.33 0.00 0.33 0.33 input hold time (crn to ck) t hd 0.33 0.00 0.33 0.33
STD80/stdm80 3-308 sec asic fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fds2cs STD80 fds2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.52 + 0.029*sl 0.53 + 0.024*sl 0.54 + 0.024*sl t phl 0.66 0.58 + 0.041*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.10 + 0.066*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sck to q t plh 0.65 0.59 + 0.030*sl 0.60 + 0.025*sl 0.61 + 0.024*sl t phl 0.59 0.50 + 0.042*sl 0.51 + 0.038*sl 0.52 + 0.037*sl t r 0.23 0.14 + 0.045*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.76 0.70 + 0.029*sl 0.71 + 0.025*sl 0.72 + 0.024*sl t phl 0.82 0.74 + 0.041*sl 0.74 + 0.038*sl 0.76 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.11 + 0.067*sl 0.09 + 0.069*sl sck to qn t plh 0.62 0.57 + 0.025*sl 0.57 + 0.023*sl 0.57 + 0.024*sl t phl 0.82 0.74 + 0.037*sl 0.74 + 0.037*sl 0.74 + 0.037*sl t r 0.19 0.09 + 0.048*sl 0.09 + 0.050*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.068*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.59 0.55 + 0.018*sl 0.56 + 0.014*sl 0.58 + 0.012*sl t phl 0.65 0.60 + 0.023*sl 0.61 + 0.020*sl 0.63 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sck to q t plh 0.66 0.63 + 0.019*sl 0.64 + 0.014*sl 0.66 + 0.012*sl t phl 0.58 0.54 + 0.023*sl 0.55 + 0.020*sl 0.56 + 0.018*sl t r 0.19 0.15 + 0.022*sl 0.15 + 0.022*sl 0.11 + 0.026*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.031*sl 0.09 + 0.034*sl ck to qn t plh 0.82 0.79 + 0.017*sl 0.79 + 0.014*sl 0.81 + 0.012*sl t phl 0.87 0.83 + 0.021*sl 0.83 + 0.019*sl 0.84 + 0.018*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.022*sl 0.11 + 0.026*sl t f 0.19 0.12 + 0.033*sl 0.13 + 0.031*sl 0.10 + 0.034*sl sck to qn t plh 0.69 0.66 + 0.014*sl 0.67 + 0.012*sl 0.67 + 0.012*sl t phl 0.89 0.85 + 0.017*sl 0.85 + 0.017*sl 0.84 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-309 STD80/stdm80 fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fds2cs stdm80 fds2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.83 0.76 + 0.038*sl 0.77 + 0.035*sl 0.77 + 0.034*sl t phl 0.93 0.83 + 0.051*sl 0.84 + 0.047*sl 0.86 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.070*sl 0.13 + 0.071*sl t f 0.31 0.14 + 0.081*sl 0.14 + 0.081*sl 0.14 + 0.082*sl sck to q t plh 0.98 0.90 + 0.041*sl 0.91 + 0.036*sl 0.93 + 0.034*sl t phl 0.82 0.72 + 0.053*sl 0.74 + 0.046*sl 0.75 + 0.044*sl t r 0.32 0.19 + 0.065*sl 0.18 + 0.067*sl 0.16 + 0.070*sl t f 0.32 0.16 + 0.078*sl 0.16 + 0.079*sl 0.14 + 0.081*sl ck to qn t plh 1.08 0.99 + 0.042*sl 1.01 + 0.036*sl 1.03 + 0.033*sl t phl 1.16 1.05 + 0.054*sl 1.07 + 0.048*sl 1.09 + 0.046*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.32 0.15 + 0.084*sl 0.16 + 0.082*sl 0.16 + 0.082*sl sck to qn t plh 0.89 0.82 + 0.034*sl 0.82 + 0.033*sl 0.82 + 0.033*sl t phl 1.21 1.11 + 0.046*sl 1.12 + 0.044*sl 1.12 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.071*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.84 0.79 + 0.024*sl 0.81 + 0.020*sl 0.82 + 0.018*sl t phl 0.92 0.86 + 0.031*sl 0.88 + 0.026*sl 0.89 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.039*sl sck to q t plh 1.00 0.95 + 0.026*sl 0.97 + 0.021*sl 0.99 + 0.018*sl t phl 0.82 0.76 + 0.031*sl 0.77 + 0.026*sl 0.79 + 0.023*sl t r 0.25 0.18 + 0.033*sl 0.19 + 0.031*sl 0.18 + 0.033*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl ck to qn t plh 1.16 1.12 + 0.023*sl 1.13 + 0.020*sl 1.14 + 0.018*sl t phl 1.23 1.17 + 0.029*sl 1.19 + 0.025*sl 1.20 + 0.023*sl t r 0.23 0.16 + 0.037*sl 0.17 + 0.033*sl 0.17 + 0.033*sl t f 0.23 0.15 + 0.042*sl 0.15 + 0.040*sl 0.16 + 0.039*sl sck to qn t plh 0.98 0.95 + 0.018*sl 0.95 + 0.017*sl 0.95 + 0.017*sl t phl 1.31 1.26 + 0.024*sl 1.27 + 0.022*sl 1.27 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-310 sec asic fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fds2s fds2sd2 fds2s fds2sd2 d crn ti te ck d crn ti te ck 0.5 0.5 0.5 0.8 0.5 0.5 0.5 0.5 0.8 0.5 8.0 8.7 stdm80 fds2s fds2sd2 fds2s fds2sd2 d crn ti te ck d crn ti te ck 0.5 0.4 0.6 1.1 0.6 0.5 0.4 0.6 1.1 0.6 8.0 8.7 parameter symbol STD80 stdm80 fds2s fds2sd2 fds2s fds2sd2 pulse width low (ck) t pwl 0.87 0.87 0.79 0.79 pulse width high (ck) t pwh 0.79 0.79 0.77 0.77 input setup time (d to ck) t su 0.90 0.90 0.74 0.74 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (crn to ck) t su 0.90 0.90 0.74 0.74 input hold time (crn to ck) t hd 0.33 0.00 0.33 0.33 input setup time (ti to ck) t su 0.87 0.87 0.71 0.71 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.74 0.74 0.63 0.63 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 q qn d te ck crn ti qn q clb cl cl clb cl clb clb cl d crn te ti cl ck clb truth table d crn ti te ck q (n+1) qn (n+1) 01x0 01 11x0 10 x0x0 01 xx01 01 xx11 10 x x x x q (n) qn (n)
sec asic 3-311 STD80/stdm80 fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fds2s STD80 fds2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.70 0.65 + 0.025*sl 0.65 + 0.024*sl 0.65 + 0.024*sl t phl 0.74 0.67 + 0.038*sl 0.67 + 0.037*sl 0.67 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl ck to qn t plh 0.57 0.52 + 0.028*sl 0.53 + 0.025*sl 0.53 + 0.024*sl t phl 0.66 0.58 + 0.041*sl 0.59 + 0.038*sl 0.59 + 0.037*sl t r 0.20 0.11 + 0.046*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.76 0.73 + 0.014*sl 0.74 + 0.012*sl 0.74 + 0.012*sl t phl 0.80 0.76 + 0.019*sl 0.76 + 0.018*sl 0.76 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl ck to qn t plh 0.58 0.54 + 0.018*sl 0.55 + 0.014*sl 0.57 + 0.012*sl t phl 0.65 0.60 + 0.023*sl 0.61 + 0.020*sl 0.63 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-312 sec asic fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fds2s stdm80 fds2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.00 0.93 + 0.035*sl 0.94 + 0.033*sl 0.94 + 0.033*sl t phl 1.05 0.95 + 0.047*sl 0.96 + 0.044*sl 0.96 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl ck to qn t plh 0.82 0.75 + 0.038*sl 0.76 + 0.035*sl 0.76 + 0.034*sl t phl 0.93 0.83 + 0.052*sl 0.85 + 0.046*sl 0.86 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.09 1.05 + 0.019*sl 1.06 + 0.017*sl 1.06 + 0.017*sl t phl 1.12 1.07 + 0.025*sl 1.08 + 0.023*sl 1.09 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl ck to qn t plh 0.82 0.78 + 0.024*sl 0.79 + 0.020*sl 0.80 + 0.018*sl t phl 0.92 0.86 + 0.030*sl 0.87 + 0.026*sl 0.89 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-313 STD80/stdm80 fds3/fds3d2 d flip-flop with synchronous set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fds3 fds3d2 fds3 fds3d2 d csn ck d csn ck 0.6 0.4 0.6 1.0 1.0 1.0 6.3 7.0 stdm80 fds3 fds3d2 fds3 fds3d2 d csn ck d csn ck 0.6 0.7 0.6 0.6 0.7 0.6 6.3 7.0 parameter symbol STD80 stdm80 fds2 fds2d2 fds2 fds2d2 pulse width low (ck) t pwl 0.87 0.87 0.82 0.82 pulse width high (ck) t pwh 0.87 0.87 0.82 0.82 input setup time (d to ck) t su 0.33 0.33 0.33 0.33 input hold time (d to ck) t hd 0.33 0.33 0.33 0.33 input setup time (csn to ck) t su 0.52 0.52 0.66 0.66 input hold time (csn to ck) t hd 0.33 0.33 0.33 0.33 d csn ck q qn qn q clb cl cl clb cl clb clb cl cl ck clb d csn truth table d csn ck q (n+1) qn (n+1) 01 01 11 10 x0 10 x x q (n) qn (n)
STD80/stdm80 3-314 sec asic fds3/fds3d2 d flip-flop with synchronous set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fds3 STD80 fds3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.71 0.66 + 0.025*sl 0.66 + 0.024*sl 0.66 + 0.024*sl t phl 0.75 0.67 + 0.038*sl 0.67 + 0.037*sl 0.67 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl ck to qn t plh 0.58 0.52 + 0.029*sl 0.53 + 0.024*sl 0.54 + 0.024*sl t phl 0.67 0.59 + 0.041*sl 0.59 + 0.038*sl 0.60 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.77 0.74 + 0.013*sl 0.75 + 0.012*sl 0.75 + 0.012*sl t phl 0.80 0.76 + 0.018*sl 0.77 + 0.018*sl 0.76 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.07 + 0.034*sl ck to qn t plh 0.58 0.55 + 0.018*sl 0.56 + 0.014*sl 0.57 + 0.012*sl t phl 0.66 0.61 + 0.023*sl 0.62 + 0.020*sl 0.63 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-315 STD80/stdm80 fds3/fds3d2 d flip-flop with synchronous clear, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fds3 stdm80 fds3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.01 0.94 + 0.035*sl 0.95 + 0.033*sl 0.95 + 0.033*sl t phl 1.05 0.96 + 0.047*sl 0.97 + 0.044*sl 0.97 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl ck to qn t plh 0.83 0.75 + 0.038*sl 0.76 + 0.035*sl 0.77 + 0.034*sl t phl 0.94 0.84 + 0.052*sl 0.86 + 0.046*sl 0.87 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.10 1.07 + 0.018*sl 1.07 + 0.017*sl 1.07 + 0.017*sl t phl 1.13 1.08 + 0.025*sl 1.08 + 0.023*sl 1.09 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.041*sl 0.13 + 0.038*sl 0.13 + 0.038*sl ck to qn t plh 0.83 0.78 + 0.024*sl 0.79 + 0.020*sl 0.81 + 0.018*sl t phl 0.93 0.87 + 0.030*sl 0.88 + 0.026*sl 0.90 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-316 sec asic fg1 d flip-flop with ck enable logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.87 0.90 pulse width high (ck) t pwh 0.82 0.82 pulse width low (e) t pwl 0.87 0.85 pulse width high (e) t pwh 0.85 0.85 input setup time (d to ck) t su 0.44 0.46 input hold time (d to ck) t hd 0.36 0.33 input setup time (d to e) t su 0.44 0.44 input hold time (d to e) t hd 0.36 0.36 dq qn e ck cke ck ckeb e d ckeb cke cke ckeb ckeb cke qn cke ckeb q rn rn rn rn truth table cell data d e ck q (n+1) qn (n+1) 01 01 11 10 x 0 x q (n) qn (n) x x q (n) qn (n) input load (sl) gate count STD80 deck 5.7 0.5 0.5 0.5 stdm80 deck 5.7 0.6 0.4 0.5
sec asic 3-317 STD80/stdm80 fg1 d flip-flop with ck enable switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fg1 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fg1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.63 0.58 + 0.028*sl 0.59 + 0.024*sl 0.59 + 0.024*sl t phl 0.72 0.64 + 0.041*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.20 0.11 + 0.046*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl e to q t plh 0.66 0.60 + 0.028*sl 0.61 + 0.024*sl 0.61 + 0.024*sl t phl 0.74 0.66 + 0.041*sl 0.66 + 0.038*sl 0.67 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn t plh 0.76 0.71 + 0.025*sl 0.71 + 0.024*sl 0.71 + 0.024*sl t phl 0.80 0.73 + 0.037*sl 0.73 + 0.037*sl 0.73 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl e to qn t plh 0.78 0.73 + 0.025*sl 0.73 + 0.024*sl 0.73 + 0.024*sl t phl 0.82 0.75 + 0.038*sl 0.75 + 0.037*sl 0.75 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.92 0.84 + 0.038*sl 0.86 + 0.035*sl 0.86 + 0.034*sl t phl 1.03 0.93 + 0.052*sl 0.94 + 0.046*sl 0.95 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl e to q t plh 0.93 0.86 + 0.038*sl 0.87 + 0.035*sl 0.88 + 0.034*sl t phl 1.04 0.94 + 0.052*sl 0.96 + 0.046*sl 0.97 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ck to qn t plh 1.10 1.03 + 0.035*sl 1.03 + 0.033*sl 1.03 + 0.033*sl t phl 1.15 1.05 + 0.046*sl 1.06 + 0.045*sl 1.06 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl e to qn t plh 1.11 1.04 + 0.035*sl 1.04 + 0.034*sl 1.05 + 0.033*sl t phl 1.16 1.07 + 0.047*sl 1.07 + 0.045*sl 1.08 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-318 sec asic fg1x4 4-bit d flip-flop with ck enable logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.87 1.86 pulse width high (ck) t pwh 0.87 1.37 pulse width low (e) t pwl 0.87 1.83 pulse width high (e) t pwh 0.87 1.39 input setup time (d0 to ck) t su 0.33 0.33 input hold time (d0 to ck) t hd 0.74 0.87 input setup time (d0 to e) t su 0.33 0.33 input hold time (d0 to e) t hd 0.76 0.90 input setup time (d1 to ck) t su 0.33 0.33 input hold time (d1 to ck) t hd 0.74 0.87 input setup time (d1 to e) t su 0.33 0.33 input hold time (d1 to e) t hd 0.76 0.90 input setup time (d2 to ck) t su 0.33 0.33 input hold time (d2 to ck) t hd 0.76 0.87 input setup time (d2 to e) t su 0.33 0.33 input hold time (d2 to e) t hd 0.76 0.90 input setup time (d3 to ck) t su 0.33 0.33 input hold time (d3 to ck) t hd 0.74 0.87 input setup time (d3 to e) t su 0.33 0.33 input hold time (d3 to e) t hd 0.76 0.90 d0 d1 d2 d3 q0 q1 q2 q3 qn0 qn1 qn2 qn3 e ck truth table cell data dn e ck qn (n+1) qnn (n+1) 01 0 1 11 1 0 x 0 x qn (n) qnn (n) x x qn (n) qnn (n) input load (sl) gate count STD80 dn e ck 18.7 0.5 0.5 0.5 stdm80 dn e ck 18.7 0.6 0.4 0.5
sec asic 3-319 STD80/stdm80 fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fg1x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.94 0.88 + 0.028*sl 0.89 + 0.024*sl 0.90 + 0.024*sl t phl 1.25 1.16 + 0.041*sl 1.17 + 0.038*sl 1.18 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl e to q0 t plh 0.96 0.91 + 0.028*sl 0.91 + 0.024*sl 0.92 + 0.024*sl t phl 1.27 1.19 + 0.041*sl 1.19 + 0.038*sl 1.20 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to q1 t plh 0.94 0.88 + 0.028*sl 0.89 + 0.025*sl 0.90 + 0.024*sl t phl 1.25 1.16 + 0.041*sl 1.17 + 0.038*sl 1.18 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl e to q1 t plh 0.96 0.91 + 0.029*sl 0.91 + 0.024*sl 0.92 + 0.024*sl t phl 1.27 1.19 + 0.041*sl 1.19 + 0.038*sl 1.20 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to q2 t plh 0.94 0.88 + 0.028*sl 0.89 + 0.024*sl 0.90 + 0.024*sl t phl 1.25 1.16 + 0.041*sl 1.17 + 0.038*sl 1.18 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl e to q2 t plh 0.96 0.91 + 0.028*sl 0.91 + 0.024*sl 0.92 + 0.024*sl t phl 1.27 1.19 + 0.041*sl 1.19 + 0.038*sl 1.20 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl ck to q3 t plh 0.94 0.88 + 0.028*sl 0.89 + 0.024*sl 0.90 + 0.024*sl t phl 1.24 1.16 + 0.041*sl 1.17 + 0.038*sl 1.18 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl e to q3 t plh 0.96 0.91 + 0.028*sl 0.91 + 0.024*sl 0.92 + 0.024*sl t phl 1.27 1.19 + 0.041*sl 1.19 + 0.038*sl 1.20 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl ck to qn0 t plh 1.28 1.23 + 0.025*sl 1.24 + 0.024*sl 1.24 + 0.024*sl t phl 1.10 1.03 + 0.038*sl 1.03 + 0.037*sl 1.03 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.07 + 0.069*sl e to qn0 t plh 1.31 1.26 + 0.025*sl 1.26 + 0.024*sl 1.26 + 0.024*sl t phl 1.13 1.05 + 0.038*sl 1.05 + 0.037*sl 1.05 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-320 sec asic fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fg1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn1 t plh 1.28 1.23 + 0.025*sl 1.24 + 0.023*sl 1.23 + 0.024*sl t phl 1.10 1.03 + 0.038*sl 1.03 + 0.037*sl 1.03 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl e to qn1 t plh 1.31 1.26 + 0.025*sl 1.26 + 0.024*sl 1.26 + 0.024*sl t phl 1.13 1.05 + 0.038*sl 1.05 + 0.037*sl 1.05 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ck to qn2 t plh 1.28 1.23 + 0.025*sl 1.24 + 0.023*sl 1.23 + 0.024*sl t phl 1.10 1.03 + 0.038*sl 1.03 + 0.037*sl 1.03 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.07 + 0.069*sl e to qn2 t plh 1.31 1.26 + 0.025*sl 1.26 + 0.024*sl 1.26 + 0.024*sl t phl 1.13 1.05 + 0.038*sl 1.05 + 0.037*sl 1.05 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl ck to qn3 t plh 1.28 1.23 + 0.025*sl 1.23 + 0.024*sl 1.23 + 0.024*sl t phl 1.10 1.03 + 0.038*sl 1.03 + 0.037*sl 1.03 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl e to qn3 t plh 1.30 1.25 + 0.025*sl 1.26 + 0.023*sl 1.26 + 0.024*sl t phl 1.13 1.05 + 0.038*sl 1.05 + 0.037*sl 1.05 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-321 STD80/stdm80 fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fg1x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.32 1.24 + 0.039*sl 1.25 + 0.035*sl 1.26 + 0.034*sl t phl 1.80 1.70 + 0.052*sl 1.71 + 0.046*sl 1.72 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.081*sl e to q0 t plh 1.33 1.26 + 0.038*sl 1.27 + 0.035*sl 1.27 + 0.034*sl t phl 1.81 1.71 + 0.052*sl 1.72 + 0.046*sl 1.74 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl ck to q1 t plh 1.32 1.24 + 0.038*sl 1.25 + 0.035*sl 1.26 + 0.034*sl t phl 1.80 1.70 + 0.052*sl 1.71 + 0.046*sl 1.73 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.15 + 0.079*sl 0.14 + 0.080*sl 0.14 + 0.081*sl e to q1 t plh 1.33 1.26 + 0.038*sl 1.27 + 0.035*sl 1.27 + 0.034*sl t phl 1.81 1.71 + 0.052*sl 1.73 + 0.046*sl 1.74 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.15 + 0.079*sl 0.14 + 0.080*sl 0.14 + 0.081*sl ck to q2 t plh 1.32 1.24 + 0.038*sl 1.25 + 0.035*sl 1.26 + 0.034*sl t phl 1.80 1.70 + 0.052*sl 1.71 + 0.046*sl 1.72 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.081*sl e to q2 t plh 1.33 1.26 + 0.038*sl 1.27 + 0.035*sl 1.27 + 0.034*sl t phl 1.81 1.71 + 0.052*sl 1.72 + 0.046*sl 1.74 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.081*sl ck to q3 t plh 1.32 1.24 + 0.039*sl 1.25 + 0.035*sl 1.26 + 0.034*sl t phl 1.80 1.69 + 0.052*sl 1.71 + 0.046*sl 1.72 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.15 + 0.079*sl 0.14 + 0.080*sl 0.13 + 0.081*sl e to q3 t plh 1.33 1.25 + 0.039*sl 1.27 + 0.035*sl 1.27 + 0.034*sl t phl 1.81 1.71 + 0.052*sl 1.72 + 0.046*sl 1.74 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl ck to qn0 t plh 1.87 1.80 + 0.035*sl 1.81 + 0.033*sl 1.81 + 0.033*sl t phl 1.55 1.45 + 0.046*sl 1.46 + 0.045*sl 1.46 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl e to qn0 t plh 1.88 1.81 + 0.035*sl 1.82 + 0.033*sl 1.82 + 0.033*sl t phl 1.56 1.47 + 0.046*sl 1.47 + 0.045*sl 1.48 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-322 sec asic fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fg1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn1 t plh 1.87 1.80 + 0.034*sl 1.80 + 0.034*sl 1.81 + 0.033*sl t phl 1.55 1.45 + 0.046*sl 1.46 + 0.045*sl 1.46 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl e to qn1 t plh 1.88 1.81 + 0.035*sl 1.82 + 0.033*sl 1.82 + 0.033*sl t phl 1.56 1.47 + 0.046*sl 1.47 + 0.044*sl 1.47 + 0.044*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl ck to qn2 t plh 1.87 1.80 + 0.035*sl 1.81 + 0.033*sl 1.81 + 0.033*sl t phl 1.55 1.45 + 0.046*sl 1.46 + 0.045*sl 1.46 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl e to qn2 t plh 1.88 1.81 + 0.035*sl 1.82 + 0.033*sl 1.82 + 0.033*sl t phl 1.56 1.47 + 0.046*sl 1.47 + 0.045*sl 1.48 + 0.044*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl ck to qn3 t plh 1.87 1.80 + 0.035*sl 1.80 + 0.033*sl 1.80 + 0.033*sl t phl 1.54 1.45 + 0.046*sl 1.46 + 0.045*sl 1.46 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl e to qn3 t plh 1.88 1.81 + 0.035*sl 1.81 + 0.033*sl 1.82 + 0.033*sl t phl 1.56 1.46 + 0.046*sl 1.47 + 0.045*sl 1.47 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-323 STD80/stdm80 fg2 d flip-flop with ck enable, reset logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.87 0.90 pulse width high (ck) t pwh 0.85 0.85 pulse width low (e) t pwl 0.87 0.87 pulse width high (e) t pwh 0.85 0.87 pulse width low (rn) t pwl 0.87 0.82 input setup time (d to ck) t su 0.44 0.46 input hold time (d to ck) t hd 0.33 0.36 input setup time (d to e) t su 0.44 0.44 input hold time (d to e) t hd 0.36 0.36 recovery time (rn to ck) t rc 0.33 0.33 input hold time (rn to ck) t hd 0.71 0.87 recovery time (rn to e) t rc 0.33 0.33 input hold time (rn to e) t hd 0.76 0.87 dq qn rn e ck cke ck ckeb e d ckeb cke cke ckeb ckeb cke q cke ckeb qn rn rn rn rn truth table cell data d e ck rn q (n+1) qn (n+1) 01 101 11 110 x 0 x 1 q (n) qn (n) xxx001 x x 1 q (n) qn (n) input load (sl) gate count STD80 d e ck rn 6.7 0.5 0.5 0.5 0.7 stdm80 d e ck rn 6.7 0.6 0.4 0.5 1.2
STD80/stdm80 3-324 sec asic fg2 d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fg2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.63 + 0.031*sl 0.64 + 0.026*sl 0.66 + 0.024*sl t phl 0.74 0.66 + 0.042*sl 0.67 + 0.038*sl 0.68 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl e to q t plh 0.71 0.65 + 0.032*sl 0.66 + 0.026*sl 0.69 + 0.024*sl t phl 0.77 0.68 + 0.041*sl 0.69 + 0.038*sl 0.70 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl rn to q t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.78 0.73 + 0.025*sl 0.74 + 0.024*sl 0.74 + 0.024*sl t phl 0.87 0.79 + 0.037*sl 0.79 + 0.037*sl 0.79 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl e to qn t plh 0.81 0.76 + 0.025*sl 0.76 + 0.024*sl 0.76 + 0.024*sl t phl 0.89 0.82 + 0.037*sl 0.82 + 0.037*sl 0.82 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.40 0.35 + 0.025*sl 0.36 + 0.024*sl 0.36 + 0.023*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-325 STD80/stdm80 fg2 d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fg2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.01 0.92 + 0.044*sl 0.94 + 0.038*sl 0.96 + 0.035*sl t phl 1.07 0.96 + 0.052*sl 0.98 + 0.046*sl 1.00 + 0.044*sl t r 0.32 0.18 + 0.071*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl e to q t plh 1.02 0.93 + 0.044*sl 0.95 + 0.037*sl 0.97 + 0.035*sl t phl 1.08 0.98 + 0.052*sl 1.00 + 0.046*sl 1.01 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl rn to q t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl ck to qn t plh 1.14 1.07 + 0.035*sl 1.08 + 0.033*sl 1.08 + 0.033*sl t phl 1.24 1.15 + 0.046*sl 1.16 + 0.045*sl 1.16 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl e to qn t plh 1.15 1.08 + 0.035*sl 1.09 + 0.033*sl 1.09 + 0.033*sl t phl 1.26 1.16 + 0.047*sl 1.17 + 0.045*sl 1.17 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.080*sl 0.11 + 0.082*sl rn to qn t plh 0.55 0.48 + 0.035*sl 0.48 + 0.033*sl 0.48 + 0.033*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-326 sec asic fg2x4 4-bit d flip-flop with ck enable, reset logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (ck) t pwl 0.93 2.00 pulse width high (ck) t pwh 0.87 1.45 pulse width low (e) t pwl 0.90 1.97 pulse width high (e) t pwh 0.87 1.45 pulse width low (rn) t pwl 0.87 0.82 input setup time (d0 to ck) t su 0.33 0.33 input hold time (d0 to ck) t hd 0.79 0.93 input setup time (d0 to e) t su 0.33 0.33 input hold time (d0 to e) t hd 0.82 0.96 input setup time (d1 to ck) t su 0.33 0.33 input hold time (d1 to ck) t hd 0.79 0.93 input setup time (d1 to e) t su 0.33 0.33 input hold time (d1 to e) t hd 0.82 0.93 input setup time (d2 to ck) t su 0.33 0.33 input hold time (d2 to ck) t hd 0.79 0.93 input setup time (d2 to e) t su 0.33 0.33 input hold time (d2 to e) t hd 0.82 0.93 input setup time (d3 to ck) t su 0.33 0.33 input hold time (d3 to ck) t hd 0.79 0.93 input setup time (d3 to e) t su 0.33 0.33 input hold time (d3 to e) t hd 0.82 0.93 recovery time (rn to ck) t rc 0.33 0.33 input hold time (rn to ck) t hd 1.09 1.31 recovery time (rn to e) t rc 0.33 0.33 input hold time (rn to e) t hd 1.09 1.31 d0 d1 d2 d3 q0 q1 q2 q3 qn0 qn1 qn2 qn3 rn e ck truth table cell data dn e ck rn qn (n+1) qnn (n+1) 01 1 0 1 11 1 1 0 x0x1qn (n) qnn (n) xxx0 0 1 x x 1 qn (n) qnn (n) input load (sl) gate count STD80 dn e ck rn 22.7 0.5 0.5 0.5 3.6 stdm80 dn e ck rn 22.7 0.6 0.4 0.5 5.1
sec asic 3-327 STD80/stdm80 fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fg2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.03 0.96 + 0.032*sl 0.97 + 0.026*sl 1.00 + 0.024*sl t phl 1.32 1.24 + 0.041*sl 1.25 + 0.038*sl 1.25 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl e to q0 t plh 1.05 0.99 + 0.032*sl 1.00 + 0.026*sl 1.02 + 0.024*sl t phl 1.35 1.27 + 0.041*sl 1.27 + 0.038*sl 1.28 + 0.037*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q0 t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to q1 t plh 1.03 0.96 + 0.032*sl 0.98 + 0.026*sl 1.00 + 0.024*sl t phl 1.32 1.24 + 0.041*sl 1.25 + 0.038*sl 1.25 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.061*sl 0.11 + 0.066*sl 0.08 + 0.069*sl e to q1 t plh 1.05 0.99 + 0.032*sl 1.00 + 0.026*sl 1.02 + 0.024*sl t phl 1.35 1.27 + 0.041*sl 1.27 + 0.038*sl 1.28 + 0.037*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.061*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q1 t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to q2 t plh 1.03 0.96 + 0.032*sl 0.97 + 0.026*sl 1.00 + 0.024*sl t phl 1.32 1.24 + 0.041*sl 1.25 + 0.038*sl 1.25 + 0.037*sl t r 0.23 0.14 + 0.045*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl e to q2 t plh 1.05 0.99 + 0.032*sl 1.00 + 0.026*sl 1.02 + 0.024*sl t phl 1.35 1.27 + 0.041*sl 1.27 + 0.038*sl 1.28 + 0.037*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q2 t phl 0.37 0.29 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to q3 t plh 1.02 0.96 + 0.032*sl 0.97 + 0.026*sl 1.00 + 0.024*sl t phl 1.32 1.24 + 0.041*sl 1.25 + 0.038*sl 1.25 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.061*sl 0.11 + 0.066*sl 0.08 + 0.069*sl e to q3 t plh 1.05 0.98 + 0.032*sl 0.99 + 0.026*sl 1.02 + 0.024*sl t phl 1.34 1.26 + 0.041*sl 1.27 + 0.038*sl 1.28 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q3 t phl 0.37 0.28 + 0.041*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-328 sec asic fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fg2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.36 1.31 + 0.025*sl 1.32 + 0.024*sl 1.32 + 0.024*sl t phl 1.20 1.12 + 0.037*sl 1.12 + 0.037*sl 1.12 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl e to qn0 t plh 1.39 1.34 + 0.025*sl 1.34 + 0.024*sl 1.34 + 0.024*sl t phl 1.22 1.15 + 0.037*sl 1.15 + 0.037*sl 1.14 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn0 t plh 0.41 0.36 + 0.025*sl 0.36 + 0.023*sl 0.36 + 0.023*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl ck to qn1 t plh 1.36 1.31 + 0.026*sl 1.32 + 0.023*sl 1.31 + 0.024*sl t phl 1.20 1.12 + 0.037*sl 1.12 + 0.037*sl 1.12 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl e to qn1 t plh 1.39 1.34 + 0.025*sl 1.34 + 0.024*sl 1.34 + 0.024*sl t phl 1.22 1.15 + 0.037*sl 1.15 + 0.037*sl 1.14 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn1 t plh 0.41 0.36 + 0.025*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl ck to qn2 t plh 1.36 1.31 + 0.026*sl 1.32 + 0.023*sl 1.31 + 0.024*sl t phl 1.20 1.12 + 0.037*sl 1.12 + 0.037*sl 1.12 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.061*sl 0.09 + 0.067*sl 0.07 + 0.069*sl e to qn2 t plh 1.39 1.34 + 0.025*sl 1.34 + 0.024*sl 1.34 + 0.024*sl t phl 1.22 1.15 + 0.037*sl 1.15 + 0.037*sl 1.14 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn2 t plh 0.41 0.36 + 0.025*sl 0.36 + 0.023*sl 0.36 + 0.023*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl ck to qn3 t plh 1.36 1.31 + 0.025*sl 1.31 + 0.024*sl 1.31 + 0.024*sl t phl 1.19 1.12 + 0.037*sl 1.12 + 0.037*sl 1.12 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl e to qn3 t plh 1.38 1.33 + 0.026*sl 1.34 + 0.023*sl 1.33 + 0.024*sl t phl 1.22 1.14 + 0.037*sl 1.14 + 0.037*sl 1.14 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn3 t plh 0.41 0.35 + 0.026*sl 0.36 + 0.023*sl 0.36 + 0.023*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-329 STD80/stdm80 fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fg2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.44 1.35 + 0.044*sl 1.37 + 0.038*sl 1.40 + 0.035*sl t phl 1.92 1.82 + 0.052*sl 1.83 + 0.046*sl 1.85 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.16 + 0.078*sl 0.15 + 0.079*sl 0.14 + 0.081*sl e to q0 t plh 1.45 1.37 + 0.044*sl 1.38 + 0.038*sl 1.41 + 0.035*sl t phl 1.93 1.83 + 0.052*sl 1.84 + 0.046*sl 1.86 + 0.045*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.18 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q0 t phl 0.48 0.37 + 0.052*sl 0.39 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.14 + 0.081*sl ck to q1 t plh 1.44 1.35 + 0.044*sl 1.37 + 0.038*sl 1.40 + 0.035*sl t phl 1.92 1.82 + 0.052*sl 1.83 + 0.046*sl 1.85 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.18 + 0.070*sl t f 0.31 0.16 + 0.078*sl 0.15 + 0.079*sl 0.14 + 0.081*sl e to q1 t plh 1.45 1.37 + 0.044*sl 1.38 + 0.038*sl 1.41 + 0.035*sl t phl 1.93 1.83 + 0.052*sl 1.84 + 0.046*sl 1.86 + 0.045*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.18 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q1 t phl 0.48 0.37 + 0.052*sl 0.39 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.14 + 0.081*sl ck to q2 t plh 1.44 1.35 + 0.044*sl 1.37 + 0.038*sl 1.40 + 0.035*sl t phl 1.92 1.82 + 0.052*sl 1.83 + 0.046*sl 1.85 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.31 0.16 + 0.078*sl 0.15 + 0.079*sl 0.14 + 0.081*sl e to q2 t plh 1.45 1.37 + 0.044*sl 1.38 + 0.038*sl 1.41 + 0.035*sl t phl 1.93 1.83 + 0.052*sl 1.84 + 0.046*sl 1.86 + 0.045*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.18 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.14 + 0.081*sl rn to q2 t phl 0.48 0.37 + 0.052*sl 0.39 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl ck to q3 t plh 1.44 1.35 + 0.044*sl 1.37 + 0.038*sl 1.39 + 0.035*sl t phl 1.92 1.81 + 0.052*sl 1.83 + 0.046*sl 1.84 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.068*sl 0.18 + 0.070*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.079*sl 0.14 + 0.081*sl e to q3 t plh 1.45 1.36 + 0.044*sl 1.38 + 0.038*sl 1.40 + 0.034*sl t phl 1.93 1.82 + 0.052*sl 1.84 + 0.046*sl 1.85 + 0.044*sl t r 0.32 0.18 + 0.071*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.14 + 0.081*sl rn to q3 t phl 0.47 0.37 + 0.052*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-330 sec asic fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fg2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.99 1.92 + 0.035*sl 1.93 + 0.033*sl 1.93 + 0.033*sl t phl 1.68 1.59 + 0.046*sl 1.59 + 0.045*sl 1.60 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.13 + 0.080*sl 0.11 + 0.082*sl e to qn0 t plh 2.01 1.94 + 0.035*sl 1.94 + 0.033*sl 1.94 + 0.033*sl t phl 1.69 1.60 + 0.047*sl 1.60 + 0.045*sl 1.61 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.13 + 0.080*sl 0.11 + 0.082*sl rn to qn0 t plh 0.56 0.48 + 0.035*sl 0.49 + 0.033*sl 0.49 + 0.033*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl ck to qn1 t plh 1.99 1.92 + 0.035*sl 1.93 + 0.033*sl 1.93 + 0.033*sl t phl 1.68 1.58 + 0.047*sl 1.59 + 0.045*sl 1.60 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.12 + 0.080*sl 0.11 + 0.082*sl e to qn1 t plh 2.01 1.94 + 0.035*sl 1.94 + 0.033*sl 1.94 + 0.033*sl t phl 1.69 1.60 + 0.047*sl 1.60 + 0.044*sl 1.61 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.13 + 0.080*sl 0.11 + 0.082*sl rn to qn1 t plh 0.56 0.48 + 0.035*sl 0.49 + 0.033*sl 0.49 + 0.033*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl ck to qn2 t plh 1.99 1.92 + 0.035*sl 1.93 + 0.033*sl 1.93 + 0.033*sl t phl 1.68 1.59 + 0.046*sl 1.59 + 0.045*sl 1.60 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.13 + 0.080*sl 0.11 + 0.082*sl e to qn2 t plh 2.01 1.94 + 0.035*sl 1.94 + 0.033*sl 1.94 + 0.033*sl t phl 1.69 1.60 + 0.047*sl 1.60 + 0.045*sl 1.61 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.13 + 0.080*sl 0.11 + 0.082*sl rn to qn2 t plh 0.56 0.48 + 0.035*sl 0.49 + 0.033*sl 0.49 + 0.033*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl ck to qn3 t plh 1.99 1.92 + 0.035*sl 1.92 + 0.033*sl 1.92 + 0.033*sl t phl 1.67 1.58 + 0.046*sl 1.58 + 0.045*sl 1.59 + 0.044*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl e to qn3 t plh 2.00 1.93 + 0.035*sl 1.93 + 0.033*sl 1.94 + 0.033*sl t phl 1.68 1.59 + 0.047*sl 1.60 + 0.045*sl 1.60 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn3 t plh 0.55 0.48 + 0.034*sl 0.48 + 0.034*sl 0.48 + 0.033*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-331 STD80/stdm80 fj1/fj1d2 jk flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 fj1 fj1d2 fj1 fj1d2 jckk jckk 0.5 0.5 0.3 0.5 0.5 0.3 7.0 7.7 stdm80 fj1 fj1d2 fj1 fj1d2 jckk jckk 0.4 0.6 0.6 0.4 0.6 0.6 7.0 7.7 parameter symbol STD80 stdm80 fj1 fj1d2 fj1 fj1d2 pulse width low (ck) t pwl 0.87 0.87 0.87 0.87 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 input setup time (j to ck) t su 0.79 0.82 0.82 0.82 input hold time (j to ck) t hd 0.33 0.33 0.33 0.33 input setup time (k to ck) t su 0.79 0.82 0.82 0.82 input hold time (k to ck) t hd 0.33 0.33 0.33 0.33 j ck k q qn j cl clb cl clb clb cl qn clb cl q k cl ck clb truth table j ck k q (n+1) qn (n+1) 0 101 1 010 0 0 q (n) qn (n) 1 1 qn (n) q (n) x x q (n) qn (n)
STD80/stdm80 3-332 sec asic fj1/fj1d2 jk flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fj1 STD80 fj1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.76 0.70 + 0.028*sl 0.71 + 0.024*sl 0.72 + 0.024*sl t phl 0.81 0.73 + 0.040*sl 0.74 + 0.037*sl 0.74 + 0.037*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.57 0.52 + 0.027*sl 0.52 + 0.024*sl 0.53 + 0.024*sl t phl 0.65 0.57 + 0.041*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.79 + 0.016*sl 0.79 + 0.013*sl 0.81 + 0.012*sl t phl 0.86 0.82 + 0.021*sl 0.83 + 0.019*sl 0.83 + 0.018*sl t r 0.17 0.13 + 0.023*sl 0.13 + 0.023*sl 0.10 + 0.026*sl t f 0.19 0.12 + 0.033*sl 0.13 + 0.031*sl 0.10 + 0.034*sl ck to qn t plh 0.58 0.54 + 0.018*sl 0.55 + 0.014*sl 0.57 + 0.012*sl t phl 0.64 0.60 + 0.023*sl 0.61 + 0.020*sl 0.62 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-333 STD80/stdm80 fj1/fj1d2 jk flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fj1 stdm80 fj1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.08 1.01 + 0.038*sl 1.02 + 0.034*sl 1.02 + 0.033*sl t phl 1.15 1.05 + 0.052*sl 1.07 + 0.046*sl 1.08 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.068*sl 0.13 + 0.071*sl t f 0.32 0.16 + 0.080*sl 0.16 + 0.079*sl 0.15 + 0.081*sl ck to qn t plh 0.82 0.74 + 0.038*sl 0.75 + 0.034*sl 0.76 + 0.034*sl t phl 0.92 0.82 + 0.051*sl 0.83 + 0.047*sl 0.85 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.070*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.17 1.12 + 0.021*sl 1.13 + 0.019*sl 1.14 + 0.017*sl t phl 1.22 1.16 + 0.029*sl 1.17 + 0.025*sl 1.19 + 0.023*sl t r 0.22 0.15 + 0.035*sl 0.15 + 0.033*sl 0.15 + 0.033*sl t f 0.23 0.15 + 0.042*sl 0.16 + 0.040*sl 0.17 + 0.037*sl ck to qn t plh 0.82 0.77 + 0.024*sl 0.79 + 0.020*sl 0.80 + 0.018*sl t phl 0.91 0.85 + 0.030*sl 0.87 + 0.026*sl 0.88 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-334 sec asic fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fj1s fj1sd2 fj1s fj1sd 2 j ck k ti te j ck k ti te 0.3 0.5 0.3 0.5 0.9 0.3 0.5 0.3 0.5 0.9 9.3 10.0 stdm80 fj1s fj1sd2 fj1s fj1sd 2 j ck k ti te j ck k ti te 0.6 0.6 0.5 0.4 1.1 0.6 0.6 0.5 0.4 1.1 9.3 10.0 q qn j ti te ck k j clb cl clb cl clb cl q clb qn k ti te cl cl ck clb truth table j ck k ti te q (n+1) qn (n+1) 01x001 10x010 0 0 x 0 q (n) qn (n) 1 1 x 0 qn (n) q (n) x x x x q (n) qn (n) x x0101 x x1110
sec asic 3-335 STD80/stdm80 fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fj1s STD80 fj1sd2 parameter symbol STD80 stdm80 fj1s fj1sd2 fj1s fj1sd2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 input setup time (j to ck) t su 0.82 0.82 1.20 1.20 input hold time (j to ck) t hd 0.33 0.33 0.33 0.33 input setup time (k to ck) t su 0.82 0.82 1.20 1.20 input hold time (k to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.66 0.66 0.93 0.93 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.63 0.63 0.82 0.82 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.59 + 0.031*sl 0.60 + 0.026*sl 0.62 + 0.024*sl t phl 0.74 0.65 + 0.044*sl 0.66 + 0.039*sl 0.68 + 0.037*sl t r 0.23 0.14 + 0.045*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.26 0.14 + 0.063*sl 0.13 + 0.065*sl 0.09 + 0.069*sl ck to qn t plh 0.77 0.72 + 0.025*sl 0.72 + 0.024*sl 0.72 + 0.024*sl t phl 0.82 0.75 + 0.037*sl 0.75 + 0.037*sl 0.75 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.60 + 0.021*sl 0.62 + 0.015*sl 0.65 + 0.012*sl t phl 0.72 0.67 + 0.025*sl 0.68 + 0.021*sl 0.71 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.20 0.14 + 0.033*sl 0.14 + 0.031*sl 0.11 + 0.034*sl ck to qn t plh 0.84 0.81 + 0.014*sl 0.81 + 0.012*sl 0.82 + 0.012*sl t phl 0.88 0.84 + 0.019*sl 0.84 + 0.018*sl 0.84 + 0.018*sl t r 0.16 0.11 + 0.024*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-336 sec asic fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fj1s stdm80 fj1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.84 + 0.043*sl 0.86 + 0.036*sl 0.88 + 0.034*sl t phl 1.04 0.93 + 0.057*sl 0.95 + 0.049*sl 0.98 + 0.045*sl t r 0.31 0.18 + 0.066*sl 0.18 + 0.068*sl 0.16 + 0.070*sl t f 0.34 0.18 + 0.081*sl 0.19 + 0.079*sl 0.18 + 0.080*sl ck to qn t plh 1.11 1.04 + 0.035*sl 1.04 + 0.033*sl 1.04 + 0.033*sl t phl 1.16 1.07 + 0.047*sl 1.07 + 0.045*sl 1.08 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.071*sl t f 0.28 0.13 + 0.078*sl 0.12 + 0.080*sl 0.11 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.92 0.86 + 0.027*sl 0.88 + 0.022*sl 0.90 + 0.019*sl t phl 1.02 0.95 + 0.034*sl 0.97 + 0.028*sl 0.99 + 0.025*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.033*sl 0.17 + 0.034*sl t f 0.25 0.16 + 0.043*sl 0.18 + 0.039*sl 0.18 + 0.038*sl ck to qn t plh 1.20 1.16 + 0.019*sl 1.16 + 0.018*sl 1.17 + 0.017*sl t phl 1.23 1.18 + 0.026*sl 1.19 + 0.023*sl 1.20 + 0.022*sl t r 0.20 0.14 + 0.032*sl 0.14 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.13 + 0.038*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-337 STD80/stdm80 fj2/fj2d2 jk flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fj2 fj2d2 fj2 fj2d2 jckkrnjckkrn 0.5 0.5 0.3 0.7 0.5 0.5 0.3 0.7 8.3 9.0 stdm80 fj2 fj2d2 fj2 fj2d2 jckkrnjckkrn 0.6 0.6 0.5 1.1 0.6 0.6 0.5 1.1 8.3 9.0 j ck k q qn rn j k cl ck clb q clb cl cl clb cl clb clb cl rn qn truth table jckkrn q (n+1) qn (n+1) 01101 10110 0 0 1 q (n) qn (n) 1 1 1 qn (n) q (n) x x 1 q (n) qn (n) xxx001
STD80/stdm80 3-338 sec asic fj2/fj2d2 jk flip-flop with reset, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fj2 STD80 fj2d2 parameter symbol STD80 stdm80 fj2 fj2d2 fj2 fj2d2 pulse width low (ck) t pwl 0.87 0.87 0.96 0.96 pulse width high (ck) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.87 0.90 input setup time (j to ck) t su 0.87 0.87 0.87 0.87 input hold time (j to ck) t hd 0.33 0.33 0.33 0.33 input setup time (k to ck) t su 0.87 0.87 0.87 0.87 input hold time (k to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.38 0.38 0.44 0.44 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.90 0.83 + 0.034*sl 0.85 + 0.027*sl 0.88 + 0.024*sl t phl 0.86 0.78 + 0.041*sl 0.78 + 0.038*sl 0.79 + 0.037*sl t r 0.25 0.16 + 0.047*sl 0.16 + 0.048*sl 0.12 + 0.051*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.065*sl 0.09 + 0.069*sl rn to q t phl 0.43 0.35 + 0.042*sl 0.36 + 0.038*sl 0.36 + 0.037*sl t f 0.25 0.13 + 0.062*sl 0.12 + 0.065*sl 0.08 + 0.069*sl ck to qn t plh 0.58 0.52 + 0.028*sl 0.53 + 0.024*sl 0.53 + 0.024*sl t phl 0.70 0.62 + 0.041*sl 0.63 + 0.038*sl 0.63 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl rn to qn t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.57 + 0.023*sl t r 0.21 0.12 + 0.043*sl 0.11 + 0.048*sl 0.07 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.96 0.92 + 0.022*sl 0.93 + 0.016*sl 0.97 + 0.012*sl t phl 0.91 0.86 + 0.023*sl 0.87 + 0.019*sl 0.88 + 0.018*sl t r 0.22 0.17 + 0.025*sl 0.18 + 0.024*sl 0.16 + 0.025*sl t f 0.20 0.14 + 0.031*sl 0.14 + 0.031*sl 0.11 + 0.034*sl rn to q t phl 0.42 0.37 + 0.025*sl 0.38 + 0.020*sl 0.40 + 0.018*sl t f 0.20 0.13 + 0.032*sl 0.14 + 0.030*sl 0.10 + 0.034*sl ck to qn t plh 0.58 0.55 + 0.018*sl 0.56 + 0.014*sl 0.57 + 0.012*sl t phl 0.69 0.65 + 0.023*sl 0.65 + 0.020*sl 0.67 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl rn to qn t plh 0.61 0.58 + 0.018*sl 0.59 + 0.013*sl 0.60 + 0.012*sl t r 0.17 0.13 + 0.019*sl 0.12 + 0.023*sl 0.09 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-339 STD80/stdm80 fj2/fj2d2 jk flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fj2 stdm80 fj2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.29 1.20 + 0.046*sl 1.22 + 0.039*sl 1.25 + 0.035*sl t phl 1.22 1.11 + 0.054*sl 1.13 + 0.047*sl 1.15 + 0.045*sl t r 0.34 0.20 + 0.071*sl 0.21 + 0.068*sl 0.20 + 0.069*sl t f 0.33 0.17 + 0.081*sl 0.18 + 0.078*sl 0.17 + 0.080*sl rn to q t phl 0.57 0.46 + 0.056*sl 0.48 + 0.048*sl 0.50 + 0.045*sl t f 0.33 0.17 + 0.080*sl 0.17 + 0.078*sl 0.16 + 0.080*sl ck to qn t plh 0.82 0.75 + 0.038*sl 0.76 + 0.034*sl 0.76 + 0.034*sl t phl 0.99 0.89 + 0.051*sl 0.90 + 0.046*sl 0.91 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.15 + 0.079*sl 0.14 + 0.080*sl 0.13 + 0.082*sl rn to qn t plh 0.87 0.80 + 0.038*sl 0.81 + 0.034*sl 0.82 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.15 + 0.068*sl 0.13 + 0.071*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.38 1.32 + 0.029*sl 1.34 + 0.023*sl 1.36 + 0.020*sl t phl 1.28 1.22 + 0.031*sl 1.23 + 0.026*sl 1.25 + 0.023*sl t r 0.28 0.20 + 0.039*sl 0.21 + 0.035*sl 0.22 + 0.034*sl t f 0.25 0.16 + 0.044*sl 0.18 + 0.039*sl 0.18 + 0.038*sl rn to q t phl 0.55 0.48 + 0.034*sl 0.50 + 0.028*sl 0.53 + 0.024*sl t f 0.25 0.16 + 0.042*sl 0.18 + 0.038*sl 0.18 + 0.037*sl ck to qn t plh 0.83 0.78 + 0.024*sl 0.79 + 0.020*sl 0.81 + 0.018*sl t phl 0.98 0.92 + 0.031*sl 0.93 + 0.026*sl 0.95 + 0.023*sl t r 0.21 0.14 + 0.032*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.14 + 0.038*sl rn to qn t plh 0.88 0.83 + 0.024*sl 0.84 + 0.020*sl 0.86 + 0.018*sl t r 0.22 0.16 + 0.030*sl 0.15 + 0.032*sl 0.14 + 0.033*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-340 sec asic fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fj2s fj2sd2 fj2s fj2s d2 j ck k ti te rn j ck k ti te rn 0.5 0.5 0.5 0.5 0.9 0.7 0.5 0.5 0.5 0.5 0.9 0.7 10.3 11.0 stdm80 fj2s fj2sd2 fj2s fj2s d2 j ck k ti te rn j ck k ti te rn 0.6 0.6 0.5 0.4 1.1 1.1 0.6 0.6 0.5 0.4 1.1 1.2 10.3 11.0 q qn j ti te ck k rn j clb cl clb cl clb cl q clb qn k ti te cl cl ck clb rn rn rn rn truth table j ck k ti te rn q (n+1) qn (n+1) 01x0101 10x0110 0 0 x 0 1 q (n) qn (n) 1 1 x 0 1 qn (n) q (n) x x x 0 1 q (n) qn (n) xxxxx0 0 1 xx01101 xx11110
sec asic 3-341 STD80/stdm80 fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fj2s fj2sd2 fj2s fj2sd2 pulse width low (ck) t pwl 0.87 0.87 0.98 0.98 pulse width high (ck) t pwh 0.79 0.85 0.82 0.85 pulse width high (rn) t pwh 0.87 0.87 0.90 0.90 input setup time (j to ck) t su 0.85 0.85 1.23 1.23 input hold time (j to ck) t hd 0.33 0.33 0.33 0.33 input setup time (k to ck) t su 0.85 0.85 1.23 1.23 input hold time (k to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.66 0.66 0.93 0.93 input hold time (ti to ck) t hd 0.33 0.33 0.33 0.33 input setup time (te to ck) t su 0.66 0.66 0.85 0.85 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.66 0.66 0.76 0.76
STD80/stdm80 3-342 sec asic fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fj2s STD80 fj2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.73 0.66 + 0.037*sl 0.68 + 0.028*sl 0.72 + 0.024*sl t phl 0.77 0.68 + 0.044*sl 0.69 + 0.039*sl 0.71 + 0.037*sl t r 0.27 0.18 + 0.048*sl 0.18 + 0.048*sl 0.14 + 0.051*sl t f 0.27 0.15 + 0.062*sl 0.14 + 0.065*sl 0.10 + 0.069*sl rn to q t phl 0.46 0.37 + 0.044*sl 0.38 + 0.038*sl 0.39 + 0.037*sl t f 0.27 0.15 + 0.060*sl 0.14 + 0.064*sl 0.09 + 0.069*sl ck to qn t plh 0.80 0.75 + 0.025*sl 0.75 + 0.024*sl 0.75 + 0.024*sl t phl 0.92 0.85 + 0.037*sl 0.85 + 0.037*sl 0.85 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.23 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.49 0.44 + 0.025*sl 0.44 + 0.024*sl 0.44 + 0.024*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.06 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.74 0.69 + 0.024*sl 0.70 + 0.017*sl 0.75 + 0.012*sl t phl 0.75 0.70 + 0.026*sl 0.71 + 0.021*sl 0.74 + 0.018*sl t r 0.24 0.19 + 0.023*sl 0.19 + 0.024*sl 0.18 + 0.025*sl t f 0.21 0.14 + 0.033*sl 0.15 + 0.031*sl 0.12 + 0.033*sl rn to q t phl 0.44 0.39 + 0.025*sl 0.40 + 0.020*sl 0.42 + 0.018*sl t f 0.20 0.14 + 0.030*sl 0.15 + 0.029*sl 0.11 + 0.034*sl ck to qn t plh 0.87 0.84 + 0.014*sl 0.84 + 0.013*sl 0.85 + 0.012*sl t phl 1.01 0.97 + 0.018*sl 0.97 + 0.017*sl 0.96 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.022*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.55 0.53 + 0.013*sl 0.53 + 0.013*sl 0.54 + 0.012*sl t r 0.16 0.11 + 0.022*sl 0.11 + 0.023*sl 0.08 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-343 STD80/stdm80 fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fj2s stdm80 fj2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.04 0.94 + 0.050*sl 0.97 + 0.041*sl 1.00 + 0.037*sl t phl 1.09 0.97 + 0.058*sl 1.00 + 0.049*sl 1.02 + 0.045*sl t r 0.36 0.22 + 0.073*sl 0.23 + 0.069*sl 0.24 + 0.068*sl t f 0.35 0.19 + 0.080*sl 0.19 + 0.078*sl 0.18 + 0.080*sl rn to q t phl 0.60 0.49 + 0.058*sl 0.52 + 0.048*sl 0.54 + 0.045*sl t f 0.34 0.18 + 0.080*sl 0.19 + 0.077*sl 0.18 + 0.079*sl ck to qn t plh 1.15 1.08 + 0.035*sl 1.09 + 0.033*sl 1.09 + 0.033*sl t phl 1.30 1.20 + 0.047*sl 1.21 + 0.045*sl 1.21 + 0.044*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.29 0.14 + 0.077*sl 0.13 + 0.080*sl 0.12 + 0.082*sl rn to qn t plh 0.67 0.60 + 0.035*sl 0.60 + 0.033*sl 0.61 + 0.033*sl t r 0.26 0.13 + 0.066*sl 0.12 + 0.070*sl 0.11 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.05 0.98 + 0.032*sl 1.00 + 0.025*sl 1.03 + 0.021*sl t phl 1.06 0.99 + 0.034*sl 1.01 + 0.029*sl 1.03 + 0.025*sl t r 0.29 0.21 + 0.039*sl 0.22 + 0.036*sl 0.23 + 0.035*sl t f 0.26 0.17 + 0.043*sl 0.18 + 0.040*sl 0.20 + 0.038*sl rn to q t phl 0.58 0.51 + 0.035*sl 0.53 + 0.028*sl 0.56 + 0.024*sl t f 0.26 0.18 + 0.041*sl 0.19 + 0.038*sl 0.20 + 0.036*sl ck to qn t plh 1.25 1.21 + 0.019*sl 1.21 + 0.018*sl 1.22 + 0.017*sl t phl 1.41 1.36 + 0.024*sl 1.36 + 0.022*sl 1.37 + 0.022*sl t r 0.20 0.14 + 0.031*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.037*sl 0.15 + 0.038*sl rn to qn t plh 0.76 0.72 + 0.019*sl 0.72 + 0.018*sl 0.73 + 0.017*sl t r 0.20 0.14 + 0.032*sl 0.14 + 0.032*sl 0.12 + 0.034*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-344 sec asic fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive logic symbol5 cell data schematic diagram input load (sl) gate count STD80 fj4 fj4d2 fj4 fj4d2 j ck k rn sn j ck k rn sn 0.3 0.5 0.3 0.7 0.7 0.3 0.5 0.3 0.7 0.7 9.3 10.0 stdm80 fj4 fj4d2 fj4 fj4d2 j ck k rn sn j ck k rn sn 0.6 0.6 0.5 1.6 1.6 0.6 0.6 0.5 1.6 1.6 9.3 10.0 j ck k q qn rn sn j cl clb k q qn cl clb clb cl clb cl rn sn cl ck clb truth table j ck k rn sn q (n+1) qn (n+1) 0 11101 1 01110 0 0 1 1 q (n) qn (n) 1 1 1 1 qn (n) q (n) x x 1 1 q (n) qn (n) xxx0101 xxx1010 xxx0000
sec asic 3-345 STD80/stdm80 fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fj4 fj4d2 fj4 fj4d2 pulse width low (ck) t pwl 0.87 0.87 0.98 0.98 pulse width high (ck) t pwh 0.79 0.85 0.82 0.85 pulse width low (rn) t pwl 0.87 0.87 0.87 0.90 pulse width low (sn) t pwl 0.87 0.87 0.85 0.93 input setup time (j to ck) t su 0.87 0.87 0.90 0.90 input hold time (j to ck) t hd 0.33 0.33 0.33 0.33 input setup time (k to ck) t su 0.87 0.87 0.90 0.90 input hold time (k to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.38 0.38 0.44 0.44 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.71 0.71 0.82 0.82
STD80/stdm80 3-346 sec asic fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fj4 STD80 fj4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.86 + 0.035*sl 0.88 + 0.027*sl 0.91 + 0.024*sl t phl 0.94 0.86 + 0.041*sl 0.87 + 0.037*sl 0.87 + 0.037*sl t r 0.26 0.16 + 0.048*sl 0.16 + 0.048*sl 0.13 + 0.051*sl t f 0.26 0.14 + 0.063*sl 0.13 + 0.065*sl 0.09 + 0.069*sl rn to q t plh 0.42 0.35 + 0.035*sl 0.37 + 0.027*sl 0.40 + 0.024*sl t phl 0.44 0.35 + 0.043*sl 0.36 + 0.038*sl 0.37 + 0.037*sl t r 0.26 0.16 + 0.048*sl 0.16 + 0.047*sl 0.12 + 0.051*sl t f 0.26 0.13 + 0.063*sl 0.13 + 0.065*sl 0.08 + 0.069*sl sn to q t plh 0.57 0.51 + 0.034*sl 0.52 + 0.027*sl 0.55 + 0.024*sl t r 0.25 0.16 + 0.047*sl 0.16 + 0.047*sl 0.12 + 0.052*sl ck to qn t plh 0.64 0.58 + 0.032*sl 0.59 + 0.026*sl 0.61 + 0.024*sl t phl 0.73 0.64 + 0.041*sl 0.65 + 0.038*sl 0.66 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to qn t plh 0.66 0.59 + 0.032*sl 0.61 + 0.026*sl 0.63 + 0.023*sl t r 0.23 0.14 + 0.048*sl 0.14 + 0.048*sl 0.10 + 0.052*sl sn to qn t plh 0.33 0.27 + 0.032*sl 0.28 + 0.025*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.12 + 0.060*sl 0.10 + 0.067*sl 0.08 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.00 0.95 + 0.022*sl 0.96 + 0.016*sl 1.01 + 0.012*sl t phl 1.02 0.97 + 0.023*sl 0.98 + 0.019*sl 0.98 + 0.018*sl t r 0.23 0.18 + 0.025*sl 0.18 + 0.024*sl 0.17 + 0.025*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.031*sl 0.12 + 0.033*sl rn to q t plh 0.43 0.38 + 0.023*sl 0.39 + 0.017*sl 0.44 + 0.012*sl t phl 0.43 0.38 + 0.025*sl 0.39 + 0.020*sl 0.41 + 0.018*sl t r 0.22 0.17 + 0.026*sl 0.18 + 0.024*sl 0.16 + 0.025*sl t f 0.20 0.14 + 0.033*sl 0.14 + 0.030*sl 0.11 + 0.034*sl sn to q t plh 0.64 0.59 + 0.022*sl 0.60 + 0.016*sl 0.65 + 0.012*sl t r 0.22 0.18 + 0.024*sl 0.18 + 0.024*sl 0.16 + 0.025*sl ck to qn t plh 0.65 0.61 + 0.020*sl 0.62 + 0.015*sl 0.66 + 0.012*sl t phl 0.72 0.67 + 0.023*sl 0.68 + 0.020*sl 0.70 + 0.018*sl t r 0.19 0.15 + 0.024*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.030*sl 0.09 + 0.034*sl rn to qn t plh 0.67 0.63 + 0.021*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t r 0.20 0.15 + 0.025*sl 0.16 + 0.023*sl 0.13 + 0.026*sl sn to qn t plh 0.35 0.30 + 0.022*sl 0.32 + 0.015*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.020*sl 0.33 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-347 STD80/stdm80 fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fj4 stdm80 fj4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.35 1.25 + 0.047*sl 1.27 + 0.040*sl 1.30 + 0.035*sl t phl 1.34 1.24 + 0.053*sl 1.25 + 0.047*sl 1.27 + 0.045*sl t r 0.35 0.20 + 0.071*sl 0.21 + 0.068*sl 0.21 + 0.069*sl t f 0.34 0.18 + 0.081*sl 0.19 + 0.078*sl 0.18 + 0.080*sl rn to q t plh 0.56 0.47 + 0.048*sl 0.49 + 0.039*sl 0.52 + 0.035*sl t phl 0.58 0.47 + 0.056*sl 0.49 + 0.048*sl 0.51 + 0.045*sl t r 0.34 0.20 + 0.070*sl 0.21 + 0.067*sl 0.20 + 0.069*sl t f 0.33 0.17 + 0.081*sl 0.18 + 0.078*sl 0.17 + 0.080*sl sn to q t plh 0.80 0.70 + 0.047*sl 0.73 + 0.039*sl 0.75 + 0.035*sl t r 0.34 0.21 + 0.069*sl 0.21 + 0.067*sl 0.20 + 0.069*sl ck to qn t plh 0.92 0.83 + 0.043*sl 0.85 + 0.037*sl 0.86 + 0.034*sl t phl 1.03 0.92 + 0.051*sl 0.94 + 0.046*sl 0.95 + 0.045*sl t r 0.31 0.18 + 0.069*sl 0.18 + 0.069*sl 0.16 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.14 + 0.081*sl rn to qn t plh 0.94 0.85 + 0.044*sl 0.88 + 0.037*sl 0.90 + 0.034*sl t r 0.32 0.18 + 0.067*sl 0.18 + 0.067*sl 0.17 + 0.070*sl sn to qn t plh 0.44 0.35 + 0.043*sl 0.37 + 0.036*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.050*sl 0.38 + 0.046*sl 0.39 + 0.045*sl t r 0.30 0.17 + 0.069*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.13 + 0.081*sl 0.13 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.43 1.37 + 0.029*sl 1.39 + 0.024*sl 1.41 + 0.020*sl t phl 1.44 1.38 + 0.030*sl 1.39 + 0.026*sl 1.41 + 0.023*sl t r 0.28 0.20 + 0.040*sl 0.22 + 0.035*sl 0.22 + 0.034*sl t f 0.26 0.18 + 0.043*sl 0.19 + 0.039*sl 0.20 + 0.038*sl rn to q t plh 0.57 0.51 + 0.031*sl 0.53 + 0.025*sl 0.55 + 0.021*sl t phl 0.56 0.49 + 0.034*sl 0.51 + 0.028*sl 0.54 + 0.024*sl t r 0.28 0.20 + 0.039*sl 0.21 + 0.035*sl 0.22 + 0.034*sl t f 0.25 0.17 + 0.041*sl 0.18 + 0.039*sl 0.18 + 0.037*sl sn to q t plh 0.88 0.82 + 0.029*sl 0.84 + 0.023*sl 0.86 + 0.020*sl t r 0.28 0.20 + 0.038*sl 0.21 + 0.036*sl 0.22 + 0.034*sl ck to qn t plh 0.93 0.87 + 0.028*sl 0.89 + 0.022*sl 0.91 + 0.019*sl t phl 1.02 0.96 + 0.031*sl 0.97 + 0.026*sl 0.99 + 0.023*sl t r 0.25 0.18 + 0.035*sl 0.18 + 0.035*sl 0.19 + 0.034*sl t f 0.23 0.15 + 0.040*sl 0.16 + 0.037*sl 0.15 + 0.038*sl rn to qn t plh 0.96 0.90 + 0.028*sl 0.92 + 0.023*sl 0.94 + 0.019*sl t r 0.25 0.18 + 0.035*sl 0.19 + 0.034*sl 0.19 + 0.033*sl sn to qn t plh 0.45 0.39 + 0.027*sl 0.41 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.18 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.039*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-348 sec asic fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fj4s fj4sd2 fj4s fj4s d2 j ck k ti te rn sn j ck k ti te rn sn 0.3 0.5 0.3 0.4 0.9 0.7 0.9 0.3 0.5 0.3 0.4 0.9 0.7 0.9 11.7 12.3 stdm80 fj4s fj4sd2 fj4s fj4s d2 j ck k ti te rn sn j ck k ti te rn sn 0.6 0.6 0.5 0.4 1.1 1.7 1.6 0.6 0.6 0.5 0.4 1.1 1.7 1.6 11.7 12.3 q qn j ti te ck k rn sn j cl clb k qn q cl clb clb cl clb cl cl ck clb te ti sn rn rn sn sn sn rn rn truth table j ck k ti te rn sn q (n+1) qn (n+1) 01x01101 10x01110 0 0 x 0 1 1 q (n) qn (n) 1 1 x 0 1 1 qn (n) q (n) x x x 0 1 1 q (n) qn (n) xxxxx01 0 1 xxxxx10 1 0 xxxxx00 0 0 x x0111 0 1 x x1111 1 0
sec asic 3-349 STD80/stdm80 fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 fj4s fj4sd2 fj4s fj4sd2 pulse width low (ck) t pwl 0.87 0.87 1.04 1.04 pulse width high (ck) t pwh 0.82 0.85 0.82 0.87 pulse width high (rn) t pwh 0.87 0.87 0.90 0.93 pulse width high (sn) t pwh 0.87 0.87 0.98 0.98 input setup time (j to ck) t su 0.90 0.90 1.28 1.28 input hold time (j to ck) t hd 0.33 0.33 0.33 0.33 input setup time (k to ck) t su 0.90 0.90 1.28 1.28 input hold time (k to ck) t hd 0.33 0.33 0.33 0.33 input setup time (ti to ck) t su 0.33 0.33 0.98 0.98 input hold time (ti to ck) t hd 0.71 0.71 0.33 0.33 input setup time (te to ck) t su 0.68 0.68 0.93 0.93 input hold time (te to ck) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.71 0.71 0.82 0.82 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.38 0.38 0.44 0.44
STD80/stdm80 3-350 sec asic fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fj4s STD80 fj4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.74 0.67 + 0.037*sl 0.69 + 0.028*sl 0.73 + 0.024*sl t phl 0.82 0.73 + 0.044*sl 0.74 + 0.039*sl 0.76 + 0.037*sl t r 0.27 0.18 + 0.048*sl 0.18 + 0.048*sl 0.15 + 0.051*sl t f 0.27 0.15 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl rn to q t plh 0.43 0.36 + 0.036*sl 0.38 + 0.027*sl 0.42 + 0.024*sl t phl 0.46 0.37 + 0.043*sl 0.38 + 0.038*sl 0.40 + 0.037*sl t r 0.27 0.17 + 0.048*sl 0.17 + 0.047*sl 0.13 + 0.051*sl t f 0.27 0.14 + 0.064*sl 0.14 + 0.064*sl 0.09 + 0.069*sl sn to q t plh 0.76 0.69 + 0.037*sl 0.71 + 0.028*sl 0.75 + 0.024*sl t r 0.27 0.18 + 0.044*sl 0.17 + 0.047*sl 0.13 + 0.051*sl ck to qn t plh 0.94 0.88 + 0.030*sl 0.89 + 0.025*sl 0.90 + 0.024*sl t phl 0.96 0.88 + 0.038*sl 0.88 + 0.037*sl 0.88 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to qn t plh 0.58 0.53 + 0.029*sl 0.53 + 0.025*sl 0.55 + 0.024*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl sn to qn t plh 0.30 0.24 + 0.031*sl 0.25 + 0.025*sl 0.27 + 0.024*sl t phl 0.37 0.29 + 0.040*sl 0.29 + 0.037*sl 0.30 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.75 0.70 + 0.024*sl 0.71 + 0.017*sl 0.77 + 0.012*sl t phl 0.80 0.75 + 0.027*sl 0.76 + 0.021*sl 0.79 + 0.018*sl t r 0.24 0.19 + 0.025*sl 0.19 + 0.024*sl 0.18 + 0.025*sl t f 0.22 0.15 + 0.033*sl 0.15 + 0.031*sl 0.13 + 0.033*sl rn to q t plh 0.44 0.39 + 0.023*sl 0.40 + 0.017*sl 0.45 + 0.012*sl t phl 0.44 0.39 + 0.025*sl 0.40 + 0.020*sl 0.43 + 0.018*sl t r 0.23 0.18 + 0.026*sl 0.18 + 0.024*sl 0.17 + 0.025*sl t f 0.21 0.14 + 0.033*sl 0.15 + 0.030*sl 0.11 + 0.034*sl sn to q t plh 0.77 0.72 + 0.024*sl 0.74 + 0.017*sl 0.79 + 0.012*sl t r 0.24 0.18 + 0.026*sl 0.19 + 0.024*sl 0.17 + 0.025*sl ck to qn t plh 1.02 0.98 + 0.018*sl 0.99 + 0.014*sl 1.02 + 0.012*sl t phl 1.04 1.00 + 0.020*sl 1.00 + 0.017*sl 1.00 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.19 0.13 + 0.030*sl 0.13 + 0.030*sl 0.09 + 0.034*sl rn to qn t plh 0.66 0.62 + 0.018*sl 0.63 + 0.014*sl 0.65 + 0.012*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl sn to qn t plh 0.32 0.28 + 0.019*sl 0.29 + 0.015*sl 0.32 + 0.012*sl t phl 0.37 0.32 + 0.023*sl 0.33 + 0.019*sl 0.34 + 0.018*sl t r 0.19 0.14 + 0.022*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-351 STD80/stdm80 fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fj4s stdm80 fj4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.06 0.96 + 0.050*sl 0.99 + 0.041*sl 1.02 + 0.037*sl t phl 1.16 1.04 + 0.057*sl 1.07 + 0.049*sl 1.09 + 0.046*sl t r 0.37 0.22 + 0.072*sl 0.23 + 0.069*sl 0.24 + 0.068*sl t f 0.35 0.19 + 0.081*sl 0.19 + 0.079*sl 0.19 + 0.080*sl rn to q t plh 0.58 0.48 + 0.049*sl 0.51 + 0.040*sl 0.54 + 0.035*sl t phl 0.60 0.49 + 0.057*sl 0.52 + 0.049*sl 0.54 + 0.045*sl t r 0.35 0.21 + 0.071*sl 0.22 + 0.067*sl 0.21 + 0.068*sl t f 0.34 0.18 + 0.082*sl 0.19 + 0.079*sl 0.18 + 0.079*sl sn to q t plh 1.09 0.99 + 0.049*sl 1.02 + 0.040*sl 1.05 + 0.035*sl t r 0.36 0.22 + 0.070*sl 0.23 + 0.067*sl 0.22 + 0.068*sl ck to qn t plh 1.37 1.28 + 0.041*sl 1.30 + 0.036*sl 1.31 + 0.034*sl t phl 1.36 1.26 + 0.049*sl 1.27 + 0.045*sl 1.28 + 0.044*sl t r 0.31 0.17 + 0.067*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.079*sl 0.13 + 0.081*sl rn to qn t plh 0.81 0.73 + 0.041*sl 0.75 + 0.036*sl 0.76 + 0.034*sl t r 0.30 0.17 + 0.067*sl 0.17 + 0.068*sl 0.15 + 0.070*sl sn to qn t plh 0.42 0.34 + 0.042*sl 0.35 + 0.036*sl 0.37 + 0.034*sl t phl 0.48 0.38 + 0.051*sl 0.39 + 0.046*sl 0.40 + 0.045*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.080*sl 0.13 + 0.081*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.06 1.00 + 0.032*sl 1.02 + 0.025*sl 1.04 + 0.022*sl t phl 1.14 1.07 + 0.035*sl 1.09 + 0.028*sl 1.11 + 0.025*sl t r 0.30 0.22 + 0.038*sl 0.23 + 0.036*sl 0.23 + 0.035*sl t f 0.27 0.18 + 0.042*sl 0.19 + 0.039*sl 0.20 + 0.038*sl rn to q t plh 0.58 0.51 + 0.031*sl 0.53 + 0.025*sl 0.56 + 0.021*sl t phl 0.58 0.51 + 0.035*sl 0.53 + 0.029*sl 0.56 + 0.024*sl t r 0.28 0.21 + 0.037*sl 0.21 + 0.036*sl 0.22 + 0.034*sl t f 0.26 0.17 + 0.042*sl 0.18 + 0.039*sl 0.19 + 0.037*sl sn to q t plh 1.10 1.03 + 0.032*sl 1.06 + 0.025*sl 1.08 + 0.021*sl t r 0.29 0.21 + 0.040*sl 0.23 + 0.035*sl 0.24 + 0.034*sl ck to qn t plh 1.48 1.43 + 0.024*sl 1.44 + 0.020*sl 1.45 + 0.019*sl t phl 1.46 1.41 + 0.026*sl 1.42 + 0.023*sl 1.43 + 0.022*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.034*sl 0.19 + 0.034*sl t f 0.24 0.15 + 0.041*sl 0.16 + 0.038*sl 0.16 + 0.037*sl rn to qn t plh 0.92 0.87 + 0.024*sl 0.88 + 0.020*sl 0.89 + 0.019*sl t r 0.25 0.17 + 0.038*sl 0.18 + 0.034*sl 0.18 + 0.033*sl sn to qn t plh 0.44 0.38 + 0.027*sl 0.40 + 0.022*sl 0.42 + 0.019*sl t phl 0.47 0.41 + 0.031*sl 0.43 + 0.026*sl 0.45 + 0.023*sl t r 0.24 0.16 + 0.037*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-352 sec asic ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ft2 ft2d2 ft2 ft2d2 ck rn ck rn 0.5 0.7 0.5 0.9 6.3 7.0 stdm80 ft2 ft2d2 ft2 ft2d2 ck rn ck rn 0.6 1.3 0.6 1.3 6.3 7.0 parameter symbol STD80 stdm80 ft2 ft2d2 ft2 ft2d2 pulse width low (ck) t pwl 0.87 0.87 0.90 0.87 pulse width high (ck) t pwh 0.79 0.85 0.90 0.85 pulse width high (rn) t pwh 0.87 0.87 0.82 0.85 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to ck) t hd 0.38 0.38 0.44 0.44 ck q qn rn ck cl clb qn cl clb cl clb cl cl clb q clb rn rn rn rn truth table ck rn q (n+1) qn (n+1) 1 qn (n) q (n) x001
sec asic 3-353 STD80/stdm80 ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ft2 STD80 ft2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.86 0.79 + 0.033*sl 0.81 + 0.026*sl 0.83 + 0.024*sl t phl 0.83 0.75 + 0.040*sl 0.75 + 0.037*sl 0.75 + 0.037*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.12 + 0.064*sl 0.11 + 0.066*sl 0.08 + 0.069*sl rn to q t phl 0.39 0.31 + 0.041*sl 0.31 + 0.038*sl 0.32 + 0.037*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl ck to qn t plh 0.58 0.52 + 0.028*sl 0.53 + 0.024*sl 0.54 + 0.024*sl t phl 0.70 0.61 + 0.042*sl 0.62 + 0.038*sl 0.63 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.24 0.11 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl rn to qn t plh 0.61 0.55 + 0.029*sl 0.56 + 0.024*sl 0.57 + 0.023*sl t r 0.21 0.12 + 0.046*sl 0.11 + 0.048*sl 0.07 + 0.052*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.89 + 0.019*sl 0.90 + 0.015*sl 0.93 + 0.012*sl t phl 0.88 0.83 + 0.022*sl 0.84 + 0.019*sl 0.84 + 0.018*sl t r 0.21 0.16 + 0.023*sl 0.16 + 0.023*sl 0.14 + 0.026*sl t f 0.19 0.12 + 0.032*sl 0.13 + 0.031*sl 0.10 + 0.034*sl rn to q t phl 0.38 0.34 + 0.023*sl 0.34 + 0.020*sl 0.36 + 0.018*sl t f 0.18 0.12 + 0.032*sl 0.12 + 0.031*sl 0.09 + 0.034*sl ck to qn t plh 0.58 0.55 + 0.018*sl 0.56 + 0.014*sl 0.57 + 0.012*sl t phl 0.69 0.64 + 0.023*sl 0.65 + 0.020*sl 0.67 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.61 0.58 + 0.018*sl 0.59 + 0.013*sl 0.60 + 0.012*sl t r 0.17 0.13 + 0.020*sl 0.12 + 0.022*sl 0.09 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-354 sec asic ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ft2 stdm80 ft2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.25 1.16 + 0.044*sl 1.18 + 0.037*sl 1.20 + 0.034*sl t phl 1.18 1.07 + 0.052*sl 1.09 + 0.046*sl 1.10 + 0.045*sl t r 0.32 0.18 + 0.070*sl 0.19 + 0.068*sl 0.18 + 0.069*sl t f 0.32 0.16 + 0.081*sl 0.16 + 0.079*sl 0.15 + 0.080*sl rn to q t phl 0.51 0.41 + 0.054*sl 0.43 + 0.047*sl 0.44 + 0.045*sl t f 0.31 0.15 + 0.082*sl 0.15 + 0.080*sl 0.15 + 0.081*sl ck to qn t plh 0.83 0.75 + 0.038*sl 0.76 + 0.034*sl 0.77 + 0.034*sl t phl 0.99 0.88 + 0.051*sl 0.90 + 0.046*sl 0.91 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.070*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.082*sl rn to qn t plh 0.87 0.79 + 0.038*sl 0.81 + 0.034*sl 0.81 + 0.033*sl t r 0.29 0.16 + 0.064*sl 0.15 + 0.068*sl 0.13 + 0.071*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.34 1.28 + 0.027*sl 1.30 + 0.022*sl 1.31 + 0.020*sl t phl 1.24 1.18 + 0.030*sl 1.20 + 0.025*sl 1.21 + 0.023*sl t r 0.26 0.19 + 0.038*sl 0.20 + 0.034*sl 0.20 + 0.034*sl t f 0.24 0.15 + 0.042*sl 0.16 + 0.039*sl 0.17 + 0.038*sl rn to q t phl 0.50 0.44 + 0.032*sl 0.45 + 0.027*sl 0.48 + 0.024*sl t f 0.23 0.14 + 0.043*sl 0.16 + 0.039*sl 0.16 + 0.038*sl ck to qn t plh 0.83 0.78 + 0.024*sl 0.79 + 0.020*sl 0.81 + 0.017*sl t phl 0.98 0.92 + 0.031*sl 0.93 + 0.026*sl 0.95 + 0.023*sl t r 0.21 0.15 + 0.032*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.87 0.83 + 0.024*sl 0.84 + 0.020*sl 0.86 + 0.017*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.032*sl 0.14 + 0.033*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-355 STD80/stdm80 ft3/ft3d2 toggle flip-flop with set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ft3 ft3d2 ft3 ft3d2 ck sn ck sn 0.5 0.7 0.5 0.7 6.0 6.7 stdm80 ft3 ft3d2 ft3 ft3d2 ck sn ck sn 0.6 1.4 0.6 1.4 6.0 6.7 parameter symbol STD80 stdm80 ft3 ft3d2 ft3 ft3d2 pulse width low (ck) t pwl 0.87 0.87 0.87 0.85 pulse width high (ck) t pwh 0.82 0.87 0.93 0.90 pulse width high (sn) t pwh 0.87 0.87 0.82 0.87 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to ck) t hd 0.66 0.66 0.76 0.76 ck q qn sn ck cl clb cl clb qn cl clb cl cl clb q clb sn sn sn sn truth table ck sn q (n+1) qn (n+1) 1 qn (n) q (n) x010
STD80/stdm80 3-356 sec asic ft3/ft3d2 toggle flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ft3 STD80 ft3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.76 0.71 + 0.026*sl 0.71 + 0.024*sl 0.71 + 0.024*sl t phl 0.85 0.77 + 0.038*sl 0.78 + 0.037*sl 0.78 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.066*sl 0.07 + 0.069*sl sn to q t plh 0.45 0.39 + 0.026*sl 0.40 + 0.024*sl 0.40 + 0.023*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl ck to qn t plh 0.63 0.57 + 0.032*sl 0.58 + 0.026*sl 0.60 + 0.024*sl t phl 0.68 0.60 + 0.041*sl 0.60 + 0.038*sl 0.61 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to qn t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.30 + 0.037*sl t f 0.24 0.11 + 0.065*sl 0.11 + 0.066*sl 0.08 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.79 + 0.015*sl 0.80 + 0.013*sl 0.81 + 0.012*sl t phl 0.93 0.89 + 0.018*sl 0.89 + 0.018*sl 0.89 + 0.018*sl t r 0.16 0.12 + 0.023*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl sn to q t plh 0.51 0.48 + 0.015*sl 0.48 + 0.013*sl 0.49 + 0.012*sl t r 0.16 0.12 + 0.023*sl 0.12 + 0.023*sl 0.09 + 0.026*sl ck to qn t plh 0.64 0.60 + 0.021*sl 0.61 + 0.015*sl 0.65 + 0.012*sl t phl 0.67 0.62 + 0.023*sl 0.63 + 0.020*sl 0.65 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.11 + 0.031*sl 0.11 + 0.031*sl 0.09 + 0.034*sl sn to qn t phl 0.36 0.31 + 0.023*sl 0.32 + 0.020*sl 0.33 + 0.018*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-357 STD80/stdm80 ft3/ft3d2 toggle flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ft3 stdm80 ft3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.09 1.02 + 0.037*sl 1.03 + 0.034*sl 1.03 + 0.033*sl t phl 1.21 1.11 + 0.049*sl 1.12 + 0.045*sl 1.13 + 0.044*sl t r 0.27 0.14 + 0.066*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.079*sl 0.13 + 0.081*sl sn to q t plh 0.60 0.53 + 0.037*sl 0.54 + 0.034*sl 0.54 + 0.033*sl t r 0.27 0.14 + 0.066*sl 0.13 + 0.069*sl 0.11 + 0.071*sl ck to qn t plh 0.90 0.82 + 0.043*sl 0.83 + 0.037*sl 0.85 + 0.035*sl t phl 0.96 0.86 + 0.051*sl 0.87 + 0.047*sl 0.89 + 0.045*sl t r 0.31 0.18 + 0.069*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl sn to qn t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.39 + 0.045*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.081*sl 0.13 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.18 1.14 + 0.020*sl 1.15 + 0.018*sl 1.15 + 0.017*sl t phl 1.31 1.26 + 0.027*sl 1.27 + 0.023*sl 1.28 + 0.022*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.042*sl 0.16 + 0.038*sl 0.16 + 0.038*sl sn to q t plh 0.69 0.65 + 0.020*sl 0.66 + 0.018*sl 0.66 + 0.017*sl t r 0.21 0.14 + 0.034*sl 0.14 + 0.033*sl 0.14 + 0.033*sl ck to qn t plh 0.92 0.86 + 0.028*sl 0.88 + 0.022*sl 0.90 + 0.019*sl t phl 0.95 0.89 + 0.031*sl 0.90 + 0.026*sl 0.92 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.15 + 0.038*sl 0.15 + 0.038*sl 0.14 + 0.038*sl sn to qn t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t f 0.21 0.13 + 0.042*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-358 sec asic latches cell list cell name function description ld1 d latch with active high ld1d2 d latch with active high, 2x drive ld1s d latch with active high, scan ld1sd2 d latch with active high, scan, 2x drive ld1q d latch with active high, q output only ld1qd2 d latch with active high, q output only, 2x drive ld1x4 4-bit d latch with active high ld1x4d2 4-bit d latch with active high, 2x drive yld1 fast d latch with active high yld1d2 fast d latch with active high, 2x drive ld1a d latch with active high, tri-state output ld1b d latch with active high, tri-state output, separate wr, wrn ld2 d latch with active high, reset ld2d2 d latch with active high, reset, 2x drive ld2q d latch with active high, reset, q output only ld2qd2 d latch with active high, reset, q output only, 2x drive yld2 fast d latch with active high, reset yld2d2 fast d latch with active high, reset, 2x drive ld3 d latch with active high, set ld3d2 d latch with active high, set, 2x drive ld4 d latch with active high, reset, set ld4d2 d latch with active high, reset, set, 2x drive ld5 d latch with active low ld5d2 d latch with active low, 2x drive ld5s d latch with active low, scan ld5sd2 d latch with active low, scan, 2x drive ld5x4 4-bit d latch with active low ld5x4d2 4-bit d latch with active low, 2x drive ld6 d latch with active low, reset ld6d2 d latch with active low, reset, 2x drive ld7 d latch with active low, set ld7d2 d latch with active low, set, 2x drive ld8 d latch with active low, reset, set ld8d2 d latch with active low, reset, set, 2x drive
sec asic 3-359 STD80/stdm80 lds2 d latch with active high, synchronous clear lds6 d latch with active low, synchronous clear ls0 sr latch ls0d2 sr latch with 2x drive ls1 sr latch with separate inputs ls2 sr latch with common inputs cell name function description latches cell list (continued)
STD80/stdm80 3-360 sec asic ld1/ld1d2 d latch with active high, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld1 ld1d2 ld1 ld1d2 dgdg 0.5 0.5 0.5 0.5 4.0 4.7 stdm80 ld1 ld1d2 ld1 ld1d2 dgdg 0.6 0.6 0.6 0.6 4.0 4.7 parameter symbol STD80 stdm80 ld1 ld1d2 ld1 ld1d2 pulse width high (g) t pwh 0.79 0.79 0.82 0.82 input setup time (d to g) t su 0.66 0.71 0.66 0.71 input hold time (d to g) t hd 0.33 0.33 0.33 0.33 d g q qn g g gb d gb g g gb qn q truth table d g q (n+1) qn (n+1) 0101 1110 x 0 q (n) qn (n)
sec asic 3-361 STD80/stdm80 ld1/ld1d2 d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1 STD80 ld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.62 + 0.038*sl 0.62 + 0.037*sl 0.62 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl g to q t plh 0.62 0.57 + 0.025*sl 0.57 + 0.024*sl 0.57 + 0.024*sl t phl 0.69 0.62 + 0.038*sl 0.62 + 0.037*sl 0.62 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d to qn t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.041*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl g to qn t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.58 0.50 + 0.042*sl 0.51 + 0.038*sl 0.52 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.57 0.54 + 0.014*sl 0.55 + 0.012*sl 0.55 + 0.012*sl t phl 0.75 0.72 + 0.018*sl 0.72 + 0.018*sl 0.71 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl g to q t plh 0.69 0.66 + 0.013*sl 0.66 + 0.012*sl 0.67 + 0.012*sl t phl 0.75 0.71 + 0.018*sl 0.71 + 0.018*sl 0.71 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d to qn t plh 0.53 0.50 + 0.018*sl 0.51 + 0.014*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl g to qn t plh 0.53 0.50 + 0.018*sl 0.51 + 0.014*sl 0.52 + 0.012*sl t phl 0.57 0.53 + 0.023*sl 0.53 + 0.020*sl 0.55 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-362 sec asic ld1/ld1d2 d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld1 stdm80 ld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.72 0.65 + 0.035*sl 0.65 + 0.033*sl 0.66 + 0.033*sl t phl 0.96 0.87 + 0.046*sl 0.87 + 0.045*sl 0.88 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl g to q t plh 0.90 0.83 + 0.035*sl 0.84 + 0.033*sl 0.84 + 0.033*sl t phl 1.00 0.91 + 0.047*sl 0.92 + 0.045*sl 0.92 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d to qn t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.58 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl g to qn t plh 0.78 0.70 + 0.038*sl 0.71 + 0.035*sl 0.72 + 0.034*sl t phl 0.83 0.73 + 0.052*sl 0.74 + 0.046*sl 0.76 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.81 0.77 + 0.018*sl 0.77 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 0.99 + 0.023*sl 1.00 + 0.022*sl t r 0.19 0.13 + 0.033*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl g to q t plh 0.99 0.95 + 0.019*sl 0.96 + 0.017*sl 0.96 + 0.017*sl t phl 1.08 1.03 + 0.026*sl 1.04 + 0.023*sl 1.05 + 0.022*sl t r 0.19 0.13 + 0.030*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d to qn t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.64 0.58 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl g to qn t plh 0.78 0.73 + 0.024*sl 0.74 + 0.020*sl 0.76 + 0.018*sl t phl 0.82 0.76 + 0.031*sl 0.77 + 0.026*sl 0.79 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.038*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-363 STD80/stdm80 ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld1s ld1sd2 ld1s ld1sd2 d g si sg d g si sg 0.3 0.6 0.4 0.9 0.3 0.6 0.4 0.9 5.7 6.3 stdm80 ld1s ld1sd2 ld1s ld1sd2 d g si sg d g si sg 0.4 1.3 0.4 1.1 0.4 1.3 0.4 1.1 5.7 6.3 parameter symbol STD80 stdm80 ld1s ld1sd2 ld1s ld1sd2 pulse width high (g) t pwh 0.87 0.96 0.90 0.96 pulse width high (sg) t pwh 0.90 0.96 0.93 0.96 input setup time (d to g) t su 0.76 0.63 0.76 0.82 input hold time (d to g) t hd 0.37 0.33 0.33 0.33 input setup time (si to sg) t su 0.74 0.63 0.74 0.82 input hold time (si to sg) t hd 0.37 0.33 0.33 0.33 q qn d g si sg g qn sg d si q truth table d g si sg q (n+1) qn (n+1) x0x0q (n)qn (n) xx1110 x00101 11xx10 01x001 010101
STD80/stdm80 3-364 sec asic ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.62 0.57 + 0.025*sl 0.57 + 0.024*sl 0.57 + 0.024*sl t phl 0.79 0.72 + 0.037*sl 0.72 + 0.037*sl 0.72 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl si to q t plh 0.68 0.63 + 0.025*sl 0.63 + 0.024*sl 0.63 + 0.024*sl t phl 0.85 0.78 + 0.037*sl 0.78 + 0.037*sl 0.77 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl g to q t plh 0.69 0.64 + 0.025*sl 0.64 + 0.024*sl 0.64 + 0.024*sl t phl 0.73 0.66 + 0.037*sl 0.66 + 0.037*sl 0.66 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl sg to q t plh 0.73 0.68 + 0.025*sl 0.68 + 0.024*sl 0.68 + 0.024*sl t phl 0.74 0.67 + 0.038*sl 0.67 + 0.037*sl 0.67 + 0.037*sl t r 0.18 0.09 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d to qn t plh 0.62 0.56 + 0.029*sl 0.57 + 0.024*sl 0.58 + 0.024*sl t phl 0.58 0.50 + 0.041*sl 0.51 + 0.038*sl 0.51 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl si to qn t plh 0.68 0.62 + 0.029*sl 0.63 + 0.024*sl 0.64 + 0.024*sl t phl 0.64 0.56 + 0.041*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl g to qn t plh 0.56 0.51 + 0.028*sl 0.51 + 0.025*sl 0.52 + 0.024*sl t phl 0.65 0.57 + 0.042*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sg to qn t plh 0.58 0.52 + 0.028*sl 0.53 + 0.025*sl 0.53 + 0.024*sl t phl 0.69 0.61 + 0.042*sl 0.62 + 0.038*sl 0.62 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-365 STD80/stdm80 ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.69 0.66 + 0.013*sl 0.66 + 0.012*sl 0.67 + 0.012*sl t phl 0.85 0.82 + 0.018*sl 0.82 + 0.018*sl 0.81 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.033*sl 0.10 + 0.031*sl 0.07 + 0.034*sl si to q t plh 0.75 0.72 + 0.013*sl 0.72 + 0.012*sl 0.73 + 0.012*sl t phl 0.91 0.88 + 0.018*sl 0.88 + 0.018*sl 0.87 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.034*sl 0.10 + 0.031*sl 0.07 + 0.034*sl g to q t plh 0.76 0.73 + 0.013*sl 0.73 + 0.012*sl 0.74 + 0.012*sl t phl 0.79 0.75 + 0.018*sl 0.75 + 0.018*sl 0.75 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl sg to q t plh 0.80 0.77 + 0.013*sl 0.77 + 0.012*sl 0.78 + 0.012*sl t phl 0.80 0.77 + 0.018*sl 0.77 + 0.018*sl 0.76 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d to qn t plh 0.63 0.59 + 0.018*sl 0.60 + 0.014*sl 0.62 + 0.012*sl t phl 0.57 0.53 + 0.023*sl 0.53 + 0.020*sl 0.55 + 0.018*sl t r 0.17 0.13 + 0.021*sl 0.13 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.12 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl si to qn t plh 0.69 0.65 + 0.018*sl 0.66 + 0.014*sl 0.68 + 0.012*sl t phl 0.64 0.59 + 0.023*sl 0.60 + 0.020*sl 0.61 + 0.018*sl t r 0.18 0.13 + 0.022*sl 0.13 + 0.022*sl 0.10 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.11 + 0.031*sl 0.09 + 0.034*sl g to qn t plh 0.57 0.53 + 0.018*sl 0.54 + 0.014*sl 0.56 + 0.012*sl t phl 0.65 0.60 + 0.023*sl 0.61 + 0.020*sl 0.62 + 0.018*sl t r 0.17 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sg to qn t plh 0.58 0.55 + 0.018*sl 0.56 + 0.014*sl 0.57 + 0.012*sl t phl 0.68 0.64 + 0.023*sl 0.64 + 0.020*sl 0.66 + 0.018*sl t r 0.17 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.09 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-366 sec asic ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld1s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.88 0.81 + 0.035*sl 0.81 + 0.033*sl 0.81 + 0.033*sl t phl 1.15 1.06 + 0.046*sl 1.06 + 0.045*sl 1.07 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl si to q t plh 0.96 0.89 + 0.035*sl 0.89 + 0.033*sl 0.89 + 0.033*sl t phl 1.26 1.16 + 0.046*sl 1.17 + 0.045*sl 1.17 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl g to q t plh 1.00 0.93 + 0.035*sl 0.93 + 0.033*sl 0.93 + 0.033*sl t phl 1.06 0.96 + 0.046*sl 0.97 + 0.045*sl 0.97 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl sg to q t plh 1.04 0.97 + 0.034*sl 0.97 + 0.033*sl 0.97 + 0.033*sl t phl 1.06 0.96 + 0.047*sl 0.97 + 0.045*sl 0.98 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d to qn t plh 0.92 0.84 + 0.040*sl 0.86 + 0.035*sl 0.87 + 0.034*sl t phl 0.81 0.70 + 0.052*sl 0.72 + 0.046*sl 0.73 + 0.044*sl t r 0.30 0.17 + 0.065*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.082*sl si to qn t plh 1.03 0.95 + 0.040*sl 0.96 + 0.035*sl 0.97 + 0.033*sl t phl 0.89 0.78 + 0.052*sl 0.80 + 0.047*sl 0.81 + 0.044*sl t r 0.30 0.17 + 0.065*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.14 + 0.081*sl g to qn t plh 0.83 0.75 + 0.039*sl 0.76 + 0.035*sl 0.77 + 0.034*sl t phl 0.93 0.83 + 0.052*sl 0.84 + 0.046*sl 0.86 + 0.044*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.078*sl 0.15 + 0.080*sl 0.13 + 0.081*sl sg to qn t plh 0.83 0.75 + 0.039*sl 0.77 + 0.035*sl 0.78 + 0.034*sl t phl 0.97 0.87 + 0.052*sl 0.88 + 0.046*sl 0.90 + 0.044*sl t r 0.29 0.15 + 0.066*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.14 + 0.081*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-367 STD80/stdm80 ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.97 0.93 + 0.018*sl 0.94 + 0.017*sl 0.94 + 0.017*sl t phl 1.24 1.19 + 0.025*sl 1.20 + 0.023*sl 1.20 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl si to q t plh 1.05 1.01 + 0.018*sl 1.02 + 0.017*sl 1.02 + 0.017*sl t phl 1.35 1.30 + 0.025*sl 1.30 + 0.023*sl 1.31 + 0.021*sl t r 0.19 0.13 + 0.033*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl g to q t plh 1.09 1.06 + 0.018*sl 1.06 + 0.017*sl 1.06 + 0.017*sl t phl 1.14 1.09 + 0.025*sl 1.09 + 0.023*sl 1.10 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl sg to q t plh 1.13 1.10 + 0.018*sl 1.10 + 0.017*sl 1.11 + 0.017*sl t phl 1.14 1.09 + 0.025*sl 1.10 + 0.023*sl 1.11 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d to qn t plh 0.93 0.88 + 0.024*sl 0.90 + 0.020*sl 0.91 + 0.018*sl t phl 0.80 0.73 + 0.031*sl 0.75 + 0.026*sl 0.77 + 0.023*sl t r 0.23 0.16 + 0.032*sl 0.16 + 0.033*sl 0.16 + 0.033*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl si to qn t plh 1.04 0.99 + 0.025*sl 1.00 + 0.020*sl 1.02 + 0.018*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.023*sl t r 0.23 0.17 + 0.032*sl 0.17 + 0.032*sl 0.16 + 0.033*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl g to qn t plh 0.83 0.78 + 0.024*sl 0.80 + 0.020*sl 0.81 + 0.018*sl t phl 0.92 0.86 + 0.031*sl 0.87 + 0.026*sl 0.89 + 0.023*sl t r 0.22 0.15 + 0.032*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl sg to qn t plh 0.84 0.79 + 0.024*sl 0.80 + 0.020*sl 0.82 + 0.018*sl t phl 0.96 0.90 + 0.031*sl 0.91 + 0.026*sl 0.93 + 0.023*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-368 sec asic ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld1q ld1qd2 ld1q ld1qd2 dgdg 0.3 0.6 0.3 0.6 3.7 4.0 stdm80 ld1q ld1qd2 ld1q ld1qd2 dgdg 0.9 0.9 0.9 0.9 3.7 4.0 parameter symbol STD80 stdm80 ld1q ld1qd2 ld1q ld1qd2 pulse width high (g) t pwh 0.87 0.87 0.82 0.82 input setup time (d to g) t su 0.46 0.49 0.55 0.57 input hold time (d to g) t hd 0.33 0.33 0.35 0.33 d g q g g gb d gb g g gb q truth table d g q (n+1) 010 111 x 0 q (n)
sec asic 3-369 STD80/stdm80 ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1q STD80 ld1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.48 0.43 + 0.026*sl 0.43 + 0.024*sl 0.43 + 0.024*sl t phl 0.60 0.52 + 0.039*sl 0.53 + 0.037*sl 0.53 + 0.037*sl t r 0.18 0.09 + 0.048*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.07 + 0.069*sl g to q t plh 0.59 0.54 + 0.025*sl 0.54 + 0.024*sl 0.54 + 0.024*sl t phl 0.60 0.52 + 0.039*sl 0.53 + 0.037*sl 0.53 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.49 0.45 + 0.016*sl 0.46 + 0.013*sl 0.47 + 0.012*sl t phl 0.60 0.55 + 0.022*sl 0.56 + 0.019*sl 0.57 + 0.018*sl t r 0.14 0.10 + 0.024*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.15 0.09 + 0.029*sl 0.09 + 0.032*sl 0.07 + 0.034*sl g to q t plh 0.60 0.57 + 0.017*sl 0.57 + 0.013*sl 0.58 + 0.012*sl t phl 0.60 0.55 + 0.022*sl 0.56 + 0.019*sl 0.57 + 0.018*sl t r 0.14 0.10 + 0.023*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.15 0.09 + 0.030*sl 0.09 + 0.032*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-370 sec asic ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld1q stdm80 ld1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.68 0.61 + 0.035*sl 0.61 + 0.033*sl 0.61 + 0.033*sl t phl 0.83 0.73 + 0.048*sl 0.74 + 0.045*sl 0.74 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl g to q t plh 0.86 0.79 + 0.035*sl 0.80 + 0.034*sl 0.80 + 0.033*sl t phl 0.87 0.77 + 0.048*sl 0.78 + 0.045*sl 0.79 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.11 + 0.082*sl *g 1 sl 3 *g 2 3 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.68 0.64 + 0.022*sl 0.65 + 0.019*sl 0.66 + 0.017*sl t phl 0.82 0.77 + 0.029*sl 0.78 + 0.024*sl 0.79 + 0.022*sl t r 0.18 0.12 + 0.033*sl 0.12 + 0.034*sl 0.11 + 0.034*sl t f 0.20 0.11 + 0.040*sl 0.12 + 0.038*sl 0.12 + 0.039*sl g to q t plh 0.87 0.82 + 0.022*sl 0.83 + 0.018*sl 0.84 + 0.017*sl t phl 0.87 0.81 + 0.029*sl 0.82 + 0.025*sl 0.84 + 0.022*sl t r 0.18 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.19 0.12 + 0.040*sl 0.12 + 0.038*sl 0.12 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-371 STD80/stdm80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive logic symbol cell data timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld1x4 ld1x4d2 ld1x4 ld1x4d2 dngdng 0.5 0.5 0.5 0.5 13.0 15.3 stdm80 ld1x4 ld1x4d2 ld1x4 ld1x4d2 dngdng 0.6 0.6 0.6 0.6 13.0 15.3 parameter symbol STD80 stdm80 ld1x4 ld1x4d2 ld1x4 ld1x4d2 pulse width high (g) t pwh 0.79 0.82 0.82 0.82 input setup time (d0 to g) t su 0.44 0.57 0.52 0.55 input hold time (d0 to g) t hd 0.55 0.55 0.60 0.55 input setup time (d1 to g) t su 0.44 0.00 0.52 0.57 input hold time (d1 to g) t hd 0.55 0.49 0.60 0.55 input setup time (d2 to g) t su 0.44 0.57 0.52 0.55 input hold time (d2 to g) t hd 0.55 0.55 0.60 0.55 input setup time (d3 to g) t su 0.44 0.00 0.52 0.55 input hold time (d3 to g) t hd 0.55 0.55 0.60 7.30 d0 d1 d2 d3 g q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table dn g qn (n+1) qnn (n+1) 0101 1110 x 0 qn (n) qnn (n)
STD80/stdm80 3-372 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1x4 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.62 + 0.038*sl 0.62 + 0.037*sl 0.62 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl g to q0 t plh 0.86 0.81 + 0.025*sl 0.81 + 0.024*sl 0.81 + 0.024*sl t phl 0.82 0.74 + 0.038*sl 0.75 + 0.037*sl 0.75 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d1 to q1 t plh 0.51 0.46 + 0.026*sl 0.46 + 0.023*sl 0.46 + 0.024*sl t phl 0.70 0.63 + 0.037*sl 0.63 + 0.037*sl 0.63 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl g to q1 t plh 0.86 0.81 + 0.025*sl 0.81 + 0.024*sl 0.81 + 0.024*sl t phl 0.82 0.75 + 0.037*sl 0.75 + 0.037*sl 0.75 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d2 to q2 t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.63 + 0.038*sl 0.63 + 0.037*sl 0.63 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl g to q2 t plh 0.86 0.81 + 0.025*sl 0.81 + 0.024*sl 0.81 + 0.024*sl t phl 0.82 0.75 + 0.038*sl 0.75 + 0.037*sl 0.75 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d3 to q3 t plh 0.51 0.46 + 0.026*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.62 + 0.038*sl 0.62 + 0.037*sl 0.62 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl g to q3 t plh 0.85 0.80 + 0.025*sl 0.81 + 0.024*sl 0.81 + 0.024*sl t phl 0.83 0.75 + 0.038*sl 0.75 + 0.037*sl 0.75 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d0 to qn0 t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.042*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl g to qn0 t plh 0.65 0.60 + 0.028*sl 0.60 + 0.024*sl 0.61 + 0.024*sl t phl 0.82 0.74 + 0.041*sl 0.74 + 0.038*sl 0.75 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-373 STD80/stdm80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1x4 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.041*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl g to qn1 t plh 0.66 0.60 + 0.028*sl 0.61 + 0.024*sl 0.61 + 0.024*sl t phl 0.82 0.74 + 0.042*sl 0.74 + 0.038*sl 0.75 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl d2 to qn2 t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.042*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl g to qn2 t plh 0.66 0.60 + 0.028*sl 0.61 + 0.024*sl 0.61 + 0.024*sl t phl 0.82 0.74 + 0.042*sl 0.74 + 0.038*sl 0.75 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl d3 to qn3 t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.042*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl g to qn3 t plh 0.66 0.60 + 0.027*sl 0.61 + 0.024*sl 0.62 + 0.024*sl t phl 0.82 0.74 + 0.041*sl 0.74 + 0.038*sl 0.75 + 0.037*sl t r 0.20 0.11 + 0.047*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-374 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1x4d2 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.57 0.54 + 0.014*sl 0.55 + 0.012*sl 0.55 + 0.012*sl t phl 0.75 0.71 + 0.019*sl 0.72 + 0.018*sl 0.71 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl g to q0 t plh 0.93 0.90 + 0.013*sl 0.90 + 0.012*sl 0.91 + 0.012*sl t phl 0.88 0.84 + 0.019*sl 0.84 + 0.018*sl 0.84 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d1 to q1 t plh 0.57 0.55 + 0.013*sl 0.55 + 0.012*sl 0.56 + 0.012*sl t phl 0.76 0.72 + 0.018*sl 0.72 + 0.018*sl 0.72 + 0.018*sl t r 0.15 0.11 + 0.019*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.10 + 0.031*sl 0.07 + 0.034*sl g to q1 t plh 0.93 0.90 + 0.013*sl 0.91 + 0.012*sl 0.91 + 0.012*sl t phl 0.88 0.84 + 0.018*sl 0.85 + 0.018*sl 0.84 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d2 to q2 t plh 0.57 0.55 + 0.014*sl 0.55 + 0.012*sl 0.56 + 0.012*sl t phl 0.76 0.72 + 0.019*sl 0.72 + 0.018*sl 0.72 + 0.018*sl t r 0.15 0.11 + 0.019*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.10 + 0.031*sl 0.07 + 0.034*sl g to q2 t plh 0.93 0.90 + 0.014*sl 0.91 + 0.012*sl 0.91 + 0.012*sl t phl 0.88 0.84 + 0.019*sl 0.85 + 0.018*sl 0.84 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d3 to q3 t plh 0.57 0.54 + 0.014*sl 0.55 + 0.012*sl 0.55 + 0.012*sl t phl 0.75 0.72 + 0.018*sl 0.72 + 0.018*sl 0.71 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl g to q3 t plh 0.93 0.90 + 0.013*sl 0.90 + 0.012*sl 0.91 + 0.012*sl t phl 0.88 0.85 + 0.019*sl 0.85 + 0.018*sl 0.85 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d0 to qn0 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.013*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl g to qn0 t plh 0.66 0.63 + 0.018*sl 0.64 + 0.014*sl 0.65 + 0.012*sl t phl 0.82 0.77 + 0.023*sl 0.78 + 0.020*sl 0.79 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-375 STD80/stdm80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1x4d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.013*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl g to qn1 t plh 0.66 0.63 + 0.018*sl 0.64 + 0.014*sl 0.65 + 0.012*sl t phl 0.82 0.77 + 0.023*sl 0.78 + 0.020*sl 0.79 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl d2 to qn2 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.013*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl g to qn2 t plh 0.66 0.63 + 0.018*sl 0.64 + 0.014*sl 0.65 + 0.012*sl t phl 0.82 0.77 + 0.023*sl 0.78 + 0.020*sl 0.79 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl d3 to qn3 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.013*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl g to qn3 t plh 0.67 0.63 + 0.018*sl 0.64 + 0.013*sl 0.66 + 0.012*sl t phl 0.81 0.77 + 0.023*sl 0.77 + 0.020*sl 0.79 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-376 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld1x4 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.72 0.65 + 0.035*sl 0.65 + 0.033*sl 0.65 + 0.033*sl t phl 0.96 0.87 + 0.047*sl 0.87 + 0.045*sl 0.88 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl g to q0 t plh 1.23 1.16 + 0.035*sl 1.16 + 0.033*sl 1.16 + 0.033*sl t phl 1.14 1.05 + 0.047*sl 1.06 + 0.045*sl 1.06 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d1 to q1 t plh 0.72 0.65 + 0.035*sl 0.66 + 0.033*sl 0.66 + 0.033*sl t phl 0.97 0.87 + 0.047*sl 0.88 + 0.045*sl 0.88 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl g to q1 t plh 1.23 1.16 + 0.035*sl 1.17 + 0.033*sl 1.17 + 0.033*sl t phl 1.15 1.06 + 0.047*sl 1.06 + 0.045*sl 1.07 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d2 to q2 t plh 0.72 0.65 + 0.035*sl 0.66 + 0.033*sl 0.66 + 0.033*sl t phl 0.97 0.87 + 0.046*sl 0.88 + 0.045*sl 0.88 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl g to q2 t plh 1.23 1.16 + 0.035*sl 1.17 + 0.033*sl 1.17 + 0.033*sl t phl 1.15 1.06 + 0.047*sl 1.06 + 0.045*sl 1.07 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d3 to q3 t plh 0.72 0.65 + 0.035*sl 0.65 + 0.033*sl 0.65 + 0.033*sl t phl 0.96 0.87 + 0.047*sl 0.87 + 0.045*sl 0.88 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl g to q3 t plh 1.22 1.16 + 0.035*sl 1.16 + 0.033*sl 1.16 + 0.033*sl t phl 1.15 1.06 + 0.046*sl 1.06 + 0.045*sl 1.07 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d0 to qn0 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.051*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl g to qn0 t plh 0.92 0.84 + 0.038*sl 0.85 + 0.035*sl 0.86 + 0.034*sl t phl 1.16 1.05 + 0.052*sl 1.07 + 0.046*sl 1.08 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-377 STD80/stdm80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) stdm80 ld1x4 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.54 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl g to qn1 t plh 0.92 0.85 + 0.038*sl 0.86 + 0.035*sl 0.86 + 0.034*sl t phl 1.16 1.05 + 0.052*sl 1.07 + 0.046*sl 1.08 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl d2 to qn2 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl g to qn2 t plh 0.92 0.84 + 0.038*sl 0.86 + 0.035*sl 0.86 + 0.034*sl t phl 1.16 1.05 + 0.052*sl 1.07 + 0.046*sl 1.08 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl d3 to qn3 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl g to qn3 t plh 0.93 0.85 + 0.038*sl 0.86 + 0.035*sl 0.87 + 0.034*sl t phl 1.15 1.05 + 0.052*sl 1.07 + 0.046*sl 1.08 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-378 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) stdm80 ld1x4d2 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.81 0.77 + 0.018*sl 0.77 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.00 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl g to q0 t plh 1.33 1.29 + 0.018*sl 1.29 + 0.017*sl 1.30 + 0.017*sl t phl 1.22 1.17 + 0.026*sl 1.18 + 0.023*sl 1.19 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d1 to q1 t plh 0.81 0.77 + 0.018*sl 0.78 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.01 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.041*sl 0.13 + 0.038*sl 0.13 + 0.038*sl g to q1 t plh 1.33 1.29 + 0.019*sl 1.30 + 0.017*sl 1.30 + 0.017*sl t phl 1.23 1.18 + 0.026*sl 1.18 + 0.023*sl 1.19 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d2 to q2 t plh 0.81 0.77 + 0.018*sl 0.78 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.01 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl g to q2 t plh 1.33 1.29 + 0.019*sl 1.30 + 0.017*sl 1.30 + 0.017*sl t phl 1.23 1.18 + 0.026*sl 1.18 + 0.023*sl 1.19 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d3 to q3 t plh 0.81 0.77 + 0.019*sl 0.77 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.00 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl g to q3 t plh 1.32 1.29 + 0.018*sl 1.29 + 0.017*sl 1.29 + 0.017*sl t phl 1.23 1.18 + 0.025*sl 1.19 + 0.023*sl 1.20 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d0 to qn0 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.64 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl g to qn0 t plh 0.93 0.88 + 0.024*sl 0.89 + 0.019*sl 0.90 + 0.018*sl t phl 1.15 1.09 + 0.031*sl 1.11 + 0.026*sl 1.12 + 0.023*sl t r 0.21 0.14 + 0.032*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-379 STD80/stdm80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) stdm80 ld1x4d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.64 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl g to qn1 t plh 0.93 0.88 + 0.024*sl 0.89 + 0.020*sl 0.91 + 0.018*sl t phl 1.15 1.09 + 0.031*sl 1.11 + 0.026*sl 1.13 + 0.023*sl t r 0.21 0.14 + 0.032*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl d2 to qn2 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.64 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl g to qn2 t plh 0.93 0.88 + 0.024*sl 0.89 + 0.019*sl 0.90 + 0.018*sl t phl 1.15 1.09 + 0.031*sl 1.11 + 0.026*sl 1.13 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.22 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl d3 to qn3 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.63 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl g to qn3 t plh 0.93 0.88 + 0.024*sl 0.90 + 0.020*sl 0.91 + 0.018*sl t phl 1.15 1.09 + 0.031*sl 1.11 + 0.026*sl 1.12 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.13 + 0.041*sl 0.14 + 0.038*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-380 sec asic yld1/yld1d2 fast d latch with active high, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 yld1 yld1d2 yld1 yld1d2 dgdg 2.1 0.5 3.1 0.5 2.7 3.7 stdm80 yld1 yld1d2 yld1 yld1d2 dgdg 2.4 0.6 3.5 0.6 2.7 3.7 parameter symbol STD80 stdm80 yld1 yld1d2 yld1 yld1d2 pulse width high (g) t pwh 0.87 0.87 0.82 0.82 input setup time (d to g) t su 0.41 0.38 0.49 0.46 input hold time (d to g) t hd 0.33 0.33 0.33 0.33 d g q qn g g gb d gb g g gb qn q truth table d g q (n+1) qn (n+1) 0101 1110 x 0 q (n) qn (n)
sec asic 3-381 STD80/stdm80 yld1/yld1d2 fast d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 yld1 STD80 yld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.42 0.26 + 0.080*sl 0.27 + 0.075*sl 0.27 + 0.075*sl t phl 0.40 0.25 + 0.076*sl 0.26 + 0.072*sl 0.26 + 0.072*sl t r 0.23 0.10 + 0.064*sl 0.10 + 0.064*sl 0.09 + 0.065*sl t f 0.24 0.09 + 0.072*sl 0.09 + 0.076*sl 0.08 + 0.076*sl g to q t plh 0.57 0.42 + 0.078*sl 0.42 + 0.076*sl 0.42 + 0.075*sl t phl 0.54 0.40 + 0.073*sl 0.40 + 0.072*sl 0.40 + 0.072*sl t r 0.22 0.10 + 0.064*sl 0.09 + 0.065*sl 0.09 + 0.065*sl t f 0.23 0.08 + 0.075*sl 0.08 + 0.076*sl 0.08 + 0.076*sl d to qn t plh 0.23 0.17 + 0.030*sl 0.18 + 0.024*sl 0.18 + 0.024*sl t phl 0.29 0.22 + 0.039*sl 0.22 + 0.036*sl 0.22 + 0.037*sl t r 0.30 0.22 + 0.039*sl 0.20 + 0.046*sl 0.14 + 0.052*sl t f 0.36 0.26 + 0.050*sl 0.24 + 0.061*sl 0.16 + 0.069*sl g to qn t plh 0.37 0.32 + 0.024*sl 0.33 + 0.024*sl 0.33 + 0.024*sl t phl 0.45 0.37 + 0.039*sl 0.37 + 0.037*sl 0.37 + 0.037*sl t r 0.23 0.14 + 0.046*sl 0.13 + 0.050*sl 0.11 + 0.052*sl t f 0.30 0.17 + 0.062*sl 0.16 + 0.066*sl 0.14 + 0.069*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.36 0.27 + 0.043*sl 0.28 + 0.038*sl 0.29 + 0.037*sl t phl 0.34 0.26 + 0.039*sl 0.26 + 0.037*sl 0.27 + 0.035*sl t r 0.16 0.10 + 0.030*sl 0.09 + 0.031*sl 0.08 + 0.033*sl t f 0.15 0.08 + 0.034*sl 0.08 + 0.037*sl 0.07 + 0.038*sl g to q t plh 0.53 0.45 + 0.040*sl 0.45 + 0.039*sl 0.46 + 0.037*sl t phl 0.49 0.40 + 0.042*sl 0.42 + 0.036*sl 0.42 + 0.036*sl t r 0.15 0.09 + 0.029*sl 0.09 + 0.032*sl 0.08 + 0.033*sl t f 0.15 0.08 + 0.034*sl 0.07 + 0.037*sl 0.07 + 0.038*sl d to qn t plh 0.22 0.19 + 0.017*sl 0.20 + 0.013*sl 0.21 + 0.012*sl t phl 0.27 0.23 + 0.022*sl 0.24 + 0.019*sl 0.25 + 0.018*sl t r 0.25 0.21 + 0.018*sl 0.20 + 0.021*sl 0.16 + 0.026*sl t f 0.31 0.26 + 0.023*sl 0.26 + 0.027*sl 0.20 + 0.033*sl g to qn t plh 0.38 0.34 + 0.018*sl 0.35 + 0.012*sl 0.36 + 0.012*sl t phl 0.45 0.40 + 0.021*sl 0.41 + 0.019*sl 0.42 + 0.018*sl t r 0.19 0.16 + 0.017*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.25 0.19 + 0.029*sl 0.19 + 0.030*sl 0.15 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-382 sec asic yld1/yld1d2 fast d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 yld1 stdm80 yld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.57 0.36 + 0.103*sl 0.38 + 0.100*sl 0.38 + 0.099*sl t phl 0.54 0.34 + 0.098*sl 0.35 + 0.096*sl 0.35 + 0.096*sl t r 0.30 0.13 + 0.085*sl 0.13 + 0.086*sl 0.13 + 0.087*sl t f 0.30 0.11 + 0.095*sl 0.11 + 0.094*sl 0.11 + 0.095*sl g to q t plh 0.81 0.60 + 0.103*sl 0.61 + 0.100*sl 0.62 + 0.099*sl t phl 0.77 0.58 + 0.097*sl 0.58 + 0.096*sl 0.58 + 0.096*sl t r 0.30 0.13 + 0.086*sl 0.13 + 0.087*sl 0.13 + 0.087*sl t f 0.30 0.11 + 0.094*sl 0.11 + 0.095*sl 0.11 + 0.095*sl d to qn t plh 0.31 0.24 + 0.035*sl 0.25 + 0.033*sl 0.25 + 0.033*sl t phl 0.38 0.28 + 0.049*sl 0.30 + 0.045*sl 0.30 + 0.044*sl t r 0.34 0.21 + 0.065*sl 0.19 + 0.069*sl 0.18 + 0.071*sl t f 0.41 0.26 + 0.071*sl 0.24 + 0.077*sl 0.22 + 0.080*sl g to qn t plh 0.54 0.47 + 0.034*sl 0.48 + 0.034*sl 0.48 + 0.033*sl t phl 0.62 0.52 + 0.049*sl 0.53 + 0.045*sl 0.54 + 0.044*sl t r 0.32 0.19 + 0.068*sl 0.18 + 0.070*sl 0.17 + 0.072*sl t f 0.38 0.22 + 0.076*sl 0.21 + 0.080*sl 0.20 + 0.081*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.50 0.38 + 0.056*sl 0.39 + 0.052*sl 0.41 + 0.050*sl t phl 0.46 0.36 + 0.050*sl 0.36 + 0.048*sl 0.37 + 0.047*sl t r 0.20 0.12 + 0.041*sl 0.12 + 0.042*sl 0.11 + 0.043*sl t f 0.19 0.10 + 0.045*sl 0.09 + 0.046*sl 0.09 + 0.046*sl g to q t plh 0.77 0.66 + 0.056*sl 0.67 + 0.052*sl 0.68 + 0.050*sl t phl 0.69 0.59 + 0.050*sl 0.60 + 0.048*sl 0.61 + 0.047*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.042*sl 0.11 + 0.043*sl t f 0.19 0.09 + 0.046*sl 0.09 + 0.046*sl 0.09 + 0.046*sl d to qn t plh 0.31 0.27 + 0.019*sl 0.28 + 0.018*sl 0.28 + 0.017*sl t phl 0.37 0.31 + 0.029*sl 0.32 + 0.025*sl 0.33 + 0.023*sl t r 0.26 0.20 + 0.029*sl 0.19 + 0.033*sl 0.18 + 0.034*sl t f 0.34 0.28 + 0.032*sl 0.27 + 0.035*sl 0.25 + 0.037*sl g to qn t plh 0.55 0.51 + 0.019*sl 0.51 + 0.018*sl 0.52 + 0.017*sl t phl 0.64 0.58 + 0.029*sl 0.59 + 0.025*sl 0.61 + 0.023*sl t r 0.25 0.19 + 0.030*sl 0.18 + 0.033*sl 0.18 + 0.034*sl t f 0.32 0.25 + 0.033*sl 0.24 + 0.037*sl 0.24 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-383 STD80/stdm80 ld1a d latch with active high, tri-state output logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) output load (sl) gate count STD80 dgeq 4.7 0.6 0.6 0.9 0.9 stdm80 dgeq 4.7 0.6 0.6 1.0 1.0 parameter symbol STD80 stdm80 pulse width high (g) t pwh 0.79 0.82 input setup time (d to g) t su 0.57 0.57 input hold time (d to g) t hd 0.33 0.33 d g q e d gb g e q g gb g g gb truth table d g e q (n+1) x x 0 hi-z 0110 1111 x 0 1 q (n)
STD80/stdm80 3-384 sec asic ld1a d latch with active high, tri-state output switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1a switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld1a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.52 + 0.021*sl 0.53 + 0.015*sl 0.56 + 0.012*sl t phl 0.66 0.58 + 0.037*sl 0.58 + 0.038*sl 0.58 + 0.039*sl t r 0.16 0.11 + 0.029*sl 0.12 + 0.025*sl 0.10 + 0.027*sl t f 0.26 0.11 + 0.071*sl 0.10 + 0.076*sl 0.09 + 0.078*sl g to q t plh 0.67 0.63 + 0.021*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t phl 0.66 0.59 + 0.036*sl 0.58 + 0.038*sl 0.58 + 0.039*sl t r 0.16 0.11 + 0.028*sl 0.11 + 0.025*sl 0.10 + 0.027*sl t f 0.26 0.12 + 0.070*sl 0.10 + 0.076*sl 0.09 + 0.078*sl e to q t plh 0.22 0.18 + 0.023*sl 0.19 + 0.016*sl 0.22 + 0.012*sl t phl 0.15 0.03 + 0.058*sl 0.07 + 0.040*sl 0.09 + 0.039*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.11 + 0.027*sl t f 0.34 0.19 + 0.070*sl 0.20 + 0.070*sl 0.12 + 0.078*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.33 0.33 + -0.001*sl 0.33 + 0.000*sl 0.33 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.82 0.76 + 0.027*sl 0.78 + 0.021*sl 0.80 + 0.019*sl t phl 0.90 0.80 + 0.050*sl 0.80 + 0.049*sl 0.80 + 0.050*sl t r 0.22 0.15 + 0.037*sl 0.16 + 0.035*sl 0.15 + 0.036*sl t f 0.34 0.15 + 0.094*sl 0.13 + 0.098*sl 0.13 + 0.099*sl g to q t plh 1.00 0.95 + 0.027*sl 0.96 + 0.021*sl 0.98 + 0.019*sl t phl 0.94 0.84 + 0.050*sl 0.85 + 0.049*sl 0.84 + 0.050*sl t r 0.22 0.15 + 0.037*sl 0.16 + 0.035*sl 0.15 + 0.036*sl t f 0.34 0.15 + 0.095*sl 0.14 + 0.098*sl 0.13 + 0.099*sl e to q t plh 0.32 0.26 + 0.028*sl 0.28 + 0.021*sl 0.30 + 0.019*sl t phl 0.22 0.11 + 0.054*sl 0.13 + 0.049*sl 0.13 + 0.050*sl t r 0.24 0.18 + 0.032*sl 0.17 + 0.034*sl 0.16 + 0.035*sl t f 0.38 0.21 + 0.086*sl 0.19 + 0.093*sl 0.15 + 0.097*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.42 0.42 + 0.000*sl 0.42 + 0.000*sl 0.42 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-385 STD80/stdm80 ld1b d latch with active high, tri-state output, separate wr, wrn logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) output load (sl) gate count STD80 d wr wrn rd zn 4.0 0.6 0.5 0.6 1.1 0.9 stdm80 d wr wrn rd zn 4.0 0.6 0.6 0.6 1.1 1.0 parameter symbol STD80 stdm80 pulse width high (wr) t pwh 0.87 1.18 pulse width low (wrn) t pwl 0.87 1.18 input setup time (d to wr) t su 0.93 1.31 input hold time (d to wr) t hd 0.33 0.33 input setup time (d to wrn) t su 0.93 1.31 input hold time (d to wrn) t hd 0.52 0.33 skew time (wr to wrn) t sk 0.78 0.88 skew time (wrn to wr) t sk 0.78 0.88 d wr wrn zn rd qn d wrn wr rd qn wrn wr wr wr wrn wrn zn truth table d wr wrn rd qn (n+1) zn (n+1) 01001 hi-z 11000 hi-z 010111 110100 x 0 1 0 qn (n) hi-z x 0 1 1 qn (n) qn (n)
STD80/stdm80 3-386 sec asic ld1b d latch with active high, tri-state output, separate wr, wrn switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld1b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to qn t plh 0.40 0.26 + 0.070*sl 0.26 + 0.070*sl 0.26 + 0.070*sl t phl 0.25 0.15 + 0.050*sl 0.16 + 0.046*sl 0.17 + 0.045*sl t r 0.78 0.40 + 0.190*sl 0.38 + 0.199*sl 0.34 + 0.204*sl t f 0.43 0.25 + 0.087*sl 0.23 + 0.096*sl 0.17 + 0.102*sl wr to qn t plh 0.30 0.19 + 0.055*sl 0.17 + 0.066*sl 0.13 + 0.070*sl t phl 0.21 0.11 + 0.049*sl 0.12 + 0.043*sl 0.11 + 0.045*sl t r 0.78 0.41 + 0.182*sl 0.38 + 0.197*sl 0.32 + 0.204*sl t f 0.44 0.28 + 0.082*sl 0.25 + 0.094*sl 0.17 + 0.102*sl wrn to qn t plh 0.30 0.19 + 0.055*sl 0.17 + 0.066*sl 0.13 + 0.070*sl t phl 0.21 0.11 + 0.049*sl 0.12 + 0.043*sl 0.11 + 0.045*sl t r 0.78 0.41 + 0.182*sl 0.38 + 0.197*sl 0.32 + 0.204*sl t f 0.44 0.28 + 0.082*sl 0.25 + 0.094*sl 0.17 + 0.102*sl d to zn t plh 0.87 0.68 + 0.092*sl 0.71 + 0.081*sl 0.80 + 0.071*sl t phl 0.81 0.59 + 0.112*sl 0.61 + 0.104*sl 0.69 + 0.095*sl t r 0.18 0.13 + 0.024*sl 0.13 + 0.025*sl 0.11 + 0.027*sl t f 0.26 0.11 + 0.072*sl 0.10 + 0.076*sl 0.09 + 0.078*sl wr to zn t plh 0.77 0.61 + 0.080*sl 0.61 + 0.076*sl 0.67 + 0.071*sl t phl 0.77 0.55 + 0.112*sl 0.57 + 0.101*sl 0.63 + 0.095*sl t r 0.18 0.13 + 0.023*sl 0.13 + 0.025*sl 0.11 + 0.027*sl t f 0.26 0.11 + 0.075*sl 0.10 + 0.076*sl 0.09 + 0.078*sl wrn to zn t plh 0.77 0.61 + 0.080*sl 0.61 + 0.076*sl 0.67 + 0.071*sl t phl 0.77 0.55 + 0.112*sl 0.57 + 0.101*sl 0.63 + 0.095*sl t r 0.18 0.13 + 0.023*sl 0.13 + 0.025*sl 0.11 + 0.027*sl t f 0.26 0.11 + 0.075*sl 0.10 + 0.076*sl 0.09 + 0.078*sl rd to zn t plh 0.26 0.22 + 0.020*sl 0.23 + 0.015*sl 0.26 + 0.012*sl t phl 0.15 0.03 + 0.057*sl 0.07 + 0.041*sl 0.09 + 0.039*sl t r 0.19 0.15 + 0.021*sl 0.14 + 0.024*sl 0.11 + 0.027*sl t f 0.33 0.19 + 0.070*sl 0.19 + 0.070*sl 0.12 + 0.078*sl t plz 0.22 0.22 + 0.000*sl 0.22 + 0.000*sl 0.22 + 0.000*sl t phz 0.36 0.36 + 0.001*sl 0.36 + 0.000*sl 0.36 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-387 STD80/stdm80 ld1b d latch with active high, tri-state output, separate wr, wrn switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld1b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to qn t plh 0.56 0.34 + 0.110*sl 0.34 + 0.109*sl 0.35 + 0.108*sl t phl 0.33 0.21 + 0.061*sl 0.21 + 0.060*sl 0.21 + 0.060*sl t r 1.22 0.58 + 0.318*sl 0.56 + 0.325*sl 0.55 + 0.327*sl t f 0.51 0.26 + 0.124*sl 0.24 + 0.130*sl 0.22 + 0.133*sl wr to qn t plh 0.42 0.22 + 0.102*sl 0.20 + 0.106*sl 0.20 + 0.107*sl t phl 0.27 0.16 + 0.058*sl 0.15 + 0.059*sl 0.15 + 0.059*sl t r 1.18 0.54 + 0.318*sl 0.51 + 0.327*sl 0.49 + 0.331*sl t f 0.51 0.27 + 0.123*sl 0.25 + 0.129*sl 0.22 + 0.133*sl wrn to qn t plh 0.42 0.22 + 0.102*sl 0.20 + 0.106*sl 0.20 + 0.107*sl t phl 0.27 0.16 + 0.058*sl 0.15 + 0.059*sl 0.15 + 0.059*sl t r 1.18 0.54 + 0.318*sl 0.51 + 0.327*sl 0.49 + 0.331*sl t f 0.51 0.27 + 0.123*sl 0.25 + 0.129*sl 0.22 + 0.133*sl d to zn t plh 1.26 0.99 + 0.139*sl 1.02 + 0.126*sl 1.08 + 0.118*sl t phl 1.13 0.84 + 0.144*sl 0.86 + 0.136*sl 0.89 + 0.133*sl t r 0.23 0.16 + 0.036*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t f 0.34 0.15 + 0.095*sl 0.15 + 0.097*sl 0.14 + 0.099*sl wr to zn t plh 1.13 0.86 + 0.130*sl 0.89 + 0.123*sl 0.93 + 0.117*sl t phl 1.07 0.79 + 0.141*sl 0.81 + 0.135*sl 0.83 + 0.132*sl t r 0.23 0.16 + 0.036*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t f 0.34 0.15 + 0.096*sl 0.15 + 0.097*sl 0.14 + 0.099*sl wrn to zn t plh 1.13 0.86 + 0.130*sl 0.89 + 0.123*sl 0.93 + 0.117*sl t phl 1.07 0.79 + 0.141*sl 0.81 + 0.135*sl 0.83 + 0.132*sl t r 0.23 0.16 + 0.036*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t f 0.34 0.15 + 0.096*sl 0.15 + 0.097*sl 0.14 + 0.099*sl rd to zn t plh 0.37 0.32 + 0.025*sl 0.33 + 0.021*sl 0.35 + 0.019*sl t phl 0.22 0.11 + 0.054*sl 0.13 + 0.049*sl 0.13 + 0.050*sl t r 0.24 0.16 + 0.037*sl 0.17 + 0.034*sl 0.16 + 0.035*sl t f 0.38 0.20 + 0.087*sl 0.19 + 0.093*sl 0.16 + 0.097*sl t plz 0.19 0.19 + 0.000*sl 0.19 + 0.000*sl 0.19 + 0.000*sl t phz 0.47 0.47 + 0.000*sl 0.46 + 0.000*sl 0.46 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-388 sec asic ld2/ld2d2 d latch with active high, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld2 ld2d2 ld2 ld2d2 d g rn d g rn 0.5 0.5 0.7 0.5 0.5 0.6 4.7 5.3 stdm80 ld2 ld2d2 ld2 ld2d2 d g rn d g rn 0.6 0.6 0.8 0.6 0.6 0.8 4.7 5.3 parameter symbol STD80 stdm80 ld2 ld2d2 ld2 ld2d2 pulse width high (g) t pwh 0.79 0.79 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to g) t su 0.55 0.76 0.71 0.76 input hold time (d to g) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to g) t hd 0.38 0.33 0.44 0.33 d g q qn rn g g gb d gb g gb q qn rn g truth table d g rn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx001
sec asic 3-389 STD80/stdm80 ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.57 0.51 + 0.032*sl 0.52 + 0.026*sl 0.54 + 0.024*sl t phl 0.64 0.56 + 0.041*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl g to q t plh 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.55 + 0.024*sl t phl 0.60 0.52 + 0.041*sl 0.53 + 0.038*sl 0.54 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.08 + 0.069*sl rn to q t plh 0.33 0.27 + 0.031*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.29 + 0.037*sl t r 0.23 0.14 + 0.045*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.066*sl 0.08 + 0.069*sl d to qn t plh 0.69 0.64 + 0.025*sl 0.64 + 0.024*sl 0.64 + 0.024*sl t phl 0.75 0.68 + 0.037*sl 0.68 + 0.037*sl 0.67 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl g to qn t plh 0.65 0.60 + 0.025*sl 0.60 + 0.024*sl 0.60 + 0.024*sl t phl 0.76 0.68 + 0.037*sl 0.68 + 0.037*sl 0.68 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.47 0.41 + 0.030*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.51 0.43 + 0.037*sl 0.43 + 0.037*sl 0.43 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.10 + 0.060*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-390 sec asic ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.59 0.54 + 0.021*sl 0.56 + 0.015*sl 0.59 + 0.012*sl t phl 0.64 0.59 + 0.023*sl 0.60 + 0.020*sl 0.61 + 0.018*sl t r 0.20 0.15 + 0.025*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.17 0.12 + 0.029*sl 0.11 + 0.031*sl 0.09 + 0.034*sl g to q t plh 0.60 0.55 + 0.021*sl 0.57 + 0.015*sl 0.60 + 0.012*sl t phl 0.60 0.55 + 0.023*sl 0.56 + 0.020*sl 0.57 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.11 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to q t plh 0.34 0.30 + 0.020*sl 0.31 + 0.015*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl d to qn t plh 0.75 0.72 + 0.014*sl 0.73 + 0.012*sl 0.73 + 0.012*sl t phl 0.83 0.80 + 0.017*sl 0.80 + 0.017*sl 0.79 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.030*sl 0.08 + 0.034*sl g to qn t plh 0.71 0.68 + 0.014*sl 0.69 + 0.012*sl 0.69 + 0.012*sl t phl 0.84 0.81 + 0.017*sl 0.81 + 0.017*sl 0.80 + 0.018*sl t r 0.15 0.11 + 0.019*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.53 0.50 + 0.018*sl 0.51 + 0.014*sl 0.53 + 0.012*sl t phl 0.59 0.55 + 0.018*sl 0.55 + 0.017*sl 0.54 + 0.018*sl t r 0.18 0.14 + 0.022*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-391 STD80/stdm80 ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.85 0.77 + 0.044*sl 0.79 + 0.038*sl 0.81 + 0.035*sl t phl 0.87 0.77 + 0.052*sl 0.79 + 0.046*sl 0.80 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl g to q t plh 0.86 0.77 + 0.044*sl 0.79 + 0.038*sl 0.81 + 0.034*sl t phl 0.86 0.76 + 0.052*sl 0.78 + 0.046*sl 0.79 + 0.044*sl t r 0.31 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.081*sl rn to q t plh 0.44 0.35 + 0.043*sl 0.37 + 0.037*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.071*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl d to qn t plh 0.95 0.88 + 0.035*sl 0.88 + 0.033*sl 0.88 + 0.033*sl t phl 1.09 1.00 + 0.047*sl 1.01 + 0.045*sl 1.01 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.078*sl 0.12 + 0.080*sl 0.11 + 0.082*sl g to qn t plh 0.94 0.87 + 0.035*sl 0.87 + 0.033*sl 0.87 + 0.033*sl t phl 1.10 1.00 + 0.047*sl 1.01 + 0.044*sl 1.01 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn t plh 0.63 0.54 + 0.042*sl 0.56 + 0.036*sl 0.58 + 0.033*sl t phl 0.67 0.58 + 0.047*sl 0.59 + 0.045*sl 0.59 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-392 sec asic ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.87 0.81 + 0.028*sl 0.83 + 0.022*sl 0.85 + 0.020*sl t phl 0.86 0.80 + 0.031*sl 0.81 + 0.026*sl 0.83 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl g to q t plh 0.87 0.82 + 0.028*sl 0.83 + 0.023*sl 0.85 + 0.019*sl t phl 0.85 0.79 + 0.031*sl 0.81 + 0.026*sl 0.83 + 0.023*sl t r 0.25 0.17 + 0.038*sl 0.18 + 0.034*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl rn to q t plh 0.44 0.39 + 0.027*sl 0.40 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.14 + 0.039*sl 0.14 + 0.039*sl 0.14 + 0.038*sl d to qn t plh 1.04 1.00 + 0.019*sl 1.00 + 0.017*sl 1.01 + 0.017*sl t phl 1.20 1.15 + 0.024*sl 1.16 + 0.022*sl 1.16 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.22 0.13 + 0.041*sl 0.15 + 0.037*sl 0.14 + 0.038*sl g to qn t plh 1.03 0.99 + 0.019*sl 0.99 + 0.017*sl 1.00 + 0.017*sl t phl 1.21 1.16 + 0.024*sl 1.16 + 0.022*sl 1.17 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.22 0.13 + 0.042*sl 0.15 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.71 0.66 + 0.023*sl 0.67 + 0.020*sl 0.68 + 0.018*sl t phl 0.78 0.73 + 0.025*sl 0.73 + 0.022*sl 0.74 + 0.021*sl t r 0.23 0.16 + 0.036*sl 0.17 + 0.033*sl 0.17 + 0.033*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-393 STD80/stdm80 ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld2q ld2qd2 ld2q ld2qd2 d g rn d g rn 0.6 0.6 0.5 0.6 0.6 0.8 4.3 4.7 stdm80 ld2q ld2qd2 ld2q ld2qd2 d g rn d g rn 0.6 0.6 0.6 0.6 0.6 0.6 4.3 4.7 parameter symbol STD80 stdm80 ld2q ld2qd2 ld2q ld2qd2 pulse width high (g) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to g) t su 0.55 0.57 0.71 0.74 input hold time (d to g) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.33 input hold time (rn to g) t hd 0.38 0.38 0.44 0.38 d g q rn g g gb d gb g gb q rn g truth table d g rn q (n+1) 0110 1111 x 0 1 q (n) xx00
STD80/stdm80 3-394 sec asic ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld2q STD80 ld2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.50 + 0.032*sl 0.51 + 0.026*sl 0.53 + 0.024*sl t phl 0.64 0.56 + 0.041*sl 0.56 + 0.037*sl 0.57 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.066*sl 0.07 + 0.069*sl g to q t plh 0.57 0.51 + 0.031*sl 0.52 + 0.026*sl 0.54 + 0.024*sl t phl 0.60 0.52 + 0.040*sl 0.52 + 0.037*sl 0.53 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to q t plh 0.32 0.26 + 0.031*sl 0.27 + 0.026*sl 0.29 + 0.024*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.037*sl 0.28 + 0.037*sl t r 0.23 0.13 + 0.046*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.066*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.58 0.54 + 0.021*sl 0.55 + 0.015*sl 0.58 + 0.012*sl t phl 0.63 0.58 + 0.023*sl 0.59 + 0.020*sl 0.61 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl g to q t plh 0.59 0.55 + 0.020*sl 0.56 + 0.016*sl 0.59 + 0.012*sl t phl 0.59 0.54 + 0.023*sl 0.55 + 0.020*sl 0.56 + 0.018*sl t r 0.19 0.14 + 0.026*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.12 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl rn to q t plh 0.33 0.30 + 0.019*sl 0.30 + 0.016*sl 0.34 + 0.012*sl t phl 0.35 0.31 + 0.022*sl 0.31 + 0.019*sl 0.32 + 0.018*sl t r 0.19 0.15 + 0.021*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.030*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-395 STD80/stdm80 ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld2q stdm80 ld2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.84 0.76 + 0.043*sl 0.78 + 0.037*sl 0.80 + 0.034*sl t phl 0.86 0.76 + 0.051*sl 0.78 + 0.046*sl 0.78 + 0.044*sl t r 0.31 0.17 + 0.069*sl 0.18 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.082*sl g to q t plh 0.85 0.76 + 0.043*sl 0.78 + 0.037*sl 0.80 + 0.034*sl t phl 0.85 0.75 + 0.051*sl 0.77 + 0.046*sl 0.78 + 0.044*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.068*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.079*sl 0.14 + 0.079*sl 0.13 + 0.082*sl rn to q t plh 0.43 0.34 + 0.042*sl 0.36 + 0.037*sl 0.38 + 0.034*sl t phl 0.46 0.36 + 0.051*sl 0.37 + 0.046*sl 0.38 + 0.044*sl t r 0.30 0.16 + 0.070*sl 0.16 + 0.069*sl 0.15 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.079*sl 0.12 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.86 0.80 + 0.028*sl 0.82 + 0.023*sl 0.84 + 0.019*sl t phl 0.85 0.79 + 0.031*sl 0.81 + 0.026*sl 0.83 + 0.023*sl t r 0.25 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.14 + 0.038*sl g to q t plh 0.86 0.81 + 0.028*sl 0.82 + 0.022*sl 0.84 + 0.020*sl t phl 0.84 0.78 + 0.031*sl 0.80 + 0.026*sl 0.82 + 0.023*sl t r 0.24 0.17 + 0.037*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.14 + 0.038*sl rn to q t plh 0.44 0.38 + 0.027*sl 0.40 + 0.022*sl 0.42 + 0.019*sl t phl 0.45 0.39 + 0.030*sl 0.40 + 0.025*sl 0.42 + 0.023*sl t r 0.24 0.16 + 0.037*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.038*sl 0.14 + 0.038*sl 0.14 + 0.037*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-396 sec asic yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 yld2 yld2d2 yld2 yld2d2 dgrndgrn 2.2 0.5 0.7 3.3 0.5 1.4 3.0 3.7 stdm80 yld2 yld2d2 yld2 yld2d2 dgrndgrn 2.5 0.6 0.8 3.6 0.6 1.6 3.0 3.7 parameter symbol STD80 stdm80 yld2 yld2d2 yld2 yld2d2 pulse width high (g) t pwh 0.87 0.87 0.82 0.82 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to g) t su 0.74 0.74 0.46 0.46 input hold time (d to g) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.36 0.33 0.33 0.33 input hold time (rn to g) t hd 0.38 0.44 0.33 0.49 d g q qn rn g g gb d gb g gb qn q rn g truth table d g rn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx001
sec asic 3-397 STD80/stdm80 yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 yld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.41 0.25 + 0.080*sl 0.26 + 0.077*sl 0.25 + 0.078*sl t phl 0.43 0.28 + 0.076*sl 0.29 + 0.073*sl 0.28 + 0.073*sl t r 0.24 0.11 + 0.064*sl 0.11 + 0.067*sl 0.10 + 0.068*sl t f 0.24 0.10 + 0.074*sl 0.09 + 0.076*sl 0.09 + 0.077*sl g to q t plh 0.58 0.42 + 0.080*sl 0.43 + 0.079*sl 0.43 + 0.078*sl t phl 0.57 0.43 + 0.074*sl 0.43 + 0.073*sl 0.43 + 0.073*sl t r 0.24 0.10 + 0.066*sl 0.10 + 0.068*sl 0.10 + 0.068*sl t f 0.24 0.09 + 0.076*sl 0.09 + 0.077*sl 0.08 + 0.077*sl rn to q t plh 0.37 0.21 + 0.078*sl 0.21 + 0.078*sl 0.21 + 0.078*sl t phl 0.42 0.25 + 0.083*sl 0.27 + 0.075*sl 0.29 + 0.073*sl t r 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.10 + 0.068*sl t f 0.38 0.24 + 0.070*sl 0.23 + 0.074*sl 0.22 + 0.076*sl d to qn t plh 0.26 0.20 + 0.027*sl 0.21 + 0.024*sl 0.20 + 0.025*sl t phl 0.28 0.20 + 0.039*sl 0.20 + 0.038*sl 0.19 + 0.038*sl t r 0.33 0.25 + 0.040*sl 0.23 + 0.048*sl 0.17 + 0.054*sl t f 0.41 0.28 + 0.063*sl 0.27 + 0.070*sl 0.19 + 0.078*sl g to qn t plh 0.40 0.35 + 0.025*sl 0.35 + 0.025*sl 0.35 + 0.025*sl t phl 0.45 0.37 + 0.040*sl 0.37 + 0.039*sl 0.37 + 0.039*sl t r 0.26 0.17 + 0.047*sl 0.16 + 0.052*sl 0.14 + 0.054*sl t f 0.35 0.21 + 0.071*sl 0.20 + 0.075*sl 0.17 + 0.078*sl rn to qn t plh 0.19 0.13 + 0.032*sl 0.14 + 0.025*sl 0.15 + 0.025*sl t phl 0.24 0.16 + 0.040*sl 0.16 + 0.038*sl 0.16 + 0.038*sl t r 0.32 0.24 + 0.040*sl 0.23 + 0.047*sl 0.17 + 0.053*sl t f 0.40 0.27 + 0.067*sl 0.26 + 0.070*sl 0.19 + 0.078*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-398 sec asic yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 yld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.38 0.27 + 0.055*sl 0.27 + 0.052*sl 0.27 + 0.052*sl t phl 0.41 0.30 + 0.059*sl 0.30 + 0.056*sl 0.31 + 0.055*sl t r 0.22 0.11 + 0.055*sl 0.10 + 0.056*sl 0.09 + 0.058*sl t f 0.23 0.09 + 0.069*sl 0.09 + 0.071*sl 0.08 + 0.071*sl g to q t plh 0.56 0.45 + 0.054*sl 0.46 + 0.053*sl 0.46 + 0.052*sl t phl 0.56 0.45 + 0.057*sl 0.45 + 0.056*sl 0.45 + 0.055*sl t r 0.21 0.10 + 0.054*sl 0.09 + 0.057*sl 0.09 + 0.058*sl t f 0.22 0.08 + 0.070*sl 0.08 + 0.071*sl 0.08 + 0.071*sl rn to q t plh 0.29 0.18 + 0.057*sl 0.19 + 0.052*sl 0.19 + 0.052*sl t phl 0.37 0.23 + 0.070*sl 0.25 + 0.061*sl 0.30 + 0.055*sl t r 0.21 0.10 + 0.054*sl 0.09 + 0.057*sl 0.09 + 0.058*sl t f 0.46 0.33 + 0.065*sl 0.32 + 0.069*sl 0.30 + 0.071*sl d to qn t plh 0.25 0.22 + 0.015*sl 0.22 + 0.013*sl 0.23 + 0.012*sl t phl 0.26 0.21 + 0.022*sl 0.22 + 0.019*sl 0.22 + 0.019*sl t r 0.26 0.23 + 0.018*sl 0.22 + 0.022*sl 0.17 + 0.027*sl t f 0.31 0.25 + 0.026*sl 0.24 + 0.032*sl 0.18 + 0.038*sl g to qn t plh 0.40 0.37 + 0.015*sl 0.37 + 0.013*sl 0.38 + 0.012*sl t phl 0.44 0.40 + 0.021*sl 0.40 + 0.020*sl 0.41 + 0.019*sl t r 0.21 0.17 + 0.021*sl 0.16 + 0.024*sl 0.13 + 0.027*sl t f 0.25 0.18 + 0.032*sl 0.17 + 0.036*sl 0.14 + 0.039*sl rn to qn t plh 0.14 0.10 + 0.020*sl 0.11 + 0.015*sl 0.14 + 0.012*sl t phl 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.14 + 0.019*sl t r 0.26 0.21 + 0.022*sl 0.21 + 0.022*sl 0.16 + 0.027*sl t f 0.28 0.23 + 0.029*sl 0.22 + 0.033*sl 0.16 + 0.039*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-399 STD80/stdm80 yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 yld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.59 0.37 + 0.110*sl 0.37 + 0.109*sl 0.38 + 0.108*sl t phl 0.58 0.39 + 0.099*sl 0.39 + 0.098*sl 0.39 + 0.098*sl t r 0.33 0.15 + 0.090*sl 0.14 + 0.091*sl 0.14 + 0.092*sl t f 0.31 0.12 + 0.095*sl 0.12 + 0.095*sl 0.12 + 0.095*sl g to q t plh 0.84 0.62 + 0.110*sl 0.62 + 0.109*sl 0.63 + 0.108*sl t phl 0.82 0.62 + 0.099*sl 0.62 + 0.099*sl 0.62 + 0.098*sl t r 0.32 0.14 + 0.091*sl 0.14 + 0.092*sl 0.14 + 0.091*sl t f 0.31 0.12 + 0.095*sl 0.12 + 0.095*sl 0.11 + 0.096*sl rn to q t plh 0.49 0.27 + 0.109*sl 0.27 + 0.108*sl 0.28 + 0.108*sl t phl 0.53 0.32 + 0.105*sl 0.33 + 0.101*sl 0.34 + 0.100*sl t r 0.32 0.14 + 0.091*sl 0.14 + 0.092*sl 0.14 + 0.092*sl t f 0.49 0.31 + 0.089*sl 0.30 + 0.093*sl 0.29 + 0.094*sl d to qn t plh 0.35 0.28 + 0.035*sl 0.28 + 0.035*sl 0.28 + 0.035*sl t phl 0.38 0.28 + 0.052*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t r 0.38 0.24 + 0.068*sl 0.23 + 0.073*sl 0.21 + 0.075*sl t f 0.48 0.31 + 0.085*sl 0.29 + 0.094*sl 0.26 + 0.097*sl g to qn t plh 0.58 0.51 + 0.035*sl 0.51 + 0.035*sl 0.51 + 0.035*sl t phl 0.63 0.53 + 0.052*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.37 0.23 + 0.070*sl 0.22 + 0.074*sl 0.20 + 0.075*sl t f 0.46 0.28 + 0.090*sl 0.26 + 0.096*sl 0.24 + 0.098*sl rn to qn t plh 0.24 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.29 0.19 + 0.050*sl 0.19 + 0.050*sl 0.19 + 0.050*sl t r 0.37 0.24 + 0.066*sl 0.22 + 0.071*sl 0.21 + 0.073*sl t f 0.46 0.28 + 0.088*sl 0.26 + 0.094*sl 0.24 + 0.098*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-400 sec asic yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 yld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.55 0.39 + 0.077*sl 0.40 + 0.074*sl 0.41 + 0.073*sl t phl 0.56 0.41 + 0.075*sl 0.41 + 0.072*sl 0.42 + 0.072*sl t r 0.29 0.13 + 0.079*sl 0.13 + 0.079*sl 0.13 + 0.079*sl t f 0.29 0.11 + 0.086*sl 0.11 + 0.087*sl 0.11 + 0.087*sl g to q t plh 0.83 0.67 + 0.077*sl 0.68 + 0.074*sl 0.69 + 0.073*sl t phl 0.79 0.64 + 0.075*sl 0.65 + 0.072*sl 0.66 + 0.072*sl t r 0.29 0.13 + 0.079*sl 0.13 + 0.079*sl 0.13 + 0.079*sl t f 0.29 0.11 + 0.087*sl 0.11 + 0.087*sl 0.11 + 0.087*sl rn to q t plh 0.39 0.24 + 0.075*sl 0.24 + 0.073*sl 0.25 + 0.072*sl t phl 0.45 0.29 + 0.083*sl 0.31 + 0.077*sl 0.32 + 0.075*sl t r 0.29 0.13 + 0.078*sl 0.12 + 0.080*sl 0.12 + 0.080*sl t f 0.58 0.43 + 0.079*sl 0.41 + 0.083*sl 0.40 + 0.085*sl d to qn t plh 0.34 0.30 + 0.019*sl 0.31 + 0.018*sl 0.31 + 0.017*sl t phl 0.36 0.31 + 0.029*sl 0.31 + 0.027*sl 0.32 + 0.025*sl t r 0.28 0.22 + 0.032*sl 0.21 + 0.034*sl 0.20 + 0.036*sl t f 0.35 0.27 + 0.041*sl 0.26 + 0.044*sl 0.24 + 0.047*sl g to qn t plh 0.58 0.54 + 0.020*sl 0.54 + 0.018*sl 0.55 + 0.018*sl t phl 0.65 0.59 + 0.029*sl 0.59 + 0.027*sl 0.60 + 0.026*sl t r 0.27 0.21 + 0.033*sl 0.20 + 0.035*sl 0.19 + 0.036*sl t f 0.33 0.24 + 0.043*sl 0.23 + 0.046*sl 0.22 + 0.048*sl rn to qn t plh 0.18 0.14 + 0.022*sl 0.15 + 0.018*sl 0.16 + 0.017*sl t phl 0.21 0.16 + 0.028*sl 0.17 + 0.025*sl 0.17 + 0.025*sl t r 0.27 0.21 + 0.030*sl 0.20 + 0.033*sl 0.18 + 0.035*sl t f 0.30 0.22 + 0.041*sl 0.21 + 0.046*sl 0.20 + 0.047*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-401 STD80/stdm80 ld3/ld3d2 d latch with active high, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld3 ld3d2 ld3 ld3d2 d g sn d g sn 0.6 0.6 0.8 0.6 0.6 0.5 4.3 5.0 stdm80 ld3 ld3d2 ld3 ld3d2 d g sn d g sn 0.6 0.6 0.6 0.6 0.6 0.6 4.3 5.0 parameter symbol STD80 stdm80 ld3 ld3d2 ld3 ld3d2 pulse width high (g) t pwh 0.87 0.87 0.82 0.82 pulse width low (sn) t pwl 0.87 0.87 0.82 0.85 input setup time (d to g) t su 0.57 0.63 0.68 0.74 input hold time (d to g) t hd 0.33 0.33 0.33 0.33 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to g) t hd 0.38 0.33 0.38 0.33 d g q qn sn g g gb d gb g gb qn q sn g truth table d g sn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx010
STD80/stdm80 3-402 sec asic ld3/ld3d2 d latch with active high, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.53 0.48 + 0.025*sl 0.48 + 0.024*sl 0.48 + 0.024*sl t phl 0.76 0.68 + 0.037*sl 0.68 + 0.037*sl 0.68 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl g to q t plh 0.64 0.59 + 0.025*sl 0.59 + 0.024*sl 0.59 + 0.024*sl t phl 0.75 0.68 + 0.037*sl 0.68 + 0.037*sl 0.68 + 0.037*sl t r 0.19 0.09 + 0.048*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl sn to q t plh 0.47 0.41 + 0.030*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.51 0.43 + 0.037*sl 0.43 + 0.037*sl 0.43 + 0.037*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.10 + 0.060*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d to qn t plh 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.55 + 0.024*sl t phl 0.49 0.40 + 0.042*sl 0.41 + 0.038*sl 0.42 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.08 + 0.069*sl g to qn t plh 0.58 0.51 + 0.032*sl 0.53 + 0.026*sl 0.55 + 0.024*sl t phl 0.60 0.52 + 0.042*sl 0.53 + 0.038*sl 0.53 + 0.037*sl t r 0.23 0.13 + 0.049*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.08 + 0.069*sl sn to qn t plh 0.33 0.27 + 0.031*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.29 + 0.037*sl t r 0.23 0.14 + 0.045*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-403 STD80/stdm80 ld3/ld3d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.59 0.56 + 0.014*sl 0.57 + 0.012*sl 0.57 + 0.012*sl t phl 0.84 0.80 + 0.018*sl 0.80 + 0.017*sl 0.79 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.030*sl 0.08 + 0.034*sl g to q t plh 0.71 0.68 + 0.014*sl 0.68 + 0.012*sl 0.69 + 0.012*sl t phl 0.84 0.80 + 0.018*sl 0.80 + 0.017*sl 0.79 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.030*sl 0.08 + 0.034*sl sn to q t plh 0.53 0.50 + 0.018*sl 0.51 + 0.014*sl 0.53 + 0.012*sl t phl 0.59 0.55 + 0.018*sl 0.55 + 0.017*sl 0.54 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl d to qn t plh 0.59 0.55 + 0.021*sl 0.56 + 0.015*sl 0.59 + 0.012*sl t phl 0.48 0.43 + 0.023*sl 0.44 + 0.020*sl 0.46 + 0.018*sl t r 0.20 0.15 + 0.025*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.11 + 0.032*sl 0.12 + 0.031*sl 0.09 + 0.034*sl g to qn t plh 0.59 0.55 + 0.021*sl 0.56 + 0.015*sl 0.59 + 0.012*sl t phl 0.59 0.54 + 0.023*sl 0.55 + 0.020*sl 0.57 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.11 + 0.031*sl 0.09 + 0.034*sl sn to qn t plh 0.34 0.30 + 0.020*sl 0.31 + 0.015*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-404 sec asic ld3/ld3d2 d latch with active high, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.75 0.68 + 0.035*sl 0.69 + 0.033*sl 0.69 + 0.033*sl t phl 1.04 0.95 + 0.047*sl 0.96 + 0.045*sl 0.96 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.14 + 0.076*sl 0.12 + 0.080*sl 0.11 + 0.082*sl g to q t plh 0.93 0.86 + 0.035*sl 0.87 + 0.033*sl 0.87 + 0.033*sl t phl 1.09 1.00 + 0.047*sl 1.00 + 0.045*sl 1.01 + 0.044*sl t r 0.26 0.13 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl sn to q t plh 0.63 0.54 + 0.042*sl 0.56 + 0.036*sl 0.58 + 0.033*sl t phl 0.67 0.58 + 0.047*sl 0.59 + 0.045*sl 0.59 + 0.044*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl d to qn t plh 0.81 0.72 + 0.044*sl 0.74 + 0.038*sl 0.76 + 0.035*sl t phl 0.68 0.57 + 0.052*sl 0.59 + 0.046*sl 0.60 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.082*sl g to qn t plh 0.85 0.77 + 0.043*sl 0.78 + 0.038*sl 0.81 + 0.035*sl t phl 0.86 0.76 + 0.052*sl 0.77 + 0.046*sl 0.79 + 0.044*sl t r 0.31 0.17 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.15 + 0.079*sl 0.14 + 0.080*sl 0.13 + 0.081*sl sn to qn t plh 0.44 0.35 + 0.043*sl 0.37 + 0.037*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.071*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-405 STD80/stdm80 ld3/ld3d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.84 0.80 + 0.019*sl 0.81 + 0.017*sl 0.81 + 0.017*sl t phl 1.16 1.11 + 0.024*sl 1.11 + 0.022*sl 1.12 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.22 0.14 + 0.039*sl 0.14 + 0.038*sl 0.14 + 0.038*sl g to q t plh 1.02 0.99 + 0.018*sl 0.99 + 0.018*sl 0.99 + 0.017*sl t phl 1.20 1.15 + 0.024*sl 1.16 + 0.022*sl 1.16 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.22 0.14 + 0.039*sl 0.14 + 0.037*sl 0.14 + 0.038*sl sn to q t plh 0.71 0.66 + 0.023*sl 0.67 + 0.020*sl 0.68 + 0.018*sl t phl 0.78 0.73 + 0.025*sl 0.73 + 0.022*sl 0.74 + 0.021*sl t r 0.23 0.16 + 0.036*sl 0.17 + 0.033*sl 0.17 + 0.033*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl d to qn t plh 0.82 0.76 + 0.028*sl 0.78 + 0.023*sl 0.80 + 0.019*sl t phl 0.67 0.60 + 0.031*sl 0.62 + 0.026*sl 0.64 + 0.023*sl t r 0.25 0.18 + 0.035*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.039*sl 0.15 + 0.038*sl g to qn t plh 0.87 0.81 + 0.028*sl 0.83 + 0.023*sl 0.85 + 0.019*sl t phl 0.85 0.79 + 0.031*sl 0.80 + 0.026*sl 0.82 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.034*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.039*sl 0.15 + 0.038*sl sn to qn t plh 0.44 0.39 + 0.027*sl 0.40 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.042*sl 0.14 + 0.038*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-406 sec asic ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld4 ld4d2 ld4 ld4d2 d g sn rn d g sn rn 0.6 0.6 0.8 0.6 0.6 0.6 0.8 0.4 6.0 6.7 stdm80 ld4 ld4d2 ld4 ld4d2 d g sn rn d g sn rn 0.6 0.6 0.8 0.6 0.6 0.6 0.8 0.6 6.0 6.7 parameter symbol STD80 stdm80 ld4 ld4d2 ld4 ld4d2 pulse width high (g) t pwh 0.87 0.87 0.82 0.85 pulse width low (rn) t pwl 0.87 0.87 0.90 1.01 pulse width low (sn) t pwl 0.87 0.87 0.82 0.87 input setup time (d to g) t su 0.63 0.71 0.74 0.87 input hold time (d to g) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.33 0.33 0.36 input hold time (rn to g) t hd 0.38 0.33 0.38 0.33 recovery time (sn) t rc 0.33 0.33 0.33 0.33 input hold time (sn to g) t hd 0.44 0.33 0.49 0.38 d g q qn sn rn g g gb d gb g gb qn q g sn rn rn rn sn sn truth table d g rn sn q (n+1) qn (n+1) 011101 111110 x 0 1 1 q (n) qn (n) xx1010 xx0101 xx0010
sec asic 3-407 STD80/stdm80 ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.74 0.69 + 0.028*sl 0.69 + 0.024*sl 0.70 + 0.024*sl t phl 0.96 0.89 + 0.038*sl 0.89 + 0.037*sl 0.89 + 0.037*sl t r 0.19 0.11 + 0.043*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl g to q t plh 0.75 0.70 + 0.028*sl 0.70 + 0.024*sl 0.71 + 0.024*sl t phl 0.92 0.84 + 0.039*sl 0.85 + 0.037*sl 0.85 + 0.037*sl t r 0.19 0.11 + 0.044*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.060*sl 0.10 + 0.066*sl 0.07 + 0.069*sl sn to q t plh 0.45 0.39 + 0.028*sl 0.40 + 0.024*sl 0.40 + 0.024*sl t phl 0.52 0.44 + 0.038*sl 0.44 + 0.037*sl 0.44 + 0.037*sl t r 0.19 0.11 + 0.044*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to q t plh 0.50 0.45 + 0.028*sl 0.45 + 0.024*sl 0.46 + 0.024*sl t phl 0.68 0.61 + 0.039*sl 0.61 + 0.037*sl 0.61 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.066*sl 0.07 + 0.069*sl d to qn t plh 0.75 0.69 + 0.031*sl 0.70 + 0.026*sl 0.72 + 0.024*sl t phl 0.67 0.59 + 0.040*sl 0.60 + 0.038*sl 0.60 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.12 + 0.049*sl 0.10 + 0.052*sl t f 0.23 0.10 + 0.066*sl 0.10 + 0.067*sl 0.08 + 0.069*sl g to qn t plh 0.71 0.65 + 0.030*sl 0.66 + 0.026*sl 0.68 + 0.024*sl t phl 0.68 0.60 + 0.040*sl 0.61 + 0.038*sl 0.61 + 0.037*sl t r 0.22 0.12 + 0.048*sl 0.12 + 0.049*sl 0.10 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.07 + 0.069*sl sn to qn t plh 0.31 0.25 + 0.030*sl 0.26 + 0.026*sl 0.28 + 0.024*sl t phl 0.38 0.30 + 0.039*sl 0.30 + 0.038*sl 0.31 + 0.037*sl t r 0.23 0.13 + 0.046*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.067*sl 0.08 + 0.069*sl rn to qn t plh 0.48 0.41 + 0.031*sl 0.43 + 0.026*sl 0.45 + 0.024*sl t phl 0.43 0.35 + 0.040*sl 0.36 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.12 + 0.049*sl 0.10 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-408 sec asic ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.81 0.78 + 0.014*sl 0.78 + 0.013*sl 0.79 + 0.012*sl t phl 1.04 1.00 + 0.019*sl 1.01 + 0.017*sl 1.00 + 0.018*sl t r 0.16 0.11 + 0.023*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.030*sl 0.09 + 0.034*sl g to q t plh 0.82 0.79 + 0.015*sl 0.79 + 0.013*sl 0.80 + 0.012*sl t phl 1.00 0.97 + 0.019*sl 0.97 + 0.017*sl 0.96 + 0.018*sl t r 0.16 0.11 + 0.023*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.12 + 0.030*sl 0.09 + 0.034*sl sn to q t plh 0.51 0.48 + 0.015*sl 0.49 + 0.013*sl 0.50 + 0.012*sl t phl 0.60 0.56 + 0.019*sl 0.56 + 0.017*sl 0.56 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.032*sl 0.12 + 0.030*sl 0.09 + 0.034*sl rn to q t plh 0.57 0.54 + 0.015*sl 0.54 + 0.013*sl 0.55 + 0.012*sl t phl 0.77 0.73 + 0.019*sl 0.73 + 0.017*sl 0.73 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl d to qn t plh 0.77 0.72 + 0.021*sl 0.74 + 0.015*sl 0.77 + 0.012*sl t phl 0.67 0.62 + 0.023*sl 0.63 + 0.020*sl 0.64 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl g to qn t plh 0.73 0.68 + 0.021*sl 0.70 + 0.015*sl 0.73 + 0.012*sl t phl 0.68 0.63 + 0.023*sl 0.64 + 0.020*sl 0.65 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sn to qn t plh 0.32 0.28 + 0.020*sl 0.29 + 0.015*sl 0.32 + 0.012*sl t phl 0.37 0.33 + 0.023*sl 0.33 + 0.020*sl 0.35 + 0.018*sl t r 0.19 0.15 + 0.022*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to qn t plh 0.49 0.45 + 0.021*sl 0.46 + 0.015*sl 0.49 + 0.012*sl t phl 0.43 0.38 + 0.023*sl 0.39 + 0.020*sl 0.40 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-409 STD80/stdm80 ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.10 1.03 + 0.037*sl 1.04 + 0.034*sl 1.04 + 0.033*sl t phl 1.33 1.24 + 0.049*sl 1.25 + 0.045*sl 1.25 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.30 0.15 + 0.077*sl 0.14 + 0.079*sl 0.13 + 0.081*sl g to q t plh 1.10 1.03 + 0.037*sl 1.04 + 0.034*sl 1.04 + 0.033*sl t phl 1.32 1.23 + 0.049*sl 1.24 + 0.045*sl 1.25 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.081*sl sn to q t plh 0.60 0.53 + 0.037*sl 0.54 + 0.034*sl 0.54 + 0.034*sl t phl 0.71 0.61 + 0.049*sl 0.62 + 0.045*sl 0.63 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.071*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.081*sl rn to q t plh 0.71 0.63 + 0.037*sl 0.64 + 0.034*sl 0.65 + 0.033*sl t phl 0.93 0.83 + 0.049*sl 0.84 + 0.046*sl 0.85 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.079*sl 0.13 + 0.081*sl d to qn t plh 1.05 0.96 + 0.042*sl 0.98 + 0.037*sl 0.99 + 0.035*sl t phl 0.99 0.89 + 0.051*sl 0.90 + 0.046*sl 0.91 + 0.044*sl t r 0.30 0.17 + 0.069*sl 0.17 + 0.070*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl g to qn t plh 1.04 0.95 + 0.042*sl 0.97 + 0.037*sl 0.99 + 0.034*sl t phl 0.99 0.89 + 0.051*sl 0.90 + 0.046*sl 0.91 + 0.044*sl t r 0.30 0.16 + 0.070*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl sn to qn t plh 0.43 0.34 + 0.042*sl 0.36 + 0.037*sl 0.37 + 0.035*sl t phl 0.49 0.39 + 0.051*sl 0.40 + 0.046*sl 0.41 + 0.045*sl t r 0.30 0.16 + 0.070*sl 0.16 + 0.070*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.082*sl 0.13 + 0.082*sl rn to qn t plh 0.65 0.56 + 0.042*sl 0.58 + 0.037*sl 0.59 + 0.034*sl t phl 0.60 0.50 + 0.051*sl 0.51 + 0.047*sl 0.52 + 0.044*sl t r 0.30 0.16 + 0.070*sl 0.17 + 0.070*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-410 sec asic ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.19 1.15 + 0.020*sl 1.16 + 0.018*sl 1.16 + 0.017*sl t phl 1.44 1.39 + 0.027*sl 1.40 + 0.023*sl 1.41 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.037*sl 0.16 + 0.037*sl g to q t plh 1.19 1.15 + 0.020*sl 1.16 + 0.018*sl 1.16 + 0.017*sl t phl 1.43 1.38 + 0.027*sl 1.39 + 0.023*sl 1.40 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.037*sl 0.16 + 0.037*sl sn to q t plh 0.69 0.65 + 0.020*sl 0.65 + 0.018*sl 0.66 + 0.017*sl t phl 0.82 0.76 + 0.027*sl 0.77 + 0.023*sl 0.78 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.038*sl 0.16 + 0.037*sl rn to q t plh 0.80 0.76 + 0.020*sl 0.77 + 0.018*sl 0.77 + 0.017*sl t phl 1.04 0.98 + 0.027*sl 0.99 + 0.023*sl 1.00 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.15 + 0.039*sl 0.16 + 0.037*sl d to qn t plh 1.06 1.01 + 0.027*sl 1.03 + 0.022*sl 1.04 + 0.019*sl t phl 0.98 0.92 + 0.031*sl 0.94 + 0.026*sl 0.95 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl g to qn t plh 1.06 1.00 + 0.027*sl 1.02 + 0.022*sl 1.03 + 0.019*sl t phl 0.98 0.92 + 0.031*sl 0.94 + 0.026*sl 0.95 + 0.023*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.039*sl sn to qn t plh 0.44 0.38 + 0.027*sl 0.40 + 0.022*sl 0.42 + 0.019*sl t phl 0.48 0.42 + 0.031*sl 0.43 + 0.026*sl 0.45 + 0.023*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.14 + 0.038*sl rn to qn t plh 0.66 0.61 + 0.027*sl 0.62 + 0.022*sl 0.64 + 0.019*sl t phl 0.59 0.53 + 0.031*sl 0.55 + 0.026*sl 0.56 + 0.023*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.22 0.14 + 0.039*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-411 STD80/stdm80 ld5/ld5d2 d latch with active low, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld5 ld5d2 ld5 ld5d2 dgndgn 0.5 0.5 0.6 0.6 4.0 4.7 stdm80 ld5 ld5d2 ld5 ld5d2 dgndgn 0.6 0.6 0.6 0.6 4.0 4.7 parameter symbol STD80 stdm80 ld5 ld5d2 ld5 ld5d2 pulse width low (gn) t pwl 0.87 0.87 0.85 0.90 input setup time (d to gn) t su 0.66 0.71 0.66 0.71 input hold time (d to gn) t hd 0.33 0.33 0.33 0.33 d gn q qn qn q d gnb gn gn gnb gn gn gnb truth table d gn q (n+1) qn (n+1) 0001 1010 x 1 q (n) qn (n)
STD80/stdm80 3-412 sec asic ld5/ld5d2 d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld5 STD80 ld5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.62 + 0.038*sl 0.62 + 0.037*sl 0.62 + 0.037*sl t r 0.19 0.09 + 0.045*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl gn to q t plh 0.67 0.62 + 0.026*sl 0.63 + 0.024*sl 0.63 + 0.024*sl t phl 0.81 0.74 + 0.038*sl 0.74 + 0.037*sl 0.74 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d to qn t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.041*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl gn to qn t plh 0.65 0.59 + 0.028*sl 0.60 + 0.024*sl 0.60 + 0.024*sl t phl 0.64 0.55 + 0.042*sl 0.56 + 0.038*sl 0.57 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.57 0.55 + 0.013*sl 0.55 + 0.012*sl 0.55 + 0.012*sl t phl 0.75 0.72 + 0.018*sl 0.72 + 0.018*sl 0.71 + 0.018*sl t r 0.15 0.11 + 0.019*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl gn to q t plh 0.74 0.71 + 0.014*sl 0.71 + 0.012*sl 0.72 + 0.012*sl t phl 0.87 0.83 + 0.018*sl 0.83 + 0.018*sl 0.83 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d to qn t plh 0.53 0.50 + 0.018*sl 0.51 + 0.014*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl gn to qn t plh 0.65 0.62 + 0.018*sl 0.63 + 0.013*sl 0.64 + 0.012*sl t phl 0.62 0.58 + 0.023*sl 0.58 + 0.020*sl 0.60 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.029*sl 0.10 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-413 STD80/stdm80 ld5/ld5d2 d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld5 stdm80 ld5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.72 0.65 + 0.035*sl 0.65 + 0.033*sl 0.65 + 0.033*sl t phl 0.96 0.87 + 0.047*sl 0.88 + 0.044*sl 0.88 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl gn to q t plh 0.93 0.86 + 0.035*sl 0.87 + 0.033*sl 0.87 + 0.033*sl t phl 1.14 1.05 + 0.046*sl 1.06 + 0.045*sl 1.06 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d to qn t plh 0.74 0.66 + 0.039*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl gn to qn t plh 0.92 0.84 + 0.038*sl 0.85 + 0.035*sl 0.86 + 0.034*sl t phl 0.86 0.76 + 0.051*sl 0.77 + 0.046*sl 0.79 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.81 0.77 + 0.019*sl 0.77 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.00 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl gn to q t plh 1.02 0.98 + 0.018*sl 0.99 + 0.017*sl 0.99 + 0.017*sl t phl 1.22 1.17 + 0.026*sl 1.18 + 0.023*sl 1.19 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d to qn t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.64 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl gn to qn t plh 0.92 0.87 + 0.024*sl 0.88 + 0.020*sl 0.90 + 0.018*sl t phl 0.85 0.79 + 0.030*sl 0.80 + 0.026*sl 0.82 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-414 sec asic ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld5s ld5sd2 ld5s ld5sd2 d gn si sg d gn si sg 0.3 0.5 0.5 1.0 0.3 0.5 0.5 1.0 6.0 6.7 stdm80 ld5s ld5sd2 ld5s ld5sd2 d gn si sg d gn si sg 0.6 0.6 0.4 1.0 0.6 0.6 0.4 1.0 6.0 6.7 parameter symbol STD80 stdm80 ld5s ld5sd2 ld5s ld5sd2 pulse width low (gn) t pwl 0.90 0.90 1.04 1.09 pulse width high (sg) t pwh 0.87 0.96 0.93 0.96 input setup time (d to gn) t su 0.66 0.60 0.66 0.74 input hold time (d to gn) t hd 0.33 0.33 0.33 0.33 input setup time (si to sg) t su 0.60 0.63 0.74 0.82 input hold time (si to sg) t hd 0.33 0.33 0.33 0.33 q qn d gn si sg sg gn si d qn q truth table dgnsisg q (n+1) qn (n+1) x 1 x 0 q (n) qn (n) xx1110 x10101 10xx10 00x001 000101
sec asic 3-415 STD80/stdm80 ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld5s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.62 0.57 + 0.025*sl 0.57 + 0.023*sl 0.57 + 0.024*sl t phl 0.79 0.72 + 0.037*sl 0.72 + 0.037*sl 0.72 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl si to q t plh 0.68 0.63 + 0.025*sl 0.64 + 0.024*sl 0.63 + 0.024*sl t phl 0.85 0.78 + 0.037*sl 0.78 + 0.037*sl 0.78 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl gn to q t plh 0.91 0.86 + 0.025*sl 0.86 + 0.024*sl 0.86 + 0.024*sl t phl 0.95 0.87 + 0.038*sl 0.87 + 0.037*sl 0.87 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl sg to q t plh 0.73 0.68 + 0.025*sl 0.68 + 0.024*sl 0.68 + 0.024*sl t phl 0.75 0.67 + 0.038*sl 0.68 + 0.037*sl 0.67 + 0.037*sl t r 0.18 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d to qn t plh 0.62 0.57 + 0.029*sl 0.58 + 0.024*sl 0.58 + 0.024*sl t phl 0.58 0.50 + 0.042*sl 0.51 + 0.038*sl 0.52 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.08 + 0.069*sl si to qn t plh 0.68 0.62 + 0.029*sl 0.63 + 0.024*sl 0.64 + 0.024*sl t phl 0.65 0.56 + 0.042*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.11 + 0.066*sl 0.08 + 0.069*sl gn to qn t plh 0.78 0.72 + 0.028*sl 0.73 + 0.024*sl 0.74 + 0.024*sl t phl 0.87 0.79 + 0.042*sl 0.80 + 0.038*sl 0.80 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl sg to qn t plh 0.58 0.52 + 0.029*sl 0.53 + 0.024*sl 0.54 + 0.024*sl t phl 0.69 0.61 + 0.041*sl 0.62 + 0.038*sl 0.63 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-416 sec asic ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.69 0.66 + 0.013*sl 0.66 + 0.012*sl 0.67 + 0.012*sl t phl 0.85 0.82 + 0.018*sl 0.82 + 0.018*sl 0.81 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.033*sl 0.10 + 0.031*sl 0.07 + 0.034*sl si to q t plh 0.75 0.72 + 0.013*sl 0.73 + 0.012*sl 0.73 + 0.012*sl t phl 0.91 0.88 + 0.018*sl 0.88 + 0.017*sl 0.87 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.07 + 0.034*sl gn to q t plh 0.98 0.95 + 0.013*sl 0.95 + 0.012*sl 0.96 + 0.012*sl t phl 1.01 0.97 + 0.018*sl 0.97 + 0.018*sl 0.97 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl sg to q t plh 0.80 0.77 + 0.013*sl 0.78 + 0.012*sl 0.78 + 0.012*sl t phl 0.81 0.77 + 0.018*sl 0.77 + 0.018*sl 0.77 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d to qn t plh 0.63 0.59 + 0.018*sl 0.60 + 0.014*sl 0.62 + 0.012*sl t phl 0.57 0.53 + 0.023*sl 0.54 + 0.020*sl 0.55 + 0.018*sl t r 0.17 0.13 + 0.020*sl 0.13 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.09 + 0.034*sl si to qn t plh 0.69 0.65 + 0.019*sl 0.66 + 0.014*sl 0.68 + 0.012*sl t phl 0.64 0.59 + 0.023*sl 0.60 + 0.020*sl 0.61 + 0.018*sl t r 0.18 0.14 + 0.019*sl 0.13 + 0.022*sl 0.10 + 0.026*sl t f 0.18 0.11 + 0.031*sl 0.11 + 0.031*sl 0.09 + 0.034*sl gn to qn t plh 0.79 0.75 + 0.018*sl 0.76 + 0.014*sl 0.78 + 0.012*sl t phl 0.86 0.82 + 0.023*sl 0.82 + 0.020*sl 0.84 + 0.018*sl t r 0.17 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.12 + 0.029*sl 0.11 + 0.031*sl 0.08 + 0.034*sl sg to qn t plh 0.59 0.55 + 0.018*sl 0.56 + 0.014*sl 0.58 + 0.012*sl t phl 0.69 0.64 + 0.023*sl 0.65 + 0.020*sl 0.66 + 0.018*sl t r 0.17 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-417 STD80/stdm80 ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld5s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.88 0.81 + 0.035*sl 0.81 + 0.033*sl 0.81 + 0.033*sl t phl 1.16 1.06 + 0.046*sl 1.07 + 0.045*sl 1.07 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl si to q t plh 0.96 0.89 + 0.035*sl 0.89 + 0.033*sl 0.90 + 0.033*sl t phl 1.26 1.17 + 0.046*sl 1.18 + 0.044*sl 1.18 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl gn to q t plh 1.28 1.21 + 0.034*sl 1.21 + 0.033*sl 1.21 + 0.033*sl t phl 1.34 1.24 + 0.046*sl 1.25 + 0.045*sl 1.25 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl sg to q t plh 1.04 0.97 + 0.035*sl 0.98 + 0.033*sl 0.98 + 0.033*sl t phl 1.07 0.97 + 0.046*sl 0.98 + 0.045*sl 0.98 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.080*sl 0.11 + 0.082*sl d to qn t plh 0.93 0.85 + 0.040*sl 0.86 + 0.035*sl 0.87 + 0.034*sl t phl 0.81 0.71 + 0.052*sl 0.72 + 0.046*sl 0.74 + 0.044*sl t r 0.30 0.17 + 0.064*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.13 + 0.082*sl si to qn t plh 1.03 0.95 + 0.040*sl 0.97 + 0.035*sl 0.98 + 0.034*sl t phl 0.89 0.79 + 0.052*sl 0.80 + 0.046*sl 0.82 + 0.044*sl t r 0.30 0.17 + 0.066*sl 0.17 + 0.067*sl 0.14 + 0.070*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.14 + 0.081*sl gn to qn t plh 1.11 1.03 + 0.039*sl 1.04 + 0.035*sl 1.05 + 0.034*sl t phl 1.21 1.10 + 0.052*sl 1.12 + 0.046*sl 1.13 + 0.045*sl t r 0.29 0.15 + 0.066*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.079*sl 0.13 + 0.081*sl sg to qn t plh 0.84 0.76 + 0.039*sl 0.77 + 0.035*sl 0.78 + 0.034*sl t phl 0.97 0.87 + 0.052*sl 0.89 + 0.046*sl 0.90 + 0.044*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.068*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.14 + 0.081*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-418 sec asic ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.97 0.94 + 0.018*sl 0.94 + 0.017*sl 0.94 + 0.017*sl t phl 1.24 1.19 + 0.025*sl 1.20 + 0.023*sl 1.21 + 0.021*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl si to q t plh 1.05 1.02 + 0.018*sl 1.02 + 0.017*sl 1.02 + 0.017*sl t phl 1.35 1.30 + 0.025*sl 1.31 + 0.022*sl 1.31 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl gn to q t plh 1.37 1.33 + 0.019*sl 1.34 + 0.017*sl 1.34 + 0.017*sl t phl 1.42 1.37 + 0.025*sl 1.38 + 0.023*sl 1.38 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl sg to q t plh 1.14 1.10 + 0.018*sl 1.10 + 0.017*sl 1.11 + 0.017*sl t phl 1.15 1.10 + 0.025*sl 1.10 + 0.023*sl 1.11 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.13 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d to qn t plh 0.94 0.89 + 0.025*sl 0.90 + 0.020*sl 0.92 + 0.018*sl t phl 0.80 0.74 + 0.031*sl 0.75 + 0.026*sl 0.77 + 0.023*sl t r 0.23 0.16 + 0.034*sl 0.17 + 0.031*sl 0.15 + 0.033*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl si to qn t plh 1.04 0.99 + 0.025*sl 1.01 + 0.020*sl 1.03 + 0.018*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.023*sl t r 0.23 0.16 + 0.034*sl 0.17 + 0.032*sl 0.16 + 0.033*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl gn to qn t plh 1.11 1.07 + 0.024*sl 1.08 + 0.020*sl 1.10 + 0.018*sl t phl 1.20 1.14 + 0.031*sl 1.15 + 0.026*sl 1.17 + 0.023*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl sg to qn t plh 0.84 0.79 + 0.024*sl 0.81 + 0.020*sl 0.82 + 0.018*sl t phl 0.96 0.90 + 0.031*sl 0.92 + 0.026*sl 0.94 + 0.023*sl t r 0.22 0.15 + 0.032*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.15 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-419 STD80/stdm80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive logic symbol cell data timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld5x4 ld5x4d2 ld5x4 ld5x4d2 dn gn dn gn 0.5 0.5 0.5 0.5 13.0 15.3 stdm80 ld5x4 ld5x4d2 ld5x4 ld5x4d2 dn gn dn gn 0.6 0.6 0.6 0.6 13.0 15.3 parameter symbol STD80 stdm80 ld5x4 ld5x4d2 ld5x4 ld5x4d2 pulse width low (gn) t pwl 0.90 0.87 1.09 1.15 input setup time (d0 to gn) t su 0.45 0.74 0.46 0.52 input hold time (d0 to gn) t hd 0.33 0.33 0.33 0.33 input setup time (d1 to gn) t su 0.45 0.52 0.46 0.52 input hold time (d1 to gn) t hd 0.33 0.33 0.33 0.33 input setup time (d2 to gn) t su 0.45 0.52 0.49 0.52 input hold time (d2 to gn) t hd 0.33 0.33 0.33 0.33 input setup time (d3 to gn) t su 0.45 0.52 0.46 0.52 input hold time (d3 to gn) t hd 0.33 0.33 0.33 0.36 d0 d1 d2 d3 gn q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table dn gn qn (n+1) qnn (n+1) 0001 1010 x 1 qn (n) qnn (n)
STD80/stdm80 3-420 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld5x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.62 + 0.038*sl 0.62 + 0.037*sl 0.62 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl gn to q0 t plh 0.81 0.76 + 0.025*sl 0.76 + 0.024*sl 0.76 + 0.024*sl t phl 1.06 0.98 + 0.038*sl 0.98 + 0.037*sl 0.98 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d1 to q1 t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.63 + 0.037*sl 0.63 + 0.037*sl 0.63 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl gn to q1 t plh 0.81 0.76 + 0.025*sl 0.77 + 0.024*sl 0.77 + 0.024*sl t phl 1.06 0.98 + 0.038*sl 0.99 + 0.037*sl 0.99 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d2 to q2 t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.63 + 0.038*sl 0.63 + 0.037*sl 0.63 + 0.037*sl t r 0.19 0.10 + 0.043*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl gn to q2 t plh 0.82 0.77 + 0.025*sl 0.77 + 0.024*sl 0.77 + 0.024*sl t phl 1.06 0.98 + 0.037*sl 0.98 + 0.037*sl 0.98 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d3 to q3 t plh 0.51 0.46 + 0.025*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.70 0.62 + 0.038*sl 0.62 + 0.037*sl 0.62 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl gn to q3 t plh 0.81 0.76 + 0.025*sl 0.76 + 0.024*sl 0.76 + 0.024*sl t phl 1.06 0.98 + 0.038*sl 0.98 + 0.037*sl 0.98 + 0.037*sl t r 0.18 0.09 + 0.046*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d0 to qn0 t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.042*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl gn to qn0 t plh 0.89 0.83 + 0.028*sl 0.84 + 0.024*sl 0.85 + 0.024*sl t phl 0.77 0.69 + 0.041*sl 0.70 + 0.038*sl 0.71 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-421 STD80/stdm80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.53 0.47 + 0.029*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.041*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl gn to qn1 t plh 0.89 0.83 + 0.028*sl 0.84 + 0.024*sl 0.85 + 0.024*sl t phl 0.78 0.69 + 0.042*sl 0.70 + 0.038*sl 0.71 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl d2 to qn2 t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.042*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.061*sl 0.10 + 0.067*sl 0.08 + 0.069*sl gn to qn2 t plh 0.89 0.83 + 0.028*sl 0.84 + 0.024*sl 0.85 + 0.024*sl t phl 0.78 0.69 + 0.042*sl 0.70 + 0.038*sl 0.71 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl d3 to qn3 t plh 0.53 0.47 + 0.028*sl 0.48 + 0.024*sl 0.49 + 0.024*sl t phl 0.47 0.39 + 0.042*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl gn to qn3 t plh 0.89 0.83 + 0.028*sl 0.84 + 0.024*sl 0.85 + 0.024*sl t phl 0.77 0.69 + 0.041*sl 0.70 + 0.038*sl 0.71 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-422 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld5x4d2 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.57 0.54 + 0.014*sl 0.55 + 0.012*sl 0.55 + 0.012*sl t phl 0.75 0.72 + 0.018*sl 0.72 + 0.018*sl 0.71 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl gn to q0 t plh 0.88 0.85 + 0.013*sl 0.86 + 0.012*sl 0.86 + 0.012*sl t phl 1.12 1.08 + 0.018*sl 1.09 + 0.018*sl 1.08 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d1 to q1 t plh 0.57 0.55 + 0.014*sl 0.55 + 0.012*sl 0.56 + 0.012*sl t phl 0.76 0.72 + 0.018*sl 0.72 + 0.018*sl 0.72 + 0.018*sl t r 0.15 0.11 + 0.019*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.10 + 0.031*sl 0.07 + 0.034*sl gn to q1 t plh 0.88 0.86 + 0.013*sl 0.86 + 0.012*sl 0.86 + 0.012*sl t phl 1.12 1.09 + 0.018*sl 1.09 + 0.018*sl 1.08 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d2 to q2 t plh 0.57 0.55 + 0.014*sl 0.55 + 0.012*sl 0.56 + 0.012*sl t phl 0.76 0.72 + 0.019*sl 0.72 + 0.018*sl 0.72 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl gn to q2 t plh 0.89 0.86 + 0.013*sl 0.86 + 0.012*sl 0.87 + 0.012*sl t phl 1.12 1.08 + 0.018*sl 1.09 + 0.018*sl 1.08 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d3 to q3 t plh 0.57 0.54 + 0.014*sl 0.55 + 0.012*sl 0.55 + 0.012*sl t phl 0.75 0.72 + 0.018*sl 0.72 + 0.018*sl 0.71 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl gn to q3 t plh 0.88 0.85 + 0.013*sl 0.86 + 0.012*sl 0.86 + 0.012*sl t phl 1.12 1.08 + 0.018*sl 1.09 + 0.018*sl 1.08 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d0 to qn0 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.013*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl gn to qn0 t plh 0.90 0.87 + 0.018*sl 0.88 + 0.014*sl 0.89 + 0.012*sl t phl 0.77 0.72 + 0.023*sl 0.73 + 0.020*sl 0.74 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-423 STD80/stdm80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld5x4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.014*sl 0.53 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.031*sl 0.08 + 0.034*sl gn to qn1 t plh 0.90 0.87 + 0.018*sl 0.88 + 0.013*sl 0.89 + 0.012*sl t phl 0.77 0.72 + 0.023*sl 0.73 + 0.020*sl 0.75 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl d2 to qn2 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.013*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl gn to qn2 t plh 0.90 0.86 + 0.018*sl 0.87 + 0.014*sl 0.89 + 0.012*sl t phl 0.77 0.73 + 0.023*sl 0.73 + 0.020*sl 0.75 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl d3 to qn3 t plh 0.54 0.50 + 0.018*sl 0.51 + 0.013*sl 0.52 + 0.012*sl t phl 0.46 0.41 + 0.023*sl 0.42 + 0.020*sl 0.44 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.031*sl 0.08 + 0.034*sl gn to qn3 t plh 0.90 0.87 + 0.018*sl 0.88 + 0.014*sl 0.89 + 0.012*sl t phl 0.77 0.72 + 0.023*sl 0.73 + 0.020*sl 0.74 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.023*sl 0.09 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-424 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld5x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.72 0.65 + 0.035*sl 0.65 + 0.033*sl 0.65 + 0.033*sl t phl 0.96 0.87 + 0.047*sl 0.88 + 0.044*sl 0.88 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl gn to q0 t plh 1.15 1.08 + 0.034*sl 1.08 + 0.033*sl 1.08 + 0.033*sl t phl 1.51 1.41 + 0.047*sl 1.42 + 0.044*sl 1.42 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d1 to q1 t plh 0.72 0.65 + 0.034*sl 0.66 + 0.033*sl 0.66 + 0.033*sl t phl 0.97 0.87 + 0.046*sl 0.88 + 0.045*sl 0.88 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl gn to q1 t plh 1.15 1.08 + 0.034*sl 1.09 + 0.033*sl 1.09 + 0.033*sl t phl 1.51 1.42 + 0.047*sl 1.42 + 0.045*sl 1.43 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d2 to q2 t plh 0.72 0.65 + 0.035*sl 0.66 + 0.033*sl 0.66 + 0.033*sl t phl 0.97 0.87 + 0.047*sl 0.88 + 0.044*sl 0.88 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl gn to q2 t plh 1.16 1.09 + 0.035*sl 1.09 + 0.033*sl 1.09 + 0.033*sl t phl 1.51 1.42 + 0.046*sl 1.42 + 0.045*sl 1.42 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.12 + 0.070*sl 0.11 + 0.072*sl t f 0.28 0.13 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d3 to q3 t plh 0.72 0.65 + 0.035*sl 0.65 + 0.033*sl 0.65 + 0.033*sl t phl 0.96 0.87 + 0.046*sl 0.87 + 0.045*sl 0.88 + 0.044*sl t r 0.26 0.12 + 0.068*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.083*sl gn to q3 t plh 1.15 1.08 + 0.035*sl 1.08 + 0.033*sl 1.08 + 0.033*sl t phl 1.51 1.41 + 0.047*sl 1.42 + 0.045*sl 1.42 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d0 to qn0 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl gn to qn0 t plh 1.28 1.20 + 0.038*sl 1.21 + 0.035*sl 1.22 + 0.034*sl t phl 1.08 0.97 + 0.052*sl 0.99 + 0.046*sl 1.00 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-425 STD80/stdm80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl gn to qn1 t plh 1.28 1.20 + 0.039*sl 1.22 + 0.035*sl 1.22 + 0.034*sl t phl 1.08 0.98 + 0.052*sl 0.99 + 0.046*sl 1.01 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl d2 to qn2 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl gn to qn2 t plh 1.28 1.20 + 0.038*sl 1.21 + 0.035*sl 1.22 + 0.034*sl t phl 1.08 0.98 + 0.052*sl 1.00 + 0.046*sl 1.01 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl d3 to qn3 t plh 0.74 0.66 + 0.038*sl 0.67 + 0.035*sl 0.68 + 0.034*sl t phl 0.65 0.55 + 0.052*sl 0.56 + 0.046*sl 0.57 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl gn to qn3 t plh 1.28 1.20 + 0.039*sl 1.22 + 0.035*sl 1.22 + 0.034*sl t phl 1.08 0.97 + 0.052*sl 0.99 + 0.046*sl 1.00 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-426 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld5x4d2 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.81 0.77 + 0.019*sl 0.77 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.01 + 0.021*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl gn to q0 t plh 1.24 1.21 + 0.019*sl 1.21 + 0.017*sl 1.22 + 0.017*sl t phl 1.60 1.54 + 0.026*sl 1.55 + 0.023*sl 1.56 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d1 to q1 t plh 0.81 0.77 + 0.019*sl 0.78 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.01 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl gn to q1 t plh 1.25 1.21 + 0.018*sl 1.21 + 0.017*sl 1.22 + 0.017*sl t phl 1.60 1.55 + 0.025*sl 1.55 + 0.023*sl 1.56 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d2 to q2 t plh 0.81 0.77 + 0.018*sl 0.78 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.01 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl gn to q2 t plh 1.25 1.21 + 0.019*sl 1.22 + 0.017*sl 1.22 + 0.017*sl t phl 1.60 1.54 + 0.025*sl 1.55 + 0.023*sl 1.56 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d3 to q3 t plh 0.81 0.77 + 0.019*sl 0.77 + 0.017*sl 0.78 + 0.017*sl t phl 1.04 0.99 + 0.026*sl 1.00 + 0.023*sl 1.00 + 0.022*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl gn to q3 t plh 1.24 1.21 + 0.019*sl 1.21 + 0.017*sl 1.22 + 0.017*sl t phl 1.60 1.54 + 0.026*sl 1.55 + 0.023*sl 1.56 + 0.022*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.032*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.040*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d0 to qn0 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.63 0.57 + 0.031*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl gn to qn0 t plh 1.30 1.25 + 0.024*sl 1.26 + 0.020*sl 1.28 + 0.018*sl t phl 1.07 1.01 + 0.031*sl 1.03 + 0.026*sl 1.04 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-427 STD80/stdm80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld5x4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.64 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.15 + 0.032*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl gn to qn1 t plh 1.30 1.25 + 0.024*sl 1.26 + 0.020*sl 1.28 + 0.018*sl t phl 1.07 1.01 + 0.030*sl 1.03 + 0.026*sl 1.04 + 0.023*sl t r 0.21 0.14 + 0.032*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl d2 to qn2 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.64 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.15 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl gn to qn2 t plh 1.29 1.24 + 0.024*sl 1.26 + 0.020*sl 1.27 + 0.018*sl t phl 1.08 1.02 + 0.030*sl 1.03 + 0.026*sl 1.05 + 0.023*sl t r 0.21 0.15 + 0.032*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl d3 to qn3 t plh 0.74 0.69 + 0.024*sl 0.70 + 0.020*sl 0.72 + 0.018*sl t phl 0.63 0.57 + 0.030*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl gn to qn3 t plh 1.30 1.25 + 0.024*sl 1.26 + 0.020*sl 1.28 + 0.018*sl t phl 1.07 1.01 + 0.031*sl 1.03 + 0.026*sl 1.04 + 0.023*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.14 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-428 sec asic ld6/ld6d2 d latch with active low, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld6 ld6d2 ld6 ld6d2 d gn rn d gn rn 0.5 0.5 0.4 0.5 0.5 0.4 4.7 5.3 stdm80 ld6 ld6d2 ld6 ld6d2 d gn rn d gn rn 0.6 0.6 0.8 0.6 0.6 0.8 4.7 5.3 parameter symbol STD80 stdm80 ld6 ld6d2 ld6 ld6d2 pulse width low (gn) t pwl 0.87 0.87 0.87 0.93 pulse width low (rn) t pwl 0.87 0.87 0.82 0.82 input setup time (d to gn) t su 0.74 0.76 0.74 0.79 input hold time (d to gn) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.38 0.33 0.33 input hold time (rn to gn) t hd 0.33 0.33 0.38 0.33 d gn q qn rn gn gn gnb rn rn d gnb gn q rn gn gnb qn truth table d gn rn q (n+1) qn (n+1) 00101 10110 x 1 1 q (n) qn (n) xx001
sec asic 3-429 STD80/stdm80 ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.57 0.51 + 0.032*sl 0.52 + 0.026*sl 0.54 + 0.024*sl t phl 0.64 0.56 + 0.041*sl 0.57 + 0.038*sl 0.58 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl gn to q t plh 0.70 0.64 + 0.031*sl 0.65 + 0.026*sl 0.67 + 0.024*sl t phl 0.66 0.57 + 0.041*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.23 0.13 + 0.049*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.08 + 0.069*sl rn to q t plh 0.33 0.27 + 0.031*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.29 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.08 + 0.069*sl d to qn t plh 0.68 0.63 + 0.025*sl 0.64 + 0.024*sl 0.64 + 0.024*sl t phl 0.75 0.67 + 0.037*sl 0.67 + 0.037*sl 0.67 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl gn to qn t plh 0.70 0.65 + 0.026*sl 0.65 + 0.024*sl 0.65 + 0.024*sl t phl 0.88 0.80 + 0.036*sl 0.80 + 0.037*sl 0.80 + 0.037*sl t r 0.19 0.09 + 0.046*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl rn to qn t plh 0.47 0.41 + 0.030*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.51 0.43 + 0.037*sl 0.43 + 0.037*sl 0.43 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-430 sec asic ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.58 0.54 + 0.021*sl 0.55 + 0.015*sl 0.59 + 0.012*sl t phl 0.63 0.59 + 0.023*sl 0.60 + 0.020*sl 0.61 + 0.018*sl t r 0.20 0.15 + 0.025*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.11 + 0.031*sl 0.11 + 0.031*sl 0.09 + 0.034*sl gn to q t plh 0.71 0.67 + 0.021*sl 0.68 + 0.015*sl 0.72 + 0.012*sl t phl 0.65 0.60 + 0.023*sl 0.61 + 0.020*sl 0.62 + 0.018*sl t r 0.20 0.15 + 0.024*sl 0.15 + 0.023*sl 0.13 + 0.026*sl t f 0.18 0.11 + 0.032*sl 0.11 + 0.031*sl 0.09 + 0.034*sl rn to q t plh 0.34 0.30 + 0.020*sl 0.31 + 0.015*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl d to qn t plh 0.75 0.72 + 0.013*sl 0.73 + 0.012*sl 0.73 + 0.012*sl t phl 0.83 0.79 + 0.018*sl 0.80 + 0.017*sl 0.79 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.030*sl 0.08 + 0.034*sl gn to qn t plh 0.76 0.73 + 0.014*sl 0.74 + 0.012*sl 0.74 + 0.012*sl t phl 0.96 0.92 + 0.017*sl 0.92 + 0.017*sl 0.91 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.033*sl 0.11 + 0.030*sl 0.08 + 0.034*sl rn to qn t plh 0.53 0.50 + 0.018*sl 0.51 + 0.014*sl 0.53 + 0.012*sl t phl 0.59 0.55 + 0.018*sl 0.55 + 0.017*sl 0.54 + 0.018*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.022*sl 0.11 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-431 STD80/stdm80 ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.85 0.77 + 0.044*sl 0.79 + 0.038*sl 0.81 + 0.035*sl t phl 0.87 0.77 + 0.052*sl 0.79 + 0.046*sl 0.80 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl gn to q t plh 1.00 0.91 + 0.044*sl 0.93 + 0.037*sl 0.95 + 0.035*sl t phl 0.89 0.79 + 0.052*sl 0.81 + 0.046*sl 0.82 + 0.044*sl t r 0.31 0.17 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.081*sl rn to q t plh 0.44 0.35 + 0.043*sl 0.37 + 0.037*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.071*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl d to qn t plh 0.95 0.87 + 0.035*sl 0.88 + 0.033*sl 0.88 + 0.033*sl t phl 1.09 1.00 + 0.047*sl 1.01 + 0.045*sl 1.01 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl gn to qn t plh 0.97 0.90 + 0.035*sl 0.90 + 0.033*sl 0.90 + 0.033*sl t phl 1.23 1.14 + 0.047*sl 1.15 + 0.044*sl 1.15 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl rn to qn t plh 0.62 0.54 + 0.042*sl 0.56 + 0.036*sl 0.58 + 0.034*sl t phl 0.67 0.58 + 0.047*sl 0.59 + 0.045*sl 0.59 + 0.044*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-432 sec asic ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.87 0.81 + 0.028*sl 0.83 + 0.022*sl 0.85 + 0.020*sl t phl 0.86 0.80 + 0.031*sl 0.81 + 0.026*sl 0.83 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.14 + 0.038*sl gn to q t plh 1.01 0.95 + 0.028*sl 0.97 + 0.022*sl 0.99 + 0.020*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.023*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.034*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl rn to q t plh 0.44 0.39 + 0.027*sl 0.40 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.042*sl 0.14 + 0.038*sl 0.14 + 0.038*sl d to qn t plh 1.03 1.00 + 0.019*sl 1.00 + 0.017*sl 1.01 + 0.017*sl t phl 1.20 1.15 + 0.024*sl 1.16 + 0.022*sl 1.16 + 0.021*sl t r 0.19 0.13 + 0.032*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.22 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl gn to qn t plh 1.06 1.02 + 0.019*sl 1.02 + 0.017*sl 1.03 + 0.017*sl t phl 1.34 1.30 + 0.024*sl 1.30 + 0.022*sl 1.31 + 0.021*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl rn to qn t plh 0.71 0.66 + 0.023*sl 0.67 + 0.020*sl 0.68 + 0.018*sl t phl 0.78 0.73 + 0.025*sl 0.73 + 0.022*sl 0.74 + 0.021*sl t r 0.23 0.16 + 0.036*sl 0.17 + 0.033*sl 0.16 + 0.034*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-433 STD80/stdm80 ld7/ld7d2 d latch with active low, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld7 ld7d2 ld7 ld7d2 d gn sn d gn sn 0.6 0.6 0.5 0.6 0.6 0.5 4.3 5.0 stdm80 ld7 ld7d2 ld7 ld7d2 d gn sn d gn sn 0.6 0.6 0.8 0.6 0.6 0.8 4.3 5.0 parameter symbol STD80 stdm80 ld7 ld7d2 ld7 ld7d2 pulse width low (gn) t pwl 0.87 0.87 0.87 0.93 pulse width low (sn) t pwl 0.87 0.87 0.82 0.87 input setup time (d to gn) t su 0.60 0.66 0.66 0.74 input hold time (d to gn) t hd 0.33 0.33 0.33 0.33 recovery time (sn) t rc 0.33 0.38 0.33 0.33 input hold time (sn to gn) t hd 0.33 0.33 0.38 0.33 d gn q qn sn gn gn gnb sn sn d gnb gn qn sn gn gnb q truth table d gn sn q (n+1) qn (n+1) 00101 10110 x 1 1 q (n) qn (n) xx010
STD80/stdm80 3-434 sec asic ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld7 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.53 0.48 + 0.025*sl 0.48 + 0.024*sl 0.48 + 0.024*sl t phl 0.76 0.68 + 0.037*sl 0.68 + 0.037*sl 0.68 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl gn to q t plh 0.69 0.64 + 0.025*sl 0.65 + 0.024*sl 0.65 + 0.024*sl t phl 0.87 0.80 + 0.037*sl 0.80 + 0.037*sl 0.80 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl sn to q t plh 0.47 0.41 + 0.030*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.51 0.43 + 0.037*sl 0.43 + 0.037*sl 0.43 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.22 0.10 + 0.062*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d to qn t plh 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.55 + 0.024*sl t phl 0.49 0.41 + 0.041*sl 0.41 + 0.038*sl 0.42 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.066*sl 0.08 + 0.069*sl gn to qn t plh 0.70 0.63 + 0.032*sl 0.65 + 0.026*sl 0.67 + 0.024*sl t phl 0.65 0.57 + 0.041*sl 0.58 + 0.038*sl 0.59 + 0.037*sl t r 0.23 0.13 + 0.047*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.062*sl 0.10 + 0.067*sl 0.08 + 0.069*sl sn to qn t plh 0.33 0.27 + 0.031*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t phl 0.36 0.28 + 0.040*sl 0.29 + 0.038*sl 0.29 + 0.037*sl t r 0.23 0.13 + 0.048*sl 0.13 + 0.048*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.061*sl 0.10 + 0.066*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-435 STD80/stdm80 ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.59 0.56 + 0.014*sl 0.57 + 0.012*sl 0.57 + 0.012*sl t phl 0.84 0.80 + 0.018*sl 0.80 + 0.017*sl 0.79 + 0.018*sl t r 0.15 0.11 + 0.022*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl gn to q t plh 0.76 0.73 + 0.014*sl 0.74 + 0.012*sl 0.74 + 0.012*sl t phl 0.95 0.92 + 0.017*sl 0.92 + 0.017*sl 0.91 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.11 + 0.023*sl 0.07 + 0.026*sl t f 0.17 0.11 + 0.032*sl 0.11 + 0.030*sl 0.08 + 0.034*sl sn to q t plh 0.53 0.50 + 0.018*sl 0.51 + 0.014*sl 0.53 + 0.012*sl t phl 0.59 0.55 + 0.018*sl 0.55 + 0.017*sl 0.54 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.030*sl 0.08 + 0.034*sl d to qn t plh 0.59 0.55 + 0.021*sl 0.56 + 0.015*sl 0.59 + 0.012*sl t phl 0.48 0.43 + 0.023*sl 0.44 + 0.020*sl 0.46 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.11 + 0.032*sl 0.12 + 0.031*sl 0.09 + 0.034*sl gn to qn t plh 0.71 0.67 + 0.021*sl 0.68 + 0.015*sl 0.71 + 0.012*sl t phl 0.64 0.60 + 0.023*sl 0.60 + 0.020*sl 0.62 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.18 0.12 + 0.030*sl 0.11 + 0.031*sl 0.09 + 0.034*sl sn to qn t plh 0.34 0.30 + 0.020*sl 0.31 + 0.015*sl 0.35 + 0.012*sl t phl 0.36 0.31 + 0.023*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-436 sec asic ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld7 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.75 0.68 + 0.035*sl 0.68 + 0.033*sl 0.69 + 0.033*sl t phl 1.05 0.95 + 0.047*sl 0.96 + 0.045*sl 0.96 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl gn to q t plh 0.96 0.89 + 0.035*sl 0.90 + 0.033*sl 0.90 + 0.033*sl t phl 1.23 1.14 + 0.046*sl 1.14 + 0.045*sl 1.14 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.29 0.14 + 0.076*sl 0.12 + 0.080*sl 0.11 + 0.082*sl sn to q t plh 0.62 0.54 + 0.042*sl 0.56 + 0.036*sl 0.58 + 0.034*sl t phl 0.67 0.58 + 0.047*sl 0.59 + 0.045*sl 0.59 + 0.044*sl t r 0.30 0.16 + 0.069*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.29 0.13 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl d to qn t plh 0.81 0.72 + 0.044*sl 0.74 + 0.038*sl 0.76 + 0.035*sl t phl 0.68 0.57 + 0.052*sl 0.59 + 0.046*sl 0.60 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl gn to qn t plh 0.99 0.90 + 0.044*sl 0.92 + 0.037*sl 0.94 + 0.035*sl t phl 0.89 0.79 + 0.052*sl 0.80 + 0.046*sl 0.82 + 0.044*sl t r 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.17 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.081*sl sn to qn t plh 0.44 0.35 + 0.043*sl 0.37 + 0.037*sl 0.39 + 0.034*sl t phl 0.47 0.37 + 0.051*sl 0.38 + 0.047*sl 0.40 + 0.045*sl t r 0.31 0.17 + 0.071*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-437 STD80/stdm80 ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.84 0.80 + 0.019*sl 0.81 + 0.017*sl 0.81 + 0.017*sl t phl 1.16 1.11 + 0.024*sl 1.11 + 0.022*sl 1.12 + 0.021*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.22 0.14 + 0.039*sl 0.14 + 0.037*sl 0.14 + 0.038*sl gn to q t plh 1.05 1.01 + 0.019*sl 1.02 + 0.017*sl 1.02 + 0.017*sl t phl 1.34 1.29 + 0.024*sl 1.30 + 0.022*sl 1.30 + 0.021*sl t r 0.19 0.13 + 0.031*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.22 0.13 + 0.041*sl 0.15 + 0.037*sl 0.14 + 0.038*sl sn to q t plh 0.71 0.66 + 0.023*sl 0.67 + 0.020*sl 0.69 + 0.018*sl t phl 0.78 0.73 + 0.025*sl 0.73 + 0.022*sl 0.74 + 0.021*sl t r 0.23 0.16 + 0.036*sl 0.17 + 0.033*sl 0.17 + 0.033*sl t f 0.21 0.13 + 0.040*sl 0.14 + 0.037*sl 0.14 + 0.038*sl d to qn t plh 0.82 0.77 + 0.028*sl 0.78 + 0.022*sl 0.80 + 0.020*sl t phl 0.66 0.60 + 0.031*sl 0.62 + 0.026*sl 0.64 + 0.023*sl t r 0.25 0.17 + 0.037*sl 0.18 + 0.034*sl 0.18 + 0.035*sl t f 0.22 0.14 + 0.039*sl 0.14 + 0.039*sl 0.15 + 0.038*sl gn to qn t plh 1.00 0.95 + 0.028*sl 0.96 + 0.023*sl 0.99 + 0.019*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.023*sl t r 0.25 0.17 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.038*sl 0.15 + 0.038*sl sn to qn t plh 0.44 0.39 + 0.027*sl 0.40 + 0.022*sl 0.43 + 0.019*sl t phl 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.21 0.13 + 0.042*sl 0.14 + 0.038*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-438 sec asic ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count STD80 ld8 ld8d2 ld8 ld8d2 d gn rn sn d gn rn sn 0.6 0.6 0.4 0.7 0.6 0.6 0.4 0.7 6.0 6.7 stdm80 ld8 ld8d2 ld8 ld8d2 d gn rn sn d gn rn sn 0.6 0.6 0.4 0.8 0.6 0.6 0.4 0.8 6.0 6.7 parameter symbol STD80 stdm80 ld8 ld8d2 ld8 ld8d2 pulse width low (gn) t pwl 0.87 0.87 0.93 1.04 pulse width low (rn) t pwl 0.87 0.87 0.90 1.01 pulse width low (sn) t pwl 0.87 0.87 0.80 0.87 input setup time (d to gn) t su 0.00 0.00 0.90 1.01 input hold time (d to gn) t hd 0.33 0.33 0.33 0.33 recovery time (rn) t rc 0.33 0.38 0.33 0.38 input hold time (rn to gn) t hd 0.33 0.33 0.33 0.33 recovery time (sn) t rc 0.33 0.38 0.33 0.38 input hold time (sn to gn) t hd 0.33 0.33 0.38 0.33 d gn q qn rn sn gn gn gnb rn rn d gnb gn qn rn gn gnb q sn sn sn truth table dgnrnsn q (n+1) qn (n+1) 001101 101110 x 1 1 1 q (n) qn (n) xx1010 xx0101 xx0010
sec asic 3-439 STD80/stdm80 ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.74 0.69 + 0.028*sl 0.69 + 0.024*sl 0.70 + 0.024*sl t phl 0.96 0.89 + 0.038*sl 0.89 + 0.037*sl 0.89 + 0.037*sl t r 0.20 0.10 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl gn to q t plh 0.87 0.82 + 0.027*sl 0.82 + 0.024*sl 0.83 + 0.024*sl t phl 0.96 0.89 + 0.039*sl 0.89 + 0.037*sl 0.89 + 0.037*sl t r 0.19 0.10 + 0.048*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.061*sl 0.10 + 0.066*sl 0.07 + 0.069*sl sn to q t plh 0.45 0.39 + 0.028*sl 0.40 + 0.024*sl 0.40 + 0.024*sl t phl 0.52 0.44 + 0.038*sl 0.44 + 0.037*sl 0.44 + 0.037*sl t r 0.19 0.11 + 0.044*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.07 + 0.069*sl rn to q t plh 0.50 0.45 + 0.028*sl 0.46 + 0.024*sl 0.46 + 0.024*sl t phl 0.69 0.61 + 0.039*sl 0.61 + 0.037*sl 0.61 + 0.037*sl t r 0.19 0.11 + 0.044*sl 0.09 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.066*sl 0.07 + 0.069*sl d to qn t plh 0.75 0.69 + 0.030*sl 0.70 + 0.026*sl 0.72 + 0.024*sl t phl 0.67 0.59 + 0.040*sl 0.60 + 0.038*sl 0.60 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.12 + 0.049*sl 0.10 + 0.052*sl t f 0.23 0.10 + 0.066*sl 0.10 + 0.067*sl 0.07 + 0.069*sl gn to qn t plh 0.75 0.69 + 0.031*sl 0.70 + 0.026*sl 0.72 + 0.024*sl t phl 0.80 0.72 + 0.040*sl 0.73 + 0.038*sl 0.73 + 0.037*sl t r 0.22 0.13 + 0.048*sl 0.12 + 0.049*sl 0.10 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.07 + 0.069*sl sn to qn t plh 0.31 0.24 + 0.031*sl 0.26 + 0.026*sl 0.28 + 0.024*sl t phl 0.38 0.30 + 0.040*sl 0.30 + 0.038*sl 0.31 + 0.037*sl t r 0.23 0.13 + 0.046*sl 0.13 + 0.049*sl 0.10 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.11 + 0.067*sl 0.08 + 0.069*sl rn to qn t plh 0.48 0.42 + 0.031*sl 0.43 + 0.026*sl 0.45 + 0.024*sl t phl 0.43 0.35 + 0.040*sl 0.36 + 0.038*sl 0.37 + 0.037*sl t r 0.22 0.13 + 0.047*sl 0.12 + 0.049*sl 0.10 + 0.052*sl t f 0.23 0.10 + 0.064*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-440 sec asic ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ld8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.81 0.78 + 0.015*sl 0.78 + 0.013*sl 0.79 + 0.012*sl t phl 1.04 1.00 + 0.019*sl 1.01 + 0.017*sl 1.00 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.030*sl 0.09 + 0.034*sl gn to q t plh 0.94 0.91 + 0.015*sl 0.91 + 0.013*sl 0.92 + 0.012*sl t phl 1.04 1.01 + 0.019*sl 1.01 + 0.017*sl 1.00 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.030*sl 0.09 + 0.034*sl sn to q t plh 0.51 0.48 + 0.015*sl 0.49 + 0.013*sl 0.50 + 0.012*sl t phl 0.60 0.56 + 0.019*sl 0.56 + 0.017*sl 0.56 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.032*sl 0.12 + 0.030*sl 0.09 + 0.034*sl rn to q t plh 0.57 0.54 + 0.015*sl 0.54 + 0.013*sl 0.55 + 0.012*sl t phl 0.77 0.73 + 0.019*sl 0.73 + 0.017*sl 0.73 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.18 0.12 + 0.029*sl 0.12 + 0.030*sl 0.09 + 0.034*sl d to qn t plh 0.77 0.72 + 0.021*sl 0.74 + 0.015*sl 0.77 + 0.012*sl t phl 0.67 0.62 + 0.023*sl 0.63 + 0.020*sl 0.64 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl gn to qn t plh 0.77 0.73 + 0.020*sl 0.74 + 0.015*sl 0.77 + 0.012*sl t phl 0.79 0.75 + 0.023*sl 0.76 + 0.020*sl 0.77 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.030*sl 0.10 + 0.031*sl 0.08 + 0.034*sl sn to qn t plh 0.32 0.28 + 0.020*sl 0.29 + 0.015*sl 0.32 + 0.012*sl t phl 0.37 0.33 + 0.023*sl 0.33 + 0.020*sl 0.35 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.18 0.12 + 0.031*sl 0.12 + 0.031*sl 0.09 + 0.034*sl rn to qn t plh 0.49 0.45 + 0.021*sl 0.46 + 0.015*sl 0.49 + 0.012*sl t phl 0.43 0.38 + 0.023*sl 0.39 + 0.020*sl 0.40 + 0.018*sl t r 0.19 0.15 + 0.022*sl 0.14 + 0.024*sl 0.12 + 0.026*sl t f 0.17 0.11 + 0.031*sl 0.11 + 0.031*sl 0.08 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-441 STD80/stdm80 ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.10 1.03 + 0.037*sl 1.04 + 0.034*sl 1.04 + 0.033*sl t phl 1.33 1.24 + 0.049*sl 1.25 + 0.045*sl 1.25 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.13 + 0.070*sl 0.11 + 0.071*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.081*sl gn to q t plh 1.24 1.17 + 0.037*sl 1.18 + 0.034*sl 1.18 + 0.033*sl t phl 1.35 1.25 + 0.049*sl 1.26 + 0.045*sl 1.27 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.13 + 0.070*sl 0.11 + 0.071*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.081*sl sn to q t plh 0.60 0.52 + 0.037*sl 0.54 + 0.034*sl 0.54 + 0.034*sl t phl 0.71 0.61 + 0.049*sl 0.62 + 0.045*sl 0.63 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.12 + 0.070*sl 0.11 + 0.071*sl t f 0.30 0.15 + 0.078*sl 0.14 + 0.079*sl 0.13 + 0.081*sl rn to q t plh 0.71 0.64 + 0.037*sl 0.65 + 0.034*sl 0.65 + 0.033*sl t phl 0.93 0.83 + 0.050*sl 0.84 + 0.046*sl 0.85 + 0.044*sl t r 0.27 0.13 + 0.067*sl 0.13 + 0.070*sl 0.11 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.079*sl 0.13 + 0.081*sl d to qn t plh 1.05 0.96 + 0.043*sl 0.98 + 0.037*sl 0.99 + 0.035*sl t phl 0.99 0.89 + 0.051*sl 0.90 + 0.046*sl 0.92 + 0.044*sl t r 0.30 0.16 + 0.070*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.082*sl gn to qn t plh 1.06 0.98 + 0.042*sl 1.00 + 0.037*sl 1.01 + 0.034*sl t phl 1.13 1.03 + 0.051*sl 1.04 + 0.046*sl 1.06 + 0.044*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.070*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl sn to qn t plh 0.43 0.34 + 0.042*sl 0.36 + 0.037*sl 0.37 + 0.034*sl t phl 0.49 0.39 + 0.051*sl 0.40 + 0.046*sl 0.41 + 0.045*sl t r 0.30 0.16 + 0.070*sl 0.16 + 0.070*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.082*sl 0.13 + 0.082*sl rn to qn t plh 0.65 0.56 + 0.042*sl 0.58 + 0.037*sl 0.59 + 0.035*sl t phl 0.60 0.50 + 0.051*sl 0.51 + 0.046*sl 0.52 + 0.045*sl t r 0.30 0.16 + 0.070*sl 0.17 + 0.070*sl 0.16 + 0.070*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.13 + 0.082*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-442 sec asic ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ld8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.19 1.15 + 0.020*sl 1.16 + 0.018*sl 1.16 + 0.017*sl t phl 1.44 1.39 + 0.027*sl 1.40 + 0.023*sl 1.41 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.037*sl 0.16 + 0.037*sl gn to q t plh 1.33 1.29 + 0.020*sl 1.30 + 0.018*sl 1.30 + 0.017*sl t phl 1.46 1.40 + 0.027*sl 1.41 + 0.023*sl 1.42 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.042*sl 0.16 + 0.037*sl 0.16 + 0.037*sl sn to q t plh 0.69 0.65 + 0.020*sl 0.65 + 0.018*sl 0.66 + 0.017*sl t phl 0.82 0.76 + 0.027*sl 0.77 + 0.023*sl 0.78 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.038*sl 0.16 + 0.037*sl rn to q t plh 0.80 0.76 + 0.020*sl 0.77 + 0.018*sl 0.77 + 0.017*sl t phl 1.04 0.98 + 0.027*sl 0.99 + 0.023*sl 1.00 + 0.022*sl t r 0.20 0.14 + 0.033*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.23 0.15 + 0.041*sl 0.15 + 0.039*sl 0.16 + 0.037*sl d to qn t plh 1.06 1.01 + 0.027*sl 1.02 + 0.022*sl 1.04 + 0.019*sl t phl 0.98 0.92 + 0.031*sl 0.94 + 0.026*sl 0.95 + 0.023*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.039*sl 0.14 + 0.038*sl gn to qn t plh 1.08 1.02 + 0.027*sl 1.04 + 0.022*sl 1.06 + 0.019*sl t phl 1.12 1.06 + 0.030*sl 1.08 + 0.026*sl 1.10 + 0.023*sl t r 0.24 0.17 + 0.037*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.22 0.14 + 0.039*sl 0.14 + 0.039*sl 0.14 + 0.038*sl sn to qn t plh 0.44 0.38 + 0.027*sl 0.40 + 0.022*sl 0.42 + 0.019*sl t phl 0.48 0.42 + 0.031*sl 0.43 + 0.026*sl 0.45 + 0.023*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.22 0.14 + 0.041*sl 0.15 + 0.038*sl 0.14 + 0.038*sl rn to qn t plh 0.66 0.61 + 0.027*sl 0.62 + 0.022*sl 0.64 + 0.019*sl t phl 0.59 0.53 + 0.031*sl 0.55 + 0.026*sl 0.56 + 0.023*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.22 0.13 + 0.041*sl 0.14 + 0.039*sl 0.14 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-443 STD80/stdm80 lds2 d latch with active high, synchronous clear logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width high (g) t pwh 0.79 0.82 input setup time (d to g) t su 0.55 0.55 input hold time (d to g) t hd 0.33 0.33 input setup time (crn to g) t su 0.55 0.55 input hold time (crn to g) t hd 0.33 0.33 d crn g q qn qn q d g gb g gb g g gb crn truth table cell data d crn g q (n+1) qn (n+1) 01101 11110 x x 0 q (n) qn (n) x0101 input load (sl) gate count STD80 d crn g 4.3 0.5 0.5 0.5 stdm80 d crn g 4.3 0.6 0.6 0.6
STD80/stdm80 3-444 sec asic lds2 d latch with active high, synchronous clear switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 lds2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.58 0.53 + 0.025*sl 0.53 + 0.024*sl 0.53 + 0.024*sl t phl 0.74 0.66 + 0.038*sl 0.66 + 0.037*sl 0.66 + 0.037*sl t r 0.19 0.10 + 0.044*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl crn to q t plh 0.60 0.55 + 0.025*sl 0.55 + 0.024*sl 0.55 + 0.024*sl t phl 0.71 0.64 + 0.038*sl 0.64 + 0.037*sl 0.64 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl g to q t plh 0.66 0.61 + 0.026*sl 0.61 + 0.023*sl 0.61 + 0.024*sl t phl 0.66 0.58 + 0.038*sl 0.59 + 0.037*sl 0.59 + 0.037*sl t r 0.19 0.09 + 0.047*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d to qn t plh 0.57 0.51 + 0.028*sl 0.52 + 0.024*sl 0.53 + 0.024*sl t phl 0.54 0.46 + 0.042*sl 0.47 + 0.038*sl 0.47 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.066*sl 0.08 + 0.069*sl crn to qn t plh 0.54 0.49 + 0.028*sl 0.49 + 0.024*sl 0.50 + 0.024*sl t phl 0.56 0.48 + 0.041*sl 0.49 + 0.038*sl 0.49 + 0.037*sl t r 0.21 0.11 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl g to qn t plh 0.49 0.44 + 0.027*sl 0.44 + 0.024*sl 0.45 + 0.024*sl t phl 0.62 0.54 + 0.041*sl 0.55 + 0.038*sl 0.55 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-445 STD80/stdm80 lds2 d latch with active high, synchronous clear switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 lds2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.84 0.77 + 0.035*sl 0.77 + 0.033*sl 0.77 + 0.033*sl t phl 1.03 0.94 + 0.047*sl 0.94 + 0.044*sl 0.94 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.080*sl 0.11 + 0.082*sl crn to q t plh 0.85 0.78 + 0.035*sl 0.78 + 0.033*sl 0.78 + 0.033*sl t phl 0.99 0.90 + 0.047*sl 0.91 + 0.044*sl 0.91 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl g to q t plh 0.95 0.88 + 0.035*sl 0.89 + 0.033*sl 0.89 + 0.033*sl t phl 0.94 0.85 + 0.047*sl 0.86 + 0.044*sl 0.86 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d to qn t plh 0.80 0.72 + 0.039*sl 0.74 + 0.035*sl 0.74 + 0.034*sl t phl 0.77 0.66 + 0.052*sl 0.68 + 0.046*sl 0.69 + 0.044*sl t r 0.29 0.15 + 0.066*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl crn to qn t plh 0.77 0.69 + 0.038*sl 0.70 + 0.035*sl 0.71 + 0.034*sl t phl 0.78 0.67 + 0.052*sl 0.69 + 0.046*sl 0.70 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.081*sl g to qn t plh 0.72 0.64 + 0.037*sl 0.65 + 0.035*sl 0.66 + 0.034*sl t phl 0.89 0.78 + 0.052*sl 0.80 + 0.046*sl 0.81 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.13 + 0.069*sl 0.12 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-446 sec asic lds6 d latch with active low, synchronous clear logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol STD80 stdm80 pulse width low (gn) t pwl 0.87 0.85 input setup time (d to gn) t su 0.68 0.68 input hold time (d to gn) t hd 0.33 0.33 input setup time (crn to gn) t su 0.68 0.68 input hold time (crn to gn) t hd 0.33 0.33 d crn gn q qn qn q d gnb gn gn gnb gn gn gnb crn truth table cell data d crn gn q (n+1) qn (n+1) 01001 11010 x x 1 q (n) qn (n) x0001 input load (sl) gate count STD80 d crn gn 4.3 0.5 0.5 0.5 stdm80 d crn gn 4.3 0.6 0.6 0.6
sec asic 3-447 STD80/stdm80 lds6 d latch with active low, synchronous clear switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 lds6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.58 0.53 + 0.025*sl 0.53 + 0.024*sl 0.53 + 0.024*sl t phl 0.74 0.66 + 0.038*sl 0.66 + 0.037*sl 0.66 + 0.037*sl t r 0.19 0.10 + 0.045*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl crn to q t plh 0.60 0.55 + 0.025*sl 0.55 + 0.024*sl 0.55 + 0.024*sl t phl 0.71 0.64 + 0.038*sl 0.64 + 0.037*sl 0.64 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.06 + 0.069*sl gn to q t plh 0.70 0.65 + 0.025*sl 0.66 + 0.024*sl 0.66 + 0.024*sl t phl 0.78 0.70 + 0.038*sl 0.70 + 0.037*sl 0.70 + 0.037*sl t r 0.18 0.10 + 0.044*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.06 + 0.069*sl d to qn t plh 0.57 0.51 + 0.028*sl 0.52 + 0.024*sl 0.53 + 0.024*sl t phl 0.54 0.46 + 0.042*sl 0.47 + 0.038*sl 0.47 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.066*sl 0.08 + 0.069*sl crn to qn t plh 0.54 0.49 + 0.028*sl 0.49 + 0.024*sl 0.50 + 0.024*sl t phl 0.56 0.48 + 0.041*sl 0.49 + 0.038*sl 0.49 + 0.037*sl t r 0.21 0.11 + 0.045*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl gn to qn t plh 0.61 0.56 + 0.028*sl 0.56 + 0.024*sl 0.57 + 0.024*sl t phl 0.67 0.58 + 0.042*sl 0.59 + 0.038*sl 0.60 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.067*sl 0.08 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-448 sec asic lds6 d latch with active low, synchronous clear switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 lds6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.84 0.77 + 0.035*sl 0.77 + 0.033*sl 0.77 + 0.033*sl t phl 1.03 0.94 + 0.047*sl 0.94 + 0.044*sl 0.95 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl crn to q t plh 0.85 0.78 + 0.035*sl 0.78 + 0.033*sl 0.78 + 0.033*sl t phl 0.99 0.90 + 0.047*sl 0.91 + 0.044*sl 0.91 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.10 + 0.082*sl gn to q t plh 0.98 0.91 + 0.035*sl 0.92 + 0.033*sl 0.92 + 0.033*sl t phl 1.08 0.99 + 0.047*sl 1.00 + 0.044*sl 1.00 + 0.044*sl t r 0.26 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.082*sl d to qn t plh 0.80 0.73 + 0.038*sl 0.74 + 0.035*sl 0.75 + 0.034*sl t phl 0.77 0.66 + 0.052*sl 0.68 + 0.046*sl 0.69 + 0.044*sl t r 0.29 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.081*sl crn to qn t plh 0.77 0.69 + 0.038*sl 0.70 + 0.035*sl 0.71 + 0.034*sl t phl 0.78 0.67 + 0.052*sl 0.69 + 0.046*sl 0.70 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.15 + 0.079*sl 0.15 + 0.080*sl 0.13 + 0.081*sl gn to qn t plh 0.86 0.78 + 0.038*sl 0.79 + 0.035*sl 0.80 + 0.034*sl t phl 0.91 0.81 + 0.052*sl 0.82 + 0.046*sl 0.84 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.13 + 0.070*sl 0.12 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.13 + 0.081*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-449 STD80/stdm80 ls0/ls0d2 sr latch with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 ls0 ls0d2 ls0 ls0d2 rn sn rn sn 0.7 0.7 1.6 1.6 1.7 3.0 stdm80 ls0 ls0d2 ls0 ls0d2 rn sn rn sn 1.1 1.1 2.2 2.2 1.7 3.0 q qn rn sn sn qn q rn truth table * both q and qn outputs will remain high during rn and sn are low. however, if rn and sn go high simultaneously, the output states are unpredictable. rn sn q (n+1) qn (n+1) 00* * 1010 0101 1 1 q (n) qn (n)
STD80/stdm80 3-450 sec asic ls0/ls0d2 sr latch with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ls0 STD80 ls0d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.19 0.13 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.25 0.16 + 0.041*sl 0.17 + 0.037*sl 0.16 + 0.038*sl t r 0.32 0.25 + 0.039*sl 0.23 + 0.047*sl 0.16 + 0.054*sl t f 0.39 0.26 + 0.066*sl 0.25 + 0.072*sl 0.19 + 0.078*sl rn to q t phl 0.40 0.26 + 0.074*sl 0.27 + 0.068*sl 0.28 + 0.068*sl t f 0.35 0.19 + 0.078*sl 0.18 + 0.081*sl 0.18 + 0.082*sl sn to qn t phl 0.40 0.26 + 0.074*sl 0.27 + 0.068*sl 0.28 + 0.068*sl t f 0.35 0.19 + 0.078*sl 0.18 + 0.081*sl 0.18 + 0.082*sl rn to qn t plh 0.19 0.13 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.25 0.17 + 0.040*sl 0.17 + 0.038*sl 0.16 + 0.038*sl t r 0.32 0.24 + 0.041*sl 0.23 + 0.047*sl 0.16 + 0.054*sl t f 0.39 0.26 + 0.066*sl 0.25 + 0.072*sl 0.19 + 0.078*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.17 0.13 + 0.017*sl 0.14 + 0.014*sl 0.15 + 0.012*sl t phl 0.18 0.14 + 0.022*sl 0.15 + 0.019*sl 0.15 + 0.019*sl t r 0.28 0.24 + 0.019*sl 0.24 + 0.022*sl 0.19 + 0.027*sl t f 0.31 0.25 + 0.030*sl 0.24 + 0.034*sl 0.20 + 0.039*sl rn to q t phl 0.34 0.26 + 0.039*sl 0.26 + 0.037*sl 0.27 + 0.035*sl t f 0.25 0.17 + 0.040*sl 0.17 + 0.041*sl 0.16 + 0.042*sl sn to qn t phl 0.33 0.25 + 0.040*sl 0.26 + 0.037*sl 0.27 + 0.035*sl t f 0.25 0.17 + 0.040*sl 0.17 + 0.041*sl 0.16 + 0.042*sl rn to qn t plh 0.17 0.13 + 0.017*sl 0.14 + 0.014*sl 0.15 + 0.012*sl t phl 0.18 0.14 + 0.022*sl 0.15 + 0.019*sl 0.15 + 0.019*sl t r 0.28 0.24 + 0.019*sl 0.24 + 0.022*sl 0.19 + 0.027*sl t f 0.31 0.24 + 0.031*sl 0.24 + 0.034*sl 0.19 + 0.039*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-451 STD80/stdm80 ls0/ls0d2 sr latch with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ls0 stdm80 ls0d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.30 0.20 + 0.050*sl 0.20 + 0.050*sl 0.20 + 0.050*sl t r 0.37 0.24 + 0.067*sl 0.23 + 0.071*sl 0.21 + 0.073*sl t f 0.46 0.27 + 0.092*sl 0.26 + 0.095*sl 0.24 + 0.098*sl rn to q t phl 0.54 0.35 + 0.096*sl 0.35 + 0.094*sl 0.35 + 0.094*sl t f 0.45 0.24 + 0.104*sl 0.24 + 0.105*sl 0.23 + 0.105*sl sn to qn t phl 0.54 0.35 + 0.095*sl 0.35 + 0.094*sl 0.35 + 0.094*sl t f 0.45 0.24 + 0.104*sl 0.24 + 0.105*sl 0.24 + 0.105*sl rn to qn t plh 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.30 0.20 + 0.050*sl 0.20 + 0.049*sl 0.20 + 0.050*sl t r 0.37 0.24 + 0.067*sl 0.23 + 0.071*sl 0.21 + 0.073*sl t f 0.46 0.27 + 0.091*sl 0.26 + 0.096*sl 0.24 + 0.098*sl *g 1 sl 3 *g 2 3 sl 7 *g 3 7 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.21 0.17 + 0.020*sl 0.18 + 0.017*sl 0.18 + 0.017*sl t phl 0.23 0.17 + 0.027*sl 0.18 + 0.025*sl 0.18 + 0.025*sl t r 0.30 0.24 + 0.031*sl 0.23 + 0.034*sl 0.22 + 0.035*sl t f 0.34 0.25 + 0.044*sl 0.25 + 0.047*sl 0.24 + 0.048*sl rn to q t phl 0.44 0.34 + 0.051*sl 0.34 + 0.049*sl 0.35 + 0.049*sl t f 0.32 0.22 + 0.053*sl 0.22 + 0.054*sl 0.22 + 0.053*sl sn to qn t phl 0.44 0.34 + 0.051*sl 0.34 + 0.049*sl 0.35 + 0.049*sl t f 0.32 0.22 + 0.053*sl 0.22 + 0.053*sl 0.22 + 0.054*sl rn to qn t plh 0.21 0.17 + 0.020*sl 0.18 + 0.017*sl 0.18 + 0.017*sl t phl 0.23 0.18 + 0.026*sl 0.18 + 0.025*sl 0.18 + 0.025*sl t r 0.30 0.24 + 0.032*sl 0.23 + 0.034*sl 0.22 + 0.035*sl t f 0.34 0.25 + 0.044*sl 0.25 + 0.047*sl 0.24 + 0.048*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-452 sec asic ls1 sr latch with separate inputs logic symbol cell data schematic diagram input load (sl) gate count STD80 rn rn1 rn2 sn sn1 sn2 3.0 0.8 0.8 0.8 0.8 0.8 0.8 stdm80 rn rn1 rn2 sn sn1 sn2 3.0 0.9 0.8 0.8 0.9 0.8 0.8 q qn sn1 rn1 rn2 sn2 sn rn rn1 q qn rn rn2 sn1 sn sn2 truth table rn* = rn1 + rn2, sn* = sn1 + sn2 * both q and qn outputs will be unknown when rn (rn*) and sn (sn*) are low. rn sn rn* sn* q (n+1) qn (n+1) 00xx * * x00x* * xx00* * 0xx0* * 101x10 01x101 1x1010 x10101 1111q (n)qn (n)
sec asic 3-453 STD80/stdm80 ls1 sr latch with separate inputs switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ls1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn1 to q t plh 0.28 0.19 + 0.044*sl 0.20 + 0.041*sl 0.19 + 0.041*sl t phl 0.44 0.29 + 0.072*sl 0.29 + 0.072*sl 0.29 + 0.073*sl t r 0.53 0.37 + 0.081*sl 0.35 + 0.089*sl 0.30 + 0.095*sl t f 0.74 0.45 + 0.145*sl 0.44 + 0.150*sl 0.41 + 0.152*sl sn2 to q t plh 0.27 0.19 + 0.044*sl 0.19 + 0.041*sl 0.19 + 0.041*sl t phl 0.50 0.36 + 0.071*sl 0.36 + 0.072*sl 0.35 + 0.073*sl t r 0.52 0.36 + 0.083*sl 0.34 + 0.091*sl 0.30 + 0.095*sl t f 0.85 0.57 + 0.143*sl 0.55 + 0.150*sl 0.53 + 0.152*sl sn to q t plh 0.21 0.15 + 0.029*sl 0.16 + 0.024*sl 0.16 + 0.024*sl t phl 0.44 0.30 + 0.071*sl 0.29 + 0.072*sl 0.29 + 0.073*sl t r 0.37 0.29 + 0.040*sl 0.28 + 0.045*sl 0.21 + 0.052*sl t f 0.74 0.45 + 0.147*sl 0.44 + 0.150*sl 0.42 + 0.152*sl rn1 to q t phl 0.73 0.48 + 0.123*sl 0.49 + 0.120*sl 0.48 + 0.121*sl t f 0.75 0.43 + 0.156*sl 0.43 + 0.157*sl 0.43 + 0.158*sl rn2 to q t phl 0.72 0.47 + 0.123*sl 0.48 + 0.120*sl 0.48 + 0.121*sl t f 0.75 0.43 + 0.156*sl 0.43 + 0.157*sl 0.43 + 0.158*sl rn to q t phl 0.64 0.42 + 0.106*sl 0.44 + 0.100*sl 0.45 + 0.099*sl t f 0.73 0.42 + 0.154*sl 0.42 + 0.153*sl 0.42 + 0.154*sl sn1 to qn t phl 0.73 0.48 + 0.123*sl 0.49 + 0.120*sl 0.48 + 0.121*sl t f 0.75 0.43 + 0.156*sl 0.43 + 0.157*sl 0.43 + 0.158*sl sn2 to qn t phl 0.72 0.47 + 0.123*sl 0.48 + 0.121*sl 0.48 + 0.121*sl t f 0.75 0.43 + 0.156*sl 0.43 + 0.157*sl 0.43 + 0.158*sl sn to qn t phl 0.64 0.42 + 0.106*sl 0.44 + 0.100*sl 0.45 + 0.099*sl t f 0.73 0.42 + 0.153*sl 0.42 + 0.153*sl 0.42 + 0.154*sl rn1 to qn t plh 0.28 0.19 + 0.044*sl 0.20 + 0.041*sl 0.19 + 0.041*sl t phl 0.44 0.29 + 0.072*sl 0.29 + 0.072*sl 0.29 + 0.073*sl t r 0.53 0.37 + 0.081*sl 0.35 + 0.089*sl 0.30 + 0.095*sl t f 0.74 0.45 + 0.145*sl 0.44 + 0.150*sl 0.41 + 0.152*sl rn2 to qn t plh 0.27 0.19 + 0.044*sl 0.19 + 0.041*sl 0.19 + 0.041*sl t phl 0.50 0.36 + 0.071*sl 0.36 + 0.072*sl 0.35 + 0.073*sl t r 0.52 0.36 + 0.083*sl 0.34 + 0.091*sl 0.30 + 0.095*sl t f 0.85 0.57 + 0.143*sl 0.55 + 0.150*sl 0.53 + 0.152*sl rn to qn t plh 0.21 0.15 + 0.029*sl 0.16 + 0.024*sl 0.16 + 0.024*sl t phl 0.44 0.29 + 0.072*sl 0.29 + 0.072*sl 0.29 + 0.073*sl t r 0.37 0.29 + 0.040*sl 0.28 + 0.045*sl 0.21 + 0.052*sl t f 0.74 0.45 + 0.146*sl 0.44 + 0.150*sl 0.42 + 0.152*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-454 sec asic ls1 sr latch with separate inputs switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ls1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn1 to q t plh 0.39 0.27 + 0.064*sl 0.27 + 0.063*sl 0.27 + 0.063*sl t phl 0.58 0.38 + 0.100*sl 0.38 + 0.099*sl 0.39 + 0.098*sl t r 0.73 0.46 + 0.133*sl 0.45 + 0.136*sl 0.43 + 0.139*sl t f 0.98 0.58 + 0.199*sl 0.58 + 0.202*sl 0.58 + 0.202*sl sn2 to q t plh 0.42 0.29 + 0.064*sl 0.29 + 0.064*sl 0.29 + 0.063*sl t phl 0.67 0.47 + 0.099*sl 0.48 + 0.099*sl 0.48 + 0.098*sl t r 0.73 0.46 + 0.134*sl 0.45 + 0.137*sl 0.44 + 0.139*sl t f 1.12 0.73 + 0.199*sl 0.72 + 0.201*sl 0.72 + 0.201*sl sn to q t plh 0.27 0.21 + 0.034*sl 0.21 + 0.033*sl 0.21 + 0.033*sl t phl 0.60 0.40 + 0.100*sl 0.40 + 0.099*sl 0.41 + 0.099*sl t r 0.43 0.30 + 0.064*sl 0.29 + 0.068*sl 0.27 + 0.070*sl t f 0.99 0.59 + 0.198*sl 0.58 + 0.201*sl 0.58 + 0.202*sl rn1 to q t phl 1.03 0.69 + 0.173*sl 0.69 + 0.172*sl 0.69 + 0.172*sl t f 1.02 0.60 + 0.208*sl 0.60 + 0.208*sl 0.60 + 0.208*sl rn2 to q t phl 1.06 0.71 + 0.173*sl 0.71 + 0.172*sl 0.71 + 0.172*sl t f 1.02 0.60 + 0.208*sl 0.60 + 0.208*sl 0.60 + 0.208*sl rn to q t phl 0.90 0.62 + 0.139*sl 0.62 + 0.137*sl 0.63 + 0.137*sl t f 0.99 0.59 + 0.203*sl 0.58 + 0.204*sl 0.59 + 0.204*sl sn1 to qn t phl 1.03 0.69 + 0.173*sl 0.69 + 0.172*sl 0.69 + 0.172*sl t f 1.02 0.60 + 0.208*sl 0.60 + 0.208*sl 0.60 + 0.208*sl sn2 to qn t phl 1.06 0.71 + 0.173*sl 0.71 + 0.172*sl 0.71 + 0.172*sl t f 1.02 0.60 + 0.208*sl 0.60 + 0.208*sl 0.60 + 0.208*sl sn to qn t phl 0.89 0.62 + 0.139*sl 0.62 + 0.137*sl 0.62 + 0.137*sl t f 0.99 0.58 + 0.204*sl 0.58 + 0.204*sl 0.59 + 0.204*sl rn1 to qn t plh 0.39 0.27 + 0.064*sl 0.27 + 0.063*sl 0.27 + 0.063*sl t phl 0.58 0.38 + 0.100*sl 0.38 + 0.099*sl 0.39 + 0.098*sl t r 0.73 0.46 + 0.133*sl 0.45 + 0.136*sl 0.43 + 0.139*sl t f 0.98 0.58 + 0.199*sl 0.58 + 0.202*sl 0.58 + 0.202*sl rn2 to qn t plh 0.42 0.29 + 0.064*sl 0.29 + 0.063*sl 0.29 + 0.063*sl t phl 0.67 0.47 + 0.099*sl 0.48 + 0.099*sl 0.48 + 0.098*sl t r 0.73 0.46 + 0.134*sl 0.45 + 0.137*sl 0.44 + 0.139*sl t f 1.12 0.73 + 0.199*sl 0.72 + 0.201*sl 0.72 + 0.201*sl rn to qn t plh 0.27 0.21 + 0.034*sl 0.21 + 0.033*sl 0.21 + 0.033*sl t phl 0.60 0.40 + 0.100*sl 0.40 + 0.099*sl 0.41 + 0.099*sl t r 0.43 0.30 + 0.065*sl 0.29 + 0.068*sl 0.27 + 0.070*sl t f 0.99 0.59 + 0.198*sl 0.58 + 0.201*sl 0.58 + 0.202*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-455 STD80/stdm80 ls2 sr latch with common inputs logic symbol cell data schematic diagram input load (sl) gate count STD80 gn rn sn 4.3 1.2 0.4 0.4 stdm80 gn rn sn 4.3 1.4 0.6 0.6 gn q qn rn sn sn qn q rn gn truth table * both q and qn outputs will be unknown when gn, rn, and sn are low. however, if gn goes high, or rn and sn go high simultaneously, the output states are unpredictable. gn rn sn q (n+1) qn (n+1) 1 x x q (n) qn (n) 0 1 1 q (n) qn (n) 00101 01010 000* *
STD80/stdm80 3-456 sec asic ls2 sr latch with common inputs switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ls2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.48 0.43 + 0.025*sl 0.43 + 0.025*sl 0.43 + 0.025*sl t phl 0.41 0.33 + 0.039*sl 0.33 + 0.039*sl 0.34 + 0.039*sl t r 0.25 0.15 + 0.049*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.35 0.20 + 0.074*sl 0.19 + 0.076*sl 0.18 + 0.078*sl rn to q t phl 0.70 0.56 + 0.069*sl 0.56 + 0.068*sl 0.56 + 0.068*sl t f 0.35 0.19 + 0.082*sl 0.19 + 0.082*sl 0.18 + 0.082*sl gn to q t plh 0.48 0.42 + 0.026*sl 0.43 + 0.025*sl 0.43 + 0.025*sl t phl 0.70 0.56 + 0.070*sl 0.56 + 0.068*sl 0.56 + 0.068*sl t r 0.25 0.16 + 0.047*sl 0.15 + 0.051*sl 0.14 + 0.052*sl t f 0.35 0.19 + 0.081*sl 0.19 + 0.082*sl 0.18 + 0.082*sl sn to qn t phl 0.70 0.56 + 0.069*sl 0.56 + 0.068*sl 0.56 + 0.068*sl t f 0.35 0.19 + 0.081*sl 0.19 + 0.082*sl 0.18 + 0.082*sl rn to qn t plh 0.48 0.43 + 0.025*sl 0.43 + 0.025*sl 0.43 + 0.025*sl t phl 0.41 0.33 + 0.040*sl 0.34 + 0.039*sl 0.34 + 0.039*sl t r 0.25 0.15 + 0.049*sl 0.14 + 0.052*sl 0.13 + 0.054*sl t f 0.35 0.20 + 0.074*sl 0.19 + 0.076*sl 0.18 + 0.078*sl gn to qn t plh 0.48 0.43 + 0.025*sl 0.43 + 0.025*sl 0.43 + 0.025*sl t phl 0.69 0.56 + 0.069*sl 0.56 + 0.068*sl 0.56 + 0.068*sl t r 0.25 0.16 + 0.047*sl 0.15 + 0.051*sl 0.14 + 0.052*sl t f 0.35 0.19 + 0.081*sl 0.19 + 0.082*sl 0.18 + 0.082*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
sec asic 3-457 STD80/stdm80 ls2 sr latch with common inputs switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ls2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.65 0.58 + 0.036*sl 0.59 + 0.035*sl 0.58 + 0.035*sl t phl 0.60 0.49 + 0.052*sl 0.50 + 0.050*sl 0.50 + 0.050*sl t r 0.35 0.20 + 0.073*sl 0.20 + 0.074*sl 0.19 + 0.075*sl t f 0.46 0.27 + 0.095*sl 0.27 + 0.097*sl 0.26 + 0.098*sl rn to q t phl 0.96 0.77 + 0.095*sl 0.77 + 0.094*sl 0.77 + 0.094*sl t f 0.46 0.25 + 0.105*sl 0.25 + 0.105*sl 0.25 + 0.105*sl gn to q t plh 0.67 0.60 + 0.036*sl 0.60 + 0.035*sl 0.60 + 0.035*sl t phl 0.98 0.79 + 0.095*sl 0.79 + 0.094*sl 0.79 + 0.094*sl t r 0.36 0.22 + 0.071*sl 0.21 + 0.073*sl 0.20 + 0.074*sl t f 0.46 0.25 + 0.106*sl 0.25 + 0.105*sl 0.25 + 0.105*sl sn to qn t phl 0.96 0.76 + 0.095*sl 0.77 + 0.094*sl 0.77 + 0.094*sl t f 0.46 0.25 + 0.105*sl 0.25 + 0.105*sl 0.25 + 0.105*sl rn to qn t plh 0.66 0.58 + 0.036*sl 0.59 + 0.035*sl 0.59 + 0.035*sl t phl 0.60 0.50 + 0.052*sl 0.50 + 0.050*sl 0.51 + 0.050*sl t r 0.35 0.21 + 0.072*sl 0.20 + 0.074*sl 0.19 + 0.075*sl t f 0.46 0.27 + 0.095*sl 0.27 + 0.097*sl 0.26 + 0.099*sl gn to qn t plh 0.67 0.60 + 0.036*sl 0.60 + 0.035*sl 0.61 + 0.035*sl t phl 0.97 0.78 + 0.095*sl 0.79 + 0.094*sl 0.79 + 0.094*sl t r 0.36 0.22 + 0.071*sl 0.21 + 0.074*sl 0.21 + 0.074*sl t f 0.46 0.25 + 0.106*sl 0.25 + 0.105*sl 0.25 + 0.105*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
STD80/stdm80 3-458 sec asic bus holder cell list logic symbol cell name function description busholder bus holder y cell data input load (sl) gate count STD80 y 1.3 3.8 stdm80 y 1.3 3.4
sec asic 3-459 STD80/stdm80 internal clock drivers cell list logic symbol cell data cell name function description STD80 ck2 internal clock driver cmos 2ma ck4 internal clock driver cmos 4ma ck8 internal clock driver cmos 8ma ck12 internal clock driver cmos 12ma stdm80 ck2 internal clock driver cmos 2ma ck4 internal clock driver cmos 4ma ck6 internal clock driver cmos 6ma ck8 internal clock driver cmos 8ma input load (sl) gate count STD80 ck2 ck4 ck8 ck12 ck2 ck4 ck8 ck12 aaaa 3.1 3.1 5.5 5.5 1.0 1.0 1.0 1.0 stdm80 ck2 ck4 ck6 ck8 ck2 ck4 ck6 ck8 aaaa 3.5 3.5 6.1 6.1 1.0 1.0 1.0 1.0 a y truth table ay 00 11
STD80/stdm80 3-460 sec asic ck2/ck4/ck8/ck12 internal clock driver cmos 2/4/8/12ma switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) STD80 ck2 STD80 ck4 STD80 ck8 STD80 ck12 path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.20 + 0.005*sl 0.20 + 0.005*sl 0.20 + 0.005*sl t phl 0.60 0.18 + 0.005*sl 0.18 + 0.005*sl 0.18 + 0.005*sl t r 1.07 0.08 + 0.012*sl 0.07 + 0.012*sl 0.06 + 0.012*sl t f 0.82 0.06 + 0.009*sl 0.06 + 0.009*sl 0.05 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* a to y t plh 0.71 0.26 + 0.003*sl 0.26 + 0.003*sl 0.26 + 0.003*sl t phl 0.64 0.23 + 0.003*sl 0.24 + 0.002*sl 0.23 + 0.003*sl t r 1.06 0.09 + 0.006*sl 0.08 + 0.006*sl 0.08 + 0.006*sl t f 0.82 0.08 + 0.004*sl 0.07 + 0.005*sl 0.06 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* a to y t plh 0.70 0.25 + 0.001*sl 0.25 + 0.001*sl 0.25 + 0.001*sl t phl 0.67 0.26 + 0.001*sl 0.26 + 0.001*sl 0.26 + 0.001*sl t r 1.05 0.09 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.003*sl t f 0.82 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* a to y t plh 0.75 0.31 + 0.001*sl 0.31 + 0.001*sl 0.31 + 0.001*sl t phl 0.72 0.31 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t r 1.06 0.12 + 0.002*sl 0.10 + 0.002*sl 0.09 + 0.002*sl t f 0.83 0.11 + 0.001*sl 0.10 + 0.001*sl 0.09 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 3-461 STD80/stdm80 ck2/ck4/ck6/ck8 internal clock driver cmos 2/4/6/8ma switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) stdm80 ck2 stdm80 ck4 stdm80 ck6 stdm80 ck8 path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* a to y t plh 1.13 0.28 + 0.004*sl 0.28 + 0.004*sl 0.28 + 0.004*sl t phl 0.93 0.29 + 0.003*sl 0.29 + 0.003*sl 0.29 + 0.003*sl t r 1.95 0.13 + 0.009*sl 0.10 + 0.010*sl 0.09 + 0.010*sl t f 1.30 0.10 + 0.006*sl 0.09 + 0.006*sl 0.09 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* a to y t plh 1.23 0.39 + 0.002*sl 0.39 + 0.002*sl 0.39 + 0.002*sl t phl 1.03 0.39 + 0.002*sl 0.40 + 0.002*sl 0.40 + 0.002*sl t r 1.95 0.17 + 0.005*sl 0.13 + 0.005*sl 0.13 + 0.005*sl t f 1.31 0.16 + 0.003*sl 0.13 + 0.003*sl 0.10 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* a to y t plh 1.17 0.33 + 0.001*sl 0.33 + 0.001*sl 0.33 + 0.001*sl t phl 1.02 0.38 + 0.001*sl 0.38 + 0.001*sl 0.39 + 0.001*sl t r 1.95 0.14 + 0.003*sl 0.12 + 0.003*sl 0.11 + 0.003*sl t f 1.32 0.12 + 0.002*sl 0.13 + 0.002*sl 0.13 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* a to y t plh 1.22 0.38 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t phl 1.08 0.43 + 0.001*sl 0.44 + 0.001*sl 0.45 + 0.001*sl t r 1.95 0.17 + 0.002*sl 0.14 + 0.002*sl 0.13 + 0.002*sl t f 1.33 0.15 + 0.002*sl 0.16 + 0.002*sl 0.15 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
STD80/stdm80 3-462 sec asic decoders cell list cell name function description dc4 2 > 4 non-inverting decoder dc4i 2 > 4 inverting decoder dc8i 3 > 8 inverting decoder
sec asic 3-463 STD80/stdm80 dc4 2 > 4 non-inverting decoder logic symbol schematic diagram s0 s1 y0 y1 y2 y3 y0 y1 y2 y3 s0 s1 truth table cell data s1 s0 y0 y1 y2 y3 001000 010100 100010 110001 input load (sl) gate count STD80 s0 s1 6.3 1.9 1.7 stdm80 s0 s1 6.3 2.4 2.2
STD80/stdm80 3-464 sec asic dc4 2 > 4 non-inverting decoder switching characteristics (typical process, 25c , 5v, t r /t f = 0.44ns, sl: standard load) STD80 dc4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to y0 t plh 0.44 0.38 + 0.029*sl 0.39 + 0.025*sl 0.40 + 0.024*sl t phl 0.45 0.37 + 0.039*sl 0.37 + 0.037*sl 0.37 + 0.037*sl t r 0.20 0.11 + 0.047*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.067*sl 0.06 + 0.069*sl s1 to y0 t plh 0.43 0.37 + 0.029*sl 0.38 + 0.025*sl 0.39 + 0.024*sl t phl 0.41 0.33 + 0.040*sl 0.33 + 0.037*sl 0.34 + 0.037*sl t r 0.20 0.10 + 0.047*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.08 + 0.068*sl 0.06 + 0.069*sl s0 to y1 t plh 0.26 0.20 + 0.029*sl 0.21 + 0.025*sl 0.22 + 0.024*sl t phl 0.34 0.26 + 0.039*sl 0.26 + 0.037*sl 0.26 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl s1 to y1 t plh 0.43 0.37 + 0.029*sl 0.38 + 0.025*sl 0.39 + 0.024*sl t phl 0.41 0.33 + 0.039*sl 0.34 + 0.037*sl 0.34 + 0.037*sl t r 0.20 0.11 + 0.047*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.066*sl 0.08 + 0.067*sl 0.07 + 0.069*sl s0 to y2 t plh 0.44 0.38 + 0.029*sl 0.39 + 0.024*sl 0.40 + 0.024*sl t phl 0.45 0.37 + 0.039*sl 0.37 + 0.037*sl 0.38 + 0.037*sl t r 0.20 0.10 + 0.048*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.062*sl 0.08 + 0.067*sl 0.06 + 0.069*sl s1 to y2 t plh 0.28 0.22 + 0.029*sl 0.23 + 0.024*sl 0.24 + 0.024*sl t phl 0.31 0.24 + 0.039*sl 0.24 + 0.037*sl 0.24 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl s0 to y3 t plh 0.26 0.20 + 0.029*sl 0.21 + 0.025*sl 0.22 + 0.024*sl t phl 0.34 0.26 + 0.039*sl 0.27 + 0.037*sl 0.27 + 0.037*sl t r 0.21 0.11 + 0.047*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl s1 to y3 t plh 0.28 0.22 + 0.029*sl 0.23 + 0.024*sl 0.24 + 0.024*sl t phl 0.31 0.24 + 0.039*sl 0.24 + 0.037*sl 0.24 + 0.037*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.10 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-465 STD80/stdm80 dc4 2 > 4 non-inverting decoder switching characteristics (typical process, 25c , 3.3v, tr/tf = 0.39ns, sl: standard load) stdm80 dc4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to y0 t plh 0.60 0.52 + 0.039*sl 0.53 + 0.035*sl 0.54 + 0.033*sl t phl 0.59 0.49 + 0.048*sl 0.50 + 0.045*sl 0.51 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.11 + 0.081*sl 0.10 + 0.082*sl s1 to y0 t plh 0.58 0.50 + 0.039*sl 0.51 + 0.035*sl 0.52 + 0.033*sl t phl 0.54 0.44 + 0.048*sl 0.45 + 0.045*sl 0.46 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.27 0.11 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl s0 to y1 t plh 0.36 0.28 + 0.039*sl 0.29 + 0.035*sl 0.30 + 0.034*sl t phl 0.43 0.34 + 0.048*sl 0.35 + 0.045*sl 0.35 + 0.044*sl t r 0.28 0.15 + 0.068*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.081*sl 0.11 + 0.083*sl s1 to y1 t plh 0.58 0.50 + 0.039*sl 0.51 + 0.035*sl 0.52 + 0.033*sl t phl 0.54 0.45 + 0.048*sl 0.45 + 0.045*sl 0.46 + 0.044*sl t r 0.28 0.15 + 0.068*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl s0 to y2 t plh 0.60 0.52 + 0.040*sl 0.53 + 0.035*sl 0.54 + 0.034*sl t phl 0.59 0.49 + 0.048*sl 0.50 + 0.045*sl 0.51 + 0.044*sl t r 0.28 0.14 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.28 0.12 + 0.078*sl 0.12 + 0.081*sl 0.10 + 0.083*sl s1 to y2 t plh 0.37 0.29 + 0.039*sl 0.30 + 0.035*sl 0.31 + 0.033*sl t phl 0.41 0.31 + 0.048*sl 0.32 + 0.045*sl 0.33 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl s0 to y3 t plh 0.36 0.28 + 0.040*sl 0.29 + 0.035*sl 0.30 + 0.034*sl t phl 0.43 0.34 + 0.049*sl 0.35 + 0.045*sl 0.35 + 0.044*sl t r 0.28 0.15 + 0.067*sl 0.14 + 0.070*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.081*sl 0.10 + 0.083*sl s1 to y3 t plh 0.37 0.29 + 0.039*sl 0.30 + 0.035*sl 0.31 + 0.033*sl t phl 0.41 0.31 + 0.048*sl 0.32 + 0.045*sl 0.33 + 0.044*sl t r 0.28 0.14 + 0.068*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.11 + 0.081*sl 0.10 + 0.083*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-466 sec asic dc4i 2 > 4 inverting decoder logic symbol schematic diagram s0 s1 yn0 yn1 yn2 yn3 yn0 yn1 yn2 yn3 s0 s1 truth table cell data s1 s0 yn0 yn1 yn2 yn3 000111 011011 101101 111110 input load (sl) gate count STD80 s0 s1 4.3 2.3 2.5 stdm80 s0 s1 4.3 2.8 2.9
sec asic 3-467 STD80/stdm80 dc4i 2 > 4 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 dc4i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.30 0.24 + 0.029*sl 0.25 + 0.025*sl 0.25 + 0.025*sl t phl 0.40 0.31 + 0.042*sl 0.32 + 0.039*sl 0.32 + 0.039*sl t r 0.22 0.13 + 0.046*sl 0.12 + 0.051*sl 0.08 + 0.054*sl t f 0.28 0.13 + 0.072*sl 0.13 + 0.075*sl 0.10 + 0.078*sl s1 to yn0 t plh 0.31 0.25 + 0.028*sl 0.26 + 0.025*sl 0.26 + 0.025*sl t phl 0.38 0.30 + 0.039*sl 0.31 + 0.038*sl 0.30 + 0.039*sl t r 0.24 0.15 + 0.044*sl 0.14 + 0.050*sl 0.10 + 0.054*sl t f 0.27 0.13 + 0.070*sl 0.12 + 0.075*sl 0.09 + 0.078*sl s0 to yn1 t plh 0.16 0.09 + 0.036*sl 0.11 + 0.026*sl 0.12 + 0.025*sl t phl 0.21 0.12 + 0.044*sl 0.13 + 0.038*sl 0.13 + 0.038*sl t r 0.28 0.19 + 0.043*sl 0.19 + 0.046*sl 0.11 + 0.054*sl t f 0.32 0.20 + 0.062*sl 0.18 + 0.071*sl 0.11 + 0.078*sl s1 to yn1 t plh 0.31 0.25 + 0.027*sl 0.26 + 0.025*sl 0.26 + 0.025*sl t phl 0.38 0.30 + 0.040*sl 0.31 + 0.038*sl 0.31 + 0.039*sl t r 0.24 0.15 + 0.043*sl 0.14 + 0.050*sl 0.10 + 0.054*sl t f 0.27 0.13 + 0.070*sl 0.12 + 0.075*sl 0.10 + 0.078*sl s0 to yn2 t plh 0.30 0.24 + 0.029*sl 0.25 + 0.025*sl 0.25 + 0.025*sl t phl 0.40 0.31 + 0.041*sl 0.32 + 0.039*sl 0.32 + 0.039*sl t r 0.22 0.13 + 0.043*sl 0.12 + 0.051*sl 0.08 + 0.054*sl t f 0.28 0.14 + 0.071*sl 0.13 + 0.075*sl 0.10 + 0.078*sl s1 to yn2 t plh 0.18 0.11 + 0.033*sl 0.13 + 0.025*sl 0.13 + 0.025*sl t phl 0.18 0.10 + 0.041*sl 0.11 + 0.038*sl 0.10 + 0.038*sl t r 0.30 0.22 + 0.041*sl 0.21 + 0.046*sl 0.13 + 0.054*sl t f 0.31 0.18 + 0.063*sl 0.16 + 0.071*sl 0.10 + 0.078*sl s0 to yn3 t plh 0.16 0.09 + 0.036*sl 0.11 + 0.026*sl 0.12 + 0.025*sl t phl 0.21 0.12 + 0.044*sl 0.13 + 0.038*sl 0.12 + 0.038*sl t r 0.28 0.19 + 0.044*sl 0.19 + 0.046*sl 0.11 + 0.054*sl t f 0.32 0.19 + 0.063*sl 0.18 + 0.071*sl 0.11 + 0.078*sl s1 to yn3 t plh 0.18 0.11 + 0.032*sl 0.13 + 0.025*sl 0.13 + 0.025*sl t phl 0.18 0.10 + 0.041*sl 0.11 + 0.038*sl 0.10 + 0.038*sl t r 0.30 0.22 + 0.039*sl 0.21 + 0.046*sl 0.13 + 0.054*sl t f 0.31 0.18 + 0.063*sl 0.16 + 0.072*sl 0.10 + 0.078*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-468 sec asic dc4i 2 > 4 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 dc4i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.39 0.31 + 0.039*sl 0.32 + 0.036*sl 0.32 + 0.035*sl t phl 0.52 0.41 + 0.055*sl 0.42 + 0.051*sl 0.43 + 0.050*sl t r 0.29 0.15 + 0.071*sl 0.14 + 0.073*sl 0.13 + 0.074*sl t f 0.37 0.18 + 0.096*sl 0.18 + 0.095*sl 0.16 + 0.098*sl s1 to yn0 t plh 0.40 0.32 + 0.038*sl 0.33 + 0.035*sl 0.33 + 0.035*sl t phl 0.50 0.39 + 0.053*sl 0.40 + 0.050*sl 0.41 + 0.050*sl t r 0.31 0.17 + 0.070*sl 0.16 + 0.072*sl 0.15 + 0.074*sl t f 0.35 0.17 + 0.094*sl 0.16 + 0.096*sl 0.15 + 0.098*sl s0 to yn1 t plh 0.21 0.13 + 0.041*sl 0.15 + 0.034*sl 0.14 + 0.035*sl t phl 0.25 0.15 + 0.052*sl 0.15 + 0.049*sl 0.15 + 0.050*sl t r 0.31 0.18 + 0.064*sl 0.16 + 0.070*sl 0.14 + 0.073*sl t f 0.36 0.18 + 0.091*sl 0.17 + 0.094*sl 0.14 + 0.098*sl s1 to yn1 t plh 0.40 0.32 + 0.038*sl 0.33 + 0.035*sl 0.33 + 0.035*sl t phl 0.50 0.39 + 0.054*sl 0.40 + 0.050*sl 0.41 + 0.050*sl t r 0.31 0.17 + 0.070*sl 0.17 + 0.072*sl 0.15 + 0.075*sl t f 0.35 0.16 + 0.095*sl 0.16 + 0.096*sl 0.15 + 0.098*sl s0 to yn2 t plh 0.39 0.31 + 0.039*sl 0.32 + 0.036*sl 0.32 + 0.035*sl t phl 0.52 0.41 + 0.055*sl 0.42 + 0.051*sl 0.43 + 0.050*sl t r 0.29 0.15 + 0.070*sl 0.14 + 0.073*sl 0.13 + 0.074*sl t f 0.37 0.18 + 0.095*sl 0.18 + 0.096*sl 0.16 + 0.098*sl s1 to yn2 t plh 0.22 0.15 + 0.038*sl 0.16 + 0.034*sl 0.16 + 0.035*sl t phl 0.24 0.13 + 0.053*sl 0.14 + 0.049*sl 0.14 + 0.049*sl t r 0.33 0.21 + 0.062*sl 0.19 + 0.070*sl 0.16 + 0.073*sl t f 0.35 0.17 + 0.091*sl 0.16 + 0.095*sl 0.14 + 0.098*sl s0 to yn3 t plh 0.21 0.13 + 0.040*sl 0.14 + 0.035*sl 0.14 + 0.035*sl t phl 0.25 0.15 + 0.052*sl 0.15 + 0.049*sl 0.15 + 0.050*sl t r 0.31 0.18 + 0.064*sl 0.16 + 0.070*sl 0.14 + 0.073*sl t f 0.36 0.18 + 0.091*sl 0.17 + 0.095*sl 0.14 + 0.098*sl s1 to yn3 t plh 0.22 0.15 + 0.038*sl 0.16 + 0.034*sl 0.16 + 0.035*sl t phl 0.24 0.13 + 0.052*sl 0.14 + 0.050*sl 0.14 + 0.050*sl t r 0.33 0.21 + 0.063*sl 0.19 + 0.070*sl 0.16 + 0.073*sl t f 0.35 0.16 + 0.093*sl 0.15 + 0.096*sl 0.14 + 0.098*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-469 STD80/stdm80 dc8i 3 > 8 inverting decoder logic symbol schematic diagram s0 s2 yn0 yn2 yn4 yn6 s1 yn1 yn3 yn5 yn7 yn0 yn1 yn2 yn3 s2 s0 yn4 yn5 yn6 yn7 s1 truth table cell data s0 s1 s2 yn 0 yn 1 yn 2 yn 3 yn 4 yn 5 yn 6 yn 7 00001111111 10010111111 01011011111 11011101111 00111110111 10111111011 01111111101 11111111110 input load (sl) gate count STD80 s0 s1 s2 11.0 5.2 4.8 5.2 stdm80 s0 s1 s2 11.0 4.9 4.9 5.2
STD80/stdm80 3-470 sec asic dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.43 0.37 + 0.030*sl 0.38 + 0.026*sl 0.39 + 0.025*sl t phl 0.58 0.48 + 0.053*sl 0.48 + 0.051*sl 0.48 + 0.051*sl t r 0.31 0.22 + 0.046*sl 0.21 + 0.049*sl 0.17 + 0.054*sl t f 0.46 0.26 + 0.097*sl 0.25 + 0.104*sl 0.21 + 0.107*sl s1 to yn0 t plh 0.40 0.34 + 0.031*sl 0.35 + 0.026*sl 0.37 + 0.025*sl t phl 0.58 0.47 + 0.053*sl 0.48 + 0.051*sl 0.48 + 0.051*sl t r 0.29 0.19 + 0.045*sl 0.19 + 0.050*sl 0.14 + 0.054*sl t f 0.46 0.26 + 0.102*sl 0.26 + 0.103*sl 0.21 + 0.107*sl s2 to yn0 t plh 0.43 0.37 + 0.029*sl 0.38 + 0.026*sl 0.39 + 0.025*sl t phl 0.56 0.46 + 0.050*sl 0.46 + 0.050*sl 0.45 + 0.051*sl t r 0.33 0.24 + 0.045*sl 0.23 + 0.048*sl 0.18 + 0.054*sl t f 0.44 0.25 + 0.098*sl 0.24 + 0.104*sl 0.21 + 0.107*sl s0 to yn1 t plh 0.19 0.13 + 0.032*sl 0.14 + 0.025*sl 0.15 + 0.025*sl t phl 0.28 0.17 + 0.052*sl 0.18 + 0.050*sl 0.17 + 0.051*sl t r 0.33 0.25 + 0.039*sl 0.24 + 0.047*sl 0.17 + 0.054*sl t f 0.46 0.27 + 0.097*sl 0.26 + 0.102*sl 0.21 + 0.107*sl s1 to yn1 t plh 0.40 0.34 + 0.031*sl 0.35 + 0.026*sl 0.37 + 0.025*sl t phl 0.58 0.47 + 0.054*sl 0.48 + 0.051*sl 0.48 + 0.051*sl t r 0.28 0.19 + 0.046*sl 0.19 + 0.050*sl 0.14 + 0.054*sl t f 0.46 0.26 + 0.101*sl 0.26 + 0.103*sl 0.22 + 0.107*sl s2 to yn1 t plh 0.43 0.37 + 0.029*sl 0.38 + 0.026*sl 0.39 + 0.025*sl t phl 0.56 0.46 + 0.052*sl 0.46 + 0.050*sl 0.45 + 0.051*sl t r 0.33 0.24 + 0.045*sl 0.23 + 0.049*sl 0.18 + 0.054*sl t f 0.45 0.25 + 0.099*sl 0.24 + 0.104*sl 0.21 + 0.107*sl s0 to yn2 t plh 0.44 0.38 + 0.030*sl 0.38 + 0.026*sl 0.40 + 0.025*sl t phl 0.58 0.48 + 0.053*sl 0.48 + 0.051*sl 0.48 + 0.051*sl t r 0.31 0.22 + 0.045*sl 0.21 + 0.049*sl 0.16 + 0.054*sl t f 0.45 0.26 + 0.097*sl 0.24 + 0.103*sl 0.20 + 0.107*sl s1 to yn2 t plh 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.26 0.15 + 0.051*sl 0.16 + 0.050*sl 0.15 + 0.051*sl t r 0.35 0.27 + 0.040*sl 0.26 + 0.046*sl 0.18 + 0.054*sl t f 0.44 0.25 + 0.097*sl 0.23 + 0.103*sl 0.20 + 0.107*sl s2 to yn2 t plh 0.41 0.35 + 0.032*sl 0.36 + 0.026*sl 0.38 + 0.025*sl t phl 0.58 0.48 + 0.054*sl 0.48 + 0.051*sl 0.48 + 0.051*sl t r 0.28 0.19 + 0.048*sl 0.19 + 0.049*sl 0.14 + 0.054*sl t f 0.46 0.26 + 0.100*sl 0.25 + 0.103*sl 0.21 + 0.107*sl s0 to yn3 t plh 0.19 0.12 + 0.033*sl 0.14 + 0.025*sl 0.15 + 0.025*sl t phl 0.27 0.17 + 0.052*sl 0.17 + 0.050*sl 0.17 + 0.051*sl t r 0.33 0.25 + 0.039*sl 0.23 + 0.047*sl 0.16 + 0.054*sl t f 0.45 0.26 + 0.095*sl 0.24 + 0.102*sl 0.20 + 0.107*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-471 STD80/stdm80 dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s1 to yn3 t plh 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.26 0.16 + 0.051*sl 0.16 + 0.050*sl 0.15 + 0.051*sl t r 0.35 0.27 + 0.040*sl 0.26 + 0.046*sl 0.18 + 0.054*sl t f 0.44 0.24 + 0.098*sl 0.23 + 0.104*sl 0.20 + 0.107*sl s2 to yn3 t plh 0.41 0.34 + 0.034*sl 0.36 + 0.026*sl 0.38 + 0.025*sl t phl 0.58 0.48 + 0.054*sl 0.48 + 0.051*sl 0.48 + 0.051*sl t r 0.29 0.19 + 0.048*sl 0.19 + 0.049*sl 0.14 + 0.054*sl t f 0.46 0.26 + 0.100*sl 0.25 + 0.103*sl 0.21 + 0.107*sl s0 to yn4 t plh 0.44 0.38 + 0.031*sl 0.39 + 0.026*sl 0.40 + 0.025*sl t phl 0.59 0.48 + 0.053*sl 0.48 + 0.051*sl 0.48 + 0.051*sl t r 0.31 0.22 + 0.046*sl 0.21 + 0.049*sl 0.16 + 0.054*sl t f 0.45 0.26 + 0.099*sl 0.25 + 0.103*sl 0.21 + 0.107*sl s1 to yn4 t plh 0.40 0.34 + 0.032*sl 0.35 + 0.026*sl 0.36 + 0.025*sl t phl 0.58 0.47 + 0.053*sl 0.47 + 0.051*sl 0.47 + 0.051*sl t r 0.28 0.19 + 0.046*sl 0.18 + 0.049*sl 0.14 + 0.054*sl t f 0.45 0.25 + 0.099*sl 0.25 + 0.103*sl 0.21 + 0.107*sl s2 to yn4 t plh 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.26 0.16 + 0.052*sl 0.16 + 0.050*sl 0.15 + 0.051*sl t r 0.35 0.27 + 0.039*sl 0.26 + 0.046*sl 0.18 + 0.054*sl t f 0.44 0.25 + 0.097*sl 0.24 + 0.102*sl 0.19 + 0.107*sl s0 to yn5 t plh 0.19 0.12 + 0.033*sl 0.14 + 0.025*sl 0.15 + 0.025*sl t phl 0.27 0.17 + 0.052*sl 0.17 + 0.050*sl 0.17 + 0.051*sl t r 0.33 0.25 + 0.040*sl 0.23 + 0.046*sl 0.16 + 0.054*sl t f 0.45 0.26 + 0.095*sl 0.24 + 0.103*sl 0.20 + 0.107*sl s1 to yn5 t plh 0.40 0.34 + 0.032*sl 0.35 + 0.026*sl 0.36 + 0.025*sl t phl 0.58 0.47 + 0.054*sl 0.48 + 0.051*sl 0.47 + 0.051*sl t r 0.28 0.19 + 0.046*sl 0.18 + 0.049*sl 0.14 + 0.054*sl t f 0.46 0.25 + 0.101*sl 0.25 + 0.103*sl 0.21 + 0.107*sl s2 to yn5 t plh 0.20 0.14 + 0.030*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.26 0.16 + 0.051*sl 0.16 + 0.050*sl 0.15 + 0.051*sl t r 0.35 0.27 + 0.039*sl 0.26 + 0.046*sl 0.18 + 0.054*sl t f 0.44 0.25 + 0.096*sl 0.23 + 0.103*sl 0.19 + 0.107*sl s0 to yn6 t plh 0.45 0.38 + 0.031*sl 0.39 + 0.026*sl 0.41 + 0.025*sl t phl 0.59 0.49 + 0.052*sl 0.49 + 0.051*sl 0.49 + 0.051*sl t r 0.31 0.22 + 0.047*sl 0.22 + 0.048*sl 0.16 + 0.054*sl t f 0.45 0.26 + 0.096*sl 0.25 + 0.103*sl 0.21 + 0.107*sl s1 to yn6 t plh 0.17 0.10 + 0.034*sl 0.12 + 0.026*sl 0.13 + 0.025*sl t phl 0.28 0.18 + 0.051*sl 0.18 + 0.050*sl 0.17 + 0.051*sl t r 0.31 0.23 + 0.039*sl 0.21 + 0.047*sl 0.14 + 0.054*sl t f 0.45 0.26 + 0.095*sl 0.24 + 0.102*sl 0.20 + 0.107*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-472 sec asic dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 dc8i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to yn6 t plh 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.26 0.15 + 0.051*sl 0.16 + 0.050*sl 0.15 + 0.051*sl t r 0.35 0.27 + 0.039*sl 0.26 + 0.046*sl 0.18 + 0.054*sl t f 0.44 0.24 + 0.097*sl 0.23 + 0.103*sl 0.20 + 0.107*sl s0 to yn7 t plh 0.19 0.13 + 0.032*sl 0.14 + 0.025*sl 0.14 + 0.025*sl t phl 0.27 0.17 + 0.050*sl 0.17 + 0.050*sl 0.16 + 0.051*sl t r 0.33 0.25 + 0.040*sl 0.23 + 0.046*sl 0.16 + 0.054*sl t f 0.44 0.25 + 0.095*sl 0.24 + 0.103*sl 0.20 + 0.107*sl s1 to yn7 t plh 0.17 0.11 + 0.034*sl 0.12 + 0.026*sl 0.14 + 0.025*sl t phl 0.28 0.18 + 0.051*sl 0.18 + 0.050*sl 0.17 + 0.051*sl t r 0.31 0.23 + 0.041*sl 0.21 + 0.046*sl 0.14 + 0.054*sl t f 0.45 0.26 + 0.095*sl 0.25 + 0.102*sl 0.20 + 0.107*sl s2 to yn7 t plh 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t phl 0.26 0.16 + 0.051*sl 0.16 + 0.050*sl 0.15 + 0.051*sl t r 0.35 0.27 + 0.039*sl 0.26 + 0.046*sl 0.18 + 0.054*sl t f 0.44 0.25 + 0.094*sl 0.23 + 0.103*sl 0.20 + 0.107*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-473 STD80/stdm80 dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.56 0.48 + 0.041*sl 0.49 + 0.037*sl 0.50 + 0.035*sl t phl 0.80 0.65 + 0.073*sl 0.66 + 0.070*sl 0.67 + 0.068*sl t r 0.41 0.27 + 0.069*sl 0.27 + 0.071*sl 0.25 + 0.073*sl t f 0.62 0.35 + 0.134*sl 0.34 + 0.137*sl 0.33 + 0.139*sl s1 to yn0 t plh 0.52 0.44 + 0.042*sl 0.45 + 0.037*sl 0.47 + 0.035*sl t phl 0.79 0.65 + 0.073*sl 0.66 + 0.069*sl 0.66 + 0.068*sl t r 0.38 0.24 + 0.070*sl 0.24 + 0.071*sl 0.23 + 0.073*sl t f 0.63 0.36 + 0.132*sl 0.36 + 0.135*sl 0.34 + 0.138*sl s2 to yn0 t plh 0.55 0.47 + 0.040*sl 0.49 + 0.036*sl 0.49 + 0.035*sl t phl 0.76 0.62 + 0.071*sl 0.63 + 0.068*sl 0.63 + 0.068*sl t r 0.43 0.30 + 0.068*sl 0.29 + 0.070*sl 0.27 + 0.073*sl t f 0.60 0.34 + 0.134*sl 0.33 + 0.137*sl 0.31 + 0.139*sl s0 to yn1 t plh 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.38 0.24 + 0.070*sl 0.24 + 0.069*sl 0.25 + 0.068*sl t r 0.38 0.25 + 0.067*sl 0.24 + 0.071*sl 0.22 + 0.074*sl t f 0.60 0.33 + 0.134*sl 0.32 + 0.137*sl 0.30 + 0.140*sl s1 to yn1 t plh 0.52 0.44 + 0.042*sl 0.45 + 0.037*sl 0.47 + 0.035*sl t phl 0.79 0.65 + 0.073*sl 0.66 + 0.070*sl 0.67 + 0.068*sl t r 0.38 0.24 + 0.070*sl 0.24 + 0.071*sl 0.22 + 0.073*sl t f 0.63 0.37 + 0.133*sl 0.36 + 0.136*sl 0.34 + 0.138*sl s2 to yn1 t plh 0.56 0.47 + 0.040*sl 0.49 + 0.036*sl 0.50 + 0.035*sl t phl 0.77 0.62 + 0.071*sl 0.63 + 0.069*sl 0.63 + 0.068*sl t r 0.43 0.30 + 0.067*sl 0.29 + 0.071*sl 0.27 + 0.073*sl t f 0.61 0.33 + 0.135*sl 0.33 + 0.138*sl 0.32 + 0.139*sl s0 to yn2 t plh 0.56 0.48 + 0.042*sl 0.50 + 0.037*sl 0.51 + 0.035*sl t phl 0.80 0.65 + 0.073*sl 0.66 + 0.070*sl 0.67 + 0.068*sl t r 0.40 0.27 + 0.068*sl 0.26 + 0.071*sl 0.25 + 0.073*sl t f 0.61 0.34 + 0.133*sl 0.33 + 0.136*sl 0.32 + 0.138*sl s1 to yn2 t plh 0.26 0.19 + 0.036*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t phl 0.36 0.22 + 0.070*sl 0.23 + 0.069*sl 0.23 + 0.068*sl t r 0.40 0.27 + 0.064*sl 0.25 + 0.070*sl 0.24 + 0.073*sl t f 0.57 0.29 + 0.137*sl 0.29 + 0.139*sl 0.28 + 0.140*sl s2 to yn2 t plh 0.53 0.44 + 0.042*sl 0.46 + 0.037*sl 0.47 + 0.035*sl t phl 0.79 0.64 + 0.074*sl 0.66 + 0.070*sl 0.67 + 0.068*sl t r 0.38 0.24 + 0.069*sl 0.23 + 0.071*sl 0.22 + 0.073*sl t f 0.62 0.35 + 0.134*sl 0.35 + 0.135*sl 0.33 + 0.138*sl s0 to yn3 t plh 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.37 0.23 + 0.070*sl 0.23 + 0.069*sl 0.24 + 0.068*sl t r 0.37 0.24 + 0.067*sl 0.23 + 0.071*sl 0.21 + 0.074*sl t f 0.58 0.31 + 0.134*sl 0.30 + 0.138*sl 0.28 + 0.140*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-474 sec asic dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s1 to yn3 t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t phl 0.36 0.22 + 0.070*sl 0.23 + 0.069*sl 0.23 + 0.068*sl t r 0.40 0.28 + 0.064*sl 0.26 + 0.070*sl 0.23 + 0.073*sl t f 0.57 0.29 + 0.137*sl 0.29 + 0.139*sl 0.28 + 0.140*sl s2 to yn3 t plh 0.53 0.45 + 0.042*sl 0.46 + 0.037*sl 0.48 + 0.035*sl t phl 0.80 0.65 + 0.074*sl 0.66 + 0.070*sl 0.67 + 0.068*sl t r 0.38 0.24 + 0.070*sl 0.24 + 0.071*sl 0.22 + 0.073*sl t f 0.63 0.36 + 0.134*sl 0.35 + 0.135*sl 0.33 + 0.138*sl s0 to yn4 t plh 0.57 0.48 + 0.042*sl 0.50 + 0.037*sl 0.51 + 0.035*sl t phl 0.80 0.65 + 0.074*sl 0.67 + 0.070*sl 0.68 + 0.068*sl t r 0.41 0.27 + 0.069*sl 0.26 + 0.071*sl 0.25 + 0.073*sl t f 0.61 0.35 + 0.133*sl 0.34 + 0.136*sl 0.33 + 0.138*sl s1 to yn4 t plh 0.52 0.43 + 0.042*sl 0.45 + 0.037*sl 0.46 + 0.035*sl t phl 0.79 0.64 + 0.073*sl 0.65 + 0.069*sl 0.66 + 0.068*sl t r 0.38 0.24 + 0.070*sl 0.23 + 0.071*sl 0.22 + 0.073*sl t f 0.62 0.35 + 0.133*sl 0.35 + 0.136*sl 0.33 + 0.138*sl s2 to yn4 t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t phl 0.37 0.23 + 0.070*sl 0.23 + 0.068*sl 0.24 + 0.067*sl t r 0.40 0.27 + 0.065*sl 0.26 + 0.070*sl 0.24 + 0.073*sl t f 0.57 0.30 + 0.133*sl 0.29 + 0.138*sl 0.27 + 0.140*sl s0 to yn5 t plh 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.37 0.23 + 0.070*sl 0.23 + 0.068*sl 0.24 + 0.068*sl t r 0.37 0.24 + 0.066*sl 0.23 + 0.071*sl 0.21 + 0.074*sl t f 0.58 0.31 + 0.134*sl 0.30 + 0.138*sl 0.28 + 0.140*sl s1 to yn5 t plh 0.52 0.43 + 0.042*sl 0.45 + 0.037*sl 0.46 + 0.035*sl t phl 0.79 0.64 + 0.073*sl 0.65 + 0.069*sl 0.66 + 0.068*sl t r 0.38 0.24 + 0.069*sl 0.23 + 0.071*sl 0.22 + 0.073*sl t f 0.62 0.35 + 0.133*sl 0.35 + 0.135*sl 0.33 + 0.138*sl s2 to yn5 t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t phl 0.37 0.23 + 0.070*sl 0.23 + 0.068*sl 0.23 + 0.068*sl t r 0.40 0.27 + 0.065*sl 0.26 + 0.070*sl 0.23 + 0.073*sl t f 0.57 0.30 + 0.135*sl 0.29 + 0.138*sl 0.28 + 0.140*sl s0 to yn6 t plh 0.58 0.49 + 0.042*sl 0.51 + 0.037*sl 0.52 + 0.035*sl t phl 0.81 0.66 + 0.073*sl 0.67 + 0.070*sl 0.68 + 0.069*sl t r 0.41 0.28 + 0.067*sl 0.26 + 0.071*sl 0.25 + 0.073*sl t f 0.62 0.35 + 0.132*sl 0.34 + 0.136*sl 0.32 + 0.138*sl s1 to yn6 t plh 0.23 0.16 + 0.038*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t phl 0.36 0.22 + 0.069*sl 0.22 + 0.068*sl 0.22 + 0.068*sl t r 0.35 0.22 + 0.066*sl 0.21 + 0.071*sl 0.19 + 0.073*sl t f 0.57 0.30 + 0.134*sl 0.29 + 0.138*sl 0.27 + 0.141*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-475 STD80/stdm80 dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 dc8i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to yn6 t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t phl 0.36 0.22 + 0.070*sl 0.23 + 0.069*sl 0.23 + 0.069*sl t r 0.40 0.27 + 0.065*sl 0.26 + 0.070*sl 0.23 + 0.073*sl t f 0.57 0.29 + 0.138*sl 0.29 + 0.139*sl 0.28 + 0.140*sl s0 to yn7 t plh 0.25 0.18 + 0.035*sl 0.18 + 0.035*sl 0.18 + 0.034*sl t phl 0.36 0.23 + 0.069*sl 0.23 + 0.068*sl 0.23 + 0.068*sl t r 0.37 0.24 + 0.066*sl 0.23 + 0.070*sl 0.21 + 0.073*sl t f 0.57 0.30 + 0.136*sl 0.29 + 0.139*sl 0.28 + 0.140*sl s1 to yn7 t plh 0.23 0.16 + 0.038*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t phl 0.36 0.22 + 0.068*sl 0.22 + 0.069*sl 0.23 + 0.068*sl t r 0.35 0.22 + 0.066*sl 0.21 + 0.071*sl 0.19 + 0.073*sl t f 0.57 0.31 + 0.134*sl 0.29 + 0.138*sl 0.28 + 0.141*sl s2 to yn7 t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.19 + 0.035*sl t phl 0.36 0.23 + 0.069*sl 0.23 + 0.069*sl 0.23 + 0.069*sl t r 0.40 0.27 + 0.066*sl 0.26 + 0.070*sl 0.24 + 0.073*sl t f 0.57 0.29 + 0.137*sl 0.29 + 0.139*sl 0.28 + 0.140*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-476 sec asic adders cell list cell name function description fa full adder fad2 full adder with 2x drive ha half adder had2 half adder with 2x drive
sec asic 3-477 STD80/stdm80 fa/fad2 full adder with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 fa fad2 fa fad2 ci a b ci a b 1.3 0.6 1.3 1.3 0.6 1.3 6.3 6.7 stdm80 fa fad2 fa fad2 ci a b ci a b 1.5 0.7 1.6 1.5 0.7 1.6 6.3 6.7 ci a b s co a ci b bb b b bb s co cib ci b cib ci ci truth table ci a b s co 00000 10010 00110 10101 01010 11001 01101 11111
STD80/stdm80 3-478 sec asic fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fa path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.84 0.78 + 0.030*sl 0.79 + 0.025*sl 0.80 + 0.024*sl t phl 0.90 0.81 + 0.044*sl 0.82 + 0.038*sl 0.84 + 0.037*sl t r 0.21 0.12 + 0.045*sl 0.11 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.066*sl 0.09 + 0.069*sl b to s t plh 0.75 0.68 + 0.035*sl 0.70 + 0.026*sl 0.73 + 0.024*sl t phl 0.87 0.79 + 0.044*sl 0.80 + 0.039*sl 0.81 + 0.037*sl t r 0.26 0.17 + 0.044*sl 0.17 + 0.047*sl 0.12 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.12 + 0.066*sl 0.09 + 0.069*sl ci to s t plh 0.43 0.37 + 0.032*sl 0.38 + 0.026*sl 0.40 + 0.024*sl t phl 0.50 0.42 + 0.044*sl 0.43 + 0.038*sl 0.44 + 0.037*sl t r 0.24 0.15 + 0.044*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.27 0.14 + 0.060*sl 0.13 + 0.065*sl 0.10 + 0.069*sl a to co t plh 0.72 0.65 + 0.032*sl 0.67 + 0.025*sl 0.68 + 0.024*sl t phl 0.86 0.77 + 0.044*sl 0.78 + 0.039*sl 0.80 + 0.037*sl t r 0.25 0.16 + 0.044*sl 0.15 + 0.046*sl 0.10 + 0.052*sl t f 0.28 0.16 + 0.064*sl 0.15 + 0.065*sl 0.12 + 0.069*sl b to co t plh 0.59 0.53 + 0.032*sl 0.54 + 0.025*sl 0.56 + 0.024*sl t phl 0.66 0.57 + 0.044*sl 0.58 + 0.039*sl 0.60 + 0.037*sl t r 0.25 0.17 + 0.042*sl 0.16 + 0.046*sl 0.10 + 0.052*sl t f 0.26 0.12 + 0.066*sl 0.12 + 0.067*sl 0.10 + 0.069*sl ci to co t plh 0.39 0.32 + 0.034*sl 0.34 + 0.025*sl 0.36 + 0.024*sl t phl 0.51 0.42 + 0.045*sl 0.43 + 0.039*sl 0.45 + 0.037*sl t r 0.23 0.14 + 0.046*sl 0.14 + 0.048*sl 0.10 + 0.052*sl t f 0.29 0.16 + 0.064*sl 0.16 + 0.065*sl 0.12 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-479 STD80/stdm80 fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 fad2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.85 0.81 + 0.021*sl 0.82 + 0.015*sl 0.85 + 0.012*sl t phl 0.91 0.85 + 0.026*sl 0.87 + 0.021*sl 0.89 + 0.018*sl t r 0.18 0.13 + 0.023*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.22 0.15 + 0.033*sl 0.15 + 0.031*sl 0.13 + 0.033*sl b to s t plh 0.78 0.73 + 0.023*sl 0.74 + 0.017*sl 0.79 + 0.012*sl t phl 0.89 0.84 + 0.026*sl 0.85 + 0.021*sl 0.88 + 0.018*sl t r 0.23 0.19 + 0.022*sl 0.19 + 0.023*sl 0.16 + 0.025*sl t f 0.21 0.14 + 0.033*sl 0.15 + 0.031*sl 0.13 + 0.034*sl ci to s t plh 0.45 0.41 + 0.022*sl 0.42 + 0.016*sl 0.46 + 0.012*sl t phl 0.52 0.46 + 0.027*sl 0.48 + 0.021*sl 0.51 + 0.018*sl t r 0.22 0.17 + 0.023*sl 0.17 + 0.023*sl 0.14 + 0.026*sl t f 0.23 0.16 + 0.032*sl 0.17 + 0.031*sl 0.14 + 0.033*sl a to co t plh 0.74 0.70 + 0.023*sl 0.71 + 0.015*sl 0.75 + 0.012*sl t phl 0.87 0.81 + 0.027*sl 0.83 + 0.022*sl 0.86 + 0.018*sl t r 0.23 0.19 + 0.021*sl 0.19 + 0.022*sl 0.15 + 0.025*sl t f 0.24 0.18 + 0.032*sl 0.18 + 0.031*sl 0.16 + 0.033*sl b to co t plh 0.62 0.57 + 0.023*sl 0.59 + 0.016*sl 0.62 + 0.012*sl t phl 0.68 0.63 + 0.026*sl 0.64 + 0.021*sl 0.67 + 0.018*sl t r 0.23 0.19 + 0.022*sl 0.19 + 0.022*sl 0.15 + 0.025*sl t f 0.21 0.15 + 0.032*sl 0.15 + 0.032*sl 0.13 + 0.033*sl ci to co t plh 0.39 0.35 + 0.022*sl 0.36 + 0.015*sl 0.40 + 0.012*sl t phl 0.51 0.45 + 0.028*sl 0.46 + 0.022*sl 0.50 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.024*sl 0.13 + 0.026*sl t f 0.24 0.18 + 0.033*sl 0.18 + 0.031*sl 0.16 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-480 sec asic fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fa path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 1.19 1.11 + 0.041*sl 1.12 + 0.035*sl 1.13 + 0.034*sl t phl 1.30 1.18 + 0.057*sl 1.21 + 0.048*sl 1.23 + 0.045*sl t r 0.29 0.16 + 0.067*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.082*sl 0.19 + 0.079*sl 0.18 + 0.080*sl b to s t plh 1.06 0.97 + 0.044*sl 0.99 + 0.038*sl 1.01 + 0.035*sl t phl 1.22 1.11 + 0.057*sl 1.13 + 0.049*sl 1.16 + 0.045*sl t r 0.34 0.20 + 0.067*sl 0.20 + 0.067*sl 0.19 + 0.069*sl t f 0.34 0.18 + 0.081*sl 0.18 + 0.079*sl 0.17 + 0.080*sl ci to s t plh 0.60 0.51 + 0.042*sl 0.53 + 0.037*sl 0.54 + 0.034*sl t phl 0.65 0.54 + 0.057*sl 0.56 + 0.049*sl 0.59 + 0.045*sl t r 0.32 0.19 + 0.067*sl 0.18 + 0.068*sl 0.17 + 0.070*sl t f 0.35 0.19 + 0.081*sl 0.19 + 0.079*sl 0.19 + 0.080*sl a to co t plh 1.01 0.93 + 0.042*sl 0.95 + 0.036*sl 0.96 + 0.034*sl t phl 1.21 1.10 + 0.058*sl 1.12 + 0.050*sl 1.15 + 0.046*sl t r 0.33 0.20 + 0.064*sl 0.19 + 0.067*sl 0.17 + 0.069*sl t f 0.37 0.20 + 0.083*sl 0.21 + 0.079*sl 0.21 + 0.080*sl b to co t plh 0.85 0.77 + 0.042*sl 0.79 + 0.036*sl 0.80 + 0.034*sl t phl 0.92 0.81 + 0.057*sl 0.83 + 0.049*sl 0.85 + 0.046*sl t r 0.33 0.20 + 0.064*sl 0.19 + 0.067*sl 0.17 + 0.069*sl t f 0.34 0.17 + 0.084*sl 0.18 + 0.081*sl 0.18 + 0.081*sl ci to co t plh 0.52 0.43 + 0.042*sl 0.45 + 0.037*sl 0.47 + 0.034*sl t phl 0.70 0.57 + 0.061*sl 0.61 + 0.051*sl 0.64 + 0.046*sl t r 0.31 0.17 + 0.069*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t f 0.38 0.22 + 0.082*sl 0.23 + 0.078*sl 0.22 + 0.079*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-481 STD80/stdm80 fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 fad2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 1.20 1.15 + 0.026*sl 1.16 + 0.021*sl 1.18 + 0.019*sl t phl 1.31 1.24 + 0.035*sl 1.26 + 0.029*sl 1.29 + 0.025*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.28 0.20 + 0.043*sl 0.21 + 0.040*sl 0.22 + 0.038*sl b to s t plh 1.09 1.03 + 0.029*sl 1.05 + 0.023*sl 1.07 + 0.020*sl t phl 1.24 1.17 + 0.036*sl 1.19 + 0.030*sl 1.22 + 0.025*sl t r 0.28 0.21 + 0.034*sl 0.21 + 0.034*sl 0.21 + 0.033*sl t f 0.28 0.19 + 0.042*sl 0.20 + 0.040*sl 0.21 + 0.038*sl ci to s t plh 0.63 0.57 + 0.028*sl 0.59 + 0.022*sl 0.61 + 0.019*sl t phl 0.67 0.59 + 0.036*sl 0.61 + 0.029*sl 0.64 + 0.025*sl t r 0.27 0.20 + 0.035*sl 0.21 + 0.033*sl 0.20 + 0.033*sl t f 0.29 0.21 + 0.044*sl 0.22 + 0.039*sl 0.23 + 0.038*sl a to co t plh 1.05 1.00 + 0.028*sl 1.02 + 0.022*sl 1.04 + 0.019*sl t phl 1.23 1.15 + 0.036*sl 1.17 + 0.030*sl 1.20 + 0.026*sl t r 0.28 0.21 + 0.033*sl 0.21 + 0.032*sl 0.21 + 0.032*sl t f 0.31 0.22 + 0.045*sl 0.23 + 0.040*sl 0.24 + 0.038*sl b to co t plh 0.89 0.84 + 0.028*sl 0.85 + 0.022*sl 0.87 + 0.019*sl t phl 0.96 0.89 + 0.035*sl 0.91 + 0.029*sl 0.93 + 0.026*sl t r 0.28 0.21 + 0.033*sl 0.22 + 0.032*sl 0.21 + 0.032*sl t f 0.27 0.19 + 0.043*sl 0.19 + 0.041*sl 0.20 + 0.039*sl ci to co t plh 0.52 0.47 + 0.027*sl 0.48 + 0.022*sl 0.50 + 0.019*sl t phl 0.70 0.62 + 0.038*sl 0.64 + 0.031*sl 0.68 + 0.026*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.32 0.23 + 0.043*sl 0.24 + 0.040*sl 0.26 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-482 sec asic ha/had2 half adder with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 ha had2 ha had2 abab 1.3 1.5 1.3 1.5 4.0 4.7 stdm80 ha had2 ha had2 abab 1.5 2.3 1.5 2.3 4.0 4.7 a b s co a s co b truth table absco 0000 0110 1010 1101
sec asic 3-483 STD80/stdm80 ha/had2 half adder with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ha STD80 had2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.47 0.41 + 0.031*sl 0.42 + 0.025*sl 0.43 + 0.024*sl t phl 0.51 0.42 + 0.044*sl 0.43 + 0.039*sl 0.45 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.065*sl 0.14 + 0.065*sl 0.10 + 0.069*sl b to s t plh 0.34 0.28 + 0.030*sl 0.29 + 0.025*sl 0.31 + 0.024*sl t phl 0.40 0.31 + 0.044*sl 0.32 + 0.039*sl 0.34 + 0.037*sl t r 0.21 0.11 + 0.048*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.12 + 0.066*sl 0.10 + 0.069*sl a to co t plh 0.28 0.22 + 0.029*sl 0.23 + 0.025*sl 0.24 + 0.024*sl t phl 0.31 0.24 + 0.039*sl 0.24 + 0.037*sl 0.24 + 0.037*sl t r 0.21 0.11 + 0.047*sl 0.11 + 0.048*sl 0.08 + 0.052*sl t f 0.22 0.09 + 0.065*sl 0.09 + 0.067*sl 0.07 + 0.069*sl b to co t plh 0.26 0.20 + 0.029*sl 0.21 + 0.025*sl 0.22 + 0.024*sl t phl 0.34 0.26 + 0.039*sl 0.26 + 0.037*sl 0.26 + 0.037*sl t r 0.21 0.11 + 0.047*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.22 0.10 + 0.063*sl 0.09 + 0.067*sl 0.07 + 0.069*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.47 0.43 + 0.020*sl 0.45 + 0.015*sl 0.48 + 0.012*sl t phl 0.51 0.46 + 0.027*sl 0.47 + 0.022*sl 0.50 + 0.018*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.22 0.15 + 0.034*sl 0.16 + 0.031*sl 0.13 + 0.033*sl b to s t plh 0.34 0.30 + 0.022*sl 0.31 + 0.015*sl 0.34 + 0.012*sl t phl 0.39 0.34 + 0.028*sl 0.35 + 0.022*sl 0.38 + 0.018*sl t r 0.18 0.14 + 0.017*sl 0.13 + 0.024*sl 0.11 + 0.026*sl t f 0.21 0.14 + 0.034*sl 0.15 + 0.032*sl 0.13 + 0.033*sl a to co t plh 0.30 0.26 + 0.018*sl 0.27 + 0.014*sl 0.30 + 0.012*sl t phl 0.32 0.27 + 0.022*sl 0.28 + 0.019*sl 0.29 + 0.018*sl t r 0.18 0.13 + 0.025*sl 0.13 + 0.023*sl 0.10 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.10 + 0.031*sl 0.07 + 0.034*sl b to co t plh 0.28 0.24 + 0.018*sl 0.25 + 0.014*sl 0.27 + 0.012*sl t phl 0.34 0.29 + 0.023*sl 0.30 + 0.019*sl 0.31 + 0.018*sl t r 0.18 0.13 + 0.022*sl 0.13 + 0.023*sl 0.10 + 0.026*sl t f 0.16 0.11 + 0.027*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-484 sec asic ha/had2 half adder with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ha stdm80 had2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.64 0.55 + 0.042*sl 0.57 + 0.036*sl 0.59 + 0.034*sl t phl 0.72 0.61 + 0.058*sl 0.63 + 0.050*sl 0.66 + 0.046*sl t r 0.29 0.16 + 0.068*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.35 0.19 + 0.083*sl 0.20 + 0.078*sl 0.19 + 0.080*sl b to s t plh 0.46 0.38 + 0.041*sl 0.40 + 0.036*sl 0.41 + 0.034*sl t phl 0.55 0.43 + 0.058*sl 0.45 + 0.049*sl 0.48 + 0.046*sl t r 0.29 0.16 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.083*sl 0.19 + 0.080*sl 0.18 + 0.080*sl a to co t plh 0.37 0.29 + 0.039*sl 0.30 + 0.035*sl 0.31 + 0.034*sl t phl 0.41 0.31 + 0.048*sl 0.32 + 0.045*sl 0.32 + 0.044*sl t r 0.28 0.14 + 0.069*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.11 + 0.081*sl 0.10 + 0.083*sl b to co t plh 0.35 0.28 + 0.039*sl 0.29 + 0.035*sl 0.30 + 0.034*sl t phl 0.43 0.33 + 0.048*sl 0.34 + 0.045*sl 0.35 + 0.044*sl t r 0.28 0.14 + 0.067*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.28 0.12 + 0.079*sl 0.11 + 0.081*sl 0.10 + 0.083*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.64 0.59 + 0.027*sl 0.61 + 0.022*sl 0.63 + 0.019*sl t phl 0.73 0.66 + 0.036*sl 0.68 + 0.030*sl 0.70 + 0.026*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.034*sl 0.17 + 0.034*sl t f 0.29 0.20 + 0.044*sl 0.21 + 0.040*sl 0.22 + 0.038*sl b to s t plh 0.46 0.41 + 0.026*sl 0.43 + 0.022*sl 0.45 + 0.019*sl t phl 0.54 0.47 + 0.036*sl 0.49 + 0.030*sl 0.52 + 0.026*sl t r 0.23 0.16 + 0.037*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.28 0.19 + 0.044*sl 0.20 + 0.040*sl 0.21 + 0.039*sl a to co t plh 0.39 0.34 + 0.025*sl 0.35 + 0.021*sl 0.37 + 0.018*sl t phl 0.41 0.35 + 0.029*sl 0.36 + 0.024*sl 0.38 + 0.022*sl t r 0.22 0.14 + 0.037*sl 0.15 + 0.034*sl 0.15 + 0.034*sl t f 0.19 0.11 + 0.039*sl 0.12 + 0.039*sl 0.12 + 0.039*sl b to co t plh 0.38 0.33 + 0.025*sl 0.34 + 0.021*sl 0.36 + 0.018*sl t phl 0.43 0.37 + 0.029*sl 0.38 + 0.024*sl 0.40 + 0.022*sl t r 0.22 0.15 + 0.035*sl 0.15 + 0.035*sl 0.15 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.12 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-485 STD80/stdm80 multiplexers cell list cell name function description mx2 2 > 1 non-inverting mux mx2d3 2 > 1 non-inverting mux with 3x drive mx2x4 4-bit 2 > 1 non-inverting mux ymx2 fast 2 > 1 non-inverting mux ymx2d2 fast 2 > 1 non-inverting mux with 2x drive mx2i 2 > 1 inverting mux mx2id2 2 > 1 inverting mux with 2x drive mx2ia 2 > 1 inverting mux with separate s and sn inputs mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 2x drive mx2ix4 4-bit 2 > 1 inverting mux mx3i 3 > 1 inverting mux mx3id2 3 > 1 inverting mux with 2x drive mx4 4 > 1 non-inverting mux mx4d2 4 > 1 non-inverting mux with 2x drive ymx4 fast 4 > 1 non-inverting mux ymx4d2 fast 4 > 1 non-inverting mux with 2x drive mx5 5 > 1 non-inverting mux mx5d2 5 > 1 non-inverting mux with 2x drive mx8 8 > 1 non-inverting mux mx8d2 8 > 1 non-inverting mux with 2x drive ymx8 fast 8 > 1 non-inverting mux ymx8d2 fast 8 > 1 non-inverting mux with 2x drive
STD80/stdm80 3-486 sec asic mx2/mx2d3 2 > 1 non-inverting mux with 1x/3x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 mx2 mx2d3 mx2 mx2d3 d0 d1 s d0 d1 s 0.7 0.7 1.0 0.6 0.6 1.0 2.7 3.3 stdm80 mx2 mx2d3 mx2 mx2d3 d0 d1 s d0 d1 s 0.7 0.7 1.6 0.7 0.7 1.6 2.7 3.3 d0 d1 y s s sb y sb s s d0 d1 truth table d0 d1 s y 0x00 1x01 x010 x111
sec asic 3-487 STD80/stdm80 mx2/mx2d3 2 > 1 non-inverting mux with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx2 STD80 mx2d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.42 0.34 + 0.043*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.065*sl 0.09 + 0.069*sl d1 to y t plh 0.32 0.26 + 0.030*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.43 0.34 + 0.044*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.066*sl 0.09 + 0.069*sl s to y t plh 0.34 0.28 + 0.028*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.40 0.31 + 0.044*sl 0.32 + 0.038*sl 0.33 + 0.037*sl t r 0.21 0.11 + 0.047*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.09 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.36 0.33 + 0.015*sl 0.34 + 0.011*sl 0.38 + 0.008*sl t phl 0.48 0.44 + 0.018*sl 0.45 + 0.016*sl 0.48 + 0.012*sl t r 0.20 0.17 + 0.016*sl 0.17 + 0.016*sl 0.15 + 0.017*sl t f 0.23 0.19 + 0.023*sl 0.19 + 0.021*sl 0.18 + 0.022*sl d1 to y t plh 0.36 0.33 + 0.015*sl 0.34 + 0.011*sl 0.37 + 0.008*sl t phl 0.48 0.44 + 0.019*sl 0.45 + 0.016*sl 0.48 + 0.012*sl t r 0.20 0.17 + 0.015*sl 0.17 + 0.015*sl 0.15 + 0.017*sl t f 0.23 0.19 + 0.021*sl 0.19 + 0.021*sl 0.18 + 0.022*sl s to y t plh 0.37 0.34 + 0.016*sl 0.35 + 0.011*sl 0.38 + 0.008*sl t phl 0.44 0.40 + 0.019*sl 0.41 + 0.016*sl 0.44 + 0.012*sl t r 0.20 0.16 + 0.016*sl 0.16 + 0.016*sl 0.15 + 0.017*sl t f 0.23 0.18 + 0.023*sl 0.18 + 0.021*sl 0.17 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-488 sec asic mx2/mx2d3 2 > 1 non-inverting mux with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx2 stdm80 mx2d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.43 0.35 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.033*sl t phl 0.57 0.45 + 0.057*sl 0.48 + 0.049*sl 0.50 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.34 0.18 + 0.082*sl 0.18 + 0.079*sl 0.18 + 0.080*sl d1 to y t plh 0.42 0.34 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.034*sl t phl 0.57 0.46 + 0.056*sl 0.48 + 0.049*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.34 0.18 + 0.080*sl 0.18 + 0.079*sl 0.17 + 0.080*sl s to y t plh 0.46 0.38 + 0.040*sl 0.40 + 0.035*sl 0.41 + 0.034*sl t phl 0.54 0.43 + 0.057*sl 0.45 + 0.048*sl 0.47 + 0.045*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.17 + 0.082*sl 0.18 + 0.079*sl 0.17 + 0.080*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.49 0.45 + 0.020*sl 0.46 + 0.016*sl 0.47 + 0.014*sl t phl 0.66 0.60 + 0.026*sl 0.62 + 0.022*sl 0.64 + 0.019*sl t r 0.24 0.20 + 0.024*sl 0.20 + 0.023*sl 0.20 + 0.023*sl t f 0.30 0.24 + 0.031*sl 0.25 + 0.027*sl 0.26 + 0.026*sl d1 to y t plh 0.48 0.44 + 0.020*sl 0.45 + 0.016*sl 0.47 + 0.014*sl t phl 0.66 0.61 + 0.026*sl 0.62 + 0.022*sl 0.64 + 0.019*sl t r 0.24 0.19 + 0.024*sl 0.20 + 0.023*sl 0.20 + 0.023*sl t f 0.30 0.24 + 0.031*sl 0.25 + 0.028*sl 0.26 + 0.026*sl s to y t plh 0.51 0.47 + 0.020*sl 0.48 + 0.016*sl 0.49 + 0.014*sl t phl 0.61 0.56 + 0.026*sl 0.57 + 0.022*sl 0.59 + 0.019*sl t r 0.25 0.20 + 0.025*sl 0.20 + 0.023*sl 0.20 + 0.023*sl t f 0.30 0.24 + 0.030*sl 0.24 + 0.028*sl 0.26 + 0.026*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-489 STD80/stdm80 mx2x4 4-bit 2 > 1 non-inverting mux logic symbol y0 y1 y2 y3 d00 d10 d01 d11 d02 d12 d03 d13 s truth table cell data s y0y1y2y3 0 d00 d01 d02 d03 1 d10 d11 d12 d13 input load (sl) gate count STD80 dxy s 8.7 0.7 1.8 stdm80 dxy s 8.7 0.7 3.9
STD80/stdm80 3-490 sec asic mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to y0 t plh 0.32 0.26 + 0.030*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.42 0.34 + 0.044*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.065*sl 0.09 + 0.069*sl d10 to y0 t plh 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.43 0.34 + 0.043*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.12 + 0.045*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.066*sl 0.09 + 0.069*sl s to y0 t plh 0.43 0.37 + 0.031*sl 0.39 + 0.025*sl 0.40 + 0.024*sl t phl 0.49 0.41 + 0.044*sl 0.42 + 0.038*sl 0.43 + 0.037*sl t r 0.23 0.15 + 0.042*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.26 0.14 + 0.064*sl 0.13 + 0.065*sl 0.09 + 0.069*sl d01 to y1 t plh 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.43 0.34 + 0.043*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.14 + 0.039*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.066*sl 0.10 + 0.069*sl d11 to y1 t plh 0.32 0.26 + 0.030*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.43 0.34 + 0.043*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.065*sl 0.10 + 0.069*sl s to y1 t plh 0.44 0.37 + 0.031*sl 0.39 + 0.025*sl 0.40 + 0.024*sl t phl 0.49 0.41 + 0.044*sl 0.42 + 0.038*sl 0.43 + 0.037*sl t r 0.23 0.15 + 0.042*sl 0.14 + 0.047*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.064*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d02 to y2 t plh 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.43 0.34 + 0.043*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.066*sl 0.10 + 0.069*sl d12 to y2 t plh 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.43 0.34 + 0.044*sl 0.35 + 0.038*sl 0.37 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.065*sl 0.10 + 0.069*sl s to y2 t plh 0.44 0.37 + 0.031*sl 0.39 + 0.025*sl 0.40 + 0.024*sl t phl 0.49 0.41 + 0.044*sl 0.42 + 0.038*sl 0.43 + 0.037*sl t r 0.23 0.15 + 0.043*sl 0.14 + 0.047*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d03 to y3 t plh 0.32 0.26 + 0.031*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.42 0.34 + 0.043*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.065*sl 0.09 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-491 STD80/stdm80 mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to y3 t plh 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.43 0.34 + 0.043*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.066*sl 0.09 + 0.069*sl s to y3 t plh 0.43 0.37 + 0.031*sl 0.38 + 0.025*sl 0.40 + 0.024*sl t phl 0.49 0.41 + 0.043*sl 0.42 + 0.038*sl 0.43 + 0.037*sl t r 0.23 0.15 + 0.042*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.26 0.14 + 0.064*sl 0.13 + 0.065*sl 0.09 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-492 sec asic mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to y0 t plh 0.43 0.35 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.033*sl t phl 0.57 0.45 + 0.057*sl 0.48 + 0.048*sl 0.50 + 0.045*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.081*sl 0.18 + 0.079*sl 0.17 + 0.080*sl d10 to y0 t plh 0.42 0.34 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.033*sl t phl 0.57 0.46 + 0.057*sl 0.48 + 0.048*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.34 0.18 + 0.082*sl 0.18 + 0.079*sl 0.18 + 0.080*sl s to y0 t plh 0.60 0.52 + 0.042*sl 0.54 + 0.035*sl 0.55 + 0.034*sl t phl 0.65 0.53 + 0.056*sl 0.56 + 0.049*sl 0.58 + 0.045*sl t r 0.31 0.18 + 0.065*sl 0.18 + 0.066*sl 0.15 + 0.070*sl t f 0.35 0.18 + 0.081*sl 0.19 + 0.078*sl 0.18 + 0.080*sl d01 to y1 t plh 0.43 0.35 + 0.040*sl 0.36 + 0.035*sl 0.38 + 0.033*sl t phl 0.57 0.46 + 0.056*sl 0.48 + 0.049*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.070*sl t f 0.34 0.18 + 0.082*sl 0.19 + 0.079*sl 0.18 + 0.080*sl d11 to y1 t plh 0.43 0.35 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.033*sl t phl 0.58 0.46 + 0.057*sl 0.49 + 0.048*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.081*sl 0.19 + 0.079*sl 0.18 + 0.080*sl s to y1 t plh 0.60 0.52 + 0.042*sl 0.54 + 0.035*sl 0.55 + 0.033*sl t phl 0.65 0.53 + 0.057*sl 0.56 + 0.049*sl 0.58 + 0.045*sl t r 0.31 0.18 + 0.066*sl 0.18 + 0.067*sl 0.16 + 0.070*sl t f 0.35 0.19 + 0.081*sl 0.20 + 0.078*sl 0.19 + 0.080*sl d02 to y2 t plh 0.43 0.35 + 0.040*sl 0.36 + 0.035*sl 0.38 + 0.033*sl t phl 0.57 0.46 + 0.056*sl 0.48 + 0.049*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.082*sl 0.19 + 0.079*sl 0.18 + 0.080*sl d12 to y2 t plh 0.43 0.35 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.034*sl t phl 0.58 0.46 + 0.056*sl 0.49 + 0.049*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.069*sl 0.15 + 0.068*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.082*sl 0.19 + 0.079*sl 0.18 + 0.080*sl s to y2 t plh 0.60 0.52 + 0.041*sl 0.54 + 0.036*sl 0.55 + 0.033*sl t phl 0.65 0.53 + 0.057*sl 0.56 + 0.048*sl 0.58 + 0.045*sl t r 0.31 0.18 + 0.065*sl 0.18 + 0.067*sl 0.16 + 0.070*sl t f 0.35 0.19 + 0.081*sl 0.20 + 0.078*sl 0.19 + 0.080*sl d03 to y3 t plh 0.43 0.35 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.034*sl t phl 0.57 0.46 + 0.056*sl 0.48 + 0.049*sl 0.50 + 0.045*sl t r 0.29 0.15 + 0.067*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.34 0.18 + 0.082*sl 0.19 + 0.079*sl 0.18 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-493 STD80/stdm80 mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to y3 t plh 0.42 0.34 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.033*sl t phl 0.57 0.46 + 0.057*sl 0.48 + 0.048*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.34 0.18 + 0.082*sl 0.18 + 0.079*sl 0.18 + 0.080*sl s to y3 t plh 0.60 0.52 + 0.041*sl 0.54 + 0.035*sl 0.55 + 0.034*sl t phl 0.65 0.53 + 0.057*sl 0.56 + 0.049*sl 0.58 + 0.045*sl t r 0.31 0.18 + 0.065*sl 0.18 + 0.067*sl 0.16 + 0.070*sl t f 0.35 0.18 + 0.081*sl 0.19 + 0.078*sl 0.18 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-494 sec asic ymx2/ymx2d2 fast 2 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 ymx2 ymx2d2 ymx2 ymx2d2 d0d1sd0d1s 2.2 2.2 1.2 2.2 2.2 0.9 2.7 3.0 stdm80 ymx2 ymx2d2 ymx2 ymx2d2 d0d1sd0d1s 2.5 2.5 1.2 2.5 0.7 1.2 2.7 3.0 d0 d1 y s y d0 d1 s truth table d0 d1 s y 0x00 1x01 x010 x111
sec asic 3-495 STD80/stdm80 ymx2/ymx2d2 fast 2 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ymx2 STD80 ymx2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.26 0.21 + 0.026*sl 0.22 + 0.024*sl 0.22 + 0.024*sl t phl 0.36 0.28 + 0.039*sl 0.28 + 0.037*sl 0.28 + 0.037*sl t r 0.19 0.11 + 0.043*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.063*sl 0.08 + 0.067*sl 0.07 + 0.069*sl d1 to y t plh 0.26 0.21 + 0.026*sl 0.22 + 0.024*sl 0.22 + 0.024*sl t phl 0.36 0.28 + 0.039*sl 0.28 + 0.037*sl 0.28 + 0.037*sl t r 0.19 0.11 + 0.042*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl s to y t plh 0.34 0.28 + 0.026*sl 0.29 + 0.024*sl 0.29 + 0.024*sl t phl 0.36 0.28 + 0.039*sl 0.29 + 0.037*sl 0.29 + 0.037*sl t r 0.18 0.09 + 0.045*sl 0.08 + 0.050*sl 0.06 + 0.052*sl t f 0.21 0.08 + 0.066*sl 0.08 + 0.068*sl 0.06 + 0.069*sl *g 1 sl 2 *g 2 2 sl 10 *g 3 10 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.28 0.25 + 0.017*sl 0.25 + 0.013*sl 0.26 + 0.012*sl t phl 0.36 0.31 + 0.022*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.15 0.11 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.09 + 0.032*sl 0.07 + 0.034*sl d1 to y t plh 0.28 0.25 + 0.016*sl 0.25 + 0.013*sl 0.26 + 0.012*sl t phl 0.36 0.31 + 0.022*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.09 + 0.031*sl 0.09 + 0.031*sl 0.07 + 0.034*sl s to y t plh 0.34 0.31 + 0.018*sl 0.32 + 0.013*sl 0.33 + 0.012*sl t phl 0.36 0.31 + 0.022*sl 0.32 + 0.019*sl 0.33 + 0.018*sl t r 0.14 0.11 + 0.014*sl 0.09 + 0.024*sl 0.07 + 0.026*sl t f 0.15 0.09 + 0.032*sl 0.09 + 0.032*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-496 sec asic ymx2/ymx2d2 fast 2 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ymx2 stdm80 ymx2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.37 0.30 + 0.035*sl 0.31 + 0.033*sl 0.31 + 0.033*sl t phl 0.47 0.38 + 0.048*sl 0.38 + 0.045*sl 0.39 + 0.044*sl t r 0.25 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.11 + 0.081*sl 0.10 + 0.083*sl d1 to y t plh 0.37 0.30 + 0.035*sl 0.31 + 0.034*sl 0.31 + 0.033*sl t phl 0.47 0.37 + 0.048*sl 0.38 + 0.045*sl 0.38 + 0.044*sl t r 0.25 0.12 + 0.067*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl s to y t plh 0.49 0.42 + 0.035*sl 0.43 + 0.034*sl 0.43 + 0.033*sl t phl 0.60 0.51 + 0.048*sl 0.52 + 0.045*sl 0.52 + 0.044*sl t r 0.25 0.12 + 0.067*sl 0.11 + 0.071*sl 0.10 + 0.072*sl t f 0.27 0.11 + 0.080*sl 0.11 + 0.082*sl 0.10 + 0.083*sl *g 1 sl 3 *g 2 3 sl 7 *g 3 7 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.38 0.34 + 0.021*sl 0.35 + 0.018*sl 0.36 + 0.017*sl t phl 0.47 0.41 + 0.028*sl 0.43 + 0.024*sl 0.44 + 0.022*sl t r 0.18 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.20 0.12 + 0.037*sl 0.12 + 0.038*sl 0.12 + 0.039*sl d1 to y t plh 0.38 0.34 + 0.022*sl 0.35 + 0.018*sl 0.36 + 0.017*sl t phl 0.47 0.41 + 0.029*sl 0.42 + 0.024*sl 0.44 + 0.022*sl t r 0.18 0.12 + 0.031*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.20 0.12 + 0.038*sl 0.12 + 0.038*sl 0.12 + 0.038*sl s to y t plh 0.50 0.45 + 0.022*sl 0.46 + 0.018*sl 0.47 + 0.017*sl t phl 0.60 0.55 + 0.028*sl 0.56 + 0.024*sl 0.57 + 0.022*sl t r 0.18 0.11 + 0.033*sl 0.11 + 0.034*sl 0.10 + 0.035*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.11 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-497 STD80/stdm80 mx2i/mx2id2 2 > 1 inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 mx2i mx2id2 mx2i mx2id2 d0d1sd0d1s 0.5 0.9 1.5 0.7 0.6 1.0 2.3 3.7 stdm80 mx2i mx2id2 mx2i mx2id2 d0d1sd0d1s 1.0 1.0 1.6 0.7 0.7 1.6 2.3 3.7 d0 d1 yn s yn d0 s d1 truth table d0 d1 s yn 0x01 1x00 x011 x110
STD80/stdm80 3-498 sec asic mx2i/mx2id2 2 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx2i STD80 mx2id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.24 0.15 + 0.044*sl 0.16 + 0.040*sl 0.15 + 0.041*sl t phl 0.26 0.14 + 0.057*sl 0.15 + 0.055*sl 0.15 + 0.055*sl t r 0.46 0.30 + 0.079*sl 0.28 + 0.088*sl 0.21 + 0.095*sl t f 0.42 0.22 + 0.097*sl 0.20 + 0.106*sl 0.16 + 0.111*sl d1 to yn t plh 0.25 0.15 + 0.047*sl 0.17 + 0.042*sl 0.17 + 0.041*sl t phl 0.42 0.31 + 0.055*sl 0.31 + 0.055*sl 0.31 + 0.055*sl t r 0.40 0.24 + 0.080*sl 0.22 + 0.090*sl 0.17 + 0.095*sl t f 0.60 0.39 + 0.102*sl 0.38 + 0.107*sl 0.35 + 0.111*sl s to yn t plh 0.25 0.16 + 0.043*sl 0.17 + 0.041*sl 0.16 + 0.041*sl t phl 0.39 0.28 + 0.056*sl 0.28 + 0.055*sl 0.28 + 0.055*sl t r 0.43 0.26 + 0.081*sl 0.24 + 0.091*sl 0.21 + 0.095*sl t f 0.35 0.14 + 0.107*sl 0.13 + 0.109*sl 0.12 + 0.111*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.44 0.41 + 0.016*sl 0.42 + 0.013*sl 0.43 + 0.012*sl t phl 0.46 0.42 + 0.022*sl 0.42 + 0.019*sl 0.43 + 0.018*sl t r 0.14 0.10 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.15 0.09 + 0.030*sl 0.09 + 0.032*sl 0.07 + 0.034*sl d1 to yn t plh 0.44 0.41 + 0.016*sl 0.42 + 0.013*sl 0.43 + 0.012*sl t phl 0.46 0.41 + 0.022*sl 0.42 + 0.019*sl 0.43 + 0.018*sl t r 0.14 0.10 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.15 0.09 + 0.031*sl 0.09 + 0.032*sl 0.07 + 0.034*sl s to yn t plh 0.42 0.38 + 0.017*sl 0.39 + 0.013*sl 0.40 + 0.012*sl t phl 0.48 0.44 + 0.022*sl 0.45 + 0.019*sl 0.46 + 0.018*sl t r 0.14 0.10 + 0.023*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.09 + 0.034*sl 0.09 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-499 STD80/stdm80 mx2i/mx2id2 2 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx2i stdm80 mx2id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.32 0.20 + 0.062*sl 0.19 + 0.063*sl 0.19 + 0.063*sl t phl 0.33 0.19 + 0.074*sl 0.19 + 0.072*sl 0.20 + 0.072*sl t r 0.59 0.33 + 0.131*sl 0.32 + 0.136*sl 0.29 + 0.139*sl t f 0.52 0.24 + 0.137*sl 0.23 + 0.140*sl 0.22 + 0.142*sl d1 to yn t plh 0.38 0.25 + 0.066*sl 0.25 + 0.064*sl 0.26 + 0.063*sl t phl 0.54 0.39 + 0.075*sl 0.40 + 0.073*sl 0.40 + 0.072*sl t r 0.55 0.29 + 0.130*sl 0.27 + 0.136*sl 0.25 + 0.139*sl t f 0.74 0.46 + 0.140*sl 0.45 + 0.142*sl 0.45 + 0.142*sl s to yn t plh 0.38 0.25 + 0.064*sl 0.25 + 0.063*sl 0.26 + 0.063*sl t phl 0.51 0.36 + 0.074*sl 0.37 + 0.072*sl 0.37 + 0.071*sl t r 0.59 0.32 + 0.134*sl 0.31 + 0.138*sl 0.30 + 0.139*sl t f 0.47 0.19 + 0.138*sl 0.18 + 0.141*sl 0.18 + 0.142*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.60 0.56 + 0.022*sl 0.57 + 0.018*sl 0.58 + 0.017*sl t phl 0.62 0.56 + 0.028*sl 0.58 + 0.024*sl 0.59 + 0.022*sl t r 0.19 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.038*sl 0.12 + 0.039*sl d1 to yn t plh 0.61 0.56 + 0.022*sl 0.57 + 0.018*sl 0.58 + 0.017*sl t phl 0.62 0.56 + 0.028*sl 0.57 + 0.024*sl 0.59 + 0.022*sl t r 0.19 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.038*sl 0.12 + 0.039*sl s to yn t plh 0.58 0.53 + 0.022*sl 0.54 + 0.018*sl 0.55 + 0.017*sl t phl 0.66 0.60 + 0.028*sl 0.61 + 0.024*sl 0.63 + 0.022*sl t r 0.19 0.12 + 0.033*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.038*sl 0.11 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-500 sec asic mx2ia/mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 mx2ia mx2id2a mx2ia mx2id2a d0 d1 s sn d0 d1 s sn 0.6 0.9 0.9 0.5 0.6 0.6 0.4 0.4 1.7 3.3 stdm80 mx2ia mx2id2a mx2ia mx2id2a d0 d1 s sn d0 d1 s sn 0.8 0.9 0.8 0.9 0.7 0.7 0.8 0.6 1.7 3.3 yn d0 d1 s sn yn d0 sn d1 s truth table d0 d1 s sn yn 0 x 011 1 x 010 x 0 101 x 1 100
sec asic 3-501 STD80/stdm80 mx2ia/mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx2ia STD80 mx2id2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.21 0.11 + 0.049*sl 0.13 + 0.041*sl 0.12 + 0.041*sl t phl 0.27 0.16 + 0.058*sl 0.16 + 0.054*sl 0.16 + 0.055*sl t r 0.42 0.26 + 0.078*sl 0.24 + 0.088*sl 0.17 + 0.095*sl t f 0.39 0.20 + 0.094*sl 0.17 + 0.105*sl 0.12 + 0.111*sl d1 to yn t plh 0.28 0.19 + 0.044*sl 0.20 + 0.041*sl 0.19 + 0.041*sl t phl 0.40 0.29 + 0.055*sl 0.29 + 0.055*sl 0.29 + 0.055*sl t r 0.44 0.28 + 0.081*sl 0.26 + 0.090*sl 0.21 + 0.095*sl t f 0.59 0.38 + 0.106*sl 0.38 + 0.108*sl 0.35 + 0.111*sl s to yn t plh 0.24 0.15 + 0.046*sl 0.16 + 0.041*sl 0.16 + 0.041*sl t phl 0.37 0.26 + 0.054*sl 0.26 + 0.055*sl 0.26 + 0.055*sl t r 0.40 0.24 + 0.080*sl 0.22 + 0.089*sl 0.17 + 0.095*sl t f 0.60 0.40 + 0.100*sl 0.38 + 0.106*sl 0.34 + 0.111*sl sn to yn t plh 0.24 0.15 + 0.046*sl 0.16 + 0.041*sl 0.16 + 0.041*sl t phl 0.37 0.26 + 0.054*sl 0.26 + 0.055*sl 0.26 + 0.055*sl t r 0.40 0.24 + 0.080*sl 0.22 + 0.089*sl 0.17 + 0.095*sl t f 0.60 0.40 + 0.100*sl 0.38 + 0.106*sl 0.34 + 0.111*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.44 0.41 + 0.015*sl 0.42 + 0.013*sl 0.43 + 0.012*sl t phl 0.46 0.42 + 0.022*sl 0.42 + 0.019*sl 0.43 + 0.018*sl t r 0.14 0.10 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.15 0.09 + 0.029*sl 0.09 + 0.032*sl 0.07 + 0.034*sl d1 to yn t plh 0.44 0.41 + 0.016*sl 0.42 + 0.013*sl 0.43 + 0.012*sl t phl 0.46 0.42 + 0.022*sl 0.42 + 0.019*sl 0.43 + 0.018*sl t r 0.14 0.10 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.09 + 0.032*sl 0.09 + 0.031*sl 0.07 + 0.034*sl s to yn t plh 0.38 0.35 + 0.017*sl 0.36 + 0.013*sl 0.37 + 0.012*sl t phl 0.40 0.35 + 0.022*sl 0.36 + 0.019*sl 0.37 + 0.018*sl t r 0.14 0.10 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.09 + 0.033*sl 0.09 + 0.031*sl 0.07 + 0.034*sl sn to yn t plh 0.38 0.35 + 0.017*sl 0.36 + 0.013*sl 0.37 + 0.012*sl t phl 0.40 0.35 + 0.022*sl 0.36 + 0.019*sl 0.37 + 0.018*sl t r 0.14 0.10 + 0.020*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.16 0.09 + 0.033*sl 0.09 + 0.031*sl 0.07 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-502 sec asic mx2ia/mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx2ia stdm80 mx2id2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.28 0.15 + 0.062*sl 0.15 + 0.063*sl 0.15 + 0.063*sl t phl 0.34 0.19 + 0.072*sl 0.19 + 0.072*sl 0.20 + 0.071*sl t r 0.54 0.28 + 0.130*sl 0.26 + 0.135*sl 0.24 + 0.139*sl t f 0.47 0.20 + 0.134*sl 0.19 + 0.140*sl 0.16 + 0.143*sl d1 to yn t plh 0.42 0.29 + 0.065*sl 0.30 + 0.063*sl 0.30 + 0.063*sl t phl 0.53 0.38 + 0.076*sl 0.39 + 0.073*sl 0.39 + 0.072*sl t r 0.60 0.33 + 0.132*sl 0.32 + 0.137*sl 0.31 + 0.139*sl t f 0.74 0.46 + 0.141*sl 0.45 + 0.142*sl 0.45 + 0.142*sl s to yn t plh 0.36 0.23 + 0.065*sl 0.24 + 0.063*sl 0.24 + 0.063*sl t phl 0.47 0.32 + 0.074*sl 0.33 + 0.073*sl 0.33 + 0.072*sl t r 0.55 0.29 + 0.130*sl 0.27 + 0.136*sl 0.25 + 0.138*sl t f 0.73 0.45 + 0.139*sl 0.44 + 0.142*sl 0.43 + 0.143*sl sn to yn t plh 0.36 0.23 + 0.065*sl 0.24 + 0.063*sl 0.24 + 0.063*sl t phl 0.47 0.32 + 0.074*sl 0.33 + 0.073*sl 0.33 + 0.072*sl t r 0.55 0.29 + 0.130*sl 0.27 + 0.136*sl 0.25 + 0.138*sl t f 0.73 0.45 + 0.139*sl 0.44 + 0.142*sl 0.43 + 0.143*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.61 0.56 + 0.022*sl 0.57 + 0.018*sl 0.58 + 0.017*sl t phl 0.62 0.56 + 0.028*sl 0.58 + 0.024*sl 0.59 + 0.022*sl t r 0.19 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.038*sl 0.12 + 0.039*sl d1 to yn t plh 0.61 0.56 + 0.022*sl 0.57 + 0.018*sl 0.58 + 0.017*sl t phl 0.62 0.56 + 0.028*sl 0.57 + 0.024*sl 0.59 + 0.022*sl t r 0.19 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.038*sl 0.12 + 0.039*sl s to yn t plh 0.52 0.47 + 0.022*sl 0.49 + 0.018*sl 0.50 + 0.017*sl t phl 0.54 0.49 + 0.028*sl 0.50 + 0.024*sl 0.51 + 0.022*sl t r 0.19 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.20 0.11 + 0.041*sl 0.13 + 0.037*sl 0.12 + 0.039*sl sn to yn t plh 0.52 0.47 + 0.022*sl 0.49 + 0.018*sl 0.50 + 0.017*sl t phl 0.54 0.49 + 0.028*sl 0.50 + 0.024*sl 0.51 + 0.022*sl t r 0.19 0.12 + 0.032*sl 0.12 + 0.033*sl 0.11 + 0.034*sl t f 0.20 0.11 + 0.041*sl 0.13 + 0.037*sl 0.12 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-503 STD80/stdm80 mx2ix4 4-bit 2 > 1 inverting mux logic symbol cell data input load (sl) gate count STD80 mx2ix4 mx2ix4 d00 d10 d01 d11 d02 d12 d03 d13 s 0.9 0.8 0.9 0.8 0.9 0.8 0.9 0.8 3.5 7.3 stdm80 mx2ix4 mx2ix4 d00 d10 d01 d11 d02 d12 d03 d13 s 1.0 0.9 1.0 0.9 1.0 0.9 1.0 0.9 4.7 7.3 yn0 yn1 yn2 yn3 d00 d10 d01 d11 d02 d12 d03 d13 s truth table s yn0 yn1 yn2 yn3 0 d00 d01 d02 d03 1 d10 d11 d12 d13
STD80/stdm80 3-504 sec asic mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx2ix4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to yn0 t plh 0.19 0.11 + 0.039*sl 0.13 + 0.032*sl 0.13 + 0.032*sl t phl 0.25 0.14 + 0.056*sl 0.14 + 0.054*sl 0.13 + 0.055*sl t r 0.36 0.25 + 0.056*sl 0.23 + 0.064*sl 0.15 + 0.072*sl t f 0.38 0.19 + 0.097*sl 0.17 + 0.106*sl 0.13 + 0.111*sl d10 to yn0 t plh 0.24 0.16 + 0.037*sl 0.18 + 0.032*sl 0.18 + 0.032*sl t phl 0.40 0.29 + 0.055*sl 0.29 + 0.055*sl 0.29 + 0.055*sl t r 0.40 0.29 + 0.058*sl 0.27 + 0.066*sl 0.21 + 0.072*sl t f 0.60 0.39 + 0.105*sl 0.38 + 0.108*sl 0.35 + 0.111*sl s to yn0 t plh 0.42 0.33 + 0.044*sl 0.34 + 0.041*sl 0.34 + 0.041*sl t phl 0.55 0.43 + 0.059*sl 0.44 + 0.055*sl 0.44 + 0.055*sl t r 0.42 0.24 + 0.086*sl 0.23 + 0.091*sl 0.19 + 0.095*sl t f 0.39 0.19 + 0.102*sl 0.18 + 0.106*sl 0.14 + 0.110*sl d01 to yn1 t plh 0.19 0.11 + 0.039*sl 0.13 + 0.032*sl 0.13 + 0.032*sl t phl 0.25 0.14 + 0.056*sl 0.14 + 0.054*sl 0.13 + 0.055*sl t r 0.36 0.25 + 0.057*sl 0.23 + 0.063*sl 0.15 + 0.072*sl t f 0.38 0.19 + 0.097*sl 0.17 + 0.106*sl 0.13 + 0.111*sl d11 to yn1 t plh 0.24 0.16 + 0.037*sl 0.17 + 0.032*sl 0.18 + 0.032*sl t phl 0.40 0.29 + 0.056*sl 0.29 + 0.055*sl 0.29 + 0.055*sl t r 0.40 0.29 + 0.060*sl 0.27 + 0.066*sl 0.21 + 0.072*sl t f 0.60 0.39 + 0.105*sl 0.38 + 0.108*sl 0.35 + 0.111*sl s to yn1 t plh 0.42 0.33 + 0.044*sl 0.34 + 0.041*sl 0.34 + 0.041*sl t phl 0.55 0.43 + 0.059*sl 0.44 + 0.055*sl 0.44 + 0.055*sl t r 0.42 0.24 + 0.086*sl 0.23 + 0.091*sl 0.19 + 0.095*sl t f 0.39 0.19 + 0.102*sl 0.18 + 0.106*sl 0.14 + 0.110*sl d02 to yn2 t plh 0.19 0.11 + 0.039*sl 0.13 + 0.032*sl 0.13 + 0.032*sl t phl 0.25 0.14 + 0.056*sl 0.14 + 0.054*sl 0.13 + 0.055*sl t r 0.36 0.25 + 0.057*sl 0.23 + 0.063*sl 0.15 + 0.072*sl t f 0.38 0.19 + 0.097*sl 0.17 + 0.106*sl 0.13 + 0.111*sl d12 to yn2 t plh 0.24 0.16 + 0.038*sl 0.18 + 0.032*sl 0.18 + 0.032*sl t phl 0.40 0.29 + 0.056*sl 0.29 + 0.055*sl 0.29 + 0.055*sl t r 0.40 0.29 + 0.059*sl 0.27 + 0.066*sl 0.21 + 0.072*sl t f 0.60 0.39 + 0.105*sl 0.38 + 0.108*sl 0.35 + 0.111*sl s to yn2 t plh 0.42 0.33 + 0.044*sl 0.34 + 0.041*sl 0.34 + 0.041*sl t phl 0.55 0.43 + 0.059*sl 0.44 + 0.055*sl 0.44 + 0.055*sl t r 0.42 0.24 + 0.086*sl 0.23 + 0.091*sl 0.19 + 0.095*sl t f 0.39 0.19 + 0.102*sl 0.18 + 0.106*sl 0.14 + 0.110*sl d03 to yn3 t plh 0.19 0.11 + 0.039*sl 0.13 + 0.032*sl 0.13 + 0.032*sl t phl 0.25 0.14 + 0.056*sl 0.14 + 0.054*sl 0.13 + 0.055*sl t r 0.36 0.25 + 0.056*sl 0.23 + 0.064*sl 0.15 + 0.072*sl t f 0.38 0.19 + 0.097*sl 0.17 + 0.106*sl 0.13 + 0.111*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-505 STD80/stdm80 mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx2ix4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to yn3 t plh 0.24 0.16 + 0.037*sl 0.18 + 0.032*sl 0.18 + 0.032*sl t phl 0.40 0.29 + 0.055*sl 0.29 + 0.055*sl 0.29 + 0.055*sl t r 0.40 0.29 + 0.058*sl 0.27 + 0.066*sl 0.21 + 0.072*sl t f 0.60 0.39 + 0.105*sl 0.38 + 0.108*sl 0.35 + 0.111*sl s to yn3 t plh 0.42 0.33 + 0.044*sl 0.34 + 0.041*sl 0.34 + 0.041*sl t phl 0.55 0.43 + 0.059*sl 0.44 + 0.055*sl 0.44 + 0.055*sl t r 0.42 0.24 + 0.086*sl 0.23 + 0.091*sl 0.19 + 0.095*sl t f 0.39 0.19 + 0.102*sl 0.18 + 0.106*sl 0.14 + 0.110*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-506 sec asic mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx2ix4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to yn0 t plh 0.26 0.16 + 0.048*sl 0.16 + 0.047*sl 0.16 + 0.047*sl t phl 0.32 0.18 + 0.074*sl 0.18 + 0.072*sl 0.19 + 0.072*sl t r 0.43 0.25 + 0.093*sl 0.23 + 0.099*sl 0.20 + 0.103*sl t f 0.47 0.20 + 0.137*sl 0.19 + 0.141*sl 0.18 + 0.142*sl d10 to yn0 t plh 0.35 0.25 + 0.050*sl 0.25 + 0.049*sl 0.26 + 0.048*sl t phl 0.53 0.38 + 0.076*sl 0.39 + 0.073*sl 0.39 + 0.072*sl t r 0.52 0.32 + 0.097*sl 0.31 + 0.101*sl 0.29 + 0.104*sl t f 0.74 0.46 + 0.140*sl 0.46 + 0.141*sl 0.45 + 0.142*sl s to yn0 t plh 0.56 0.43 + 0.066*sl 0.44 + 0.063*sl 0.44 + 0.063*sl t phl 0.74 0.58 + 0.079*sl 0.60 + 0.072*sl 0.61 + 0.071*sl t r 0.58 0.31 + 0.134*sl 0.31 + 0.136*sl 0.29 + 0.138*sl t f 0.52 0.25 + 0.135*sl 0.25 + 0.137*sl 0.22 + 0.140*sl d01 to yn1 t plh 0.26 0.16 + 0.048*sl 0.16 + 0.047*sl 0.16 + 0.047*sl t phl 0.32 0.18 + 0.074*sl 0.18 + 0.072*sl 0.19 + 0.072*sl t r 0.43 0.25 + 0.093*sl 0.23 + 0.099*sl 0.20 + 0.103*sl t f 0.47 0.20 + 0.137*sl 0.19 + 0.141*sl 0.18 + 0.142*sl d11 to yn1 t plh 0.35 0.25 + 0.050*sl 0.25 + 0.048*sl 0.25 + 0.048*sl t phl 0.53 0.38 + 0.076*sl 0.39 + 0.073*sl 0.40 + 0.072*sl t r 0.52 0.32 + 0.097*sl 0.31 + 0.101*sl 0.29 + 0.104*sl t f 0.74 0.46 + 0.140*sl 0.46 + 0.141*sl 0.45 + 0.142*sl s to yn1 t plh 0.56 0.43 + 0.066*sl 0.44 + 0.063*sl 0.44 + 0.063*sl t phl 0.74 0.58 + 0.078*sl 0.60 + 0.072*sl 0.61 + 0.071*sl t r 0.58 0.31 + 0.134*sl 0.31 + 0.136*sl 0.29 + 0.138*sl t f 0.52 0.25 + 0.135*sl 0.25 + 0.137*sl 0.22 + 0.140*sl d02 to yn2 t plh 0.26 0.16 + 0.048*sl 0.16 + 0.047*sl 0.16 + 0.047*sl t phl 0.32 0.18 + 0.074*sl 0.18 + 0.072*sl 0.19 + 0.072*sl t r 0.43 0.25 + 0.093*sl 0.23 + 0.099*sl 0.20 + 0.103*sl t f 0.47 0.20 + 0.137*sl 0.19 + 0.141*sl 0.18 + 0.142*sl d12 to yn2 t plh 0.35 0.25 + 0.050*sl 0.25 + 0.048*sl 0.25 + 0.048*sl t phl 0.53 0.38 + 0.076*sl 0.39 + 0.073*sl 0.40 + 0.072*sl t r 0.52 0.32 + 0.097*sl 0.31 + 0.101*sl 0.29 + 0.104*sl t f 0.74 0.46 + 0.140*sl 0.46 + 0.141*sl 0.45 + 0.142*sl s to yn2 t plh 0.56 0.43 + 0.066*sl 0.44 + 0.063*sl 0.44 + 0.063*sl t phl 0.74 0.58 + 0.079*sl 0.60 + 0.072*sl 0.61 + 0.071*sl t r 0.58 0.31 + 0.134*sl 0.31 + 0.136*sl 0.29 + 0.138*sl t f 0.52 0.25 + 0.135*sl 0.25 + 0.137*sl 0.22 + 0.140*sl d03 to yn3 t plh 0.26 0.16 + 0.048*sl 0.16 + 0.047*sl 0.16 + 0.047*sl t phl 0.32 0.18 + 0.074*sl 0.18 + 0.072*sl 0.19 + 0.072*sl t r 0.43 0.25 + 0.093*sl 0.23 + 0.099*sl 0.20 + 0.103*sl t f 0.47 0.20 + 0.137*sl 0.19 + 0.141*sl 0.18 + 0.142*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-507 STD80/stdm80 mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx2ix4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to yn3 t plh 0.35 0.25 + 0.050*sl 0.25 + 0.049*sl 0.26 + 0.048*sl t phl 0.53 0.38 + 0.076*sl 0.39 + 0.073*sl 0.39 + 0.072*sl t r 0.52 0.32 + 0.097*sl 0.31 + 0.101*sl 0.29 + 0.104*sl t f 0.74 0.46 + 0.140*sl 0.46 + 0.142*sl 0.45 + 0.142*sl s to yn3 t plh 0.56 0.43 + 0.066*sl 0.44 + 0.063*sl 0.44 + 0.063*sl t phl 0.74 0.58 + 0.079*sl 0.60 + 0.072*sl 0.61 + 0.071*sl t r 0.58 0.31 + 0.134*sl 0.31 + 0.136*sl 0.29 + 0.138*sl t f 0.52 0.25 + 0.135*sl 0.25 + 0.137*sl 0.22 + 0.140*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-508 sec asic mx3i/mx3id2 3 > 1 inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 mx3i mx3id2 mx3i mx3id2 d0 d1 d2 s0 s1 d0 d1 d2 s0 s1 0.7 0.6 0.6 1.0 1.0 0.7 0.6 0.7 1.0 1.0 5.3 5.7 stdm80 mx3i mx3id2 mx3i mx3id2 d0 d1 d2 s0 s1 d0 d1 d2 s0 s1 0.7 0.7 0.7 1.6 1.5 0.7 0.7 0.7 1.6 1.5 5.3 5.7 d0 d1 d2 yn s0 s1 d0 d1 s0 s1 d2 yn truth table s0 s1 yn 00 d0 10 d1 x1 d2
sec asic 3-509 STD80/stdm80 mx3i/mx3id2 3 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx3i STD80 mx3id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.56 0.51 + 0.027*sl 0.52 + 0.024*sl 0.52 + 0.024*sl t phl 0.61 0.53 + 0.039*sl 0.54 + 0.037*sl 0.54 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.09 + 0.067*sl 0.07 + 0.069*sl d1 to yn t plh 0.57 0.51 + 0.026*sl 0.52 + 0.024*sl 0.52 + 0.024*sl t phl 0.61 0.53 + 0.039*sl 0.53 + 0.037*sl 0.54 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.22 0.09 + 0.064*sl 0.08 + 0.067*sl 0.07 + 0.069*sl d2 to yn t plh 0.43 0.38 + 0.026*sl 0.38 + 0.024*sl 0.38 + 0.024*sl t phl 0.46 0.38 + 0.039*sl 0.38 + 0.037*sl 0.39 + 0.037*sl t r 0.18 0.09 + 0.047*sl 0.09 + 0.050*sl 0.06 + 0.052*sl t f 0.22 0.10 + 0.060*sl 0.08 + 0.068*sl 0.06 + 0.069*sl s0 to yn t plh 0.53 0.47 + 0.027*sl 0.48 + 0.024*sl 0.48 + 0.024*sl t phl 0.62 0.54 + 0.039*sl 0.54 + 0.037*sl 0.54 + 0.037*sl t r 0.19 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.22 0.10 + 0.061*sl 0.08 + 0.067*sl 0.07 + 0.069*sl s1 to yn t plh 0.41 0.36 + 0.026*sl 0.36 + 0.024*sl 0.37 + 0.024*sl t phl 0.51 0.44 + 0.038*sl 0.44 + 0.037*sl 0.44 + 0.037*sl t r 0.19 0.10 + 0.046*sl 0.09 + 0.049*sl 0.06 + 0.052*sl t f 0.22 0.09 + 0.066*sl 0.09 + 0.067*sl 0.07 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.58 0.55 + 0.017*sl 0.56 + 0.013*sl 0.57 + 0.012*sl t phl 0.61 0.57 + 0.022*sl 0.58 + 0.019*sl 0.58 + 0.018*sl t r 0.16 0.12 + 0.021*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d1 to yn t plh 0.59 0.55 + 0.017*sl 0.56 + 0.013*sl 0.57 + 0.012*sl t phl 0.61 0.57 + 0.022*sl 0.57 + 0.019*sl 0.58 + 0.018*sl t r 0.16 0.12 + 0.022*sl 0.12 + 0.022*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.031*sl 0.07 + 0.034*sl d2 to yn t plh 0.44 0.41 + 0.016*sl 0.42 + 0.013*sl 0.43 + 0.012*sl t phl 0.46 0.41 + 0.022*sl 0.42 + 0.019*sl 0.43 + 0.018*sl t r 0.14 0.10 + 0.021*sl 0.10 + 0.023*sl 0.07 + 0.026*sl t f 0.15 0.10 + 0.029*sl 0.09 + 0.032*sl 0.07 + 0.034*sl s0 to yn t plh 0.55 0.51 + 0.017*sl 0.52 + 0.013*sl 0.53 + 0.012*sl t phl 0.62 0.58 + 0.022*sl 0.58 + 0.019*sl 0.59 + 0.018*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.022*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.029*sl 0.10 + 0.031*sl 0.07 + 0.034*sl s1 to yn t plh 0.43 0.40 + 0.017*sl 0.40 + 0.013*sl 0.42 + 0.012*sl t phl 0.52 0.47 + 0.022*sl 0.48 + 0.019*sl 0.49 + 0.018*sl t r 0.15 0.11 + 0.020*sl 0.11 + 0.023*sl 0.08 + 0.026*sl t f 0.16 0.10 + 0.031*sl 0.10 + 0.031*sl 0.07 + 0.034*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 10, *grou p 3 : 10 < sl < < = =
STD80/stdm80 3-510 sec asic mx3i/mx3id2 3 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx3i stdm80 mx3id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.82 0.75 + 0.037*sl 0.76 + 0.034*sl 0.76 + 0.033*sl t phl 0.84 0.74 + 0.049*sl 0.75 + 0.045*sl 0.75 + 0.044*sl t r 0.27 0.14 + 0.064*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.080*sl 0.11 + 0.082*sl d1 to yn t plh 0.83 0.75 + 0.037*sl 0.76 + 0.034*sl 0.77 + 0.033*sl t phl 0.83 0.73 + 0.049*sl 0.75 + 0.045*sl 0.75 + 0.044*sl t r 0.27 0.15 + 0.063*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.28 0.12 + 0.081*sl 0.12 + 0.080*sl 0.11 + 0.082*sl d2 to yn t plh 0.59 0.52 + 0.035*sl 0.53 + 0.034*sl 0.53 + 0.033*sl t phl 0.61 0.52 + 0.048*sl 0.53 + 0.045*sl 0.53 + 0.044*sl t r 0.26 0.12 + 0.066*sl 0.11 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.080*sl 0.11 + 0.081*sl 0.10 + 0.083*sl s0 to yn t plh 0.78 0.71 + 0.037*sl 0.72 + 0.034*sl 0.72 + 0.033*sl t phl 0.86 0.76 + 0.049*sl 0.77 + 0.045*sl 0.78 + 0.044*sl t r 0.27 0.14 + 0.064*sl 0.13 + 0.069*sl 0.11 + 0.071*sl t f 0.28 0.12 + 0.080*sl 0.12 + 0.080*sl 0.11 + 0.082*sl s1 to yn t plh 0.57 0.49 + 0.036*sl 0.50 + 0.034*sl 0.50 + 0.033*sl t phl 0.69 0.60 + 0.048*sl 0.61 + 0.045*sl 0.61 + 0.044*sl t r 0.26 0.13 + 0.067*sl 0.12 + 0.070*sl 0.10 + 0.072*sl t f 0.28 0.12 + 0.079*sl 0.12 + 0.080*sl 0.11 + 0.082*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.85 0.80 + 0.023*sl 0.82 + 0.019*sl 0.83 + 0.017*sl t phl 0.85 0.79 + 0.029*sl 0.80 + 0.024*sl 0.82 + 0.022*sl t r 0.21 0.15 + 0.031*sl 0.15 + 0.032*sl 0.13 + 0.033*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d1 to yn t plh 0.86 0.81 + 0.023*sl 0.82 + 0.019*sl 0.83 + 0.017*sl t phl 0.84 0.79 + 0.029*sl 0.80 + 0.024*sl 0.81 + 0.022*sl t r 0.21 0.15 + 0.030*sl 0.15 + 0.032*sl 0.13 + 0.033*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl d2 to yn t plh 0.61 0.56 + 0.022*sl 0.57 + 0.018*sl 0.59 + 0.017*sl t phl 0.62 0.56 + 0.029*sl 0.57 + 0.024*sl 0.59 + 0.022*sl t r 0.19 0.12 + 0.032*sl 0.12 + 0.033*sl 0.12 + 0.034*sl t f 0.19 0.12 + 0.039*sl 0.12 + 0.038*sl 0.11 + 0.039*sl s0 to yn t plh 0.81 0.77 + 0.023*sl 0.78 + 0.019*sl 0.79 + 0.017*sl t phl 0.87 0.81 + 0.029*sl 0.83 + 0.024*sl 0.84 + 0.022*sl t r 0.21 0.15 + 0.031*sl 0.14 + 0.032*sl 0.13 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.13 + 0.038*sl s1 to yn t plh 0.59 0.54 + 0.023*sl 0.55 + 0.019*sl 0.56 + 0.017*sl t phl 0.71 0.65 + 0.029*sl 0.66 + 0.024*sl 0.68 + 0.022*sl t r 0.20 0.14 + 0.030*sl 0.13 + 0.033*sl 0.12 + 0.034*sl t f 0.20 0.12 + 0.039*sl 0.13 + 0.038*sl 0.12 + 0.038*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-511 STD80/stdm80 mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 mx4 mx4d2 mx4 mx4d 2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 0.7 0.6 0.7 0.7 1.2 1.3 0.7 0.6 0.7 0.7 1.2 1.3 6.3 6.7 stdm80 mx4 mx4d2 mx4 mx4d 2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 0.7 0.7 0.7 0.7 2.5 1.5 0.7 0.7 0.7 0.7 2.5 1.5 6.3 6.7 y d0 d1 d2 d3 s0 s1 s0b s0 s0 s1b s1 s1 d0 d1 d2 d3 y s0 s0 s0b s0 s0b s1 s1b s1b s1 truth table s0 s1 y 00d0 10d1 01d2 11d3
STD80/stdm80 3-512 sec asic mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.46 0.39 + 0.036*sl 0.41 + 0.027*sl 0.44 + 0.024*sl t phl 0.59 0.48 + 0.050*sl 0.50 + 0.041*sl 0.55 + 0.037*sl t r 0.27 0.17 + 0.048*sl 0.17 + 0.047*sl 0.13 + 0.051*sl t f 0.34 0.20 + 0.066*sl 0.21 + 0.064*sl 0.17 + 0.069*sl d1 to y t plh 0.46 0.38 + 0.037*sl 0.41 + 0.027*sl 0.44 + 0.024*sl t phl 0.59 0.49 + 0.050*sl 0.51 + 0.041*sl 0.55 + 0.037*sl t r 0.27 0.18 + 0.045*sl 0.17 + 0.047*sl 0.13 + 0.051*sl t f 0.34 0.20 + 0.066*sl 0.21 + 0.065*sl 0.17 + 0.068*sl d2 to y t plh 0.46 0.38 + 0.036*sl 0.40 + 0.027*sl 0.44 + 0.024*sl t phl 0.59 0.48 + 0.050*sl 0.50 + 0.041*sl 0.55 + 0.037*sl t r 0.27 0.17 + 0.046*sl 0.17 + 0.047*sl 0.13 + 0.051*sl t f 0.33 0.20 + 0.065*sl 0.21 + 0.065*sl 0.17 + 0.069*sl d3 to y t plh 0.45 0.38 + 0.036*sl 0.40 + 0.027*sl 0.44 + 0.024*sl t phl 0.59 0.49 + 0.050*sl 0.51 + 0.041*sl 0.55 + 0.037*sl t r 0.27 0.17 + 0.047*sl 0.17 + 0.047*sl 0.13 + 0.051*sl t f 0.34 0.21 + 0.065*sl 0.21 + 0.065*sl 0.17 + 0.069*sl s0 to y t plh 0.50 0.42 + 0.037*sl 0.44 + 0.027*sl 0.48 + 0.024*sl t phl 0.57 0.47 + 0.050*sl 0.49 + 0.041*sl 0.54 + 0.037*sl t r 0.27 0.17 + 0.046*sl 0.17 + 0.047*sl 0.13 + 0.051*sl t f 0.33 0.20 + 0.065*sl 0.20 + 0.065*sl 0.17 + 0.069*sl s1 to y t plh 0.36 0.29 + 0.034*sl 0.31 + 0.027*sl 0.34 + 0.024*sl t phl 0.44 0.34 + 0.050*sl 0.36 + 0.042*sl 0.40 + 0.037*sl t r 0.24 0.14 + 0.048*sl 0.14 + 0.050*sl 0.12 + 0.052*sl t f 0.30 0.17 + 0.069*sl 0.17 + 0.067*sl 0.15 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-513 STD80/stdm80 mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.47 0.42 + 0.025*sl 0.44 + 0.017*sl 0.49 + 0.012*sl t phl 0.59 0.53 + 0.031*sl 0.54 + 0.024*sl 0.60 + 0.018*sl t r 0.24 0.19 + 0.026*sl 0.19 + 0.024*sl 0.18 + 0.025*sl t f 0.30 0.22 + 0.038*sl 0.23 + 0.032*sl 0.22 + 0.033*sl d1 to y t plh 0.47 0.42 + 0.024*sl 0.43 + 0.017*sl 0.49 + 0.012*sl t phl 0.59 0.53 + 0.032*sl 0.55 + 0.024*sl 0.60 + 0.018*sl t r 0.24 0.19 + 0.026*sl 0.19 + 0.024*sl 0.17 + 0.025*sl t f 0.30 0.22 + 0.037*sl 0.23 + 0.032*sl 0.22 + 0.033*sl d2 to y t plh 0.46 0.42 + 0.024*sl 0.43 + 0.017*sl 0.48 + 0.012*sl t phl 0.59 0.53 + 0.032*sl 0.54 + 0.024*sl 0.60 + 0.018*sl t r 0.24 0.18 + 0.027*sl 0.19 + 0.023*sl 0.17 + 0.025*sl t f 0.30 0.22 + 0.039*sl 0.23 + 0.032*sl 0.22 + 0.033*sl d3 to y t plh 0.46 0.41 + 0.024*sl 0.43 + 0.017*sl 0.48 + 0.012*sl t phl 0.59 0.53 + 0.031*sl 0.54 + 0.024*sl 0.60 + 0.018*sl t r 0.24 0.18 + 0.028*sl 0.19 + 0.024*sl 0.17 + 0.025*sl t f 0.30 0.22 + 0.038*sl 0.23 + 0.032*sl 0.22 + 0.033*sl s0 to y t plh 0.50 0.45 + 0.025*sl 0.47 + 0.017*sl 0.52 + 0.012*sl t phl 0.57 0.51 + 0.031*sl 0.53 + 0.024*sl 0.58 + 0.018*sl t r 0.24 0.19 + 0.025*sl 0.20 + 0.023*sl 0.17 + 0.025*sl t f 0.29 0.22 + 0.037*sl 0.23 + 0.032*sl 0.22 + 0.033*sl s1 to y t plh 0.37 0.32 + 0.023*sl 0.33 + 0.017*sl 0.38 + 0.012*sl t phl 0.44 0.37 + 0.032*sl 0.39 + 0.024*sl 0.45 + 0.018*sl t r 0.21 0.16 + 0.028*sl 0.16 + 0.025*sl 0.16 + 0.026*sl t f 0.27 0.19 + 0.039*sl 0.20 + 0.033*sl 0.20 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-514 sec asic mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.65 0.55 + 0.047*sl 0.57 + 0.040*sl 0.61 + 0.035*sl t phl 0.84 0.70 + 0.068*sl 0.74 + 0.056*sl 0.78 + 0.050*sl t r 0.35 0.21 + 0.071*sl 0.21 + 0.068*sl 0.21 + 0.069*sl t f 0.46 0.28 + 0.087*sl 0.30 + 0.080*sl 0.31 + 0.079*sl d1 to y t plh 0.64 0.55 + 0.047*sl 0.57 + 0.039*sl 0.60 + 0.035*sl t phl 0.84 0.71 + 0.067*sl 0.74 + 0.056*sl 0.79 + 0.050*sl t r 0.35 0.21 + 0.070*sl 0.22 + 0.068*sl 0.21 + 0.069*sl t f 0.46 0.29 + 0.086*sl 0.30 + 0.080*sl 0.31 + 0.079*sl d2 to y t plh 0.64 0.55 + 0.047*sl 0.57 + 0.040*sl 0.60 + 0.035*sl t phl 0.84 0.71 + 0.067*sl 0.74 + 0.056*sl 0.78 + 0.050*sl t r 0.35 0.21 + 0.070*sl 0.22 + 0.068*sl 0.21 + 0.069*sl t f 0.45 0.28 + 0.086*sl 0.30 + 0.080*sl 0.31 + 0.079*sl d3 to y t plh 0.64 0.54 + 0.047*sl 0.57 + 0.039*sl 0.59 + 0.035*sl t phl 0.84 0.71 + 0.067*sl 0.74 + 0.056*sl 0.79 + 0.050*sl t r 0.35 0.21 + 0.070*sl 0.21 + 0.068*sl 0.21 + 0.069*sl t f 0.46 0.28 + 0.087*sl 0.30 + 0.080*sl 0.31 + 0.079*sl s0 to y t plh 0.71 0.61 + 0.047*sl 0.64 + 0.040*sl 0.67 + 0.035*sl t phl 0.84 0.70 + 0.067*sl 0.74 + 0.056*sl 0.78 + 0.050*sl t r 0.35 0.21 + 0.070*sl 0.22 + 0.068*sl 0.21 + 0.069*sl t f 0.46 0.29 + 0.085*sl 0.30 + 0.080*sl 0.31 + 0.079*sl s1 to y t plh 0.50 0.41 + 0.046*sl 0.43 + 0.039*sl 0.45 + 0.035*sl t phl 0.61 0.47 + 0.067*sl 0.51 + 0.056*sl 0.55 + 0.049*sl t r 0.33 0.19 + 0.073*sl 0.20 + 0.069*sl 0.19 + 0.070*sl t f 0.42 0.23 + 0.091*sl 0.26 + 0.082*sl 0.27 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-515 STD80/stdm80 mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.66 0.60 + 0.031*sl 0.62 + 0.025*sl 0.65 + 0.021*sl t phl 0.86 0.77 + 0.043*sl 0.80 + 0.035*sl 0.83 + 0.029*sl t r 0.29 0.22 + 0.036*sl 0.22 + 0.035*sl 0.23 + 0.035*sl t f 0.40 0.30 + 0.048*sl 0.32 + 0.042*sl 0.34 + 0.039*sl d1 to y t plh 0.66 0.60 + 0.031*sl 0.62 + 0.025*sl 0.64 + 0.021*sl t phl 0.86 0.78 + 0.043*sl 0.80 + 0.035*sl 0.84 + 0.029*sl t r 0.29 0.22 + 0.035*sl 0.22 + 0.036*sl 0.23 + 0.034*sl t f 0.40 0.31 + 0.048*sl 0.32 + 0.042*sl 0.35 + 0.039*sl d2 to y t plh 0.65 0.59 + 0.031*sl 0.61 + 0.025*sl 0.64 + 0.021*sl t phl 0.85 0.77 + 0.043*sl 0.79 + 0.034*sl 0.83 + 0.029*sl t r 0.29 0.22 + 0.036*sl 0.22 + 0.036*sl 0.23 + 0.034*sl t f 0.40 0.30 + 0.048*sl 0.32 + 0.042*sl 0.34 + 0.040*sl d3 to y t plh 0.65 0.59 + 0.031*sl 0.61 + 0.025*sl 0.63 + 0.021*sl t phl 0.86 0.77 + 0.043*sl 0.80 + 0.034*sl 0.83 + 0.029*sl t r 0.29 0.22 + 0.036*sl 0.22 + 0.035*sl 0.23 + 0.034*sl t f 0.40 0.31 + 0.047*sl 0.32 + 0.042*sl 0.34 + 0.039*sl s0 to y t plh 0.72 0.66 + 0.031*sl 0.68 + 0.025*sl 0.70 + 0.021*sl t phl 0.86 0.77 + 0.043*sl 0.80 + 0.035*sl 0.84 + 0.029*sl t r 0.30 0.22 + 0.036*sl 0.23 + 0.035*sl 0.23 + 0.034*sl t f 0.40 0.30 + 0.048*sl 0.32 + 0.042*sl 0.34 + 0.040*sl s1 to y t plh 0.51 0.45 + 0.031*sl 0.47 + 0.024*sl 0.49 + 0.021*sl t phl 0.63 0.54 + 0.043*sl 0.56 + 0.035*sl 0.60 + 0.029*sl t r 0.27 0.20 + 0.037*sl 0.20 + 0.037*sl 0.22 + 0.035*sl t f 0.37 0.28 + 0.048*sl 0.29 + 0.044*sl 0.31 + 0.040*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-516 sec asic ymx4/ymx4d2 fast 4 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 ymx4 ymx4d2 ymx4 ymx4d2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 1.9 1.9 1.8 1.9 1.5 1.3 1.9 1.9 1.8 1.9 1.5 1.3 5.7 6.0 stdm80 ymx4 ymx4d2 ymx4 ymx4d2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 0.5 2.1 0.5 2.1 1.5 1.2 0.5 2.1 0.5 2.1 1.5 1.2 5.7 6.0 y d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 y s0 s1 truth table s0 s1 y 00d0 10d1 01d2 11d3
sec asic 3-517 STD80/stdm80 ymx4/ymx4d2 fast 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ymx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.38 0.33 + 0.029*sl 0.34 + 0.025*sl 0.35 + 0.024*sl t phl 0.49 0.40 + 0.044*sl 0.41 + 0.039*sl 0.43 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.064*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d1 to y t plh 0.39 0.32 + 0.032*sl 0.34 + 0.025*sl 0.35 + 0.024*sl t phl 0.49 0.40 + 0.044*sl 0.41 + 0.039*sl 0.43 + 0.037*sl t r 0.22 0.12 + 0.047*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.064*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d2 to y t plh 0.38 0.32 + 0.030*sl 0.33 + 0.025*sl 0.34 + 0.024*sl t phl 0.49 0.40 + 0.044*sl 0.41 + 0.039*sl 0.43 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d3 to y t plh 0.38 0.32 + 0.030*sl 0.34 + 0.025*sl 0.34 + 0.024*sl t phl 0.49 0.40 + 0.044*sl 0.41 + 0.039*sl 0.43 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl s0 to y t plh 0.50 0.44 + 0.029*sl 0.45 + 0.025*sl 0.46 + 0.024*sl t phl 0.46 0.37 + 0.044*sl 0.38 + 0.039*sl 0.40 + 0.037*sl t r 0.21 0.12 + 0.047*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.27 0.14 + 0.065*sl 0.14 + 0.065*sl 0.10 + 0.069*sl s1 to y t plh 0.32 0.27 + 0.029*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.40 0.31 + 0.044*sl 0.32 + 0.039*sl 0.34 + 0.037*sl t r 0.20 0.11 + 0.046*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.066*sl 0.10 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-518 sec asic ymx4/ymx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ymx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.40 0.36 + 0.020*sl 0.37 + 0.015*sl 0.40 + 0.012*sl t phl 0.50 0.44 + 0.028*sl 0.45 + 0.022*sl 0.49 + 0.018*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.23 0.17 + 0.032*sl 0.17 + 0.031*sl 0.15 + 0.033*sl d1 to y t plh 0.40 0.36 + 0.019*sl 0.37 + 0.015*sl 0.40 + 0.012*sl t phl 0.49 0.44 + 0.027*sl 0.45 + 0.022*sl 0.49 + 0.018*sl t r 0.18 0.14 + 0.022*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.23 0.17 + 0.032*sl 0.17 + 0.031*sl 0.14 + 0.033*sl d2 to y t plh 0.39 0.35 + 0.019*sl 0.36 + 0.015*sl 0.39 + 0.012*sl t phl 0.49 0.44 + 0.027*sl 0.45 + 0.022*sl 0.48 + 0.018*sl t r 0.18 0.14 + 0.022*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.23 0.16 + 0.033*sl 0.17 + 0.031*sl 0.14 + 0.033*sl d3 to y t plh 0.39 0.36 + 0.019*sl 0.37 + 0.015*sl 0.39 + 0.012*sl t phl 0.49 0.44 + 0.028*sl 0.45 + 0.021*sl 0.48 + 0.018*sl t r 0.18 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.23 0.16 + 0.034*sl 0.17 + 0.031*sl 0.15 + 0.033*sl s0 to y t plh 0.51 0.47 + 0.019*sl 0.48 + 0.015*sl 0.50 + 0.012*sl t phl 0.47 0.41 + 0.028*sl 0.42 + 0.022*sl 0.46 + 0.018*sl t r 0.18 0.13 + 0.023*sl 0.13 + 0.023*sl 0.11 + 0.026*sl t f 0.23 0.16 + 0.033*sl 0.17 + 0.031*sl 0.14 + 0.033*sl s1 to y t plh 0.33 0.29 + 0.019*sl 0.30 + 0.015*sl 0.33 + 0.012*sl t phl 0.40 0.34 + 0.027*sl 0.36 + 0.022*sl 0.39 + 0.018*sl t r 0.17 0.12 + 0.024*sl 0.12 + 0.024*sl 0.10 + 0.026*sl t f 0.22 0.15 + 0.034*sl 0.16 + 0.032*sl 0.14 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-519 STD80/stdm80 ymx4/ymx4d2 fast 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ymx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.55 0.47 + 0.040*sl 0.48 + 0.035*sl 0.50 + 0.033*sl t phl 0.69 0.57 + 0.058*sl 0.60 + 0.049*sl 0.63 + 0.046*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.36 0.21 + 0.079*sl 0.21 + 0.079*sl 0.20 + 0.079*sl d1 to y t plh 0.56 0.47 + 0.041*sl 0.49 + 0.035*sl 0.50 + 0.034*sl t phl 0.68 0.57 + 0.058*sl 0.59 + 0.049*sl 0.62 + 0.046*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.36 0.20 + 0.079*sl 0.21 + 0.079*sl 0.20 + 0.079*sl d2 to y t plh 0.54 0.46 + 0.040*sl 0.47 + 0.035*sl 0.49 + 0.034*sl t phl 0.69 0.57 + 0.058*sl 0.60 + 0.049*sl 0.62 + 0.046*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.36 0.20 + 0.081*sl 0.21 + 0.078*sl 0.20 + 0.080*sl d3 to y t plh 0.55 0.47 + 0.040*sl 0.48 + 0.035*sl 0.49 + 0.034*sl t phl 0.68 0.57 + 0.058*sl 0.59 + 0.049*sl 0.62 + 0.046*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.36 0.20 + 0.081*sl 0.21 + 0.078*sl 0.20 + 0.080*sl s0 to y t plh 0.69 0.61 + 0.041*sl 0.62 + 0.035*sl 0.64 + 0.034*sl t phl 0.90 0.78 + 0.059*sl 0.81 + 0.049*sl 0.83 + 0.046*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.36 0.20 + 0.081*sl 0.20 + 0.079*sl 0.20 + 0.080*sl s1 to y t plh 0.44 0.36 + 0.040*sl 0.38 + 0.035*sl 0.39 + 0.033*sl t phl 0.54 0.43 + 0.058*sl 0.46 + 0.049*sl 0.48 + 0.046*sl t r 0.29 0.15 + 0.069*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.35 0.18 + 0.083*sl 0.20 + 0.079*sl 0.19 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-520 sec asic ymx4/ymx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ymx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.56 0.51 + 0.026*sl 0.52 + 0.021*sl 0.54 + 0.019*sl t phl 0.70 0.63 + 0.037*sl 0.65 + 0.031*sl 0.68 + 0.026*sl t r 0.23 0.16 + 0.034*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.31 0.22 + 0.043*sl 0.23 + 0.040*sl 0.24 + 0.038*sl d1 to y t plh 0.57 0.51 + 0.026*sl 0.53 + 0.021*sl 0.55 + 0.019*sl t phl 0.70 0.62 + 0.037*sl 0.64 + 0.030*sl 0.67 + 0.026*sl t r 0.23 0.15 + 0.035*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.31 0.22 + 0.043*sl 0.23 + 0.040*sl 0.25 + 0.038*sl d2 to y t plh 0.55 0.50 + 0.025*sl 0.51 + 0.021*sl 0.53 + 0.019*sl t phl 0.70 0.62 + 0.037*sl 0.64 + 0.031*sl 0.68 + 0.026*sl t r 0.22 0.15 + 0.035*sl 0.15 + 0.035*sl 0.16 + 0.034*sl t f 0.31 0.22 + 0.044*sl 0.23 + 0.040*sl 0.25 + 0.038*sl d3 to y t plh 0.56 0.50 + 0.026*sl 0.52 + 0.021*sl 0.54 + 0.019*sl t phl 0.70 0.62 + 0.037*sl 0.64 + 0.030*sl 0.67 + 0.026*sl t r 0.22 0.15 + 0.036*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.31 0.22 + 0.043*sl 0.23 + 0.040*sl 0.24 + 0.038*sl s0 to y t plh 0.70 0.65 + 0.025*sl 0.66 + 0.021*sl 0.68 + 0.019*sl t phl 0.91 0.83 + 0.037*sl 0.86 + 0.030*sl 0.89 + 0.026*sl t r 0.22 0.15 + 0.036*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t f 0.30 0.22 + 0.044*sl 0.23 + 0.040*sl 0.24 + 0.038*sl s1 to y t plh 0.45 0.39 + 0.026*sl 0.41 + 0.021*sl 0.43 + 0.019*sl t phl 0.56 0.48 + 0.037*sl 0.50 + 0.031*sl 0.53 + 0.026*sl t r 0.22 0.15 + 0.035*sl 0.15 + 0.035*sl 0.16 + 0.034*sl t f 0.29 0.20 + 0.045*sl 0.22 + 0.040*sl 0.23 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-521 STD80/stdm80 mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count STD80 mx5 mx5d2 mx5 mx5d2 d0 d1 d2 d3 d4 s0 s1 s2 d0 d1 d2 d3 d4 s0 s1 s2 0.6 0.6 0.6 0.7 0.7 0.6 1.1 1.0 0.6 0.6 0.6 0.7 0.7 0.6 1.1 1.0 9.3 9.7 stdm80 mx5 mx5d2 mx5 mx5d2 d0 d1 d2 d3 d4 s0 s1 s2 d0 d1 d2 d3 d4 s0 s1 s2 0.8 0.7 0.7 0.7 0.8 0.8 1.5 1.5 0.8 0.7 0.7 0.7 0.8 0.8 1.5 1.5 9.3 9.7 y s0 s1 s2 d0 d1 d2 d3 d4 d0 d1 d2 d3 s0 s0b s0 s0b s0 s0 s0b s0 d4 s2 s2b s1b s1 s1 s1b s2b s2 y s1b s1 s1 s2b s2 s2 truth table s0 s1 s2 y 000d0 100d1 010d2 110d3 xx1d4
STD80/stdm80 3-522 sec asic mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.74 0.68 + 0.031*sl 0.69 + 0.025*sl 0.70 + 0.024*sl t phl 0.85 0.76 + 0.044*sl 0.77 + 0.039*sl 0.79 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.063*sl 0.13 + 0.065*sl 0.10 + 0.069*sl d1 to y t plh 0.74 0.68 + 0.030*sl 0.69 + 0.025*sl 0.70 + 0.024*sl t phl 0.85 0.76 + 0.044*sl 0.77 + 0.039*sl 0.79 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.063*sl 0.13 + 0.065*sl 0.10 + 0.069*sl d2 to y t plh 0.71 0.65 + 0.031*sl 0.66 + 0.025*sl 0.68 + 0.024*sl t phl 0.81 0.73 + 0.044*sl 0.74 + 0.039*sl 0.75 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.065*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d3 to y t plh 0.71 0.65 + 0.031*sl 0.66 + 0.025*sl 0.68 + 0.024*sl t phl 0.81 0.73 + 0.044*sl 0.74 + 0.039*sl 0.75 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.065*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d4 to y t plh 0.31 0.25 + 0.030*sl 0.27 + 0.025*sl 0.28 + 0.024*sl t phl 0.42 0.34 + 0.044*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.064*sl 0.13 + 0.065*sl 0.09 + 0.069*sl s0 to y t plh 0.86 0.80 + 0.030*sl 0.81 + 0.025*sl 0.83 + 0.024*sl t phl 0.91 0.82 + 0.044*sl 0.83 + 0.039*sl 0.85 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.26 0.14 + 0.064*sl 0.13 + 0.065*sl 0.10 + 0.069*sl s1 to y t plh 0.51 0.45 + 0.031*sl 0.47 + 0.025*sl 0.48 + 0.024*sl t phl 0.54 0.45 + 0.044*sl 0.46 + 0.039*sl 0.48 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl s2 to y t plh 0.34 0.28 + 0.028*sl 0.29 + 0.025*sl 0.30 + 0.024*sl t phl 0.39 0.31 + 0.044*sl 0.32 + 0.039*sl 0.33 + 0.037*sl t r 0.21 0.11 + 0.047*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.25 0.12 + 0.066*sl 0.12 + 0.066*sl 0.09 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-523 STD80/stdm80 mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.75 0.71 + 0.020*sl 0.72 + 0.015*sl 0.75 + 0.012*sl t phl 0.85 0.80 + 0.027*sl 0.81 + 0.021*sl 0.84 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.15 + 0.033*sl 0.16 + 0.031*sl 0.13 + 0.033*sl d1 to y t plh 0.75 0.71 + 0.021*sl 0.72 + 0.015*sl 0.75 + 0.012*sl t phl 0.85 0.80 + 0.027*sl 0.81 + 0.021*sl 0.84 + 0.018*sl t r 0.19 0.15 + 0.022*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.15 + 0.033*sl 0.16 + 0.031*sl 0.13 + 0.033*sl d2 to y t plh 0.72 0.68 + 0.021*sl 0.69 + 0.015*sl 0.72 + 0.012*sl t phl 0.82 0.76 + 0.027*sl 0.77 + 0.021*sl 0.81 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.15 + 0.033*sl 0.16 + 0.031*sl 0.13 + 0.033*sl d3 to y t plh 0.72 0.68 + 0.021*sl 0.69 + 0.015*sl 0.72 + 0.012*sl t phl 0.82 0.76 + 0.027*sl 0.77 + 0.021*sl 0.81 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.15 + 0.034*sl 0.16 + 0.031*sl 0.13 + 0.033*sl d4 to y t plh 0.32 0.29 + 0.018*sl 0.29 + 0.015*sl 0.32 + 0.012*sl t phl 0.43 0.38 + 0.026*sl 0.39 + 0.021*sl 0.41 + 0.018*sl t r 0.18 0.13 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.21 0.14 + 0.033*sl 0.15 + 0.031*sl 0.13 + 0.033*sl s0 to y t plh 0.87 0.83 + 0.021*sl 0.84 + 0.015*sl 0.87 + 0.012*sl t phl 0.91 0.86 + 0.027*sl 0.87 + 0.021*sl 0.90 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.15 + 0.034*sl 0.16 + 0.031*sl 0.13 + 0.033*sl s1 to y t plh 0.52 0.48 + 0.021*sl 0.49 + 0.015*sl 0.52 + 0.012*sl t phl 0.54 0.49 + 0.027*sl 0.50 + 0.022*sl 0.53 + 0.018*sl t r 0.19 0.14 + 0.025*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.16 + 0.032*sl 0.16 + 0.031*sl 0.13 + 0.033*sl s2 to y t plh 0.34 0.30 + 0.021*sl 0.31 + 0.015*sl 0.34 + 0.012*sl t phl 0.39 0.34 + 0.027*sl 0.35 + 0.021*sl 0.38 + 0.018*sl t r 0.18 0.13 + 0.024*sl 0.13 + 0.024*sl 0.11 + 0.026*sl t f 0.20 0.13 + 0.034*sl 0.14 + 0.032*sl 0.12 + 0.034*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-524 sec asic mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 1.07 0.98 + 0.042*sl 1.00 + 0.036*sl 1.01 + 0.034*sl t phl 1.21 1.10 + 0.058*sl 1.12 + 0.049*sl 1.15 + 0.046*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.35 0.19 + 0.082*sl 0.20 + 0.078*sl 0.19 + 0.080*sl d1 to y t plh 1.07 0.98 + 0.041*sl 1.00 + 0.036*sl 1.02 + 0.034*sl t phl 1.21 1.10 + 0.058*sl 1.12 + 0.049*sl 1.15 + 0.046*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.35 0.19 + 0.081*sl 0.20 + 0.079*sl 0.19 + 0.080*sl d2 to y t plh 1.02 0.94 + 0.042*sl 0.96 + 0.036*sl 0.97 + 0.034*sl t phl 1.16 1.05 + 0.058*sl 1.07 + 0.049*sl 1.10 + 0.046*sl t r 0.30 0.16 + 0.067*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.35 0.19 + 0.081*sl 0.20 + 0.079*sl 0.19 + 0.080*sl d3 to y t plh 1.02 0.94 + 0.042*sl 0.96 + 0.036*sl 0.97 + 0.034*sl t phl 1.16 1.05 + 0.058*sl 1.07 + 0.049*sl 1.10 + 0.046*sl t r 0.30 0.16 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.35 0.19 + 0.081*sl 0.20 + 0.079*sl 0.19 + 0.080*sl d4 to y t plh 0.42 0.34 + 0.040*sl 0.36 + 0.035*sl 0.37 + 0.033*sl t phl 0.57 0.46 + 0.057*sl 0.48 + 0.048*sl 0.51 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.34 0.18 + 0.080*sl 0.18 + 0.079*sl 0.18 + 0.080*sl s0 to y t plh 1.23 1.15 + 0.041*sl 1.17 + 0.036*sl 1.18 + 0.034*sl t phl 1.29 1.18 + 0.058*sl 1.20 + 0.049*sl 1.23 + 0.046*sl t r 0.30 0.16 + 0.067*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.35 0.19 + 0.081*sl 0.20 + 0.079*sl 0.19 + 0.080*sl s1 to y t plh 0.72 0.64 + 0.042*sl 0.66 + 0.036*sl 0.67 + 0.034*sl t phl 0.77 0.65 + 0.058*sl 0.68 + 0.049*sl 0.71 + 0.046*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.35 0.19 + 0.082*sl 0.20 + 0.078*sl 0.19 + 0.080*sl s2 to y t plh 0.46 0.38 + 0.041*sl 0.39 + 0.035*sl 0.41 + 0.034*sl t phl 0.54 0.43 + 0.057*sl 0.45 + 0.048*sl 0.47 + 0.045*sl t r 0.29 0.15 + 0.068*sl 0.15 + 0.069*sl 0.14 + 0.070*sl t f 0.34 0.18 + 0.081*sl 0.18 + 0.079*sl 0.17 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-525 STD80/stdm80 mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 1.08 1.02 + 0.027*sl 1.04 + 0.022*sl 1.06 + 0.019*sl t phl 1.22 1.15 + 0.036*sl 1.17 + 0.030*sl 1.20 + 0.026*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.034*sl 0.17 + 0.033*sl t f 0.29 0.20 + 0.044*sl 0.22 + 0.039*sl 0.23 + 0.038*sl d1 to y t plh 1.08 1.02 + 0.027*sl 1.04 + 0.022*sl 1.06 + 0.019*sl t phl 1.22 1.15 + 0.036*sl 1.17 + 0.030*sl 1.20 + 0.025*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.29 0.20 + 0.043*sl 0.21 + 0.040*sl 0.22 + 0.038*sl d2 to y t plh 1.03 0.98 + 0.027*sl 0.99 + 0.022*sl 1.01 + 0.019*sl t phl 1.17 1.10 + 0.036*sl 1.12 + 0.030*sl 1.14 + 0.026*sl t r 0.24 0.16 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.29 0.20 + 0.043*sl 0.21 + 0.040*sl 0.22 + 0.038*sl d3 to y t plh 1.03 0.98 + 0.027*sl 0.99 + 0.022*sl 1.01 + 0.019*sl t phl 1.17 1.10 + 0.036*sl 1.12 + 0.030*sl 1.14 + 0.026*sl t r 0.24 0.16 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.29 0.20 + 0.043*sl 0.21 + 0.040*sl 0.22 + 0.038*sl d4 to y t plh 0.43 0.38 + 0.026*sl 0.39 + 0.021*sl 0.41 + 0.019*sl t phl 0.58 0.51 + 0.035*sl 0.53 + 0.029*sl 0.56 + 0.025*sl t r 0.22 0.15 + 0.035*sl 0.15 + 0.035*sl 0.16 + 0.034*sl t f 0.27 0.19 + 0.043*sl 0.20 + 0.040*sl 0.21 + 0.038*sl s0 to y t plh 1.24 1.19 + 0.027*sl 1.20 + 0.022*sl 1.22 + 0.019*sl t phl 1.30 1.23 + 0.036*sl 1.25 + 0.030*sl 1.27 + 0.026*sl t r 0.24 0.16 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.29 0.20 + 0.043*sl 0.21 + 0.040*sl 0.22 + 0.038*sl s1 to y t plh 0.73 0.68 + 0.027*sl 0.69 + 0.022*sl 0.71 + 0.019*sl t phl 0.78 0.70 + 0.036*sl 0.72 + 0.030*sl 0.75 + 0.026*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.29 0.20 + 0.043*sl 0.21 + 0.040*sl 0.22 + 0.038*sl s2 to y t plh 0.46 0.41 + 0.026*sl 0.42 + 0.021*sl 0.44 + 0.019*sl t phl 0.54 0.47 + 0.035*sl 0.49 + 0.029*sl 0.51 + 0.025*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.035*sl 0.16 + 0.034*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.040*sl 0.21 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-526 sec asic mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 mx8 mx8 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.6 0.7 0.7 0.7 0.6 0.7 0.7 0.7 0.7 1.2 1.3 12.7 mx8d2 mx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.6 0.7 0.7 0.7 0.6 0.7 0.7 0.7 0.6 1.2 1.0 13.0 stdm80 mx8 mx8 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 2.2 1.5 12.7 mx8d2 mx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 2.2 1.5 13.0 y d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 truth table s0 s1 s2 y 000d0 100d1 010d2 110d3 001d4 101d5 011d6 111d7
sec asic 3-527 STD80/stdm80 mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive schematic diagram d0 d1 d2 d3 s0 s0b s0 s0b s0 s0 s0b s1b s1 s1 s0 s1b s1 s1 s1b s2b s2 y d4 d5 d6 d7 s0 s0b s0 s0b s1b s1 s1 s1b s2 s2b s2b s2 s2
STD80/stdm80 3-528 sec asic mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.66 0.57 + 0.044*sl 0.60 + 0.031*sl 0.67 + 0.024*sl t phl 0.82 0.70 + 0.060*sl 0.73 + 0.046*sl 0.82 + 0.037*sl t r 0.35 0.24 + 0.052*sl 0.25 + 0.048*sl 0.22 + 0.051*sl t f 0.45 0.31 + 0.072*sl 0.33 + 0.065*sl 0.30 + 0.068*sl d1 to y t plh 0.66 0.57 + 0.044*sl 0.60 + 0.032*sl 0.68 + 0.024*sl t phl 0.82 0.70 + 0.060*sl 0.73 + 0.046*sl 0.82 + 0.037*sl t r 0.35 0.24 + 0.051*sl 0.25 + 0.048*sl 0.22 + 0.051*sl t f 0.45 0.31 + 0.072*sl 0.33 + 0.065*sl 0.30 + 0.068*sl d2 to y t plh 0.64 0.56 + 0.044*sl 0.58 + 0.031*sl 0.65 + 0.024*sl t phl 0.81 0.69 + 0.060*sl 0.72 + 0.046*sl 0.80 + 0.037*sl t r 0.34 0.24 + 0.050*sl 0.25 + 0.048*sl 0.21 + 0.051*sl t f 0.45 0.30 + 0.071*sl 0.32 + 0.065*sl 0.29 + 0.068*sl d3 to y t plh 0.64 0.56 + 0.044*sl 0.58 + 0.031*sl 0.65 + 0.024*sl t phl 0.81 0.69 + 0.060*sl 0.72 + 0.046*sl 0.80 + 0.037*sl t r 0.34 0.24 + 0.051*sl 0.25 + 0.048*sl 0.21 + 0.051*sl t f 0.45 0.30 + 0.071*sl 0.32 + 0.065*sl 0.29 + 0.068*sl d4 to y t plh 0.65 0.56 + 0.044*sl 0.59 + 0.031*sl 0.66 + 0.024*sl t phl 0.82 0.70 + 0.060*sl 0.73 + 0.046*sl 0.81 + 0.037*sl t r 0.35 0.25 + 0.050*sl 0.25 + 0.047*sl 0.22 + 0.051*sl t f 0.45 0.31 + 0.072*sl 0.32 + 0.065*sl 0.30 + 0.068*sl d5 to y t plh 0.65 0.56 + 0.044*sl 0.59 + 0.031*sl 0.66 + 0.024*sl t phl 0.82 0.70 + 0.060*sl 0.73 + 0.046*sl 0.81 + 0.037*sl t r 0.35 0.25 + 0.050*sl 0.25 + 0.047*sl 0.22 + 0.051*sl t f 0.45 0.31 + 0.072*sl 0.32 + 0.065*sl 0.30 + 0.068*sl d6 to y t plh 0.64 0.56 + 0.044*sl 0.58 + 0.031*sl 0.66 + 0.024*sl t phl 0.81 0.69 + 0.060*sl 0.72 + 0.046*sl 0.81 + 0.037*sl t r 0.34 0.24 + 0.050*sl 0.25 + 0.047*sl 0.22 + 0.051*sl t f 0.45 0.31 + 0.073*sl 0.32 + 0.065*sl 0.29 + 0.068*sl d7 to y t plh 0.64 0.56 + 0.044*sl 0.58 + 0.031*sl 0.66 + 0.024*sl t phl 0.81 0.69 + 0.060*sl 0.72 + 0.046*sl 0.81 + 0.037*sl t r 0.34 0.24 + 0.050*sl 0.25 + 0.048*sl 0.22 + 0.051*sl t f 0.45 0.31 + 0.073*sl 0.32 + 0.065*sl 0.29 + 0.068*sl s0 to y t plh 0.93 0.84 + 0.044*sl 0.86 + 0.031*sl 0.94 + 0.024*sl t phl 1.04 0.92 + 0.060*sl 0.95 + 0.046*sl 1.04 + 0.037*sl t r 0.35 0.25 + 0.050*sl 0.25 + 0.048*sl 0.22 + 0.051*sl t f 0.45 0.31 + 0.072*sl 0.32 + 0.065*sl 0.30 + 0.068*sl s1 to y t plh 0.56 0.48 + 0.044*sl 0.50 + 0.031*sl 0.58 + 0.024*sl t phl 0.69 0.57 + 0.060*sl 0.60 + 0.046*sl 0.69 + 0.037*sl t r 0.33 0.24 + 0.050*sl 0.24 + 0.048*sl 0.21 + 0.051*sl t f 0.44 0.30 + 0.071*sl 0.31 + 0.065*sl 0.29 + 0.068*sl s2 to y t plh 0.38 0.30 + 0.039*sl 0.32 + 0.030*sl 0.37 + 0.024*sl t phl 0.45 0.34 + 0.057*sl 0.36 + 0.046*sl 0.44 + 0.037*sl t r 0.26 0.15 + 0.053*sl 0.16 + 0.052*sl 0.16 + 0.051*sl t f 0.34 0.19 + 0.077*sl 0.20 + 0.070*sl 0.22 + 0.068*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-529 STD80/stdm80 mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 mx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.67 0.61 + 0.029*sl 0.63 + 0.021*sl 0.71 + 0.012*sl t phl 0.83 0.76 + 0.037*sl 0.78 + 0.028*sl 0.87 + 0.019*sl t r 0.32 0.26 + 0.030*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t f 0.42 0.33 + 0.041*sl 0.35 + 0.034*sl 0.37 + 0.032*sl d1 to y t plh 0.67 0.62 + 0.029*sl 0.63 + 0.021*sl 0.71 + 0.012*sl t phl 0.83 0.76 + 0.037*sl 0.78 + 0.028*sl 0.87 + 0.019*sl t r 0.32 0.26 + 0.031*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t f 0.42 0.33 + 0.044*sl 0.35 + 0.034*sl 0.37 + 0.032*sl d2 to y t plh 0.65 0.60 + 0.029*sl 0.62 + 0.020*sl 0.69 + 0.012*sl t phl 0.82 0.74 + 0.037*sl 0.76 + 0.028*sl 0.85 + 0.019*sl t r 0.31 0.26 + 0.029*sl 0.27 + 0.025*sl 0.26 + 0.025*sl t f 0.41 0.33 + 0.042*sl 0.34 + 0.034*sl 0.36 + 0.032*sl d3 to y t plh 0.65 0.60 + 0.029*sl 0.62 + 0.020*sl 0.69 + 0.012*sl t phl 0.82 0.74 + 0.037*sl 0.76 + 0.028*sl 0.85 + 0.019*sl t r 0.31 0.25 + 0.030*sl 0.27 + 0.025*sl 0.26 + 0.025*sl t f 0.41 0.33 + 0.042*sl 0.34 + 0.034*sl 0.36 + 0.032*sl d4 to y t plh 0.66 0.60 + 0.029*sl 0.62 + 0.020*sl 0.70 + 0.012*sl t phl 0.82 0.75 + 0.037*sl 0.77 + 0.028*sl 0.86 + 0.019*sl t r 0.32 0.26 + 0.030*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t f 0.41 0.33 + 0.041*sl 0.35 + 0.034*sl 0.36 + 0.032*sl d5 to y t plh 0.66 0.60 + 0.029*sl 0.62 + 0.021*sl 0.70 + 0.012*sl t phl 0.82 0.75 + 0.038*sl 0.77 + 0.028*sl 0.86 + 0.019*sl t r 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t f 0.41 0.33 + 0.043*sl 0.35 + 0.034*sl 0.36 + 0.032*sl d6 to y t plh 0.65 0.60 + 0.029*sl 0.61 + 0.020*sl 0.69 + 0.012*sl t phl 0.82 0.75 + 0.037*sl 0.77 + 0.028*sl 0.85 + 0.019*sl t r 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t f 0.41 0.33 + 0.041*sl 0.34 + 0.034*sl 0.36 + 0.032*sl d7 to y t plh 0.65 0.60 + 0.029*sl 0.61 + 0.020*sl 0.69 + 0.012*sl t phl 0.82 0.75 + 0.037*sl 0.77 + 0.028*sl 0.85 + 0.019*sl t r 0.32 0.26 + 0.029*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t f 0.41 0.33 + 0.040*sl 0.34 + 0.034*sl 0.36 + 0.032*sl s0 to y t plh 0.94 0.88 + 0.029*sl 0.90 + 0.020*sl 0.98 + 0.012*sl t phl 1.05 0.98 + 0.037*sl 1.00 + 0.028*sl 1.09 + 0.019*sl t r 0.32 0.26 + 0.028*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t f 0.41 0.33 + 0.043*sl 0.35 + 0.034*sl 0.36 + 0.032*sl s1 to y t plh 0.57 0.51 + 0.029*sl 0.53 + 0.020*sl 0.61 + 0.012*sl t phl 0.69 0.62 + 0.037*sl 0.64 + 0.028*sl 0.73 + 0.019*sl t r 0.31 0.25 + 0.029*sl 0.26 + 0.025*sl 0.26 + 0.025*sl t f 0.40 0.32 + 0.040*sl 0.34 + 0.034*sl 0.35 + 0.032*sl s2 to y t plh 0.38 0.33 + 0.026*sl 0.34 + 0.020*sl 0.41 + 0.012*sl t phl 0.46 0.38 + 0.036*sl 0.40 + 0.028*sl 0.49 + 0.019*sl t r 0.24 0.18 + 0.029*sl 0.19 + 0.027*sl 0.20 + 0.025*sl t f 0.32 0.23 + 0.045*sl 0.24 + 0.037*sl 0.28 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-530 sec asic mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.97 0.86 + 0.056*sl 0.89 + 0.045*sl 0.93 + 0.039*sl t phl 1.25 1.08 + 0.082*sl 1.13 + 0.065*sl 1.19 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.30 + 0.070*sl 0.32 + 0.068*sl t f 0.63 0.45 + 0.093*sl 0.47 + 0.084*sl 0.50 + 0.080*sl d1 to y t plh 0.97 0.86 + 0.056*sl 0.89 + 0.045*sl 0.94 + 0.039*sl t phl 1.24 1.08 + 0.082*sl 1.13 + 0.065*sl 1.19 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.30 + 0.070*sl 0.32 + 0.068*sl t f 0.63 0.45 + 0.093*sl 0.47 + 0.084*sl 0.50 + 0.080*sl d2 to y t plh 0.94 0.83 + 0.056*sl 0.87 + 0.045*sl 0.91 + 0.039*sl t phl 1.22 1.06 + 0.081*sl 1.11 + 0.065*sl 1.17 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.30 + 0.069*sl 0.31 + 0.068*sl t f 0.62 0.43 + 0.093*sl 0.46 + 0.084*sl 0.49 + 0.080*sl d3 to y t plh 0.94 0.83 + 0.055*sl 0.87 + 0.045*sl 0.91 + 0.039*sl t phl 1.22 1.06 + 0.081*sl 1.11 + 0.065*sl 1.17 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.30 + 0.070*sl 0.31 + 0.068*sl t f 0.62 0.43 + 0.093*sl 0.46 + 0.084*sl 0.49 + 0.080*sl d4 to y t plh 0.96 0.84 + 0.056*sl 0.88 + 0.045*sl 0.92 + 0.039*sl t phl 1.23 1.07 + 0.082*sl 1.12 + 0.065*sl 1.18 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.30 + 0.070*sl 0.32 + 0.068*sl t f 0.63 0.44 + 0.093*sl 0.47 + 0.084*sl 0.50 + 0.080*sl d5 to y t plh 0.96 0.84 + 0.056*sl 0.88 + 0.045*sl 0.92 + 0.039*sl t phl 1.23 1.07 + 0.082*sl 1.12 + 0.065*sl 1.18 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.30 + 0.070*sl 0.32 + 0.068*sl t f 0.63 0.44 + 0.093*sl 0.47 + 0.084*sl 0.50 + 0.080*sl d6 to y t plh 0.95 0.83 + 0.056*sl 0.87 + 0.045*sl 0.91 + 0.039*sl t phl 1.23 1.07 + 0.081*sl 1.11 + 0.065*sl 1.18 + 0.056*sl t r 0.44 0.29 + 0.076*sl 0.31 + 0.069*sl 0.31 + 0.068*sl t f 0.63 0.44 + 0.092*sl 0.47 + 0.084*sl 0.50 + 0.080*sl d7 to y t plh 0.95 0.83 + 0.056*sl 0.87 + 0.045*sl 0.91 + 0.039*sl t phl 1.23 1.07 + 0.081*sl 1.11 + 0.065*sl 1.18 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.31 + 0.070*sl 0.31 + 0.068*sl t f 0.63 0.44 + 0.092*sl 0.47 + 0.084*sl 0.50 + 0.080*sl s0 to y t plh 1.35 1.24 + 0.056*sl 1.27 + 0.045*sl 1.31 + 0.039*sl t phl 1.56 1.39 + 0.081*sl 1.44 + 0.065*sl 1.50 + 0.056*sl t r 0.44 0.29 + 0.075*sl 0.31 + 0.070*sl 0.32 + 0.068*sl t f 0.63 0.44 + 0.093*sl 0.47 + 0.084*sl 0.50 + 0.080*sl s1 to y t plh 0.83 0.72 + 0.056*sl 0.75 + 0.045*sl 0.79 + 0.039*sl t phl 1.03 0.87 + 0.082*sl 0.92 + 0.065*sl 0.98 + 0.056*sl t r 0.43 0.28 + 0.075*sl 0.30 + 0.070*sl 0.31 + 0.068*sl t f 0.61 0.43 + 0.093*sl 0.45 + 0.085*sl 0.49 + 0.080*sl s2 to y t plh 0.52 0.41 + 0.051*sl 0.44 + 0.044*sl 0.47 + 0.039*sl t phl 0.62 0.47 + 0.074*sl 0.50 + 0.063*sl 0.56 + 0.055*sl t r 0.36 0.20 + 0.080*sl 0.22 + 0.074*sl 0.24 + 0.071*sl t f 0.45 0.25 + 0.102*sl 0.28 + 0.092*sl 0.33 + 0.085*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-531 STD80/stdm80 mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 mx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 1.00 0.92 + 0.037*sl 0.95 + 0.029*sl 0.98 + 0.024*sl t phl 1.27 1.17 + 0.053*sl 1.20 + 0.042*sl 1.25 + 0.034*sl t r 0.38 0.30 + 0.041*sl 0.31 + 0.037*sl 0.32 + 0.036*sl t f 0.58 0.47 + 0.057*sl 0.50 + 0.046*sl 0.53 + 0.041*sl d1 to y t plh 1.00 0.93 + 0.038*sl 0.95 + 0.029*sl 0.99 + 0.024*sl t phl 1.27 1.16 + 0.053*sl 1.20 + 0.042*sl 1.25 + 0.034*sl t r 0.38 0.30 + 0.041*sl 0.31 + 0.037*sl 0.32 + 0.036*sl t f 0.58 0.47 + 0.057*sl 0.50 + 0.046*sl 0.53 + 0.041*sl d2 to y t plh 0.97 0.90 + 0.038*sl 0.92 + 0.029*sl 0.96 + 0.024*sl t phl 1.25 1.14 + 0.053*sl 1.18 + 0.041*sl 1.23 + 0.034*sl t r 0.38 0.30 + 0.040*sl 0.31 + 0.037*sl 0.32 + 0.036*sl t f 0.57 0.46 + 0.057*sl 0.49 + 0.046*sl 0.52 + 0.041*sl d3 to y t plh 0.97 0.90 + 0.038*sl 0.92 + 0.029*sl 0.96 + 0.024*sl t phl 1.25 1.14 + 0.052*sl 1.17 + 0.041*sl 1.23 + 0.034*sl t r 0.38 0.30 + 0.040*sl 0.31 + 0.037*sl 0.32 + 0.036*sl t f 0.57 0.46 + 0.057*sl 0.49 + 0.046*sl 0.52 + 0.041*sl d4 to y t plh 0.98 0.91 + 0.037*sl 0.93 + 0.029*sl 0.96 + 0.024*sl t phl 1.25 1.15 + 0.053*sl 1.18 + 0.041*sl 1.23 + 0.034*sl t r 0.38 0.30 + 0.041*sl 0.31 + 0.037*sl 0.32 + 0.036*sl t f 0.57 0.46 + 0.057*sl 0.49 + 0.046*sl 0.53 + 0.041*sl d5 to y t plh 0.98 0.90 + 0.038*sl 0.93 + 0.029*sl 0.96 + 0.024*sl t phl 1.25 1.15 + 0.052*sl 1.18 + 0.041*sl 1.23 + 0.034*sl t r 0.38 0.30 + 0.040*sl 0.31 + 0.038*sl 0.32 + 0.036*sl t f 0.57 0.46 + 0.057*sl 0.49 + 0.046*sl 0.53 + 0.041*sl d6 to y t plh 0.97 0.89 + 0.037*sl 0.92 + 0.029*sl 0.96 + 0.024*sl t phl 1.25 1.14 + 0.053*sl 1.18 + 0.041*sl 1.23 + 0.034*sl t r 0.38 0.30 + 0.041*sl 0.31 + 0.037*sl 0.31 + 0.036*sl t f 0.57 0.46 + 0.057*sl 0.49 + 0.046*sl 0.52 + 0.042*sl d7 to y t plh 0.97 0.89 + 0.037*sl 0.92 + 0.029*sl 0.96 + 0.024*sl t phl 1.25 1.14 + 0.053*sl 1.18 + 0.041*sl 1.23 + 0.034*sl t r 0.38 0.30 + 0.040*sl 0.30 + 0.038*sl 0.32 + 0.036*sl t f 0.57 0.46 + 0.056*sl 0.49 + 0.046*sl 0.52 + 0.042*sl s0 to y t plh 1.38 1.30 + 0.038*sl 1.33 + 0.029*sl 1.36 + 0.024*sl t phl 1.58 1.48 + 0.053*sl 1.51 + 0.041*sl 1.56 + 0.034*sl t r 0.38 0.30 + 0.039*sl 0.31 + 0.038*sl 0.32 + 0.036*sl t f 0.57 0.46 + 0.056*sl 0.49 + 0.046*sl 0.52 + 0.041*sl s1 to y t plh 0.85 0.77 + 0.037*sl 0.80 + 0.029*sl 0.83 + 0.024*sl t phl 1.06 0.95 + 0.053*sl 0.99 + 0.041*sl 1.04 + 0.034*sl t r 0.38 0.29 + 0.040*sl 0.30 + 0.038*sl 0.32 + 0.036*sl t f 0.57 0.45 + 0.056*sl 0.49 + 0.046*sl 0.51 + 0.042*sl s2 to y t plh 0.53 0.46 + 0.035*sl 0.48 + 0.028*sl 0.51 + 0.024*sl t phl 0.64 0.54 + 0.050*sl 0.57 + 0.040*sl 0.61 + 0.034*sl t r 0.31 0.23 + 0.042*sl 0.24 + 0.040*sl 0.25 + 0.038*sl t f 0.43 0.31 + 0.058*sl 0.34 + 0.049*sl 0.37 + 0.045*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 3-532 sec asic ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive logic symbol cell data input load (sl) gate count STD80 ymx8/ymx8d2 ymx8 ymx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 3.2 3.2 3.0 3.1 3.2 3.1 2.9 3.0 0.6 1.6 1.1 11.0 11.3 stdm80 ymx8/ymx8d2 ymx8 ymx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 3.7 3.7 3.5 3.6 3.6 3.6 3.4 3.4 0.6 1.8 1.2 11.0 11.3 y d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 truth table s0 s1 s2 y 000d0 100d1 010d2 110d3 001d4 101d5 011d6 111d7
sec asic 3-533 STD80/stdm80 ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive schematic diagram d0 d1 d2 d3 y s0 s1 d4 d5 d6 d7 s2
STD80/stdm80 3-534 sec asic ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ymx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.50 0.44 + 0.031*sl 0.45 + 0.025*sl 0.46 + 0.024*sl t phl 0.59 0.50 + 0.045*sl 0.51 + 0.039*sl 0.53 + 0.037*sl t r 0.23 0.14 + 0.044*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.28 0.15 + 0.063*sl 0.15 + 0.065*sl 0.11 + 0.069*sl d1 to y t plh 0.50 0.43 + 0.031*sl 0.45 + 0.025*sl 0.46 + 0.024*sl t phl 0.59 0.50 + 0.044*sl 0.51 + 0.039*sl 0.53 + 0.037*sl t r 0.23 0.14 + 0.045*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.064*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d2 to y t plh 0.49 0.43 + 0.031*sl 0.44 + 0.025*sl 0.46 + 0.024*sl t phl 0.58 0.49 + 0.045*sl 0.51 + 0.039*sl 0.52 + 0.037*sl t r 0.23 0.14 + 0.044*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.28 0.15 + 0.062*sl 0.15 + 0.065*sl 0.10 + 0.069*sl d3 to y t plh 0.49 0.43 + 0.031*sl 0.45 + 0.025*sl 0.46 + 0.024*sl t phl 0.59 0.49 + 0.045*sl 0.51 + 0.039*sl 0.53 + 0.037*sl t r 0.23 0.14 + 0.044*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.28 0.15 + 0.063*sl 0.15 + 0.065*sl 0.10 + 0.069*sl d4 to y t plh 0.48 0.42 + 0.030*sl 0.44 + 0.025*sl 0.45 + 0.024*sl t phl 0.58 0.49 + 0.044*sl 0.50 + 0.039*sl 0.52 + 0.037*sl t r 0.22 0.14 + 0.044*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.063*sl 0.15 + 0.065*sl 0.10 + 0.069*sl d5 to y t plh 0.48 0.42 + 0.031*sl 0.43 + 0.025*sl 0.45 + 0.024*sl t phl 0.58 0.49 + 0.044*sl 0.50 + 0.039*sl 0.52 + 0.037*sl t r 0.23 0.14 + 0.044*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d6 to y t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.44 + 0.024*sl t phl 0.57 0.48 + 0.044*sl 0.50 + 0.039*sl 0.51 + 0.037*sl t r 0.23 0.13 + 0.045*sl 0.13 + 0.047*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.064*sl 0.14 + 0.065*sl 0.10 + 0.069*sl d7 to y t plh 0.48 0.42 + 0.030*sl 0.43 + 0.025*sl 0.44 + 0.024*sl t phl 0.57 0.48 + 0.044*sl 0.49 + 0.039*sl 0.51 + 0.037*sl t r 0.22 0.14 + 0.044*sl 0.13 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl s0 to y t plh 0.96 0.90 + 0.030*sl 0.91 + 0.025*sl 0.92 + 0.024*sl t phl 0.93 0.85 + 0.044*sl 0.86 + 0.039*sl 0.87 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.27 0.15 + 0.063*sl 0.14 + 0.065*sl 0.10 + 0.069*sl s1 to y t plh 0.57 0.51 + 0.030*sl 0.52 + 0.025*sl 0.53 + 0.024*sl t phl 0.51 0.42 + 0.044*sl 0.44 + 0.039*sl 0.45 + 0.037*sl t r 0.22 0.13 + 0.045*sl 0.12 + 0.048*sl 0.08 + 0.052*sl t f 0.27 0.15 + 0.062*sl 0.14 + 0.065*sl 0.10 + 0.069*sl s2 to y t plh 0.32 0.27 + 0.029*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t phl 0.40 0.31 + 0.044*sl 0.32 + 0.039*sl 0.34 + 0.037*sl t r 0.20 0.11 + 0.049*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.26 0.13 + 0.065*sl 0.13 + 0.066*sl 0.10 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 3-535 STD80/stdm80 ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 ymx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.51 0.47 + 0.020*sl 0.48 + 0.015*sl 0.51 + 0.012*sl t phl 0.60 0.54 + 0.028*sl 0.55 + 0.022*sl 0.59 + 0.018*sl t r 0.19 0.15 + 0.024*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.24 0.17 + 0.033*sl 0.17 + 0.031*sl 0.15 + 0.033*sl d1 to y t plh 0.51 0.47 + 0.021*sl 0.48 + 0.015*sl 0.51 + 0.012*sl t phl 0.60 0.54 + 0.028*sl 0.55 + 0.022*sl 0.59 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.24 0.17 + 0.033*sl 0.17 + 0.031*sl 0.15 + 0.033*sl d2 to y t plh 0.51 0.47 + 0.020*sl 0.48 + 0.015*sl 0.51 + 0.012*sl t phl 0.59 0.54 + 0.028*sl 0.55 + 0.022*sl 0.58 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.24 0.17 + 0.034*sl 0.17 + 0.031*sl 0.15 + 0.033*sl d3 to y t plh 0.51 0.47 + 0.020*sl 0.48 + 0.015*sl 0.51 + 0.012*sl t phl 0.59 0.54 + 0.028*sl 0.55 + 0.022*sl 0.58 + 0.018*sl t r 0.19 0.15 + 0.024*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.24 0.17 + 0.034*sl 0.18 + 0.031*sl 0.15 + 0.033*sl d4 to y t plh 0.50 0.46 + 0.020*sl 0.47 + 0.015*sl 0.50 + 0.012*sl t phl 0.59 0.53 + 0.028*sl 0.55 + 0.022*sl 0.58 + 0.018*sl t r 0.19 0.15 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.23 0.17 + 0.034*sl 0.17 + 0.031*sl 0.15 + 0.033*sl d5 to y t plh 0.50 0.46 + 0.020*sl 0.47 + 0.015*sl 0.50 + 0.012*sl t phl 0.59 0.53 + 0.028*sl 0.55 + 0.022*sl 0.58 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.23 0.17 + 0.033*sl 0.17 + 0.031*sl 0.15 + 0.033*sl d6 to y t plh 0.49 0.45 + 0.020*sl 0.46 + 0.015*sl 0.49 + 0.012*sl t phl 0.58 0.52 + 0.028*sl 0.54 + 0.022*sl 0.57 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.23 0.17 + 0.034*sl 0.17 + 0.031*sl 0.15 + 0.033*sl d7 to y t plh 0.49 0.45 + 0.020*sl 0.46 + 0.015*sl 0.49 + 0.012*sl t phl 0.58 0.53 + 0.027*sl 0.54 + 0.022*sl 0.57 + 0.018*sl t r 0.19 0.14 + 0.024*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.24 0.17 + 0.034*sl 0.17 + 0.031*sl 0.15 + 0.033*sl s0 to y t plh 0.97 0.93 + 0.020*sl 0.94 + 0.015*sl 0.97 + 0.012*sl t phl 0.94 0.89 + 0.028*sl 0.90 + 0.022*sl 0.93 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.23 0.17 + 0.033*sl 0.17 + 0.031*sl 0.15 + 0.033*sl s1 to y t plh 0.58 0.54 + 0.020*sl 0.55 + 0.015*sl 0.58 + 0.012*sl t phl 0.52 0.47 + 0.028*sl 0.48 + 0.022*sl 0.51 + 0.018*sl t r 0.18 0.14 + 0.020*sl 0.14 + 0.023*sl 0.11 + 0.026*sl t f 0.23 0.17 + 0.032*sl 0.17 + 0.031*sl 0.15 + 0.033*sl s2 to y t plh 0.33 0.29 + 0.020*sl 0.30 + 0.015*sl 0.33 + 0.012*sl t phl 0.40 0.34 + 0.028*sl 0.36 + 0.022*sl 0.39 + 0.018*sl t r 0.17 0.13 + 0.021*sl 0.12 + 0.024*sl 0.10 + 0.026*sl t f 0.22 0.15 + 0.034*sl 0.16 + 0.032*sl 0.14 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 3-536 sec asic ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ymx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.76 0.68 + 0.042*sl 0.69 + 0.036*sl 0.71 + 0.034*sl t phl 0.85 0.73 + 0.059*sl 0.76 + 0.050*sl 0.79 + 0.046*sl t r 0.30 0.17 + 0.066*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.37 0.21 + 0.081*sl 0.21 + 0.078*sl 0.21 + 0.079*sl d1 to y t plh 0.76 0.68 + 0.042*sl 0.69 + 0.036*sl 0.71 + 0.034*sl t phl 0.85 0.73 + 0.059*sl 0.76 + 0.050*sl 0.79 + 0.046*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.37 0.21 + 0.081*sl 0.21 + 0.078*sl 0.21 + 0.079*sl d2 to y t plh 0.75 0.67 + 0.042*sl 0.69 + 0.036*sl 0.70 + 0.034*sl t phl 0.84 0.72 + 0.059*sl 0.75 + 0.050*sl 0.78 + 0.046*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.37 0.21 + 0.081*sl 0.21 + 0.078*sl 0.21 + 0.079*sl d3 to y t plh 0.76 0.67 + 0.042*sl 0.69 + 0.036*sl 0.71 + 0.034*sl t phl 0.84 0.72 + 0.059*sl 0.75 + 0.050*sl 0.78 + 0.046*sl t r 0.30 0.17 + 0.066*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.37 0.21 + 0.080*sl 0.21 + 0.078*sl 0.21 + 0.079*sl d4 to y t plh 0.74 0.66 + 0.042*sl 0.67 + 0.036*sl 0.69 + 0.034*sl t phl 0.84 0.72 + 0.059*sl 0.75 + 0.050*sl 0.78 + 0.046*sl t r 0.30 0.17 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.36 0.20 + 0.080*sl 0.21 + 0.078*sl 0.20 + 0.079*sl d5 to y t plh 0.74 0.65 + 0.041*sl 0.67 + 0.036*sl 0.69 + 0.034*sl t phl 0.84 0.72 + 0.059*sl 0.75 + 0.050*sl 0.77 + 0.046*sl t r 0.30 0.17 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.36 0.20 + 0.080*sl 0.21 + 0.078*sl 0.20 + 0.079*sl d6 to y t plh 0.73 0.64 + 0.042*sl 0.66 + 0.036*sl 0.68 + 0.034*sl t phl 0.82 0.70 + 0.059*sl 0.73 + 0.050*sl 0.76 + 0.046*sl t r 0.30 0.16 + 0.068*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.37 0.21 + 0.081*sl 0.21 + 0.078*sl 0.20 + 0.079*sl d7 to y t plh 0.73 0.64 + 0.042*sl 0.66 + 0.035*sl 0.67 + 0.034*sl t phl 0.82 0.71 + 0.059*sl 0.73 + 0.050*sl 0.76 + 0.046*sl t r 0.30 0.16 + 0.068*sl 0.17 + 0.068*sl 0.15 + 0.070*sl t f 0.36 0.20 + 0.081*sl 0.21 + 0.078*sl 0.20 + 0.079*sl s0 to y t plh 1.40 1.32 + 0.042*sl 1.34 + 0.036*sl 1.35 + 0.034*sl t phl 1.36 1.24 + 0.059*sl 1.27 + 0.049*sl 1.30 + 0.046*sl t r 0.30 0.16 + 0.067*sl 0.16 + 0.068*sl 0.15 + 0.070*sl t f 0.36 0.20 + 0.080*sl 0.21 + 0.078*sl 0.20 + 0.080*sl s1 to y t plh 0.79 0.71 + 0.041*sl 0.72 + 0.036*sl 0.74 + 0.034*sl t phl 0.75 0.63 + 0.059*sl 0.66 + 0.050*sl 0.69 + 0.046*sl t r 0.30 0.16 + 0.067*sl 0.16 + 0.068*sl 0.14 + 0.070*sl t f 0.36 0.20 + 0.081*sl 0.21 + 0.078*sl 0.20 + 0.079*sl s2 to y t plh 0.44 0.36 + 0.040*sl 0.37 + 0.035*sl 0.39 + 0.034*sl t phl 0.54 0.43 + 0.058*sl 0.45 + 0.050*sl 0.48 + 0.046*sl t r 0.28 0.15 + 0.069*sl 0.15 + 0.069*sl 0.13 + 0.071*sl t f 0.35 0.18 + 0.083*sl 0.19 + 0.079*sl 0.19 + 0.080*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
sec asic 3-537 STD80/stdm80 ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 ymx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.78 0.72 + 0.027*sl 0.74 + 0.022*sl 0.76 + 0.019*sl t phl 0.87 0.79 + 0.038*sl 0.81 + 0.031*sl 0.84 + 0.026*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.31 0.23 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.038*sl d1 to y t plh 0.78 0.72 + 0.027*sl 0.74 + 0.022*sl 0.76 + 0.019*sl t phl 0.87 0.79 + 0.038*sl 0.81 + 0.031*sl 0.84 + 0.026*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.31 0.23 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.038*sl d2 to y t plh 0.77 0.72 + 0.027*sl 0.73 + 0.022*sl 0.75 + 0.019*sl t phl 0.86 0.78 + 0.037*sl 0.80 + 0.031*sl 0.83 + 0.026*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.035*sl 0.18 + 0.033*sl t f 0.32 0.23 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.038*sl d3 to y t plh 0.77 0.72 + 0.026*sl 0.73 + 0.022*sl 0.75 + 0.019*sl t phl 0.86 0.78 + 0.038*sl 0.80 + 0.031*sl 0.84 + 0.026*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.31 0.22 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.038*sl d4 to y t plh 0.76 0.70 + 0.026*sl 0.72 + 0.022*sl 0.74 + 0.019*sl t phl 0.85 0.78 + 0.038*sl 0.80 + 0.031*sl 0.83 + 0.026*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.31 0.22 + 0.044*sl 0.23 + 0.040*sl 0.25 + 0.038*sl d5 to y t plh 0.75 0.70 + 0.026*sl 0.72 + 0.022*sl 0.73 + 0.019*sl t phl 0.85 0.78 + 0.037*sl 0.80 + 0.031*sl 0.83 + 0.026*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.18 + 0.033*sl t f 0.31 0.22 + 0.044*sl 0.23 + 0.040*sl 0.25 + 0.038*sl d6 to y t plh 0.74 0.69 + 0.027*sl 0.71 + 0.021*sl 0.72 + 0.019*sl t phl 0.84 0.76 + 0.037*sl 0.78 + 0.031*sl 0.82 + 0.026*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.31 0.22 + 0.044*sl 0.23 + 0.040*sl 0.25 + 0.038*sl d7 to y t plh 0.74 0.69 + 0.026*sl 0.71 + 0.021*sl 0.72 + 0.019*sl t phl 0.84 0.76 + 0.038*sl 0.79 + 0.031*sl 0.82 + 0.026*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.034*sl 0.17 + 0.034*sl t f 0.31 0.22 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.038*sl s0 to y t plh 1.42 1.37 + 0.026*sl 1.38 + 0.022*sl 1.40 + 0.019*sl t phl 1.38 1.30 + 0.037*sl 1.32 + 0.031*sl 1.35 + 0.026*sl t r 0.23 0.16 + 0.035*sl 0.17 + 0.035*sl 0.17 + 0.034*sl t f 0.31 0.22 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.038*sl s1 to y t plh 0.81 0.75 + 0.026*sl 0.77 + 0.021*sl 0.78 + 0.019*sl t phl 0.77 0.69 + 0.037*sl 0.71 + 0.031*sl 0.75 + 0.026*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.035*sl 0.17 + 0.034*sl t f 0.31 0.22 + 0.044*sl 0.24 + 0.040*sl 0.25 + 0.038*sl s2 to y t plh 0.45 0.40 + 0.026*sl 0.41 + 0.021*sl 0.43 + 0.019*sl t phl 0.55 0.48 + 0.038*sl 0.50 + 0.031*sl 0.53 + 0.026*sl t r 0.22 0.15 + 0.035*sl 0.15 + 0.035*sl 0.16 + 0.034*sl t f 0.30 0.21 + 0.044*sl 0.22 + 0.041*sl 0.24 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
input/output cells 4
contents overview...............................................................................................................................4-1 summary tables ...................................................................................................................4-2 input buffers .........................................................................................................................4-8 output buffers.......................................................................................................................4-23 bi-directional buffers ............................................................................................................4-97 input clock drivers ...............................................................................................................4-99 oscillators .............................................................................................................................4-122 pci buffers ...........................................................................................................................4-145 pcmcia buffers ...................................................................................................................4-152 cardbus i/o buffers..............................................................................................................4-159 usb i/o buffers ....................................................................................................................4-168 voltage detector ...................................................................................................................4-173 power pads...........................................................................................................................4-174
input/output cells overview sec asic 4-1 STD80/stdm80 overview the fourth chapter describes various kinds of input/output cells (5v/3.3v, normal and interface operations) in STD80/stdm80 libraries. the switching characteristics of each cell are attached to its basic cell information. the ac characteristics of bi-directional buffers are not included in this data sheet, however, they can be derived from different combinations of input and output buffers. there are so many possible combinations of input/output cells, therefore, the naming conventions are adopted to help you memorize and use this cell library ef?ciently. you can refer to the naming conventions contained in summary tables section. the summary tables section shows the list of 5v and 3.3v i/o cells separated by the category (input, output, bi-directional, etc.), and the more detailed description tables can be found on the leading part of each category.
summary tables input/output cells STD80/stdm80 4-2 sec asic summary tables input buffers output buffers cell type cell name STD80 stdm80 page cmos level pic/picd/picu o o 4-9 phic/phicd/phicu C o plic/plicd/plicu o C ttl schmitt trigger level pil/pild/pilu o C 4-13 phil/phild/philu C o cmos schmitt trigger level pis/pisd/pisu o o 4-16 phis/phisd/phisu C o plis/plisd/plisu o C ttl level pit/pitd/pitu o C 4-20 phit/phitd/phitu C o p v i a b va none normal operation c cmos level h 5v interface in stdm80 l ttl schmitt trigger level l 3.3v interface in STD80 s cmos schmitt trigger level b t ttl level none no resistor d pull-down resistor u pull-up resistor cell type cell name current drive (ma) page STD80 stdm80 normal poby 1/2/4/8/12/16/20/24 1/2/4/6/8/10/12/16 4-24 pobysh 12/16/20/24 C pobysm 4/8/12/16/20/24 4/6/8/10/12/16 phoby C 1/2/4/8/12/16/20/24 phobysh C 12/16/20/24 phobysm C 4/8/12/16/20/24 ploby 1/2/4/6/8/10/12/16 C plobysm 4/6/8/10/12/16 C
input/output cells summary tables sec asic 4-3 STD80/stdm80 open drain pody 1/2/4/8/12/16/20/24 1/2/4/6/8/10/12/16 4-41 podysh 12/16/20/24 C podysm 4/8/12/16/20/24 4/6/8/10/12/16 phody C 1/2/4/8/12/16/20/24 phodysh C 12/16/20/24 phodysm C 4/8/12/16/20/24 plody 1/2/4/6/8/10/12/16 C plodysm 4/6/8/10/12/16 C tri-state poty 1/2/4/8/12/16/20/24 1/2/4/6/8/10/12/16 4-64 potysh 12/16/20/24 C potysm 4/8/12/16/20/24 4/6/8/10/12/16 photy C 1/2/4/8/12/16/20/24 photysh C 12/16/20/24 photysm C 4/8/12/16/20/24 ploty 1/2/4/6/8/10/12/16 C plotysm 4/6/8/10/12/16 C p v o x y z vy none normal operation 1 1ma drive h 5v interface in stdm80 2 2ma drive l 3.3v interface in STD80 4 4ma drive x 6 6ma drive b normal buffer 8 8ma drive d open drain buffer 10 10ma drive t tri-state buffer 12 12ma drive z 16 16ma drive none no slew-rate control 20 20ma drive sh high slew-rate control 24 24ma drive sm medium slew-rate control cell type cell name current drive (ma) page STD80 stdm80
summary tables input/output cells STD80/stdm80 4-4 sec asic bi-directional buffers cell type cell name STD80 stdm80 page open drain pbadyz/pbaudyz o o 4-98 phbadyz/phbaudyz C o plbadyz/plbaudyz o C tri-state pbatyz/pbadtyz/pbautyz o o phbatyz/phbadtyz/phbautyz C o plbatyz/plbadtyz/plbautyz o C p v b a b x y z va none normal operation c cmos level h 5v interface in stdm80 l ttl schmitt trigger level l 3.3v interface in STD80 s cmos schmitt trigger level b t ttl level none no resistor y d pull-down resistor 1 1ma drive u pull-up resistor 2 2ma drive x 4 4ma drive d open drain buffer 6 6ma drive t tri-state buffer 8 8ma drive z 10 10ma drive none no slew-rate control 12 12ma drive sh high slew-rate control 16 16ma drive sm medium slew-rate control 20 20ma drive 24 24ma drive
input/output cells summary tables sec asic 4-5 STD80/stdm80 input clock drivers oscillators cell type cell name current drive (ma) page STD80 stdm80 cmos level psckdcy 2/4/8/12 2/4/6/8 4-100 psckdcdy 2/4/8/12 2/4/6/8 psckdcuy 2/4/8/12 2/4/6/8 ttl schmitt trigger level psckdly 2/4/8/12 C 4-107 psckdldy 2/4/8/12 C psckdluy 2/4/8/12 C cmos schmitt trigger level psckdsy 2/4/8/12 2/4/6/8 4-111 psckdsdy 2/4/8/12 2/4/6/8 psckdsuy 2/4/8/12 2/4/6/8 ttl level psckdty 2/4/8/12 C 4-118 psckdtdy 2/4/8/12 C psckdtuy 2/4/8/12 C psckd a b y ay c cmos level 2 2ma drive l ttl schmitt trigger level 4 4ma drive s cmos schmitt trigger level 6 6ma drive t ttl level 8 8ma drive b 12 12ma drive none no resistor d pull-down resistor u pull-up resistor cell type cell name page STD80 stdm80 oscillator psosck(1/2) psosck(16/26) psosck(1/2) psosck(16/26) 4-123 psoscm(1/2/3/4/5/6) psoscm(16/26/36/46/56/66) psoscm(1/2/3/4/5/6) psoscm(16/26/36/46/56/66) 4-132
summary tables input/output cells STD80/stdm80 4-6 sec asic pci buffers pcmcia buffers cardbus i/o buffers cell type cell name page STD80 stdm80 pci input psipcia/plsipcia psipcia3/phsipcia 4-148 pci output psopcia/plsopcia psopcia3/phsopcia 4-149 universal pci input psipciau psipciau 4-150 universal pci output psopciau psopciau 4-151 cell type cell name page pcmcia input pvic(5/3) 4-155 pvil/pvild/pvilu(5/3) pvit/pvitd/pitu(5/3) pcmcia output pvob4/pvob8/pvob12(5/3) 4-156 pvod4/pvod8/pvod12(5/3) pvot4/pvot8/pvot12(5/3) 4-157 pvot8sm/pvot12sm(5/3) pcmcia bi-directional pvbtt4/pvbtt8/pvbtt12(5/3) 4-158 pvbtdt8sm/pvbct8sm(5/3) cell type cell name page STD80 stdm80 cardbus input plitcbu pitcbu 4-162 cardbus output plotcbu/ plotcckcbu/ plotcvscbu potcbu/ potcckcbu/ potcvscbu 4-163 plodcckcbu podcckcbu 4-164 cardbus bi-directional plbttcbu/ plbtcckcbu/ plbtcvscbu pbttcbu/ pbtcckcbu/ pbtcvscbu 4-165 plbdcckcbu pbdcckcbu 4-166 level shifter plscb plscb 4-167
input/output cells summary tables sec asic 4-7 STD80/stdm80 usb i/o buffers voltage detector power pads cell type cell name page STD80 stdm80 usb pbusb/pbusb1 pbusb/pbusb1 4-170 cell type cell name page voltage detector vdet 4-173 cell type cell name page STD80 stdm80 5v vdd vdd5(i/p/o/ip/oi/op/t) vdd5(p/o/op) 4-174 3.3v vdd vdd3(p/o/op) vdd3(i/p/o/ip/oi/op/t) 5v vss vss5(i/p/o/ip/oi/op/t) vss5(p/o/op) 3.3v vss vss3(p/o/op) vss3(i/p/o/ip/oi/op/t)
STD80/stdm80 4-8 sec asic input buffers cell list cell name function description STD80 pic/picd/picu 5v cmos level input buffers pil/pild/pilu 5v ttl schmitt trigger level input buffers pis/pisd/pisu 5v cmos schmitt trigger level input buffers pit/pitd/pitu 5v ttl level input buffers plic/plicd/plicu 3.3v interface cmos level input buffers plis/plisd/plisu 3.3v interface cmos schmitt trigger level input buffers stdm80 pic/picd/picu 3.3v cmos level input buffers pis/pisd/pisu 3.3v cmos schmitt trigger level input buffers phic/phicd/phicu 5v interface cmos level input buffers phil/phild/philu 5v interface ttl schmitt trigger level input buffers phis/phisd/phisu 5v interface cmos schmitt trigger level input buffers phit/phitd/phitu 5v interface ttl level input buffers
sec asic 4-9 STD80/stdm80 pvic/pvicd/pvicu cmos level input buffers cell availability logic symbol notes: 1. STD80 3.3v interface input buffers (plic/plicd/plicu) are not available to receive input signals from 5v devices. 2. fail-safe input buffers are available to receive signals from 5v devices without reducing reliability. however, if you want to use fail-safe input buffers, please contact to sec asic ?rst. library 5v operation 3.3v operation STD80 pic/picd/picu plic/plicd/plicu stdm80 phic/phicd/phicu pic/picd/picu y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 STD80 pi pic/picd/picu 1.6 plic/plicd/plicu 1.2 stdm80 pi pic/picd/picu 1.9 phic/phicd/phicu 1.4 STD80/stdm80 pvic/pvicd/pvicu 1.0
STD80/stdm80 4-10 sec asic pvic/pvicd/pvicu cmos level input buffers STD80 pic switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.23 0.21 + 0.009*sl 0.22 + 0.008*sl 0.22 + 0.008*sl t phl 0.24 0.21 + 0.011*sl 0.21 + 0.010*sl 0.22 + 0.010*sl t r 0.13 0.10 + 0.014*sl 0.10 + 0.014*sl 0.09 + 0.015*sl t f 0.13 0.10 + 0.016*sl 0.10 + 0.018*sl 0.09 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 picd switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.24 0.23 + 0.008*sl 0.23 + 0.008*sl 0.23 + 0.008*sl t phl 0.24 0.22 + 0.011*sl 0.22 + 0.011*sl 0.22 + 0.010*sl t r 0.13 0.10 + 0.013*sl 0.10 + 0.015*sl 0.09 + 0.016*sl t f 0.13 0.10 + 0.015*sl 0.10 + 0.018*sl 0.09 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 picu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.23 0.21 + 0.010*sl 0.22 + 0.008*sl 0.22 + 0.007*sl t phl 0.24 0.22 + 0.012*sl 0.22 + 0.010*sl 0.22 + 0.010*sl t r 0.13 0.11 + 0.014*sl 0.11 + 0.014*sl 0.10 + 0.015*sl t f 0.13 0.10 + 0.018*sl 0.10 + 0.017*sl 0.09 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 plic switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.49 0.47 + 0.009*sl 0.48 + 0.007*sl 0.48 + 0.007*sl t phl 0.78 0.76 + 0.010*sl 0.76 + 0.012*sl 0.80 + 0.005*sl t r 0.15 0.13 + 0.011*sl 0.12 + 0.012*sl 0.12 + 0.013*sl t f 0.16 0.13 + 0.012*sl 0.13 + 0.014*sl 0.15 + 0.011*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 4-11 STD80/stdm80 pvic/pvicd/pvicu cmos level input buffers STD80 plicd switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.48 0.47 + 0.008*sl 0.47 + 0.007*sl 0.47 + 0.007*sl t phl 0.79 0.77 + 0.011*sl 0.76 + 0.012*sl 0.81 + 0.006*sl t r 0.15 0.12 + 0.012*sl 0.12 + 0.012*sl 0.12 + 0.013*sl t f 0.17 0.15 + 0.012*sl 0.15 + 0.012*sl 0.16 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 plicu switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.49 0.48 + 0.008*sl 0.48 + 0.008*sl 0.49 + 0.006*sl t phl 0.78 0.76 + 0.011*sl 0.77 + 0.007*sl 0.74 + 0.011*sl t r 0.15 0.12 + 0.013*sl 0.13 + 0.011*sl 0.11 + 0.014*sl t f 0.17 0.15 + 0.012*sl 0.14 + 0.016*sl 0.19 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = stdm80 pic switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.27 0.25 + 0.011*sl 0.25 + 0.009*sl 0.26 + 0.009*sl t phl 0.28 0.26 + 0.012*sl 0.26 + 0.010*sl 0.27 + 0.010*sl t r 0.17 0.14 + 0.016*sl 0.13 + 0.019*sl 0.13 + 0.019*sl t f 0.16 0.12 + 0.019*sl 0.11 + 0.023*sl 0.19 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 picd switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.26 0.24 + 0.007*sl 0.23 + 0.011*sl 0.26 + 0.009*sl t phl 0.29 0.26 + 0.013*sl 0.27 + 0.011*sl 0.27 + 0.010*sl t r 0.18 0.14 + 0.019*sl 0.15 + 0.016*sl 0.11 + 0.020*sl t f 0.17 0.13 + 0.020*sl 0.13 + 0.018*sl 0.11 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-12 sec asic pvic/pvicd/pvicu cmos level input buffers stdm80 picu switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.28 0.25 + 0.011*sl 0.26 + 0.009*sl 0.26 + 0.009*sl t phl 0.29 0.27 + 0.009*sl 0.26 + 0.011*sl 0.27 + 0.010*sl t r 0.17 0.14 + 0.016*sl 0.13 + 0.018*sl 0.11 + 0.019*sl t f 0.17 0.12 + 0.022*sl 0.13 + 0.021*sl 0.19 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 phic switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.43 0.42 + 0.010*sl 0.42 + 0.009*sl 0.43 + 0.008*sl t phl 0.63 0.63 + 0.003*sl 0.60 + 0.012*sl 0.64 + 0.008*sl t r 0.16 0.11 + 0.022*sl 0.13 + 0.017*sl 0.13 + 0.017*sl t f 0.20 0.17 + 0.012*sl 0.17 + 0.014*sl 0.18 + 0.012*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 phicd switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.44 0.43 + 0.005*sl 0.42 + 0.009*sl 0.44 + 0.007*sl t phl 0.64 0.63 + 0.004*sl 0.61 + 0.012*sl 0.64 + 0.009*sl t r 0.15 0.13 + 0.013*sl 0.12 + 0.017*sl 0.12 + 0.017*sl t f 0.20 0.17 + 0.014*sl 0.17 + 0.014*sl 0.17 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 phicu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.44 0.42 + 0.009*sl 0.42 + 0.009*sl 0.43 + 0.008*sl t phl 0.64 0.63 + 0.002*sl 0.61 + 0.013*sl 0.65 + 0.008*sl t r 0.15 0.12 + 0.016*sl 0.11 + 0.019*sl 0.15 + 0.015*sl t f 0.20 0.16 + 0.018*sl 0.18 + 0.013*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-13 STD80/stdm80 pvil/pvild/pvilu ttl schmitt trigger level input buffers cell availability logic symbol library 5v operation 3.3v operation STD80 pil/pild/pilu C stdm80 phil/phild/philu C y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 STD80 pi pil/pild/pilu 1.6 stdm80 pi phil/phild/philu 1.4 STD80/stdm80 pvil/pvild/pvilu 1.0
STD80/stdm80 4-14 sec asic pvil/pvild/pvilu ttl schmitt trigger level input buffers STD80 pil switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.44 0.43 + 0.009*sl 0.43 + 0.008*sl 0.43 + 0.008*sl t phl 1.52 1.49 + 0.014*sl 1.49 + 0.013*sl 1.51 + 0.011*sl t r 0.16 0.14 + 0.014*sl 0.13 + 0.015*sl 0.13 + 0.015*sl t f 0.52 0.49 + 0.013*sl 0.50 + 0.011*sl 0.51 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 pild switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.46 0.44 + 0.009*sl 0.44 + 0.008*sl 0.44 + 0.008*sl t phl 1.53 1.50 + 0.014*sl 1.51 + 0.013*sl 1.52 + 0.011*sl t r 0.17 0.14 + 0.014*sl 0.14 + 0.015*sl 0.14 + 0.015*sl t f 0.52 0.50 + 0.012*sl 0.50 + 0.012*sl 0.51 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 pilu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.45 0.43 + 0.009*sl 0.43 + 0.008*sl 0.44 + 0.008*sl t phl 1.55 1.52 + 0.014*sl 1.53 + 0.013*sl 1.54 + 0.011*sl t r 0.17 0.14 + 0.015*sl 0.14 + 0.014*sl 0.14 + 0.015*sl t f 0.52 0.50 + 0.013*sl 0.50 + 0.012*sl 0.51 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = stdm80 phil switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.51 + 0.009*sl 0.51 + 0.009*sl 0.51 + 0.008*sl t phl 2.21 2.19 + 0.010*sl 2.19 + 0.010*sl 2.21 + 0.008*sl t r 0.15 0.12 + 0.016*sl 0.12 + 0.017*sl 0.11 + 0.017*sl t f 0.20 0.15 + 0.024*sl 0.19 + 0.012*sl 0.11 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-15 STD80/stdm80 pvil/pvild/pvilu ttl schmitt trigger level input buffers stdm80 phild switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.54 0.52 + 0.009*sl 0.52 + 0.008*sl 0.53 + 0.008*sl t phl 2.22 2.20 + 0.013*sl 2.21 + 0.010*sl 2.22 + 0.008*sl t r 0.15 0.12 + 0.017*sl 0.12 + 0.016*sl 0.10 + 0.019*sl t f 0.20 0.16 + 0.020*sl 0.18 + 0.012*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 philu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.51 + 0.009*sl 0.51 + 0.008*sl 0.52 + 0.008*sl t phl 2.24 2.22 + 0.013*sl 2.22 + 0.010*sl 2.24 + 0.009*sl t r 0.15 0.12 + 0.017*sl 0.12 + 0.017*sl 0.10 + 0.018*sl t f 0.22 0.19 + 0.016*sl 0.20 + 0.010*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-16 sec asic pvis/pvisd/pvisu cmos schmitt trigger level input buffers cell availability logic symbol notes: 1. STD80 3.3v interface input buffers (plis/plisd/plisu) are not available to receive input signals from 5v devices. 2. fail-safe input buffers are available to receive signals from 5v devices without reducing reliability. however, if you want to use fail-safe input buffers, please contact to sec asic ?rst. library 5v operation 3.3v operation STD80 pis/pisd/pisu plis/plisd/plisu stdm80 phis/phisd/phisu pis/pisd/pisu y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 STD80 pi pis/pisd/pisu 1.6 plis/plisd/plisu 1.2 stdm80 pi pis/pisd/pisu 1.9 phis/phisd/phisu 1.2 STD80/stdm80 pvis/pvisd/pvisu 1.0
sec asic 4-17 STD80/stdm80 pvis/pvisd/pvisu cmos schmitt trigger level input buffers STD80 pis switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.28 0.26 + 0.013*sl 0.26 + 0.011*sl 0.26 + 0.011*sl t phl 0.43 0.40 + 0.015*sl 0.40 + 0.013*sl 0.41 + 0.012*sl t r 0.16 0.12 + 0.023*sl 0.12 + 0.022*sl 0.11 + 0.023*sl t f 0.20 0.17 + 0.018*sl 0.17 + 0.017*sl 0.17 + 0.017*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 pisd switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.29 0.27 + 0.012*sl 0.27 + 0.012*sl 0.27 + 0.011*sl t phl 0.44 0.41 + 0.015*sl 0.41 + 0.013*sl 0.42 + 0.012*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.12 + 0.023*sl t f 0.20 0.17 + 0.018*sl 0.17 + 0.017*sl 0.16 + 0.017*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 pisu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.29 0.26 + 0.013*sl 0.27 + 0.012*sl 0.27 + 0.011*sl t phl 0.44 0.40 + 0.015*sl 0.41 + 0.013*sl 0.42 + 0.012*sl t r 0.16 0.12 + 0.023*sl 0.12 + 0.022*sl 0.11 + 0.023*sl t f 0.20 0.17 + 0.018*sl 0.17 + 0.017*sl 0.17 + 0.017*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 plis switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.73 + 0.008*sl 0.73 + 0.008*sl 0.74 + 0.006*sl t phl 1.63 1.61 + 0.010*sl 1.61 + 0.011*sl 1.65 + 0.006*sl t r 0.15 0.13 + 0.013*sl 0.13 + 0.011*sl 0.11 + 0.014*sl t f 0.17 0.12 + 0.023*sl 0.15 + 0.013*sl 0.18 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 4-18 sec asic pvis/pvisd/pvisu cmos schmitt trigger level input buffers STD80 plisd switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.77 0.75 + 0.008*sl 0.75 + 0.007*sl 0.76 + 0.007*sl t phl 1.65 1.63 + 0.011*sl 1.63 + 0.011*sl 1.66 + 0.007*sl t r 0.15 0.13 + 0.012*sl 0.13 + 0.011*sl 0.11 + 0.013*sl t f 0.17 0.15 + 0.014*sl 0.15 + 0.010*sl 0.15 + 0.011*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 plisu switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.75 + 0.008*sl 0.75 + 0.007*sl 0.75 + 0.007*sl t phl 1.64 1.62 + 0.010*sl 1.62 + 0.012*sl 1.66 + 0.006*sl t r 0.15 0.13 + 0.011*sl 0.13 + 0.012*sl 0.13 + 0.012*sl t f 0.16 0.14 + 0.011*sl 0.13 + 0.013*sl 0.13 + 0.013*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = stdm80 pis switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.51 0.50 + 0.009*sl 0.50 + 0.008*sl 0.51 + 0.007*sl t phl 1.11 1.09 + 0.012*sl 1.09 + 0.009*sl 1.11 + 0.008*sl t r 0.25 0.22 + 0.018*sl 0.24 + 0.008*sl 0.20 + 0.012*sl t f 0.34 0.32 + 0.010*sl 0.32 + 0.010*sl 0.32 + 0.010*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 pisd switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.52 + 0.008*sl 0.52 + 0.008*sl 0.53 + 0.007*sl t phl 1.13 1.11 + 0.010*sl 1.11 + 0.010*sl 1.13 + 0.008*sl t r 0.24 0.20 + 0.017*sl 0.22 + 0.011*sl 0.22 + 0.011*sl t f 0.34 0.32 + 0.012*sl 0.32 + 0.010*sl 0.33 + 0.009*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-19 STD80/stdm80 pvis/pvisd/pvisu cmos schmitt trigger level input buffers stdm80 pisu switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.51 + 0.009*sl 0.52 + 0.008*sl 0.53 + 0.007*sl t phl 1.12 1.10 + 0.011*sl 1.10 + 0.009*sl 1.12 + 0.008*sl t r 0.23 0.22 + 0.008*sl 0.21 + 0.011*sl 0.21 + 0.011*sl t f 0.36 0.34 + 0.010*sl 0.34 + 0.008*sl 0.33 + 0.010*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 phis switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.55 0.53 + 0.009*sl 0.53 + 0.009*sl 0.54 + 0.008*sl t phl 1.07 1.06 + 0.005*sl 1.04 + 0.011*sl 1.07 + 0.009*sl t r 0.16 0.11 + 0.022*sl 0.13 + 0.016*sl 0.13 + 0.016*sl t f 0.19 0.17 + 0.014*sl 0.17 + 0.014*sl 0.17 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 phisd switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.55 0.53 + 0.009*sl 0.53 + 0.009*sl 0.53 + 0.008*sl t phl 1.08 1.06 + 0.009*sl 1.06 + 0.011*sl 1.08 + 0.009*sl t r 0.15 0.12 + 0.014*sl 0.12 + 0.017*sl 0.09 + 0.019*sl t f 0.19 0.17 + 0.015*sl 0.17 + 0.013*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 phisu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.56 0.54 + 0.009*sl 0.54 + 0.009*sl 0.54 + 0.008*sl t phl 1.08 1.06 + 0.009*sl 1.05 + 0.011*sl 1.08 + 0.009*sl t r 0.16 0.11 + 0.023*sl 0.13 + 0.015*sl 0.09 + 0.019*sl t f 0.20 0.17 + 0.013*sl 0.17 + 0.013*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-20 sec asic pvit/pvitd/pvitu ttl level input buffers cell availability logic symbol library 5v operation 3.3v operation STD80 pit/pitd/pitu C stdm80 phit/phitd/phitu C y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 STD80 pi pit/pitd/pitu 1.6 stdm80 pi phit/phitd/phitu 1.4 STD80/stdm80 pvit/pvitd/pvitu 1.0
sec asic 4-21 STD80/stdm80 pvit/pvitd/pvitu ttl level input buffers STD80 pit switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.011*sl 0.23 + 0.011*sl 0.23 + 0.011*sl t phl 0.32 0.30 + 0.011*sl 0.31 + 0.009*sl 0.32 + 0.008*sl t r 0.15 0.11 + 0.023*sl 0.11 + 0.023*sl 0.10 + 0.024*sl t f 0.17 0.15 + 0.010*sl 0.15 + 0.010*sl 0.15 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 pitd switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.26 0.24 + 0.011*sl 0.24 + 0.011*sl 0.24 + 0.011*sl t phl 0.34 0.31 + 0.011*sl 0.32 + 0.009*sl 0.33 + 0.008*sl t r 0.15 0.11 + 0.023*sl 0.11 + 0.023*sl 0.10 + 0.024*sl t f 0.17 0.15 + 0.010*sl 0.15 + 0.010*sl 0.15 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = STD80 pitu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.011*sl 0.23 + 0.011*sl 0.23 + 0.011*sl t phl 0.33 0.31 + 0.011*sl 0.31 + 0.009*sl 0.32 + 0.007*sl t r 0.15 0.11 + 0.024*sl 0.11 + 0.023*sl 0.10 + 0.024*sl t f 0.17 0.15 + 0.009*sl 0.15 + 0.010*sl 0.15 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = stdm80 phit switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.009*sl 0.23 + 0.009*sl 0.23 + 0.008*sl t phl 0.93 0.91 + 0.007*sl 0.90 + 0.011*sl 0.93 + 0.008*sl t r 0.17 0.16 + 0.004*sl 0.12 + 0.016*sl 0.11 + 0.017*sl t f 0.20 0.17 + 0.012*sl 0.17 + 0.014*sl 0.15 + 0.016*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-22 sec asic pvit/pvitd/pvitu ttl level input buffers stdm80 phitd switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.27 0.26 + 0.009*sl 0.26 + 0.009*sl 0.26 + 0.008*sl t phl 0.93 0.92 + 0.006*sl 0.91 + 0.011*sl 0.94 + 0.009*sl t r 0.16 0.13 + 0.014*sl 0.12 + 0.016*sl 0.11 + 0.017*sl t f 0.20 0.17 + 0.017*sl 0.17 + 0.014*sl 0.17 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 phitu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.009*sl 0.23 + 0.009*sl 0.23 + 0.008*sl t phl 0.93 0.92 + 0.008*sl 0.91 + 0.011*sl 0.94 + 0.008*sl t r 0.17 0.16 + 0.004*sl 0.12 + 0.016*sl 0.11 + 0.018*sl t f 0.20 0.17 + 0.013*sl 0.17 + 0.013*sl 0.15 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-23 STD80/stdm80 output buffers cell list cell name function description STD80 pob(1/2/4/8/12/16/20/24) 5v normal output buffers pob(12/16/20/24)sh 5v normal output buffers with high slew-rate pob(4/8/12/16/20/24)sm 5v normal output buffers with medium slew-rate pod(1/2/4/8/12/16/20/24) 5v open drain output buffers pod(12/16/20/24)sh 5v open drain output buffers with high slew-rate pod(4/8/12/16/20/24)sm 5v open drain output buffers with medium slew-rate pot(1/2/4/8/12/16/20/24) 5v tri-state output buffers pot(12/16/20/24)sh 5v tri-state output buffers with high slew-rate pot(4/8/12/16/20/24)sm 5v tri-state output buffers with medium slew-rate plob(1/2/4/6/8/10/12/16) 3.3v interface normal output buffers plob(4/6/8/10/12/16)sm 3.3v interface normal output buffers with medium slew-rate plod(1/2/4/6/8/10/12/16) 3.3v interface open drain output buffers plod(4/6/8/10/12/16)sm 3.3v interface open drain output buffers with medium slew-rate plot(1/2/4/6/8/10/12/16) 3.3v interface tri-state output buffers plot(4/6/8/10/12/16)sm 3.3v interface tri-state output buffers with medium slew-rate stdm80 pob(1/2/4/6/8/10/12/16) 3.3v normal output buffers pob(4/6/8/10/12/16)sm 3.3v normal output buffers with medium slew-rate control pod(1/2/4/6/8/10/12/16) 3.3v open drain output buffers pod(4/6/8/10/12/16)sm 3.3v open drain output buffers with medium slew-rate control pot(1/2/4/6/8/10/12/16) 3.3v tri-state output buffers pot(4/6/8/10/12/16)sm 3.3v tri-state output buffers with medium slew-rate control phob(1/2/4/8/12/16/20/24) 5v interface normal output buffers phob(12/16/20/24)sh 5v interface normal output buffers with high slew-rate control phob(4/8/12/16/20/24)sm 5v interface normal output buffers with medium slew-rate control phod(1/2/4/8/12/16/20/24) 5v interface open drain output buffers phod(12/16/20/24)sh 5v interface open drain output buffers with high slew-rate control phod(4/8/12/16/20/24)sm 5v interface open drain output buffers with medium slew-rate control phot(1/2/4/8/12/16/20/24) 5v interface tri-state output buffers phot(12/16/20/24)sh 5v interface tri-state output buffers with high slew-rate control phot(4/8/12/16/20/24)sm 5v interface tri-state output buffers with medium slew-rate control
STD80/stdm80 4-24 sec asic pvobyz normal output buffers cell availability logic symbol truth table i/o slot library 5v operation 3.3v operation STD80 pob(1/2/4/8/12/16/20/24) pob(12/16/20/24)sh pob(4/8/12/16/20/24)sm plob(1/2/4/6/8/10/12/16) plob(4/6/8/10/12/16)sm stdm80 phob(1/2/4/8/12/16/20/24) phob(12/16/20/24)sh phob(4/8/12/16/20/24)sm pob(1/2/4/6/8/10/12/16) pob(4/6/8/10/12/16)sm apad 00 11 STD80/stdm80 pvobyz 1.0 pa d a input load (sl) STD80 a pob(1/2/4/8/12/16) 5.5 pob20 9.5 pob24 10.2 pob12sh 20.6 pob16sh 20.0 pob(20/24)sh 10.44 pob4sm 21.3 pob(8/12)sm 20.6 pob16sm 20.0 pob(20/24)sm 11.7 plob(1/2/4/6/8/10/12/16) 2.3 plob(4/6/8/10/12/16)sm 2.3 stdm80 a pob1 6.5 pob(2/12/16) 6.1 pob(4/6) 4.8 pob8 4.6 pob10 5.2 pob(4/6/8/10/12)sm 13.3 pob16sm 13.4 phob(1/2/4/8/12/16/20/24) 2.8 phob(12/16/20/24)sh 2.8 phob(4/8/12/16/20/24)sm 2.8
sec asic 4-25 STD80/stdm80 pvobyz normal output buffers STD80 pob1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 14.98 0.36 + 0.292*cl 0.37 + 0.292*cl 0.37 + 0.292*cl t phl 12.03 0.39 + 0.233*cl 0.39 + 0.233*cl 0.39 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 7.60 0.30 + 0.146*cl 0.29 + 0.146*cl 0.30 + 0.146*cl t phl 6.13 0.31 + 0.116*cl 0.31 + 0.116*cl 0.31 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.98 0.29 + 0.094*cl 0.29 + 0.094*cl 0.29 + 0.094*cl t phl 4.02 0.31 + 0.074*cl 0.30 + 0.074*cl 0.31 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.70 0.36 + 0.047*cl 0.36 + 0.047*cl 0.36 + 0.047*cl t phl 2.22 0.36 + 0.037*cl 0.36 + 0.037*cl 0.36 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-26 sec asic pvobyz normal output buffers STD80 pob12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.14 0.42 + 0.034*cl 0.42 + 0.034*cl 0.41 + 0.035*cl t phl 1.78 0.42 + 0.027*cl 0.42 + 0.027*cl 0.41 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.77 0.52 + 0.025*cl 0.52 + 0.025*cl 0.51 + 0.025*cl t phl 1.49 0.50 + 0.020*cl 0.50 + 0.020*cl 0.50 + 0.020*cl t r 2.97 0.13 + 0.057*cl 0.12 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob20 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.36 0.37 + 0.020*cl 0.37 + 0.020*cl 0.36 + 0.020*cl t phl 1.24 0.45 + 0.016*cl 0.45 + 0.016*cl 0.45 + 0.016*cl t r 2.33 0.10 + 0.045*cl 0.08 + 0.045*cl 0.09 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.12 + 0.032*cl 0.11 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob24 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.28 0.41 + 0.017*cl 0.41 + 0.017*cl 0.40 + 0.017*cl t phl 1.17 0.48 + 0.014*cl 0.48 + 0.014*cl 0.48 + 0.014*cl t r 2.07 0.10 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.14 + 0.028*cl 0.13 + 0.028*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-27 STD80/stdm80 pvobyz normal output buffers STD80 pob12sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.78 1.00 + 0.036*cl 1.02 + 0.035*cl 1.03 + 0.035*cl t phl 3.24 1.65 + 0.032*cl 1.76 + 0.030*cl 1.81 + 0.030*cl t r 4.33 0.48 + 0.077*cl 0.44 + 0.078*cl 0.41 + 0.078*cl t f 3.73 0.96 + 0.055*cl 0.97 + 0.055*cl 0.97 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob16sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.57 1.22 + 0.027*cl 1.28 + 0.026*cl 1.31 + 0.026*cl t phl 2.95 1.70 + 0.025*cl 1.82 + 0.024*cl 1.87 + 0.023*cl t r 3.42 0.69 + 0.055*cl 0.66 + 0.055*cl 0.65 + 0.055*cl t f 2.99 0.95 + 0.041*cl 1.01 + 0.040*cl 1.02 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob20sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 0.98 + 0.021*cl 1.03 + 0.020*cl 1.04 + 0.020*cl t phl 2.09 1.22 + 0.017*cl 1.26 + 0.017*cl 1.28 + 0.017*cl t r 2.70 0.56 + 0.043*cl 0.53 + 0.043*cl 0.52 + 0.043*cl t f 2.22 0.69 + 0.031*cl 0.68 + 0.031*cl 0.67 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob24sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 1.06 + 0.019*cl 1.12 + 0.019*cl 1.15 + 0.018*cl t phl 2.15 1.36 + 0.016*cl 1.40 + 0.015*cl 1.42 + 0.015*cl t r 2.52 0.63 + 0.038*cl 0.63 + 0.038*cl 0.61 + 0.038*cl t f 2.14 0.79 + 0.027*cl 0.79 + 0.027*cl 0.78 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-28 sec asic pvobyz normal output buffers STD80 pob4sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.22 0.53 + 0.094*cl 0.53 + 0.094*cl 0.53 + 0.094*cl t phl 4.76 1.03 + 0.074*cl 1.04 + 0.074*cl 1.05 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.23 + 0.212*cl 0.24 + 0.212*cl t f 8.05 0.42 + 0.153*cl 0.37 + 0.153*cl 0.35 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob8sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.16 0.81 + 0.047*cl 0.82 + 0.047*cl 0.82 + 0.047*cl t phl 3.37 1.41 + 0.039*cl 1.48 + 0.038*cl 1.52 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.29 + 0.105*cl 0.28 + 0.105*cl t f 4.46 0.74 + 0.074*cl 0.72 + 0.075*cl 0.69 + 0.075*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob12sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.59 0.85 + 0.035*cl 0.87 + 0.035*cl 0.86 + 0.035*cl t phl 2.88 1.34 + 0.031*cl 1.44 + 0.029*cl 1.48 + 0.029*cl t r 4.21 0.40 + 0.076*cl 0.36 + 0.077*cl 0.34 + 0.077*cl t f 3.54 0.80 + 0.055*cl 0.82 + 0.055*cl 0.82 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob16sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.27 0.96 + 0.026*cl 1.00 + 0.026*cl 1.01 + 0.026*cl t phl 2.46 1.28 + 0.024*cl 1.36 + 0.022*cl 1.41 + 0.022*cl t r 3.27 0.52 + 0.055*cl 0.49 + 0.055*cl 0.48 + 0.056*cl t f 2.77 0.73 + 0.041*cl 0.77 + 0.040*cl 0.78 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-29 STD80/stdm80 pvobyz normal output buffers STD80 pob20sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.70 0.69 + 0.020*cl 0.70 + 0.020*cl 0.70 + 0.020*cl t phl 1.72 0.83 + 0.018*cl 0.88 + 0.017*cl 0.92 + 0.017*cl t r 2.52 0.35 + 0.043*cl 0.33 + 0.044*cl 0.31 + 0.044*cl t f 2.10 0.54 + 0.031*cl 0.55 + 0.031*cl 0.55 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pob24sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.68 0.77 + 0.018*cl 0.79 + 0.018*cl 0.81 + 0.018*cl t phl 1.74 0.91 + 0.017*cl 0.98 + 0.016*cl 1.02 + 0.015*cl t r 2.31 0.42 + 0.038*cl 0.40 + 0.038*cl 0.39 + 0.038*cl t f 2.01 0.62 + 0.028*cl 0.63 + 0.028*cl 0.64 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob1 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 21.37 0.92 + 0.409*cl 0.93 + 0.409*cl 0.92 + 0.409*cl t phl 13.83 0.63 + 0.264*cl 0.63 + 0.264*cl 0.63 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob2 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.45 0.80 + 0.193*cl 0.80 + 0.193*cl 0.80 + 0.193*cl t phl 6.71 0.54 + 0.124*cl 0.54 + 0.123*cl 0.53 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-30 sec asic pvobyz normal output buffers STD80 plob4 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.52 0.70 + 0.096*cl 0.69 + 0.097*cl 0.70 + 0.096*cl t phl 3.66 0.58 + 0.062*cl 0.58 + 0.062*cl 0.58 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.15 + 0.133*cl 0.16 + 0.133*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob6 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.98 0.76 + 0.064*cl 0.76 + 0.064*cl 0.76 + 0.064*cl t phl 2.73 0.69 + 0.041*cl 0.67 + 0.041*cl 0.67 + 0.041*cl t r 7.52 0.20 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.58 0.17 + 0.088*cl 0.14 + 0.089*cl 0.13 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob8 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.24 0.84 + 0.048*cl 0.83 + 0.048*cl 0.83 + 0.048*cl t phl 2.33 0.81 + 0.030*cl 0.81 + 0.030*cl 0.79 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.24 + 0.065*cl 0.22 + 0.066*cl 0.17 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob10 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.90 0.98 + 0.038*cl 0.97 + 0.039*cl 0.97 + 0.039*cl t phl 2.06 0.83 + 0.025*cl 0.83 + 0.025*cl 0.83 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.21 + 0.052*cl 0.21 + 0.052*cl 0.17 + 0.053*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-31 STD80/stdm80 pvobyz normal output buffers STD80 plob12 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.72 1.11 + 0.032*cl 1.11 + 0.032*cl 1.11 + 0.032*cl t phl 1.94 0.90 + 0.021*cl 0.92 + 0.021*cl 0.92 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.27 + 0.043*cl 0.24 + 0.044*cl 0.24 + 0.044*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob16 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.49 1.28 + 0.024*cl 1.26 + 0.024*cl 1.27 + 0.024*cl t phl 1.86 1.04 + 0.016*cl 1.07 + 0.016*cl 1.08 + 0.016*cl t r 3.00 0.25 + 0.055*cl 0.23 + 0.055*cl 0.24 + 0.055*cl t f 1.98 0.36 + 0.033*cl 0.38 + 0.032*cl 0.32 + 0.033*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob4sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 6.25 1.29 + 0.099*cl 1.28 + 0.099*cl 1.29 + 0.099*cl t phl 4.16 0.97 + 0.064*cl 0.97 + 0.064*cl 0.98 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.26 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob6sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.76 1.48 + 0.066*cl 1.48 + 0.066*cl 1.48 + 0.066*cl t phl 3.43 1.31 + 0.042*cl 1.32 + 0.042*cl 1.32 + 0.042*cl t r 7.71 0.27 + 0.149*cl 0.24 + 0.149*cl 0.25 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.37 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-32 sec asic pvobyz normal output buffers STD80 plob8sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.11 1.66 + 0.049*cl 1.66 + 0.049*cl 1.67 + 0.049*cl t phl 3.21 1.58 + 0.033*cl 1.63 + 0.032*cl 1.65 + 0.032*cl t r 5.86 0.35 + 0.110*cl 0.30 + 0.111*cl 0.29 + 0.111*cl t f 3.91 0.69 + 0.065*cl 0.65 + 0.065*cl 0.60 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob10sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.60 1.67 + 0.039*cl 1.67 + 0.039*cl 1.67 + 0.039*cl t phl 2.85 1.50 + 0.027*cl 1.57 + 0.026*cl 1.61 + 0.026*cl t r 4.72 0.42 + 0.086*cl 0.36 + 0.087*cl 0.34 + 0.087*cl t f 3.34 0.85 + 0.050*cl 0.78 + 0.051*cl 0.80 + 0.050*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob12sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.46 1.83 + 0.032*cl 1.85 + 0.032*cl 1.85 + 0.032*cl t phl 2.89 1.66 + 0.025*cl 1.77 + 0.023*cl 1.83 + 0.022*cl t r 4.07 0.54 + 0.071*cl 0.46 + 0.072*cl 0.46 + 0.072*cl t f 3.09 1.01 + 0.042*cl 1.04 + 0.041*cl 1.00 + 0.042*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plob16sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.40 2.11 + 0.026*cl 2.17 + 0.025*cl 2.18 + 0.025*cl t phl 3.07 1.95 + 0.022*cl 2.09 + 0.020*cl 2.17 + 0.020*cl t r 3.39 0.75 + 0.053*cl 0.68 + 0.054*cl 0.66 + 0.054*cl t f 2.88 1.24 + 0.033*cl 1.35 + 0.031*cl 1.28 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-33 STD80/stdm80 pvobyz normal output buffers stdm80 pob1 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 20.96 0.52 + 0.409*cl 0.52 + 0.409*cl 0.52 + 0.409*cl t phl 13.70 0.50 + 0.264*cl 0.50 + 0.264*cl 0.50 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.05 0.40 + 0.193*cl 0.40 + 0.193*cl 0.40 + 0.193*cl t phl 6.58 0.41 + 0.124*cl 0.41 + 0.124*cl 0.41 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.18 0.36 + 0.096*cl 0.36 + 0.096*cl 0.36 + 0.096*cl t phl 3.54 0.46 + 0.062*cl 0.46 + 0.062*cl 0.45 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.26 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.63 0.41 + 0.064*cl 0.41 + 0.064*cl 0.41 + 0.064*cl t phl 2.60 0.56 + 0.041*cl 0.55 + 0.041*cl 0.55 + 0.041*cl t r 7.52 0.20 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.58 0.16 + 0.088*cl 0.15 + 0.089*cl 0.13 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-34 sec asic pvobyz normal output buffers stdm80 pob8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.89 0.48 + 0.048*cl 0.48 + 0.048*cl 0.48 + 0.048*cl t phl 2.20 0.69 + 0.030*cl 0.68 + 0.030*cl 0.66 + 0.031*cl t r 5.67 0.18 + 0.110*cl 0.16 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.24 + 0.065*cl 0.20 + 0.066*cl 0.19 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob10 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.50 0.58 + 0.038*cl 0.57 + 0.039*cl 0.57 + 0.039*cl t phl 1.94 0.71 + 0.025*cl 0.71 + 0.025*cl 0.71 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.17 + 0.088*cl 0.17 + 0.088*cl t f 2.84 0.22 + 0.052*cl 0.21 + 0.052*cl 0.18 + 0.053*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob12 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.27 0.67 + 0.032*cl 0.67 + 0.032*cl 0.66 + 0.032*cl t phl 1.82 0.78 + 0.021*cl 0.78 + 0.021*cl 0.79 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.19 + 0.073*cl 0.17 + 0.073*cl t f 2.43 0.28 + 0.043*cl 0.25 + 0.043*cl 0.24 + 0.044*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob16 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.04 0.83 + 0.024*cl 0.83 + 0.024*cl 0.82 + 0.024*cl t phl 1.73 0.92 + 0.016*cl 0.94 + 0.016*cl 0.95 + 0.016*cl t r 3.00 0.26 + 0.055*cl 0.23 + 0.055*cl 0.23 + 0.055*cl t f 1.99 0.37 + 0.032*cl 0.37 + 0.032*cl 0.34 + 0.033*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-35 STD80/stdm80 pvobyz normal output buffers stdm80 pob4sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.50 0.54 + 0.099*cl 0.54 + 0.099*cl 0.54 + 0.099*cl t phl 3.98 0.79 + 0.064*cl 0.78 + 0.064*cl 0.79 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.26 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob6sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.98 0.72 + 0.065*cl 0.69 + 0.066*cl 0.70 + 0.066*cl t phl 3.24 1.12 + 0.042*cl 1.14 + 0.042*cl 1.14 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.26 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.38 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob8sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.32 0.87 + 0.049*cl 0.87 + 0.049*cl 0.87 + 0.049*cl t phl 3.02 1.39 + 0.033*cl 1.43 + 0.032*cl 1.46 + 0.032*cl t r 5.85 0.32 + 0.110*cl 0.29 + 0.111*cl 0.27 + 0.111*cl t f 3.91 0.69 + 0.064*cl 0.62 + 0.065*cl 0.60 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob10sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.82 0.88 + 0.039*cl 0.89 + 0.039*cl 0.88 + 0.039*cl t phl 2.66 1.31 + 0.027*cl 1.38 + 0.026*cl 1.43 + 0.026*cl t r 4.70 0.38 + 0.086*cl 0.33 + 0.087*cl 0.32 + 0.087*cl t f 3.34 0.85 + 0.050*cl 0.79 + 0.051*cl 0.80 + 0.050*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-36 sec asic pvobyz normal output buffers stdm80 pob12sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.66 1.04 + 0.032*cl 1.06 + 0.032*cl 1.06 + 0.032*cl t phl 2.70 1.47 + 0.025*cl 1.58 + 0.023*cl 1.63 + 0.022*cl t r 4.05 0.50 + 0.071*cl 0.45 + 0.072*cl 0.42 + 0.072*cl t f 3.09 1.03 + 0.041*cl 1.02 + 0.041*cl 1.00 + 0.042*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pob16sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.59 1.31 + 0.026*cl 1.35 + 0.025*cl 1.37 + 0.025*cl t phl 2.87 1.76 + 0.022*cl 1.89 + 0.020*cl 1.98 + 0.020*cl t r 3.36 0.70 + 0.053*cl 0.66 + 0.054*cl 0.66 + 0.054*cl t f 2.88 1.25 + 0.033*cl 1.30 + 0.032*cl 1.31 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob1 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 15.36 0.75 + 0.292*cl 0.75 + 0.292*cl 0.75 + 0.292*cl t phl 12.37 0.73 + 0.233*cl 0.61 + 0.234*cl 0.83 + 0.232*cl t r 33.59 0.59 + 0.660*cl 0.59 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob2 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 7.99 0.68 + 0.146*cl 0.68 + 0.146*cl 0.68 + 0.146*cl t phl 6.46 0.61 + 0.117*cl 0.65 + 0.116*cl 0.75 + 0.115*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-37 STD80/stdm80 pvobyz normal output buffers stdm80 phob4 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.37 0.68 + 0.094*cl 0.68 + 0.094*cl 0.68 + 0.094*cl t phl 4.35 0.64 + 0.074*cl 0.64 + 0.074*cl 0.56 + 0.075*cl t r 10.81 0.21 + 0.212*cl 0.22 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.14 + 0.155*cl 0.15 + 0.155*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob8 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.09 0.75 + 0.047*cl 0.74 + 0.047*cl 0.75 + 0.047*cl t phl 2.56 0.70 + 0.037*cl 0.70 + 0.037*cl 0.76 + 0.036*cl t r 5.43 0.13 + 0.106*cl 0.12 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.09 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob12 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.53 0.81 + 0.034*cl 0.81 + 0.034*cl 0.81 + 0.035*cl t phl 2.11 0.73 + 0.028*cl 0.76 + 0.027*cl 0.81 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.12 + 0.056*cl 0.08 + 0.057*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob16 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.16 0.91 + 0.025*cl 0.91 + 0.025*cl 0.91 + 0.025*cl t phl 1.83 0.83 + 0.020*cl 0.77 + 0.021*cl 0.88 + 0.019*cl t r 2.97 0.14 + 0.057*cl 0.12 + 0.057*cl 0.11 + 0.057*cl t f 2.20 0.15 + 0.041*cl 0.14 + 0.041*cl 0.14 + 0.041*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-38 sec asic pvobyz normal output buffers stdm80 phob20 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.90 0.91 + 0.020*cl 0.90 + 0.020*cl 0.91 + 0.020*cl t phl 1.65 0.87 + 0.016*cl 0.87 + 0.016*cl 0.86 + 0.016*cl t r 2.34 0.11 + 0.045*cl 0.08 + 0.045*cl 0.10 + 0.045*cl t f 1.75 0.15 + 0.032*cl 0.10 + 0.033*cl 0.13 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob24 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.85 0.99 + 0.017*cl 0.98 + 0.017*cl 0.98 + 0.017*cl t phl 1.60 0.91 + 0.014*cl 0.92 + 0.014*cl 0.91 + 0.014*cl t r 2.08 0.12 + 0.039*cl 0.11 + 0.039*cl 0.08 + 0.040*cl t f 1.57 0.17 + 0.028*cl 0.13 + 0.028*cl 0.13 + 0.028*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob12sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.76 1.98 + 0.036*cl 2.00 + 0.035*cl 2.01 + 0.035*cl t phl 3.90 2.31 + 0.032*cl 2.42 + 0.030*cl 2.47 + 0.030*cl t r 4.37 0.54 + 0.077*cl 0.48 + 0.077*cl 0.46 + 0.078*cl t f 3.74 0.96 + 0.056*cl 0.99 + 0.055*cl 0.98 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob16sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.54 2.19 + 0.027*cl 2.25 + 0.026*cl 2.28 + 0.026*cl t phl 3.60 2.35 + 0.025*cl 2.46 + 0.024*cl 2.52 + 0.023*cl t r 3.47 0.76 + 0.054*cl 0.73 + 0.055*cl 0.69 + 0.055*cl t f 3.00 0.96 + 0.041*cl 1.00 + 0.040*cl 1.04 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-39 STD80/stdm80 pvobyz normal output buffers stdm80 phob20sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.62 1.56 + 0.021*cl 1.61 + 0.020*cl 1.63 + 0.020*cl t phl 2.54 1.67 + 0.017*cl 1.71 + 0.017*cl 1.73 + 0.017*cl t r 2.73 0.60 + 0.043*cl 0.54 + 0.043*cl 0.56 + 0.043*cl t f 2.23 0.71 + 0.031*cl 0.71 + 0.030*cl 0.65 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob24sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.62 1.65 + 0.019*cl 1.71 + 0.019*cl 1.73 + 0.018*cl t phl 2.60 1.81 + 0.016*cl 1.85 + 0.015*cl 1.86 + 0.015*cl t r 2.54 0.67 + 0.037*cl 0.63 + 0.038*cl 0.65 + 0.038*cl t f 2.15 0.82 + 0.027*cl 0.78 + 0.027*cl 0.80 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob4sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 6.14 1.45 + 0.094*cl 1.44 + 0.094*cl 1.46 + 0.094*cl t phl 5.43 1.71 + 0.074*cl 1.72 + 0.074*cl 1.72 + 0.074*cl t r 10.84 0.25 + 0.212*cl 0.25 + 0.212*cl 0.24 + 0.212*cl t f 8.06 0.43 + 0.153*cl 0.39 + 0.153*cl 0.36 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob8sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.12 1.77 + 0.047*cl 1.78 + 0.047*cl 1.78 + 0.047*cl t phl 4.04 2.08 + 0.039*cl 2.14 + 0.038*cl 2.18 + 0.038*cl t r 5.60 0.38 + 0.104*cl 0.34 + 0.105*cl 0.32 + 0.105*cl t f 4.47 0.74 + 0.074*cl 0.73 + 0.075*cl 0.69 + 0.075*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-40 sec asic pvobyz normal output buffers stdm80 phob12sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.54 1.79 + 0.035*cl 1.81 + 0.035*cl 1.82 + 0.035*cl t phl 3.53 2.00 + 0.031*cl 2.09 + 0.030*cl 2.13 + 0.029*cl t r 4.25 0.46 + 0.076*cl 0.41 + 0.077*cl 0.40 + 0.077*cl t f 3.56 0.83 + 0.055*cl 0.81 + 0.055*cl 0.83 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob16sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.19 1.87 + 0.026*cl 1.92 + 0.026*cl 1.93 + 0.026*cl t phl 3.10 1.91 + 0.024*cl 2.01 + 0.022*cl 2.05 + 0.022*cl t r 3.32 0.59 + 0.055*cl 0.56 + 0.055*cl 0.53 + 0.055*cl t f 2.78 0.74 + 0.041*cl 0.77 + 0.040*cl 0.80 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob20sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.35 1.33 + 0.020*cl 1.36 + 0.020*cl 1.36 + 0.020*cl t phl 2.19 1.30 + 0.018*cl 1.35 + 0.017*cl 1.39 + 0.017*cl t r 2.54 0.39 + 0.043*cl 0.35 + 0.044*cl 0.33 + 0.044*cl t f 2.12 0.56 + 0.031*cl 0.57 + 0.031*cl 0.56 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phob24sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.33 1.42 + 0.018*cl 1.44 + 0.018*cl 1.47 + 0.018*cl t phl 2.21 1.38 + 0.017*cl 1.45 + 0.016*cl 1.48 + 0.015*cl t r 2.34 0.46 + 0.038*cl 0.44 + 0.038*cl 0.42 + 0.038*cl t f 2.02 0.65 + 0.028*cl 0.65 + 0.027*cl 0.66 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-41 STD80/stdm80 pvodyz open drain output buffers cell availability logic symbol notes: 1. STD80 standard open-drain output buffers, pod(1/2/4/8/12/16/20/24), cannot tolerate external pull-ups to more than 5.5v. and stdm80 standard open-drain output buffers, pod(1/2/4/6/8/10/12/16), cannot tolerate external pull-ups to more than 3.6v. 2. fail-safe open-drain output buffers with external pull-ups to more than 5.5 v (in case of STD80) / 3.6v (in case of stdm80) can drive signals to that voltage range. however, if you want to use fail-safe open-drains, please contact to sec asic ?rst. i/o slot library 5v operation 3.3v operation STD80 pod(1/2/4/8/12/16/20/24) pod(12/16/20/24)sh pod(4/8/12/16/20/24)sm plod(1/2/4/6/8/10/12/16) plod(4/6/8/10/12/16)sm stdm80 phod(1/2/4/8/12/16/20/24) phod(12/16/20/24)sh phod(4/8/12/16/20/24)sm pod(1/2/4/6/8/10/12/16) pod(4/6/8/10/12/16)sm STD80/stdm80 pvodyz 1.0 pa d tn en truth table input load (sl) tn en pad 100 0 x hi-z x 1 hi-z STD80 tn en pod(1/2/4/8/12/16/20/24) 1.4 1.6 pod(12/16/20/24)sh 1.4 1.6 pod(4/8/12/16/20/24)sm 1.4 1.6 plod(1/2/4/6/8/10/12/16) 1.2 1.2 plod(4/6/8/10/12/16)sm 1.2 1.2 stdm80 tn en pod(1/2/4/6/8/10/12/16) 1.8 1.8 pod(4/6/8/10/12/16)sm 1.8 1.8 phod(1/2/4/8/12/16/20/24) 1.4 1.4 phod(12/16/20/24)sh 1.4 1.4 phod(4/8/12/16/20/24)sm 1.4 1.4
STD80/stdm80 4-42 sec asic pvodyz open drain output buffers STD80 pod1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 12.21 0.56 + 0.233*cl 0.57 + 0.233*cl 0.56 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.39 + 0.485*cl t plz 0.50 0.50 + 0.000*cl 0.50 + 0.000*cl 0.50 + 0.000*cl en to pad t phl 12.36 0.72 + 0.233*cl 0.71 + 0.233*cl 0.73 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.39 + 0.485*cl t plz 0.41 0.41 + 0.000*cl 0.41 + 0.000*cl 0.41 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.29 0.47 + 0.116*cl 0.47 + 0.116*cl 0.47 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.20 + 0.243*cl 0.21 + 0.243*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl en to pad t phl 6.45 0.63 + 0.116*cl 0.63 + 0.116*cl 0.62 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.20 + 0.243*cl 0.21 + 0.243*cl t plz 0.44 0.44 + 0.000*cl 0.44 + 0.000*cl 0.44 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.19 0.48 + 0.074*cl 0.48 + 0.074*cl 0.47 + 0.074*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.54 0.54 + 0.000*cl 0.54 + 0.000*cl 0.54 + 0.000*cl en to pad t phl 4.34 0.63 + 0.074*cl 0.64 + 0.074*cl 0.63 + 0.074*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.45 0.45 + 0.000*cl 0.45 + 0.000*cl 0.45 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-43 STD80/stdm80 pvodyz open drain output buffers STD80 pod8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.38 0.53 + 0.037*cl 0.53 + 0.037*cl 0.53 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl en to pad t phl 2.54 0.69 + 0.037*cl 0.69 + 0.037*cl 0.69 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.54 0.54 + 0.000*cl 0.54 + 0.000*cl 0.54 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.95 0.58 + 0.027*cl 0.58 + 0.027*cl 0.58 + 0.027*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.10 + 0.057*cl t plz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.68 + 0.000*cl en to pad t phl 2.10 0.74 + 0.027*cl 0.74 + 0.027*cl 0.74 + 0.027*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.10 + 0.057*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.66 0.66 + 0.020*cl 0.66 + 0.020*cl 0.67 + 0.020*cl t f 2.19 0.15 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 0.76 0.76 + 0.000*cl 0.76 + 0.000*cl 0.76 + 0.000*cl en to pad t phl 1.82 0.82 + 0.020*cl 0.83 + 0.020*cl 0.82 + 0.020*cl t f 2.19 0.15 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.67 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-44 sec asic pvodyz open drain output buffers STD80 pod20 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.53 0.74 + 0.016*cl 0.74 + 0.016*cl 0.75 + 0.016*cl t f 1.79 0.20 + 0.032*cl 0.19 + 0.032*cl 0.17 + 0.032*cl t plz 0.85 0.84 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl en to pad t phl 1.69 0.89 + 0.016*cl 0.90 + 0.016*cl 0.90 + 0.016*cl t f 1.79 0.20 + 0.032*cl 0.19 + 0.032*cl 0.17 + 0.032*cl t plz 0.76 0.76 + 0.000*cl 0.76 + 0.000*cl 0.76 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod24 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.48 0.77 + 0.014*cl 0.79 + 0.014*cl 0.79 + 0.014*cl t f 1.62 0.23 + 0.028*cl 0.22 + 0.028*cl 0.21 + 0.028*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 1.64 0.93 + 0.014*cl 0.95 + 0.014*cl 0.95 + 0.014*cl t f 1.62 0.23 + 0.028*cl 0.22 + 0.028*cl 0.21 + 0.028*cl t plz 0.81 0.81 + 0.000*cl 0.82 + 0.000*cl 0.82 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod12sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.58 1.17 + 0.028*cl 1.19 + 0.028*cl 1.20 + 0.028*cl t f 3.19 0.41 + 0.056*cl 0.37 + 0.056*cl 0.35 + 0.056*cl t plz 0.52 0.52 + 0.000*cl 0.52 + 0.000*cl 0.52 + 0.000*cl en to pad t phl 2.74 1.33 + 0.028*cl 1.35 + 0.028*cl 1.35 + 0.028*cl t f 3.19 0.41 + 0.056*cl 0.37 + 0.056*cl 0.35 + 0.056*cl t plz 0.44 0.44 + 0.000*cl 0.44 + 0.000*cl 0.44 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-45 STD80/stdm80 pvodyz open drain output buffers STD80 pod16sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.45 1.36 + 0.022*cl 1.42 + 0.021*cl 1.44 + 0.021*cl t f 2.56 0.60 + 0.039*cl 0.57 + 0.040*cl 0.56 + 0.040*cl t plz 0.52 0.52 + 0.000*cl 0.52 + 0.000*cl 0.52 + 0.000*cl en to pad t phl 2.61 1.52 + 0.022*cl 1.57 + 0.021*cl 1.61 + 0.021*cl t f 2.56 0.60 + 0.039*cl 0.57 + 0.040*cl 0.56 + 0.040*cl t plz 0.44 0.44 + 0.000*cl 0.44 + 0.000*cl 0.44 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod20sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.27 1.34 + 0.019*cl 1.42 + 0.018*cl 1.45 + 0.017*cl t f 2.26 0.73 + 0.031*cl 0.73 + 0.031*cl 0.72 + 0.031*cl t plz 0.56 0.56 + 0.000*cl 0.56 + 0.000*cl 0.56 + 0.000*cl en to pad t phl 2.43 1.49 + 0.019*cl 1.57 + 0.018*cl 1.62 + 0.017*cl t f 2.26 0.73 + 0.031*cl 0.73 + 0.031*cl 0.72 + 0.031*cl t plz 0.47 0.47 + 0.000*cl 0.47 + 0.000*cl 0.47 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod24sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.29 1.40 + 0.018*cl 1.50 + 0.017*cl 1.54 + 0.016*cl t f 2.17 0.81 + 0.027*cl 0.82 + 0.027*cl 0.82 + 0.027*cl t plz 0.56 0.56 + 0.000*cl 0.56 + 0.000*cl 0.56 + 0.000*cl en to pad t phl 2.45 1.56 + 0.018*cl 1.66 + 0.016*cl 1.70 + 0.016*cl t f 2.17 0.81 + 0.027*cl 0.82 + 0.027*cl 0.82 + 0.027*cl t plz 0.47 0.47 + 0.000*cl 0.47 + 0.000*cl 0.47 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-46 sec asic pvodyz open drain output buffers STD80 pod4sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.43 0.71 + 0.074*cl 0.72 + 0.074*cl 0.71 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.57 0.57 + 0.000*cl 0.57 + 0.000*cl 0.57 + 0.000*cl en to pad t phl 4.58 0.87 + 0.074*cl 0.87 + 0.074*cl 0.87 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.49 0.49 + 0.000*cl 0.49 + 0.000*cl 0.49 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod8sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.87 1.01 + 0.037*cl 1.01 + 0.037*cl 1.02 + 0.037*cl t f 4.07 0.27 + 0.076*cl 0.24 + 0.076*cl 0.22 + 0.077*cl t plz 0.57 0.57 + 0.000*cl 0.57 + 0.000*cl 0.57 + 0.000*cl en to pad t phl 3.03 1.17 + 0.037*cl 1.17 + 0.037*cl 1.17 + 0.037*cl t f 4.07 0.27 + 0.076*cl 0.24 + 0.076*cl 0.22 + 0.077*cl t plz 0.49 0.49 + 0.000*cl 0.49 + 0.000*cl 0.49 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod12sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.38 1.00 + 0.028*cl 1.01 + 0.027*cl 1.03 + 0.027*cl t f 3.10 0.36 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.56 0.56 + 0.000*cl 0.56 + 0.000*cl 0.56 + 0.000*cl en to pad t phl 2.54 1.16 + 0.028*cl 1.17 + 0.027*cl 1.18 + 0.027*cl t f 3.10 0.36 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.48 0.48 + 0.000*cl 0.48 + 0.000*cl 0.48 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-47 STD80/stdm80 pvodyz open drain output buffers STD80 pod16sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.12 1.06 + 0.021*cl 1.10 + 0.021*cl 1.12 + 0.020*cl t f 2.47 0.51 + 0.039*cl 0.48 + 0.040*cl 0.46 + 0.040*cl t plz 0.59 0.59 + 0.000*cl 0.59 + 0.000*cl 0.59 + 0.000*cl en to pad t phl 2.27 1.21 + 0.021*cl 1.26 + 0.021*cl 1.28 + 0.020*cl t f 2.47 0.51 + 0.039*cl 0.48 + 0.040*cl 0.46 + 0.040*cl t plz 0.51 0.51 + 0.000*cl 0.51 + 0.000*cl 0.51 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod20sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.98 1.08 + 0.018*cl 1.15 + 0.017*cl 1.17 + 0.017*cl t f 2.15 0.62 + 0.031*cl 0.61 + 0.031*cl 0.60 + 0.031*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl en to pad t phl 2.14 1.24 + 0.018*cl 1.30 + 0.017*cl 1.34 + 0.017*cl t f 2.15 0.62 + 0.031*cl 0.61 + 0.031*cl 0.60 + 0.031*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pod24sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.00 1.14 + 0.017*cl 1.22 + 0.016*cl 1.27 + 0.016*cl t f 2.07 0.71 + 0.027*cl 0.73 + 0.027*cl 0.73 + 0.027*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl en to pad t phl 2.16 1.30 + 0.017*cl 1.38 + 0.016*cl 1.42 + 0.016*cl t f 2.07 0.71 + 0.027*cl 0.73 + 0.027*cl 0.73 + 0.027*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-48 sec asic pvodyz open drain output buffers STD80 plod1 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 14.09 0.89 + 0.264*cl 0.88 + 0.264*cl 0.88 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.80 0.80 + 0.000*cl 0.80 + 0.000*cl 0.80 + 0.000*cl en to pad t phl 14.20 1.00 + 0.264*cl 1.00 + 0.264*cl 1.00 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.73 0.73 + 0.000*cl 0.73 + 0.000*cl 0.73 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod2 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.97 0.79 + 0.124*cl 0.79 + 0.124*cl 0.80 + 0.123*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl en to pad t phl 7.08 0.91 + 0.123*cl 0.90 + 0.124*cl 0.90 + 0.124*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.78 0.78 + 0.000*cl 0.78 + 0.000*cl 0.78 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod4 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.92 0.83 + 0.062*cl 0.83 + 0.062*cl 0.82 + 0.062*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.16 + 0.133*cl t plz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t phl 4.03 0.94 + 0.062*cl 0.94 + 0.062*cl 0.94 + 0.062*cl t f 6.81 0.16 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-49 STD80/stdm80 pvodyz open drain output buffers STD80 plod6 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.96 0.90 + 0.041*cl 0.90 + 0.041*cl 0.91 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.13 + 0.089*cl 0.13 + 0.089*cl t plz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl en to pad t phl 3.07 1.01 + 0.041*cl 1.02 + 0.041*cl 1.01 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.12 + 0.089*cl 0.13 + 0.089*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod8 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.54 0.99 + 0.031*cl 0.99 + 0.031*cl 0.99 + 0.031*cl t f 3.48 0.18 + 0.066*cl 0.15 + 0.066*cl 0.16 + 0.066*cl t plz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl en to pad t phl 2.65 1.10 + 0.031*cl 1.10 + 0.031*cl 1.11 + 0.031*cl t f 3.47 0.18 + 0.066*cl 0.15 + 0.066*cl 0.13 + 0.066*cl t plz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod10 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.32 1.08 + 0.025*cl 1.08 + 0.025*cl 1.09 + 0.025*cl t f 2.84 0.24 + 0.052*cl 0.17 + 0.053*cl 0.19 + 0.053*cl t plz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl en to pad t phl 2.43 1.19 + 0.025*cl 1.20 + 0.025*cl 1.19 + 0.025*cl t f 2.84 0.23 + 0.052*cl 0.19 + 0.053*cl 0.19 + 0.053*cl t plz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-50 sec asic pvodyz open drain output buffers STD80 plod12 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.20 1.16 + 0.021*cl 1.17 + 0.021*cl 1.18 + 0.021*cl t f 2.43 0.28 + 0.043*cl 0.25 + 0.044*cl 0.26 + 0.043*cl t plz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl en to pad t phl 2.31 1.27 + 0.021*cl 1.28 + 0.021*cl 1.28 + 0.021*cl t f 2.44 0.28 + 0.043*cl 0.27 + 0.043*cl 0.26 + 0.043*cl t plz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod16 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.11 1.29 + 0.016*cl 1.32 + 0.016*cl 1.32 + 0.016*cl t f 1.99 0.37 + 0.032*cl 0.38 + 0.032*cl 0.34 + 0.033*cl t plz 1.31 1.31 + 0.000*cl 1.31 + 0.000*cl 1.31 + 0.000*cl en to pad t phl 2.22 1.40 + 0.016*cl 1.42 + 0.016*cl 1.44 + 0.016*cl t f 2.00 0.39 + 0.032*cl 0.37 + 0.032*cl 0.36 + 0.033*cl t plz 1.25 1.24 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod4sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.51 1.32 + 0.064*cl 1.32 + 0.064*cl 1.32 + 0.064*cl t f 7.11 0.28 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 4.62 1.43 + 0.064*cl 1.43 + 0.064*cl 1.43 + 0.064*cl t f 7.10 0.27 + 0.137*cl 0.24 + 0.137*cl 0.23 + 0.137*cl t plz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-51 STD80/stdm80 pvodyz open drain output buffers STD80 plod6sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.77 1.65 + 0.042*cl 1.66 + 0.042*cl 1.67 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.44 + 0.089*cl 0.39 + 0.089*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 3.88 1.76 + 0.042*cl 1.78 + 0.042*cl 1.79 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.42 + 0.089*cl 0.39 + 0.089*cl t plz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod8sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.56 1.92 + 0.033*cl 1.98 + 0.032*cl 1.99 + 0.032*cl t f 3.93 0.72 + 0.064*cl 0.65 + 0.065*cl 0.61 + 0.066*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 3.67 2.03 + 0.033*cl 2.09 + 0.032*cl 2.10 + 0.032*cl t f 3.93 0.72 + 0.064*cl 0.65 + 0.065*cl 0.62 + 0.066*cl t plz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod10sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.20 1.83 + 0.027*cl 1.92 + 0.026*cl 1.95 + 0.026*cl t f 3.38 0.91 + 0.049*cl 0.84 + 0.050*cl 0.82 + 0.050*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 3.31 1.94 + 0.027*cl 2.03 + 0.026*cl 2.07 + 0.026*cl t f 3.38 0.92 + 0.049*cl 0.88 + 0.050*cl 0.82 + 0.050*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-52 sec asic pvodyz open drain output buffers STD80 plod12sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.23 1.99 + 0.025*cl 2.10 + 0.023*cl 2.16 + 0.023*cl t f 3.15 1.12 + 0.041*cl 1.06 + 0.041*cl 1.08 + 0.041*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 3.34 2.10 + 0.025*cl 2.21 + 0.023*cl 2.28 + 0.023*cl t f 3.15 1.12 + 0.041*cl 1.11 + 0.041*cl 1.06 + 0.041*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plod16sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.38 2.23 + 0.023*cl 2.41 + 0.021*cl 2.48 + 0.020*cl t f 2.98 1.43 + 0.031*cl 1.44 + 0.031*cl 1.41 + 0.031*cl t plz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t phl 3.50 2.35 + 0.023*cl 2.51 + 0.021*cl 2.60 + 0.020*cl t f 2.99 1.45 + 0.031*cl 1.42 + 0.031*cl 1.42 + 0.031*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod1 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 13.96 0.76 + 0.264*cl 0.76 + 0.264*cl 0.76 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.64 0.64 + 0.000*cl 0.64 + 0.000*cl 0.64 + 0.000*cl en to pad t phl 14.16 0.96 + 0.264*cl 0.96 + 0.264*cl 0.96 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-53 STD80/stdm80 pvodyz open drain output buffers stdm80 pod2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.85 0.68 + 0.124*cl 0.67 + 0.124*cl 0.68 + 0.123*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.68 + 0.000*cl en to pad t phl 7.04 0.87 + 0.124*cl 0.87 + 0.123*cl 0.87 + 0.124*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.57 0.57 + 0.000*cl 0.57 + 0.000*cl 0.57 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.80 0.71 + 0.062*cl 0.71 + 0.062*cl 0.71 + 0.062*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.99 0.90 + 0.062*cl 0.90 + 0.062*cl 0.90 + 0.062*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl t plz 0.64 0.64 + 0.000*cl 0.64 + 0.000*cl 0.64 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.85 0.79 + 0.041*cl 0.79 + 0.041*cl 0.79 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.14 + 0.089*cl 0.13 + 0.089*cl t plz 0.82 0.82 + 0.000*cl 0.82 + 0.000*cl 0.82 + 0.000*cl en to pad t phl 3.04 0.98 + 0.041*cl 0.98 + 0.041*cl 0.98 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.13 + 0.089*cl 0.14 + 0.089*cl t plz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-54 sec asic pvodyz open drain output buffers stdm80 pod8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.40 0.86 + 0.031*cl 0.85 + 0.031*cl 0.86 + 0.031*cl t f 3.49 0.21 + 0.066*cl 0.18 + 0.066*cl 0.16 + 0.066*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl en to pad t phl 2.61 1.07 + 0.031*cl 1.06 + 0.031*cl 1.07 + 0.031*cl t f 3.47 0.18 + 0.066*cl 0.15 + 0.066*cl 0.15 + 0.066*cl t plz 0.78 0.78 + 0.000*cl 0.78 + 0.000*cl 0.78 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod10 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.18 0.95 + 0.025*cl 0.95 + 0.025*cl 0.95 + 0.025*cl t f 2.86 0.27 + 0.052*cl 0.22 + 0.052*cl 0.21 + 0.053*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl en to pad t phl 2.39 1.15 + 0.025*cl 1.16 + 0.025*cl 1.15 + 0.025*cl t f 2.84 0.24 + 0.052*cl 0.19 + 0.053*cl 0.20 + 0.053*cl t plz 0.85 0.84 + 0.000*cl 0.84 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod12 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.07 1.03 + 0.021*cl 1.03 + 0.021*cl 1.03 + 0.021*cl t f 2.46 0.33 + 0.043*cl 0.30 + 0.043*cl 0.25 + 0.044*cl t plz 1.02 1.02 + 0.000*cl 1.02 + 0.000*cl 1.02 + 0.000*cl en to pad t phl 2.27 1.23 + 0.021*cl 1.25 + 0.021*cl 1.25 + 0.021*cl t f 2.44 0.28 + 0.043*cl 0.25 + 0.044*cl 0.26 + 0.043*cl t plz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-55 STD80/stdm80 pvodyz open drain output buffers stdm80 pod16 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.98 1.16 + 0.016*cl 1.18 + 0.016*cl 1.20 + 0.016*cl t f 2.01 0.39 + 0.032*cl 0.39 + 0.032*cl 0.38 + 0.032*cl t plz 1.15 1.15 + 0.000*cl 1.15 + 0.000*cl 1.15 + 0.000*cl en to pad t phl 2.18 1.36 + 0.016*cl 1.40 + 0.016*cl 1.39 + 0.016*cl t f 2.00 0.39 + 0.032*cl 0.36 + 0.033*cl 0.34 + 0.033*cl t plz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod4sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.39 1.20 + 0.064*cl 1.20 + 0.064*cl 1.20 + 0.064*cl t f 7.11 0.28 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl t plz 0.70 0.70 + 0.000*cl 0.70 + 0.000*cl 0.70 + 0.000*cl en to pad t phl 4.58 1.39 + 0.064*cl 1.39 + 0.064*cl 1.39 + 0.064*cl t f 7.10 0.27 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod6sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.65 1.54 + 0.042*cl 1.55 + 0.042*cl 1.55 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.43 + 0.089*cl 0.39 + 0.089*cl t plz 0.70 0.70 + 0.000*cl 0.70 + 0.000*cl 0.70 + 0.000*cl en to pad t phl 3.85 1.73 + 0.042*cl 1.74 + 0.042*cl 1.74 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.43 + 0.089*cl 0.39 + 0.089*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-56 sec asic pvodyz open drain output buffers stdm80 pod8sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.44 1.80 + 0.033*cl 1.85 + 0.032*cl 1.88 + 0.032*cl t f 3.93 0.73 + 0.064*cl 0.64 + 0.065*cl 0.63 + 0.065*cl t plz 0.70 0.70 + 0.000*cl 0.70 + 0.000*cl 0.70 + 0.000*cl en to pad t phl 3.63 2.00 + 0.033*cl 2.04 + 0.032*cl 2.07 + 0.032*cl t f 3.93 0.72 + 0.064*cl 0.66 + 0.065*cl 0.62 + 0.065*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod10sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.08 1.72 + 0.027*cl 1.80 + 0.026*cl 1.84 + 0.026*cl t f 3.38 0.91 + 0.049*cl 0.86 + 0.050*cl 0.83 + 0.050*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.27 1.91 + 0.027*cl 1.99 + 0.026*cl 2.03 + 0.026*cl t f 3.38 0.92 + 0.049*cl 0.87 + 0.050*cl 0.83 + 0.050*cl t plz 0.65 0.65 + 0.000*cl 0.65 + 0.000*cl 0.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pod12sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.11 1.87 + 0.025*cl 1.99 + 0.023*cl 2.04 + 0.023*cl t f 3.15 1.13 + 0.040*cl 1.07 + 0.041*cl 1.07 + 0.041*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.30 2.06 + 0.025*cl 2.18 + 0.023*cl 2.24 + 0.023*cl t f 3.15 1.12 + 0.041*cl 1.09 + 0.041*cl 1.08 + 0.041*cl t plz 0.65 0.65 + 0.000*cl 0.65 + 0.000*cl 0.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-57 STD80/stdm80 pvodyz open drain output buffers stdm80 pod16sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.27 2.12 + 0.023*cl 2.28 + 0.021*cl 2.37 + 0.020*cl t f 2.98 1.43 + 0.031*cl 1.46 + 0.031*cl 1.43 + 0.031*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.46 2.31 + 0.023*cl 2.48 + 0.021*cl 2.56 + 0.020*cl t f 2.98 1.43 + 0.031*cl 1.45 + 0.031*cl 1.43 + 0.031*cl t plz 0.65 0.65 + 0.000*cl 0.65 + 0.000*cl 0.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod1 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 12.57 0.93 + 0.233*cl 0.93 + 0.233*cl 0.93 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl en to pad t phl 12.75 1.10 + 0.233*cl 1.10 + 0.233*cl 1.10 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.77 0.77 + 0.000*cl 0.77 + 0.000*cl 0.77 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod2 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.66 0.84 + 0.116*cl 0.84 + 0.116*cl 0.84 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 6.83 1.01 + 0.116*cl 1.01 + 0.116*cl 1.01 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl t plz 0.80 0.80 + 0.000*cl 0.80 + 0.000*cl 0.80 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-58 sec asic pvodyz open drain output buffers stdm80 phod4 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.56 0.85 + 0.074*cl 0.85 + 0.074*cl 0.85 + 0.074*cl t f 7.88 0.14 + 0.155*cl 0.14 + 0.155*cl 0.15 + 0.155*cl t plz 0.88 0.88 + 0.000*cl 0.88 + 0.000*cl 0.88 + 0.000*cl en to pad t phl 4.73 1.02 + 0.074*cl 1.02 + 0.074*cl 1.02 + 0.074*cl t f 7.88 0.15 + 0.155*cl 0.15 + 0.155*cl 0.15 + 0.155*cl t plz 0.80 0.80 + 0.000*cl 0.80 + 0.000*cl 0.80 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod8 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.76 0.90 + 0.037*cl 0.90 + 0.037*cl 0.90 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t phl 2.93 1.07 + 0.037*cl 1.07 + 0.037*cl 1.07 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod12 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.32 0.95 + 0.027*cl 0.96 + 0.027*cl 0.96 + 0.027*cl t f 2.93 0.11 + 0.056*cl 0.12 + 0.056*cl 0.09 + 0.057*cl t plz 1.03 1.03 + 0.000*cl 1.03 + 0.000*cl 1.03 + 0.000*cl en to pad t phl 2.49 1.13 + 0.027*cl 1.13 + 0.027*cl 1.13 + 0.027*cl t f 2.94 0.12 + 0.056*cl 0.09 + 0.057*cl 0.10 + 0.057*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-59 STD80/stdm80 pvodyz open drain output buffers stdm80 phod16 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.03 1.04 + 0.020*cl 1.03 + 0.020*cl 1.04 + 0.020*cl t f 2.20 0.15 + 0.041*cl 0.15 + 0.041*cl 0.15 + 0.041*cl t plz 1.11 1.11 + 0.000*cl 1.10 + 0.000*cl 1.11 + 0.000*cl en to pad t phl 2.21 1.21 + 0.020*cl 1.21 + 0.020*cl 1.20 + 0.020*cl t f 2.20 0.15 + 0.041*cl 0.16 + 0.041*cl 0.14 + 0.041*cl t plz 1.03 1.03 + 0.000*cl 1.03 + 0.000*cl 1.03 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod20 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.90 1.11 + 0.016*cl 1.12 + 0.016*cl 1.12 + 0.016*cl t f 1.80 0.23 + 0.031*cl 0.18 + 0.032*cl 0.18 + 0.032*cl t plz 1.19 1.19 + 0.000*cl 1.18 + 0.000*cl 1.19 + 0.000*cl en to pad t phl 2.08 1.28 + 0.016*cl 1.29 + 0.016*cl 1.29 + 0.016*cl t f 1.80 0.22 + 0.032*cl 0.19 + 0.032*cl 0.20 + 0.032*cl t plz 1.12 1.11 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod24 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.86 1.15 + 0.014*cl 1.16 + 0.014*cl 1.16 + 0.014*cl t f 1.63 0.24 + 0.028*cl 0.22 + 0.028*cl 0.22 + 0.028*cl t plz 1.24 1.24 + 0.000*cl 1.24 + 0.000*cl 1.24 + 0.000*cl en to pad t phl 2.03 1.32 + 0.014*cl 1.33 + 0.014*cl 1.34 + 0.014*cl t f 1.64 0.25 + 0.028*cl 0.23 + 0.028*cl 0.24 + 0.028*cl t plz 1.17 1.17 + 0.000*cl 1.17 + 0.000*cl 1.17 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-60 sec asic pvodyz open drain output buffers stdm80 phod12sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.95 1.54 + 0.028*cl 1.57 + 0.028*cl 1.57 + 0.028*cl t f 3.20 0.42 + 0.056*cl 0.37 + 0.056*cl 0.35 + 0.056*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 3.13 1.71 + 0.028*cl 1.74 + 0.028*cl 1.75 + 0.028*cl t f 3.20 0.42 + 0.056*cl 0.38 + 0.056*cl 0.34 + 0.057*cl t plz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod16sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.82 1.73 + 0.022*cl 1.79 + 0.021*cl 1.81 + 0.021*cl t f 2.57 0.61 + 0.039*cl 0.57 + 0.040*cl 0.57 + 0.040*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 2.99 1.90 + 0.022*cl 1.96 + 0.021*cl 1.99 + 0.021*cl t f 2.57 0.62 + 0.039*cl 0.57 + 0.040*cl 0.56 + 0.040*cl t plz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod20sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.64 1.70 + 0.019*cl 1.78 + 0.018*cl 1.83 + 0.017*cl t f 2.27 0.74 + 0.031*cl 0.76 + 0.030*cl 0.72 + 0.031*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 2.82 1.88 + 0.019*cl 1.95 + 0.018*cl 2.00 + 0.017*cl t f 2.27 0.75 + 0.030*cl 0.73 + 0.031*cl 0.74 + 0.031*cl t plz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-61 STD80/stdm80 pvodyz open drain output buffers stdm80 phod24sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.66 1.77 + 0.018*cl 1.87 + 0.017*cl 1.91 + 0.016*cl t f 2.18 0.82 + 0.027*cl 0.81 + 0.027*cl 0.84 + 0.027*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 2.83 1.94 + 0.018*cl 2.04 + 0.017*cl 2.08 + 0.016*cl t f 2.18 0.84 + 0.027*cl 0.84 + 0.027*cl 0.86 + 0.027*cl t plz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod4sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.80 1.08 + 0.074*cl 1.09 + 0.074*cl 1.08 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 4.97 1.26 + 0.074*cl 1.25 + 0.074*cl 1.26 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod8sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.24 1.38 + 0.037*cl 1.38 + 0.037*cl 1.39 + 0.037*cl t f 4.08 0.28 + 0.076*cl 0.25 + 0.076*cl 0.23 + 0.077*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 3.41 1.55 + 0.037*cl 1.56 + 0.037*cl 1.56 + 0.037*cl t f 4.08 0.28 + 0.076*cl 0.24 + 0.076*cl 0.23 + 0.077*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-62 sec asic pvodyz open drain output buffers stdm80 phod12sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.75 1.37 + 0.028*cl 1.39 + 0.027*cl 1.40 + 0.027*cl t f 3.11 0.37 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 2.92 1.54 + 0.028*cl 1.56 + 0.027*cl 1.57 + 0.027*cl t f 3.11 0.36 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod16sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.49 1.43 + 0.021*cl 1.47 + 0.021*cl 1.50 + 0.020*cl t f 2.48 0.52 + 0.039*cl 0.49 + 0.040*cl 0.46 + 0.040*cl t plz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl en to pad t phl 2.66 1.60 + 0.021*cl 1.65 + 0.021*cl 1.66 + 0.020*cl t f 2.48 0.52 + 0.039*cl 0.51 + 0.039*cl 0.47 + 0.040*cl t plz 0.86 0.86 + 0.000*cl 0.86 + 0.000*cl 0.86 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phod20sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.35 1.45 + 0.018*cl 1.52 + 0.017*cl 1.55 + 0.017*cl t f 2.16 0.62 + 0.031*cl 0.63 + 0.031*cl 0.61 + 0.031*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t phl 2.52 1.62 + 0.018*cl 1.69 + 0.017*cl 1.72 + 0.017*cl t f 2.16 0.64 + 0.031*cl 0.60 + 0.031*cl 0.61 + 0.031*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-63 STD80/stdm80 pvodyz open drain output buffers stdm80 phod24sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.37 1.51 + 0.017*cl 1.59 + 0.016*cl 1.63 + 0.016*cl t f 2.08 0.72 + 0.027*cl 0.74 + 0.027*cl 0.74 + 0.027*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t phl 2.54 1.68 + 0.017*cl 1.76 + 0.016*cl 1.81 + 0.016*cl t f 2.08 0.73 + 0.027*cl 0.72 + 0.027*cl 0.74 + 0.027*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-64 sec asic pvotyz tri-state output buffers cell availability logic symbol truth table i/o slot library 5v operation 3.3v operation STD80 pot(1/2/4/8/12/16/20/24) pot(12/16/20/24)sh pot(4/8/12/16/20/24)sm plot(1/2/4/6/8/10/12/16) plot(4/6/8/10/12/16)sm stdm80 phot(1/2/4/8/12/16/20/24) phot(12/16/20/24)sh phot(4/8/12/16/20/24)sm pot(1/2/4/6/8/10/12/16) pot(4/6/8/10/12/16)sm tn en a pad 1000 1011 x 1 x hi-z 0 x x hi-z STD80/stdm80 pvotyz 1.0 pa d a tn en input load (sl) STD80 tn en a pot(1/2/4/8/12/16/20/24) 1.4 1.6 2.4 pot(12/16/20/24)sh 1.4 1.6 2.4 pot(4/8/12/16/20/24)sm 1.4 1.6 2.4 plot(1/2/4/6/8/10/12/16) 1.2 1.2 2.3 plot(4/6/8/10/12/16)sm 1.2 1.2 2.3 stdm80 tn en a pot(1/2/4/6/8/10/12/16) 1.8 1.8 2.6 pot(4/6/8/10/12/16)sm 1.8 1.8 2.6 phot(1/2/4/8/12/16/20/24) 1.4 1.4 2.8 phot(12/16/20/24)sh 1.4 1.4 2.8 phot(4/8/12/16/20/24)sm 1.4 1.4 2.8
sec asic 4-65 STD80/stdm80 pvotyz tri-state output buffers STD80 pot1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 15.24 0.63 + 0.292*cl 0.63 + 0.292*cl 0.63 + 0.292*cl t phl 12.28 0.63 + 0.233*cl 0.63 + 0.233*cl 0.63 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.59 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl tn to pad t plh 15.23 0.73 + 0.290*cl 1.33 + 0.282*cl 2.49 + 0.268*cl t phl 12.30 0.65 + 0.233*cl 0.65 + 0.233*cl 0.65 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.63 0.63 + 0.000*cl 0.63 + 0.000*cl 0.63 + 0.000*cl t phz 0.58 0.58 + 0.000*cl 0.58 + 0.000*cl 0.58 + 0.000*cl en to pad t plh 15.39 0.88 + 0.290*cl 1.49 + 0.282*cl 2.68 + 0.268*cl t phl 12.45 0.81 + 0.233*cl 0.81 + 0.233*cl 0.81 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.55 0.55 + 0.000*cl 0.55 + 0.000*cl 0.55 + 0.000*cl t phz 0.50 0.50 + 0.000*cl 0.50 + 0.000*cl 0.50 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 7.86 0.56 + 0.146*cl 0.55 + 0.146*cl 0.56 + 0.146*cl t phl 6.37 0.55 + 0.116*cl 0.55 + 0.116*cl 0.55 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl tn to pad t plh 7.86 0.55 + 0.146*cl 0.54 + 0.146*cl 0.56 + 0.146*cl t phl 6.39 0.57 + 0.116*cl 0.57 + 0.116*cl 0.57 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl t plz 0.69 0.69 + 0.000*cl 0.69 + 0.000*cl 0.69 + 0.000*cl t phz 0.63 0.63 + 0.000*cl 0.63 + 0.000*cl 0.63 + 0.000*cl en to pad t plh 8.01 0.70 + 0.146*cl 0.71 + 0.146*cl 0.70 + 0.146*cl t phl 6.55 0.73 + 0.116*cl 0.72 + 0.117*cl 0.73 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl t plz 0.61 0.61 + 0.000*cl 0.61 + 0.000*cl 0.61 + 0.000*cl t phz 0.55 0.55 + 0.000*cl 0.55 + 0.000*cl 0.55 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-66 sec asic pvotyz tri-state output buffers STD80 pot4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.25 0.56 + 0.094*cl 0.56 + 0.094*cl 0.56 + 0.094*cl t phl 4.25 0.54 + 0.074*cl 0.54 + 0.074*cl 0.55 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl tn to pad t plh 5.24 0.55 + 0.094*cl 0.55 + 0.094*cl 0.55 + 0.094*cl t phl 4.27 0.56 + 0.074*cl 0.56 + 0.074*cl 0.57 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl t phz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.68 + 0.000*cl en to pad t plh 5.39 0.70 + 0.094*cl 0.70 + 0.094*cl 0.70 + 0.094*cl t phl 4.43 0.72 + 0.074*cl 0.71 + 0.074*cl 0.72 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.67 0.67 + 0.000*cl 0.67 + 0.000*cl 0.67 + 0.000*cl t phz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.96 0.62 + 0.047*cl 0.62 + 0.047*cl 0.62 + 0.047*cl t phl 2.45 0.60 + 0.037*cl 0.60 + 0.037*cl 0.60 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl tn to pad t plh 2.95 0.61 + 0.047*cl 0.61 + 0.047*cl 0.61 + 0.047*cl t phl 2.47 0.62 + 0.037*cl 0.61 + 0.037*cl 0.62 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl t phz 0.82 0.82 + 0.000*cl 0.82 + 0.000*cl 0.82 + 0.000*cl en to pad t plh 3.11 0.76 + 0.047*cl 0.76 + 0.047*cl 0.76 + 0.047*cl t phl 2.63 0.77 + 0.037*cl 0.77 + 0.037*cl 0.77 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.84 0.84 + 0.000*cl 0.83 + 0.000*cl 0.84 + 0.000*cl t phz 0.74 0.74 + 0.000*cl 0.74 + 0.000*cl 0.74 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-67 STD80/stdm80 pvotyz tri-state output buffers STD80 pot12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.41 0.68 + 0.035*cl 0.68 + 0.035*cl 0.68 + 0.035*cl t phl 2.02 0.66 + 0.027*cl 0.66 + 0.027*cl 0.66 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl tn to pad t plh 2.39 0.66 + 0.035*cl 0.67 + 0.035*cl 0.66 + 0.035*cl t phl 2.03 0.67 + 0.027*cl 0.67 + 0.027*cl 0.67 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl t plz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl t phz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl en to pad t plh 2.54 0.82 + 0.035*cl 0.81 + 0.035*cl 0.82 + 0.035*cl t phl 2.19 0.82 + 0.027*cl 0.83 + 0.027*cl 0.83 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl t phz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.84 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 0.78 + 0.025*cl 0.77 + 0.025*cl 0.77 + 0.025*cl t phl 1.74 0.75 + 0.020*cl 0.74 + 0.020*cl 0.74 + 0.020*cl t r 2.97 0.13 + 0.057*cl 0.13 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl tn to pad t plh 2.01 0.75 + 0.025*cl 0.74 + 0.025*cl 0.75 + 0.025*cl t phl 1.75 0.75 + 0.020*cl 0.75 + 0.020*cl 0.75 + 0.020*cl t r 2.97 0.14 + 0.057*cl 0.12 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 1.20 1.20 + 0.000*cl 1.20 + 0.000*cl 1.20 + 0.000*cl t phz 1.07 1.07 + 0.000*cl 1.07 + 0.000*cl 1.07 + 0.000*cl en to pad t plh 2.16 0.90 + 0.025*cl 0.91 + 0.025*cl 0.90 + 0.025*cl t phl 1.90 0.91 + 0.020*cl 0.90 + 0.020*cl 0.91 + 0.020*cl t r 2.97 0.14 + 0.057*cl 0.13 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 1.12 1.12 + 0.000*cl 1.11 + 0.000*cl 1.12 + 0.000*cl t phz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-68 sec asic pvotyz tri-state output buffers STD80 pot20 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.66 0.67 + 0.020*cl 0.67 + 0.020*cl 0.66 + 0.020*cl t phl 1.51 0.72 + 0.016*cl 0.73 + 0.016*cl 0.72 + 0.016*cl t r 2.33 0.09 + 0.045*cl 0.09 + 0.045*cl 0.08 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.11 + 0.032*cl 0.11 + 0.032*cl tn to pad t plh 1.65 0.65 + 0.020*cl 0.65 + 0.020*cl 0.65 + 0.020*cl t phl 1.52 0.73 + 0.016*cl 0.74 + 0.016*cl 0.73 + 0.016*cl t r 2.33 0.10 + 0.045*cl 0.09 + 0.045*cl 0.08 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.12 + 0.032*cl 0.11 + 0.032*cl t plz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl t phz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl en to pad t plh 1.80 0.81 + 0.020*cl 0.81 + 0.020*cl 0.81 + 0.020*cl t phl 1.67 0.88 + 0.016*cl 0.89 + 0.016*cl 0.89 + 0.016*cl t r 2.33 0.10 + 0.045*cl 0.09 + 0.045*cl 0.08 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.12 + 0.032*cl 0.11 + 0.032*cl t plz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot24 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.59 0.72 + 0.017*cl 0.72 + 0.018*cl 0.72 + 0.018*cl t phl 1.45 0.75 + 0.014*cl 0.76 + 0.014*cl 0.75 + 0.014*cl t r 2.07 0.11 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.13 + 0.028*cl 0.13 + 0.028*cl tn to pad t plh 1.58 0.70 + 0.018*cl 0.71 + 0.017*cl 0.70 + 0.018*cl t phl 1.46 0.76 + 0.014*cl 0.77 + 0.014*cl 0.77 + 0.014*cl t r 2.07 0.11 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.14 + 0.028*cl 0.13 + 0.028*cl t plz 1.07 1.07 + 0.000*cl 1.06 + 0.000*cl 1.07 + 0.000*cl t phz 0.97 0.97 + 0.000*cl 0.97 + 0.000*cl 0.96 + 0.000*cl en to pad t plh 1.73 0.86 + 0.018*cl 0.86 + 0.018*cl 0.86 + 0.018*cl t phl 1.62 0.92 + 0.014*cl 0.92 + 0.014*cl 0.93 + 0.014*cl t r 2.07 0.11 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.14 + 0.028*cl 0.13 + 0.028*cl t plz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-69 STD80/stdm80 pvotyz tri-state output buffers STD80 pot12sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.17 1.39 + 0.036*cl 1.41 + 0.035*cl 1.42 + 0.035*cl t phl 3.66 2.06 + 0.032*cl 2.17 + 0.030*cl 2.23 + 0.030*cl t r 4.34 0.49 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.73 0.96 + 0.055*cl 0.97 + 0.055*cl 0.98 + 0.055*cl tn to pad t plh 3.12 1.34 + 0.036*cl 1.37 + 0.035*cl 1.37 + 0.035*cl t phl 3.67 2.07 + 0.032*cl 2.18 + 0.031*cl 2.24 + 0.030*cl t r 4.34 0.49 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.74 0.98 + 0.055*cl 0.98 + 0.055*cl 0.98 + 0.055*cl t plz 1.30 1.30 + 0.000*cl 1.30 + 0.000*cl 1.30 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 3.28 1.50 + 0.036*cl 1.53 + 0.035*cl 1.53 + 0.035*cl t phl 3.82 2.22 + 0.032*cl 2.34 + 0.031*cl 2.39 + 0.030*cl t r 4.34 0.49 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.74 0.98 + 0.055*cl 0.98 + 0.055*cl 0.98 + 0.055*cl t plz 1.22 1.22 + 0.000*cl 1.22 + 0.000*cl 1.22 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot16sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.97 1.61 + 0.027*cl 1.68 + 0.026*cl 1.70 + 0.026*cl t phl 3.36 2.11 + 0.025*cl 2.21 + 0.024*cl 2.28 + 0.023*cl t r 3.43 0.70 + 0.055*cl 0.68 + 0.055*cl 0.66 + 0.055*cl t f 3.00 0.95 + 0.041*cl 1.01 + 0.040*cl 1.02 + 0.040*cl tn to pad t plh 2.92 1.56 + 0.027*cl 1.63 + 0.026*cl 1.65 + 0.026*cl t phl 3.35 2.07 + 0.025*cl 2.21 + 0.024*cl 2.26 + 0.023*cl t r 3.43 0.71 + 0.055*cl 0.68 + 0.055*cl 0.66 + 0.055*cl t f 3.03 1.01 + 0.040*cl 1.05 + 0.040*cl 1.06 + 0.040*cl t plz 1.27 1.27 + 0.000*cl 1.27 + 0.000*cl 1.27 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 3.07 1.72 + 0.027*cl 1.78 + 0.026*cl 1.80 + 0.026*cl t phl 3.50 2.23 + 0.025*cl 2.36 + 0.024*cl 2.42 + 0.023*cl t r 3.43 0.71 + 0.055*cl 0.68 + 0.055*cl 0.66 + 0.055*cl t f 3.03 1.01 + 0.040*cl 1.05 + 0.040*cl 1.06 + 0.040*cl t plz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-70 sec asic pvotyz tri-state output buffers STD80 pot20sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.36 1.30 + 0.021*cl 1.35 + 0.021*cl 1.36 + 0.020*cl t phl 2.38 1.52 + 0.017*cl 1.55 + 0.017*cl 1.57 + 0.017*cl t r 2.71 0.57 + 0.043*cl 0.55 + 0.043*cl 0.53 + 0.043*cl t f 2.23 0.71 + 0.030*cl 0.69 + 0.031*cl 0.68 + 0.031*cl tn to pad t plh 2.31 1.25 + 0.021*cl 1.29 + 0.021*cl 1.32 + 0.020*cl t phl 2.29 1.35 + 0.019*cl 1.43 + 0.018*cl 1.47 + 0.017*cl t r 2.72 0.59 + 0.043*cl 0.55 + 0.043*cl 0.54 + 0.043*cl t f 2.22 0.67 + 0.031*cl 0.68 + 0.031*cl 0.67 + 0.031*cl t plz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl t phz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t plh 2.47 1.41 + 0.021*cl 1.46 + 0.021*cl 1.47 + 0.020*cl t phl 2.44 1.51 + 0.019*cl 1.58 + 0.018*cl 1.63 + 0.017*cl t r 2.72 0.59 + 0.043*cl 0.55 + 0.043*cl 0.54 + 0.043*cl t f 2.22 0.67 + 0.031*cl 0.68 + 0.031*cl 0.67 + 0.031*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl t phz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot24sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.35 1.38 + 0.019*cl 1.44 + 0.019*cl 1.47 + 0.018*cl t phl 2.45 1.66 + 0.016*cl 1.69 + 0.015*cl 1.72 + 0.015*cl t r 2.53 0.65 + 0.038*cl 0.64 + 0.038*cl 0.63 + 0.038*cl t f 2.15 0.82 + 0.027*cl 0.81 + 0.027*cl 0.79 + 0.027*cl tn to pad t plh 2.30 1.33 + 0.020*cl 1.39 + 0.019*cl 1.42 + 0.018*cl t phl 2.30 1.42 + 0.018*cl 1.52 + 0.016*cl 1.55 + 0.016*cl t r 2.55 0.68 + 0.037*cl 0.66 + 0.038*cl 0.64 + 0.038*cl t f 2.12 0.74 + 0.028*cl 0.77 + 0.027*cl 0.76 + 0.027*cl t plz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.70 + 0.000*cl t phz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t plh 2.46 1.48 + 0.020*cl 1.54 + 0.019*cl 1.58 + 0.018*cl t phl 2.46 1.57 + 0.018*cl 1.67 + 0.016*cl 1.71 + 0.016*cl t r 2.55 0.68 + 0.037*cl 0.66 + 0.037*cl 0.64 + 0.038*cl t f 2.12 0.74 + 0.028*cl 0.77 + 0.027*cl 0.76 + 0.027*cl t plz 0.62 0.62 + 0.000*cl 0.63 + 0.000*cl 0.63 + 0.000*cl t phz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-71 STD80/stdm80 pvotyz tri-state output buffers STD80 pot4sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.59 0.90 + 0.094*cl 0.90 + 0.094*cl 0.90 + 0.094*cl t phl 5.18 1.45 + 0.074*cl 1.46 + 0.074*cl 1.47 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.24 + 0.212*cl 0.23 + 0.212*cl t f 8.06 0.42 + 0.153*cl 0.38 + 0.153*cl 0.35 + 0.154*cl tn to pad t plh 5.55 0.85 + 0.094*cl 0.86 + 0.094*cl 0.86 + 0.094*cl t phl 5.19 1.47 + 0.074*cl 1.48 + 0.074*cl 1.49 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.24 + 0.212*cl 0.23 + 0.212*cl t f 8.06 0.42 + 0.153*cl 0.38 + 0.153*cl 0.35 + 0.154*cl t plz 1.33 1.33 + 0.000*cl 1.33 + 0.000*cl 1.33 + 0.000*cl t phz 1.10 1.10 + 0.000*cl 1.10 + 0.000*cl 1.10 + 0.000*cl en to pad t plh 5.70 1.01 + 0.094*cl 1.01 + 0.094*cl 1.01 + 0.094*cl t phl 5.35 1.63 + 0.074*cl 1.64 + 0.074*cl 1.64 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.24 + 0.212*cl 0.23 + 0.212*cl t f 8.06 0.42 + 0.153*cl 0.38 + 0.153*cl 0.35 + 0.154*cl t plz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot8sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.55 1.20 + 0.047*cl 1.20 + 0.047*cl 1.21 + 0.047*cl t phl 3.79 1.83 + 0.039*cl 1.89 + 0.038*cl 1.93 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.31 + 0.105*cl 0.28 + 0.105*cl t f 4.46 0.74 + 0.074*cl 0.72 + 0.075*cl 0.69 + 0.075*cl tn to pad t plh 3.51 1.16 + 0.047*cl 1.16 + 0.047*cl 1.16 + 0.047*cl t phl 3.80 1.84 + 0.039*cl 1.91 + 0.038*cl 1.94 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.31 + 0.105*cl 0.28 + 0.105*cl t f 4.47 0.74 + 0.074*cl 0.72 + 0.075*cl 0.70 + 0.075*cl t plz 1.30 1.30 + 0.000*cl 1.30 + 0.000*cl 1.30 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 3.66 1.31 + 0.047*cl 1.31 + 0.047*cl 1.32 + 0.047*cl t phl 3.96 1.99 + 0.039*cl 2.07 + 0.038*cl 2.10 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.31 + 0.105*cl 0.28 + 0.105*cl t f 4.47 0.74 + 0.074*cl 0.72 + 0.075*cl 0.70 + 0.075*cl t plz 1.22 1.22 + 0.000*cl 1.22 + 0.000*cl 1.22 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-72 sec asic pvotyz tri-state output buffers STD80 pot12sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.98 1.24 + 0.035*cl 1.25 + 0.035*cl 1.26 + 0.035*cl t phl 3.29 1.75 + 0.031*cl 1.85 + 0.029*cl 1.89 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.35 + 0.077*cl t f 3.55 0.81 + 0.055*cl 0.82 + 0.055*cl 0.82 + 0.055*cl tn to pad t plh 2.93 1.19 + 0.035*cl 1.20 + 0.035*cl 1.21 + 0.035*cl t phl 3.30 1.76 + 0.031*cl 1.86 + 0.030*cl 1.91 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.36 + 0.077*cl t f 3.55 0.82 + 0.055*cl 0.83 + 0.055*cl 0.82 + 0.055*cl t plz 1.54 1.54 + 0.000*cl 1.54 + 0.000*cl 1.54 + 0.000*cl t phz 1.39 1.39 + 0.000*cl 1.39 + 0.000*cl 1.38 + 0.000*cl en to pad t plh 3.09 1.34 + 0.035*cl 1.36 + 0.035*cl 1.36 + 0.035*cl t phl 3.46 1.92 + 0.031*cl 2.02 + 0.030*cl 2.06 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.36 + 0.077*cl t f 3.55 0.82 + 0.055*cl 0.83 + 0.055*cl 0.82 + 0.055*cl t plz 1.46 1.45 + 0.000*cl 1.45 + 0.000*cl 1.45 + 0.000*cl t phz 1.31 1.30 + 0.000*cl 1.31 + 0.000*cl 1.31 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot16sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.66 1.34 + 0.026*cl 1.38 + 0.026*cl 1.40 + 0.026*cl t phl 2.86 1.68 + 0.024*cl 1.76 + 0.022*cl 1.81 + 0.022*cl t r 3.28 0.53 + 0.055*cl 0.51 + 0.055*cl 0.49 + 0.056*cl t f 2.77 0.73 + 0.041*cl 0.77 + 0.040*cl 0.78 + 0.040*cl tn to pad t plh 2.61 1.29 + 0.026*cl 1.33 + 0.026*cl 1.34 + 0.026*cl t phl 2.86 1.66 + 0.024*cl 1.76 + 0.023*cl 1.80 + 0.022*cl t r 3.29 0.54 + 0.055*cl 0.51 + 0.055*cl 0.49 + 0.056*cl t f 2.79 0.76 + 0.040*cl 0.79 + 0.040*cl 0.80 + 0.040*cl t plz 1.72 1.72 + 0.000*cl 1.71 + 0.000*cl 1.72 + 0.000*cl t phz 1.65 1.65 + 0.000*cl 1.64 + 0.000*cl 1.65 + 0.000*cl en to pad t plh 2.76 1.44 + 0.026*cl 1.49 + 0.026*cl 1.50 + 0.026*cl t phl 3.02 1.82 + 0.024*cl 1.91 + 0.023*cl 1.97 + 0.022*cl t r 3.29 0.54 + 0.055*cl 0.51 + 0.055*cl 0.49 + 0.056*cl t f 2.79 0.76 + 0.040*cl 0.79 + 0.040*cl 0.80 + 0.040*cl t plz 1.64 1.64 + 0.000*cl 1.64 + 0.000*cl 1.63 + 0.000*cl t phz 1.57 1.57 + 0.000*cl 1.57 + 0.000*cl 1.56 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-73 STD80/stdm80 pvotyz tri-state output buffers STD80 pot20sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 1.02 + 0.020*cl 1.04 + 0.020*cl 1.04 + 0.020*cl t phl 2.01 1.13 + 0.018*cl 1.18 + 0.017*cl 1.21 + 0.017*cl t r 2.53 0.36 + 0.043*cl 0.33 + 0.044*cl 0.32 + 0.044*cl t f 2.11 0.54 + 0.031*cl 0.55 + 0.031*cl 0.54 + 0.031*cl tn to pad t plh 2.00 0.99 + 0.020*cl 1.01 + 0.020*cl 1.01 + 0.020*cl t phl 2.01 1.11 + 0.018*cl 1.17 + 0.017*cl 1.21 + 0.017*cl t r 2.53 0.37 + 0.043*cl 0.34 + 0.044*cl 0.32 + 0.044*cl t f 2.12 0.57 + 0.031*cl 0.57 + 0.031*cl 0.57 + 0.031*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.78 + 0.000*cl en to pad t plh 2.16 1.14 + 0.020*cl 1.16 + 0.020*cl 1.17 + 0.020*cl t phl 2.17 1.27 + 0.018*cl 1.33 + 0.017*cl 1.37 + 0.017*cl t r 2.53 0.37 + 0.043*cl 0.34 + 0.044*cl 0.32 + 0.044*cl t f 2.12 0.57 + 0.031*cl 0.57 + 0.031*cl 0.57 + 0.031*cl t plz 0.79 0.79 + 0.000*cl 0.78 + 0.000*cl 0.79 + 0.000*cl t phz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 pot24sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.01 1.10 + 0.018*cl 1.12 + 0.018*cl 1.14 + 0.018*cl t phl 2.04 1.21 + 0.017*cl 1.27 + 0.016*cl 1.31 + 0.015*cl t r 2.33 0.44 + 0.038*cl 0.42 + 0.038*cl 0.40 + 0.038*cl t f 2.01 0.62 + 0.028*cl 0.64 + 0.028*cl 0.64 + 0.027*cl tn to pad t plh 1.98 1.06 + 0.018*cl 1.10 + 0.018*cl 1.10 + 0.018*cl t phl 2.03 1.17 + 0.017*cl 1.25 + 0.016*cl 1.29 + 0.016*cl t r 2.34 0.46 + 0.038*cl 0.43 + 0.038*cl 0.41 + 0.038*cl t f 2.04 0.66 + 0.027*cl 0.67 + 0.027*cl 0.68 + 0.027*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl en to pad t plh 2.13 1.21 + 0.018*cl 1.25 + 0.018*cl 1.26 + 0.018*cl t phl 2.18 1.33 + 0.017*cl 1.41 + 0.016*cl 1.45 + 0.016*cl t r 2.34 0.46 + 0.038*cl 0.43 + 0.038*cl 0.41 + 0.038*cl t f 2.04 0.66 + 0.027*cl 0.67 + 0.027*cl 0.68 + 0.027*cl t plz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl t phz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-74 sec asic pvotyz tri-state output buffers STD80 plot1 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 21.62 1.17 + 0.409*cl 1.17 + 0.409*cl 1.17 + 0.409*cl t phl 14.16 0.96 + 0.264*cl 0.96 + 0.264*cl 0.96 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl tn to pad t plh 21.41 1.49 + 0.398*cl 3.49 + 0.372*cl 6.57 + 0.335*cl t phl 14.16 0.96 + 0.264*cl 0.96 + 0.264*cl 0.96 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl t phz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl en to pad t plh 21.52 1.61 + 0.398*cl 3.63 + 0.371*cl 6.73 + 0.335*cl t phl 14.29 1.09 + 0.264*cl 1.08 + 0.264*cl 1.08 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.98 0.93 + 0.001*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plot2 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.70 1.05 + 0.193*cl 1.05 + 0.193*cl 1.05 + 0.193*cl t phl 7.04 0.87 + 0.124*cl 0.87 + 0.124*cl 0.87 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl tn to pad t plh 10.50 0.85 + 0.193*cl 0.85 + 0.193*cl 0.87 + 0.193*cl t phl 7.05 0.87 + 0.124*cl 0.87 + 0.124*cl 0.87 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 1.13 1.13 + 0.000*cl 1.13 + 0.000*cl 1.13 + 0.000*cl t phz 1.06 1.06 + 0.000*cl 1.05 + 0.000*cl 1.06 + 0.000*cl en to pad t plh 10.63 1.02 + 0.192*cl 0.84 + 0.195*cl 1.10 + 0.192*cl t phl 7.17 1.00 + 0.124*cl 1.00 + 0.124*cl 0.99 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl t phz 1.02 1.05 + -0.001*cl 0.88 + 0.002*cl 1.02 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-75 STD80/stdm80 pvotyz tri-state output buffers STD80 plot4 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.81 0.98 + 0.096*cl 0.98 + 0.097*cl 0.98 + 0.096*cl t phl 4.00 0.92 + 0.062*cl 0.91 + 0.062*cl 0.91 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl tn to pad t plh 5.60 0.78 + 0.096*cl 0.78 + 0.096*cl 0.78 + 0.096*cl t phl 4.00 0.92 + 0.062*cl 0.91 + 0.062*cl 0.92 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl t plz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl t phz 1.70 1.70 + 0.000*cl 1.70 + 0.000*cl 1.70 + 0.000*cl en to pad t plh 5.72 0.90 + 0.096*cl 0.90 + 0.097*cl 0.90 + 0.096*cl t phl 4.14 1.06 + 0.062*cl 1.05 + 0.062*cl 1.06 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.14 + 0.133*cl 0.16 + 0.133*cl t plz 1.19 1.19 + 0.000*cl 1.14 + 0.001*cl 1.19 + 0.000*cl t phz 1.65 1.65 + 0.000*cl 1.72 + -0.001*cl 1.64 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plot6 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.26 1.04 + 0.064*cl 1.04 + 0.064*cl 1.05 + 0.064*cl t phl 3.07 1.02 + 0.041*cl 1.01 + 0.041*cl 1.01 + 0.041*cl t r 7.52 0.20 + 0.146*cl 0.19 + 0.146*cl 0.20 + 0.146*cl t f 4.58 0.17 + 0.088*cl 0.14 + 0.089*cl 0.14 + 0.089*cl tn to pad t plh 4.05 0.84 + 0.064*cl 0.82 + 0.064*cl 0.85 + 0.064*cl t phl 3.05 0.99 + 0.041*cl 0.99 + 0.041*cl 0.99 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.19 + 0.146*cl 0.20 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.12 + 0.089*cl 0.13 + 0.089*cl t plz 1.40 1.40 + 0.000*cl 1.54 + -0.002*cl 1.38 + 0.000*cl t phz 2.09 2.09 + 0.000*cl 2.09 + 0.000*cl 2.09 + 0.000*cl en to pad t plh 4.17 0.95 + 0.064*cl 0.94 + 0.064*cl 0.96 + 0.064*cl t phl 3.19 1.13 + 0.041*cl 1.13 + 0.041*cl 1.14 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.14 + 0.089*cl 0.12 + 0.089*cl t plz 1.35 1.41 + -0.001*cl 1.32 + 0.000*cl 1.32 + 0.000*cl t phz 2.02 2.02 + 0.000*cl 2.02 + 0.000*cl 2.02 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-76 sec asic pvotyz tri-state output buffers STD80 plot8 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.52 1.11 + 0.048*cl 1.11 + 0.048*cl 1.11 + 0.048*cl t phl 2.67 1.15 + 0.030*cl 1.14 + 0.031*cl 1.13 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.16 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.24 + 0.065*cl 0.20 + 0.066*cl 0.18 + 0.066*cl tn to pad t plh 3.32 0.90 + 0.048*cl 0.89 + 0.048*cl 0.92 + 0.048*cl t phl 2.62 1.08 + 0.031*cl 1.08 + 0.031*cl 1.08 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.17 + 0.110*cl 0.16 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.15 + 0.066*cl 0.14 + 0.066*cl t plz 1.51 1.47 + 0.001*cl 1.68 + -0.002*cl 1.40 + 0.001*cl t phz 2.48 2.47 + 0.000*cl 2.48 + 0.000*cl 2.48 + 0.000*cl en to pad t plh 3.45 1.07 + 0.048*cl 0.89 + 0.050*cl 1.14 + 0.047*cl t phl 2.77 1.22 + 0.031*cl 1.22 + 0.031*cl 1.22 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.14 + 0.066*cl 0.15 + 0.066*cl t plz 1.45 1.45 + 0.000*cl 1.44 + 0.000*cl 1.31 + 0.002*cl t phz 2.41 2.41 + 0.000*cl 2.41 + 0.000*cl 2.40 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plot10 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.16 1.23 + 0.039*cl 1.23 + 0.039*cl 1.23 + 0.039*cl t phl 2.41 1.18 + 0.025*cl 1.17 + 0.025*cl 1.18 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.21 + 0.052*cl 0.17 + 0.053*cl 0.20 + 0.053*cl tn to pad t plh 2.95 1.01 + 0.039*cl 1.02 + 0.039*cl 0.99 + 0.039*cl t phl 2.40 1.16 + 0.025*cl 1.18 + 0.025*cl 1.17 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.84 0.23 + 0.052*cl 0.18 + 0.053*cl 0.20 + 0.053*cl t plz 1.65 1.68 + -0.001*cl 1.55 + 0.001*cl 1.72 + -0.001*cl t phz 1.88 1.88 + 0.000*cl 1.88 + 0.000*cl 1.88 + 0.000*cl en to pad t plh 3.07 1.13 + 0.039*cl 1.14 + 0.039*cl 1.13 + 0.039*cl t phl 2.55 1.31 + 0.025*cl 1.30 + 0.025*cl 1.31 + 0.025*cl t r 4.56 0.19 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.21 + 0.052*cl 0.21 + 0.052*cl 0.17 + 0.053*cl t plz 1.57 1.53 + 0.001*cl 1.77 + -0.002*cl 1.57 + 0.000*cl t phz 1.82 1.82 + 0.000*cl 1.82 + 0.000*cl 1.82 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-77 STD80/stdm80 pvotyz tri-state output buffers STD80 plot12 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.95 1.34 + 0.032*cl 1.34 + 0.032*cl 1.34 + 0.032*cl t phl 2.28 1.24 + 0.021*cl 1.25 + 0.021*cl 1.25 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.20 + 0.073*cl 0.16 + 0.073*cl t f 2.43 0.26 + 0.043*cl 0.26 + 0.043*cl 0.22 + 0.044*cl tn to pad t plh 2.74 1.12 + 0.032*cl 1.13 + 0.032*cl 1.14 + 0.032*cl t phl 2.28 1.24 + 0.021*cl 1.26 + 0.021*cl 1.26 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.27 + 0.043*cl 0.25 + 0.043*cl 0.24 + 0.044*cl t plz 1.76 1.74 + 0.000*cl 1.77 + 0.000*cl 1.76 + 0.000*cl t phz 1.69 1.69 + 0.000*cl 1.69 + 0.000*cl 1.69 + 0.000*cl en to pad t plh 2.86 1.25 + 0.032*cl 1.13 + 0.034*cl 1.36 + 0.031*cl t phl 2.40 1.37 + 0.021*cl 1.37 + 0.021*cl 1.37 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.19 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.26 + 0.043*cl 0.26 + 0.043*cl 0.22 + 0.044*cl t plz 1.73 1.72 + 0.000*cl 1.72 + 0.000*cl 1.85 + -0.002*cl t phz 1.63 1.63 + 0.000*cl 1.63 + 0.000*cl 1.63 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plot16 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.71 1.49 + 0.024*cl 1.49 + 0.024*cl 1.49 + 0.024*cl t phl 2.20 1.38 + 0.016*cl 1.40 + 0.016*cl 1.41 + 0.016*cl t r 3.00 0.26 + 0.055*cl 0.24 + 0.055*cl 0.23 + 0.055*cl t f 1.98 0.36 + 0.032*cl 0.38 + 0.032*cl 0.31 + 0.033*cl tn to pad t plh 2.49 1.26 + 0.025*cl 1.26 + 0.025*cl 1.26 + 0.025*cl t phl 2.19 1.37 + 0.016*cl 1.40 + 0.016*cl 1.40 + 0.016*cl t r 3.01 0.27 + 0.055*cl 0.27 + 0.055*cl 0.23 + 0.055*cl t f 1.99 0.36 + 0.032*cl 0.38 + 0.032*cl 0.35 + 0.033*cl t plz 2.01 1.99 + 0.000*cl 2.00 + 0.000*cl 2.00 + 0.000*cl t phz 1.94 1.93 + 0.000*cl 1.93 + 0.000*cl 1.93 + 0.000*cl en to pad t plh 2.61 1.38 + 0.025*cl 1.38 + 0.025*cl 1.39 + 0.025*cl t phl 2.31 1.49 + 0.016*cl 1.52 + 0.016*cl 1.53 + 0.016*cl t r 3.01 0.28 + 0.055*cl 0.23 + 0.055*cl 0.23 + 0.055*cl t f 1.99 0.37 + 0.032*cl 0.32 + 0.033*cl 0.35 + 0.033*cl t plz 1.96 1.99 + -0.001*cl 1.94 + 0.000*cl 1.81 + 0.002*cl t phz 1.88 1.87 + 0.000*cl 1.87 + 0.000*cl 1.87 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-78 sec asic pvotyz tri-state output buffers STD80 plot4sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 6.25 1.28 + 0.099*cl 1.28 + 0.099*cl 1.28 + 0.099*cl t phl 4.52 1.33 + 0.064*cl 1.33 + 0.064*cl 1.33 + 0.064*cl t r 11.58 0.27 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl tn to pad t plh 6.03 1.06 + 0.099*cl 1.06 + 0.099*cl 1.06 + 0.099*cl t phl 4.53 1.34 + 0.064*cl 1.34 + 0.064*cl 1.34 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.27 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.23 + 0.137*cl t plz 1.19 1.16 + 0.001*cl 1.20 + 0.000*cl 1.20 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 6.15 1.18 + 0.099*cl 1.18 + 0.099*cl 1.18 + 0.099*cl t phl 4.67 1.48 + 0.064*cl 1.47 + 0.064*cl 1.48 + 0.064*cl t r 11.58 0.27 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.26 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl t plz 1.15 1.20 + -0.001*cl 1.12 + 0.000*cl 1.12 + 0.000*cl t phz 1.03 1.03 + 0.000*cl 1.03 + 0.000*cl 1.03 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plot6sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.76 1.48 + 0.066*cl 1.48 + 0.066*cl 1.48 + 0.066*cl t phl 3.76 1.65 + 0.042*cl 1.66 + 0.042*cl 1.67 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.24 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.37 + 0.089*cl tn to pad t plh 4.53 1.25 + 0.066*cl 1.25 + 0.066*cl 1.25 + 0.066*cl t phl 3.77 1.65 + 0.042*cl 1.66 + 0.042*cl 1.68 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.25 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.47 + 0.088*cl 0.41 + 0.089*cl 0.39 + 0.089*cl t plz 1.14 1.14 + 0.000*cl 1.14 + 0.000*cl 1.14 + 0.000*cl t phz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl en to pad t plh 4.65 1.37 + 0.066*cl 1.37 + 0.066*cl 1.37 + 0.066*cl t phl 3.89 1.78 + 0.042*cl 1.78 + 0.042*cl 1.79 + 0.042*cl t r 7.71 0.27 + 0.149*cl 0.24 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.40 + 0.089*cl 0.39 + 0.089*cl t plz 1.09 1.09 + 0.000*cl 1.26 + -0.002*cl 1.06 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-79 STD80/stdm80 pvotyz tri-state output buffers STD80 plot8sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.10 1.65 + 0.049*cl 1.65 + 0.049*cl 1.66 + 0.049*cl t phl 3.55 1.92 + 0.033*cl 1.97 + 0.032*cl 1.99 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.29 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.64 + 0.065*cl 0.58 + 0.066*cl tn to pad t plh 3.88 1.42 + 0.049*cl 1.43 + 0.049*cl 1.43 + 0.049*cl t phl 3.56 1.92 + 0.033*cl 1.97 + 0.032*cl 1.99 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.30 + 0.111*cl 0.29 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.67 + 0.065*cl 0.60 + 0.066*cl t plz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl t phz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl en to pad t plh 3.99 1.54 + 0.049*cl 1.55 + 0.049*cl 1.55 + 0.049*cl t phl 3.68 2.04 + 0.033*cl 2.09 + 0.032*cl 2.11 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.30 + 0.111*cl 0.29 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.64 + 0.065*cl 0.61 + 0.065*cl t plz 1.09 1.14 + -0.001*cl 1.07 + 0.000*cl 1.07 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plot10sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.57 1.64 + 0.039*cl 1.64 + 0.039*cl 1.65 + 0.039*cl t phl 3.21 1.86 + 0.027*cl 1.94 + 0.026*cl 1.97 + 0.026*cl t r 4.71 0.40 + 0.086*cl 0.34 + 0.087*cl 0.34 + 0.087*cl t f 3.35 0.86 + 0.050*cl 0.85 + 0.050*cl 0.78 + 0.051*cl tn to pad t plh 3.35 1.41 + 0.039*cl 1.43 + 0.039*cl 1.41 + 0.039*cl t phl 3.21 1.85 + 0.027*cl 1.93 + 0.026*cl 1.97 + 0.026*cl t r 4.70 0.39 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.35 0.87 + 0.050*cl 0.85 + 0.050*cl 0.80 + 0.051*cl t plz 1.26 1.24 + 0.000*cl 1.27 + 0.000*cl 1.27 + 0.000*cl t phz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl en to pad t plh 3.46 1.53 + 0.039*cl 1.53 + 0.039*cl 1.53 + 0.039*cl t phl 3.33 1.97 + 0.027*cl 2.06 + 0.026*cl 2.09 + 0.026*cl t r 4.70 0.40 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.35 0.88 + 0.050*cl 0.85 + 0.050*cl 0.80 + 0.050*cl t plz 1.23 1.28 + -0.001*cl 1.01 + 0.003*cl 1.38 + -0.002*cl t phz 1.13 1.13 + 0.000*cl 1.13 + 0.000*cl 1.13 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-80 sec asic pvotyz tri-state output buffers STD80 plot12sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.42 1.79 + 0.033*cl 1.80 + 0.032*cl 1.82 + 0.032*cl t phl 3.25 2.02 + 0.025*cl 2.13 + 0.023*cl 2.19 + 0.022*cl t r 4.06 0.50 + 0.071*cl 0.46 + 0.072*cl 0.43 + 0.072*cl t f 3.10 1.03 + 0.041*cl 1.03 + 0.041*cl 1.02 + 0.041*cl tn to pad t plh 3.19 1.56 + 0.033*cl 1.56 + 0.033*cl 1.60 + 0.032*cl t phl 3.24 2.00 + 0.025*cl 2.12 + 0.023*cl 2.17 + 0.023*cl t r 4.06 0.52 + 0.071*cl 0.44 + 0.072*cl 0.45 + 0.072*cl t f 3.12 1.08 + 0.041*cl 1.07 + 0.041*cl 1.04 + 0.041*cl t plz 1.27 1.27 + 0.000*cl 1.27 + 0.000*cl 1.27 + 0.000*cl t phz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl en to pad t plh 3.31 1.68 + 0.033*cl 1.69 + 0.032*cl 1.71 + 0.032*cl t phl 3.36 2.12 + 0.025*cl 2.24 + 0.023*cl 2.30 + 0.023*cl t r 4.06 0.51 + 0.071*cl 0.47 + 0.072*cl 0.43 + 0.072*cl t f 3.11 1.07 + 0.041*cl 1.04 + 0.041*cl 1.04 + 0.041*cl t plz 1.23 1.28 + -0.001*cl 1.20 + 0.000*cl 1.06 + 0.002*cl t phz 1.13 1.13 + 0.000*cl 1.13 + 0.000*cl 1.13 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = STD80 plot16sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.35 2.06 + 0.026*cl 2.11 + 0.025*cl 2.13 + 0.025*cl t phl 3.43 2.31 + 0.022*cl 2.45 + 0.020*cl 2.53 + 0.020*cl t r 3.38 0.74 + 0.053*cl 0.69 + 0.053*cl 0.64 + 0.054*cl t f 2.88 1.25 + 0.033*cl 1.31 + 0.032*cl 1.29 + 0.032*cl tn to pad t plh 3.11 1.82 + 0.026*cl 1.86 + 0.025*cl 1.90 + 0.025*cl t phl 3.40 2.26 + 0.023*cl 2.42 + 0.021*cl 2.50 + 0.020*cl t r 3.39 0.76 + 0.053*cl 0.71 + 0.053*cl 0.68 + 0.054*cl t f 2.94 1.37 + 0.031*cl 1.40 + 0.031*cl 1.38 + 0.031*cl t plz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.17 + 0.001*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl en to pad t plh 3.23 1.93 + 0.026*cl 1.98 + 0.025*cl 2.01 + 0.025*cl t phl 3.52 2.38 + 0.023*cl 2.54 + 0.021*cl 2.63 + 0.020*cl t r 3.38 0.76 + 0.053*cl 0.70 + 0.053*cl 0.67 + 0.054*cl t f 2.94 1.36 + 0.032*cl 1.40 + 0.031*cl 1.38 + 0.031*cl t plz 1.20 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl t phz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-81 STD80/stdm80 pvotyz tri-state output buffers stdm80 pot1 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 21.36 0.92 + 0.409*cl 0.92 + 0.409*cl 0.92 + 0.409*cl t phl 14.04 0.84 + 0.264*cl 0.84 + 0.264*cl 0.84 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl tn to pad t plh 21.33 1.42 + 0.398*cl 3.44 + 0.371*cl 6.52 + 0.335*cl t phl 14.08 0.88 + 0.264*cl 0.88 + 0.264*cl 0.88 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.86 0.86 + 0.000*cl 0.86 + 0.000*cl 0.86 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl en to pad t plh 21.52 1.61 + 0.398*cl 3.67 + 0.371*cl 6.79 + 0.334*cl t phl 14.28 1.08 + 0.264*cl 1.08 + 0.264*cl 1.08 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.77 0.77 + 0.000*cl 0.76 + 0.000*cl 0.76 + 0.000*cl t phz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pot2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.45 0.80 + 0.193*cl 0.80 + 0.193*cl 0.80 + 0.193*cl t phl 6.93 0.75 + 0.124*cl 0.75 + 0.124*cl 0.75 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl tn to pad t plh 10.43 0.78 + 0.193*cl 0.78 + 0.193*cl 0.79 + 0.193*cl t phl 6.97 0.79 + 0.124*cl 0.80 + 0.123*cl 0.79 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl t phz 0.86 0.86 + 0.000*cl 0.86 + 0.000*cl 0.86 + 0.000*cl en to pad t plh 10.62 0.97 + 0.193*cl 0.97 + 0.193*cl 0.99 + 0.193*cl t phl 7.16 0.99 + 0.124*cl 0.98 + 0.124*cl 0.99 + 0.123*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.78 + 0.000*cl 0.79 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-82 sec asic pvotyz tri-state output buffers stdm80 pot4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf ] path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.55 0.72 + 0.097*cl 0.73 + 0.096*cl 0.73 + 0.096*cl t phl 3.89 0.80 + 0.062*cl 0.80 + 0.062*cl 0.80 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl tn to pad t plh 5.53 0.71 + 0.096*cl 0.71 + 0.097*cl 0.71 + 0.097*cl t phl 3.92 0.83 + 0.062*cl 0.83 + 0.062*cl 0.83 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl t plz 1.08 1.07 + 0.000*cl 1.08 + 0.000*cl 1.06 + 0.000*cl t phz 1.52 1.50 + 0.000*cl 1.51 + 0.000*cl 1.51 + 0.000*cl en to pad t plh 5.72 0.89 + 0.097*cl 0.89 + 0.097*cl 0.89 + 0.097*cl t phl 4.11 1.02 + 0.062*cl 1.02 + 0.062*cl 1.03 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl t plz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl t phz 1.40 1.40 + 0.000*cl 1.40 + 0.000*cl 1.40 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pot6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.00 0.79 + 0.064*cl 0.79 + 0.064*cl 0.78 + 0.064*cl t phl 2.95 0.91 + 0.041*cl 0.90 + 0.041*cl 0.90 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.20 + 0.146*cl 0.20 + 0.146*cl t f 4.58 0.16 + 0.088*cl 0.15 + 0.089*cl 0.13 + 0.089*cl tn to pad t plh 3.98 0.77 + 0.064*cl 0.76 + 0.064*cl 0.77 + 0.064*cl t phl 2.97 0.91 + 0.041*cl 0.91 + 0.041*cl 0.91 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.13 + 0.089*cl 0.13 + 0.089*cl t plz 1.21 1.21 + 0.000*cl 1.21 + 0.000*cl 1.20 + 0.000*cl t phz 1.89 1.89 + 0.000*cl 1.89 + 0.000*cl 1.89 + 0.000*cl en to pad t plh 4.17 0.95 + 0.064*cl 0.95 + 0.064*cl 0.95 + 0.064*cl t phl 3.16 1.10 + 0.041*cl 1.10 + 0.041*cl 1.11 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.20 + 0.146*cl 0.19 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.14 + 0.089*cl 0.13 + 0.089*cl t plz 1.13 1.18 + -0.001*cl 1.11 + 0.000*cl 1.11 + 0.000*cl t phz 1.79 1.78 + 0.000*cl 1.78 + 0.000*cl 1.78 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-83 STD80/stdm80 pvotyz tri-state output buffers stdm80 pot8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.27 0.86 + 0.048*cl 0.85 + 0.048*cl 0.86 + 0.048*cl t phl 2.55 1.04 + 0.030*cl 1.02 + 0.031*cl 1.01 + 0.031*cl t r 5.66 0.17 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.25 + 0.065*cl 0.20 + 0.066*cl 0.18 + 0.066*cl tn to pad t plh 3.25 0.83 + 0.048*cl 0.83 + 0.048*cl 0.83 + 0.048*cl t phl 2.54 1.00 + 0.031*cl 0.99 + 0.031*cl 1.00 + 0.031*cl t r 5.66 0.17 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.15 + 0.066*cl 0.15 + 0.066*cl t plz 1.33 1.32 + 0.000*cl 1.39 + -0.001*cl 1.33 + 0.000*cl t phz 2.28 2.28 + 0.000*cl 2.28 + 0.000*cl 2.28 + 0.000*cl en to pad t plh 3.43 1.02 + 0.048*cl 1.02 + 0.048*cl 1.02 + 0.048*cl t phl 2.73 1.18 + 0.031*cl 1.19 + 0.031*cl 1.18 + 0.031*cl t r 5.66 0.17 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.16 + 0.066*cl 0.14 + 0.066*cl t plz 1.24 1.24 + 0.000*cl 1.24 + 0.000*cl 1.24 + 0.000*cl t phz 2.17 2.17 + 0.000*cl 2.17 + 0.000*cl 2.17 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pot10 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.90 0.97 + 0.039*cl 0.97 + 0.039*cl 0.97 + 0.039*cl t phl 2.29 1.06 + 0.025*cl 1.05 + 0.025*cl 1.06 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.22 + 0.052*cl 0.17 + 0.053*cl 0.19 + 0.053*cl tn to pad t plh 2.88 0.95 + 0.039*cl 0.94 + 0.039*cl 0.95 + 0.039*cl t phl 2.32 1.08 + 0.025*cl 1.09 + 0.025*cl 1.09 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.17 + 0.088*cl 0.16 + 0.088*cl t f 2.84 0.22 + 0.052*cl 0.18 + 0.053*cl 0.19 + 0.053*cl t plz 1.46 1.46 + 0.000*cl 1.44 + 0.000*cl 1.45 + 0.000*cl t phz 1.69 1.69 + 0.000*cl 1.69 + 0.000*cl 1.69 + 0.000*cl en to pad t plh 3.07 1.14 + 0.039*cl 1.13 + 0.039*cl 1.14 + 0.039*cl t phl 2.51 1.28 + 0.025*cl 1.28 + 0.025*cl 1.28 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.16 + 0.088*cl 0.17 + 0.088*cl t f 2.83 0.22 + 0.052*cl 0.19 + 0.053*cl 0.18 + 0.053*cl t plz 1.37 1.37 + 0.000*cl 1.36 + 0.000*cl 1.37 + 0.000*cl t phz 1.58 1.58 + 0.000*cl 1.58 + 0.000*cl 1.58 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-84 sec asic pvotyz tri-state output buffers stdm80 pot12 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.70 1.09 + 0.032*cl 1.09 + 0.032*cl 1.08 + 0.032*cl t phl 2.16 1.13 + 0.021*cl 1.14 + 0.021*cl 1.13 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.18 + 0.073*cl 0.17 + 0.073*cl t f 2.42 0.26 + 0.043*cl 0.23 + 0.044*cl 0.24 + 0.044*cl tn to pad t plh 2.67 1.06 + 0.032*cl 1.06 + 0.032*cl 1.07 + 0.032*cl t phl 2.20 1.16 + 0.021*cl 1.18 + 0.021*cl 1.17 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.26 + 0.043*cl 0.26 + 0.043*cl 0.24 + 0.044*cl t plz 1.59 1.58 + 0.000*cl 1.58 + 0.000*cl 1.59 + 0.000*cl t phz 1.50 1.50 + 0.000*cl 1.50 + 0.000*cl 1.50 + 0.000*cl en to pad t plh 2.86 1.25 + 0.032*cl 1.25 + 0.032*cl 1.25 + 0.032*cl t phl 2.39 1.36 + 0.021*cl 1.36 + 0.021*cl 1.37 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.28 + 0.043*cl 0.26 + 0.043*cl 0.24 + 0.044*cl t plz 1.49 1.49 + 0.000*cl 1.49 + 0.000*cl 1.49 + 0.000*cl t phz 1.43 1.38 + 0.001*cl 1.45 + 0.000*cl 1.45 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pot16 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.46 1.24 + 0.024*cl 1.24 + 0.024*cl 1.24 + 0.024*cl t phl 2.08 1.27 + 0.016*cl 1.29 + 0.016*cl 1.30 + 0.016*cl t r 3.00 0.26 + 0.055*cl 0.23 + 0.055*cl 0.23 + 0.055*cl t f 1.98 0.34 + 0.033*cl 0.34 + 0.033*cl 0.34 + 0.033*cl tn to pad t plh 2.42 1.19 + 0.025*cl 1.20 + 0.025*cl 1.20 + 0.025*cl t phl 2.11 1.29 + 0.016*cl 1.32 + 0.016*cl 1.33 + 0.016*cl t r 3.01 0.27 + 0.055*cl 0.24 + 0.055*cl 0.24 + 0.055*cl t f 1.98 0.35 + 0.033*cl 0.35 + 0.033*cl 0.32 + 0.033*cl t plz 1.83 1.83 + 0.000*cl 1.83 + 0.000*cl 1.83 + 0.000*cl t phz 1.74 1.74 + 0.000*cl 1.74 + 0.000*cl 1.74 + 0.000*cl en to pad t plh 2.61 1.38 + 0.025*cl 1.38 + 0.025*cl 1.39 + 0.025*cl t phl 2.30 1.48 + 0.016*cl 1.51 + 0.016*cl 1.52 + 0.016*cl t r 3.01 0.28 + 0.055*cl 0.24 + 0.055*cl 0.23 + 0.055*cl t f 1.98 0.36 + 0.032*cl 0.36 + 0.032*cl 0.32 + 0.033*cl t plz 1.73 1.73 + 0.000*cl 1.73 + 0.000*cl 1.72 + 0.000*cl t phz 1.66 1.65 + 0.000*cl 1.66 + 0.000*cl 1.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-85 STD80/stdm80 pvotyz tri-state output buffers stdm80 pot4sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.99 1.03 + 0.099*cl 1.03 + 0.099*cl 1.03 + 0.099*cl t phl 4.41 1.22 + 0.064*cl 1.22 + 0.064*cl 1.22 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.28 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl tn to pad t plh 5.96 1.00 + 0.099*cl 1.00 + 0.099*cl 1.00 + 0.099*cl t phl 4.45 1.26 + 0.064*cl 1.25 + 0.064*cl 1.26 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.27 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl t plz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t plh 6.15 1.18 + 0.099*cl 1.19 + 0.099*cl 1.15 + 0.100*cl t phl 4.64 1.45 + 0.064*cl 1.45 + 0.064*cl 1.45 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.27 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.23 + 0.137*cl t plz 0.91 0.85 + 0.001*cl 0.94 + 0.000*cl 0.94 + 0.000*cl t phz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pot6sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.51 1.23 + 0.066*cl 1.23 + 0.066*cl 1.23 + 0.066*cl t phl 3.65 1.53 + 0.042*cl 1.55 + 0.042*cl 1.55 + 0.042*cl t r 7.71 0.27 + 0.149*cl 0.24 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.42 + 0.089*cl 0.38 + 0.089*cl tn to pad t plh 4.47 1.19 + 0.066*cl 1.20 + 0.066*cl 1.19 + 0.066*cl t phl 3.69 1.58 + 0.042*cl 1.59 + 0.042*cl 1.59 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.25 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.42 + 0.089*cl 0.37 + 0.089*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl t phz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t plh 4.66 1.38 + 0.066*cl 1.38 + 0.066*cl 1.38 + 0.066*cl t phl 3.89 1.77 + 0.042*cl 1.78 + 0.042*cl 1.79 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.25 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.38 + 0.089*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl t phz 0.77 0.77 + 0.000*cl 0.77 + 0.000*cl 0.77 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-86 sec asic pvotyz tri-state output buffers stdm80 pot8sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.85 1.40 + 0.049*cl 1.40 + 0.049*cl 1.40 + 0.049*cl t phl 3.44 1.80 + 0.033*cl 1.85 + 0.032*cl 1.87 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.30 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.63 + 0.065*cl 0.61 + 0.066*cl tn to pad t plh 3.81 1.36 + 0.049*cl 1.22 + 0.051*cl 1.39 + 0.049*cl t phl 3.48 1.84 + 0.033*cl 1.89 + 0.032*cl 1.91 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.29 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.63 + 0.065*cl 0.62 + 0.065*cl t plz 0.95 0.95 + 0.000*cl 0.93 + 0.000*cl 0.95 + 0.000*cl t phz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t plh 4.00 1.55 + 0.049*cl 1.55 + 0.049*cl 1.55 + 0.049*cl t phl 3.67 2.04 + 0.033*cl 2.08 + 0.032*cl 2.10 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.29 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.69 + 0.064*cl 0.61 + 0.065*cl 0.62 + 0.065*cl t plz 0.88 0.93 + -0.001*cl 0.85 + 0.000*cl 0.85 + 0.000*cl t phz 0.77 0.77 + 0.000*cl 0.77 + 0.000*cl 0.77 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pot10sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.32 1.38 + 0.039*cl 1.39 + 0.039*cl 1.39 + 0.039*cl t phl 3.10 1.74 + 0.027*cl 1.82 + 0.026*cl 1.86 + 0.026*cl t r 4.70 0.39 + 0.086*cl 0.35 + 0.087*cl 0.34 + 0.087*cl t f 3.34 0.85 + 0.050*cl 0.83 + 0.050*cl 0.80 + 0.050*cl tn to pad t plh 3.28 1.35 + 0.039*cl 1.35 + 0.039*cl 1.35 + 0.039*cl t phl 3.13 1.77 + 0.027*cl 1.86 + 0.026*cl 1.89 + 0.026*cl t r 4.71 0.40 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.36 0.88 + 0.049*cl 0.84 + 0.050*cl 0.79 + 0.051*cl t plz 1.09 1.09 + 0.000*cl 1.08 + 0.000*cl 1.08 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl en to pad t plh 3.47 1.53 + 0.039*cl 1.54 + 0.039*cl 1.54 + 0.039*cl t phl 3.33 1.97 + 0.027*cl 2.05 + 0.026*cl 2.08 + 0.026*cl t r 4.70 0.39 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.36 0.88 + 0.049*cl 0.84 + 0.050*cl 0.80 + 0.051*cl t plz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-87 STD80/stdm80 pvotyz tri-state output buffers stdm80 pot12sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.17 1.54 + 0.033*cl 1.55 + 0.032*cl 1.56 + 0.032*cl t phl 3.14 1.91 + 0.025*cl 2.02 + 0.023*cl 2.07 + 0.022*cl t r 4.06 0.51 + 0.071*cl 0.45 + 0.072*cl 0.44 + 0.072*cl t f 3.10 1.03 + 0.041*cl 1.00 + 0.042*cl 1.01 + 0.042*cl tn to pad t plh 3.14 1.51 + 0.033*cl 1.64 + 0.031*cl 1.43 + 0.033*cl t phl 3.17 1.93 + 0.025*cl 2.04 + 0.023*cl 2.10 + 0.023*cl t r 4.06 0.51 + 0.071*cl 0.46 + 0.072*cl 0.43 + 0.072*cl t f 3.12 1.08 + 0.041*cl 1.06 + 0.041*cl 1.02 + 0.042*cl t plz 1.09 1.09 + 0.000*cl 1.07 + 0.000*cl 1.07 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl en to pad t plh 3.32 1.69 + 0.033*cl 1.70 + 0.032*cl 1.70 + 0.032*cl t phl 3.36 2.12 + 0.025*cl 2.24 + 0.023*cl 2.29 + 0.023*cl t r 4.06 0.52 + 0.071*cl 0.46 + 0.072*cl 0.43 + 0.072*cl t f 3.12 1.08 + 0.041*cl 1.06 + 0.041*cl 1.03 + 0.041*cl t plz 0.99 0.98 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 pot16sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.10 1.80 + 0.026*cl 1.86 + 0.025*cl 1.87 + 0.025*cl t phl 3.31 2.19 + 0.022*cl 2.33 + 0.020*cl 2.41 + 0.020*cl t r 3.37 0.73 + 0.053*cl 0.70 + 0.053*cl 0.66 + 0.054*cl t f 2.88 1.25 + 0.033*cl 1.32 + 0.032*cl 1.30 + 0.032*cl tn to pad t plh 3.05 1.72 + 0.026*cl 1.82 + 0.025*cl 1.84 + 0.025*cl t phl 3.32 2.18 + 0.023*cl 2.34 + 0.021*cl 2.43 + 0.020*cl t r 3.38 0.76 + 0.052*cl 0.70 + 0.053*cl 0.67 + 0.054*cl t f 2.95 1.38 + 0.031*cl 1.41 + 0.031*cl 1.37 + 0.031*cl t plz 1.08 1.07 + 0.000*cl 1.08 + 0.000*cl 1.08 + 0.000*cl t phz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl en to pad t plh 3.23 1.94 + 0.026*cl 2.00 + 0.025*cl 2.01 + 0.025*cl t phl 3.52 2.37 + 0.023*cl 2.54 + 0.021*cl 2.62 + 0.020*cl t r 3.39 0.77 + 0.052*cl 0.69 + 0.053*cl 0.68 + 0.054*cl t f 2.94 1.37 + 0.031*cl 1.41 + 0.031*cl 1.37 + 0.031*cl t plz 0.99 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl t phz 0.89 0.88 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-88 sec asic pvotyz tri-state output buffers stdm80 phot1 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 15.51 0.90 + 0.292*cl 0.90 + 0.292*cl 0.89 + 0.292*cl t phl 12.56 0.91 + 0.233*cl 0.92 + 0.233*cl 0.91 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl tn to pad t plh 10.17 1.03 + 0.183*cl 1.63 + 0.175*cl 2.79 + 0.161*cl t phl 17.31 1.10 + 0.324*cl 1.11 + 0.324*cl 1.10 + 0.324*cl t r 16.39 0.24 + 0.323*cl 0.24 + 0.323*cl 0.24 + 0.323*cl t f 20.78 0.31 + 0.409*cl 0.31 + 0.409*cl 0.31 + 0.409*cl t plz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t plh 10.34 1.19 + 0.183*cl 1.80 + 0.175*cl 2.98 + 0.161*cl t phl 17.47 1.27 + 0.324*cl 1.27 + 0.324*cl 1.27 + 0.324*cl t r 16.39 0.24 + 0.323*cl 0.24 + 0.323*cl 0.24 + 0.323*cl t f 20.78 0.31 + 0.409*cl 0.31 + 0.409*cl 0.31 + 0.409*cl t plz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot2 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 8.13 0.83 + 0.146*cl 0.82 + 0.146*cl 0.83 + 0.146*cl t phl 6.65 0.83 + 0.116*cl 0.84 + 0.116*cl 0.84 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.30 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl tn to pad t plh 5.51 0.88 + 0.093*cl 0.88 + 0.093*cl 0.89 + 0.093*cl t phl 9.09 0.99 + 0.162*cl 0.99 + 0.162*cl 0.99 + 0.162*cl t r 8.20 0.12 + 0.161*cl 0.13 + 0.161*cl 0.12 + 0.161*cl t f 10.40 0.17 + 0.205*cl 0.17 + 0.205*cl 0.17 + 0.205*cl t plz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.05 + 0.000*cl t phz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl en to pad t plh 5.68 1.05 + 0.093*cl 1.05 + 0.093*cl 1.05 + 0.093*cl t phl 9.25 1.15 + 0.162*cl 1.15 + 0.162*cl 1.15 + 0.162*cl t r 8.20 0.12 + 0.161*cl 0.13 + 0.161*cl 0.12 + 0.161*cl t f 10.40 0.17 + 0.205*cl 0.17 + 0.205*cl 0.17 + 0.205*cl t plz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-89 STD80/stdm80 pvotyz tri-state output buffers stdm80 phot4 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.52 0.83 + 0.094*cl 0.83 + 0.094*cl 0.83 + 0.094*cl t phl 4.54 0.83 + 0.074*cl 0.82 + 0.074*cl 0.83 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.15 + 0.155*cl 0.14 + 0.155*cl 0.15 + 0.155*cl tn to pad t plh 3.87 0.90 + 0.059*cl 0.90 + 0.059*cl 0.89 + 0.059*cl t phl 6.14 0.97 + 0.103*cl 0.97 + 0.103*cl 0.98 + 0.103*cl t r 5.27 0.09 + 0.104*cl 0.09 + 0.104*cl 0.09 + 0.104*cl t f 6.64 0.12 + 0.130*cl 0.12 + 0.130*cl 0.11 + 0.131*cl t plz 1.13 1.12 + 0.000*cl 1.12 + 0.000*cl 1.07 + 0.001*cl t phz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t plh 4.03 1.06 + 0.059*cl 1.03 + 0.060*cl 1.08 + 0.059*cl t phl 6.30 1.13 + 0.103*cl 1.14 + 0.103*cl 1.13 + 0.103*cl t r 5.27 0.09 + 0.104*cl 0.09 + 0.104*cl 0.08 + 0.104*cl t f 6.64 0.12 + 0.130*cl 0.13 + 0.130*cl 0.11 + 0.131*cl t plz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl t phz 0.88 0.88 + 0.000*cl 0.88 + 0.000*cl 0.88 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot8 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.23 0.89 + 0.047*cl 0.89 + 0.047*cl 0.89 + 0.047*cl t phl 2.74 0.88 + 0.037*cl 0.88 + 0.037*cl 0.89 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl tn to pad t plh 2.45 0.97 + 0.030*cl 0.96 + 0.030*cl 0.97 + 0.030*cl t phl 3.61 1.03 + 0.052*cl 1.02 + 0.052*cl 1.07 + 0.051*cl t r 2.64 0.06 + 0.052*cl 0.05 + 0.052*cl 0.05 + 0.052*cl t f 3.34 0.08 + 0.065*cl 0.09 + 0.065*cl 0.08 + 0.065*cl t plz 1.30 1.30 + 0.000*cl 1.29 + 0.000*cl 1.30 + 0.000*cl t phz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl en to pad t plh 2.62 1.13 + 0.030*cl 1.13 + 0.030*cl 1.13 + 0.030*cl t phl 3.77 1.18 + 0.052*cl 1.19 + 0.052*cl 1.18 + 0.052*cl t r 2.64 0.06 + 0.052*cl 0.05 + 0.052*cl 0.05 + 0.052*cl t f 3.34 0.08 + 0.065*cl 0.08 + 0.065*cl 0.08 + 0.065*cl t plz 1.25 1.28 + -0.001*cl 1.23 + 0.000*cl 1.23 + 0.000*cl t phz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-90 sec asic pvotyz tri-state output buffers stdm80 phot12 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.68 0.95 + 0.034*cl 0.95 + 0.035*cl 0.95 + 0.035*cl t phl 2.30 0.94 + 0.027*cl 0.95 + 0.027*cl 0.94 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.11 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.11 + 0.056*cl 0.09 + 0.057*cl tn to pad t plh 2.12 1.03 + 0.022*cl 1.03 + 0.022*cl 1.03 + 0.022*cl t phl 2.97 1.07 + 0.038*cl 1.07 + 0.038*cl 1.04 + 0.038*cl t r 1.96 0.06 + 0.038*cl 0.05 + 0.038*cl 0.05 + 0.038*cl t f 2.47 0.08 + 0.048*cl 0.08 + 0.048*cl 0.08 + 0.048*cl t plz 1.43 1.42 + 0.000*cl 1.33 + 0.001*cl 1.50 + -0.001*cl t phz 1.10 1.10 + 0.000*cl 1.10 + 0.000*cl 1.10 + 0.000*cl en to pad t plh 2.29 1.19 + 0.022*cl 1.19 + 0.022*cl 1.19 + 0.022*cl t phl 3.14 1.24 + 0.038*cl 1.24 + 0.038*cl 1.24 + 0.038*cl t r 1.96 0.06 + 0.038*cl 0.06 + 0.038*cl 0.05 + 0.038*cl t f 2.47 0.08 + 0.048*cl 0.09 + 0.048*cl 0.07 + 0.048*cl t plz 1.37 1.35 + 0.000*cl 1.36 + 0.000*cl 1.36 + 0.000*cl t phz 1.02 1.02 + 0.000*cl 1.02 + 0.000*cl 1.02 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot16 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.30 1.05 + 0.025*cl 1.05 + 0.025*cl 1.04 + 0.025*cl t phl 2.02 1.03 + 0.020*cl 1.04 + 0.020*cl 1.02 + 0.020*cl t r 2.97 0.14 + 0.057*cl 0.12 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.15 + 0.041*cl 0.14 + 0.041*cl 0.14 + 0.041*cl tn to pad t plh 1.91 1.11 + 0.016*cl 1.11 + 0.016*cl 1.11 + 0.016*cl t phl 2.54 1.16 + 0.028*cl 1.15 + 0.028*cl 1.17 + 0.028*cl t r 1.47 0.10 + 0.027*cl 0.09 + 0.027*cl 0.08 + 0.028*cl t f 1.82 0.07 + 0.035*cl 0.08 + 0.035*cl 0.07 + 0.035*cl t plz 1.60 1.58 + 0.000*cl 1.68 + -0.001*cl 1.60 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl en to pad t plh 2.08 1.27 + 0.016*cl 1.28 + 0.016*cl 1.27 + 0.016*cl t phl 2.71 1.33 + 0.028*cl 1.27 + 0.028*cl 1.32 + 0.028*cl t r 1.47 0.10 + 0.027*cl 0.09 + 0.028*cl 0.08 + 0.028*cl t f 1.82 0.07 + 0.035*cl 0.07 + 0.035*cl 0.08 + 0.035*cl t plz 1.53 1.53 + 0.000*cl 1.53 + 0.000*cl 1.53 + 0.000*cl t phz 1.10 1.10 + 0.000*cl 1.10 + 0.000*cl 1.10 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-91 STD80/stdm80 pvotyz tri-state output buffers stdm80 phot20 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.93 0.94 + 0.020*cl 0.94 + 0.020*cl 0.94 + 0.020*cl t phl 1.79 1.01 + 0.016*cl 1.01 + 0.016*cl 1.00 + 0.016*cl t r 2.34 0.10 + 0.045*cl 0.10 + 0.045*cl 0.08 + 0.045*cl t f 1.75 0.16 + 0.032*cl 0.14 + 0.032*cl 0.12 + 0.032*cl tn to pad t plh 1.65 1.02 + 0.013*cl 1.02 + 0.013*cl 1.02 + 0.013*cl t phl 2.23 1.14 + 0.022*cl 1.13 + 0.022*cl 1.12 + 0.022*cl t r 1.15 0.07 + 0.022*cl 0.05 + 0.022*cl 0.05 + 0.022*cl t f 1.44 0.06 + 0.028*cl 0.06 + 0.028*cl 0.06 + 0.028*cl t plz 1.40 1.39 + 0.000*cl 1.47 + -0.001*cl 1.40 + 0.000*cl t phz 1.15 1.15 + 0.000*cl 1.14 + 0.000*cl 1.15 + 0.000*cl en to pad t plh 1.82 1.18 + 0.013*cl 1.22 + 0.012*cl 1.19 + 0.013*cl t phl 2.39 1.29 + 0.022*cl 1.29 + 0.022*cl 1.29 + 0.022*cl t r 1.15 0.07 + 0.022*cl 0.06 + 0.022*cl 0.05 + 0.022*cl t f 1.44 0.07 + 0.028*cl 0.05 + 0.028*cl 0.06 + 0.028*cl t plz 1.33 1.29 + 0.001*cl 1.51 + -0.002*cl 1.33 + 0.000*cl t phz 1.07 1.07 + 0.000*cl 1.07 + 0.000*cl 1.07 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot24 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.86 0.99 + 0.017*cl 0.98 + 0.018*cl 0.99 + 0.018*cl t phl 1.73 1.04 + 0.014*cl 1.04 + 0.014*cl 1.04 + 0.014*cl t r 2.07 0.10 + 0.039*cl 0.12 + 0.039*cl 0.09 + 0.040*cl t f 1.57 0.17 + 0.028*cl 0.16 + 0.028*cl 0.15 + 0.028*cl tn to pad t plh 1.62 1.07 + 0.011*cl 1.07 + 0.011*cl 1.07 + 0.011*cl t phl 2.13 1.16 + 0.019*cl 1.17 + 0.019*cl 1.17 + 0.019*cl t r 1.03 0.09 + 0.019*cl 0.06 + 0.019*cl 0.07 + 0.019*cl t f 1.28 0.07 + 0.024*cl 0.09 + 0.024*cl 0.05 + 0.024*cl t plz 1.46 1.45 + 0.000*cl 1.40 + 0.001*cl 1.46 + 0.000*cl t phz 1.14 1.14 + 0.000*cl 1.14 + 0.000*cl 1.14 + 0.000*cl en to pad t plh 1.79 1.23 + 0.011*cl 1.23 + 0.011*cl 1.23 + 0.011*cl t phl 2.29 1.33 + 0.019*cl 1.31 + 0.020*cl 1.33 + 0.019*cl t r 1.03 0.09 + 0.019*cl 0.07 + 0.019*cl 0.07 + 0.019*cl t f 1.28 0.07 + 0.024*cl 0.06 + 0.024*cl 0.05 + 0.024*cl t plz 1.39 1.39 + 0.000*cl 1.38 + 0.000*cl 1.39 + 0.000*cl t phz 1.07 1.07 + 0.000*cl 1.07 + 0.000*cl 1.06 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-92 sec asic pvotyz tri-state output buffers stdm80 phot12sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.44 1.66 + 0.036*cl 1.69 + 0.035*cl 1.69 + 0.035*cl t phl 3.94 2.34 + 0.032*cl 2.45 + 0.031*cl 2.51 + 0.030*cl t r 4.34 0.50 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.74 0.97 + 0.055*cl 1.00 + 0.055*cl 0.99 + 0.055*cl tn to pad t plh 2.80 1.64 + 0.023*cl 1.68 + 0.023*cl 1.70 + 0.022*cl t phl 4.69 2.58 + 0.042*cl 2.69 + 0.041*cl 2.74 + 0.040*cl t r 2.26 0.43 + 0.037*cl 0.41 + 0.037*cl 0.38 + 0.037*cl t f 2.79 0.45 + 0.047*cl 0.43 + 0.047*cl 0.39 + 0.048*cl t plz 1.75 1.74 + 0.000*cl 1.71 + 0.001*cl 1.81 + -0.001*cl t phz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl en to pad t plh 2.97 1.81 + 0.023*cl 1.85 + 0.023*cl 1.86 + 0.022*cl t phl 4.86 2.75 + 0.042*cl 2.84 + 0.041*cl 2.90 + 0.040*cl t r 2.26 0.43 + 0.037*cl 0.40 + 0.037*cl 0.38 + 0.037*cl t f 2.79 0.45 + 0.047*cl 0.40 + 0.047*cl 0.41 + 0.047*cl t plz 1.68 1.68 + 0.000*cl 1.68 + 0.000*cl 1.68 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot16sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.24 1.89 + 0.027*cl 1.94 + 0.026*cl 1.97 + 0.026*cl t phl 3.64 2.39 + 0.025*cl 2.50 + 0.024*cl 2.56 + 0.023*cl t r 3.43 0.71 + 0.055*cl 0.68 + 0.055*cl 0.67 + 0.055*cl t f 3.00 0.96 + 0.041*cl 1.01 + 0.040*cl 1.02 + 0.040*cl tn to pad t plh 2.73 1.81 + 0.019*cl 1.88 + 0.017*cl 1.91 + 0.017*cl t phl 4.24 2.60 + 0.033*cl 2.72 + 0.031*cl 2.78 + 0.030*cl t r 1.90 0.61 + 0.026*cl 0.60 + 0.026*cl 0.59 + 0.026*cl t f 2.17 0.50 + 0.033*cl 0.47 + 0.034*cl 0.47 + 0.034*cl t plz 1.72 1.72 + 0.000*cl 1.72 + 0.000*cl 1.72 + 0.000*cl t phz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl en to pad t plh 2.90 1.97 + 0.018*cl 2.04 + 0.018*cl 2.08 + 0.017*cl t phl 4.40 2.77 + 0.033*cl 2.89 + 0.031*cl 2.94 + 0.031*cl t r 1.90 0.61 + 0.026*cl 0.61 + 0.026*cl 0.59 + 0.026*cl t f 2.17 0.49 + 0.033*cl 0.48 + 0.034*cl 0.47 + 0.034*cl t plz 1.65 1.65 + 0.000*cl 1.65 + 0.000*cl 1.65 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-93 STD80/stdm80 pvotyz tri-state output buffers stdm80 phot20sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.63 1.57 + 0.021*cl 1.62 + 0.021*cl 1.63 + 0.020*cl t phl 2.66 1.80 + 0.017*cl 1.84 + 0.017*cl 1.85 + 0.017*cl t r 2.72 0.58 + 0.043*cl 0.55 + 0.043*cl 0.55 + 0.043*cl t f 2.24 0.72 + 0.030*cl 0.70 + 0.031*cl 0.69 + 0.031*cl tn to pad t plh 2.25 1.52 + 0.015*cl 1.58 + 0.014*cl 1.61 + 0.014*cl t phl 3.05 1.82 + 0.024*cl 1.91 + 0.023*cl 1.93 + 0.023*cl t r 1.53 0.53 + 0.020*cl 0.50 + 0.020*cl 0.51 + 0.020*cl t f 1.63 0.32 + 0.026*cl 0.29 + 0.027*cl 0.27 + 0.027*cl t plz 1.08 1.06 + 0.000*cl 1.16 + -0.001*cl 1.08 + 0.000*cl t phz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl en to pad t plh 2.42 1.69 + 0.015*cl 1.75 + 0.014*cl 1.78 + 0.013*cl t phl 3.21 1.98 + 0.025*cl 2.07 + 0.023*cl 2.09 + 0.023*cl t r 1.53 0.53 + 0.020*cl 0.50 + 0.020*cl 0.50 + 0.020*cl t f 1.63 0.30 + 0.026*cl 0.32 + 0.026*cl 0.27 + 0.027*cl t plz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot24sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.62 1.65 + 0.019*cl 1.72 + 0.019*cl 1.73 + 0.018*cl t phl 2.73 1.94 + 0.016*cl 1.97 + 0.015*cl 1.99 + 0.015*cl t r 2.54 0.66 + 0.038*cl 0.67 + 0.037*cl 0.63 + 0.038*cl t f 2.15 0.81 + 0.027*cl 0.82 + 0.027*cl 0.79 + 0.027*cl tn to pad t plh 2.27 1.58 + 0.014*cl 1.65 + 0.013*cl 1.68 + 0.012*cl t phl 3.04 1.90 + 0.023*cl 1.99 + 0.022*cl 2.04 + 0.021*cl t r 1.47 0.59 + 0.018*cl 0.60 + 0.018*cl 0.57 + 0.018*cl t f 1.52 0.37 + 0.023*cl 0.38 + 0.023*cl 0.34 + 0.023*cl t plz 1.08 1.08 + 0.000*cl 1.08 + 0.000*cl 1.08 + 0.000*cl t phz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl en to pad t plh 2.43 1.74 + 0.014*cl 1.82 + 0.013*cl 1.84 + 0.012*cl t phl 3.20 2.07 + 0.023*cl 2.16 + 0.021*cl 2.19 + 0.021*cl t r 1.48 0.60 + 0.018*cl 0.61 + 0.017*cl 0.57 + 0.018*cl t f 1.52 0.37 + 0.023*cl 0.35 + 0.023*cl 0.35 + 0.023*cl t plz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-94 sec asic pvotyz tri-state output buffers stdm80 phot4sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.86 1.16 + 0.094*cl 1.17 + 0.094*cl 1.17 + 0.094*cl t phl 5.46 1.74 + 0.074*cl 1.75 + 0.074*cl 1.75 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.23 + 0.212*cl 0.24 + 0.212*cl t f 8.06 0.43 + 0.153*cl 0.38 + 0.153*cl 0.36 + 0.153*cl tn to pad t plh 4.17 1.20 + 0.059*cl 1.20 + 0.059*cl 1.20 + 0.059*cl t phl 7.07 1.90 + 0.103*cl 1.90 + 0.103*cl 1.91 + 0.103*cl t r 5.29 0.13 + 0.103*cl 0.11 + 0.103*cl 0.11 + 0.104*cl t f 6.69 0.18 + 0.130*cl 0.16 + 0.130*cl 0.16 + 0.130*cl t plz 1.77 1.77 + 0.000*cl 1.77 + 0.000*cl 1.77 + 0.000*cl t phz 1.26 1.26 + 0.000*cl 1.26 + 0.000*cl 1.26 + 0.000*cl en to pad t plh 4.33 1.36 + 0.059*cl 1.36 + 0.060*cl 1.37 + 0.059*cl t phl 7.24 2.07 + 0.103*cl 2.04 + 0.104*cl 2.07 + 0.103*cl t r 5.29 0.13 + 0.103*cl 0.11 + 0.103*cl 0.11 + 0.104*cl t f 6.69 0.17 + 0.130*cl 0.16 + 0.130*cl 0.16 + 0.130*cl t plz 1.71 1.70 + 0.000*cl 1.71 + 0.000*cl 1.71 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot8sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.82 1.47 + 0.047*cl 1.48 + 0.047*cl 1.48 + 0.047*cl t phl 4.07 2.11 + 0.039*cl 2.18 + 0.038*cl 2.21 + 0.038*cl t r 5.58 0.35 + 0.105*cl 0.31 + 0.105*cl 0.29 + 0.105*cl t f 4.47 0.75 + 0.074*cl 0.72 + 0.075*cl 0.70 + 0.075*cl tn to pad t plh 2.99 1.49 + 0.030*cl 1.50 + 0.030*cl 1.50 + 0.030*cl t phl 4.98 2.31 + 0.053*cl 2.37 + 0.053*cl 2.38 + 0.052*cl t r 2.80 0.29 + 0.050*cl 0.26 + 0.051*cl 0.23 + 0.051*cl t f 3.50 0.31 + 0.064*cl 0.28 + 0.064*cl 0.25 + 0.065*cl t plz 1.76 1.74 + 0.000*cl 1.66 + 0.001*cl 1.76 + 0.000*cl t phz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl en to pad t plh 3.15 1.65 + 0.030*cl 1.67 + 0.030*cl 1.67 + 0.030*cl t phl 5.14 2.48 + 0.053*cl 2.54 + 0.053*cl 2.56 + 0.052*cl t r 2.80 0.29 + 0.050*cl 0.26 + 0.051*cl 0.23 + 0.051*cl t f 3.50 0.31 + 0.064*cl 0.28 + 0.064*cl 0.25 + 0.065*cl t plz 1.71 1.70 + 0.000*cl 1.69 + 0.000*cl 1.69 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-95 STD80/stdm80 pvotyz tri-state output buffers stdm80 phot12sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.25 1.51 + 0.035*cl 1.52 + 0.035*cl 1.53 + 0.035*cl t phl 3.57 2.04 + 0.031*cl 2.13 + 0.029*cl 2.18 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.35 + 0.077*cl t f 3.55 0.81 + 0.055*cl 0.83 + 0.055*cl 0.82 + 0.055*cl tn to pad t plh 2.63 1.50 + 0.023*cl 1.53 + 0.022*cl 1.55 + 0.022*cl t phl 4.30 2.26 + 0.041*cl 2.35 + 0.040*cl 2.39 + 0.039*cl t r 2.18 0.37 + 0.036*cl 0.32 + 0.037*cl 0.32 + 0.037*cl t f 2.69 0.39 + 0.046*cl 0.37 + 0.046*cl 0.33 + 0.047*cl t plz 1.99 1.99 + 0.000*cl 1.93 + 0.001*cl 2.05 + -0.001*cl t phz 1.42 1.42 + 0.000*cl 1.41 + 0.000*cl 1.42 + 0.000*cl en to pad t plh 2.80 1.67 + 0.022*cl 1.67 + 0.022*cl 1.71 + 0.022*cl t phl 4.47 2.42 + 0.041*cl 2.51 + 0.040*cl 2.55 + 0.039*cl t r 2.18 0.37 + 0.036*cl 0.33 + 0.037*cl 0.32 + 0.037*cl t f 2.69 0.38 + 0.046*cl 0.36 + 0.047*cl 0.34 + 0.047*cl t plz 1.92 1.92 + 0.000*cl 1.92 + 0.000*cl 1.84 + 0.001*cl t phz 1.35 1.35 + 0.000*cl 1.35 + 0.000*cl 1.35 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot16sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.93 1.61 + 0.026*cl 1.65 + 0.026*cl 1.67 + 0.026*cl t phl 3.14 1.96 + 0.024*cl 2.05 + 0.023*cl 2.09 + 0.022*cl t r 3.29 0.54 + 0.055*cl 0.50 + 0.056*cl 0.50 + 0.055*cl t f 2.77 0.74 + 0.041*cl 0.77 + 0.040*cl 0.79 + 0.040*cl tn to pad t plh 2.45 1.56 + 0.018*cl 1.59 + 0.017*cl 1.67 + 0.016*cl t phl 3.72 2.16 + 0.031*cl 2.25 + 0.030*cl 2.30 + 0.029*cl t r 1.77 0.45 + 0.026*cl 0.46 + 0.026*cl 0.46 + 0.026*cl t f 2.07 0.38 + 0.034*cl 0.38 + 0.034*cl 0.36 + 0.034*cl t plz 2.19 2.23 + -0.001*cl 2.17 + 0.000*cl 2.11 + 0.001*cl t phz 1.56 1.56 + 0.000*cl 1.56 + 0.000*cl 1.56 + 0.000*cl en to pad t plh 2.61 1.73 + 0.018*cl 1.78 + 0.017*cl 1.80 + 0.017*cl t phl 3.89 2.32 + 0.031*cl 2.41 + 0.030*cl 2.47 + 0.029*cl t r 1.77 0.46 + 0.026*cl 0.47 + 0.026*cl 0.45 + 0.026*cl t f 2.07 0.38 + 0.034*cl 0.39 + 0.034*cl 0.36 + 0.034*cl t plz 2.12 2.10 + 0.000*cl 2.11 + 0.000*cl 2.11 + 0.000*cl t phz 1.49 1.49 + 0.000*cl 1.49 + 0.000*cl 1.49 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
STD80/stdm80 4-96 sec asic pvotyz tri-state output buffers stdm80 phot20sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.30 1.29 + 0.020*cl 1.30 + 0.020*cl 1.31 + 0.020*cl t phl 2.30 1.41 + 0.018*cl 1.46 + 0.017*cl 1.49 + 0.017*cl t r 2.53 0.36 + 0.043*cl 0.34 + 0.044*cl 0.31 + 0.044*cl t f 2.11 0.54 + 0.031*cl 0.56 + 0.031*cl 0.56 + 0.031*cl tn to pad t plh 1.98 1.30 + 0.013*cl 1.34 + 0.013*cl 1.34 + 0.013*cl t phl 2.76 1.57 + 0.024*cl 1.61 + 0.023*cl 1.64 + 0.023*cl t r 1.36 0.35 + 0.020*cl 0.32 + 0.021*cl 0.30 + 0.021*cl t f 1.58 0.26 + 0.026*cl 0.24 + 0.027*cl 0.22 + 0.027*cl t plz 1.25 1.24 + 0.000*cl 1.18 + 0.001*cl 1.31 + -0.001*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl en to pad t plh 2.14 1.47 + 0.013*cl 1.50 + 0.013*cl 1.51 + 0.013*cl t phl 2.92 1.74 + 0.024*cl 1.79 + 0.023*cl 1.83 + 0.023*cl t r 1.35 0.33 + 0.020*cl 0.34 + 0.020*cl 0.29 + 0.021*cl t f 1.59 0.28 + 0.026*cl 0.24 + 0.027*cl 0.22 + 0.027*cl t plz 1.18 1.15 + 0.001*cl 1.19 + 0.000*cl 1.19 + 0.000*cl t phz 0.97 0.97 + 0.000*cl 0.97 + 0.000*cl 0.97 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = stdm80 phot24sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.28 1.36 + 0.018*cl 1.40 + 0.018*cl 1.41 + 0.018*cl t phl 2.32 1.49 + 0.017*cl 1.56 + 0.016*cl 1.59 + 0.015*cl t r 2.33 0.44 + 0.038*cl 0.43 + 0.038*cl 0.41 + 0.038*cl t f 2.01 0.62 + 0.028*cl 0.66 + 0.027*cl 0.65 + 0.027*cl tn to pad t plh 1.98 1.35 + 0.013*cl 1.40 + 0.012*cl 1.42 + 0.012*cl t phl 2.75 1.65 + 0.022*cl 1.73 + 0.021*cl 1.76 + 0.021*cl t r 1.30 0.42 + 0.018*cl 0.43 + 0.017*cl 0.39 + 0.018*cl t f 1.47 0.32 + 0.023*cl 0.32 + 0.023*cl 0.31 + 0.023*cl t plz 1.25 1.24 + 0.000*cl 1.24 + 0.000*cl 1.25 + 0.000*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl en to pad t plh 2.14 1.52 + 0.013*cl 1.56 + 0.012*cl 1.58 + 0.012*cl t phl 2.92 1.80 + 0.022*cl 1.93 + 0.021*cl 1.94 + 0.020*cl t r 1.29 0.40 + 0.018*cl 0.43 + 0.017*cl 0.41 + 0.018*cl t f 1.47 0.33 + 0.023*cl 0.30 + 0.023*cl 0.31 + 0.023*cl t plz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.17 + 0.000*cl t phz 0.97 0.97 + 0.000*cl 0.97 + 0.000*cl 0.97 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-97 STD80/stdm80 bi-directional buffers cell list cell name function description STD80 pbadyz 5v open-drain bi-directional buffers pbaudyz 5v open-drain bi-directional buffers with pull-up pbatyz 5v tri-state bi-directional buffers pbadtyz 5v tri-state bi-directional buffers with pull-down pbautyz 5v tri-state bi-directional buffers with pull-up plbadyz 3.3v interface open-drain bi-directional buffers plbaudyz 3.3v interface open-drain bi-directional buffers with pull-up plbatyz 3.3v interface tri-state bi-directional buffers plbadtyz 3.3v interface tri-state bi-directional buffers with pull-down plbautyz 3.3v interface tri-state bi-directional buffers with pull-up stdm80 pbadyz 3.3v open-drain bi-directional buffers pbaudyz 3.3v open-drain bi-directional buffers with pull-up pbatyz 3.3v tri-state bi-directional buffers pbadtyz 3.3v tri-state bi-directional buffers with pull-down pbautyz 3.3v tri-state bi-directional buffers with pull-up phbadyz 5v interface open-drain bi-directional buffers phbaudyz 5v interface open-drain bi-directional buffers with pull-up phbatyz 5v interface tri-state bi-directional buffers phbadtyz 5v interface tri-state bi-directional buffers with pull-down phbautyz 5v interface tri-state bi-directional buffers with pull-up
STD80/stdm80 4-98 sec asic pvbadyz/pvbaudyz open drain bi-directional buffers pvbadyz pvbaudyz pa d tn en y po pi pa d tn en y po pi pvbatyz/pvbadtyz/pvbautyz tri-state bi-directional buffers pvbatyz pvbadtyz pvbautyz pa d a tn en y po pi pa d a tn en y po pi pa d a tn en y po pi
sec asic 4-99 STD80/stdm80 input clock drivers cell list cell name function description STD80 psckdc(2/4/8/12) 5v cmos level input clock drivers psckdcd(2/4/8/12) 5v cmos level input clock drivers with pull-down psckdcu(2/4/8/12) 5v cmos level input clock drivers with pull-up psckdl(2/4/8/12) 5v ttl schmitt trigger level input clock drivers psckdld(2/4/8/12) 5v ttl schmitt trigger level input clock drivers with pull-down psckdlu(2/4/8/12) 5v ttl schmitt trigger level input clock drivers with pull-up psckds(2/4/8/12) 5v cmos schmitt trigger level input clock drivers psckdsd(2/4/8/12) 5v cmos schmitt trigger level input clock drivers with pull-down psckdsu(2/4/8/12) 5v cmos schmitt trigger level input clock drivers with pull-up psckdt(2/4/8/12) 5v ttl level input clock drivers psckdtd(2/4/8/12) 5v ttl level input clock drivers with pull-down psckdtu(2/4/8/12) 5v ttl level input clock drivers with pull-up stdm80 psckdc(2/4/6/8) 3.3v cmos level input clock drivers psckdcd(2/4/6/8) 3.3v cmos level input clock drivers with pull-down psckdcu(2/4/6/8) 3.3v cmos level input clock drivers with pull-up psckds(2/4/6/8) 3.3v cmos schmitt trigger level input clock drivers psckdsd(2/4/6/8) 3.3v cmos schmitt trigger level input clock drivers with pull-down psckdsu(2/4/6/8) 3.3v cmos schmitt trigger level input clock drivers with pull-up
STD80/stdm80 4-100 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers cell availability logic symbol library 5v operation 3.3v operation STD80 psckdc(2/4/8/12) psckdcd(2/4/8/12) psckdcu(2/4/8/12) C stdm80 C psckdc(2/4/6/8) psckdcd(2/4/6/8) psckdcu(2/4/6/8) y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot STD80 pi psckdc(2/4/8/12) 1.6 psckdcd(2/4/8/12) 1.6 psckdcu(2/4/8/12) 1.6 stdm80 pi psckdc(2/4/6/8) 1.9 psckdcd(2/4/6/8) 1.9 psckdcu(2/4/6/8) 1.9 STD80/stdm80 psckdcy/psckdcdy/psckdcuy 1.0
sec asic 4-101 STD80/stdm80 psckdcy/psckdcdy/psckdcuy cmos level input clock drivers STD80 psckdc2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.70 0.24 + 0.005*sl 0.24 + 0.006*sl 0.24 + 0.005*sl t phl 0.64 0.22 + 0.005*sl 0.22 + 0.005*sl 0.22 + 0.005*sl t r 1.08 0.09 + 0.012*sl 0.08 + 0.012*sl 0.07 + 0.012*sl t f 0.84 0.08 + 0.009*sl 0.07 + 0.009*sl 0.06 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdc4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.003*sl 0.30 + 0.003*sl 0.30 + 0.003*sl t phl 0.68 0.27 + 0.003*sl 0.27 + 0.003*sl 0.27 + 0.002*sl t r 1.07 0.10 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl t f 0.83 0.09 + 0.004*sl 0.08 + 0.005*sl 0.07 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdc8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.32 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t phl 0.73 0.32 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t r 1.06 0.10 + 0.003*sl 0.09 + 0.003*sl 0.08 + 0.003*sl t f 0.82 0.10 + 0.002*sl 0.09 + 0.002*sl 0.07 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdc12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.82 0.38 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t phl 0.78 0.37 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t r 1.06 0.13 + 0.002*sl 0.11 + 0.002*sl 0.10 + 0.002*sl t f 0.84 0.12 + 0.001*sl 0.11 + 0.001*sl 0.10 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
STD80/stdm80 4-102 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers STD80 psckdcd2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.71 0.26 + 0.005*sl 0.25 + 0.006*sl 0.26 + 0.005*sl t phl 0.64 0.22 + 0.005*sl 0.23 + 0.005*sl 0.22 + 0.005*sl t r 1.08 0.09 + 0.012*sl 0.08 + 0.012*sl 0.08 + 0.012*sl t f 0.84 0.08 + 0.009*sl 0.07 + 0.009*sl 0.06 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdcd4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.31 + 0.003*sl 0.31 + 0.003*sl 0.31 + 0.003*sl t phl 0.68 0.27 + 0.003*sl 0.27 + 0.003*sl 0.28 + 0.002*sl t r 1.07 0.10 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl t f 0.83 0.09 + 0.004*sl 0.08 + 0.005*sl 0.07 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdcd8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.33 + 0.001*sl 0.33 + 0.001*sl 0.33 + 0.001*sl t phl 0.73 0.32 + 0.001*sl 0.33 + 0.001*sl 0.32 + 0.001*sl t r 1.06 0.10 + 0.003*sl 0.09 + 0.003*sl 0.08 + 0.003*sl t f 0.83 0.10 + 0.002*sl 0.08 + 0.002*sl 0.08 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdcd12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.83 0.39 + 0.001*sl 0.39 + 0.001*sl 0.39 + 0.001*sl t phl 0.79 0.38 + 0.001*sl 0.38 + 0.001*sl 0.39 + 0.001*sl t r 1.06 0.12 + 0.002*sl 0.11 + 0.002*sl 0.10 + 0.002*sl t f 0.84 0.13 + 0.001*sl 0.11 + 0.001*sl 0.10 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-103 STD80/stdm80 psckdcy/psckdcdy/psckdcuy cmos level input clock drivers STD80 psckdcu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.70 0.25 + 0.005*sl 0.25 + 0.005*sl 0.25 + 0.005*sl t phl 0.64 0.23 + 0.005*sl 0.23 + 0.005*sl 0.23 + 0.005*sl t r 1.08 0.09 + 0.012*sl 0.08 + 0.012*sl 0.08 + 0.012*sl t f 0.84 0.08 + 0.009*sl 0.07 + 0.009*sl 0.06 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdcu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.003*sl 0.30 + 0.003*sl 0.30 + 0.003*sl t phl 0.69 0.27 + 0.003*sl 0.28 + 0.002*sl 0.27 + 0.003*sl t r 1.07 0.10 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl t f 0.83 0.09 + 0.004*sl 0.08 + 0.005*sl 0.07 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdcu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.77 0.32 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t phl 0.74 0.33 + 0.001*sl 0.33 + 0.001*sl 0.33 + 0.001*sl t r 1.06 0.10 + 0.003*sl 0.09 + 0.003*sl 0.08 + 0.003*sl t f 0.83 0.10 + 0.002*sl 0.08 + 0.002*sl 0.08 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdcu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.82 0.38 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t phl 0.79 0.38 + 0.001*sl 0.39 + 0.001*sl 0.39 + 0.001*sl t r 1.06 0.13 + 0.002*sl 0.11 + 0.002*sl 0.10 + 0.002*sl t f 0.83 0.12 + 0.001*sl 0.11 + 0.001*sl 0.09 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
STD80/stdm80 4-104 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers stdm80 psckdc2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.14 0.36 + 0.004*sl 0.29 + 0.004*sl 0.30 + 0.004*sl t phl 0.95 0.31 + 0.003*sl 0.31 + 0.003*sl 0.32 + 0.003*sl t r 1.97 0.14 + 0.009*sl 0.11 + 0.010*sl 0.14 + 0.009*sl t f 1.31 0.11 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = stdm80 psckdc4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.26 0.42 + 0.002*sl 0.42 + 0.002*sl 0.43 + 0.002*sl t phl 1.05 0.41 + 0.002*sl 0.42 + 0.002*sl 0.41 + 0.002*sl t r 1.96 0.16 + 0.005*sl 0.14 + 0.005*sl 0.13 + 0.005*sl t f 1.32 0.13 + 0.003*sl 0.15 + 0.003*sl 0.13 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = stdm80 psckdc6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.23 0.39 + 0.001*sl 0.38 + 0.001*sl 0.39 + 0.001*sl t phl 1.05 0.41 + 0.001*sl 0.41 + 0.001*sl 0.41 + 0.001*sl t r 1.96 0.14 + 0.003*sl 0.11 + 0.003*sl 0.14 + 0.003*sl t f 1.33 0.23 + 0.002*sl 0.17 + 0.002*sl 0.14 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = stdm80 psckdc8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.28 0.44 + 0.001*sl 0.44 + 0.001*sl 0.44 + 0.001*sl t phl 1.13 0.49 + 0.001*sl 0.49 + 0.001*sl 0.49 + 0.001*sl t r 1.95 0.15 + 0.002*sl 0.14 + 0.002*sl 0.14 + 0.002*sl t f 1.33 0.17 + 0.001*sl 0.12 + 0.002*sl 0.15 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
sec asic 4-105 STD80/stdm80 psckdcy/psckdcdy/psckdcuy cmos level input clock drivers stdm80 psckdcd2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.17 0.32 + 0.004*sl 0.31 + 0.004*sl 0.33 + 0.004*sl t phl 0.96 0.32 + 0.003*sl 0.32 + 0.003*sl 0.32 + 0.003*sl t r 1.97 0.14 + 0.009*sl 0.10 + 0.010*sl 0.15 + 0.009*sl t f 1.30 0.12 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = stdm80 psckdcd4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.27 0.43 + 0.002*sl 0.43 + 0.002*sl 0.44 + 0.002*sl t phl 1.06 0.42 + 0.002*sl 0.42 + 0.002*sl 0.42 + 0.002*sl t r 1.96 0.16 + 0.005*sl 0.15 + 0.005*sl 0.14 + 0.005*sl t f 1.31 0.18 + 0.003*sl 0.12 + 0.003*sl 0.11 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = stdm80 psckdcd6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.24 0.40 + 0.001*sl 0.40 + 0.001*sl 0.41 + 0.001*sl t phl 1.08 0.43 + 0.001*sl 0.43 + 0.001*sl 0.44 + 0.001*sl t r 1.96 0.15 + 0.003*sl 0.11 + 0.003*sl 0.13 + 0.003*sl t f 1.32 0.15 + 0.002*sl 0.10 + 0.002*sl 0.12 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = stdm80 psckdcd8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.28 0.44 + 0.001*sl 0.44 + 0.001*sl 0.44 + 0.001*sl t phl 1.13 0.49 + 0.001*sl 0.50 + 0.001*sl 0.50 + 0.001*sl t r 1.96 0.16 + 0.002*sl 0.12 + 0.002*sl 0.15 + 0.002*sl t f 1.31 0.16 + 0.001*sl 0.16 + 0.001*sl 0.10 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
STD80/stdm80 4-106 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers stdm80 psckdcu2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.15 0.29 + 0.004*sl 0.30 + 0.004*sl 0.31 + 0.004*sl t phl 0.96 0.32 + 0.003*sl 0.32 + 0.003*sl 0.32 + 0.003*sl t r 1.98 0.14 + 0.009*sl 0.11 + 0.010*sl 0.16 + 0.009*sl t f 1.31 0.11 + 0.006*sl 0.10 + 0.006*sl 0.09 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = stdm80 psckdcu4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.26 0.42 + 0.002*sl 0.43 + 0.002*sl 0.43 + 0.002*sl t phl 1.06 0.42 + 0.002*sl 0.42 + 0.002*sl 0.42 + 0.002*sl t r 1.96 0.18 + 0.005*sl 0.13 + 0.005*sl 0.14 + 0.005*sl t f 1.31 0.15 + 0.003*sl 0.13 + 0.003*sl 0.11 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = stdm80 psckdcu6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.23 0.39 + 0.001*sl 0.39 + 0.001*sl 0.39 + 0.001*sl t phl 1.07 0.43 + 0.001*sl 0.43 + 0.001*sl 0.44 + 0.001*sl t r 1.96 0.16 + 0.003*sl 0.13 + 0.003*sl 0.13 + 0.003*sl t f 1.32 0.16 + 0.002*sl 0.13 + 0.002*sl 0.13 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = stdm80 psckdcu8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.28 0.45 + 0.001*sl 0.45 + 0.001*sl 0.45 + 0.001*sl t phl 1.13 0.49 + 0.001*sl 0.49 + 0.001*sl 0.50 + 0.001*sl t r 1.95 0.15 + 0.002*sl 0.15 + 0.002*sl 0.13 + 0.002*sl t f 1.32 0.17 + 0.001*sl 0.12 + 0.002*sl 0.13 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
sec asic 4-107 STD80/stdm80 psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers cell availability logic symbol library 5v operation 3.3v operation STD80 psckdl(2/4/8/12) psckdld(2/4/8/12) psckdlu(2/4/8/12) C stdm80 C C y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot STD80 pi psckdl(2/4/8/12) 1.6 psckdld(2/4/8/12) 1.6 psckdlu(2/4/8/12) 1.6 STD80/stdm80 psckdly/psckdldy/psckdluy 1.0
STD80/stdm80 4-108 sec asic psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers STD80 psckdl2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.90 0.44 + 0.006*sl 0.45 + 0.005*sl 0.45 + 0.005*sl t phl 2.28 1.75 + 0.007*sl 1.79 + 0.006*sl 1.82 + 0.006*sl t r 1.09 0.13 + 0.012*sl 0.11 + 0.012*sl 0.10 + 0.012*sl t f 1.24 0.58 + 0.008*sl 0.58 + 0.008*sl 0.57 + 0.008*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdl4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.99 0.53 + 0.003*sl 0.54 + 0.003*sl 0.54 + 0.003*sl t phl 2.94 2.36 + 0.004*sl 2.42 + 0.003*sl 2.46 + 0.003*sl t r 1.10 0.16 + 0.006*sl 0.15 + 0.006*sl 0.13 + 0.006*sl t f 1.48 0.83 + 0.004*sl 0.84 + 0.004*sl 0.84 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdl8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.92 0.47 + 0.001*sl 0.47 + 0.001*sl 0.47 + 0.001*sl t phl 2.51 1.99 + 0.002*sl 2.03 + 0.001*sl 2.06 + 0.001*sl t r 1.08 0.14 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.36 0.73 + 0.002*sl 0.73 + 0.002*sl 0.72 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdl12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.01 0.55 + 0.001*sl 0.56 + 0.001*sl 0.57 + 0.001*sl t phl 3.22 2.65 + 0.001*sl 2.70 + 0.001*sl 2.74 + 0.001*sl t r 1.10 0.18 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.64 1.02 + 0.001*sl 1.03 + 0.001*sl 1.03 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-109 STD80/stdm80 psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers STD80 psckdld2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.91 0.46 + 0.006*sl 0.46 + 0.005*sl 0.46 + 0.005*sl t phl 2.29 1.76 + 0.007*sl 1.80 + 0.006*sl 1.83 + 0.006*sl t r 1.09 0.13 + 0.012*sl 0.11 + 0.012*sl 0.10 + 0.012*sl t f 1.24 0.58 + 0.008*sl 0.58 + 0.008*sl 0.57 + 0.008*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdld4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 1.00 0.54 + 0.003*sl 0.55 + 0.003*sl 0.55 + 0.003*sl t phl 2.95 2.38 + 0.004*sl 2.43 + 0.003*sl 2.47 + 0.003*sl t r 1.10 0.16 + 0.006*sl 0.15 + 0.006*sl 0.13 + 0.006*sl t f 1.48 0.83 + 0.004*sl 0.85 + 0.004*sl 0.83 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdld8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.93 0.48 + 0.001*sl 0.48 + 0.001*sl 0.48 + 0.001*sl t phl 2.53 2.00 + 0.002*sl 2.05 + 0.001*sl 2.08 + 0.001*sl t r 1.08 0.14 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.36 0.73 + 0.002*sl 0.73 + 0.002*sl 0.72 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdld12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.02 0.57 + 0.001*sl 0.58 + 0.001*sl 0.58 + 0.001*sl t phl 3.24 2.67 + 0.001*sl 2.72 + 0.001*sl 2.76 + 0.001*sl t r 1.10 0.19 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.64 1.01 + 0.001*sl 1.03 + 0.001*sl 1.03 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
STD80/stdm80 4-110 sec asic psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers STD80 psckdlu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.90 0.45 + 0.005*sl 0.45 + 0.005*sl 0.45 + 0.005*sl t phl 2.32 1.78 + 0.007*sl 1.83 + 0.006*sl 1.85 + 0.006*sl t r 1.09 0.13 + 0.012*sl 0.11 + 0.012*sl 0.10 + 0.012*sl t f 1.24 0.59 + 0.008*sl 0.58 + 0.008*sl 0.57 + 0.008*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdlu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.99 0.53 + 0.003*sl 0.54 + 0.003*sl 0.54 + 0.003*sl t phl 2.98 2.41 + 0.004*sl 2.47 + 0.003*sl 2.50 + 0.003*sl t r 1.10 0.16 + 0.006*sl 0.15 + 0.006*sl 0.13 + 0.006*sl t f 1.48 0.83 + 0.004*sl 0.85 + 0.004*sl 0.84 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdlu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.92 0.47 + 0.001*sl 0.47 + 0.001*sl 0.47 + 0.001*sl t phl 2.55 2.03 + 0.002*sl 2.07 + 0.001*sl 2.10 + 0.001*sl t r 1.08 0.14 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.36 0.74 + 0.002*sl 0.74 + 0.002*sl 0.72 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdlu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.01 0.56 + 0.001*sl 0.57 + 0.001*sl 0.57 + 0.001*sl t phl 3.27 2.70 + 0.001*sl 2.75 + 0.001*sl 2.79 + 0.001*sl t r 1.10 0.18 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.65 1.02 + 0.001*sl 1.04 + 0.001*sl 1.04 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-111 STD80/stdm80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers cell availability logic symbol library 5v operation 3.3v operation STD80 psckds(2/4/8/12) psckdsd(2/4/8/12) psckdsu(2/4/8/12) C stdm80 C psckds(2/4/6/8) psckdsd(2/4/6/8) psckdsu(2/4/6/8) y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot STD80 pi psckds(2/4/8/12) 1.6 psckdsd(2/4/8/12) 1.6 psckdsu(2/4/8/12) 1.6 stdm80 pi psckds(2/4/6/8) 1.9 psckdsd(2/4/6/8) 1.9 psckdsu(2/4/6/8) 1.9 STD80/stdm80 psckdsy/psckdsdy/psckdsuy 1.0
STD80/stdm80 4-112 sec asic psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers STD80 psckds2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.77 0.32 + 0.005*sl 0.31 + 0.006*sl 0.32 + 0.005*sl t phl 1.00 0.55 + 0.006*sl 0.57 + 0.005*sl 0.58 + 0.005*sl t r 1.09 0.11 + 0.012*sl 0.10 + 0.012*sl 0.09 + 0.012*sl t f 0.93 0.22 + 0.009*sl 0.21 + 0.009*sl 0.19 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckds4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.88 0.43 + 0.003*sl 0.43 + 0.003*sl 0.43 + 0.003*sl t phl 1.27 0.79 + 0.003*sl 0.82 + 0.003*sl 0.84 + 0.003*sl t r 1.09 0.15 + 0.006*sl 0.13 + 0.006*sl 0.12 + 0.006*sl t f 1.02 0.35 + 0.004*sl 0.34 + 0.004*sl 0.32 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckds8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.92 0.48 + 0.001*sl 0.48 + 0.001*sl 0.48 + 0.001*sl t phl 1.31 0.84 + 0.002*sl 0.87 + 0.001*sl 0.89 + 0.001*sl t r 1.08 0.15 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.02 0.35 + 0.002*sl 0.34 + 0.002*sl 0.33 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckds12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.04 0.59 + 0.001*sl 0.59 + 0.001*sl 0.60 + 0.001*sl t phl 1.58 1.08 + 0.001*sl 1.12 + 0.001*sl 1.14 + 0.001*sl t r 1.11 0.19 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.14 0.49 + 0.001*sl 0.48 + 0.001*sl 0.47 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-113 STD80/stdm80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers STD80 psckdsd2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.33 + 0.005*sl 0.33 + 0.005*sl 0.33 + 0.005*sl t phl 1.01 0.56 + 0.006*sl 0.58 + 0.005*sl 0.59 + 0.005*sl t r 1.09 0.11 + 0.012*sl 0.10 + 0.012*sl 0.09 + 0.012*sl t f 0.93 0.22 + 0.009*sl 0.21 + 0.009*sl 0.19 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdsd4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.89 0.44 + 0.003*sl 0.44 + 0.003*sl 0.44 + 0.003*sl t phl 1.28 0.81 + 0.003*sl 0.83 + 0.003*sl 0.85 + 0.003*sl t r 1.09 0.15 + 0.006*sl 0.13 + 0.006*sl 0.12 + 0.006*sl t f 1.02 0.35 + 0.004*sl 0.34 + 0.004*sl 0.33 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdsd8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.94 0.49 + 0.001*sl 0.50 + 0.001*sl 0.50 + 0.001*sl t phl 1.33 0.85 + 0.001*sl 0.88 + 0.001*sl 0.90 + 0.001*sl t r 1.08 0.15 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.02 0.35 + 0.002*sl 0.34 + 0.002*sl 0.33 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdsd12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.06 0.60 + 0.001*sl 0.61 + 0.001*sl 0.61 + 0.001*sl t phl 1.59 1.10 + 0.001*sl 1.13 + 0.001*sl 1.15 + 0.001*sl t r 1.11 0.19 + 0.002*sl 0.18 + 0.002*sl 0.16 + 0.002*sl t f 1.14 0.48 + 0.001*sl 0.48 + 0.001*sl 0.47 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
STD80/stdm80 4-114 sec asic psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers STD80 psckdsu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.32 + 0.005*sl 0.33 + 0.005*sl 0.32 + 0.005*sl t phl 1.01 0.56 + 0.006*sl 0.58 + 0.005*sl 0.58 + 0.005*sl t r 1.09 0.11 + 0.012*sl 0.10 + 0.012*sl 0.09 + 0.012*sl t f 0.93 0.22 + 0.009*sl 0.21 + 0.009*sl 0.20 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdsu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.89 0.44 + 0.003*sl 0.44 + 0.003*sl 0.44 + 0.003*sl t phl 1.28 0.80 + 0.003*sl 0.83 + 0.003*sl 0.85 + 0.003*sl t r 1.09 0.15 + 0.006*sl 0.13 + 0.006*sl 0.12 + 0.006*sl t f 1.03 0.35 + 0.004*sl 0.34 + 0.004*sl 0.33 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdsu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.93 0.48 + 0.001*sl 0.49 + 0.001*sl 0.49 + 0.001*sl t phl 1.33 0.85 + 0.002*sl 0.88 + 0.001*sl 0.90 + 0.001*sl t r 1.08 0.15 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.02 0.35 + 0.002*sl 0.34 + 0.002*sl 0.33 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdsu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.05 0.59 + 0.001*sl 0.60 + 0.001*sl 0.61 + 0.001*sl t phl 1.60 1.10 + 0.001*sl 1.13 + 0.001*sl 1.16 + 0.001*sl t r 1.11 0.19 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.14 0.49 + 0.001*sl 0.48 + 0.001*sl 0.47 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-115 STD80/stdm80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers stdm80 psckds2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.48 0.62 + 0.004*sl 0.63 + 0.004*sl 0.63 + 0.004*sl t phl 2.03 1.28 + 0.004*sl 1.34 + 0.004*sl 1.37 + 0.003*sl t r 2.01 0.23 + 0.009*sl 0.21 + 0.009*sl 0.18 + 0.009*sl t f 1.52 0.39 + 0.006*sl 0.39 + 0.006*sl 0.42 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = stdm80 psckds4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.73 0.84 + 0.002*sl 0.87 + 0.002*sl 0.88 + 0.002*sl t phl 2.70 1.86 + 0.002*sl 1.93 + 0.002*sl 1.99 + 0.002*sl t r 2.07 0.32 + 0.005*sl 0.31 + 0.005*sl 0.30 + 0.005*sl t f 1.74 0.62 + 0.003*sl 0.64 + 0.003*sl 0.64 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = stdm80 psckds6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.62 0.75 + 0.002*sl 0.77 + 0.001*sl 0.78 + 0.001*sl t phl 2.37 1.57 + 0.001*sl 1.64 + 0.001*sl 1.68 + 0.001*sl t r 2.03 0.28 + 0.003*sl 0.23 + 0.003*sl 0.24 + 0.003*sl t f 1.61 0.51 + 0.002*sl 0.48 + 0.002*sl 0.49 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = stdm80 psckds8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.74 0.86 + 0.001*sl 0.89 + 0.001*sl 0.90 + 0.001*sl t phl 2.70 1.87 + 0.001*sl 1.94 + 0.001*sl 2.00 + 0.001*sl t r 2.06 0.30 + 0.002*sl 0.31 + 0.002*sl 0.28 + 0.002*sl t f 1.72 0.61 + 0.001*sl 0.63 + 0.001*sl 0.63 + 0.001*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
STD80/stdm80 4-116 sec asic psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers stdm80 psckdsd2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.50 0.63 + 0.004*sl 0.65 + 0.004*sl 0.65 + 0.004*sl t phl 2.05 1.30 + 0.004*sl 1.35 + 0.004*sl 1.39 + 0.003*sl t r 2.01 0.23 + 0.009*sl 0.21 + 0.009*sl 0.18 + 0.009*sl t f 1.51 0.39 + 0.006*sl 0.42 + 0.006*sl 0.37 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = stdm80 psckdsd4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.74 0.85 + 0.002*sl 0.89 + 0.002*sl 0.91 + 0.002*sl t phl 2.72 1.88 + 0.002*sl 1.96 + 0.002*sl 2.01 + 0.002*sl t r 2.07 0.31 + 0.005*sl 0.35 + 0.004*sl 0.28 + 0.005*sl t f 1.73 0.63 + 0.003*sl 0.63 + 0.003*sl 0.62 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = stdm80 psckdsd6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.63 0.76 + 0.002*sl 0.78 + 0.001*sl 0.79 + 0.001*sl t phl 2.39 1.59 + 0.001*sl 1.66 + 0.001*sl 1.70 + 0.001*sl t r 2.03 0.26 + 0.003*sl 0.25 + 0.003*sl 0.22 + 0.003*sl t f 1.62 0.51 + 0.002*sl 0.48 + 0.002*sl 0.50 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = stdm80 psckdsd8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.76 0.87 + 0.001*sl 0.90 + 0.001*sl 0.91 + 0.001*sl t phl 2.72 1.88 + 0.001*sl 1.96 + 0.001*sl 2.02 + 0.001*sl t r 2.06 0.32 + 0.002*sl 0.31 + 0.002*sl 0.26 + 0.002*sl t f 1.72 0.64 + 0.001*sl 0.62 + 0.001*sl 0.60 + 0.001*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
sec asic 4-117 STD80/stdm80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers stdm80 psckdsu2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.49 0.63 + 0.004*sl 0.64 + 0.004*sl 0.65 + 0.004*sl t phl 2.05 1.29 + 0.004*sl 1.35 + 0.004*sl 1.38 + 0.003*sl t r 2.01 0.24 + 0.009*sl 0.19 + 0.009*sl 0.20 + 0.009*sl t f 1.52 0.40 + 0.006*sl 0.41 + 0.006*sl 0.39 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = stdm80 psckdsu4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.74 0.85 + 0.002*sl 0.88 + 0.002*sl 0.89 + 0.002*sl t phl 2.72 1.88 + 0.002*sl 1.96 + 0.002*sl 2.02 + 0.002*sl t r 2.06 0.32 + 0.005*sl 0.32 + 0.005*sl 0.28 + 0.005*sl t f 1.74 0.64 + 0.003*sl 0.65 + 0.003*sl 0.63 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = stdm80 psckdsu6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.63 0.76 + 0.002*sl 0.78 + 0.001*sl 0.78 + 0.001*sl t phl 2.38 1.59 + 0.001*sl 1.66 + 0.001*sl 1.70 + 0.001*sl t r 2.03 0.28 + 0.003*sl 0.23 + 0.003*sl 0.24 + 0.003*sl t f 1.61 0.51 + 0.002*sl 0.49 + 0.002*sl 0.49 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = stdm80 psckdsu8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.75 0.87 + 0.001*sl 0.90 + 0.001*sl 0.91 + 0.001*sl t phl 2.72 1.88 + 0.001*sl 1.96 + 0.001*sl 2.02 + 0.001*sl t r 2.06 0.30 + 0.002*sl 0.30 + 0.002*sl 0.27 + 0.002*sl t f 1.72 0.62 + 0.001*sl 0.63 + 0.001*sl 0.61 + 0.001*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
STD80/stdm80 4-118 sec asic psckdty/psckdtdy/psckdtuy ttl level input clock drivers cell availability logic symbol library 5v operation 3.3v operation STD80 psckdt(2/4/8/12) psckdtd(2/4/8/12) psckdtu(2/4/8/12) C stdm80 C C y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot STD80 pi psckdt(2/4/8/12) 1.6 psckdtd(2/4/8/12) 1.6 psckdtu(2/4/8/12) 1.6 STD80/stdm80 psckdty/psckdtdy/psckdtuy 1.0
sec asic 4-119 STD80/stdm80 psckdty/psckdtdy/psckdtuy ttl level input clock drivers STD80 psckdt2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.68 0.23 + 0.005*sl 0.22 + 0.006*sl 0.22 + 0.006*sl t phl 0.90 0.45 + 0.006*sl 0.47 + 0.005*sl 0.48 + 0.005*sl t r 1.08 0.08 + 0.012*sl 0.08 + 0.012*sl 0.07 + 0.012*sl t f 0.92 0.20 + 0.009*sl 0.19 + 0.009*sl 0.18 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdt4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.72 0.27 + 0.003*sl 0.27 + 0.003*sl 0.27 + 0.003*sl t phl 1.13 0.65 + 0.003*sl 0.68 + 0.003*sl 0.70 + 0.003*sl t r 1.06 0.08 + 0.006*sl 0.07 + 0.006*sl 0.07 + 0.006*sl t f 1.01 0.33 + 0.004*sl 0.31 + 0.004*sl 0.31 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdt8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.001*sl 0.30 + 0.001*sl 0.30 + 0.001*sl t phl 1.17 0.69 + 0.001*sl 0.72 + 0.001*sl 0.74 + 0.001*sl t r 1.05 0.08 + 0.003*sl 0.07 + 0.003*sl 0.07 + 0.003*sl t f 1.00 0.32 + 0.002*sl 0.32 + 0.002*sl 0.30 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdt12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.34 + 0.001*sl 0.34 + 0.001*sl 0.34 + 0.001*sl t phl 1.39 0.89 + 0.001*sl 0.92 + 0.001*sl 0.95 + 0.001*sl t r 1.05 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl t f 1.12 0.45 + 0.001*sl 0.45 + 0.001*sl 0.44 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
STD80/stdm80 4-120 sec asic psckdty/psckdtdy/psckdtuy ttl level input clock drivers STD80 psckdtd2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.70 0.24 + 0.005*sl 0.24 + 0.006*sl 0.24 + 0.005*sl t phl 0.91 0.46 + 0.006*sl 0.48 + 0.005*sl 0.49 + 0.005*sl t r 1.08 0.08 + 0.012*sl 0.08 + 0.012*sl 0.07 + 0.012*sl t f 0.92 0.20 + 0.009*sl 0.20 + 0.009*sl 0.18 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdtd4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.73 0.28 + 0.003*sl 0.28 + 0.003*sl 0.28 + 0.003*sl t phl 1.14 0.66 + 0.003*sl 0.69 + 0.003*sl 0.71 + 0.003*sl t r 1.06 0.08 + 0.006*sl 0.07 + 0.006*sl 0.07 + 0.006*sl t f 1.01 0.33 + 0.004*sl 0.32 + 0.004*sl 0.31 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdtd8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.32 + 0.001*sl 0.31 + 0.001*sl 0.31 + 0.001*sl t phl 1.18 0.70 + 0.002*sl 0.73 + 0.001*sl 0.75 + 0.001*sl t r 1.05 0.09 + 0.003*sl 0.07 + 0.003*sl 0.07 + 0.003*sl t f 1.00 0.32 + 0.002*sl 0.32 + 0.002*sl 0.31 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdtd12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.80 0.35 + 0.001*sl 0.35 + 0.001*sl 0.35 + 0.001*sl t phl 1.40 0.90 + 0.001*sl 0.93 + 0.001*sl 0.95 + 0.001*sl t r 1.05 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl t f 1.12 0.45 + 0.001*sl 0.45 + 0.001*sl 0.43 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-121 STD80/stdm80 psckdty/psckdtdy/psckdtuy ttl level input clock drivers STD80 psckdtu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.68 0.23 + 0.005*sl 0.22 + 0.006*sl 0.23 + 0.005*sl t phl 0.91 0.46 + 0.006*sl 0.48 + 0.005*sl 0.49 + 0.005*sl t r 1.08 0.08 + 0.012*sl 0.07 + 0.012*sl 0.07 + 0.012*sl t f 0.92 0.20 + 0.009*sl 0.19 + 0.009*sl 0.19 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = STD80 psckdtu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.72 0.27 + 0.003*sl 0.27 + 0.003*sl 0.27 + 0.003*sl t phl 1.14 0.66 + 0.003*sl 0.69 + 0.003*sl 0.71 + 0.003*sl t r 1.06 0.08 + 0.006*sl 0.07 + 0.006*sl 0.07 + 0.006*sl t f 1.01 0.33 + 0.004*sl 0.32 + 0.004*sl 0.31 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = STD80 psckdtu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.001*sl 0.30 + 0.001*sl 0.30 + 0.001*sl t phl 1.18 0.70 + 0.002*sl 0.73 + 0.001*sl 0.75 + 0.001*sl t r 1.05 0.08 + 0.003*sl 0.07 + 0.003*sl 0.07 + 0.003*sl t f 1.01 0.33 + 0.002*sl 0.32 + 0.002*sl 0.31 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = STD80 psckdtu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.34 + 0.001*sl 0.34 + 0.001*sl 0.34 + 0.001*sl t phl 1.40 0.90 + 0.001*sl 0.93 + 0.001*sl 0.96 + 0.001*sl t r 1.05 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl t f 1.12 0.46 + 0.001*sl 0.45 + 0.001*sl 0.44 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
STD80/stdm80 4-122 sec asic oscillators cell list cell name function description STD80/stdm80 psosck1 oscillator cell with enable (~ 100khz) psosck2 oscillator cell with enable (100k ~ 1mhz) psosck16 oscillator cell with enable and resistor (~ 100khz) psosck26 oscillator cell with enable and resistor (100k ~ 1mhz) psoscm1 oscillator cell with enable (1m ~ 10mhz) psoscm2 oscillator cell with enable (10m ~ 30mhz) psoscm3 oscillator cell with enable (30m ~ 60mhz) psoscm4 oscillator cell with enable (60m ~ 80mhz) psoscm5 oscillator cell with enable (80m ~ 100mhz) psoscm6 oscillator cell with enable (50m ~ 100mhz) psoscm16 oscillator cell with enable and resistor (1m ~ 10mhz) psoscm26 oscillator cell with enable and resistor (10m ~ 30mhz) psoscm36 oscillator cell with enable and resistor (30m ~ 60mhz) psoscm46 oscillator cell with enable and resistor (60m ~ 80mhz) psoscm56 oscillator cell with enable and resistor (80m ~ 100mhz) psoscm66 oscillator cell with enable and resistor (50m ~ 100mhz)
sec asic 4-123 STD80/stdm80 psosck(1/2) psosck(16/26) oscillator cell with enable oscillator cell with enable and resistor logic symbol truth table cell data pada e pady yn 0001 0110 1001 1101 input load (sl) i/o slots psosck1/2 psosck1/2 e 2.6 2.0 yn e pa da pa dy logic symbol truth table cell data pada e pady yn 0001 0110 1001 1101 input load (sl) i/o slots psosck(16/26) psosck(16/26) e 2.6 2.0 yn e pa da pa dy
STD80/stdm80 4-124 sec asic psosck(1/2) oscillator cell with enable STD80 psosck1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 259.38 0.46 + 5.178*cl 0.49 + 5.178*cl 0.44 + 5.179*cl t phl 349.70 0.50 + 6.984*cl 0.50 + 6.984*cl 0.50 + 6.984*cl t r 582.75 0.55 + 11.644*cl 0.62 + 11.643*cl 0.77 + 11.641*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 259.45 0.53 + 5.178*cl 0.48 + 5.179*cl 0.57 + 5.178*cl t phl 349.81 0.61 + 6.984*cl 0.61 + 6.984*cl 0.61 + 6.984*cl t r 582.75 0.59 + 11.643*cl 0.54 + 11.644*cl 0.70 + 11.642*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.60 0.60 + 0.179*sl 0.61 + 0.178*sl 0.60 + 0.178*sl t phl 0.53 0.53 + 0.130*sl 0.54 + 0.129*sl 0.54 + 0.129*sl t r 0.26 0.26 + 0.082*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.068*sl 0.17 + 0.071*sl 0.17 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.72 0.72 + 0.178*sl 0.72 + 0.178*sl 0.72 + 0.178*sl t phl 0.60 0.60 + 0.130*sl 0.61 + 0.129*sl 0.61 + 0.129*sl t r 0.25 0.25 + 0.084*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.069*sl 0.17 + 0.071*sl 0.17 + 0.072*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-125 STD80/stdm80 psosck(1/2) oscillator cell with enable STD80 psosck2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 26.32 0.43 + 0.518*cl 0.42 + 0.518*cl 0.43 + 0.518*cl t phl 35.38 0.46 + 0.698*cl 0.46 + 0.698*cl 0.46 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.54 + 1.543*cl 0.51 + 1.543*cl 0.54 + 1.543*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 26.40 0.50 + 0.518*cl 0.50 + 0.518*cl 0.51 + 0.518*cl t phl 35.48 0.56 + 0.698*cl 0.56 + 0.698*cl 0.56 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.52 + 1.543*cl 0.59 + 1.542*cl 0.53 + 1.543*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.54 0.54 + 0.022*sl 0.54 + 0.021*sl 0.55 + 0.020*sl t phl 0.46 0.46 + 0.015*sl 0.46 + 0.014*sl 0.47 + 0.013*sl t r 0.20 0.20 + 0.008*sl 0.20 + 0.009*sl 0.19 + 0.010*sl t f 0.14 0.14 + 0.007*sl 0.14 + 0.007*sl 0.13 + 0.008*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.66 0.66 + 0.020*sl 0.66 + 0.020*sl 0.66 + 0.020*sl t phl 0.54 0.54 + 0.015*sl 0.54 + 0.014*sl 0.54 + 0.013*sl t r 0.18 0.18 + 0.009*sl 0.18 + 0.010*sl 0.18 + 0.010*sl t f 0.13 0.13 + 0.007*sl 0.13 + 0.007*sl 0.13 + 0.008*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-126 sec asic psosck(1/2) oscillator cell with enable stdm80 psosck1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 259.38 0.46 + 5.178*cl 0.49 + 5.178*cl 0.44 + 5.179*cl t phl 349.70 0.50 + 6.984*cl 0.50 + 6.984*cl 0.50 + 6.984*cl t r 582.75 0.55 + 11.644*cl 0.62 + 11.643*cl 0.77 + 11.641*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 259.45 0.53 + 5.178*cl 0.48 + 5.179*cl 0.57 + 5.178*cl t phl 349.81 0.61 + 6.984*cl 0.61 + 6.984*cl 0.61 + 6.984*cl t r 582.75 0.59 + 11.643*cl 0.54 + 11.644*cl 0.70 + 11.642*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.60 0.60 + 0.179*sl 0.61 + 0.178*sl 0.60 + 0.178*sl t phl 0.53 0.53 + 0.130*sl 0.54 + 0.129*sl 0.54 + 0.129*sl t r 0.26 0.26 + 0.082*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.068*sl 0.17 + 0.071*sl 0.17 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.72 0.72 + 0.178*sl 0.72 + 0.178*sl 0.72 + 0.178*sl t phl 0.60 0.60 + 0.130*sl 0.61 + 0.129*sl 0.61 + 0.129*sl t r 0.25 0.25 + 0.084*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.069*sl 0.17 + 0.071*sl 0.17 + 0.072*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-127 STD80/stdm80 psosck(1/2) oscillator cell with enable stdm80 psosck2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 26.32 0.43 + 0.518*cl 0.42 + 0.518*cl 0.43 + 0.518*cl t phl 35.38 0.46 + 0.698*cl 0.46 + 0.698*cl 0.46 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.54 + 1.543*cl 0.51 + 1.543*cl 0.54 + 1.543*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 26.40 0.50 + 0.518*cl 0.50 + 0.518*cl 0.51 + 0.518*cl t phl 35.48 0.56 + 0.698*cl 0.56 + 0.698*cl 0.56 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.52 + 1.543*cl 0.59 + 1.542*cl 0.53 + 1.543*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.54 0.54 + 0.022*sl 0.54 + 0.021*sl 0.55 + 0.020*sl t phl 0.46 0.46 + 0.015*sl 0.46 + 0.014*sl 0.47 + 0.013*sl t r 0.20 0.20 + 0.008*sl 0.20 + 0.009*sl 0.19 + 0.010*sl t f 0.14 0.14 + 0.007*sl 0.14 + 0.007*sl 0.13 + 0.008*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.66 0.66 + 0.020*sl 0.66 + 0.020*sl 0.66 + 0.020*sl t phl 0.54 0.54 + 0.015*sl 0.54 + 0.014*sl 0.54 + 0.013*sl t r 0.18 0.18 + 0.009*sl 0.18 + 0.010*sl 0.18 + 0.010*sl t f 0.13 0.13 + 0.007*sl 0.13 + 0.007*sl 0.13 + 0.008*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-128 sec asic psosck(16/26) oscillator cell with enable and resistor STD80 psosck16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 259.38 0.46 + 5.178*cl 0.49 + 5.178*cl 0.44 + 5.179*cl t phl 349.70 0.50 + 6.984*cl 0.50 + 6.984*cl 0.50 + 6.984*cl t r 582.75 0.55 + 11.644*cl 0.62 + 11.643*cl 0.77 + 11.641*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 259.45 0.53 + 5.178*cl 0.48 + 5.179*cl 0.57 + 5.178*cl t phl 349.81 0.61 + 6.984*cl 0.61 + 6.984*cl 0.61 + 6.984*cl t r 582.75 0.59 + 11.643*cl 0.54 + 11.644*cl 0.70 + 11.642*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.60 0.60 + 0.179*sl 0.61 + 0.178*sl 0.60 + 0.178*sl t phl 0.53 0.53 + 0.130*sl 0.54 + 0.129*sl 0.54 + 0.129*sl t r 0.26 0.26 + 0.082*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.068*sl 0.17 + 0.071*sl 0.17 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.72 0.72 + 0.178*sl 0.72 + 0.178*sl 0.72 + 0.178*sl t phl 0.60 0.60 + 0.130*sl 0.61 + 0.129*sl 0.61 + 0.129*sl t r 0.25 0.25 + 0.084*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.069*sl 0.17 + 0.071*sl 0.17 + 0.072*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-129 STD80/stdm80 psosck(16/26) oscillator cell with enable and resistor STD80 psosck26 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 26.32 0.43 + 0.518*cl 0.42 + 0.518*cl 0.43 + 0.518*cl t phl 35.38 0.46 + 0.698*cl 0.46 + 0.698*cl 0.46 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.54 + 1.543*cl 0.51 + 1.543*cl 0.54 + 1.543*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 26.40 0.50 + 0.518*cl 0.50 + 0.518*cl 0.51 + 0.518*cl t phl 35.48 0.56 + 0.698*cl 0.56 + 0.698*cl 0.56 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.52 + 1.543*cl 0.59 + 1.542*cl 0.53 + 1.543*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.54 0.54 + 0.022*sl 0.54 + 0.021*sl 0.55 + 0.020*sl t phl 0.46 0.46 + 0.015*sl 0.46 + 0.014*sl 0.47 + 0.013*sl t r 0.20 0.20 + 0.008*sl 0.20 + 0.009*sl 0.19 + 0.010*sl t f 0.14 0.14 + 0.007*sl 0.14 + 0.007*sl 0.13 + 0.008*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.66 0.66 + 0.020*sl 0.66 + 0.020*sl 0.66 + 0.020*sl t phl 0.54 0.54 + 0.015*sl 0.54 + 0.014*sl 0.54 + 0.013*sl t r 0.18 0.18 + 0.009*sl 0.18 + 0.010*sl 0.18 + 0.010*sl t f 0.13 0.13 + 0.007*sl 0.13 + 0.007*sl 0.13 + 0.008*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-130 sec asic psosck(16/26) oscillator cell with enable and resistor stdm80 psosck16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 259.38 0.46 + 5.178*cl 0.49 + 5.178*cl 0.44 + 5.179*cl t phl 349.70 0.50 + 6.984*cl 0.50 + 6.984*cl 0.50 + 6.984*cl t r 582.75 0.55 + 11.644*cl 0.62 + 11.643*cl 0.77 + 11.641*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 259.45 0.53 + 5.178*cl 0.48 + 5.179*cl 0.57 + 5.178*cl t phl 349.81 0.61 + 6.984*cl 0.61 + 6.984*cl 0.61 + 6.984*cl t r 582.75 0.59 + 11.643*cl 0.54 + 11.644*cl 0.70 + 11.642*cl t f 772.14 0.82 + 15.426*cl 0.55 + 15.430*cl 0.83 + 15.427*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.60 0.60 + 0.179*sl 0.61 + 0.178*sl 0.60 + 0.178*sl t phl 0.53 0.53 + 0.130*sl 0.54 + 0.129*sl 0.54 + 0.129*sl t r 0.26 0.26 + 0.082*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.068*sl 0.17 + 0.071*sl 0.17 + 0.072*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.72 0.72 + 0.178*sl 0.72 + 0.178*sl 0.72 + 0.178*sl t phl 0.60 0.60 + 0.130*sl 0.61 + 0.129*sl 0.61 + 0.129*sl t r 0.25 0.25 + 0.084*sl 0.25 + 0.086*sl 0.24 + 0.087*sl t f 0.18 0.18 + 0.069*sl 0.17 + 0.071*sl 0.17 + 0.072*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-131 STD80/stdm80 psosck(16/26) oscillator cell with enable and resistor stdm80 psosck26 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 26.32 0.43 + 0.518*cl 0.42 + 0.518*cl 0.43 + 0.518*cl t phl 35.38 0.46 + 0.698*cl 0.46 + 0.698*cl 0.46 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.54 + 1.543*cl 0.51 + 1.543*cl 0.54 + 1.543*cl path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* e to pady t plh 26.40 0.50 + 0.518*cl 0.50 + 0.518*cl 0.51 + 0.518*cl t phl 35.48 0.56 + 0.698*cl 0.56 + 0.698*cl 0.56 + 0.698*cl t r 58.61 0.39 + 1.164*cl 0.40 + 1.164*cl 0.37 + 1.165*cl t f 77.67 0.52 + 1.543*cl 0.59 + 1.542*cl 0.53 + 1.543*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.54 0.54 + 0.022*sl 0.54 + 0.021*sl 0.55 + 0.020*sl t phl 0.46 0.46 + 0.015*sl 0.46 + 0.014*sl 0.47 + 0.013*sl t r 0.20 0.20 + 0.008*sl 0.20 + 0.009*sl 0.19 + 0.010*sl t f 0.14 0.14 + 0.007*sl 0.14 + 0.007*sl 0.13 + 0.008*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* e to yn t plh 0.66 0.66 + 0.020*sl 0.66 + 0.020*sl 0.66 + 0.020*sl t phl 0.54 0.54 + 0.015*sl 0.54 + 0.014*sl 0.54 + 0.013*sl t r 0.18 0.18 + 0.009*sl 0.18 + 0.010*sl 0.18 + 0.010*sl t f 0.13 0.13 + 0.007*sl 0.13 + 0.007*sl 0.13 + 0.008*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-132 sec asic psoscm(1/2/3/4/5/6) psoscm(16/26/36/46/56/66) oscillator cell with enable oscillator cell with enable and resistor logic symbol truth table sec tester standard real application cell data pada e pady yn 0011 0111 10xx 1100 pada e pady yn 0011 0111 1011 1100 input load (sl) i/o slots psoscm(1/2/3/4/5/6) psoscm(1/2/3/4/5/6) e 2.6 2.0 yn e pa da pa dy logic symbol truth table sec tester standard real application cell data pada e pady yn 0011 0111 10xx 1100 pada e pady yn 0011 0111 1011 1100 input load (sl) i/o slots psoscm (16/26/36/46/56/66) psoscm (16/26/36/46/56/66) e 2.6 2.0 yn e pa da pa dy
sec asic 4-133 STD80/stdm80 psoscm(1/2/3/4/5/6) oscillators with enable STD80 psoscm1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = STD80 psoscm2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-134 sec asic psoscm(1/2/3/4/5/6) oscillators with enable STD80 psoscm3 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 1.41 0.12 + 0.026*cl 0.12 + 0.026*cl 0.12 + 0.026*cl t phl 1.87 0.12 + 0.035*cl 0.12 + 0.035*cl 0.12 + 0.035*cl t r 3.00 0.10 + 0.058*cl 0.09 + 0.058*cl 0.09 + 0.058*cl t f 3.96 0.11 + 0.077*cl 0.11 + 0.077*cl 0.10 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.19 0.19 + 0.003*sl 0.19 + 0.003*sl 0.20 + 0.002*sl t phl 0.21 0.21 + 0.002*sl 0.21 + 0.003*sl 0.21 + 0.003*sl t r 0.10 0.10 + 0.002*sl 0.10 + 0.002*sl 0.10 + 0.002*sl t f 0.08 0.08 + 0.004*sl 0.09 + 0.001*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = STD80 psoscm4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.76 0.12 + 0.013*cl 0.12 + 0.013*cl 0.12 + 0.013*cl t phl 0.99 0.12 + 0.017*cl 0.11 + 0.017*cl 0.12 + 0.017*cl t r 1.54 0.10 + 0.029*cl 0.09 + 0.029*cl 0.09 + 0.029*cl t f 2.02 0.10 + 0.038*cl 0.10 + 0.038*cl 0.10 + 0.038*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.002*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.000*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.09 0.09 + 0.001*sl 0.09 + 0.001*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-135 STD80/stdm80 psoscm(1/2/3/4/5/6) oscillators with enable STD80 psoscm5 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.55 0.11 + 0.009*cl 0.11 + 0.009*cl 0.12 + 0.009*cl t phl 0.70 0.12 + 0.012*cl 0.12 + 0.012*cl 0.11 + 0.012*cl t r 1.06 0.10 + 0.019*cl 0.09 + 0.019*cl 0.09 + 0.019*cl t f 1.38 0.10 + 0.025*cl 0.10 + 0.026*cl 0.09 + 0.026*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.001*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.10 0.10 + 0.001*sl 0.10 + 0.000*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = STD80 psoscm6 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.44 0.11 + 0.007*cl 0.11 + 0.007*cl 0.12 + 0.006*cl t phl 0.55 0.11 + 0.009*cl 0.12 + 0.009*cl 0.11 + 0.009*cl t r 0.82 0.11 + 0.014*cl 0.11 + 0.014*cl 0.09 + 0.014*cl t f 1.06 0.11 + 0.019*cl 0.10 + 0.019*cl 0.10 + 0.019*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.25 0.25 + 0.001*sl 0.25 + 0.001*sl 0.25 + 0.001*sl t phl 0.26 0.26 + 0.001*sl 0.26 + 0.001*sl 0.26 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.001*sl 0.11 + 0.001*sl t f 0.11 0.11 + 0.000*sl 0.11 + 0.001*sl 0.10 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-136 sec asic psoscm(1/2/3/4/5/6) oscillators with enable stdm80 psoscm1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 psoscm2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-137 STD80/stdm80 psoscm(1/2/3/4/5/6) oscillators with enable stdm80 psoscm3 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 1.41 0.12 + 0.026*cl 0.12 + 0.026*cl 0.12 + 0.026*cl t phl 1.87 0.12 + 0.035*cl 0.12 + 0.035*cl 0.12 + 0.035*cl t r 3.00 0.10 + 0.058*cl 0.09 + 0.058*cl 0.09 + 0.058*cl t f 3.96 0.11 + 0.077*cl 0.11 + 0.077*cl 0.10 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.19 0.19 + 0.003*sl 0.19 + 0.003*sl 0.20 + 0.002*sl t phl 0.21 0.21 + 0.002*sl 0.21 + 0.003*sl 0.21 + 0.003*sl t r 0.10 0.10 + 0.002*sl 0.10 + 0.002*sl 0.10 + 0.002*sl t f 0.08 0.08 + 0.004*sl 0.09 + 0.001*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 psoscm4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.76 0.12 + 0.013*cl 0.12 + 0.013*cl 0.12 + 0.013*cl t phl 0.99 0.12 + 0.017*cl 0.11 + 0.017*cl 0.12 + 0.017*cl t r 1.54 0.10 + 0.029*cl 0.09 + 0.029*cl 0.09 + 0.029*cl t f 2.02 0.10 + 0.038*cl 0.10 + 0.038*cl 0.10 + 0.038*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.002*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.000*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.09 0.09 + 0.001*sl 0.09 + 0.001*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-138 sec asic psoscm(1/2/3/4/5/6) oscillators with enable stdm80 psoscm5 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.55 0.11 + 0.009*cl 0.11 + 0.009*cl 0.12 + 0.009*cl t phl 0.70 0.12 + 0.012*cl 0.12 + 0.012*cl 0.11 + 0.012*cl t r 1.06 0.10 + 0.019*cl 0.09 + 0.019*cl 0.09 + 0.019*cl t f 1.38 0.10 + 0.025*cl 0.10 + 0.026*cl 0.09 + 0.026*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.001*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.10 0.10 + 0.001*sl 0.10 + 0.000*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 psoscm6 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.44 0.11 + 0.007*cl 0.11 + 0.007*cl 0.12 + 0.006*cl t phl 0.55 0.11 + 0.009*cl 0.12 + 0.009*cl 0.11 + 0.009*cl t r 0.82 0.11 + 0.014*cl 0.11 + 0.014*cl 0.09 + 0.014*cl t f 1.06 0.11 + 0.019*cl 0.10 + 0.019*cl 0.10 + 0.019*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.25 0.25 + 0.001*sl 0.25 + 0.001*sl 0.25 + 0.001*sl t phl 0.26 0.26 + 0.001*sl 0.26 + 0.001*sl 0.26 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.001*sl 0.11 + 0.001*sl t f 0.11 0.11 + 0.000*sl 0.11 + 0.001*sl 0.10 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-139 STD80/stdm80 psoscm(16/26/36/46/56/66) oscillators with enable and resistor STD80 psoscm16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = STD80 psoscm26 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-140 sec asic psoscm(16/26/36/46/56/66) oscillators with enable and resistor STD80 psoscm36 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 1.41 0.12 + 0.026*cl 0.12 + 0.026*cl 0.12 + 0.026*cl t phl 1.87 0.12 + 0.035*cl 0.12 + 0.035*cl 0.12 + 0.035*cl t r 3.00 0.10 + 0.058*cl 0.09 + 0.058*cl 0.09 + 0.058*cl t f 3.96 0.11 + 0.077*cl 0.11 + 0.077*cl 0.10 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.19 0.19 + 0.003*sl 0.19 + 0.003*sl 0.20 + 0.002*sl t phl 0.21 0.21 + 0.002*sl 0.21 + 0.003*sl 0.21 + 0.003*sl t r 0.10 0.10 + 0.002*sl 0.10 + 0.002*sl 0.10 + 0.002*sl t f 0.08 0.08 + 0.004*sl 0.09 + 0.001*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = STD80 psoscm46 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.76 0.12 + 0.013*cl 0.12 + 0.013*cl 0.12 + 0.013*cl t phl 0.99 0.12 + 0.017*cl 0.11 + 0.017*cl 0.12 + 0.017*cl t r 1.54 0.10 + 0.029*cl 0.09 + 0.029*cl 0.09 + 0.029*cl t f 2.02 0.10 + 0.038*cl 0.10 + 0.038*cl 0.10 + 0.038*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.002*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.000*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.09 0.09 + 0.001*sl 0.09 + 0.001*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-141 STD80/stdm80 psoscm(16/26/36/46/56/66) oscillators with enable and resistor STD80 psoscm56 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.55 0.11 + 0.009*cl 0.11 + 0.009*cl 0.12 + 0.009*cl t phl 0.70 0.12 + 0.012*cl 0.12 + 0.012*cl 0.11 + 0.012*cl t r 1.06 0.10 + 0.019*cl 0.09 + 0.019*cl 0.09 + 0.019*cl t f 1.38 0.10 + 0.025*cl 0.10 + 0.026*cl 0.09 + 0.026*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.001*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.10 0.10 + 0.001*sl 0.10 + 0.000*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = STD80 psoscm66 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.44 0.11 + 0.007*cl 0.11 + 0.007*cl 0.12 + 0.006*cl t phl 0.55 0.11 + 0.009*cl 0.12 + 0.009*cl 0.11 + 0.009*cl t r 0.82 0.11 + 0.014*cl 0.11 + 0.014*cl 0.09 + 0.014*cl t f 1.06 0.11 + 0.019*cl 0.10 + 0.019*cl 0.10 + 0.019*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.25 0.25 + 0.001*sl 0.25 + 0.001*sl 0.25 + 0.001*sl t phl 0.26 0.26 + 0.001*sl 0.26 + 0.001*sl 0.26 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.001*sl 0.11 + 0.001*sl t f 0.11 0.11 + 0.000*sl 0.11 + 0.001*sl 0.10 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-142 sec asic psoscm(16/26/36/46/56/66) oscillators with enable and resistor stdm80 psoscm16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 psoscm26 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.24 + 0.004*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.09 + 0.002*sl 0.09 + 0.002*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-143 STD80/stdm80 psoscm(16/26/36/46/56/66) oscillators with enable and resistor stdm80 psoscm36 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 1.41 0.12 + 0.026*cl 0.12 + 0.026*cl 0.12 + 0.026*cl t phl 1.87 0.12 + 0.035*cl 0.12 + 0.035*cl 0.12 + 0.035*cl t r 3.00 0.10 + 0.058*cl 0.09 + 0.058*cl 0.09 + 0.058*cl t f 3.96 0.11 + 0.077*cl 0.11 + 0.077*cl 0.10 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.19 0.19 + 0.003*sl 0.19 + 0.003*sl 0.20 + 0.002*sl t phl 0.21 0.21 + 0.002*sl 0.21 + 0.003*sl 0.21 + 0.003*sl t r 0.10 0.10 + 0.002*sl 0.10 + 0.002*sl 0.10 + 0.002*sl t f 0.08 0.08 + 0.004*sl 0.09 + 0.001*sl 0.08 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 psoscm46 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.76 0.12 + 0.013*cl 0.12 + 0.013*cl 0.12 + 0.013*cl t phl 0.99 0.12 + 0.017*cl 0.11 + 0.017*cl 0.12 + 0.017*cl t r 1.54 0.10 + 0.029*cl 0.09 + 0.029*cl 0.09 + 0.029*cl t f 2.02 0.10 + 0.038*cl 0.10 + 0.038*cl 0.10 + 0.038*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.002*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.000*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.09 0.09 + 0.001*sl 0.09 + 0.001*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
STD80/stdm80 4-144 sec asic psoscm(16/26/36/46/56/66) oscillators with enable and resistor stdm80 psoscm56 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.55 0.11 + 0.009*cl 0.11 + 0.009*cl 0.12 + 0.009*cl t phl 0.70 0.12 + 0.012*cl 0.12 + 0.012*cl 0.11 + 0.012*cl t r 1.06 0.10 + 0.019*cl 0.09 + 0.019*cl 0.09 + 0.019*cl t f 1.38 0.10 + 0.025*cl 0.10 + 0.026*cl 0.09 + 0.026*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.001*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.000*sl 0.10 + 0.001*sl t f 0.10 0.10 + 0.001*sl 0.10 + 0.000*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = stdm80 psoscm66 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.44 0.11 + 0.007*cl 0.11 + 0.007*cl 0.12 + 0.006*cl t phl 0.55 0.11 + 0.009*cl 0.12 + 0.009*cl 0.11 + 0.009*cl t r 0.82 0.11 + 0.014*cl 0.11 + 0.014*cl 0.09 + 0.014*cl t f 1.06 0.11 + 0.019*cl 0.10 + 0.019*cl 0.10 + 0.019*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = g [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.25 0.25 + 0.001*sl 0.25 + 0.001*sl 0.25 + 0.001*sl t phl 0.26 0.26 + 0.001*sl 0.26 + 0.001*sl 0.26 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.001*sl 0.11 + 0.001*sl t f 0.11 0.11 + 0.000*sl 0.11 + 0.001*sl 0.10 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-145 STD80/stdm80 pci buffers overview pci buffers are designed for pci local bus application which is an industry-standard, high-performance 32- or 64-bit bus architecture. sec asic supports 5v and 3.3v signalling environment pci bi-directional buffers including a universal buffer. the universal buffer requires a select control (en3v) signal. en3v pin should be tied to the voltage detector output directly. features C high performance C low cost C easy use C longevity: both 5v and 3.3v signalling environments speci?ed. general description the pci buffers signalling environment is controlled by en3v pin which is logically low in a 5v operation and logically high in a 3.3v operation. if you use a voltage detector cell with the pci buffer, you have to connect this en3v pin to vdet (voltage detector) output. do not use a level shifter buffer (plscb). cell list cell name function description STD80 psipcia 5v pci input buffer psopcia 5v pci output buffer plsipcia internal 5v/external 3.3v pci input buffer plsopcia internal 5v/external 3.3v pci output buffer psipciau universal pci input buffer psopciau universal pci output buffer stdm80 psipcia3 3.3v pci input buffer psopcia3 3.3v pci output buffer phsipcia internal 3.3v/external 5v pci input buffer phsopcia internal 3.3v/external 5v pci output buffer psipciau universal pci input buffer psopciau universal pci output buffer
STD80/stdm80 4-146 sec asic pci buffers electrical characteristics sec asic guarantees pci buffers electrical characteristics under all conditions (v cc = 3.6v, temp. = 0 c ~ v cc = 3.0v, temp. = 125 c). 5v dc speci?cations 5v ac speci?cations notes: 1. equation a :i oh = 11.9 * (v out C 5.25) * (v out + 2.45) for v cc > v out > 3.1v 2. equation b :i ol = 78.5 * v out * (4.4 C v out ) for 0v < v out < 0.71v 3. the minimum slew rate (slowest signal edge) is guaranteed. the maximum slew rate (fastest signal edge) is a guideline, and rise and fall times faster than the maximum can occur. designers should ensure that signal integrity modelling includes the potential for rise and fall times faster than the maximum shown in the table. symbol parameter condition min max unit v cc supply voltage 4.75 5.25 v v il input low voltage C0.5 0.8 v ih input high voltage 2.0 v cc + 0.5 i il input low leakage current v in = 0.5 C70 m a i ih input high leakage current v in = 2.7 70 v ol output low voltage i out = 3ma, 6ma 0.55 v v oh output high voltage i out = e2ma 2.4 c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 c idsel idsel pin capacitance 8 l pin pin inductance 20 nh symbol parameter condition min max unit i oh (ac) switching current high 0 < v out 1.4 e44 ma 1.4 < v out < 2.4 e44 (vout e 1.4) / 0.024 3.1 < v out < v cc eqt?n a 1 (test point) v out = 3.1 e142 i ol (ac) switching current low v out 3 2.2 95 2.2 > v out > 0.55 v out /0.023 0.71 > v out > 0 eqt?n b 2 (test point) v out = 0.71 206 i cl low clamp current e5 < v in e1 e25 + (v in + 1) / 0.015 slew r 3 output rise slew rate 0.4v to 2.4v load 1 5 v/ns slew f 3 output fall slew rate 2.4v to 0.4v load 1 5
sec asic 4-147 STD80/stdm80 pci buffers 3.3v dc characteristics 3.3v ac characteristics notes: 1. equation c :i oh = (98.0 / v cc ) * (v out C v cc ) * (v out + 0.4v cc ) for v cc > v out > 0.7v 2. equation d :i ol = (256 / v cc ) * v out * (v cc C v out ) for 0v < v out < 0.18v cc 3. the minimum slew rate (slowest signal edge) is guaranteed. the maximum slew rate (fastest signal edge) is a guideline, and rise and fall times faster than the maximum can occur. designers should ensure that signal integrity modelling includes the potential for rise and fall times faster than the maximum shown in the table. symbol parameter condition min max unit v cc supply voltage 3.0 3.6 v v il input low voltage C0.5 0.3v cc v v ih input high voltage 0.5v cc v cc + 0.5 v v ipu input pull-up voltage 0.7v cc v i il input leakage current 0 < v in < v cc 10 m a v ol output low voltage i out = 1500 m a 0.1v cc v v oh output high voltage i out = e500 m a 0.9v cc v c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf l pin pin inductance 20 nh symbol parameter condition min max unit i oh (ac) switching current high 0 < v out 0.3v cc e12v cc ma 0.3v cc < v out < 0.9v cc e17.1 (v cc e v out )ma 0.7v cc < v out < v cc eqt?n c 1 (test point) v out = 0.7v cc e32v cc ma i ol (ac) switching current low v cc > v out 3 0.6v cc 16v cc ma 0.6v cc > v out > 0.1v cc 26.7v out ma 0.18v cc > v out > 0 eqt?n d 2 (test point) v out = 0.18v cc 38v cc ma i cl low clamp current e3 < v in e1 e25 + (v in + 1) / 0.015 ma i ch high clamp current v cc + 4 > v in 3 v cc + 1 25 + (v in e v cc e 1) / 0.015 ma slew r 3 output rise slew rate 0.2v cc to 0.6v cc load 1 4 v/ns slew f 3 output fall slew rate 0.6v cc to 0.2v cc load 1 4 v/ns
STD80/stdm80 4-148 sec asic psipcia/plsipcia/psipcia3/phsipcia pci input buffers logic symbol input load (sl) STD80 tn en a pi psipcia/plsipcia 1.0 1.6 3.6 1.0 stdm80 tn en a pi psipcia3/phsipcia 1.0 1.6 3.6 1.0 pa d y po pi truth table input truth table output truth table i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z STD80/stdm80 psipcia/plsipcia psipcia3/phsipcia 1.0
sec asic 4-149 STD80/stdm80 psopcia/plsopcia/psopcia3/phsopcia pci output buffers logic symbol input load (sl) STD80 tn en a pi psopcia/plsopcia 1.0 1.6 3.6 1.0 stdm80 tn en a pi psopcia3/phsopcia 1.0 1.6 3.6 1.0 pa d a tn en truth table input truth table output truth table i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z STD80/stdm80 psopcia/plsopcia psopcia3/phsopcia 1.0
STD80/stdm80 4-150 sec asic psipciau universal pci input buffer logic symbol input load (sl) STD80/stdm80 tn en a pi psipciau 1.0 1.6 3.6 1.0 pa d y po pi en3v truth table input truth table output truth table * en3v (active-high) enables the 3.3v mode. i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z STD80/stdm80 psipciau 1.0
sec asic 4-151 STD80/stdm80 psopciau universal pci output buffer logic symbol input load (sl) STD80/stdm80 tn en a pi psopciau 1.0 1.6 3.6 1.0 pa d a tn en en3v truth table input truth table output truth table * en3v (active-high) enables the 3.3v mode. i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z STD80/stdm80 psopciau 1.0
STD80/stdm80 4-152 sec asic pcmcia buffers overview pc card technology is used in a wide variety of products including notebook computers, palmtop computers, pen computers, desktop computers, printers, telephones, medical instruments and others embedded application hosts. for pcmcia interface, sec asic supports various kinds of pcmcia buffers. these pcmcia buffers enable you to C maintain interface conditions and speed independent of battery voltage C allow groups of card interface input buffers to be powered down C use a voltage detector cell C select pull-up/pull-down option (50k/100k/200k, default = 100k). general description all of pcmcia buffers are controlled by s3v5v signal that is logically low in a 5v operation and logically high in a 3.3v operation. if you use a voltage detector cell with a pcmcia buffer, you have to connect the s3v5v pin to vdet (voltage detector) output. logic levels notes: 1. pcmcia input buffer is ttl compatible. 2. pcmcia output buffer has a balanced t r & t f . parameter min max v ih 2.0v v il 0.8v v oh 2.4v v ol 0.5v
sec asic 4-153 STD80/stdm80 pcmcia buffers cell list cell name function description STD80/stdm80 pvic(5/3) 5v/3.3v cmos level pcmcia input buffers pvil(5/3) 5v/3.3v ttl schmitt trigger level pcmcia input buffers pvild(5/3) 5v/3.3v ttl schmitt trigger level pcmcia input buffers with pull-down pvilu(5/3) 5v/3.3v ttl schmitt trigger level pcmcia input buffers with pull-up pvit(5/3) 5v/3.3v ttl level pcmcia input buffers pvitd(5/3) 5v/3.3v ttl level pcmcia input buffers with pull-down pvitu(5/3) 5v/3.3v ttl level pcmcia input buffers with pull-up pvob4(5/3) 5v/3.3v 4ma pcmcia output buffers without src pvob8(5/3) 5v/3.3v 8ma pcmcia output buffers without src pvob12(5/3) 5v/3.3v 12ma pcmcia output buffers without src pvod4(5/3) 5v/3.3v 4ma open-drain pcmcia output buffers without src pvod8(5/3) 5v/3.3v 8ma open-drain pcmcia output buffers without src pvod12(5/3) 5v/3.3v 12ma open-drain pcmcia output buffers without src pvot4(5/3) 5v/3.3v 4ma tri-state pcmcia output buffers without src pvot8(5/3) 5v/3.3v 8ma tri-state pcmcia output buffers without src pvot12(5/3) 5v/3.3v 12ma tri-state pcmcia output buffers without src pvot8sm(5/3) 5v/3.3v 8ma tri-state pcmcia output buffers with src pvot12sm(5/3) 5v/3.3v 12ma tri-state pcmcia output buffers with src pvbtt4(5/3) 5v/3.3v 4ma pcmcia bi-directional buffers without src pvbtt8(5/3) 5v/3.3v 8ma pcmcia bi-directional buffers without src pvbtt12(5/3) 5v/3.3v 12ma pcmcia bi-directional buffers without src pvbtdt8sm(5/3) 5v/3.3v 8ma pcmcia bi-directional buffers with src, pull-down pvbct8sm(5/3) 5v/3.3v 8ma pcmcia bi-directional buffers with src
STD80/stdm80 4-154 sec asic pcmcia buffers naming conventions pcmcia input buffers (pvi a b v) pcmcia output buffers (pvo x y z v) pcmcia bi-directional buffers (pvb a b x y z v) ab c cmos level none no resistor l ttl schmitt trigger level d pull-down resistor s cmos schmitt trigger level u pull-up resistor t ttl level y x 4 4ma drive b normal buffer 8 8ma drive d open-drain buffer 12 12ma drive t tri-state buffer v z 55v none no slew-rate control (fastest) 3 3.3v sm medium slew-rate control sh high slew-rate control
sec asic 4-155 STD80/stdm80 pvic(5/3) cmos level pcmcia input buffers logic symbol pin connection truth table cell availability input output pa d pi y po pa d p i y p o 1110 0x01 1011 5v operation 3.3v operation pvic5 pvic3 y po pi pa d pvil(d/u)(5/3)/pvit(d/u)(5/3) ttl level pcmcia input buffers logic symbol pin connection truth table cell availability input output pa d pi s3v5v y po pa d p i y p o 1110 0x01 1011 5v operation 3.3v operation pvil5 pvil3 pvild5 pvild3 pvilu5 pvilu3 pvit5 pvit3 pvitd5 pvitd3 pvitu5 pvitu3 s3v5v y po pi pa d
STD80/stdm80 4-156 sec asic pvob(4/8/12)(5/3) pcmcia output buffers logic symbol pin connection truth table cell availability input output a s3v5v pa d apad 00 11 5v operation 3.3v operation pvob45 pvob43 pvob85 pvob83 pvob125 pvob123 pa d a s3v5v pvod(4/8/12)(5/3) open drain pcmcia output buffers logic symbol pin connection truth table cell availability input output tn en s3v5v pa d tn en pad 100 0 x hi-z x 1 hi-z 5v operation 3.3v operation pvod45 pvod43 pvod85 pvod83 pvod125 pvod123 pa d s3v5v tn en
sec asic 4-157 STD80/stdm80 pvot(4/8/12)(5/3) tri-state pcmcia output buffers logic symbol pin connection truth table cell availability input output tn en a s3v5v pa d tn en a pad 1000 1011 x 1 x hi-z 0 x x hi-z 5v operation 3.3v operation pvot45 pvot43 pvot85 pvot83 pvot125 pvot123 pa d a s3v5v tn en pvot(8/12)sm(5/3) tri-state pcmcia output buffers logic symbol pin connection truth table cell availability input output tn en a s3v5v pa d tn en a pad 1000 1011 x 1 x hi-z 0 x x hi-z 5v operation 3.3v operation pvot8sm5 pvot8sm3 pvot12sm5 pvot12sm3 pa d a s3v5v tn en
STD80/stdm80 4-158 sec asic pvbtt(4/8/12)(5/3) pcmcia bi-directional buffers logic symbol pin connection cell availability input output tn en a s3v5v pi pa d y po 5v operation 3.3v operation pvbtt45 pvbtt43 pvbtt85 pvbtt83 pvbtt125 pvbtt123 pa d a tn en y po pi s3v5v pvbtdt8sm/pvbct8sm(5/3) pcmcia bi-directional buffers logic symbol pin connection cell availability input output tn en a s3v5v pi pa d y po 5v operation 3.3v operation pvbtdt8sm5 pvbtdt8sm3 pvbct8sm5 pvbct8sm3 pa d a tn en y po pi s3v5v
sec asic 4-159 STD80/stdm80 cardbus i/o buffers overview cardbus i/o buffers have 3.3v operation, 32-bit bus width and 33mhz of transmission speed. the latest version of the pc card standard adds information to improve compatibility with the standard by requiring a card information structure (cis) on every pc card. the standard has also been enhanced to support the following optional features: C low-voltage only operation (3.3v) C hardware direct memory access (dma) C multiple-function cards C industry standard power management interface (apm) C high throughput 32-bit bus mastering interface (cardbus) sec asic supports nine different cardbus i/o buffers. if necessary, a voltage detector cell can be used with them. for maximum ?exibility, cardbus i/o buffers have not only a level shifter but also a pull-up enable control pin. cardbus i/o buffers have only 3.3v electrical speci?cations, however, we can support 5v/3.3v ?exible operation by using of a level shifter. regardless of the i/o voltage, s3v5v pin controls the same input level and output driving current. s3v5v pin should be tied to the voltage detector in a mixed system, or ground in a 3.3v-only system. we can not attribute a level shifter to puen (pull-up enable) pin, because we have only four level shifters. in order to control the puen pin with an internal signal, you should use the level shifter butter (plscb) in a mixed system. for minimizing power consumption, cardbus i/o buffers have a nand type input with a control pin. therefore, the input buffers operate as active-high input buffers. however, if the control pin is in low state, the output y is low and not tri-state. general description the cardbus i/o buffer is controlled by s3v5v signal that is logically low in a 5v operation and logically high in a 3.3v operation. if you use a voltage detector cell with the cardbus i/o buffer, you have to connect this s3v5v pin to vdet (voltage detector) output. do not use a level shifter buffer (plscb). cstschg buffer speci?cation the cstschg pin can be used by the cardbus pc card to remotely power up the system. the design of the cardbus pc cards output buffer and the systems input buffer must ensure no electrical damage results. C an output buffer for cstschg pin never exceed 1ma. C an input buffer for cstschg pin is able to withstand sustained forward bias current of 1ma. cclk speci?cation the electrical characteristics of cclk follows 3.3v signalling of pci local bus speci?cation revision 2.1. refer to the pci buffer electrical characteristics.
STD80/stdm80 4-160 sec asic cardbus i/o buffers cell list cell name function description STD80 plitcbu 3.3v interface universal ttl cardbus input buffer with pull-up plotcbu 3.3v interface tri-state cardbus output buffer with pull-up plotcckcbu 3.3v interface tri-state cardbus output clock driver with pull-up plotcvscbu 3.3v interface tri-state output card voltage sense with pull-up plodcckcbu 3.3v interface open drain cardbus output clock driver with pull-up plbttcbu 3.3v interface tri-state cardbus bi-directional buffer with pull-up plbtcckcbu 3.3v interface cardbus bi-directional clock driver with pull-up plbtcvscbu 3.3v interface tri-state bi-directional card voltage sense with pull-up plbdcckcbu 3.3v interface open drain cardbus bi-directional clock driver with pull-up plscb 3.3v interface level shifter buffer stdm80 pitcbu universal ttl cardbus input buffer with pull-up potcbu tri-state cardbus output buffer with pull-up potcckcbu tri-state cardbus output clock driver with pull-up potcvscbu tri-state output card voltage sense with pull-up podcckcbu open drain cardbus output clock driver with pull-up pbttcbu tri-state cardbus bi-directional buffer with pull-up pbtcckcbu cardbus bi-directional clock driver with pull-up pbtcvscbu tri-state bi-directional card voltage sense with pull-up pbdcckcbu open drain cardbus bi-directional clock driver with pull-up plscb level shifter buffer
sec asic 4-161 STD80/stdm80 cardbus i/o buffers electrical characteristics (normal cardbus interface type buffers) 3.3v dc speci?cations notes: 1. this is determined solely by the maximum current capacity of the v cc pins on the connector. 2. input leakage currents include high-z output leakage for all bi-directional buffers with high-z outputs. ccd1#, ccd2#, cvs1 and cvs2 do not have to meet leakage requirements. 3.3v ac speci?cations note: 1. this does not apply to cclk . minimum and maximum rates are measured with the minimum capacitive load a driver will see (7pf). the values ensure the fastest edge rate will not switch rail-to-rail faster than 3.6ns. symbol parameter condition min max unit v cc supply voltage 3.0 3.6 v v ih input high voltage 0.475v cc v cc + 0.5 v il input low voltage C0.5 0.325v cc v oh output high voltage i out = C150 m a 0.9v cc v ol output low voltage i out = 700 m a 0.1v cc i cc 1 supply current 1 a i il 2 input leakage current 0 < v in < v cc 10 m a symbol parameter condition min max unit t rcb 1 output rise time 0.2v cc C 0.6v cc 0.25 1.0 v/ns t fcb 1 output fall time 0.6v cc C 0.2v cc 0.25 1.0 i cl low clamp current C3 < v in < C1 C25 + (v in + 1) / 0.015 ma i ch high clamp current v cc + 4 > v in > v cc + 1 25 + (v in C v cc C 1) / 0.015
STD80/stdm80 4-162 sec asic pvitcbu universal ttl cardbus input buffer with pull-up cell availability logic symbol library 5v operation 3.3v operation STD80 C plitcbu stdm80 C pitcbu level shifter pa d level shifter y po c s3v5v puen pi truth table * puen (pull-up control pin) is low enable. cell data pad c pi y po 11110 01x01 11011 x0x01 input load (sl) i/o slot cpi 1.0 4.0 1.6
sec asic 4-163 STD80/stdm80 pvotcbu/pvotcckcbu/pvotcvscbu tri-state cardbus output buffers with pull-up cell availability logic symbol plotcbu/plotcckcbu plotcvscbu library 5v operation 3.3v operation STD80 C plotcbu/plotcckcbu/plotcvscbu stdm80 C potcbu/potcckcbu/potcvscbu pa d level shifter level shifter tn en a puen s3v5v pa d level shifter level shifter tn en a puen truth table * puen (pull-up control pin) is low enable. cell data aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z input load (sl) i/o slot a en tn puen 1.0 2.3 1.2 1.2 0.5
STD80/stdm80 4-164 sec asic pvodcckcbu open drain cardbus output clock driver with pull-up cell availability logic symbol library 5v operation 3.3v operation STD80 C plodcckcbu stdm80 C podcckcbu pa d level shifter tn en puen truth table * puen (pull-up control pin) is low enable. cell data en tn pad 010 1 x hi-z x 0 hi-z input load (sl) i/o slot en tn puen 1.0 1.2 1.2 0.5
sec asic 4-165 STD80/stdm80 pvbttcbu/pvbtcckcbu/pvbtcvscbu cardbus bi-directional buffers with pull-up cell availability logic symbol plbttcbu/plbtcckcbu plbtcvscbu library 5v operation 3.3v operation STD80 C plbttcbu/plbtcckcbu/plbtcvscbu stdm80 C podcckcbu pa d level shifter tn en puen level shifter level shifter level shifter pi po c y a s3v5v pa d level shifter tn en puen level shifter level shifter level shifter pi po c y a s3v5v truth table input truth table output truth table * puen (pull-up control pin) is low enable. cell data pad c pi y po 11110 01x01 11011 x0x01 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z input load (sl) i/o slot a en tn puen c pi 1.0 2.3 1.2 1.2 0.5 4.0 1.6
STD80/stdm80 4-166 sec asic pvbdcckcbu open drain cardbus bi-directional clock driver with pull-up cell availability logic symbol library 5v operation 3.3v operation STD80 C plbdcckcbu stdm80 C pbdcckcbu pa d level shifter tn en puen level shifter level shifter pi po c y s3v5v truth table input truth table output truth table * puen (pull-up control pin) is low enable. cell data pad c pi y po 11110 01x01 11011 x0x01 en tn pad 010 1 x hi-z x 0 hi-z input load (sl) i/o slot en tn puen c pi 1.0 1.2 1.2 0.5 4.0 1.6
sec asic 4-167 STD80/stdm80 plscb level shifter buffer cell availability logic symbol library 5v operation 3.3v operation STD80 C plscb stdm80 C plscb x1 z1 z2 x2 truth table cell data xn zn 00 1 (vddxi) 1 (vddxo) input load (sl) i/o slot x1 x2 1.0 2.4 2.4
STD80/stdm80 4-168 sec asic usb (universal serial bus) i/o buffers overview usb i/o buffer consists of a differential input receiver, a differential output driver, two single-ended drivers and two pads. the differential input receiver has 0.8v ~ 2.5v common mode input voltage range and both of the two single-ended receivers have 0.8v and 2.0v as their low and high input threshold voltages, v il , v ih . for low power consumption in a stand-by mode, the stand-by (stbys) pins of two kinds of receivers should be in high state. the differential output drivers has low speed slew rate (losr) pin to select the operation speed and has enl to achieve bi-directional half duplex operation. electrical speci?cations dc electrical characteristics full speed source electrical characteristics parameter symbol condition (notes 1, 2) min max unit supply voltage vdd v bus 4.75 5.25 v supply current high power function i cchpf 500 ma low power function i cclpf 100 uncon?g. function / hub i ccinit 100 suspended device i ccs 500 m a leakage current hi-z state data line leakage i lo 0v < vin < 3.3v C10 10 m a input levels differential input sensitivity v di 0.2 v differential common mode range v cm includes v di range 0.8 2.5 single ended receiver threshold v se 0.8 2.0 output levels static output low v ol rl of 1.5k w to 3.6v 0.3 v static output high v oh rl of 15k w to gnd 2.8 4.0 parameter symbol condition (notes 1, 2, 3) min max unit driver characteristics transition time rise time fall time t r t f notes 5, 6 and figure 1 cl = 50pf cl = 50pf 4.0 4.0 20.0 20.0 ns rise/fall time matching t rem (t r /t f ) 90 110 % output signal crossover voltage v crs 1.3 2.0 v
sec asic 4-169 STD80/stdm80 usb (universal serial bus) i/o buffers low speed source electrical characteristics notes: 1. all voltages are measured from the local ground potential, unless otherwise speci?ed. 2. all timings use a capacitive load (cl) to ground of 50pf, unless otherwise speci?ed. 3. full speed timings have a 1.5k w pull-up to 2.8v on the d+ data line. 4. low speed timings have a 1.5k w pull-up to 2.8v on the de data line. 5. measured from 10% to 90% of the data signal. 6. the rising and falling edges should be smoothly transitioning (monotonic). figure 1: data signal rise and fall time parameter symbol condition (notes 1, 2, 4) min max unit driver characteristics transition time rise time fall time t r t f notes 5, 6 and figure 1 cl = 50pf cl = 350pf cl = 50pf cl = 350pf 75 75 300 300 ns rise/fall time matching t rem (t r /t f ) 80 120 % output signal crossover voltage v crs 1.3 2.0 v c l c l differential data lines 10% 90% 90% 10% rise time fall time t r t f full speed: 4 to 20ns at c l = 50pf low speed: 75ns at c l = 50pf, 300ns at c l = 350pf
STD80/stdm80 4-170 sec asic pbusb/pbusb1 universal serial bus buffer symbol cell structure pbusb = picdr + piser + potfls (+ ndt3) pbusb1 = picdr + piser + potfls1 (+ ndt3) ndt3 input nand tree (soft-macro internal cell) picdr differential receiver piser single-ended receiver potfls tri-state output buffer with low speed potfls1 tri-state output buffer with full speed there only exists pbusb not pbusb1 in the physical db. the division of cell name (pbusb/pbusb1) is caused to notify that one of their component cells, potfls/potfls1 has different ac timing values each other. dp dm stbyd rxd rxdp rxdm txd enl losr stbys pin connection input output bi-direction stbyd stbys txd enl losr rxd rxdp rxdm dp dm
sec asic 4-171 STD80/stdm80 pbusb/pbusb1 universal serial bus buffer ndt3 input nand tree (soft-macro internal cell) symbol pin connection input output a (pi) b c d y (po) a (pi) b c y (po) d picdr differential receiver symbol pin connection input output stbyd dp dm rxd dp dm stbyd rxd
STD80/stdm80 4-172 sec asic pbusb/pbusb1 universal serial bus buffer piser single-ended receiver symbol pin connection input output stbys dp dm rxdp rxdm dp stbys rxdp dm rxdm po tfls/po tfls1 tri-state output buffer with low/full speed symbol pin connection potfls has ac characteristics for low speed, and potfls1 for full speed. input output txd enl losr dp dm txd enl dp losr dm
sec asic 4-173 STD80/stdm80 voltage detector cell list logic symbol * y pin should be connected to s3v5v pin directly. do not use a level shifter buffer (plscb). cell name function description vdet voltage detector reset y pin connection truth table * if i/o supply voltage is 3.3v, output y is high state. input output reset y reset y 00 1 0 (1) *
STD80/stdm80 4-174 sec asic power pads cell list logic symbol cell name function description STD80 vdd power pads vss power pads vdd5i vss5i 5v internal vdd5p vss5p 5v pre-driver vdd5o vss5o 5v output-driver vdd5ip vss5ip 5v internal and pre-driver vdd5oi vss5oi 5v output-driver and internal vdd5op vss5op 5v output-driver and pre-driver vdd5t vss5t 5v total vdd3p vss3p 3.3v pre-driver vdd3o vss3o 3.3v output-driver vdd3op vss3op 3.3v output-driver and pre-driver stdm80 vdd power pads vss power pads vdd3i vss3i 3.3v internal vdd3p vss3p 3.3v pre-driver vdd3o vss3o 3.3v output-driver vdd3ip vss3ip 3.3v internal and pre-driver vdd3oi vss3oi 3.3v output-driver and internal vdd3op vss3op 3.3v output-driver and pre-driver vdd3t vss3t 3.3v total vdd5p vss5p 5v pre-driver vdd5o vss5o 5v output-driver vdd5op vss5op 5v output-driver and pre-driver
memory compilers 5
contents overview .............................................................................................................................. 5-1 memory compilers selection guide..................................................................................... 5-2 crom gen........................................................................................................................... 5-3 drom gen........................................................................................................................... 5-10 spsram gen ...................................................................................................................... 5-17 spsrama gen .................................................................................................................... 5-27 sparam gen....................................................................................................................... 5-39 dpsram gen ...................................................................................................................... 5-48 dpsrama gen.................................................................................................................... 5-59 dparam gen....................................................................................................................... 5-72
memory compilers overview sec asic 5-1 STD80/stdm80 overview this chapter contains information for memory compilers available in STD80/stdm80 cell library. these are complete compilers that consist of various generators to satisfy the requirements of the circuit at hand. each of the ?nal building block, the physical layout, will be implemented as a stand-alone, densely packed, pitch-matched array. using this complex layout generator and adopting state-of-the-art logic and circuit design technique, these memory cells can realize extreme density and performance. in each layout generator, we added an option which makes the aspect ratio of the physical layout selectable so that the asic designers can choose the aspect ratio according to the convenience of the chip level layout. in the STD80/stdm80 cell library, there are 4 groups of memory compilers roms; static rams; register file; fifo. generators each memory compiler is a set of various, parameterized generators. the generators are: ? layout generator : generates an array of custom, pitch-matched leaf cells. ? schematic generator & netlister : extracts a netlist which can be used for both lvs check and functional veri?cation. ? function & timing model generators : for gate level simulation, dynamic/static timing analysis and synthesis ? symbol generator : for schematic capture ? critical path generator & etc : there are many special purpose generators such as critical path generator used for both circuit design and ac timing characterization. advanced design technique all of 0.5 m m cmos standard cell memory compilers adopt very advanced design technique to obtain extremely high performance in terms of both speed and power consumption. below are major techniques. for reducing power consumption minimized bit-line precharge/discharge voltage swing zero static current consuming sense ampliter automatic power down after an access for optimizing and minimizing the read access time size sensitive self-timer delay extremely simple tri-state output circuit flexible aspect ratio the size of a memory cell is de?ned by its number of words (words) and number of bits per word (bpw). but, this size is only a logical size. the physical size of a memory is de?ned by the number of rows (rows) and the number of columns (cols) of its bit cell array. usually, we can't make the bit cell array with words and bpw because the range of words is much larger than the range of bpw. if we make the bit cell array with words and bpw, most of memory layouts will have too tall and too thin aspect ratio. therefore, column decoder and y-mux circuit are included in most of memory cells to adjust the aspect ratio.
memory compilers selection guide memory compilers STD80/stdm80 5-2 sec asic in 0.5 m m cmos standard cell memory compilers, the y-mux type selecting option was added to give the customers freedom selecting aspect ratio of the memory layout. many of the characteristics of a memory cell depend on its y-mux type. so, when you change the y-mux type from one to the other to change the aspect ratio, you have to know that it will change many major characteristics, such as access time, area and power consumption, of the memory. < figure 1. example of y-mux types and aspect ratio > dual banks in some of 0.5 m m cmos standard cell memory compilers is a generator option which detnes the number of bit array banks. this dual bank scheme doubles the maximum capacity of the memory compilers. memory compilers selection guide * under-developed memory group cell name function description rom crom gen contact programmable synchronous rom generator drom gen diffusion programmable synchronous rom generator static ram spsram gen single-port synchronous ram generator C reads and writes at the same edge of clock spsrama gen single-port synchronous ram generator C alternative C reads and writes at different edges of clock sparam gen single-port asynchronous ram generator C fully asynchronous read, wen synchronized write dpsram gen dual-port synchronous ram generator C reads and writes at the same edge of clock dparam* gen dual-port asynchronous ram generator C fully asynchronous read, wen synchronized write dpsrama gen dual-port synchronous ram generator C alternative C reads and writes at different edges of clock register file iriw* 1 read port, 1 write port synchronous register file fifo fifo* synchronous fifo y-mux = 4 y-mux = 8 y-mux = 16
sec asic 5-3 STD80/stdm80 crom gen contact programmable synchronous rom generator logic symbol function description crom gen is a contact programmable synchronous rom. when ck rises, dout [ ] presents data programmed in the location addressed by a [ ]. csn is used to enable/disable the clock. oen is used to enable/disable the data output driver. generators and cell con?gurations crom gen. generates layout, netlist, symbol and functional & timing model of crom. the layout of crom is an automatically generated array of custom, pitch-matched leaf cells. to customize the con?guration of crom, you can give certain values to following four generator parameters: ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y) ? number of banks (ba). the valid range of these parameters is speci?ed in the following table: parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 32 64 128 256 max 1024 2048 4096 8192 step 8 16 32 64 bpw (b) ba = 1 min 1111 max 64 32 16 8 step 1111 ba = 2min2222 max 128 64 32 16 step 1111 ck csn oen dout [bC1:0] cromxmb a [m:0] notes: 1. words (w) is the number of words in crom. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. banks (ba) is the number of banks. 5. m = log 2 w e 1 features ? synchronous operation ? read initiated at rising edge of clock ? static differential operation ? stand-by (power down) mode available ? tri-state output ? low noise output circuit ? programmable with contact layer ? flexible aspect ratio ? optional dual bank capacity ? up to 128k bits capacity ? up to 8k number of words ? up to 128 number of bits per word
STD80/stdm80 5-4 sec asic crom gen contact programmable synchronous rom generator pin descriptions pin capacitance (unit = sl) application notes 1) putting busholders on dout [ ] as you will see in the timing diagrams, dout [ ] is valid only when ck is high. if you want dout [ ] to be stable regardless of ck state, you should put STD80/stdm80 busholder cells on the dout [ ] bus externally. 2) customizing aspect ratio aspect ratio is programmable using low address decoder types. as you can see in the con?guration table, there are up to 4 selections of ymux for the same words and the same bpw crom. you can choose one of them in accordance with your chip level layout preference. larger ymux means fatter and shorter aspect ratio and smaller ymux means thinner and taller aspect ratio. as you can see in the characteristic tables, aspect ratio affects major characteristics of crom, in general, larger ymux crom has faster speed and bigger area than smaller ymux crom. 3) selecting number of banks to enlarge the capacity of crom, we added one more option to choose number of banks. if you want to use larger crom than 64k bit crom, you can select dual bank (ba = 2). you can also select dual bank for smaller one than 64k bit crom. dual bank crom is a little bigger and a little faster than single bank one. (please refer to the characteristic tables.) name i/o description ck i clock serves as the input clock to the memory block. when ck is low the memory is in a precharge state. upon the rising edge, an access cycle begins. csn i chip select negative acts as the memory enable signal for selections of multiple blocks on a common clock. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur, conversely, if low only then may a read access occur. csn may not change during ck is high. oen i output enable negative controls the output drivers from driven to tri-state condition. oen may not change during ck is high. a [ ] i address selects the location to be accessed. a [ ] may not change during ck is high. dout [ ] o during a read access, data word programmed will be presented to the data out ports. dout [ ] is tri-statable. when ck is high, csn is low and oen is low, only then, dout [ ] drives a certain value. otherwise, dout [ ] keeps hi-z state. ck csn oen a dout ymux 4 ymux 8 ymux 16 ymux 32 1-bank 5.8 1.8 2.2 1.7 4.0 8.7 18.0 37.0 2-bank 11.5 3.7 4.4 1.7 4.0 8.7 18.0 37.0
sec asic 5-5 STD80/stdm80 crom gen contact programmable synchronous rom generator block diagrams < 1-bank > < 2-bank > rom core y dec. & sense amp address buffer control logic out driver x dec. word dout [bC1:0] oen a [m:0] ck csn line drv. & rom core address buffer control logic x dec. word dout [bC1:(bC1)/2] line drv. & (left) word line drv. rom core dout [{(bC1)/2C1}:0] (right) oen a [m:0] ck csn y dec. & sense amp (left) out driver (left) y dec. & sense amp (right) out driver (right)
STD80/stdm80 5-6 sec asic crom gen contact programmable synchronous rom generator characteristic reference table STD80 stdm80 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing requirements & delay (typical process, 5v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 2.60 2.60 3.00 3.00 3.90 3.90 minckh minimum clock pulse width high 4.90 4.90 5.90 5.90 7.80 7.80 t as address setup time 0.40 0.40 0.60 0.60 1.00 1.00 t ah address hold time 0 0 1.40 1.40 1.70 1.70 t cs csn setup time 0.38 0.38 0.38 0.38 0.38 0.38 t ch csn hold time 000000 t os oen setup time 000000 t oh oen hold time 1.80 1.80 1.90 1.90 2.10 1.90 t acc access time 3.10 3.10 3.50 3.50 4.20 4.20 t da deaccess time 1.90 1.90 1.90 1.90 1.90 1.90 size ( m m) width 466 595 757 886 1329 1458 height 443 443 638 638 1028 1028 power ( m w/mhz) power_ck (normal mode: csn low) 1283 2700 6475 power_csn (stand-by mode: csn high) 45 71 121 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing requirements & delay (typical process, 3.3v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 3.60 3.60 4.20 4.20 5.50 5.50 minckh minimum clock pulse width high 7.10 7.10 8.50 8.50 11.40 11.40 t as address setup time 0.40 0.40 0.70 0.70 1.40 1.30 t ah address hold time 0 0 1.80 1.80 2.30 2.20 t cs csn setup time 0.60 0.60 0.60 0.60 0.60 0.60 t ch csn hold time 000000 t os oen setup time 000000 t oh oen hold time 2.50 2.40 2.60 2.50 2.90 2.60 t acc access time 4.40 4.40 5.00 5.00 6.10 6.10 t da deaccess time 2.60 2.60 2.60 2.60 2.60 2.60 size ( m m) width 466 595 757 886 1329 1458 height 443 443 638 638 1028 1028 power ( m w/mhz) power_ck (normal mode: csn low) 604 1299 3321 power_csn (stand-by mode: csn high) 18 29 50
sec asic 5-7 STD80/stdm80 crom gen contact programmable synchronous rom generator characteristic equation tables STD80 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] timing type timing equation y = 4 minckh (3.3175e C 03 * w + 1.4583e C 01 * s + 2.2165e C 01 * 0.019 * sl + 2.7969) * 1.1 minckl (1.7122e C 03 * w + 1.8311e C 01 * s + 5.8198e C 03 * 0.019 * sl + 1.9047) tacc (1.5030e C 03 * w + 1.6557e C 01 * s + 3.9827e C 01 * 0.019 * sl + 2.3576) y = 8 minckh (1.6322e C 03 * w + 1.4692e C 01 * s + 2.5139e C 01 * 0.019 * sl + 2.7965) * 1.1 minckl (8.5614e C 04 * w + 1.8311e C 01 * s + 5.8198e C 03 * 0.019 * sl + 1.9047) tacc (7.5152e C 04 * w + 1.6557e C 01 * s + 3.9827e C 01 * 0.019 * sl + 2.3576) y = 16 minckh (8.0853e C 04 * w + 1.4912e C 01 * s + 2.9137e C 01 * 0.019 * sl + 2.7911) * 1.1 minckl (4.2807e C 04 * w + 1.8311e C 01 * s + 5.8198e C 03 * 0.019 * sl + 1.9047) tacc (3.7576e C 04 * w + 1.6557e C 01 * s + 3.9827e C 01 * 0.019 * sl + 2.3576) y = 32 minckh (3.8015e C 04 * w + 1.6008e C 01 * s + 3.9802e C 01 * 0.019 * sl + 2.8462) * 1.1 minckl (2.1403e C 04 * w + 1.8311e C 01 * s + 5.8198e C 03 * 0.019 * sl + 1.9047) tacc (1.8788e C 04 * w + 1.6557e C 01 * s + 3.9827e C 0 1 * 0.019 * sl + 2.3576) power type power equation y = 4 power_ck (4.6376e C 02 * w + 1.5361 * b + 4.7973 + 2.4698e C 03 * w * b) * vdd 2 * f power_csn (1.4304e C 05 * w + 6.4197e C 02 * b + 8.0019e C 01 C 1.1140e C 06 * w * b) * vdd 2 * f y = 8 power_ck (2.7020e C 02 * w + 2.6893 * b + 3.6826 + 2.0572e C 03 * w * b) * vdd 2 * f power_csn (7.1521e C 06 * w + 1.2839e C 01 * b + 8.0019e C 01 C 1.1140e C 06 * w * b) * vdd 2 * f y = 16 power_ck (1.3385e C 02 * w + 4.9883 * b + 3.7560 + 1.8472e C 03 * w * b) * vdd 2 * f power_csn (3.5760e C 06 * w + 2.5679e C 01 * b + 8.0019e C 01 C 1.1140e C 06 * w * b) * vdd 2 * f y = 32 power_ck (6.3702e C 03 * w + 9.5401 * b + 4.8783 + 1.8001e C 03 * w * b) * vdd 2 * f power_csn (1.7880e C 06 * w + 5.1358e C 01 * b + 8.0019e C 01 C 1.1140e C 06 * w * b) * vdd 2 * f < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word ba: number of banks (1 or 2) sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
STD80/stdm80 5-8 sec asic crom gen contact programmable synchronous rom generator 3) size equation [unit: m m] width = 8.75 * ( log 2 (w / y) ) + 129.65 * ba + 4.4 * (b * y) + 1.4 [ m m] height = 247.15 + 3.05 * w / y [ m m] stdm80 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 8.75 * ( log 2 (w / y) ) + 129.65 * ba + 4.4 * (b * y) + 1.4 [ m m] height = 247.15 + 3.05 * w / y [ m m] timing type timing equation y = 4 minckh (4.9874e C 03 * w + 1.2996e C 01 * s + 3.0225e C 01 * 0.019 * sl + 4.1325) * 1.1 minckl (2.5384e C 03 * w + 2.2222e C 01 * s + 2.5303e C 03 * 0.019 * sl + 2.6714) tacc (2.1877e C 03 * w + 1.8452e C 01 * s + 5.0657e C 01 * 0.019 * sl + 3.3008) y = 8 minckh (2.4557e C 03 * w + 1.8154e C 01 * s + 3.2224e C 01 * 0.019 * sl + 4.1080) * 1.1 minckl (1.2692e C 03 * w + 2.2222e C 01 * s + 2.5303e C 03 * 0.019 * sl + 2.6714) tacc (1.0938e C 03 * w + 1.8452e C 01 * s + 5.0657e C 01 * 0.019 * sl + 3.3008) y = 16 minckh (1.2061e C 03 * w +1.9444e C 01 * s + 3.9119e C 01 * 0.019 * sl + 4.1096) * 1.1 minckl (6.3462e C 04 * w + 2.2222e C 01 * s + 2.5303e C 03 * 0.019 * sl + 2.6714) tacc (5.4693e C 04 * w + 1.8452e C 01 * s + 5.0657e C 01 * 0.019 * sl + 3.3008) y = 32 minckh (5.6878e C 04 * w + 2.0039e C 01 * s + 5.2378e C 01 * 0.019 * sl + 4.2085) * 1.1 minckl (3.1731e C 04 * w + 2.2222e C 01 * s + 2.5303e C 03 * 0.019 * sl + 2.6714) tacc (2.7346e C 04 * w + 1.8452e C 01 * s + 5.0657e C 01 * 0.019 * sl + 3.3008) power type power equation y = 4 power_ck (3.6222e C 02 * w + 1.5020 * b + 7.9632 + 3.4749e C 03 * w * b) * vdd 2 * f power_csn (2.0622e C 05 * w + 6.2300e C 02 * b + 7.3939e C 01 C 1.6060e C 06 * w * b) * vdd 2 * f y = 8 power_ck (2.0111e C 02 * w + 2.6231 * b + 7.1117 + 3.0340e C 03 * w * b) * vdd 2 * f power_csn (1.0311e C 05 * w + 1.2460e C 01 * b + 7.3939e C 01 -1.6060e C 06 * w * b) * vdd 2 * f y = 16 power_ck (9.9589e C 03 * w + 4.9313 * b + 7.1000 + 2.7268e C 03 * w * b) * vdd 2 * f power_csn (5.1556e C 06 * w + 2.4920e C 01 * b + 7.3939e C 01 -1.6060e C 06 * w * b) * vdd 2 * f y = 32 power_ck (5.3331e C 03 * w + 9.6566 * b + 6.9698 + 2.5764e C 03 * w * b) * vdd 2 * f power_csn (2.5778e C 06 * w + 4.9840e C 01 * b + 7.3939e C 01 -1.6060e C 06 * w * b) * vdd 2 * f
sec asic 5-9 STD80/stdm80 crom gen contact programmable synchronous rom generator timing diagrams read cycle csn control oen control dout ck t as a t ah minckl minckh t acc t da valid (csn / oen : low) dout ck a csn t cs t ch (oen : low) t acc dout ck a oen t os t oh (csn : low) t acc
STD80/stdm80 5-10 sec asic drom gen diffusion programmable synchronous rom generator logic symbol function description drom is a diffusion programmable synchronous rom. when ck rises, dout [ ] presents data programmed in the location addressed by a [ ]. csn is used to enable/disable the clock. oen is used to enable/disable the data output driver. generators and cell con?gurations drom gen. generates layout, netlist, symbol and functional & timing model of drom. the layout of drom is an automatically generated array of custom, pitch-matched leaf cells. to customize the con?guration of drom, you can give certain values to following four generator parameters: ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y) ? number of banks (ba). the valid range of these parameters is speci?ed in the following table: parameters ymux = 8 ymux = 16 ymux = 32 words (w) min 16 32 64 max 4096 8192 16384 step 16 32 64 bpw (b) ba = 1 min 2 2 2 max 64 32 16 step 1 1 1 ba = 2 min 4 4 4 max 128 64 32 step 1 1 1 ck csn oen dout [bC1:0] dromxmb a [m:0] notes: 1. words (w) is the number of words in a drom. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. banks (ba) is the number of banks. 5. m = log 2 w e 1 features ? synchronous operation ? read initiated at rising edge of clock ? stand-by (power down) mode available ? latched output ? unconditionally controlled tri-state output ? low noise output circuit ? programmable with diffusion layer ? flexible aspect ratio ? optional dual bank capacity ? up to 512k bits capacity ? up to 16k number of words ? up to 128 number of bits per word
sec asic 5-11 STD80/stdm80 drom gen diffusion programmable synchronous rom generator pin descriptions pin capacitance (unit = sl) application notes 1) customizing aspect ratio aspect ratio is programmable using low address decoder types. as you can see in the con?guration table, there are up to 3 selections of ymux for the same words and the same bpw drom. you can choose one of them in accordance with your chip level layout preference. larger ymux means fatter and shorter aspect ratio and smaller ymux means thinner and taller aspect ratio. as you can see in the characteristic tables, aspect ratio affects major characteristics of drom, in general, larger ymux drom has faster speed and bigger area than smaller ymux drom. 2) selecting number of banks to enlarge the capacity of drom, we added one more option to choose number of banks. if you want to use larger drom than 256k bit drom, you can select dual bank (ba = 2). you can also select dual bank for smaller one than 256k bit drom. dual bank drom is a little bigger and a little faster than single bank one. (please refer to the characteristic tables.) name i/o description ck i clock serves as the input clock to the memory block. when ck is low the memory is in a precharge state. upon the rising edge, an access cycle begins. csn i chip select negative acts as the memory enable signal for selections of multiple blocks on a common clock. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur, conversely, if low only then may a read access occur. csn may not change during ck is high. oen i output enable negative unconditionally controls the output drivers from driven to tri-state condition. a [ ] i address selects the location to be accessed. a [ ] may not change during ck is high. dout [ ] o during a read access, data word programmed will be presented to the data out ports. dout [ ] is latched during a full cycle. when csn is low and oen is low, only then, dout [ ] drives a certain value. otherwise, dout [ ] keeps hi-z state. ck csn oen a dout 1-bank 2.1 0.6 1.1 2.3 44.0 2-bank 4.2 1.2 2.2 2.3 44.0
STD80/stdm80 5-12 sec asic drom gen diffusion programmable synchronous rom generator block diagrams < 1-bank > < 2-bank > rom core y dec. & sense amp address buffer control logic out driver x dec. word dout [bC1:0] oen a [m:0] ck csn line drv. & rom core address buffer control logic x dec. word dout [bC1:(bC1)/2] line drv. & (left) word line drv. rom core dout [{(bC1)/2C1}:0] (right) oen a [m:0] ck csn y dec. & sense amp (left) out driver (left) y dec. & sense amp (right) out driver (right)
sec asic 5-13 STD80/stdm80 drom gen diffusion programmable synchronous rom generator characteristic reference table STD80 stdm80 symbol description 256x16m8 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing requirements & delay (typical process, 5v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 1.60 1.50 1.60 1.50 1.90 1.60 minckh minimum clock pulse width high 4.40 4.20 5.0 4.8 6.5 6.2 t as address setup time 0.10 0.10 0.20 0.20 0.30 0.30 t ah address hold time 000000 t cs csn setup time 0.40 0.40 0.40 0.40 0.40 0.40 t ch csn hold time 000000 t acc access time 5.20 5.10 5.90 5.70 7.10 6.70 t da deaccess time 3.80 3.60 4.40 4.20 5.60 5.20 t zd hi-z to valid data 1.70 1.70 1.70 1.70 1.70 1.70 t dz valid data to hi-z 1.00 0.90 1.00 0.90 1.00 1.00 mincyc minimum clock cycle time 5.70 5.40 7.30 7.00 10.20 9.70 size ( m m) width 556 720 576 740 917 1081 height 305 305 526 526 823 823 power ( m w/mhz) power_ck (normal mode: csn low) 785 1452 3842 power_csn (stand-by mode: csn high) 15 15 24 symbol description 256x16m8 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing requirements & delay (typical process, 3.3v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 2.30 2.10 2.30 2.10 2.60 2.30 minckh minimum clock pulse width high 6.70 6.40 7.70 7.50 10.10 9.60 t as address setup time 0.20 0.20 0.30 0.30 0.40 0.40 t ah address hold time 000000 t cs csn setup time 0.50 0.50 0.50 0.50 0.50 0.50 t ch csn hold time 000000 t acc access time 7.80 7.50 8.80 8.60 10.70 10.20 t da deaccess time 5.90 5.60 6.90 6.70 8.80 8.30 t zd hi-z to valid data 2.40 2.40 2.40 2.40 2.40 2.40 t dz valid data to hi-z 1.90 1.80 1.90 1.80 2.00 1.90 mincyc minimum clock cycle time 8.40 8.10 11.10 10.80 15.60 14.90 size ( m m) width 556 720 576 740 917 1081 height 305 305 526 526 823 823 power ( m w/mhz) power_ck (normal mode: csn low) 364 705 1962 power_csn (stand-by mode: csn high) 9 9 13
STD80/stdm80 5-14 sec asic drom gen diffusion programmable synchronous rom generator characteristic equation tables STD80 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 10.2 * ( log 2 (w / y) ) + 164.8 * ba + 2.5843 (b * y) + 8.2 [ m m] height = 225.1 + 2.30 * w / y + m [ m m] m = 6.05 (if y = 8), m = 8.45 (if y = 16), m = 10.85 (if y = 32) timing type timing equation y = 8 minckh (8.2203e C 04 * w + 2.3006e C 02 * b / ba + 8.6348e C 02 * s + 3.6997) mincyc (2.1349e C 03 * w + 3.1585e C 02 * b / ba + 7.9769e C 02 * s + 4.5076) minckl (1.7851e C 02 * b / ba + 2.4313e C 01 * s + 1.0586 C 1.4159e C 03 * b / ba * s) tacc (8.1748e C 04 * w + 2.2545e C 02 * b / ba + 9.3201e C 02 * s + 6.9313e C 01 * 0.019 * sl + 4.4137) y = 16 minckh (4.1293e C 04 * w + 4.5635e C 02 * b / ba + 8.2236e C 02 * s + 4.0192) mincyc (1.0224e C 03 * w + 6.6842e C 02 * b / ba + 2.0888e C 01 * s + 4.6828) minckl (3.5702e C 02 * b / ba + 2.4313e C 01 * s + 1.0586 C 2.8318e C 03 * b / ba * s) tacc (4.0874e C 04 * w + 4.5090e C 02 * b / ba + 9.3201e C 02 * s + 6.9313e C 01 * 0.019 * sl + 4.4137) y = 32 minckh (2.0606e C 04 * w + 8.9923e C 02 * b / ba + 9.7039e C 02 * s + 4.6465) mincyc (4.6249e C 04 * w + 1.3320e C 01 * b / ba + 1.6529e C 01 * s + 5.3888) minckl (7.1405e C 02 * b / ba + 2.4313e C 01 * s + 1.0586 C 5.6636e C 03 * b / ba * s) tacc (2.0437e C 04 * w + 9.0181e C 02 * b / ba + 9.3201e C 02 * s + 6.9313e C 01 * 0.019 * sl + 4.4137) power type power equation y = 8 power_ck (1.5962e C 02 * w + 1.0692 * b + 5.3930 + 1.1779e C 03 * w * b) * vdd 2 * f power_csn (1.0460e C 10 * w + 2.2399e C 02 * b + 2.5200e C 01 C 1.4450e C 11 * w * b) * vdd 2 * f y = 16 power_ck (7.5901e C 03 * w + 1.7134 * b + 5.4951 + 1.3695e C 03 * w * b) * vdd 2 * f power_csn (5.1138e C 11 * w + 4.4799e C 02 * b + 2.5200e C 01 C 1.4319e C 11 * w * b) * vdd 2 * f y = 32 power_ck (3.4176e C 03 * w + 3.2755 * b + 6.0417 + 1.5281e C 03 * w * b) * vdd 2 * f power_csn (2.5284e C 11 * w + 8.9599e C 02 * b + 2.5200e C 01 C 1.4253e C 11 * w * b) * vdd 2 * f < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word ba: number of banks (1 or 2) sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
sec asic 5-15 STD80/stdm80 drom gen diffusion programmable synchronous rom generator stdm80 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 10.2 * ( log 2 (w / y) ) + 164.8 * ba + 2.5843 (b * y) + 8.2 [ m m] height = 225.1 + 2.30 * w / y + m [ m m] m = 6.05 (if y = 8), m = 8.45 (if y = 16), m = 10.85 (if y = 32) timing type timing equation y = 8 mincyc (3.5198e C 03 * w + 4.5826e C 02 * b / ba + 2.4255e C 01 * s + 6.4868) minckh (1.3433e C 03 * w + 3.3260e C 02 * b / ba + 1.2351e C 01 * s + 5.6854) minckl (2.3158e C 02 * b / ba + 2.9813e C 01 * s + 1.6106 C 2.4974e C 03 * b / ba * s) tacc (1.3364e C 03 * w + 3.3374e C 02 * b / ba + 1.0962e C 01 * s + 8.2600e C 01 * 0.019 * sl + 6.6360) y = 16 mincyc (1.6536e C 03 * w + 9.2665e C 02 * b / ba + 2.9389e C 01 * s + 6.9996) minckh (6.6951e C 04 * w + 6.6059e C 02 * b / ba + 1.1160e C 01 * s + 6.1996) minckl (4.6317e C 02 * b / ba + 2.9813e C 01 * s + 1.6106 C 4.9948e C 03 * b / ba * s) tacc (6.6823e C 04 * w + 6.6748e C 02 * b / ba + 1.0962e C 01 * s + 8.2600e C 01 * 0.019 * sl + 6.6360) y = 32 mincyc (7.6109e C 04 * w + 1.9146e C 01 * b / ba + 2.5595e C 01 * s + 8.0221) minckh (3.3361e C 04 * w + 1.3092e C 01 * b / ba + 1.1383e C 01 * s + 7.1958) minckl (9.2635e C 02 * b / ba + 2.9813e C 01 * s + 1.6106 C 9.9896e C 03 * b / ba * s) tacc (3.3411e C 04 * w + 1.3349e C 01 * b / ba + 1.0962e C 01 * s + 8.2600e -01 * 0.019 * sl + 6.6360) power type power equation y = 8 power_ck (1.6785e C 02 * w + 1.1261 * b + 5.1661 + 1.4915e C 03 * w * b) * vdd 2 * f power_csn (1.2353e C 05 * w + 2.9755e C 02 * b + 3.4939e C 01 C 1.2733e C 06 * w * b) * vdd 2 * f y = 16 power_ck (7.8633e C 03 * w + 1.7350 * b + 5.5361 + 1.7510e C 03 * w * b) * vdd 2 * f power_csn (6.1769e C 06 * w + 5.9511e C 02 * b + 3.4939e C 01 C 1.2733e C 06 * w * b) * vdd 2 * f y = 32 power_ck (4.0198e C 03 * w + 3.7202 * b + 5.2484 + 1.7655e C 03 * w * b) * vdd 2 * f power_csn (3.0884e C 06 * w + 1.1902e C 01 * b + 3.4939e C 01 C 1.2733e C 06 * w * b) * vdd 2 * f
STD80/stdm80 5-16 sec asic drom gen diffusion programmable synchronous rom generator timing diagrams read cycle csn control oen control dout ck t as a t ah minckl minckh t acc t da (csn / oen : low) mincyc dout ck a csn t cs t ch t dz t zd (oen : low) valid t acc dout oen t zd t dz (csn : low) valid
sec asic 5-17 STD80/stdm80 spsram gen single-port synchronous ram generator logic symbol function description spsram is a single-port synchronous static ram. when ck rises, if wen is high, dout [ ] presents data stored in the location addressed by a [ ], otherwise the value of di [ ] is written into the location addressed by a [ ]. csn is used to enable/disable the clock. oen is used to enable/disable the data output driver. generators and cell con?gurations spsram gen. generates layout, netlist, symbol and functional & timing model of spsram. the layout of spsram is an automatically generated array of custom, pitch-matched leaf cells. to customize the con?guration of spsram, you can give certain values to following four generator parameters: ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y) ? number of banks (ba). the valid range of these parameters is speci?ed in the following table: parameters ymux = 2 ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 4 8 16 32 64 max 512 1024 2048 4096 8192 step 2 4 8 16 32 bpw (b) ba = 1 min 11111 max 128 64 32 16 8 step 11111 ba = 2min 22222 max 256 128 64 32 16 step 11111 ck csn wen oen a [m:0] spsramxmb dout [bC1:0] di [bC1:0] notes: 1. words (w) is the number of words in spsram. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. banks (ba) is the number of banks. 5. m = log 2 w e 1 features ? synchronous operation ? read initiated at rising edge of clock ? write completed at rising edge of clock ? stand-by (power down) mode available ? tri-state output ? separated data i/o ? low noise output circuit ? flexible aspect ratio ? optional dual bank capacity ? up to 128k bits capacity ? up to 8k number of words ? up to 256 number of bits per word
STD80/stdm80 5-18 sec asic spsram gen single-port synchronous ram generator pin descriptions pin capacitance (unit = sl) application notes 1) putting busholders on dout [ ] as you will see in the timing diagrams, dout [ ] is valid only when ck is high. if you want dout [ ] to be stable regardless of ck state, you should put STD80/stdm80 busholder cells on the dout [ ] bus externally. 2) customizing aspect ratio aspect ratio is programmable using low address decoder types. as you can see in the con?guration table, there are up to 5 selections of ymux for the same words and the same bpw spsram. you can choose one of them in accordance with your chip level layout preference. larger ymux means fatter and shorter aspect ratio and smaller ymux means thinner and taller aspect ratio. as you can see in the characteristic tables, aspect ratio affects major characteristics of spsram, in general, larger ymux spsram has faster speed and bigger area than smaller ymux spsram. 3) selecting number of banks to enlarge the capacity of spsram, we added one more option to choose number of banks. if you want to use larger spsram than 64k bit spsram, you can select dual bank (ba = 2). you can also select dual bank for smaller one than 64k bit spsram. dual bank spsram is a little bigger and a little faster than single bank one. (please refer to the characteristic tables.) name i/o description ck i clock serves as the input clock to the memory block. when ck is low, the memory is in a precharge state. upon the rising edge, an access begins. csn i chip select negative acts as the memory enable signal for selections of multiple blocks on a common clock. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur, conversely, if low only then may a read or write access occur. csn may not change during ck is high. wen i write enable negative selects the type of memory access. read is the high state, and write is the low state. oen i output enable negative controls the output drivers from driven to tri-state condition. oen may not change during ck is high. a [ ] i address selects the location to be accessed. a [ ] may not change during ck is high. di [ ] i when ck rises while wen is low, the data in word value is written to the accessed location. dout [ ] o during a read access, data word stored will be presented to the data out ports. dout [ ] is tri-statable. when ck is high, csn is low and oen is low, only then, dout [ ] drives a certain value. otherwise, dout [ ] keeps hi-z state. during a write access, data word written will be presented at the data out ports if output driver is enabled. ck csn wen oen a di dout ymux 2 ymux 4 ymux 8 ymux 16 ymux 32 1-bank 3.5 1.0 0.5 1.6 1.2 2.1 3.1 3.3 7.7 15.0 31.0 2-bank 7.0 2.1 1.0 3.1 1.2 2.1 3.1 3.3 7.7 15.0 31.0
sec asic 5-19 STD80/stdm80 spsram gen single-port synchronous ram generator block diagrams < 1-bank > < 2-bank > ram core y dec. & sense amp address buffer control logic i/o driver di [bC1:0] x dec. word dout [bC1:0] wen a [m:0] csn oen line drv. & ck ram core address buffer control logic di [bC1:(bC1)/2] x dec. word dout [bC1:(bC1)/2] line drv. & (left) word line drv. ram core di [{(bC1)/2C1}:0] dout [{(bC1)/2C1}:0] (right) wen a [m:0] csn oen ck y dec. & sense amp (left) i/o driver (left) y dec. & sense amp (right) i/o driver (right)
STD80/stdm80 5-20 sec asic spsram gen single-port synchronous ram generator characteristic reference table STD80 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing requirements & delay (typical process, 5v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 2.00 1.90 2.40 2.30 3.17 2.90 minckh minimum clock pulse width high 5.60 5.60 5.90 5.80 6.56 6.45 t as address setup time 0.36 0.38 0.59 0.56 1.10 0.98 t ah address hold time 0.34 0.34 0.39 0.46 0.50 0.63 t cs csn setup time 0.51 0.51 0.51 0.51 0.51 0.51 t ch csn hold time 000000 t ds data input setup time 000000 t dh data input hold time 2.90 2.70 3.60 3.30 5.00 4.40 t os oen setup time 000000 t oh oen hold time 1.30 1.30 1.50 1.50 2.00 1.80 t ws wen setup time 000000 t wh wen hold time 000000 t acc access time 2.95 2.86 3.50 3.30 4.60 4.24 t da deaccess time 2.10 2.00 2.20 2.10 2.50 2.20 mincyc minimum clock cycle time 7.85 7.70 8.90 8.60 11.00 10.10 size ( m m) width 622 703 1131 1212 2142 2222 height 902 902 1501 1501 2697 2697 power ( m w/mhz) power_ck (normal mode: csn low) 1261 2412 5150 power_csn (stand-by mode: csn high) 107 155 300
sec asic 5-21 STD80/stdm80 spsram gen single-port synchronous ram generator characteristic reference table (cont.) stdm80 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing requirements & delay (typical process, 3.3v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 2.80 2.70 3.40 3.20 4.50 4.10 minckh minimum clock pulse width high 8.40 8.40 8.80 8.80 9.40 9.50 t as address setup time 0.40 0.40 0.68 0.65 1.40 1.20 t ah address hold time 0.36 0.40 0.40 0.40 0.60 0.60 t cs csn setup time 0.44 0.44 0.44 0.44 0.44 0.44 t ch csn hold time 000000 t ds data input setup time 000000 t dh data input hold time 4.00 3.80 4.90 4.50 6.70 5.90 t os oen setup time 000000 t oh oen hold time 2.00 2.00 2.30 2.20 2.70 2.60 t ws wen setup time 000000 t wh wen hold time 000000 t acc access time 4.30 4.20 5.10 4.80 6.70 6.10 t da deaccess time 2.80 2.70 3.00 2.80 3.40 3.00 mincyc minimum clock cycle time 11.50 11.20 13.20 12.60 16.50 15.40 size ( m m) width 622 703 1131 1212 2142 2222 height 902 902 1501 1501 2697 2697 power ( m w/mhz) power_ck (normal mode: csn low) 529 1063 2395 power_csn (stand-by mode: csn high) 52 92 163
STD80/stdm80 5-22 sec asic spsram gen single-port synchronous ram generator characteristic equation tables STD80 1) timing characteristics [unit: ns] timing type timing equation y = 2 minckh (2.0583e C 03 * w + 1.8220e C 03 * b / ba + 1.2739 * 0.019 * sl + 1.6496) minckl (1.9900e C 03 * w + 3.8135e C 03 * b / ba + 1.6302 + 6.2396e C 07 * w * b / ba) mincyc (5.4783e C 03 * w + 8.6924e C 03 * b / ba + 1.0451 * 0.019 * sl + 3.3130) * 1.08 tacc (2.8771e C 03 * w + 5.6933e C 03 * b / ba + 9.7039e C 02 * s + 5.6468e C 01 * 0.019 * sl + 2.1791) y = 4 minckh (1.0291e C 03 * w + 3.6440e C 03 * b / ba + 1.2739 * 0.019 * sl + 1.6496) minckl (9.9503e C 04 * w + 7.6271e C 03 * b / ba + 1.6302 + 6.2396e C 07 * w * b / ba) mincyc (2.7391e C 03 * w + 1.7384e C 02 * b / ba + 1.0451 * 0.019 * sl + 3.3130) * 1.08 tacc (1.4385e C 03 * w + 1.1386e C 02 * b / ba + 9.7039e C 02 * s + 5.6468e C 01 * 0.019 * sl + 2.1791) y = 8 minckh (5.1457e C 04 * w + 7.2880e C 03 * b / ba + 1.2739 * 0.019 * sl + 1.6496) minckl (4.9751e C 04 * w + 1.5254e C 02 * b / ba + 1.6302 + 6.2396e C 07 * w * b / ba) mincyc (1.3695e C 03 * w + 3.4769e C 02 * b / ba + 1.0451 * 0.019 * sl + 3.3130) * 1.08 tacc (7.1928e C 04 * w + 2.2773e C 02 * b / ba + 9.7039e C 02 * s + 5.6468e C 01 * 0.019 * sl + 2.1791) y = 16 minckh (2.5728e C 04 * w + 1.4576e C 02 * b / ba + 1.2739 * 0.019 * sl + 1.6496) minckl (2.4875e C 04 * w + 3.0508e C 02 * b / ba + 1.6302 + 6.2396e C 07 * w *b / ba) mincyc (6.8479e C 04 * w + 6.9539e C 02 * b / ba + 1.0451 * 0.019 * sl + 3.3130) * 1.08 tacc (3.5964e C 04 * w + 4.5547e C 02 * b / ba + 9.7039e C 02 * s + 5.6468e C 01 * 0.019 * sl + 2.1791) y = 32 minckh (1.2864e C 04 * w + 2.9152e C 02 * b / ba + 1.2739 * 0.019 * sl + 1.6496) minckl (1.2437e C 04 * w + 6.1017e C 02 * b / ba + 1.6302 + 6.2394e C 07 * w * b / ba) mincyc (3.4239e C 04 * w +1.3907e C 01 * b / ba + 1.0451 * 0.019 * sl + 3.3130) * 1.08 tacc (1.7982e C 04 * w + 9.1094e C 02 * b / ba + 9.7039e C 02 * s + 5.6468e C 01 * 0.019 * sl + 2.1791) < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word ba: number of banks (1 or 2) sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
sec asic 5-23 STD80/stdm80 spsram gen single-port synchronous ram generator 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 6 * ( log2 (w / y) ) + 76.3 * ba + 4.4 (b * y / 4 + ba) + 6.75 * b * y + 2.25 [ m m] height = 297.5 + 9.35 * w / y + m [ m m] m = 5.75 (if y = 2, 4, 8, 16), m = 8.15 (if y = 32) stdm80 1) timing characteristics [unit: ns] power type power equation y = 2 power_ck (1.3452e C 01 * w + 9.8737e C 01 * b + 1.9854 + 2.5351e C 03 * w * b) * vdd 2 * f power_csn (8.8861e C 03 * w + 1.3209e C 01 * b + 1.1430e C 01 C 2.8037e C 04 * w * b) * vdd 2 * f y = 4 power_ck (6.9202e C 02 * w + 1.4519 * b + 3.0524 + 1.5738e C 03 * w * b) * vdd 2 * f power_csn (4.4430e C 03 * w + 2.6419e C 01 * b + 1.1430e C 01 C 2.8037e C 04 * w * b) * vdd 2 * f y = 8 power_ck (3.3665e C 02 * w + 2.2848 * b + 3.6310 + 1.3354e C 03 * w * b) * vdd 2 * f power_csn (2.2215e C 3 * w + 5.2839e C 01 * b + 1.1430e C 01 C 2.8037e C 04 * w * b) * vdd 2 * f y = 16 power_ck (1.6925e C 02 * w + 4.0510 * b + 3.4129 + 1.0574e C 03 * w * b) * vdd 2 * f power_csn (1.1107e C 03 * w + 1.0567 * b + 1.1430e C 01 C 2.8037e C 04 * w * b) * vdd 2 * f y = 32 power_ck (8.4295e C 03 * w + 7.5842 * b + 2.9152 + 9.5723e C 04 * w * b) * vdd 2 * f power_csn (5.5538e C 04 * w + 2.1135 * b + 1.1430e C 01 C 2.8037e C 04 * w * b) * vdd 2 * f timing type timing equation y = 2 minckh (2.7855e C 03 * w + 2.7711e C 03 * b / ba + 1.7719 * 0.019 * sl + 3.0534 C 1.2983e C 03 * b / ba * 0.019 * sl) minckl (2.9979e C 03 * w + 5.1004e C 03 * b / ba + 2.2601 C 5.1494e C 09 * b / ba * w) mincyc (8.1165e C 03 * w + 1.6054e C 02 * b / ba + 1.4542 * 0.019 * sl + 4.9456) * 1.08 tacc (3.9714e C 03 * w + 7.8602e C 03 * b /ba + 1.7038e C 01 * s + 7.1508e C 01 * 0.019 * sl + 3.1048) y = 4 minckh (1.3927e C 03 * w + 5.5423e C 03 * b /ba + 1.7719 * 0.019 * sl + 3.0534 C 2.5966e C 03 * b / ba * 0.019 * sl) minckl (1.4989e C 03 * w + 1.0200e C 02 * b / ba + 2.2601 C 5.1639e C 09 * b / ba * w) mincyc (4.0582e C 03 * w + 3.2109e C 02 * b / ba + 1.4542 * 0.019 * sl + 4.9456) * 1.08 tacc (1.9857e C 03 * w + 1.5720e C 02 * b / ba + 1.7038e C 01 * s +7.1508e C 01 * 0.019 * sl + 3.1048) y = 8 minckh (6.9638e C 04 * w + 1.1084e C 02 * b / ba + 1.7719 * 0.019 * sl + 3.0534 C 5.1932e C 03 * b / ba * 0.019 * sl) minckl (7.4948e C 04 * w + 2.0401e C 02 * b / ba + 2.2601 C 5.1817e C 09 * b / ba * w) mincyc (2.0291e C 03 * w + 6.4219e C 02 * b / ba + 1.4542 * 0.019 * sl + 4.9456) * 1.08
STD80/stdm80 5-24 sec asic 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 6 * ( log2 (w / y) ) + 76.3 * ba + 4.4 (b * y / 4 + ba) + 6.75 * b * y + 2.25 [ m m] height = 297.5 + 9.35 * w / y + m [ m m] m = 5.75 (if y = 2, 4, 8, 16), m = 8.15 (if y = 32) tacc (9.9285e e 04 * w + 3.1441e e 02 * b / ba + 1.7038e e 01 * s + 7.1508e e 01 * 0.019 * sl+ 3.1048) y = 16 minckh (3.4819e C 04 * w + 2.2169e C 02 * b / ba + 1.7719 * 0.019 * sl + 3.0534 C 1.0386e C 02 * b / ba * 0.019 * sl) minckl (3.7474e C 04 * w + 4.0803e C 02 * b / ba + 2.2601 C 5.1761e C 09 * b / ba * w) mincyc (1.0145e C 03 * w + 1.2843e C 01 * b / ba + 1.4542 * 0.019 * sl + 4.9456) * 1.08 tacc (4.9642e C 04 * w + 6.2882e C 02 * b / ba + 1.7038e C 01 * s + 7.1508e C 01 * 0.019 * sl + 3.1048) y = 32 minckh (1.7409e C 04 * w + 4.4338e C 02 * b / ba + 1.7719 * 0.019 * sl + 3.0534 C 2.0773e C 02 * b / ba * 0.019 * sl) minckl (1.8737e C 04 * w + 8.1606e C 02 * b / ba + 2.2601 C 5.1446e C 09 * b / ba * w) mincyc (5.0728e C 04 * w + 2.5687e C 01 * b / ba + 1.4542 * 0.019 * sl + 4.9456) * 1.08 tacc (2.4821e C 04 * w + 1.2576e C 01 * b / ba + 1.7038e C 01 * s + 7.1508e C 01 * 0.019 * sl + 3.1048) power type power equation y = 2 power_ck (1.3167e C 01 * w + 7.9148e C 01 * b + 1.7625 + 1.1349e C 03 *w * b) * vdd 2 * f power_csn (3.1611e C 03 * w + 1.2166e C 01 * b + 6.3691e C 01 C 4.2817e C 05 * w * b) * vdd 2 * f y = 4 power_ck (6.5837e C 02 * w + 1.5829 * b + 1.7625 + 1.1349e C 03 * w * b) * vdd 2 * f power_csn (1.5805e C 03 * w + 2.4333e C 01 * b + 6.3691e C 01 C 4.2817e C 05 * w * b) * vdd 2 * f y = 8 power_ck (3.0498e C 02 * w + 2.4446 * b + 4.0763 + 1.4227e C 03 * w * b) * vdd 2 * f power_csn (7.9029e C 04 * w + 4.8667e C 01 * b + 6.3691e C 01 C 4.2817e C 05 * w * b) * vdd 2 * f y = 16 power_ck (1.5183e C 02 * w + 4.0522 * b + 4.5947 + 1.34e C 03 * w * b) * vdd 2 * f power_csn (3.9514e C 04 * w + 9.7335e C 01 * b + 6.3691e C 01 C 4.2817e C 05 * w * b) * vdd 2 * f y = 32 power_ck (7.8479e C 03 * w + 8.1911 * b + 3.4364 + 1.0426e C 03 * w * b) * vdd 2 * f power_csn (1.9757e C 04 * w + 1.9467 * b + 6.3691e C 01 C 4.2817e C 05 * w * b) * vdd 2 * f timing type timing equation spsram gen single-port synchronous ram generator
sec asic 5-25 STD80/stdm80 spsram gen single-port synchronous ram generator timing diagrams read cycle write cycle csn control dout ck t as a t ah minckl (csn / oen : low) minckh hi-z t acc t da wen t ws t wh mincyc dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen t ws t wh di t ds t dh dout ck a csn (oen : low) t cs hi-z t acc t ch
STD80/stdm80 5-26 sec asic spsram gen single-port synchronous ram generator oen control dout ck a oen (csn : low) t os t oh t acc
sec asic 5-27 STD80/stdm80 spsrama gen single-port synchronous ram generator C alternative logic symbol function description spsrama is a single-port synchronous static ram. when wen is high and ck rises, dout [ ] presents data stored in the location addressed by a [ ]. when wen is low and ck falls, or when ck is high and wen rises, the value of di [ ] is written into the location addressed by a [ ]. csn is used to enable/disable the clock. oen is used to enable/disable the data output driver. spsrama is an alternative of spsram. the major difference of these two rams is the timing of read and write. spsrama reads and writes at different edge of the clock since spsram reads and writes at the same edge of the clock. generators and cell con?gurations spsrama gen. generates layout, netlist, symbol and functional & timing model of spsrama. the layout of spsrama is an automatically generated array of custom, pitch-matched leaf cells. to customize the con?guration of spsrama, you can give certain values to following four generator parameters: ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y) ? number of banks (ba). the valid range of these parameters is speci?ed in the following table: parameters ymux = 2 ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 4 8 16 32 64 max 512 1024 2048 4096 8192 step 2 4 8 16 32 bpw (b) ba = 1 min 11111 max 128 64 32 16 8 step 11111 ba = 2min 22222 max 256 128 64 32 16 step 11111 ck csn wen oen a [m:0] spsramaxmb dout [bC1:0] di [bC1:0] notes: 1. words (w) is the number of words in spsrama. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. banks (ba) is the number of banks. 5. m = log 2 w e 1 features ? synchronous operation ? read initiated at rising edge of clock ? write completed at falling edge of clock ? possible read modi?ed write cycle ? stand-by (power down) mode available ? tri-state output ? separated data i/o ? low noise output circuit ? possible bi-directional operation ? flexible aspect ratio ? optional dual bank capacity ? up to 128k bits capacity ? up to 8k number of words ? up to 256 number of bits per word
STD80/stdm80 5-28 sec asic spsrama gen single-port synchronous ram generator C alternative pin descriptions pin capacitance (unit = sl) name i/o description ck i clock serves as the input clock to the memory block. when ck is low, the memory is in a precharge state. upon the rising edge, a read cycle begins. upon the falling edge, a write cycle ends. csn i chip select negative acts as the memory enable signal for selections of multiple blocks on a common clock. when csn is high, the memory goes to stand-by (power down) mode and no access to the memory can occur, conversely, if low only then may a read or write access occur. csn may not change during ck is high. wen i write enable negative selects the type of memory access. read is the high state, and write is the low state. when wen rises while ck is high, a write cycle ends. oen i output enable negative controls the output drivers from driven to tri-state condition. oen may not change during ck is high. a [ ] i address selects the location to be accessed. a [ ] may not change during ck is high. di [ ] i when ck falls while wen is low, or when wen rises while ck is high, the data in word value is written to the accessed location. dout [ ] o during a read access, data word stored will be presented to the data out ports. dout [ ] is tri-statable. when ck is high, csn is low and oen is low, only then, dout [ ] drives a certain value. otherwise, dout [ ] keeps hi-z state. during a write access, the value of dout [ ] is unpredictable. ck csn wen oen a di dout ymux 2 ymux 4 ymux 8 ymux 16 ymux 32 1-bank 3.5 1.0 0.5 1.6 1.2 2.1 3.1 3.3 7.7 15.0 31.0 2-bank 7.0 2.1 1.0 3.1 1.2 2.1 3.1 3.3 7.7 15.0 31.0
sec asic 5-29 STD80/stdm80 spsrama gen single-port synchronous ram generator C alternative application notes 1) putting busholders on dout [ ] as you will see in the timing diagrams, dout [ ] is valid only when ck is high. if you want dout [ ] to be stable regardless of ck state, you should put STD80/stdm80 busholder cells on the dout [ ] bus externally. 2) customizing aspect ratio aspect ratio is programmable using low address decoder types. as you can see in the con?guration table, there are up to 5 selections of ymux for the same words and the same bpw spsrama. you can choose one of them in accordance with your chip level layout preference. larger ymux means fatter and shorter aspect ratio and smaller ymux means thinner and taller aspect ratio. as you can see in the characteristic tables, aspect ratio affects major characteristics of spsram, in general, larger ymux spsrama has faster speed and bigger area than smaller ymux spsrama. 3) selecting number of banks to enlarge the capacity of spsrama, we added one more option to choose number of banks. if you want to use larger spsrama than 64k bit spsrama, you can select dual bank (ba = 2). you can also select dual bank for smaller one than 64k bit spsrama. dual bank spsrama is a little bigger and a little faster than single bank one. (please refer to the characteristic tables.) 4) using bi-directional data port because having the same phase, di [ ] and dout [ ] of spsrama can be tied directly. with tying them up together and controlling wen and oen properly, you can use them as bi-directional data ports.
STD80/stdm80 5-30 sec asic spsrama gen single-port synchronous ram generator C alternative block diagrams < 1-bank > < 2-bank > ram core y dec. & sense amp address buffer control logic i/o driver di [bC1:0] x dec. word dout [bC1:0] wen a [m:0] csn oen line drv. & ck ram core address buffer control logic di [bC1:(bC1)/2] x dec. word dout [bC1:(bC1)/2] line drv. & (left) word line drv. ram core di [{(bC1)/2C1}:0] dout [{(bC1)/2C1}:0] (right) wen a [m:0] csn oen ck y dec. & sense amp (left) i/o driver (left) y dec. & sense amp (right) i/o driver (right)
sec asic 5-31 STD80/stdm80 spsrama gen single-port synchronous ram generator C alternative characteristic reference table STD80 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2--ba 1-ba 2-ba timing requirements & delay (typical process, 5v, 25 o c, output load = 10sl, unit = ns) t rp minimum read pulse width 6.35 6.28 6.87 6.72 7.91 7.61 t pc minimum pre-charge period 2.56 2.25 3.64 3.20 5.78 4.90 t wp minimum write pulse width 1.13 1.16 1.40 1.40 1.95 2.00 t as address setup time 0.45 0.44 0.68 0.68 0.98 1.00 t ah address hold time 0.83 0.77 1.16 1.00 1.82 1.57 t cs csn setup time 0.37 0.37 0.37 0.37 0.37 0.37 t ch csn hold time 000000 t ds data input setup time 0.69 0.76 0.86 0.98 1.19 1.44 t dh data input hold time 1.67 1.52 1.99 1.69 2.61 2.01 t os oen setup time 000000 t oh oen hold time 1.25 1.21 1.44 1.37 1.83 1.67 t wh wen hold time 0.71 0.70 0.73 0.71 0.76 0.72 t acc access time 4.60 4.50 5.10 5.00 6.27 5.90 t da deaccess time 1.90 1.70 2.10 1.90 2.30 1.90 size ( m m) width 622 703 1131 1212 2142 2222 height 902 902 1501 1501 2697 2697 power ( m w/mhz) power_ck (normal mode: csn low) 1416 3575 9673 power_csn (stand-by mode: csn high) 102 191 385
STD80/stdm80 5-32 sec asic spsrama gen single-port synchronous ram generator C alternative characteristic reference table (cont.) stdm80 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing requirements & delay (typical process, 3.3v, 25 o c, output load = 10sl, unit = ns) t rp minimum read pulse width 9.37 9.30 10.00 9.80 11.40 11.0 t pc minimum pre-charge period 3.58 3.30 5.10 5.10 8.10 7.00 t wp minimum write pulse width 1.63 1.63 2.06 2.10 2.90 3.00 t as address setup time 0.54 0.54 0.82 0.83 1.29 1.37 t ah address hold time 0.17 1.10 1.48 1.33 2.10 1.80 t cs csn setup time 0.55 0.55 0.55 0.55 0.55 0.55 t ch csn hold time 000000 t ds data input setup time 0.82 0.90 1.14 1.33 1.75 2.10 t dh data input hold time 2.25 2.00 2.65 2.20 3.45 2.60 t os oen setup time 000000 t oh oen hold time 1.83 1.79 2.00 1.90 2.36 2.21 t wh wen hold time 0.91 0.90 0.93 0.91 0.98 0.93 t acc access time 6.50 5.30 7.30 7.00 8.98 8.35 t da deaccess time 2.60 2.30 2.80 2.40 3.20 2.60 size ( m m) width 622 703 1131 1212 2142 2222 height 902 902 1501 1501 2697 2697 power ( m w/mhz) power_ck (normal mode: csn low) 685 1718 4867 power_csn (stand-by mode: csn high) 46 88 180
sec asic 5-33 STD80/stdm80 spsrama gen single-port synchronous ram generator C alternative characteristic equation tables STD80 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] timing type timing equation y = 2 tpc 5.05e C 03 * w + 1.32e C 02 * b / ba + 3.12e C 01 * s + 1.1222 trp 2.88e C 03 * w + 4.63e C 03 * b / ba C 2.55e C 01 * s + 1.4029 * 0.019 * sl + 2.1511 tacc 2.94e C 03 * w + 5.16e C 03 * b / ba + 6.26e C 01 * 0.019 * sl + 2.2007 + 8.28e C 07 * w * b / ba + 1.79e C 05 * w * 0.019 * sl C 1.39e C 04 * b / ba * 0.019 * sl y = 4 tpc 2.52e C 03 * w + 2.65e C 02 * b / ba + 3.12e C 01 * s + 1.1222 trp 1.44e C 03 * w + 9.26e C 03 * b / ba C 2.55e C 01 * s + 1.4029 * 0.019 * sl + 2.1511 tacc 1.47e C 03 * w + 1.03e C 02 * b / ba + 6.26e C 01 * 0.019 * sl + 2.2007 + 8.28e C 07 * w * b / ba + 8.97e C 06 * w * 0.019 * sl C 2.78e C 04 * b / ba * 0.019 * sl y = 8 tpc 1.26e C 03 * w + 5.31e C 02 * b / ba + 3.12e C 01 * s + 1.1222 trp 7.20e C 04 * w + 1.85e C 02 * b / ba C 2.55e C 01 * s + 1.4029 * 0.019 * sl + 2.1511 tacc 7.36e C 04 * w + 2.06e C 02 * b / ba + 6.26e C 01 * 0.019 * sl + 2.2007 + 8.28e C 07 * w * b / ba + 4.48e C 06 * w * 0.019 * sl C 5.57e C 04 * b / ba * 0.019 * sl y = 16 tpc 6.31e C 04 * w + 1.06e C 01 * b / ba + 3.12e C 01 * s + 1.1222 trp 3.60e C 04 * w + 3.70e C 02 * b / ba C 2.55e C 01 * s + 1.4029 * 0.019 * sl + 2.1511 tacc 3.68e C 04 * w + 4.13e C 02 * b / ba + 6.26e C 01 * 0.019 * sl + 2.2007 + 8.28e C 07 * w * b / ba + 2.24e C 06 * w * 0.019 * sl C 1.11e C 03 * b / ba * 0.019 * sl y = 32 tpc 3.15e C 04 * w + 2.12e C 01 * b / ba + 3.12e C 01 * s + 1.1222 trp 1.80e C 04 * w + 7.41e C 02 * b / ba C 2.55e C 01 * s + 1.4029 * 0.019 * sl + 2.1511 tacc 1.84e C 04 * w + 8.26e C 02 * b / ba + 6.26e C 01 * 0.019 * sl + 2.2007 + 8.28e C 07 * w * b / ba + 1.12e C 06 * w * 0.019 * sl C 2.23e C 03 * b / ba * 0.019 * sl power type power equation y = 2 power_ck (1.8029e C 01 * w + 8.6499e C 01 * b C 5.9569 + 2.8970e C 03 * w * b) * vdd 2 * f power_csn (3.2494e C 03 * w + 8.7595e C 02 * b + 7.7824e C 01 + 2.6855e C 05 * w * b) * vdd 2 * f y = 4 power_ck (9.0149e C 02 * w + 1.7299 * b C 5.9569 + 2.8970e C 03 * w * b) * vdd 2 * f power_csn (1.6247e C 03 * w + 1.7519e C 01 * b + 7.7824e C 01 + 2.6855e C 05 * w * b) * vdd 2 * f < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word ba: number of banks (1 or 2) sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
STD80/stdm80 5-34 sec asic 3) size equation [unit: m m] width = 6 * ( log 2 (w / y) ) + 76.3 * ba + 4.4 (b * y / 4 + ba) + 6.75 * b * y + 2.25 [ m m] height = 297.5 + 9.35 * w / y + m [ m m] m = 5.75 (if y = 2, 4, 8, 16), m = 8.15 (if y = 32) stdm80 1) timing characteristics [unit: ns] y = 8 power_ck (4.5074e C 02 * w + 3.4599 * b C 5.9569 + 2.8970e C 03 * w * b) * vdd 2 * f power_csn (8.1236e C 04 * w + 3.5038e C 01 * b + 7.7824e C 01 + 2.6855e C 05 * w * b) * vdd 2 * f y = 16 power_ck (2.2537e C 02 * w + 6.9199 * b C 5.9569 + 2.8970e C 03 * w * b) * vdd 2 * f power_csn (4.0618e C 04 * w + 7.0076e C 01 * b + 7.7824e C 01 + 2.6855e C 05 * w * b) * vdd 2 * f y = 32 power_ck (1.1268e C 02 * w + 1.3839e + 01 * b C 5.9569 + 2.8970e C 03 * w * b) * vdd 2 * f power_csn (2.0309e C 04 * w + 1.4015 * b + 7.7824e C 01 + 2.6855e C 05* w * b) * vdd 2 * f timing type timing equation y = 2 tpc 7.56e C 03 * w + 1.75e C 02 * b / ba + 4.15e C 01 * s + 1.5587 trp 3.66e C 03 * w + 3.61e C 03 * b / ba C 9.61e C 02 * s + 1.8958 * 0.019 * sl + 3.5506 + 9.78e C 06 * w * b / ba C 2.65e C 04 * w * s C 9.07e C 04 * b / ba * s + 3.97e C 05 * w * 0.019 * sl C 2.35e C 04 * b / ba * 0.019 * sl C 2.86e C 03 * s * 0.019 * sl tacc 3.97e C 03 * w + 9.69e C 03 * b / ba + 8.90e C 01 * 0.019 * sl + 3.0333 y = 4 tpc 3.78e C 03 * w + 3.50e C 02 * b / ba + 4.15e C 01 * s + 1.5587 trp 1.83e C 03 * w + 7.22e C 03 * b / ba C 9.61e C 02 * s + 1.8958 * 0.019 * sl + 3.5506 + 9.78e C 06 * w * b / ba C 1.32e C 04 * w * s C 1.81e C 03 * b / ba * s + 1.98e C 05 * w * 0.019 * sl C 4.70e C 04 * b / ba * 0.019 * sl C 2.86e C 03 * s * 0.019 * sl tacc 1.98e C 03 * w + 1.93e C 02 * b / ba + 8.90e C 01 * 0.019 * sl + 3.0333 y = 8 tpc 1.89e C 03 * w + 7.00e C 02 * b / ba + 4.15e C 01 * s + 1.5587 trp 9.15e C 04 * w + 1.44e C 02 * b / ba C 9.61e C 02 * s + 1.8958 * 0.019 * sl + 3.5506 + 9.79e C 06 * w * b / ba C 6.64e C 05 * w * s C 3.63e C 03 * b / ba * s + 9.92e C 06 * w * 0.019 * sl C 9.41e C 04 * b / ba * 0.019 * sl C 2.86e -03 * s * 0.019 * sl tacc 9.93e C 04 * w + 3.87e C 02 * b / ba + 8.90e C 01 * 0.019 * sl + 3.0333 y = 16 tpc 9.46e C 04 * w + 1.40e C 01 * b / ba + 4.15e C 01 * s + 1.5587 trp 4.57e C 04 * w + 2.88e C 02 * b / ba C 9.61e C 02 * s + 1.8958 * 0.019 * sl + 3.5506 + 9.79e C 06 * w * b / ba C 3.32e C 05 * w * s C 7.26e C 03 * b / ba * s + 4.96e C 06 * w * 0.019 * sl C 1.88e C 03 * b / ba * 0.019 * sl C 2.86e C 03 * s * 0.019*sl tacc 4.96e C 04 * w + 7.75e C 02 * b / ba + 8.90e C 01 * 0.019 * sl + 3.0333 y = 32 tpc 4.73e C 04 * w + 2.80e C 01 * b / ba + 4.15e C 01 * s + 1.5587 power type power equation spsrama gen single-port synchronous ram generator C alternative
sec asic 5-35 STD80/stdm80 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 6 * ( log 2 (w / y) ) + 76.3 * ba + 4.4 (b * y / 4 + ba) + 6.75 * b * y + 2.25 [ m m] height = 297.5 + 9.35 * w / y + m [ m m] m = 5.75 (if y = 2, 4, 8, 16), m = 8.15 (if y = 32) trp 2.28e e 04 * w + 5.77e e 02 * b / ba e 9.61e e 02 * s + 1.8958 * 0.019 * sl + 3.5506 + 9.78e e 06 * w * b / ba e 1.66e e 05 * w * s e 1.45e e 02 * b / ba * s + 2.48e e 06 * w * 0.019 * sl e 3.76e e 03 * b / ba * 0.019 * sl e 2.86e e 03 * s * 0.019 * sl tacc 2.48e e 04 * w + 1.55e e 01 * b / ba + 8.90e e 01 * 0.019 * sl + 3.0333 power type power equation y = 2 power_ck (1.4598e C 01 * w + 8.2665e C 01 * b + 1.2695 + 4.0463e C 03 * w * b) * vdd 2 * f power_csn (3.1326e C 03 * w + 9.6584e C 02 * b + 6.3753e C 01 + 2.9811e C 05 * w * b) * vdd 2 * f y = 4 power_ck (7.2994e C 02 * w + 1.6533 * b + 1.2695 + 4.0463e C 03 * w * b) * vdd 2 * f power_csn (1.5663e C 03 * w + 1.9316e C 01 * b + 6.3753e C 01 + 2.9811e C 05 * w * b) * vdd 2 * f y = 8 power_ck (3.6497e C 02 * w + 3.3066 * b + 1.2695 + 4.0463e C 03 * w * b) * vdd 2 * f power_csn (7.8315e C 04 * w + 3.8633e C 01 * b + 6.3753e C 01 + 2.9811e C 05 * w * b) * vdd 2 * f y = 16 power_ck (1.8248e C 02 * w + 6.6132 * b + 1.2695 + 4.0463e C 03 * w * b) * vdd 2 * f power_csn (3.9157e C 04 * w + 7.7267e C 01 * b + 6.3753e C 01 + 2.9811e C 05 * w * b) * vdd 2 * f y = 32 power_ck (9.1243e C 03 * w + 1.3226e + 01 * b + 1.2695 + 4.0463e C 03 * w * b) * vdd 2 * f power_csn (1.9578e C 04 * w + 1.5453 * b + 6.3753e C 01 + 2.9811e C 05 * w * b) * vdd 2 * f timing type timing equation spsrama gen single-port synchronous ram generator C alternative
STD80/stdm80 5-36 sec asic spsrama gen single-port synchronous ram generator C alternative timing diagrams read cycle ck de?ned write cycle wen de?ned write cycle dout ck t as a t ah (csn / oen : low, di :dont care) hi-z t acc t da wen t wh stable t pc t rp valid dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di unknown t ds t dh stable t pc t rp stable t wp dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di unknown t ds t dh stable t pc t rp stable t wp
sec asic 5-37 STD80/stdm80 spsrama gen single-port synchronous ram generator C alternative ck de?ned read-modi?ed-write cycle wen de?ned read-modi?ed-write cycle csn control dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di valid t ds t dh stable t pc t rp stable t wp dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di valid t ds t dh stable t pc t rp stable t wp dout ck a csn (oen : low, wen / di : dont care) t cs t ch hi-z t as t ah t da t acc
STD80/stdm80 5-38 sec asic spsrama gen single-port synchronous ram generator C alternative oen control dout ck a oen (csn : low, wen / di : dont care) t os t oh t as t ah t acc t da hi-z
sec asic 5-39 STD80/stdm80 sparam gen single-port asynchronous ram generator logic symbol function description sparam is a single-port asynchronous static ram. when wen is high, just after the address (a [ ]) transition, dout [ ] presents data stored in the location addressed by a [ ]. upon wen rising edge, the value of di [ ] is written into the location addressed by a [ ]. csn is used to enable/disable the access. oen is used to enable/disable the data output driver. generators and cell con?gurations sparam generates layout, netlist, symbol and functional & timing model of a sparam. the layout of sparam is an automatically generated array of custom, pitch-matched leaf cells. there are four generator parameters to resolve the con?guration of a sparam. ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y) ? number of banks (ba). the valid range of these parameters is speci?ed in the following table: parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 16 32 64 128 max 1024 2048 4096 8192 step 8 16 32 64 bpw (b) ba = 1 min 1111 max 64 32 16 8 step 1111 ba = 2min2222 max 128 64 32 16 step 1111 csn wen oen a [m:0] di [bC1:0] sparamxmb dout [bC1:0] notes: 1. words (w) is the number of words in sparam. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. banks (ba) is the number of banks. 5. m = log 2 w e 1 features ? asynchronous operation ? address transition detectors ? write enable transition detector ? chip select transition detector ? stand-by (power down) mode available ? tri-state output ? separated data i/o ? low noise output circuit ? flexible aspect ratio ? optional dual bank capacity ? up to 128k bits capacity ? up to 8k number of words ? up to 128 number of bits per word
STD80/stdm80 5-40 sec asic sparam gen single-port asynchronous ram generator pin descriptions pin capacitance (unit = sl) application notes 1) fitting the layout shape (aspect ratio) layout shape can be ?tted by choosing one of 4 ymux parameters in the above con?guration table in accordance with your chip level layout design preference. larger one makes the layout shape ?at and short. smaller one makes it thin and tall. in general, ?at and short sparam is faster than thin and tall one. 2) selecting number of banks the maximum capacity of sparam (ba=1) reaches to 64k. it can be doubled by setting the bank parameter (ba) 2 and the bpw double. in that case, note that the words can't be doubled. by the way, the bank parameter ba=2 can be applied to the con?guration smaller than 64k. please refer to the con?guration table above. sparam (ba=2) is a little bigger than sparam(ba=1) for the same capacity. name i/o description csn i "chip select negative" acts as the memory enable signal for selecting one of multiple memory blocks. when csn is high, dout[ ] goes to hi-z state, the memory goes to stand-by (power down) mode and no access to the memory can occur. conversely, if csn is low only then may a read or write access occur. when csn falls, a read access is initiated. csn should be stable when wen is low. wen i "write enable negative" selects the type of memory access. when wen is high, the sparam is in read mode. otherwise, it is in write mode. upon the rising edge of wen, a write access completed and a read access initiated. when wen is low, a[ ] and csn should be stable. oen i "output enable negative" unconditionally enables or disables the output drivers. a [ ] i "address" selects the location to be accessed. when a[ ] changes, the transition is detected and the internal clock pulse will be generated. a[ ] should be stable when wen is low. di [ ] i when wen rises, the "data in" word value is written to the location addressed. dout [ ] o during a read access, the data word stored will be presented to the "data out" ports. dout[ ] is tri-statable. when csn is low and oen is low, only then, dout[ ] drives a certain value. otherwise, dout[ ] keeps hi-z state. during a write access, the data on dout is unpredictable. csn wen oen a di dout ymux 4 ymux 8 ymux 16 ymux 32 1-bank 9.7 4.2 0.7 4.2 1.9 5.5 11.7 24.1 49.0 2-bank 19.3 8.4 1.3 4.2 1.9 5.5 11.7 24.1 49.0
sec asic 5-41 STD80/stdm80 sparam gen single-port asynchronous ram generator block diagrams (1 bank) < 1-bank > < 2-bank > ram core y dec. & sense amp i/o drivers di [ ] x dec. word dout [ ] wen a [ ] csn oen line drv. address buffer control logic & at d & ram core address buffer control logic di [ ] x dec. word dout [ ] line drv. & (left) word line drv. ram core di [ ] dout [ ] (right) wen a [ ] csn oen y dec. & sense amp (left) i/o driver (left) column muxs and i/o drivers (right) sense (right)
STD80/stdm80 5-42 sec asic sparam gen single-port asynchronous ram generator characteristic reference table STD80 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing (typical process, 5v, 25 o c, output load = 10sl, input slope = 0.2 ns unit = ns) t acc access time 5.6 5.6 5.9 5.9 6.3 6.3 t da deaccess time 0.7 0.7 0.7 0.7 0.7 0.7 t dz active to hi-z 1.2 1.2 1.2 1.2 1.2 1.2 t zd hi-z to active 1.6 1.6 1.6 1.6 1.6 1.6 t as address setup time 0.1 0.1 0.1 0.1 0.1 0.1 t ah address hold time 1.1 1.0 1.2 1.0 1.3 1.1 t ds input data setup time 0.6 0.6 0.7 0.8 0.9 1.2 t dh input data hold time 0.8 0.8 1.0 0.8 1.4 1.0 t wen min. wen pulse width low 2.6 2.6 2.7 2.7 2.9 2.9 t cs csn setup time 0.1 0.1 0.1 0.1 0.1 0.1 t ch csn hold time 0.9 0.9 0.9 0.9 0.9 0.9 size ( m m) width 723 891 1206 1374 2172 2340 height 972 972 1577 1577 2786 2786 power ( m w/mhz) power_add (normal mode: csn low) 2825 5250 11350 power_csn (stand-by mode: csn high) 250 455 862
sec asic 5-43 STD80/stdm80 sparam gen single-port asynchronous ram generator characteristic reference table (cont.) stdm80 symbol description 256x16m4 1024x16m8 4kx16m16 1-ba 2-ba 1-ba 2-ba 1-ba 2-ba timing (typical process, 3.3v, 25 o c, output load = 10sl, input slope = 0.2 ns unit = ns) t acc access time 8.3 8.3 8.7 8.7 9.4 9.4 t da deaccess time 0.9 0.9 0.9 0.9 0.9 0.9 t dz active to hi-z 1.8 1.8 1.8 1.8 1.8 1.8 t zd hi-z to active 2.2 2.2 2.2 2.2 2.2 2.2 t as address setup time 0.1 0.1 0.1 0.1 0.1 0.1 t ah address hold time 1.4 1.4 1.5 1.4 1.7 1.4 t ds input data setup time 0.8 0.9 1.0 1.2 1.3 1.7 t dh input data hold time 1.1 1.0 1.4 1.1 1.8 1.4 t wen min. wen pulse width low 4.0 4.0 4.1 4.1 4.3 4.3 t cs csn setup time 0.1 0.1 0.1 0.1 0.1 0.1 t ch csn hold time 1.7 1.7 1.7 1.7 1.7 1.7 size ( m m) width 723 891 1206 1374 2172 2340 height 972 972 1577 1577 2786 2786 power ( m w/mhz) power_add (normal mode: csn low) 1262 2395 5618 power_csn (stand-by mode: csn high) 163 304 577
STD80/stdm80 5-44 sec asic sparam gen single-port asynchronous ram generator characteristic equation tables STD80 (typical process, 5v, 25 o c) 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] notes: 1. power_add : this is a normal mode power of memory. when csn is low. 2. power_csn : this is a standby mode power of memory. when csn is high. 3) size equation [unit: m m] width = 12*(log2(w/y))+170*ba+7.55*(b*y)-5 height = 366.7+9.45*w/y timing type timing equation y = 4 tacc (9.15e-04*w+4.93e-02*s+1.59e-01*sl*0.019+5.33) twen (4.24e-04*w+2.12e-01*s+2.36-3.57e-06*w*s) y = 8 tacc (4.57e-04*w+4.93e-02*s+1.59e-01*sl*0.019+5.33) twen (2.12e-04*w+2.12e-01*s+2.36-1.78e-06*w*s) y = 16 tacc (2.28e-04*w+4.93e-02*s+1.59e-01*sl*0.019+5.33) twen (1.06e-04*w+2.12e-01*s+2.36-8.93e-07*w*s) y = 32 tacc (1.14e-04*w+4.93e-02*s+1.59e-01*sl*0.019+5.33) twen (5.30e-05*w+2.12e-01*s+2.36-4.46e-07*w*s) power type power equation y = 4 power_add (2.9072e-02*w+3.4109*b+3.5237e+01 +3.8993e-03*w*b)*vdd 2 *f power_csn (1.5442e-02*w+2.5843e-01*b+2.0571 +6.8027e-07*w*b)*vdd 2 *f y = 8 power_add (1.5487e-02*w+5.7627*b+3.5725e+01 +4.0492e-03*w*b)*vdd 2 *f power_csn (7.7211e-03*w+5.1686e-01*b+2.0571 +6.8026e-07*w*b)*vdd 2 *f y = 16 power_add (5.8213e-03*w+1.1800e+01*b+4.1049e+01 +3.0633e-03*w*b)*vdd 2 *f power_csn (3.8605e-03*w+1.0337*b+2.0571 +6.8026e-07*w*b)*vdd 2 *f y = 32 power_add (2.4814e-03*w+2.3136e+01*b+4.2708e+01 +3.1289e-03*w*b)*vdd 2 *f power_csn (1.9302e-03*w+2.0674*b+2.0571 +6.8026e-07*w*b)*vdd 2 *f < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word ba: number of banks (1 or 2) sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
sec asic 5-45 STD80/stdm80 sparam gen single-port asynchronous ram generator stdm80 (typical process, 3.3v, 25 o c) 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] notes: 1. power_add : this is a normal mode power of memory. when csn is low. 2. power_csn : this is a standby mode power of memory. when csn is high. 3) size equation [unit: m m] width = 12*(log2(w/y))+170*ba+7.55*(b*y)-5 height = 366.7+9.45*w/y timing type timing equation y = 4 tacc (1.35e-03*w+8.73e-02*s+1.93e-01*sl*0.019+7.89) twen (4.77e-04*w+2.91e-01*s+3.69-2.98e-05*w*s) y = 8 tacc (6.76e-04*w+8.73e-02*s+1.93e-01*sl*0.019+7.89) twen (2.38e-04*w+2.91e-01*s+3.69-1.49e-05*w*s) y = 16 tacc (3.38e-04*w+8.73e-02*s+1.93e-01*sl*0.019+7.89) twen (1.19e-04*w+2.91e-01*s+3.69-7.47e-06*w*s) y = 32 tacc (1.69e-04*w+8.73e-02*s+1.93e-01*sl*0.019+7.89) twen (5.97e-05*w+2.91e-01*s+3.69-3.73e-06*w*s) power type power equation y = 4 power_add (2.7532e-02*w+3.8304*b+3.0565e+01 +4.1607e-03*w*b)*vdd 2 *f power_csn (1.4978e-02*w+5.8712e-01*b+2.5513 -2.2987e-05*w*b)*vdd 2 *f y = 8 power_add (1.8626e-02*w+6.6841*b+3.0143e+01 +3.8965e-03*w*b)*vdd 2 *f power_csn (7.4892e-03*w+1.1742*b+2.5513 -2.2987e-05*w*b)*vdd 2 *f y = 16 power_add (4.5158e-03*w+1.2019e+01*b+4.0375e+01 +4.0406e-03*w*b)*vdd 2 *f power_csn (3.7446e-03*w+2.3484*b+2.5513 -2.2987e-05*w*b)*vdd 2 *f y = 32 power_add (1.7548e-03*w+2.3408e+01*b+4.2508e+01 +4.1451e-03*w*b)*vdd 2 *f power_csn (1.8723e-03*w+4.6969*b+2.5513 -2.2987e-05*w*b)*vdd 2 *f
STD80/stdm80 5-46 sec asic sparam gen single-port asynchronous ram generator timing diagrams basic read timing csn controlled read timing oen controlled read timing (wen = high; csn, oen = low) a dout t acc t da t acc t da a t acc t dz csn hi-z (wen = high; oen = low) dout hi-z n1 n2 n3 n1 n2 n3 t zd a t dz oen dout t zd hi-z hi-z n1 n2 n3 n1 n2 n3 (wen = high; csn = low)
sec asic 5-47 STD80/stdm80 sparam gen single-port asynchronous ram generator basic write timing read-write-read timing (when t1, t2 > tacc) (oen = dont care) a di t dh csn t as t ah wen t cs t ch t wen t ds stable (csn, oen = low) a di t dh t1 t2 wen t ds dx dout dx t acc t da t acc t acc valid stable
STD80/stdm80 5-48 sec asic dpsram gen dual-port synchronous ram generator logic symbol function description dpsram is a dual-port synchronous static ram. when ck1 rises, if wen1 is high, dout1 [ ] presents data stored in the location addressed by a1 [ ], otherwise the value of di1 [ ] is written into the location addressed by a1 [ ]. csn1 is used to enable/disable ck1. oen1 is used to enable/disable tri-state drivers of dout1 [ ]. the functionality of port2 is the same to port1. the port1 and port2 function independently each other. generators and cell con?gurations dpsram gen. generates layout, netlist, symbol and functional & timing model of dpsram. the layout of dpsram is an automatically generated array of custom, pitch-matched leaf cells. to customize the con?guration of dpsram, you can give certain values to following three generator parameters: ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y). the valid range of these parameters is speci?ed in the following table: parameters ymux = 2 ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 4 8 16 32 64 max 512 1024 2048 4096 8192 step 2 4 8 16 32 bpw (b) min 1 1 1 1 1 max 128 64 32 16 8 step 1 1 1 1 1 notes: 1. words (w) is the number of words in dpsram. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. m = log 2 w e 1 ck1 ck2 csn1 csn2 wen1 dpsramxm dout1 [bC1:0] wen2 oen1 oen2 a1 [m:0] a2 [m:0] di1 [bC1:0] di2 [bC1:0] dout2 [bC1:0] features ? synchronous operation ? read initiated at rising edge of clock ? write completed at rising edge of clock ? stand-by (power down) mode available ? tri-state output ? separated data i/o ? low noise output circuit ? flexible aspect ratio ? up to 64k bits capacity ? up to 8k number of words ? up to 128 number of bits per word
sec asic 5-49 STD80/stdm80 dpsram gen dual-port synchronous ram generator pin descriptions pin capacitance (unit = sl) application notes 1) putting busholders on dout1 [ ] and dout2 [ ] as you will see in the timing diagrams, dout1 [ ] (dout2 [ ]) is valid only when ck1 (ck2) is high. if you want dout1 [ ] (dout2 [ ]) to be stable regardless of ck1 (ck2) state, you should put STD80/stdm80 busholder cells on the dout1 [ ] (dout2 [ ]) bus externally. 2) customizing aspect ratio aspect ratio is programmable using low address decoder types. as you can see in the con?guration table, there are up to 5 selections of ymux for the same words and the same bpw dpsram. you can choose one of them in accordance with your chip level layout preference. larger ymux means fatter and shorter aspect ratio and smaller ymux means thinner and taller aspect ratio. as you can see in the characteristic tables, aspect ratio affects major characteristics of dpsram, in general, larger ymux dpsram has faster speed and bigger area than smaller ymux dpsram. 3) contention modes simultaneous accesses to the same location through both ports cause a contention. dpsram has no contention preventing scheme. you have to take care of the contention modes. please refer to the timing diagrams of contention modes to get more information of contention modes. name i/o description ck1 ck2 i clocks serve as input clocks to each port of the memory block. when ck1 (ck2) is low, port1 (port2) is in a precharge state. upon the rising edge, an access begins. csn1 csn2 i chip select negatives act as each ports enable signal for selections of multiple blocks on a common clock. when csn1 (csn2) is high, port1 (port2) goes to stand-by (power down) mode and no access can occur, conversely, if low only then may a read or write access occur. csn1 (csn2) may not change during ck1 (ck2) is high. wen1 wen2 i write enable negatives select the type of memory access. read is the high state, and write is the low state. oen1 oen2 i output enable negatives control the output drivers from driven to tri-state condi- tion. oen1 (oen2) may not change during ck1 (ck2) is high. a1 [ ] a2 [ ] i addresses select the location to be accessed. a1 [ ] (a2 [ ]) may not change during ck1 (ck2) is high. di1 [ ] di2 [ ] i when ck1 (ck2) rises while wen1 (wen2) is low, the data in word value is written to the accessed location. dout1 [ ] dout2 [ ] o during a read access, data word stored will be presented to the data out ports. dout1 [ ] and dout2 [ ] are tri-statable. only when ck1 (ck2) is high, csn1 (csn2) and oen1 (oen2) is low, dout1 [ ] (dout2 [ ]) drives a certain value. otherwise, dout1 [ ] (dout2 [ ]) keeps hi-z state. during a write access, data word written will be presented at the data out ports if output driver is enabled. ck csn wen oen a di dout ymux 2 ymux 4 ymux 8 ymux 16 ymux 32 5.8 1.9 0.9 2.3 1.0 2.0 5.4 5.4 12.0 25.0 51.0
STD80/stdm80 5-50 sec asic dpsram gen dual-port synchronous ram generator block diagram ram core word y dec. & sense amp i/o driver x dec. control logic & a2 [m:0] ck2 oen2 address buffer port1 dout1 [bC1:0] di1 [bC1:0] a1 [m:0] di2 [bC1:0] dout2 [bC1:0] wen1 wen2 ck1 csn1 csn2 oen1 liine drv. port1 port1 word x dec. liine drv. port2 port2 control logic & address buffer port2
sec asic 5-51 STD80/stdm80 dpsram gen dual-port synchronous ram generator characteristic reference table STD80 symbol description 256x16m4 1024x16m8 4kx16m16 timing requirements & delay (typical process, 5v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 2.20 2.70 3.90 minckh minimum clock pulse width high 4.10 4.40 5.20 t cc clock to clock setup time 3.10 4.10 6.30 t as address setup time 0.34 0.54 0.77 t ah address hold time 0.48 0.43 0.33 t cs csn setup time 0.45 0.45 0.45 t ch csn hold time 0 0 0 t ds data input setup time 0 0 0 t dh data input hold time 3.10 3.90 5.40 t os oen setup time 0 0 0 t oh oen hold time 1.25 1.35 1.55 t ws wen setup time 0 0 0 t wh wen hold time 0 0 0 t acc access time 3.10 3.80 5.10 t da deaccess time 1.90 2.10 2.40 mincyc minimum clock cycle time 6.70 8.60 12.50 size ( m m) width 996 1787 3353 height 1110 1802 3194 power ( m w/mhz) power_ck (normal mode: csn low) 1632 3150 6512 power_csn (stand-by mode: csn high) 250 475 900
STD80/stdm80 5-52 sec asic dpsram gen dual-port synchronous ram generator characteristic reference table (cont.) stdm80 symbol description 256x16m4 1024x16m8 4kx16m16 timing requirements & delay (typical process, 3.3v, 25 o c, output load = 10sl, unit = ns) minckl minimum clock pulse width low 3.00 3.80 5.40 minckh minimum clock pulse width high 5.50 6.40 7.90 t cc clock to clock setup time 4.20 5.60 8.40 t as address setup time 0.37 0.67 1.20 t ah address hold time 0.58 0.54 0.50 t cs csn setup time 0.56 0.56 0.56 t ch csn hold time 0 0 0 t ds data input setup time 0 0 0 t dh data input hold time 4.30 5.20 7.20 t os oen setup time 0 0 0 t oh oen hold time 1.90 2.00 2.30 t ws wen setup time 0 0 0 t wh wen hold time 0 0 0 t acc access time 4.50 5.40 7.10 t da deaccess time 2.40 2.60 3.00 mincyc minimum clock cycle time 9.90 12.90 18.90 size ( m m) width 996 1787 3353 height 1110 1802 3194 power ( m w/mhz) power_ck (normal mode: csn low) 762 1546 3659 power_csn (stand-by mode: csn high) 108 206 435
sec asic 5-53 STD80/stdm80 dpsram gen dual-port synchronous ram generator characteristic equation tables STD80 1) timing characteristics [unit: ns] timing type timing equation y = 2 minckh (2.3646e C 03 * w + 2.8351e C 03 * b + 9.8324e C 01 * 0.019 * sl + 1.2350 + 2.1938e C 05 * w * b C 6.3558e C 04 * w * 0.019 * sl C 2.4658e C 03 * b * 0.019 * sl) minckl (3.0467e C 03 * w + 5.8227e C 03 * b + 1.5699 + 1.7795e C 07 * w * b) mincyc (1.18e C 02 * w + 7.9429e C 03 * b C 1.4125e C 01 * 0.019 * sl + 3.5681 + 1.3689e C 01 * 0.019 * sl * 0.019 * sl) * 1.1 tacc (3.1469e C 03 * w + 6.8856e C 03 * b + 1.4939e C 01 * s + 3.6108e C 01 * 0.019 * sl + 2.3066) y = 4 minckh (1.1823e C 03 * w + 5.6702e C 03 * b + 9.8324e C 01 * 0.019 * sl + 1.2350 + 2.1938e C 05 * w * b C 3.1779e C 04 * w * 0.019 * sl C 4.9317e C 03 * b * 0.019 * sl) minckl (1.5233e C 03 * w + 1.1645e C 02 * b + 1.5699 + 1.7796e C 07 * w * b) mincyc (5.94e C 03 * w + 1.5885e C 02 * b C 1.4125e C 01 * 0.019 * sl + 3.5681 + 1.3689e C 01 * 0.019 * sl * 0.019 * sl) * 1.1 tacc (1.5734e C 03 * w + 1.3771e C 02 * b + 1.4939e C 01 * s + 3.6108e C 01 * 0.019 * sl + 2.3066) y = 8 minckh (6.1758e C 04 * w + 1.3960e C 02 * b + 7.2178e C 01 * 0.019 * sl + 1.4573) minckl (7.6168e C 04 * w + 2.3291e C 02 * b + 1.5699 + 1.7794e C 07 * w * b) mincyc (2.97e C 03 * w + 3.1771e C 02 * b C 1.4125e C 01 * 0.019 * sl + 3.5681 + 1.3689e C 01 * 0.019 * sl * 0.019 * sl) * 1.1 tacc (7.8672e C 04 * w + 2.7542e C 02 * b + 1.4939e C 01 * s + 3.6108e C 01 * 0.019 * sl + 2.3066) y = 16 minckh (4.9053e C 04 * w + 2.5687e C 02 * b + 8.1759e C 01 * 0.019 * sl + 1.4633 C 7.5634e C 06 * w * b C 6.0306e C 05 * w * 0.019 * sl + 4.8660e C 03 * b * 0.019 * sl) minckl (3.8084e C 04 * w + 4.6582e C 02 * b + 1.5699 + 1.7794e C 07 * w * b) mincyc (1.48e C 03 * w + 6.3543e C 02 * b C 1.4125e C 01 * 0.019 * sl + 3.5681 + 1.3689e C 01 * 0.019 * sl * 0.019 * sl) *1.1 tacc (3.9701e C 04 * w + 5.7737e C 02 * b + 1.4501e C 01 * s + 1.5318e C 01 * 0.019 * sl + 2.2527) y = 32 minckh (1.4662e C 04 * w + 4.1246e C 02 * b + 8.0560e C 01 * 0.019 * sl + 2.0499) minckl (1.9042e C 04 * w + 9.3164e C 02 * b + 1.5699 + 1.7791e C 07 * w * b) mincyc (7.43e C 04 * w + 1.2708e C 01 * b C 1.4125e C 01 * 0.019 * sl + 3.5681 + 1.3689e C 01 * 0.019 * sl * 0.019 * sl) * 1.1 < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
STD80/stdm80 5-54 sec asic 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 16.6 * ( log2 (w / y) ) + 12.1 * b * y + 121.7 [ m m] height = 404.95 + 10.85 * w/y + m [ m m] (m = 8.15 (if y = 2, 8), m = 10.55 (if y = 4, 16), m = 12.95 (if y = 32)) stdm80 1) timing characteristics [unit: ns] tacc (1.9668e C 04 * w + 1.1017e C 01 * b + 1.4939e C 01 * s + 3.6108e C 01 * 0.019 * sl + 2.3066) power type power equation y = 2 power_ck (2.0763e C 01 * w + 1.1277 * b + 3.1186 C 1.0486e C 04 * w * b) * vdd 2 * f power_csn (1.0551e C 02 * w + 2.4929e C 01 * b + 9.5587e C 01 C 3.1253e C 05 * w * b) * vdd 2 * f y = 4 power_ck (1.0381e C 01 * w + 2.2555 * b + 3.1186 C 1.0486e C 04 * w * b) * vdd 2 * f power_csn (5.2757e C 03 * w + 4.9858e C 01 * b + 9.5587e C 01 C 3.1253e C 05 * w * b) * vdd 2 * f y = 8 power_ck (4.9408e C 02 * w + 3.5969 * b + 4.6093 + 8.6446e C 04 * w * b) * vdd 2 * f power_csn (2.6378e C 03 * w + 9.9716e C 01 * b + 9.5587e C 01 C 3.1253e C 05 * w * b) * vdd 2 * f y = 16 power_ck (2.4666e C 02 * w + 6.0326 * b + 4.9311 + 8.8607e C 04 * w * b) * vdd 2 * f power_csn (1.3189e C 03 * w + 1.9943 * b + 9.5587e C 01 C 3.1253e C 05 * w * b) * vdd 2 * f y = 32 power_ck (1.2221e C 02 * w + 1.0298e + 01 * b + 5.7362 + 7.6259e C 04 * w * b) * vdd 2 * f power_csn (6.5946e C 04 * w + 3.9886 * b + 9.5587e C 01 C 3.1253e C 05 * w * b) * vdd 2 * f timing type timing equation y = 2 minckh (4.1092e C 03 * w + 4.0747e C 03 * b + 9.0315e C 01 * 0.019 * sl + 2.2883) minckl (4.1417e C 03 * w + 7.9201e C 03 * b + 2.2145 + 1.1253e C 06 * w * b) mincyc (2.1473e C 02 * w + 5.8971e C 03 * b + 5.9619e C 01 * 0.019 * sl + 4.6027 C 6.1247e C 04 * w * 0.019 * sl) * 1.1 tacc (4.1701e C 03 * w + 9.8971e C 03 * b + 1.7063e C 01 * s + 4.3595e C 01 * 0.019 * sl + 3.3675) y = 4 minckh (2.0546e C 03 * w + 8.1494e C 03 * b + 9.0315e C 01 * 0.019 * sl + 2.2883) minckl (2.0708e C 03 * w + 1.5840e C 02 * b + 2.2145 + 1.1253e C 06 * w * b) mincyc (1.0736e C 02 * w + 1.1794e C 02 * b + 5.9619e C 01 * 0.019 * sl + 4.6027 C 3.0623e C 04 * w * 0.019 * sl) * 1.1 tacc (2.0850e C 03 * w + 1.9794e C 02 * b + 1.7063e C 01 * s + 4.3595e C 01 * 0.019 * sl + 3.3675) timing type timing equation dpsram gen dual-port synchronous ram generator
sec asic 5-55 STD80/stdm80 2) power characteristics [unit: m w] 3) size equation [unit: m m] width = 16.6 * ( log 2 (w / y) ) + 12.1 * b * y + 121.7 [ m m] height = 404.95 + 10.85 * w / y + m [ m m] (m = 8.15 (if y = 2, 8), m = 10.55 (if y = 4, 16), m = 12.95 (if y = 32)) y = 8 minckh (5.6171e C 04 * w C 1.3181e C 02 * b + 6.8946e C 01 * 0.019 * sl + 2.8571 + 2.7457e C 05 * w * b + 1.1695e C 04 * w * 0.019 * sl + 9.4850e C 03 * b * 0.019 * sl) minckl (1.0354e C 03 * w + 3.1680e C 02 * b + 2.2145 + 1.1253e C 06 * w * b) mincyc (5.3684e C 03 * w + 2.3588e C 02 * b + 5.9619e C 01 * 0.019 * sl + 4.6027 C 1.5311e C 04 * w * 0.019 * sl) * 1.1 tacc (1.0425e C 03 * w + 3.9588e C 02 * b + 1.7063e C 01 * s + 4.3595e C 01 * 0.019 * sl + 3.3675) y = 16 minckh (5.1367e C 04 * w + 3.1572e C 02 * b + 9.3585e C 01 * 0.019 * sl + 2.6593) minckl (5.1771e C 04 * w + 6.3361e C 02 * b + 2.2145 + 1.1253e C 06 * w * b) mincyc (2.6842e C 03 * w + 4.7177e C 02 * b + 5.9619e C 01 * 0.019 * sl + 4.6027 C 7.6559e C 05 * w * 0.019 * sl) * 1.1 tacc (5.2127e C 04 * w + 7.9177e C 02 * b + 1.7063e C 01 * s + 4.3595e C 01 * 0.019 * sl + 3.3675) y = 32 minckh (2.4832e C 04 * w + 6.6898e C 02 * b + 9.2358e C 01 * 0.019 * sl + 3.1671) minckl (2.5885e C 04 * w + 1.2672e C 01 * b + 2.2145 + 1.1253e C 06 * w * b) mincyc (1.3421e C 03 * w + 9.4355e C 02 * b + 5.9619e C 01 * 0.019 * sl + 4.6027 C 3.8279e C 05 * w * 0.019 * sl) * 1.1 tacc (2.6063e C 04 * w + 1.5835e C 01 * b + 1.7063e C 01 * s + 4.3595e C 01 * 0.019 * sl + 3.3675) power type power equation y = 2 power_ck (1.6148e C 01 * w + 9.5794e C 01 * b + 9.7215 + 2.3042e C 03 * w * b) * vdd 2 * f power_csn (7.3480e C 03 * w + 2.3132e C 01 * b + 1.7751 + 7.5474e C 05 * w * b) * vdd 2 * f y = 4 power_ck (8.0741e C 02 * w + 1.9158 * b + 9.7215 + 2.3042e C 03 * w * b) * vdd 2 * f power_csn (3.6740e C 03 * w + 4.6264e C 01 * b + 1.7751 + 7.5474e C 05 * w * b) * vdd 2 * f y = 8 power_ck (4.0704e C 02 * w + 3.0779 * b + 1.1325e + 01 + 2.4858e C 03 * w * b) * vdd 2 * f power_csn (1.8370e C 03 * w + 9.2529e C 01 * b + 1.7751 + 7.5474e C 05 * w * b) * vdd 2 * f y = 16 power_ck (2.1023e C 02 * w + 5.0567 * b + 9.5773 + 2.4457e C 03 * w * b) * vdd 2 * f power_csn (9.1850e C 04 * w + 1.8505 * b + 1.7751 + 7.5474e C 05 * w * b) * vdd 2 * f y = 32 power_ck (1.0031e C 02 * w + 7.8426 * b + 1.0827e + 01 + 2.6112e C 03 * w * b) * vdd 2 * f power_csn (4.5925e C 04 * w + 3.7011 * b + 1.7751 + 7.5474e C 05 * w * b) * vdd 2 * f timing type timing equation dpsram gen dual-port synchronous ram generator
STD80/stdm80 5-56 sec asic dpsram gen dual-port synchronous ram generator timing diagrams read cycle write cycle csn control dout ck t as a t ah minckl (csn / oen : low) minckh hi-z t acc t da wen t ws t wh mincyc dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen t ws t wh di t ds t dh dout ck a csn (oen : low) t cs t ch hi-z t acc
sec asic 5-57 STD80/stdm80 dpsram gen dual-port synchronous ram generator oen control function diagrams readCwrite contention (t < t cc ; oen, csn = low) dout ck a oen (csn : low) t os t oh t acc ax ax t hi-z hi-z dx unknown dx a1 a2 ck1 ck2 wen1 wen2 di2 dout1 dout2
STD80/stdm80 5-58 sec asic dpsram gen dual-port synchronous ram generator writeCread contention (t < t cc ; oen, csn = low) writeCwrite contention (t < t cc ; oen, csn = low) ax ax t hi-z hi-z dx unknown dx a1 a2 ck1 ck2 wen1 wen2 di1 dout1 dout2 ax ax t hi-z hi-z unknown dx a1 a2 ck1 ck2 wen1 wen2 di1 dout1 dout2 dy unknown di2
sec asic 5-59 STD80/stdm80 dpsrama gen dual-port synchronous ram generator C alternative logic symbol function description dpsrama is a dual-port synchronous static ram. when wen1 is high and ck1 rises, dout1 [ ] presents data stored in the location addressed by a1 [ ]. when wen1 is low and ck1 falls, or when ck1 is high and wen1 rises, the value of di1 [ ] is written into the location addressed by a1 [ ]. csn1 is used to enable/disable ck1. oen1 is used to enable/disable tri-state drivers of dout1 [ ]. the functionality of port2 is the same to port1. the port1 and port2 function independently each other. dpsrama is an alternative of dpsram. the major difference of these two rams is the timing of read and write. dpsrama reads and writes at different edge of the clock since dpsram reads and writes at the same edge of the clock. generators and cell con?gurations dpsrama gen. generates layout, netlist, symbol and functional & timing model of dpsrama. the layout of dpsrama is an automatically generated array of custom, pitch-matched leaf cells. to customize the con?guration of dpsrama, you can give certain values to following three generator parameters: ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y). the valid range of these parameters is speci?ed in the following table: parameters ymux = 2 ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 4 8 16 32 64 max 512 1024 2048 4096 8192 step 2 4 8 16 32 bpw (b) min 1 1 1 1 1 max 128 64 32 16 8 step 1 1 1 1 1 notes: 1. words (w) is the number of words in dpsrama. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. m = log 2 w e 1 ck1 ck2 csn1 csn2 wen1 dpsramaxm dout1 [bC1:0] wen2 oen1 oen2 a1 [m:0] a2 [m:0] di1 [bC1:0] di2 [bC1:0] dout2 [bC1:0] features ? synchronous operation ? read initiated at rising edge of clock ? write completed at falling edge of clock ? possible read modi?ed write cycle ? stand-by (power down) mode available ? tri-state output ? separated data i/o ? low noise output circuit ? possible bi-directional operation ? flexible aspect ratio ? up to 64k bits capacity ? up to 8k number of words ? up to 128 number of bits per word
STD80/stdm80 5-60 sec asic dpsrama gen dual-port synchronous ram generator C alternative pin descriptions pin capacitance (unit = sl) name i/o description ck1 ck2 i clocks serve as input clocks to each port of the memory block. when ck1 (ck2) is low, port1 (port2) is in a precharge state. upon the rising edge, a read cycle begins. upon the falling edge, a write cycle ends. csn1 csn2 i chip select negatives act as each ports enable signal for selections of multiple blocks on a common clock. when csn1 (csn2) is high, port1 (port2) goes to stand-by (power down) mode and no access can occur, conversely, if low only then may a read or write access occur. csn1 (csn2) may not change during ck1 (ck2) is high. wen1 wen2 i write enable negatives select the type of memory access. read is the high state, and write is the low state. oen1 oen2 i output enable negatives control the output drivers from driven to tri-state condition. oen1 (oen2) may not change during ck1 (ck2) is high. a1 [ ] a2 [ ] i addresses select the location to be accessed. a1 [ ] (a2 [ ]) may not change during ck1 (ck2) is high. di1 [ ] di2 [ ] i when ck1 (ck2) falls while wen1 (wen2) is low, or when wen1 (wen2) rises while ck1 (ck2) is high, the data in word value is written to the accessed location. dout1 [ ] dout2 [ ] o during a read access, data word stored will be presented to the data out ports. dout1 [ ] and dout2 [ ] are tri-statable. when ck1 (ck2) is high, csn1 (csn2) is low and oen1 (oen2) is low, only then, dout1 [ ] (dout2 [ ]) drives a certain value. otherwise, dout1 [ ] (dout2 [ ]) keeps hi-z state. during a write access, the value of dout1 [ ] (dout2 [ ]) is unpredictable. ck csn wen oen a di dout ymux 2 ymux 4 ymux 8 ymux 16 ymux 32 5.8 1.9 0.9 2.3 1.0 2.0 5.4 5.4 12.0 25.0 51.0
sec asic 5-61 STD80/stdm80 dpsrama gen dual-port synchronous ram generator C alternative application notes 1) putting busholders on dout1 [ ] and dout2 [ ] as you will see in the timing diagrams, dout1 [ ] (dout2 [ ]) is valid only when ck1 (ck2) is high. if you want dout1 [ ] (dout2 [ ]) to be stable regardless of ck1 (ck2) state, you should put STD80/stdm80 busholder cells on the dout1 [ ] (dout2 [ ]) bus externally. 2) customizing aspect ratio aspect ratio is programmable using low address decoder types. as you can see in the con?guration table, there are up to 5 selections of ymux for the same words and the same bpw dpsrama. you can choose one of them in accordance with your chip level layout preference. larger ymux means fatter and shorter aspect ratio and smaller ymux means thinner and taller aspect ratio. as you can see in the characteristic tables, aspect ratio affects major characteristics of dpsram, in general, larger ymux dpsrama has faster speed and bigger area than smaller ymux dpsrama. 3) contention modes simultaneous accesses to the same location through both ports cause a contention. dpsrama has no contention preventing scheme. you have to take care of the contention modes. please refer to the timing diagrams of contention modes to get more information of contention modes. 4) using bi-directional data port because having the same phase, di1 [ ] (di2 [ ]) and dout1 [ ] (dout2 [ ]) of dpsrama can be tied directly. with tying them up together and controlling wen1 (wen2) and oen1 (oen2) properly, you can use them as bi-directional data ports. block diagram ram core word y dec. & sense amp i/o driver x dec. control logic & a2 [m:0] ck2 oen2 address buffer port1 dout1 [bC1:0] di1 [bC1:0] a1 [m:0] di2 [bC1:0] dout2 [bC1:0] wen1 wen2 ck1 csn1 csn2 oen1 liine drv. port1 port1 word x dec. liine drv. port2 port2 control logic & address buffer port2
STD80/stdm80 5-62 sec asic dpsrama gen dual-port synchronous ram generator C alternative characteristic reference table STD80 symbol description 256x16m4 1024x16m8 4kx16m16 timing requirements & delay (typical process, 5v, 25 o c, output load = 10sl, unit = ns) t rp minimum read pulse width 3.40 4.00 5.00 t pc minimum pre-charge period 3.70 5.29 10.5 t wp minimum write pulse width 1.63 2.29 3.51 t rwc read-write contention 1.17 1.75 2.92 t wrc write-read contention 0 0 0 t wwc write-write contention 1.12 1.92 3.44 t as address setup time 0.44 0.65 0.87 t ah address hold time 1.11 1.91 2.20 t cs csn setup time 0.48 0.48 0.48 t ch csn hold time 0 0 0 t ds data input setup time 1.22 1.76 2.84 t dh data input hold time 1.42 1.72 2.31 t os oen setup time 0 0 0 t oh oen hold time 1.12 1.23 1.48 t wh wen hold time 0.57 0.54 0.48 t acc access time 4.00 4.70 6.00 t da deaccess time 1.80 1.90 2.20 size ( m m) width 996 1787 3353 height 1110 1802 3194 power ( m w/mhz) power_ck (normal mode: csn low) 1877 4497 12177 power_csn (stand-by mode: csn high) 243 465 919
sec asic 5-63 STD80/stdm80 dpsrama gen dual-port synchronous ram generator C alternative characteristic reference table (cont.) stdm80 symbol description 256x16m4 1024x16m8 4kx16m16 timing requirements & delay (typical process, 3.3v, 25 o c, output load = 10sl, unit = ns) t rp minimum read pulse width 5.03 6.24 7.78 t pc minimum pre-charge period 7.45 8.14 15.20 t wp minimum write pulse width 2.32 3.23 5.03 t rwc read-write contention 1.83 2.62 4.18 t wrc write-read contention 0 0 0 t wwc write-write contention 1.41 2.36 4.26 t as address setup time 0.45 0.89 1.75 t ah address hold time 1.45 2.33 4.10 t cs csn setup time 0.65 0.65 0.65 t ch csn hold time 0 0 0 t ds data input setup time 1.57 2.50 4.43 t dh data input hold time 1.93 2.30 3.05 t os oen setup time 0 0 0 t oh oen hold time 1.63 1.75 2.00 t wh wen hold time 0.67 0.56 0.63 t acc access time 5.70 6.50 8.30 t da deaccess time 2.40 2.60 3.00 size ( m m) width 996 1787 3353 height 1110 1802 3194 power ( m w/mhz) power_ck (normal mode: csn low) 882 2009 5374 power_csn (stand-by mode: csn high) 107 201 404
STD80/stdm80 5-64 sec asic dpsrama gen dual-port synchronous ram generator C alternative characteristic equation tables STD80 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] timing type timing equation y = 2 tpc 1.41e C 02 * w + 6.61e C 03 * b + 3.33e C 01 * s + 1.2822 trp 3.10e C 03 * w + 4.03e C 03 * b C 2.28e C 01 * s + 8.93e C 01 * 0.019 * sl + 2.2859 tacc 3.19e C 03 * w + 7.64e C 03 * b + 1.21e C 01 * s + 3.96e C 01 * 0.019 * sl + 2.1815 y = 4 tpc 7.09e C 03 * w + 1.32e C 02 * b + 3.33e C 01 * s + 1.2822 trp 1.55e C 03 * w + 8.07e C 03 * b C 2.28e C 01 * s + 8.93e C 01 * 0.019 * sl + 2.2859 tacc 1.59e C 03 * w + 1.52e C 02 * b + 1.21e C 01 * s + 3.96e C 01 * 0.019 * sl + 2.1815 y = 8 tpc 3.54e C 03 * w + 2.64e C 02 * b + 3.33e C 01 * s + 1.2822 trp 7.75e C 04 * w + 1.61e C 02 * b C 2.28e C 01 * s + 8.93e C 01 * 0.019 * sl + 2.2859 tacc 7.97e C 04 * w + 3.05e C 02 * b + 1.21e C 01 * s + 3.96e C 01 * 0.019 * sl + 2.1815 y = 16 tpc 1.77e C 03 * w + 5.29e C 02 * b + 3.33e C 01 * s + 1.2822 trp 3.87e C 04 * w + 3.23e C 02 * b C 2.28e C 01 * s + 8.93e C 01 * 0.019 * sl + 2.2859 tacc 3.98e C 04 * w + 6.11e C 02 * b + 1.21e C 01 * s + 3.96e C 01 * 0.019 * sl + 2.1815 y = 32 tpc 8.86e C 04 * w + 1.05e C 01 * b + 3.33e C 01 * s + 1.2822 trp 1.93e C 04 * w + 6.46e C 02 * b C 2.28e C 01 * s + 8.93e C 01 * 0.019 * sl + 2.2859 tacc 1.99e C 04 * w + 1.22e C 01 * b + 1.21e C 01 * s + 3.96e C 01 * 0.019 * sl + 2.1815 power type power equation y = 2 power_ck (1.8534e C 01 * w + 1.0095 * b + 2.7972 + 3.9703e C 03 * w * b) * vdd 2 * f power_csn (9.7679e C 03 * w + 2.3114e C 01 * b + 1.0169 + 1.8078e C 05 * w * b) * vdd 2 * f y = 4 power_ck (9.2672e C 02 * w + 2.0190 * b + 2.7972 + 3.9703e C 03 * w * b) * vdd 2 * f power_csn (4.8839e C 03 * w + 4.6228e C 01 * b + 1.0169 + 1.8078e C 05 * w * b) * vdd 2 * f y = 8 power_ck (4.6336e C 02 * w + 4.0381 * b + 2.7972 + 3.9703e C 03 * w * b) * vdd 2 * f power_csn (2.4419e C 03 * w + 9.2456e C 01 * b + 1.0169 + 1.8078e C 05 * w * b) * vdd 2 * f y = 16 power_ck (2.3168e C 02 * w + 8.0763 * b + 2.7972 + 3.9703e C 03 * w * b) * vdd 2 * f < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
sec asic 5-65 STD80/stdm80 3) size equation [unit: m m] width = 16.6 * ( log 2 (w / y) ) + 12.1 * b * y + 121.7 [ m m] height = 404.95 + 10.85 * w / y + m [ m m] m = 8.15 (if y = 2, 8), m = 10.55 (if y = 4, 16), m = 12.95 (if y = 32) stdm80 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] power_csn (1.2209e C 03 * w + 1.8491 * b + 1.0169 + 1.8078e C 05 * w * b) * vdd 2 * f y = 32 power_ck (1.1584e C 02 * w + 1.6152e + 01 * b + 2.7971 + 3.9703e C 03 * w * b) * vdd 2 * f power_csn (6.1049e C 04 * w + 3.6982 * b + 1.0169 + 1.8078e C 05 * w * b) * vdd 2 * f timing type timing equation y = 2 tpc 1.99e C 02 * w + 1.01e C 02 * b + 2.53e C 01 * s + 2.0311 trp 4.25e C 03 * w + 6.96e C 03 * b C 9.32e C 02 * s + 1.2362 * 0.019 * sl + 3.3780 tacc 4.19e C 03 * w + 1.01e C 02 * b + 1.05e C 01 * s + 5.13e C 01 * 0.019 * sl + 3.2329 y = 4 tpc 9.99e C 03 * w + 2.02e C 02 * b + 2.53e C 01 * s + 2.0311 trp 2.12e C 03 * w + 1.39e C 02 * b C 9.32e C 02 * s + 1.2362 * 0.019 * sl + 3.3780 tacc 2.09e C 03 * w + 2.03e C 02 * b + 1.05e C 01 * s + 5.13e C 01 * 0.019 * sl + 3.2329 y = 8 tpc 4.99e C 03 * w + 4.04e C 02 * b + 2.53e C 01 * s + 2.0311 trp 1.06e C 03 * w + 2.78e C 02 * b C 9.32e C 02 * s + 1.2362 * 0.019 * sl + 3.3780 tacc 1.04e C 03 * w + 4.07e C 02 * b + 1.05e C 01 * s + 5.13e C 01 * 0.019 * sl + 3.2329 y = 16 tpc 2.49e C 03 * w + 8.09e C 02 * b + 2.53e C 01 * s + 2.0311 trp 5.31e C 04 * w + 5.57e C 02 * b C 9.32e C 02 * s + 1.2362 * 0.019 * sl + 3.3780 tacc 5.24e C 04 * w + 8.14e C 02 * b + 1.05e C 01 * s + 5.13e C 01 * 0.019 * sl + 3.2329 y = 32 tpc 1.24e C 03 * w + 1.61e C 01 * b + 2.53e C 01 * s + 2.0311 trp 2.65e C 04 * w + 1.11e C 01 * b C 9.32e C 02 * s + 1.2362 * 0.019 * sl + 3.3780 tacc 2.62e C 04 * w + 1.62e C 01 * b + 1.05e C 01 * s + 5.13e C 01 * 0.019 * sl + 3.2329 power type power equation y = 2 power_ck (1.7365e C 01 * w + 9.5041e C 01 * b +1.1391e + 01 + 4.1433e C 03 * w * b) * vdd 2 * f power_csn (7.3119e C 03 * w + 2.2202e C 01 * b + 1.6135 + 5.1415e C 05 * w * b) * vdd 2 * f y = 4 power_ck (8.6829e C 02 * w + 1.9008 * b + 1.1391e + 01 + 4.1433e C 03 * w * b) * vdd 2 * f power_csn (3.6559e C 03 * w + 4.4405e C 01 * b + 1.6135 + 5.1415e C 05 * w * b) * vdd 2 * f y = 8 power_ck (4.3414e C 02 * w + 3.8016 * b + 1.1391e + 01 + 4.1433e C 03 * w * b) * vdd 2 * f power type power equation dpsrama gen dual-port synchronous ram generator C alternative
STD80/stdm80 5-66 sec asic 3) size equation [unit: m m] width = 16.6 * ( log 2 (w / y) ) + 12.1 * b * y + 121.7 [ m m] height = 404.95 + 10.85 * w / y + m [ m m] m = 8.15 (if y = 2, 8), m = 10.55 (if y = 4, 16), m = 12.95 (if y = 32) power_csn (1.8279e e 03 * w + 8.8811e e 01 * b + 1.6135 + 5.1415e e 05 * w * b) * vdd 2 * f y = 16 power_ck (2.1707e C 02 * w + 7.6033 * b + 1.1391e + 01 + 4.1433e C 03 * w * b) * vdd 2 * f power_csn (9.1398e C 04 * w + 1.7762 * b + 1.6135 + 5.1415e C 05 * w * b) * vdd 2 * f y = 32 power_ck (1.0853e C 02 * w + 1.5206e + 01 * b + 1.1391e + 01 + 4.1433e C 03 * w * b) * vdd 2 * f power_csn (4.5699e C 04 * w + 3.5524 * b + 1.6135 + 5.1415e C 05 * w * b) * vdd 2 * f power type power equation dpsrama gen dual-port synchronous ram generator C alternative
sec asic 5-67 STD80/stdm80 dpsrama gen dual-port synchronous ram generator C alternative timing diagrams read cycle ck de?ned write cycle wen de?ned write cycle dout ck t as a t ah (csn / oen : low, di :dont care) hi-z t acc t da wen t wh stable t pc t rp valid dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di unknown t ds t dh stable t pc t rp stable t wp dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di unknown t ds t dh stable t pc t rp stable t wp
STD80/stdm80 5-68 sec asic dpsrama gen dual-port synchronous ram generator C alternative ck de?ned read-modi?ed-write cycle wen de?ned read-modi?ed-write cycle csn control dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di valid t ds t dh stable t pc t rp stable t wp dout ck t as a t ah (csn / oen : low) hi-z t acc t da wen di valid t ds t dh stable t pc t rp stable t wp dout ck a csn (oen : low, wen / di : dont care) t cs t ch hi-z t as t ah t da t acc
sec asic 5-69 STD80/stdm80 dpsrama gen dual-port synchronous ram generator C alternative oen control function diagrams readCwrite contention (max (t 1 , t 2 ) t rwc ) dout ck a oen (csn : low, wen / di : don?t care) t os t oh t as t ah t acc t da hi-z t 1 unknown (a1 = a2) ck1 wen1 ck2 wen2 dout1 dout2 unknown t 2 (csn1 / csn2 / oen1 / oen2 : low, di1 : don?t care, di2 : valid) * if the greater of t 1 or t 2 is smaller than or equal to t rwc , it is read-write contention. the read by port1 is invalid, the write by port2 is still valid.
STD80/stdm80 5-70 sec asic dpsrama gen dual-port synchronous ram generator C alternative writeCread contention (min (t 1 , t 2 ) 3 t wrc ) writeCwrite contention (max (t 1 , t 2 ) t wwc at ck detned write cycle) t 1 unknown (a1 = a2) ck1 wen1 ck2 wen2 dout1 dout2 unknown t 2 (csn1 / csn2 / oen1 / oen2 : low, di1 : valid, di2 : don?t care) * if the smaller of t 1 or t 2 is greater than or equal to t wrc , it is write-read contention. the read by port2 is invalid, the write by port1 is still valid. t 1 unknown (a1 = a2) ck1 wen1 ck2 wen2 dout1 dout2 unknown t 2 (csn1 / csn2 / oen1 / oen2 : low, di1 / di2 : valid) * if the greater of t 1 or t 2 is smaller than or equal to t wwc , it is write-write contention. data stored at current address will be unpredictable.
sec asic 5-71 STD80/stdm80 dpsrama gen dual-port synchronous ram generator C alternative writeCwrite contention (max (t 1 , t 2 ) t wwc at wen detned write cycle) t 1 unknown (a1 = a2) ck1 wen1 ck2 wen2 dout1 dout2 unknown t 2 (csn1 / csn2 / oen1 / oen2 : low, di1 / di2 : valid) * if the greater of t 1 or t 2 is smaller than or equal to t wwc , it is write-write contention. data stored at current address will be unpredictable.
STD80/stdm80 5-72 sec asic dparam gen dual-port asynchronous ram generator logic symbol function description dparam is a dual port asynchronous static ram. when wen1 is high, just after the address(a1[ ]) transition, dout1[ ] presents the data stored in the location addressed by a1[ ]. upon wen1 rising edge, the value of di1[ ] is written into the location addressed by a1[ ]. csn1 is used to enable/disable the accesses. oen1 is used to enable/disable the data output driver. port2 has the same functionalities as those of port1, and two functionalities are independent of each other. generators and cell con?gurations sparam generates layout, netlist, symbol and functional & timing model of a sparam. the layout of sparam is an automatically generated array of custom, pitch-matched leaf cells. there are four generator parameters to resolve the con?guration of a sparam. ? number of words (w) ? number of bits per word (b) ? lower address decoder type (y). the valid range of these parameters is speci?ed in the following table: parameters ymux = 4 ymux = 8 ymux = 16 ymux = 32 words (w) min 16 32 64 128 max 1024 2048 4096 8192 step 8 16 32 64 bpw (b) min 1 1 1 1 max 64 32 16 8 step 1 1 1 1 notes: 1. words (w) is the number of words in dparam. 2. bpw (b) is the number of bits per word. 3. ymux (y) is one of the lower address decoder types. 4. m = log 2 w e 1 csn1 csn2 wen1 dparamxm dout1 [bC1:0] wen2 oen1 oen2 a1 [m:0] a2 [m:0] di1 [bC1:0] di2 [bC1:0] dout2 [bC1:0] features ? asynchronous operation ? address transition detectors ? write enable transition detector ? chip select transition detector ? stand-by (power down) mode available ? tri-state output ? separated data i/o ? low noise output circuit ? flexible aspect ratio ? up to 64k bits capacity ? up to 8k number of words ? up to 64 number of bits per word
sec asic 5-73 STD80/stdm80 dparam gen dual-port asynchronous ram generator pin descriptions pin capacitance (unit = sl) application notes 1) fitting the layout shape (aspect ratio) layout shape can be ?tted by choosing one of 4 ymux parameters in the above con?guration table in accordance with your chip level layout design preference. larger one makes the layout shape ?at and short. smaller one makes it thin and tall. in general, ?at and short dparam is faster than thin and tall one. 2) contention modes simultaneous accesses to the same location through both ports cause a contention. dparam has no contention-preventing scheme. user has to take care of the contention modes. please refer to the timing diagrams of contention modes to get more information of contention modes. name i/o description csn i "chip select negative" acts as the memory enable signal for selecting one of multiple memory blocks. when csn is high, dout[ ] goes to hi-z state, the memory goes to stand-by (power down) mode and no access to the memory can occur. conversely, if csn is low only then may a read or write access occur. when csn falls, a read access is initiated. csn should be stable when wen is low. wen1 i "write enable negative" selects the type of memory access. when wen is high, the sparam is in read mode. otherwise, it is in write mode. upon the rising edge of wen, a write access completed and a read access initiated. when wen is low, a[ ] and csn should be stable. oen1 i "output enable negative" unconditionally enables or disables the output drivers. a [ ] i "address" selects the location to be accessed. when a[ ] changes, the transition is detected and the internal clock pulse will be generated. a[ ] should be stable when wen is low. d [ ] i when wen rises, the "data in" word value is written to the location addressed. dout [ ] o during a read access, the data word stored will be presented to the "data out" ports. dout[ ] is tri-statable. when csn is low and oen is low, only then, dout[ ] drives a certain value. otherwise, dout[ ] keeps hi-z state. during a write access, the data on dout is unpredictable. csn wen oen a di dout ymux 4 ymux 8 ymux 16 ymux 32 STD80/stdm80 11.4 4.9 0.8 4.9 2.4 6.0 13.2 27.5 56.0
STD80/stdm80 5-74 sec asic dparam gen dual-port asynchronous ram generator block diagram ram core word column muxs and sense amps i/o driver row control logic & a2 [ ] wen2 address buffer port1 di2 [ ] di1 [ ] a1 [ ] di2 [ ] dout2 [ ] csn2 oen2 line drv. port1 word dec. line drv. port1 port2 control logic & address buffer port2 row dec. port2 wen1 csn1 oen1
sec asic 5-75 STD80/stdm80 dparam gen dual-port asynchronous ram generator characteristic reference table STD80 symbol description 256x16m4 1024x16m8 4kx16m16 timing (typical process, 5v, 25 o c, output load = 10sl, input slope = 0.2ns unit = ns) t acc access time 6.3 6.7 7.7 t da deaccess time 4.8 4.9 4.9 t dz active to hi-z 0.8 0.8 0.8 t zd hi-z to active 1.7 1.7 1.7 t as address setup time 0.1 0.1 0.1 t ah address hold time 1.2 1.5 2.0 t ds input data setup time 2.0 2.7 4.1 t dh input data hold time 0.9 1.1 1.7 t wen minimum wen pulse width low 3.1 3.4 3.9 t cs csn setup time 0.1 0.1 0.1 t ch csn hold time 0.9 0.9 0.9 t rwc read-write contention time 6.3 6.8 7.8 t wwc write-write contention time 3.1 3.4 3.9 size ( m m) width 1239 2013 3562 height 1075 1770 3158 power ( m w/mhz) power_add (normal mode: csn low) 3150 4950 8960 power_csn (stand-by mode: csn high) 485 855 1595
STD80/stdm80 5-76 sec asic dparam gen dual-port asynchronous ram generator characteristic reference table stdm80 symbol description 256x16m4 1024x16m8 4kx16m16 timing (typical process, 3.3v, 25 o c, output load = 10sl, input slope = 0.2ns unit = ns) t acc access time 9.2 9.9 11.2 t da deaccess time 7.2 7.2 7.3 t dz active to hi-z 1.8 1.8 1.8 t zd hi-z to active 2.4 2.4 2.4 t as address setup time 0.1 0.1 0.1 t ah address hold time 1.6 1.9 2.5 t ds input data setup time 1.3 1.8 2.8 t dh input data hold time 1.2 1.5 2.1 t wen minimum wen pulse width low 4.6 4.9 5.5 t cs csn setup time 0.1 0.1 0.1 t ch csn hold time 1.7 1.7 1.7 t rwc read-write contention time 9.2 9.9 11.2 t wwc write-write contention time 4.6 4.9 5.5 size ( m m) width 1239 2013 3562 height 1075 1770 3158 power ( m w/mhz) power_add (normal mode: csn low) 1409 2253 3967 power_csn (stand-by mode: csn high) 221 380 700
sec asic 5-77 STD80/stdm80 dparam gen dual-port asynchronous ram generator characteristic equation tables STD80 (typical process, 5v, 25 o c ) 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] notes: 1. power_add : this is a normal mode power of memory. when csn is low. 2. power_csn : this is a standby mode power of memory. when csn is high. 3) size equation [unit: m m] width 12.1*b*y+464.6 height 10.85*w/y+380.75 timing type timing equation y = 4 tacc (1.81e-03*w+4.05e-02*s+1.73e-01*sl*0.019+5.74) twen (1.01e-03*w+2.17e-01*s+2.78+5.13e-06*w*s) y = 8 tacc (9.23e-04*w+6.35e-02*s+1.81e-01*sl*0.019+5.72) twen (5.06e-04*w+2.17e-01*s+2.78+2.56e-06*w*s) y = 16 tacc (4.52e-04*w+5.59e-02*s+1.69e-01*sl*0.019+5.81) twen (2.53e-04*w+2.17e-01*s+2.78+1.28e-06*w*s) y = 32 tacc (2.26e-04*w+5.81e-02*s+1.58e-01*sl*0.019+5.91) twen (1.26e-04*w+2.17e-01*s+2.78+6.42e-07*w*s) power type power equation y = 4 power_add ((0.409*w+24*b+141)/5.0)*vdd 2 *f power_csn ((0.148*w+2.27*b+22.3)/5.0)*vdd 2 *f y = 8 power_add ((0.217*w+38.1*b+158)/5.0)*vdd 2 *f power_csn ((0.074*w+4.54*b+22.3)/5.0)*vdd 2 *f y = 16 power_add ((0.0886*w+76.9*b+199)/5.0)*vdd 2 *f power_csn ((0.037*w+9.08*b+22.3)/5.0)*vdd 2 *f y = 32 power_add ((0.0406*w+150*b+206)/5.0)*vdd 2 *f power_csn ((0.0185*w+18.1*b+22.3)/5.0)*vdd 2 *f < condition & descriptions > w: number of words y: ymux type s: input slope (unit: ns) vdd: operating voltage (unit: v) b: bits per word sl: number of fanouts (unit: standard load) f: operating frequency (unit: mhz)
STD80/stdm80 5-78 sec asic dparam gen dual-port asynchronous ram generator stdm80 (typical process, 3.3v, 25 o c) 1) timing characteristics [unit: ns] 2) power characteristics [unit: m w] notes: 1. power_add : this is a normal mode power of memory. when csn is low. 2. power_csn : this is a standby mode power of memory. when csn is high. 3) size equation [unit: m m] width 12.1*b*y+464.6 height 10.85*w/y+380.75 timing type timing equation y = 4 tacc (2.51e-03*w+9.12e-02*s+2.02e-01*sl*0.019+8.47) twen (1.16e-03*w+6.54e-02*s+4.25+1.20e-04*w*s) y = 8 tacc (1.24e-03*w+9.22e-02*s+2.06e-01*sl*0.019+8.51) twen (5.83e-04*w+6.54e-02*s+4.25+6.04e-05*w*s) y = 16 tacc (6.18e-04*w+1.07e-01*s+1.94e-01*sl*0.019+8.61) twen (2.91e-04*w+6.54e-02*s+4.25+3.02e-05*w*s) y = 32 tacc (3.10e-04*w+1.05e-01*s+1.97e-01*sl*0.019+8.73) twen (1.45e-04*w+6.54e-02*s+4.25+1.51e-05*w*s) power type power equation y = 4 power_add ((0.273*w+16.4*b+94.7)/3.3)*vdd 2 *f power_csn ((0.0951*w+1.5*b+18.2)/3.3)*vdd 2 *f y = 8 power_add ((0.153*w+27*b+94.5)/3.3)*vdd 2 *f power_csn ((0.0475*w+3.01*b+1.82)/3.3)*vdd 2 *f y = 16 power_add ((0.0594*w+51.8*b+130)/3.3)*vdd 2 *f power_csn ((0.0237*w+6.02*b+18.2)/3.3)*vdd 2 *f y = 32 power_add ((0.0253*w+105*b+138)/3.3)*vdd 2 *f power_csn ((0.0118*w+12*b+18.2)/3.3)*vdd 2 *f
sec asic 5-79 STD80/stdm80 dparam gen dual-port asynchronous ram generator timing diagrams basic read timing csn controlled read timing oen controlled read timing (wen = high; csn, oen = low) a dout t acc t da t acc t da a t acc t dz csn hi-z (wen = high; oen = low) dout hi-z n1 n2 n3 n1 n2 n3 t zd a t dz oen dout t zd hi-z hi-z n1 n2 n3 n1 n2 n3 (wen = high; csn = low)
STD80/stdm80 5-80 sec asic dparam gen dual-port asynchronous ram generator basic write timing read-write-read timing (when t1, t2 > tacc) read-write contention (when min (t1, t2) <= trwc) (oen = dont care) a di t dh csn t as t ah wen t cs t ch t wen t ds stable stable (csn, oen = low) a di t dh t1 t2 wen t ds dx dout dx t acc t da t acc t acc valid stable (wen = high; oen1,csn2 = low) a2 t1 ax csn1 dout1 unknown t2 wen2 a1 ax the read by port1 is invalid, the write by port2 is still valid. * if the smaller of t1 or t2 is smaller than or equal to trwc, it is read-write contention.
sec asic 5-81 STD80/stdm80 dparam dual-port asynchronous static ram write-read contention write-write contention (when t1 <= twwc) (csn1, oen2=low; wen2=high) a2 ax wen1 csn2 a1 ax dout2 unknown * if read access by port2 begins while wen1 is low and the addresses of both ports are same, it is write-read contention. the read by port2 is invalid, the write by port1 is still valid. (csn1, csn2=low) t1 wen1 wen2 will be unpredictable. regardless of the value of t1, read by port1 after wen1 rise is invalid. * if t1 is smaller than or equal to twwc, it is write-write contention. the data stored at current address it is a sort of write-read contention. a1=a2
datapath compilers 6
contents overview .............................................................................................................................. 6-1 datapath compilers information .......................................................................................... 6-3 macro cells adder/subtracter .................................................................................................................. 6-5 arithmetic logic unit ............................................................................................................ 6-7 array multiplier ..................................................................................................................... 6-10 barrel shifter ........................................................................................................................ 6-16 carry-select adder............................................................................................................... 6-19 comparator .......................................................................................................................... 6-21 decrementer ........................................................................................................................ 6-23 fast multiplier ....................................................................................................................... 6-25 incrementer .......................................................................................................................... 6-27 incrementer/decrementer .................................................................................................... 6-29 normalizer............................................................................................................................ 6-31 one detector........................................................................................................................ 6-33 parity .................................................................................................................................... 6-35 priority encoder.................................................................................................................... 6-37 register file ......................................................................................................................... 6-39 saturating adder .................................................................................................................. 6-49 zero detector ....................................................................................................................... 6-51 logic cells and-or ............................................................................................................................... 6-53 and-or-invert................................................................................................................. 6-55 buffer/inverter....................................................................................................................... 6-57 bus holder ........................................................................................................................... 6-59 d flip-flop............................................................................................................................ 6-60 full adder............................................................................................................................. 6-72 latch .................................................................................................................................... 6-74 multiplexer ............................................................................................................................ 6-82 nand/and .......................................................................................................................... 6-85 nor/or............................................................................................................................... 6-87 or-and ............................................................................................................................... 6-89 or-and-invert................................................................................................................. 6-91 tri-state buffer/inverter ........................................................................................................ 6-93 xnor/xor .......................................................................................................................... 6-95
datapath compilers overview sec asic 6-1 STD80/stdm80 overview the datapath cell library is a set of high-level logic elements developed by samsung asic. datapath cells generate application-specific design libraries that can be used with the datapath place and route tool to construct complex datapaths. the blocks which are produced using datapath cells can then be globally routed using the chip level place and route tool like arccell. datapath compiler automatically places and routes circuits that have an inherently regular structure. datapath compiler differs from a standard cell place and route tool in that it enables you to map regularity from a logical design into a layout. with datapath, you can create layouts that are as dense as custom layouts. a typical application of datapath is a multi-bit arithmetic logic function. datapath compiler enables you to: ? generate schematics automatically according to the user-specific parameters ? support functional models, test vectors and auto-characterized timing models ? produce layouts that exhibit modularity and topological regularity ? control the layout placement and density ? perform over-the-cell routing and tlm maze routing with channel compaction ? produce cap file and wire delay file for back-annotation process. datapath process flow the datapath process flow begins the physical design portion of the ic design process. the logic design and circuit analysis have been completed and the next step is to produce a layout for the design. the figure 6-1 illustrates the recommended methodology for using datapath to create a layout for a design and illustrates how the datapath cell library fits into the datapath process flow. figure 6-1. datapath process flow and datapath cell library define layout topology build datapath schematic build control file placement create cell library datapath cell library generators improve placement global routing channel routing
overview datapath compilers STD80/stdm80 6-2 sec asic a datapath layout is a two-dimensional array of rows and columns with routing channels between the rows. the orientation of bits and words with respect to rows and columns defines the datapath layout topology. feedthrough terminals are the locations on a datapath cell where the datapath router can cross the row without connecting to the cell. feedthroughs can be built into the cell (that is, the cell contains a vertical wire with a top and bottom terminal that is not connected internal to the cell), or they can be locations where there is sufficient room to route a wire vertically over the cell. the figure 6-2 illustrates a typical datapath topology. figure 6-2. typical data topology gnd vdd data control c1 c2 csb addr alu barrel 2:1 mux buffer shifter feedthrough
datapath compilers datapath compilers information sec asic 6-3 STD80/stdm80 datapath compilers information macro cells cell name function bits features adder adder/subtracter 4 ~ 128 ? ripple/carry-bypass scheme ? 2s complement over?ow flag addersat saturating adder 4 ~ 128 ? ripple/carry-bypass scheme ? 2s complement alu arithmetic logic unit 4 ~ 128 ? 2s complement over?ow/carry-out flag ? 9 arithmetic, 15 logical functions bs barrel shifter 4 ~ 128 ? transmission gate multiplexing scheme ? bi-directional shift or rotate ? fill vacant bits with data cmp comparator 4 ~ 128 ? less than or equal flag & equal flag ? greater than or equal flag & equal flag ? greater than & equal flag ? less than & equal flag ? 2s complement csadder carry-select adder 4 ~ 128 ? double carry-select algorithm ? 2s complement over?ow flag dec decrementer 4 ~ 128 ? ripple/carry-bypass scheme enc priority encoder 4 ~ 128 ? detect from lsb/msb fmpy fast multiplier 8 ~ 64 ? modi?ed wallace tree architecture ? 2s complement inc incrementer 4 ~ 128 ? ripple/carry-bypass scheme incdec incrementer/decrementer according to select signal 4 ~ 128 ? ripple/carry-bypass scheme mpy array multiplier 6 ~ 64 ? supporting accumulator and pipes ? 2s complement multiplication norm normalizer 4 ~ 128 ? outputs shift amount and all0 flag oned one detector 4 ~ 128 ? generating one flag parity parity generator 4 ~ 128 ? generating parity flag regf register file 8 ~ 128 ? con?gurable read (1 ~ 4)/write (1 ~ 2) ? address decoders on either side of block zerod zero detector 4 ~ 128 ? generating zero flag
datapath compilers information datapath compilers STD80/stdm80 6-4 sec asic logic cells cell name function bits features ao and-or 4 ~ 128 ? con?gurable 21 and 22 types aoi and-or-invert 4 ~ 128 ? con?gurable 21 and 22 types buffer buffer/inverter 4 ~ 128 ? buffers and inverters bushldr bus holder 4 ~ 128 ? bus holder dff d flip-flop 4 ~ 128 ? negative/positive edge triggered ? scan logic and set/reset options ? tri-state and normal outputs fadder full adder 4 ~ 128 ? full adder array latch transparent latch 4 ~ 128 ? high input enable ? scan logic and set/reset options ? tri-state and normal outputs mux multiplexer 4 ~ 128 ? inverting/non-inverting ? con?gurable 2, 3, 4 and 8 inputs nand nand/and 4 ~ 128 ? con?gurable 2, 3 and 4 inputs nor nor/or 4 ~ 128 ? con?gurable 2, 3 and 4 inputs oa or-and 4 ~ 128 ? con?gurable 21 and 22 types oai or-and-invert 4 ~ 128 ? con?gurable 21 and 22 types tristate tri-state buffer/inverter 4 ~ 128 ? tri-state buffers and inverters xor exclusive or/nor 4 ~ 128 ? con?gurable 2 and 3 inputs
sec asic 6-5 STD80/stdm80 adder/subtracter features ? twos complement or unsigned magnitude operation ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? simple ripple and sophisticated group bypass scheme ? twos complement overflow flag ? n -bit (4 to 128) adder ? three drive strength options for output general description the adder/subtracter builds an n -bit wide adder schematic. the schematic generated is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. the adder/subtracter performs twos complement addition/subtraction or unsigned magnitude addition. the overflow flag gets set if an overflow occurs while adding two positive or negative numbers. the overflow is ignored while doing unsigned magnitude operations. design description the adder/subtracter performs add/subtract function. an n -bit wide operand (ain), an n -bit wide operand (bin), a 1-bit wide input carry signal (cin), an n -bit wide output bus (sout) and 1-bit wide output carry signal (cout) serve as the i/o signals to the module. the adder/subtracter can be built with two different carry chains allowing speed/area trade-offs. the ripple carry chain is high in density, but low in performance. the carry-bypass chain has a unique grouping of bits which creates a high performance design. this scheme is preferable for the addition of large data words to attain high speed. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 nopass 0: group bypass; 1: ripple adder 0/1 subtract 0: adder; 1: subtracter 0/1 cinlogic 0: cin ? ~cin; 1: cin ? cin 0/1 over?ow over?ow ?ag for signed operation 0/1 drv drive strength 1/2/4 ain [bitse1:0] sout [bitse1:0] bin [bitse1:0] cin sub (optional) cout ovf (optional) +/e
STD80/stdm80 6-6 sec asic adder/subtracter pin description function table truth table performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description ain [bitsC1:0] i data input bin [bitsC1:0] data input cin carry-in sub it speci?es addition/subtraction (optional when the parameter subtract = 1). sout[bitsC1:0] o result of addition/subtraction cout it speci?es the carry-out of two given numbers. ovf over?ow/under?ow of signal addition/subtraction (optional when the param- eter over?ow = 1). type function adder if (cinlogic == 1), sout = ain + bin + cin, else sout = ain + bin + ~cin subtracter if (cinlogic == 1), sout = ain + ~bin + cin, else sout = ain + ~bin + ~cin over?ow (~sout [bitsC1]) ? (ain [bitsC1] ? bin [bitsC1]) + (sout [bitsC1]) ? (~ain [bitsC1]) ? (~ bin [bitsC1]) inputs outputs ain bin cin sout cout 00000 10010 01010 11001 00110 10101 01101 11111 parameters : nopass = 0, subtract = 0, cinlogic = 1, over?ow = 1, drv =1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 240.5 104.8 2.807 2.303 0.230 16 451.7 103.4 3.247 2.811 0.439 24 662.9 107.8 3.447 2.933 0.625 32 874.1 108.9 3.719 3.501 0.825 dpm80 8 240.5 104.8 4.638 4.312 0.147 16 451.7 103.4 5.218 4.922 0.279 24 662.9 107.8 5.668 5.342 0.387 32 874.1 108.9 5.896 5.620 0.524 pin capacitance pin name value (pf) dp80 dpm80 ain 0.049 0.048 bin 0.039 0.039 cin 0.095 0.092
sec asic 6-7 STD80/stdm80 arithmetic logic unit features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? high performance arithmetic logic unit ? twos complement overflow flag ? n -bit (4 to 128) adder used ? carry-out flag ? three drive strength options for output general description the arithmetic logic unit builds an n -bit wide arithmetic logic unit schematic. the schematic generated is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. design description the logic circuit produced by the generator performs 15 logical, 9 arithmetic operations. an n -bit wide operand (ain), an n -bit wide operand (bin), a 1-bit wide input carry signal(cin), an n -bit wide output bus(sout) and 1-bit output carry signal(cout) serve as the i/o signals to the module. the arithmetic logic unit is built with a carry-bypass chain. the carry-bypass chain has a unique grouping of bits which creates a high performance design. this scheme provides high performance for large data words arithmetic operations. the overflow flag gets set if an overflow occurs while adding two positive or negative numbers. this flag is ignored for unsigned magnitude operations but is important when using the block in twos complement arithmetic operations. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 over?ow over?ow ?ag for signed operation 0/1 drv drive strength 1/2/4 ain [bitsC1:0] sout [bitsC1:0] bin [bitsC1:0] cout alu ovf (optional) c [7:0] cin
STD80/stdm80 6-8 sec asic arithmetic logic unit pin description function table pin capacitance pin name i/o description ain [bitsC1:0] i data input for arithmetic/logical operations bin [bitsC1:0] data input for arithmetic/logical operations c [7:0] operational code control inputs refer to opcode in the function table below. cin carry-in for arithmetic operations it must be maintained to 0 in a logical operation. sout [bitsC1:0] o result of an arithmetic/logical operation cout carry-out of an arithmetic operation ovf over?ow/under?ow of a signed addition (optional when the parameter over?ow = 1) logical opcode arithmetic opcode 0 0x00 a + b + cin 0x76 ~a & ~b 0x01 a + ~b + cin 0xb9 ~a & b 0x02 b + ~a + cin 0xd9 ~a 0x03 ~a + cin 0xf3 a & ~b 0x04 ~b + cin 0xf5 ~b 0x05 a + cin 0xfc a ^ b 0x06 b + cin 0xfa ~a | ~b 0x07 a C ~cin 0x33 a & b 0x08 b C ~cin 0x55 ~(a ^ b) 0x09 pass b 0x0a ~a | b 0x0b pass a 0x0c a | ~b 0x0d a | b 0x0e pin name value (pf) dp80 dpm80 ain 0.045 0.044 bin 0.091 0.089 cin 0.069 0.068 c 0.375 0.366 note : while the alu is not active, it is preferable to keep the opcode to 0x00. if c input has an improper code, which is not in the above table, it can cause the undesirable power consumption.
sec asic 6-9 STD80/stdm80 arithmetic logic unit performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) parameters : over?ow = 1, drv =1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 240.9 159.2 2.901 2.563 0.155 16 452.1 155.7 3.291 3.061 0.305 24 663.3 157.4 3.551 3.213 0.445 32 874.5 159.1 3.841 3.493 0.592 dpm80 8 240.9 159.2 4.400 4.158 0.155 16 452.1 155.7 4.990 4.748 0.305 24 663.3 157.4 5.436 5.218 0.445 32 874.5 159.1 5.856 5.638 0.592
STD80/stdm80 6-10 sec asic array multiplier features ? functional model, test-vector, schematic and layout generators ? timing model with auto-characterization ? high speed and density ? twos complement multiplication general description the array multiplier can be optimized for multiple-targeted technologies. the array multiplier can build multipliers from 6-bits to 64-bits with an accumulator, a configurable size of output buffer and a pipe. design description the array multiplier uses the modified booths algorithm to encode the multiplier bits by partitioning the bits into three bit groups, with one bit shared between groups and performing the desired operation as required by the algorithm. the use of the modified booths algorithm reduces by half the number of partial products formed. you can insert one pipeline stage, which increases the efficiency of the multiplier. the msb adder used in the design is a fast group bypass adder and does not require pipes. the lsb adder is programmable to take pipes and is, therefore, the adder array. the clocks to the pipeline control how the internal data changes so that the data is always stable throughout the clock period and there is no hold problem. the multiplier and the multiplicand are programmable in increments by the two bits from a minimum of 6 bits to a maximum of 64 bits. symbol parameter description * x_width should be greater than or equal to y_width (x 3 y). parameter name description range x_width* multiplicand bits (the x-input width) 6 to 64 even y_width multiplier bits (the y-input width) 6 to 64 even pipes pipeline stage 0/1 accum 0: none; n: (x_width+n) bit accumulator 0/1/2/3/4 obuff 1: 6x output buffer; 2: 12x output buffer 1/2 xin [x_widthC1:0] prodh [x_width+1:0] yin [y_widthC1:0] mclk (optional) rst_b (optional) x prodl [y_widthC3:0]
sec asic 6-11 STD80/stdm80 array multiplier pin description pin capacitance timing diagram without pipes with 1 pipe timing parameters (with 1 pipe) pin name i/o description xin [x_widthC1:0] i data input C multiplicand yin [y_widthC1:0] data input C multiplier mclk clock input to the latches used in the design (optional when pipes = 1 or accum 3 1) rst_b input reset line for the latches (active high). if the multiplier has an accumulator, the reset lines ensure that the contents of the accumulator is zero before the trst set of xin * yin arrives to the accumulator (optional when pipes = 1 or accum 3 1). prodh [x_width+1:0] o data output lines from the msb adder. the values of these lines together with the prodl values gives the output data (product). prodl [y_widthe3:0] data output lines from the lsb adder pin name value (pf) dp80 dpm80 xin 0.082 0.080 yin 0.078 0.076 symbol description inputs outputs t setup input stage delay C setup time xin, yin C t hold input state delay C hold time xin, yin C t d output state delay C prodh, prodl t d xin yin prodh prodl t setup t d rst_b yin xin mclk prodh prodl t hold total delay = t setup +t d
STD80/stdm80 6-12 sec asic array multiplier performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) without pipes parameters : io_latch = 0, accum =0, obuff = 1, met_layer = 3, pipe=0 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 x 8 290.4 413.6 5.524 5.354 0.600 16 x 8 501.6 413.6 5.553 5.582 C 16 x 16 501.6 673.6 7.762 7.672 2.830 24 x 8 765.6 413.6 5.893 5.693 C 24 x 16 765.6 673.6 7.902 7.772 C 24 x 24 765.6 967.6 10.022 9.892 4.791 32 x 8 976.8 413.6 6.363 6.193 C 32 x 16 976.8 673.6 8.062 7.912 C 32 x 24 976.8 967.6 10.192 10.032 C 32 x 32 976.8 1237.6 12.162 12.164 7.560 dpm80 8 x 8 290.4 413.6 8.604 8.492 0.364 16 x 8 501.6 413.6 8.794 8.952 C 16 x 16 501.6 673.6 11.654 11.762 1.627 24 x 8 765.6 413.6 9.144 9.162 C 24 x 16 765.6 673.6 11.854 12.062 C 24 x 24 765.6 967.6 14.754 14.862 2.815 32 x 8 976.8 413.6 9.714 9.732 C 32 x 16 976.8 673.6 12.254 12.162 C 32 x 24 976.8 967.6 15.154 15.062 C 32 x 32 976.8 1237.6 18.054 17.962 4.468
sec asic 6-13 STD80/stdm80 array multiplier performance table (cont.) (t = 25 c, slope = 1.0ns, cap. = 0.4pf) with 1 pipe parameters : io_latch = 0, accum =0, obuff = 1, met_layer = 3, pipe=1 library bit area ( m m x m m) delay (ns) width height t plh t phl dp80 8 x 8 290.4 531.5 5.230 5.080 16 x 8 501.6 531.5 5.940 5.730 16 x 16 501.6 826.7 6.740 6.530 24 x 8 765.6 531.5 6.152 5.952 24 x 16 765.6 826.7 6.952 6.752 24 x 24 765.6 1163.2 7.822 7.672 32 x 8 976.8 531.5 6.652 6.482 32 x 16 976.8 826.7 7.452 7.282 32 x 24 976.8 1163.2 8.322 8.142 32 x 32 976.8 1469.8 9.232 9.082 dpm80 8 x 8 290.4 531.5 7.804 7.732 16 x 8 501.6 531.5 8.904 8.762 16 x 16 501.6 826.7 10.234 10.092 24 x 8 765.6 531.5 9.326 9.214 24 x 16 765.6 826.7 10.626 10.534 24 x 24 765.6 1163.2 12.126 12.034 32 x 8 976.8 531.5 10.066 10.074 32 x 16 976.8 826.7 11.426 11.434 32 x 24 976.8 1163.2 12.826 12.834 32 x 32 976.8 1469.8 14.326 14.334
STD80/stdm80 6-14 sec asic array multiplier timing requirements with 1 pipe parameters : io_latch = 0, accum =0, obuff = 1, met_layer = 3, pipe=1 size timing field value (ns) dp80 dpm80 8x8 min_pulse_width_high mclk 0.630 0.756 min_pulse_width_low mclk 0.661 1.050 min_pulse_width_low rst_b 0.909 1.360 hold_falling xin mclk 0.227 0.299 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 2.720 3.710 setup_falling yin mclk 3.170 4.520 16 x 8 min_pulse_width_high mclk 0.913 1.140 min_pulse_width_low mclk 0.854 1.330 min_pulse_width_low rst_b 1.360 2.010 hold_falling xin mclk 0.321 0.462 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 2.720 3.710 setup_falling yin mclk 3.280 4.660 16 x 16 min_pulse_width_high mclk 0.913 1.140 min_pulse_width_low mclk 0.854 1.330 min_pulse_width_low rst_b 1.360 2.010 hold_falling xin mclk 0.285 0.405 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 3.490 4.890 setup_falling yin mclk 4.000 5.740 24 x 8 min_pulse_width_high mclk 0.744 0.951 min_pulse_width_low mclk 0.773 1.240 min_pulse_width_low rst_b 1.130 1.760 hold_falling xin mclk 0.320 0.465 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 2.720 3.710 setup_falling yin mclk 3.300 4.780 24 x 16 min_pulse_width_high mclk 0.744 0.951 min_pulse_width_low mclk 0.773 1.240 min_pulse_width_low rst_b 1.130 1.760 hold_falling xin mclk 0.284 0.408 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 3.490 4.890 setup_falling yin mclk 4.020 5.860
sec asic 6-15 STD80/stdm80 array multiplier timing requirements (cont.) with 1 pipe (cont.) parameters : io_latch = 0, accum =0, obuff = 1, met_layer = 3, pipe=1 size timing field value (ns) dp80 dpm80 24 x 24 min_pulse_width_high mclk 0.744 0.951 min_pulse_width_low mclk 0.773 1.240 min_pulse_width_low rst_b 1.130 1.760 hold_falling xin mclk 0.248 0.351 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 4.280 6.070 setup_falling yin mclk 4.750 6.940 32 x 8 min_pulse_width_high mclk 0.880 1.150 min_pulse_width_low mclk 0.869 1.390 min_pulse_width_low rst_b 1.350 2.110 hold_falling xin mclk 0.370 0.561 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 2.720 3.710 setup_falling yin mclk 3.410 4.890 32 x 16 min_pulse_width_high mclk 0.880 1.150 min_pulse_width_low mclk 0.869 1.390 min_pulse_width_low rst_b 1.350 2.110 hold_falling xin mclk 0.334 0.504 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 3.490 4.890 setup_falling yin mclk 4.130 5.970 32 x 24 min_pulse_width_high mclk 0.880 1.150 min_pulse_width_low mclk 0.869 1.390 min_pulse_width_low rst_b 1.350 2.110 hold_falling xin mclk 0.298 0.447 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 4.280 6.070 setup_falling yin mclk 4.860 7.060 32x32 min_pulse_width_high mclk 0.880 1.150 min_pulse_width_low mclk 0.869 1.390 min_pulse_width_low rst_b 1.350 2.110 hold_falling xin mclk 0.262 0.390 hold_falling yin mclk 0.042 C0.040 setup_falling xin mclk 5.230 7.260 setup_falling yin mclk 5.640 8.180
STD80/stdm80 6-16 sec asic barrel shifter features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? high performance barrel shifter ? n -bit (4 to 128) shifter ? transmission gate multiplexing scheme ? bi-directional shift, fill vacant bits with data, or rotates ? three drive strength options for output general description the barrel shifter builds an n-bit wide barrel shifter schematic. the schematic generated is used to drive the datapath placement and routing tool in combination with technology-specific layout leafcells. the barrel shifter can shift and rotate input signals in either direction. the direction of the shift can be chosen between msb(left) and lsb(right) of the bit string. the barrel shifter supports both arithmetic and logical shift operations. design description the barrel shifter is constructed as a series of cascaded 2-to-1 and 4-to-1 multiplexers. in its largest configuration (128 bits), three rows of 4-to-1 and one row of 2-to-1 muxs are used. the architecture is based on a left-shifter block, a right-shifter block, a fill block and a direction block. data can be shifted left or right; the vacant bits are padded with zeros during a left shift and can be padded with msb of the shift data bus during a right shift. a shift data bus (sh_din) fills the vacant bits during a shift operation. during a right shift, the shift data bus fills the vacant bits with data from the lsb of the shift data bus; during a left shift, the shift data bus fills the vacant bits with data from the msb of the shift data bus (essentially a circular shift). symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type direction of shift left/right/both drv drive strength 1/2/4 din [bitsC1:0] dout [bitsC1:0] sh_din [bitsC1:0] sh_dir (optional) c1 c2 sh [ log 2 bits e1:0] max_dsh round-up
sec asic 6-17 STD80/stdm80 barrel shifter pin description round-up function table pin capacitance pin name i/o description din [bitsC1:0] i data input sh_din [bitsC1:0] shift data input sh_dir shift direction (left/right) (optional when the parameter type = both) c1, c2 control signals sh [ log 2 bits e1:0] shift amount (in binary) max_dsh it tlls data output with tlling information according to c1 and c2. it refreshes output with tll data. dout [bitse1:0] o data output sh_dir c1 c2 dout 0 0 0 shift right and ?ll with zeros 0 1 0 shift right and ?ll with data bus (sh_din) 1 0 0 shift left and ?ll with zeros 1 1 0 shift left and ?ll with data bus (sh_din) 0 0 1 shift right and ?ll with msb 1 1 1 left rotation 0 1 1 right rotation pin name value (pf) dp80 dpm80 c1 0.057 0.057 c2 0.083 0.081 din 0.268 0.250 max_dsh 0.073 0.072 sh 0.192 0.184 sh_din 0.043 0.042 sh_dir 0.042 0.041
STD80/stdm80 6-18 sec asic barrel shifter performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) parameters : type = both, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 264.0 295.0 3.251 2.344 0.116 16 475.2 376.9 3.521 2.544 0.223 24 686.4 481.1 4.111 2.954 0.438 32 897.6 517.1 4.281 3.014 1.041 dpm80 8 264.0 295.0 4.856 2.356 0.068 16 475.2 376.9 5.256 2.967 0.135 24 686.4 481.1 6.076 3.896 0.261 32 897.6 517.1 6.316 4.286 0.477
sec asic 6-19 STD80/stdm80 carry-select adder features ? twos complement or unsigned magnitude operation ? functional model, test vector, schematic, and layout generators ? timing model with auto-characterization ? sophisticated double carry-select algorithm ? twos complement overflow flag ? n -bit (4 to 128) adder ? three drive strength options for output general description the carry-select adder performs twos complement addition or unsigned magnitude operation. the high performance carry-select adder design can have layout leaf cells optimized for multiple-targeted technologies. the overflow flag gets set if an overflow occurs while adding two positive or negative numbers. the overflow is ignored for unsigned magnitude operations. design description the carry-select adder performs high speed binary addition by using a sophisticated double carry-select algorithm with group delay equalization for carry propagation. the outer carry-select scheme is used to provide a short path between the low order inputs and the high order outputs. the internal carry-select schemes are placed within these blocks to reduce their block propagation delays. the sizes of the carry-select blocks increase along the carry propagation tree to produce a fast addition. an n -bit wide operand (ain), an n -bit wide operand (bin), a 1-bit wide input carry signal (cin), and an n -bit wide output bus (sout) and 1-bit output carry signal (cout) serve as the i/o signals to the module. the generated layout is constrained to four rows of cells for minimal area consumption. this fast carry-select adder is configured for your highest performance applications and outperforms normal carry-select adders by modulating the size of the groups to equalize carry propagation delay, and by providing a second level of carry-select scheme. symbol parameter description parameter name description range instance_name name of carry-select adder instance to be generated any string bits number of bits in the input data bus 4 to 128 over?ow it determines whether over?ow output is present; 0: no over?ow; 1: over?ow 0/1 drv drive strength 1/2/4 ain [bitsC1:0] sout [bitsC1:0] bin [bitsC1:0] cin cout ovf (optional) +/C
STD80/stdm80 6-20 sec asic carry-select adder pin description function table truth table performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description ain [bitsC1:0] i input data word bin [bitsC1:0] input data word cin carry-in sout [bitsC1:0] o sum output (ain + bin + cin) cout carry-out ovf over?ow output occurs during a signed addition (optional when the parameter over?ow = 1). type function adder ain + bin + cin over?ow (~sout [bitsC1]) ? (ain [bitsC1] ? bin [bitsC1]) + (sout [bitsC1]) ? (~ain [bitsC1]) ? (~bin [bitsC1]) inputs outputs ain bin cin sout cout 00000 10010 01010 11001 00110 10101 01101 11111 parameters : over?ow = 0, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 240.5 146.8 2.232 2.046 0.427 16 451.7 149.5 2.693 2.527 0.884 24 662.9 151.3 3.085 2.857 1.352 32 874.1 151.3 3.143 2.967 1.817 dpm80 8 240.5 146.8 3.388 3.082 0.216 16 451.7 149.5 4.068 3.762 0.451 24 662.9 151.3 4.571 4.289 0.694 32 874.1 151.3 4.847 4.541 0.930 pin capacitance pin name value (pf) dp80 dpm80 ain 0.077 0.076 bin 0.071 0.071 cin 0.061 0.059
sec asic 6-21 STD80/stdm80 comparator features ? functional model, test vector, schematic, and layout generators ? timing model with auto-characterization ? fast signed comparison ? less than or equal and equal flags ? greater than or equal and equal flags ? greater than and equal flags ? less than and equal flags ? n -bit (4 to 128) comparator general description the comparator builds an n -bit wide comparator schematic. the schematic generated is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. the comparator supports signed comparisons. design description the logic circuit produced by the generator produces two different flags according to options. in case of greater than or equal and equal flags (a 3 b and a = b), two n -bit wide data operands (ain, bin) and two 1-bit wide outputs (ageb, aeqb) serve as the i/o signals to the module. in case of less than or equal and equal flags (a b and a = b), two 1-bit wide outputs (aleb, aeqb) serve as the i/o signals to the module. in case of greater than and equal flags (a > b and a = b), two 1-bit wide outputs (aeqb, agtb) serve as the i/o signals to the module. in case of less than and equal flags (a < b and a = b), two 1-bit wide outputs (altb and aeqb) serve as the i/o signals to the module. the comparator is built with a unique carry-bypass chain. the carry-bypass chain has a unique grouping of bits which modulates the group sizes to minimize carry propagation delay, which creates a high performance design. this scheme is optimized for the comparison of large data words to attain high speed. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type type of ?ags to be generated C 0: le, 1: ge, 2: lt, 3: gt 0/1/2/3 drv drive strength 1/2/4 ain [bitsC1:0] bin [bitsC1:0] aeqb aleb (optional) = <= >= < > ageb (optional) altb (optional) agtb (optional)
STD80/stdm80 6-22 sec asic comparator pin description function table truth table performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description ain [bitsC1:0] i data input bus a bin [bitsC1:0] data input bus b aeqb o equality ?ag (a = b) that speci?es the signed equality of input busses aleb (optional) less than or equal to ?ag (a b) ageb (optional) greater than or equal to ?ag (a 3 b) altb (optional) less than ?ag (a < b) agtb (optional) greater than ?ag (a > b) type function aeqb (equal) == aleb (less than or equal) <= ageb (greater than or equal) >= altb (less than) < agtb (greater than) > inputs outputs ain bin aeqb aleb ageb agtb altb 0011100 0101001 1000110 1111100 parameters : type = 1, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 213.2 105.3 2.651 2.433 0.099 16 424.4 108.7 2.439 1.831 0.184 24 635.6 112.3 2.671 2.453 0.248 32 846.8 110.7 3.109 2.051 0.340 dpm80 8 213.2 105.3 4.878 4.586 0.058 16 424.4 108.7 4.714 4.378 0.107 24 635.6 112.3 4.898 4.606 0.143 32 846.8 110.7 5.504 5.178 0.195 pin capacitance pin name value (pf) dp80 dpm80 ain 0.072 0.072 bin 0.075 0.075
sec asic 6-23 STD80/stdm80 decrementer features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? simple ripple and sophisticated carry-bypass scheme ? n -bit (4 to 128) decrementer ? buffered carry path ? three drive strengths on output general description the decrementer builds an n -bit wide decrementer schematic. the schematic generated is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. the decrementer supports signed decrements. design description the logic circuit produced by the generator performs decrement functions. an n -bit wide operand (ain), a 1-bit wide input carry signal (decn), and an n -bit wide output bus (sout) serve as the i/o signals to the module. the decrementer is built with a unique carry-bypass chain. the carry-bypass chain has a unique grouping of bits which modulates the group sizes to minimize delay which creates a high performance design. this scheme is optimized for the decrement of large data words to attain high speed. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 nopass 0: group bypass; 1: ripple adder 0/1 drv drive strength 1/2/4 ain [bitsC1:0] decn sout [bitsC1:0] C 1
STD80/stdm80 6-24 sec asic decrementer pin description function table truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description ain [bitsC1:0] i data input decn decrement signal which is active low sout [bitsC1:0] o data output C result of decrementer type function decrementer ain C 1 inputs output ain decn sout 0 1 0 1 1 1 0 0 1 1 0 0 pin name value (pf) dp80 dpm80 ain 0.023 0.023 decn 0.095 0.092 parameters : nopass = 0, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 213.2 94.5 2.449 2.165 0.095 16 424.4 96.7 2.825 2.207 0.207 24 635.6 99.8 3.027 2.809 0.240 32 846.8 99.8 3.225 2.607 0.315 dpm80 8 213.2 94.5 3.890 3.574 0.061 16 424.4 96.7 4.473 4.157 0.125 24 635.6 99.8 4.747 4.475 0.156 32 846.8 99.8 5.063 4.737 0.203
sec asic 6-25 STD80/stdm80 fast multiplier features ? functional model, test vector, schematic and layout generator ? timing model with auto-characterization ? fastest architecture for large multipliers ? supports twos complement multiplication ? three drive strength options for output general description the fast multiplier can be optimized for multiple-targeted technologies. the fast multiplier can build multipliers from 8-bits to 64-bits. there are output buffers which can be varied to three drive strengths. design description the fast multiplier is based on a modified wallace tree architecture, using the baugh-wooley algorithm to sum partial products for signed multiplication. the traditional wallace tree depends on a carry save adder (csa) which reduces three partial products to two redundant outputs (sum, carry). the modified wallace tree architecture is based on a 4-2 carry save adder (csa42). the csa42 reduces four partial products to two redundant outputs. this architecture reduces the number of partial products by two at each stage of the wallace tree so that the core of a 32 x 32 multiplication can be achieved in four csa42 delays. the final sum (msb) is generated by adding the final two redundant products from the multiplier core (sum, carry). the msb adder uses a double carry select architecture to generate the final sum. symbol parameter description notes: if m >= n, m = n, n+1, n+2, ..., 126 where n = 8, 12, 16, 20, 24, 32, 40 and 64 if m <= n, n = m, m+1, m+2, ..., 126 where m = 8, 12, 16, 20, 24, 32, 40 and 64 parameter name description range m multiplicand bits (x-input width) refer to the note. n multiplier bits (y-input width) refer to the note. drv 1x/2x/4x output drive strength 1/2/4 a [mC1:0] sout [m+nC1:0] b [nC1:0] x
STD80/stdm80 6-26 sec asic fast multiplier pin description pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description a [mC1:0] i data input C multiplicand b [nC1:0] data input C multiplier sout [m+nC1:0] o data output C result pin name value (pf) dp80 dpm80 a 0.040 0.039 b 0.040 0.039 parameters : drv = 1 library n x m area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 x 8 689.0 485.8 4.807 4.417 0.981 8 x 16 900.2 484.7 5.987 5.577 C 8 x 24 689.0 485.8 6.177 5.777 C 8 x 32 900.2 484.7 6.377 5.967 C 16 x 16 689.0 485.8 6.517 6.127 8.073 16 x 24 900.2 484.7 7.297 6.907 C 16 x 32 689.0 485.8 7.227 6.837 C 24 x 24 900.2 484.7 7.717 7.327 8.946 24 x 32 689.0 485.8 7.897 7.507 C 32 x 32 900.2 484.7 8.557 8.157 15.442 dpm80 8 x 8 689.0 485.8 7.378 6.956 0.648 8 x 16 900.2 484.7 8.928 8.456 C 8 x 24 689.0 485.8 9.468 8.996 C 8 x 32 900.2 484.7 9.808 9.336 C 16 x 16 689.0 485.8 9.878 9.396 5.260 16 x 24 900.2 484.7 11.058 10.586 C 16 x 32 689.0 485.8 11.058 10.576 C 24 x 24 900.2 484.7 11.738 11.306 5.920 24 x 32 689.0 485.8 12.138 11.606 C 32 x 32 900.2 484.7 13.238 12.806 10.147
sec asic 6-27 STD80/stdm80 incrementer features ? functional model, test vector, schematic, and layout generators ? timing model with auto-characterization ? simple ripple and sophisticated carry-bypass scheme ? n -bit (4 to 128) incrementer ? buffered carry path ? three drive strengths on output general description the incrementer builds an n -bit wide incrementer schematic. the schematic generated is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. the incrementer supports signed increments. design description the logic circuit produced by the generator performs increment functions. an n -bit wide operand (ain), a 1-bit wide input carry signal (cin), and an n -bit wide output bus (sout) and 1-bit output carry signal (cout) serve as the i/o signals to the module. the incrementer can be built with two different carry chains allowing speed/area trade-offs. the ripple carry chain is high in density and low in performance. the carry-bypass chain has a unique grouping of bits which creates a high performance design. this scheme is preferable for the increment of high order bits to attain high performance. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 nopass 0: group bypass; 1: ripple adder 0/1 drv drive strength 1/2/4 ain [bitsC1:0] cin sout [bitsC1:0] cout +1
STD80/stdm80 6-28 sec asic incrementer pin description function table truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description ain [bitsC1:0] i data input cin carry-in increment signal sout [bitsC1:0] o output data bus C result of incrementer cout carry-out signal type function incrementer ain + cin inputs output ain cin sout 0 0 0 1 0 1 0 1 1 1 1 0 pin name bit value (pf) dp80 dpm80 ain 8/16/24/32 0.143 0.139 cin 8/16/24/32 0.109 0.106 parameters : nopass = 0, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 213.2 88.7 2.087 1.479 0.085 16 424.4 94.9 2.155 1.861 0.154 24 635.6 92.3 2.426 2.208 0.222 32 846.8 92.5 2.514 1.897 0.291 dpm80 8 213.2 88.7 3.180 2.884 0.053 16 424.4 94.9 3.500 3.194 0.097 24 635.6 92.3 3.774 3.502 0.140 32 846.8 92.5 4.090 3.774 0.185
sec asic 6-29 STD80/stdm80 incrementer/decrementer features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? simple ripple and sophisticated carry-bypass scheme ? n -bit (4 to 128) incrementer/decrementer ? buffered carry path ? three multiple drive strengths options for output general description the incrementer/decrementer builds an n -bit wide incrementer/decrementer schematic. the schematic generated is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. the incrementer/decrementer supports signed decrements. design description the logic circuit produced by the generator performs increment or decrement function by control signal. an n -bit wide operand (ain), a 1-bit wide input control signal (ctrl), and an n -bit wide output bus (sout) serve as the i/o signals to the module. the incrementer/decrementer is built with a unique carry-bypass chain. the carry-bypass chain has a unique grouping of bits which modulates the group sizes to minimize carry propagation delay, which creates a high performance design. this scheme is optimized for the incrementer/decrementer of large data words to attain high speed. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 nopass 0: group bypass; 1: ripple adder 0/1 drv drive strength 1/2/4 ain [bitsC1:0] sout [(nC1):0] C 1 ctrl +1
STD80/stdm80 6-30 sec asic incrementer/decrementer pin description function table truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description ain [bitsC1:0] i data input ctrl i decrement signal which is active low, increment signal which is active high sout [bitsC1:0] o data output C result of incrementer or decrementer type function decrementer ainC1 incrementer ain+1 inputs output ain ctrl sout 0 1 1 1 1 0 0 0 1 1 0 0 pin name value (pf) dp80 dpm80 ain 0.053 0.052 ctrl 0.821 0.800 parameters : nopass = 0, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 213.2 100.6 2.784 2.500 0.05 16 424.4 107.5 3.169 2.875 0.08 24 635.6 106.1 3.381 3.153 0.08 32 846.8 106.3 3.569 3.275 0.11 dpm80 8 213.2 100.6 4.184 3.888 0.03 16 424.4 107.5 4.621 4.305 0.05 24 635.6 106.1 4.895 4.623 0.06 32 846.8 106.3 5.211 4.895 0.08
sec asic 6-31 STD80/stdm80 normalizer features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? n -bit (4 to 128) normalizer ? high performance ? outputs shift amount ? three drive strength options for output general description the normalizer detects the number of leading zeros in the input data word, and outputs the data word so the left-most 1 appears in the msb position, along with the shifted amount. if no 1 is detected in the data input, the all0 flag is set. the normalizer is a high performance datapath function which can build normalizers between 4-128 bits in 1 bit increments. design description the normalizer is built from 2 sub-functions, an priority encoder, and a left shifter. the priority encoder detects the left-most 1 from the data input word and outputs the amount to be shifted. then the amount is passed into the left shifter block and the leading 1 is shifted to the msb position with the lsb filled with 0. the priority encoder uses a parallel technique to calculate the high and low output address bits to speed up the leading 1 detection. a binary tree is used to determine the address of the high order bits, while a multiplexer tree is used to propagate the values of the low order bits. the left shifter is constructed as a series of cascaded 2-to-1 and 4-to-1 multiplexers. in its largest configuration (128 bits), three rows of 4-to-1 and one row of 2-to-1 muxs are used. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 drv drive strength 1/2/4 din [bitsC1:0] dout [bitsC1:0] shift [ log 2 bits e1:0] normalizer all0 round-up
STD80/stdm80 6-32 sec asic normalizer pin description round-up pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description din [bitsC1:0] i data input all0 o output ?ag that zeros all bits on the data input bus shift [ log 2 bits e1:0] data output e encoded address of the leading 1 bit dout [bitse1:0] normalized data output pin name bit value (pf) dp80 dpm80 din 8/24/32 0.184 0.172 16 0.322 0.296 parameters : drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 266.5 177.5 1.759 1.660 0.114 16 477.7 205.0 2.080 1.980 0.226 24 688.9 262.6 2.250 2.300 0.384 32 900.1 297.6 2.400 2.300 0.507 dpm80 8 266.5 177.5 2.586 2.504 0.068 16 477.7 205.0 3.036 2.964 0.136 24 688.9 262.6 3.246 3.414 0.230 32 900.1 297.6 3.486 3.414 0.307
sec asic 6-33 STD80/stdm80 one detector features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? fast datapath one flag ? n -bit (4 to 128) one detector ? three drive strength options for output general description the one detector builds an n -bit wide schematic that is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. the one detector detects 0 in the inputs and if there is no 0, it sets one to 1. design description the one detector performs deciding whether the input is one or not. an n -bit wide operand (ain) and a 1-bit wide one flag (one) serve as the i/o signals to the module. the one detector can be built with simple and gates. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 drv drive strength 1/2/4 a [bitsC1:0] one 1
STD80/stdm80 6-34 sec asic one detector pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description a [bitsC1:0] i data input one o it speci?es whether all the bits in the input a are 0 or 1. a one all 1 1 any 0 0 pin name value (pf) dp80 dpm80 a 0.036 0.035 parameters : drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 213.3 61.3 1.672 1.037 0.030 16 424.5 64.6 1.950 1.186 0.032 24 662.0 68.0 2.210 1.355 0.068 32 846.9 71.4 2.230 1.335 0.065 dpm80 8 213.3 61.3 2.477 1.580 0.030 16 424.5 64.6 2.907 1.786 0.032 24 662.0 68.0 3.287 1.986 0.068 32 846.9 71.4 3.327 1.986 0.065
sec asic 6-35 STD80/stdm80 parity features ? functional model, test-vector, schematic and layout generators ? timing model with auto-characterization ? n -bit (4 to 128) parity ? high speed and density ? three drive strength options for output general description the parity builds an n-bit wide parity schematic. the parity calculates the parity value of the specified input bits by performing the xor function across all inputs. the design is optimized for multiple targeted technologies. design description the parity uses a binary tree architecture for high speed calculations of the parity value. to minimize the area of the implementation, the layout cells used in the parity are placed in a single datapath row. it enables different drive strengths to be specified for the output. symbol parameter description parameter name description range instance_name name of parity generator to be created any string bits number of bits in the input data bus 4 to 128 drv drive strength 1/2/4 a [bitsC1:0] parity 1s = odd
STD80/stdm80 6-36 sec asic parity pin description pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description a [bitsC1:0] i data input bus for parity generation parity o output parity value for inputs (odd parity) pin name value (pf) dp80 dpm80 a 0.033 0.034 parameters : drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 188.3 58.5 1.444 1.180 0.030 16 399.5 64.2 1.803 1.459 0.032 24 635.6 67.4 2.000 1.385 0.068 32 821.9 71.1 2.000 1.736 0.065 dpm80 8 188.3 58.5 2.203 1.963 0.018 16 399.5 64.2 2.655 2.413 0.015 24 635.6 67.4 3.105 2.789 0.037 32 821.9 71.1 3.105 2.863 0.032
sec asic 6-37 STD80/stdm80 priority encoder features ? functional model, test-vectors, schematics and layout generators ? timing model with auto characterization ? high speed and density ? n -bit (4 to 128) priority encoder general description the priority encoder builds an n-bit wide schematic that is used to drive the datapath placement and routing tool in combination with technology-specific layout leafcells. the priority encoder detects the leading 1 on data bus. design description the priority encoder uses a parallel processing technique to calculate the high and low output address bits to speed up the leading 1 detection. a binary tree is used to determine the address of the high order bits, while a multiplexer tree is used to propagate the values of the low order bits. this design supports a wide range of input data width with a narrow delay time spectrum. it can create either a leftmost one or a rightmost one priority encoder. symbol parameter description parameter name description range instance_name name of priority encoder to be created any string bits number of bits in the input data bus 4 to 128 type 0: detect from msb; 1: detect from lsb 0/1 drv drive strength 1/2/4 a [bitsC1:0] dout [ log 2 bits e1:0] all0 pe round-up
STD80/stdm80 6-38 sec asic priority encoder pin description round-up pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description a [bitsC1:0] i data input bus for the leading one detection dout [ log 2 bits e1:0] o data output e encoded address of the leading 1 bit all0 output ?ag that zeros all bits on the data input bus pin name value (pf) dp80 dpm80 a 0.064 0.062 parameters : type = 0, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 213.2 91.7 1.612 1.940 0.030 16 424.4 99.6 1.934 2.260 0.057 24 635.6 109.8 2.104 2.590 0.068 32 846.8 118.4 2.264 2.590 0.207 dpm80 8 213.2 91.7 2.648 2.664 0.018 16 424.4 99.6 3.108 3.124 0.030 24 635.6 109.8 3.308 3.574 0.037 32 846.8 118.4 3.558 3,574 0.124
sec asic 6-39 STD80/stdm80 register file features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? configurable read/write ports for macro block ? address decoders on either side of the datapath block ? n -bit (4 to 128) register file general description the register file is optimized for multiple-targeted technologies. the register file can be built with one to four read ports and with one to two write ports. the maximum number of words is 128 and there can be up to 128 bits per word. design description the register file can be used as a stand-alone module or as part of a datapath block. to allow some flexibility, it allows you to place the control block to the right or left side of the register block. all read and write ports are independent. the read ports always output data; data will be changed after the read address has been changed. the write ports are enabled by ren and data is latched into the memory location on the falling edge of the clock. symbol (1read, 1write) parameter description parameter name description range words number of words in the register file 8 to 128 bits number of bits per word 8 to 128 writes number of write ports 1/2 reads number of read ports 1/2/3/4 control where to place control with respect to memory left/right clk ren w_addr0 [ log 2 words e1:0] r_addr0 [ log 2 words e1:0] d0 [bitse1:0] q0 [bitse1:0] round-up
STD80/stdm80 6-40 sec asic register file pin description round-up pin capacitance pin name i/o description clk clk [1:0] (when # (write port) = 1.) (when # (write port) = 2.) i clock signal (active-high) for each write port. when the clock is high, data pass into the decoded memory location and is latched on the falling clock edge. ren ren [1:0] (when # (write port) = 1.) (when # (write port) = 2.) register enable signal (active-low) for each write port. a high state prevents a write operation to the write port; a low state allows a write operation. w_addr0 [ log 2 words e1:0] data input e write address bus there is one address bus for each write port and there can be from 1 to 2 write ports. r_addr0 [ log 2 words e1:0] data input e read address bus there is one address bus for each read port and there can be from 1 to 4 read ports. d0 <0>...d0 [bitse1:0] input e word values written into the write port location during the write operation. there is one input bus for each write port. q0 <0>...q0 [bitse1:0] o output data previously written into the register tle data are present at all times and its value depends on the read address. there is one output bus for each read port. library word pin name clk d0 ren r_addr0 r_addr1 w_addr0 dp80 8 0.176 0.033 0.064 0.032 0.032 0.033 16 0.255 0.033 0.064 0.032 0.032 0.033 24 0.334 0.033 0.064 0.032 0.032 0.033 32 0.390 0.033 0.064 0.032 0.032 0.033 dpm80 8 0.173 0.032 0.062 0.031 0.031 0.032 16 0.250 0.032 0.062 0.031 0.031 0.032 24 0.327 0.032 0.062 0.031 0.031 0.032 32 0.381 0.032 0.062 0.031 0.031 0.032
sec asic 6-41 STD80/stdm80 register file performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) parameters : read = 1, write = 2, control = left library words x bit area ( m m x m m) delay (ns) width height t plh t phl dp80 8 x 8 237.6 343.2 2.490 2.070 8 x 16 448.8 343.2 2.570 2.160 8 x 24 660.0 343.2 2.650 2.260 8 x 32 871.2 343.2 2.730 2.360 16 x 8 237.6 549.9 2.900 2.460 16 x 16 448.8 549.9 2.980 2.560 16 x 24 660.0 549.9 3.060 2.650 16 x 32 871.2 549.9 3.140 2.750 24 x 8 237.6 740.5 3.051 2.601 24 x 16 448.8 740.5 3.131 2.701 24 x 24 660.0 740.5 3.211 2.801 24 x 32 871.2 740.5 3.291 2.891 32 x 8 237.6 924.1 3.361 2.901 32 x 16 448.8 924.1 3.441 3.001 32 x 24 660.0 924.1 3.521 3.091 32 x 32 871.2 924.1 3.601 3.191 dpm80 8 x 8 237.6 343.2 3.735 3.201 8 x 16 448.8 343.2 3.915 3.351 8 x 24 660.0 343.2 4.085 3.511 8 x 32 871.2 343.2 4.255 3.661 16 x 8 237.6 549.9 4.436 3.882 16 x 16 448.8 549.9 4.596 4.042 16 x 24 660.0 549.9 4.756 4.192 16 x 32 871.2 549.9 4.916 4.342 24 x 8 237.6 740.5 4.896 4.282 24 x 16 448.8 740.5 5.056 4.432 24 x 24 660.0 740.5 5.226 4.592 24 x 32 871.2 740.5 5.386 4.742 32 x 8 237.6 924.1 5.496 4.812 32 x 16 448.8 924.1 5.656 4.962 32 x 24 660.0 924.1 5.816 5.122 32 x 32 871.2 924.1 5.976 5.272
STD80/stdm80 6-42 sec asic register file timing diagram write operation read operation note : not allowed to read and write in the same location at the same time. timing parameters symbol description input output t dsetup input data setup time d0 C t dhold input data hold time d0 C t ensetup ren setup time ren C t enhold ren hold time ren C t asetup w_addr setup time w_addr C t ahold w_addr hold time w_addr C pwh clk pulse width high clk C pwl clk pulse width low clk C t d read access time r_addr q0 d0 ren w_addr0 valid clk t dsetup valid t dhold t ensetup t enhold pwh pwl t asetup t ahold r_addr0 valid t d valid q0
sec asic 6-43 STD80/stdm80 register file timing requirements parameters : read = 1, write = 2, control = left words x bit timing field value (ns) dp80 dpm80 8 x 8 min_pulse_width_high clk 0.576 0.686 min_pulse_width_low clk 0.333 0.801 hold_rising d0 ren 0.100 0.237 hold_falling d0 clk 0.136 0.273 hold_rising ren clk C0.472 C0.741 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.339 0.345 setup_falling d0 clk 0.364 0.347 setup_rising ren clk 0.970 1.430 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 8 x 16 min_pulse_width_high clk 0.698 0.874 min_pulse_width_low clk 0.469 1.010 hold_rising d0 ren 0.146 0.325 hold_falling d0 clk 0.182 0.374 hold_rising ren clk C0.488 C0.788 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.293 0.257 setup_falling d0 clk 0.318 0.246 setup_rising ren clk 0.987 1.450 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 8 x 24 min_pulse_width_high clk 0.820 1.060 min_pulse_width_low clk 0.605 1.210 hold_rising d0 ren 0.192 0.414 hold_falling d0 clk 0.228 0.476 hold_rising ren clk C0.503 C0.836 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.247 0.169 setup_falling d0 clk 0.272 0.144 setup_rising ren clk 1.000 1.470 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100
STD80/stdm80 6-44 sec asic register file timing requirements (cont.) parameters : read = 1, write = 2, control = left words x bit timing field value (ns) dp80 dpm80 8 x 32 min_pulse_width_high clk 0.941 1.250 min_pulse_width_low clk 0.741 1.420 hold_rising d0 ren 0.238 0.502 hold_falling d0 clk 0.274 0.577 hold_rising ren clk C0.519 C0.883 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.201 0.080 setup_falling d0 clk 0.226 0.043 setup_rising ren clk 1.020 1.490 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 16 x 8 min_pulse_width_high clk 0.576 0.686 min_pulse_width_low clk 0.333 0.801 hold_rising d0 ren 0.100 0.237 hold_falling d0 clk 0.136 0.273 hold_rising ren clk C0.726 C1.170 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.339 0.345 setup_falling d0 clk 0.364 0.347 setup_rising ren clk 1.360 1.940 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 16 x 16 min_pulse_width_high clk 0.698 0.874 min_pulse_width_low clk 0.469 1.010 hold_rising d0 ren 0.146 0.325 hold_falling d0 clk 0.182 0.374 hold_rising ren clk C0.742 C1.220 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.293 0.257 setup_falling d0 clk 0.318 0.246 setup_rising ren clk 1.380 1.960 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100
sec asic 6-45 STD80/stdm80 register file timing requirements (cont.) parameters : read = 1, write = 2, control = left words x bit timing field value (ns) dp80 dpm80 16 x 24 min_pulse_width_high clk 0.820 1.060 min_pulse_width_low clk 0.605 1.210 hold_rising d0 ren 0.192 0.414 hold_falling d0 clk 0.228 0.476 hold_rising ren clk C0.757 C1.270 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.247 0.169 setup_falling d0 clk 0.272 0.144 setup_rising ren clk 1.400 1.980 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 16 x 32 min_pulse_width_high clk 0.941 1.250 min_pulse_width_low clk 0.741 1.420 hold_rising d0 ren 0.238 0.502 hold_falling d0 clk 0.274 0.577 hold_rising ren clk C0.773 C1.310 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.201 0.080 setup_falling d0 clk 0.226 0.043 setup_rising ren clk 1.410 2.000 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 24 x 8 min_pulse_width_high clk 0.576 0.686 min_pulse_width_low clk 0.333 0.801 hold_rising d0 ren 0.100 0.237 hold_falling d0 clk 0.136 0.273 hold_rising ren clk C0.953 C1.600 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.339 0.345 setup_falling d0 clk 0.364 0.347 setup_rising ren clk 1.760 2.450 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100
STD80/stdm80 6-46 sec asic register file timing requirements (cont.) parameters : read = 1, write = 2, control = left words x bit timing field value (ns) dp80 dpm80 24 x 16 min_pulse_width_high clk 0.698 0.874 min_pulse_width_low clk 0.469 1.010 hold_rising d0 ren 0.146 0.325 hold_falling d0 clk 0.182 0.374 hold_rising ren clk C0.961 C1.650 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.293 0.257 setup_falling d0 clk 0.318 0.246 setup_rising ren clk 1.770 2.470 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 24 x 24 min_pulse_width_high clk 0.820 1.060 min_pulse_width_low clk 0.605 1.210 hold_rising d0 ren 0.192 0.414 hold_falling d0 clk 0.228 0.476 hold_rising ren clk C0.969 C1.700 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.247 0.169 setup_falling d0 clk 0.272 0.144 setup_rising ren clk 1.790 2.500 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 24 x 32 min_pulse_width_high clk 0.941 1.250 min_pulse_width_low clk 0.741 1.420 hold_rising d0 ren 0.238 0.502 hold_falling d0 clk 0.274 0.577 hold_rising ren clk C0.977 C1.740 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.201 0.080 setup_falling d0 clk 0.226 0.043 setup_rising ren clk 1.810 2.550 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100
sec asic 6-47 STD80/stdm80 register file timing requirements (cont.) parameters : read = 1, write = 2, control = left words x bit timing field value (ns) dp80 dpm80 32 x 8 min_pulse_width_high clk 0.576 0.686 min_pulse_width_low clk 0.333 0.801 hold_rising d0 ren 0.100 0.237 hold_falling d0 clk 0.136 0.273 hold_rising ren clk C1.130 C2.030 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.339 0.345 setup_falling d0 clk 0.364 0.347 setup_rising ren clk 2.150 3.010 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 32 x 16 min_pulse_width_high clk 0.698 0.874 min_pulse_width_low clk 0.469 1.010 hold_rising d0 ren 0.146 0.325 hold_falling d0 clk 0.182 0.374 hold_rising ren clk C1.140 C2.080 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.293 0.257 setup_falling d0 clk 0.318 0.246 setup_rising ren clk 2.170 3.060 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100 32 x 24 min_pulse_width_high clk 0.820 1.060 min_pulse_width_low clk 0.605 1.210 hold_rising d0 ren 0.192 0.414 hold_falling d0 clk 0.228 0.476 hold_rising ren clk C1.150 C2.130 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.247 0.169 setup_falling d0 clk 0.272 0.144 setup_rising ren clk 2.180 3.110 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100
STD80/stdm80 6-48 sec asic register file timing requirements (cont.) parameters : read = 1, write = 2, control = left words x bit timing field value (ns) dp80 dpm80 32 x 32 min_pulse_width_high clk 0.941 1.250 min_pulse_width_low clk 0.741 1.420 hold_rising d0 ren 0.238 0.502 hold_falling d0 clk 0.274 0.577 hold_rising ren clk C1.150 C2.180 hold_falling ren clk C0.200 C0.200 hold_falling w_addr0 clk C0.200 C0.200 setup_rising d0 ren 0.201 0.080 setup_falling d0 clk 0.226 0.043 setup_rising ren clk 2.200 3.160 setup_falling ren clk 0.800 1.100 setup_falling w_addr0 clk 0.800 1.100
sec asic 6-49 STD80/stdm80 saturating adder features ? functional model, test vector, schematic, and layout generators ? timing model with auto-characterization ? high performance saturation scheme ? twos complement overflow flag ? n -bit (4 to 128) saturating adder ? three drive strength options for output general description the saturating adder builds an n -bit wide adder schematic that is used to drive the datapath place and route tool in combination with technology-specific layout leaf cells. the saturate flag saturates the output to the largest positive number on an overflow or to the smallest negative number on an underflow. design description the saturating adder performs addition functions. an n -bit wide operand (ain), an n -bit wide operand (bin), a 1-bit wide input carry signal (cin), and an n -bit wide output bus (sout) and a 1-bit saturation flag (sat) serve as the i/o signals to the module. the saturating adder can be built with two different carry chains allowing speed/area trade-offs. the ripple carry chain is high in density, with lower performance. the carry-bypass chain has a unique grouping of bits which creates a high performance design. this scheme is preferable for the addition of large data words to attain high speed. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 nopass 0: group bypass; 1: ripple adder 0/1 drv drive strength 1/2/4 ain [bitsC1:0] sout [bitsC1:0] bin [bitsC1:0] cin sat sat
STD80/stdm80 6-50 sec asic saturating adder pin description function table truth table performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description ain [bitsC1:0] i data input bin [bitsC1:0] data input cin carry-in sat o saturate ?ag sout output result of addition type function sout ain + bin + cin if (ain and bin have positive values, and sat output becomes 1), then sout [bitsC2:0] = 1, sout [bitsC1] = 0. if (ain and bin have negative values, and sat output becomes 1), then sout [bitsC2:0] = 0, sout [bitsC1] = 1. sat if the result of two positive numbers addition is negative value or the result of two negative numbers addition is positive, then sat is 1. inputs outputs ain bin cin sout sat 00000 00011 01000 11010 00110 10100 01101 11110 parameters : nopass = 0, drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 266.4 134.9 3.685 3.395 0.313 16 477.6 135.1 4.265 3.965 0.599 24 688.8 138.2 4.595 4.285 0.872 32 900.0 137.4 5.015 4.685 1.148 dpm80 8 266.4 134.9 5.944 5.406 0.203 16 477.6 135.1 6.804 6.266 0.388 24 688.8 138.2 7.484 6.936 0.563 32 900.0 137.4 8.034 7.496 0.737 pin capacitance pin name value (pf) dp80 dpm80 ain 0.049 0.048 bin 0.039 0.039 cin 0.095 0.092
sec asic 6-51 STD80/stdm80 zero detector features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? fast datapath zero flag ? n -bit (4 to 128) zero detector ? three drive strength options for output general description the zero detector builds an n -bit wide schematic that is used to drive the datapath placement and routing tool in combination with technology-specific layout leaf cells. the zero detector detects 1 in the inputs and if there is no 1, it sets zero to 1. design description the zero detector performs deciding whether the input is zero or not. an n -bit wide operand (ain) and a 1-bit wide zero flag (zero) serve as the i/o signals to the module. the zero detector can be built with simple or gates. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 drv drive strength 1/2/4 a [bitsC1:0] zero 0
STD80/stdm80 6-52 sec asic zero detector pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf, f = 10mhz) pin name i/o description a [bitsC1:0] i data input zero o it speci?es whether all the bits in the input a are 0 or 1. a zero all 0 1 any 1 0 pin name value (pf) dp80 dpm80 a 0.023 0.023 parameters : drv = 1 library bit area ( m m x m m) delay (ns) current (ma) width height t plh t phl dp80 8 213.3 59.6 1.468 1.054 0.030 16 424.5 61.6 1.633 1.242 0.032 24 662.0 65.1 1.797 1.416 0.068 32 846.9 68.4 1.797 1.430 0.065 dpm80 8 213.3 59.6 2.214 1.522 0.030 16 424.5 61.6 2.524 1.770 0.032 24 662.0 65.1 2.814 2.010 0.068 32 846.9 68.4 2.814 2.030 0.065
sec asic 6-53 STD80/stdm80 and-or features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for types 21 and 22 ? two drive strength options for output general description the high performance datapath and-or design can be optimized for multiple-targeted technologies. the generator can build and-or gates ranging from 4-bits to 128-bits for two different configurations (21 and 22) and two different drive strengths. design description the and-or design has schematic and layout generators that can build a variety of and-or gates. you have an option to build the different kinds of structure configurations by setting the type parameter to 21/22 depending on your application. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type con?guration type 21/22 drv drive strength 1/2 ao21 ao22 ii00 ii01 o ii10 o ii00 ii01 ii11 ii10
STD80/stdm80 6-54 sec asic and-or pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) ao22 pin name i/o description ii00 [bitsC1:0] i data input ii01 [bitsC1:0] data input ii10 [bitsC1:0] data input ii11 [bitsC1:0] data input o o data output ao21 inputs output ii00 ii01 ii10 o xx11 x000 0x 00 1101 ao21 pin name value (pf) dp80 dpm80 ii10 0.023 0.023 ii01 0.024 0.023 ii00 0.024 0.023 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl ao21 8/16/24/32 26.4 x bits 54.7 0.923 0.816 1.367 1.285 ao22 8/16/24/32 26.4 x bits 54.7 1.043 0.792 1.489 1.277 ao22 inputs output ii00 ii01 ii10 ii11 o x0x00 0xx00 x00x0 0x0x0 11xx1 xx111 ao22 pin name value (pf) dp80 dpm80 ii11 0.024 0.023 ii10 0.023 0.022 ii01 0.024 0.024 ii00 0.024 0.023
sec asic 6-55 STD80/stdm80 and-or-invert features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for types 21 and 22 ? two drive strength options for output general description the high performance datapath and-or-invert design can be optimized for multiple-targeted technologies. the generator can build and-or-invert gates ranging from 4-bits to 128-bits for two different configurations (21 and 22) and two different drive strengths. design description the and-or-invert design has schematic and layout generators that can build a variety of and-or-invert gates. you have an option to build the different kinds of and-or-invert structure configurations by setting the type parameter to 21/22 depending on your application. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type con?guration type 21/22 drv drive strength 1/2 aoi21 aoi22 ii00 ii01 o ii10 o ii00 ii01 ii11 ii10
STD80/stdm80 6-56 sec asic and-or-invert pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) aoi22 pin name i/o description ii00 [bitsC1:0] i data input ii01 [bitsC1:0] data input ii10 [bitsC1:0] data input ii11 [bitsC1:0] data input o o data output aoi21 inputs output ii00 ii01 ii10 o xx10 x001 0x 01 1100 aoi21 pin name value (pf) dp80 dpm80 ii10 0.023 0.023 ii01 0.024 0.024 ii00 0.024 0.024 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl aoi21 8/16/24/32 26.4 x bits 54.5 1.213 0.738 1.715 1.051 aoi22 8/16/24/32 26.4 x bits 58.4 1.213 0.858 1.735 1.193 aoi22 inputs output ii00 ii01 ii10 ii11 o x0x01 0xx01 x00x1 0x0x1 11xx0 xx110 aoi22 pin name value (pf) dp80 dpm80 ii11 0.024 0.024 ii10 0.023 0.022 ii01 0.025 0.025 ii00 0.024 0.024
sec asic 6-57 STD80/stdm80 buffer/inverter features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for buffer/inverter design ? four drive strength options for output general description the high performance buffer/inverter design is optimized for multiple-targeted technologies. the generator design has the capability to build buffers/inverters ranging from 4-bits to 128-bits for various drive strength configurations. design description the buffer/inverter design has schematic and layout generators that can build a variety of buffers and inverters. you have an option to select either buffer or inverter by setting the type parameter to 1 or 0 respectively. the design supports four different drive strength options (1x, 2x, 4x and 8x). symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type type of a cell to be generated; 0: inverter; 1: buffer 0/1 drv drive strength 1/2/4/8 buffer inverter i o i o
STD80/stdm80 6-58 sec asic buffer/inverter pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf ) pin name description i [bitsC1:0] input o [bitsC1:0] output buffer io 00 11 pin name value (pf) buffer inverter dp80 dpm80 dp80 dpm80 i 0.023 0.022 0.031 0.030 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl buffer 8/16/24/32 26.4 x bits 55.7 0.843 0.642 1.249 0.943 inverter 8/16/24/32 26.4 x bits 53.6 0.913 0.521 1.314 0.789 inverter io 01 10
sec asic 6-59 STD80/stdm80 bus holder features ? variable word width of 4 to 128 bits general description the high performance datapath bus holder design can be optimized for multiple-targeted technologies. the generator can build bus holders ranging from 4-bits to 128-bits. design description the bus holder design has schematic and layout generators that can build a variety of bus holders. the primary function of the bus holder is to hold the previous state, when the drivers on a bus go tri-stated. symbol parameter description pin description pin capacitance parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 pin name description i [bitsC1:0] data input pin name value (pf) dp80 dpm80 i 0.055 0.054 i
STD80/stdm80 6-60 sec asic d flip-flop features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? separate load enable line ? scan logic, set, reset and tri-stated output with enable high input options ? clock edge specification option ? tri-stated, normal and inverted outputs ? two drive strength options for output general description the high performance d flip-flop design can be optimized for multiple-targeted technologies. the generator can build d flip-flops ranging from 4-bits to 128-bits, with scan logic, set, reset and tri-stated output with enable high input options. the clock edge specification can also be controlled by users, either positive or negative edged. this generator supports a tri-state output and two different drive strengths. design description the d flip-flop design has schematic and layout generators that can build a variety of d flip-flops depending on the parameters set. the design supports scan inputs with test enable input. you can also have set, reset input along with the scan inputs, and tri-stated output with enable high input. the clock edge can be specified by setting the clk parameter to 0 or 1 (negative clk or positive clk respectively). both q (normal data out), qn (inverted data out) and qt (tri-state data output) are available. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 scan scan inputs C 0: no scan; 1: scan 0/1 set set C 0: no; 1: set 0/1 rst reset C 0: no; 1: reset 0/1 tri tri-stated output with enable high input 0/1 q normal data output 0/1 qn inverted data output 0/1 clk clock edge spec. C 0: negative clk; 1: positive clk 0/1 drv drive strength 1/4 d [bitsC1:0] q [bitsC1:0] qt [bitsC1:0] (optional) en [bitsC1:0] (optional) ti [bitsC1:0] (optional) te (optional) setn (optional) reset (optional) clk qn [bitsC1:0] (optional)
sec asic 6-61 STD80/stdm80 d flip-flop pin description truth table pin name i/o description d [bitsC1:0] i data input en [bitsC1:0] enable input (optional when tri = 1) ti [bitsC1:0] test input (optional when scan = 1) te test enable input (optional when scan = 1) setn set input (optional when set = 1) reset reset input (optional when rst = 1) clk clock input (positive- or negative-edge) q [bitsC1:0] o normal data output qn [bitsC1:0] inverted data output (optional when qn = 1) qt [bitsC1:0] tri-stated data output (optional when tri = 1) positive edge trigger (clk = 1) inputs outputs d clk en setn reset ti te q (n+1) qn (n+1) qt (n+1) x x 0 x x x x x x hi-z xx100xx101 xx101xx101 xx111xx010 d 1 1 0 x 0 q (n) qn (n) qt (n) d - 1 1 0 x 0 d ~d d x 1 1 0 d 1 q (n) qn (n) qt (n) x - 1 1 0 d 1 d ~d d negative edge trigger (clk = 0) inputs outputs d clk en setn reset ti te q (n+1) qn (n+1) qt (n+1) x x 0 x x x x x x hi-z xx100xx101 xx101xx101 xx111xx010 d - 1 1 0 x 0 q (n) qn (n) qt (n) d 1 1 0 x 0 d ~d d x - 1 1 0 d 1 q (n) qn (n) qt (n) x 1 1 0 d 1 d ~d d
STD80/stdm80 6-62 sec asic d flip-flop pin capacitance pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 0, rst = 0, set = 0, scan = 0, clk = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.031 0.031 (parameters : qn = 1, q = 1, tri = 0, rst = 0, set = 0, scan = 0, clk = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.031 0.031 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 0, clk = 0, drv = 1) clk 8 0.272 0.264 16 0.544 0.528 24 0.816 0.792 32 1.088 1.056 d 8/16/24/32 0.031 0.031 en 8/16/24/32 0.023 0.023 qt 8/16/24/32 0.027 0.028 (parameters : qn = 1, q = 1, tri = 0, rst = 1, set = 0, scan = 0, clk = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.031 0.031 reset 8 0.424 0.416 16 0.848 0.832 24 1.272 1.248 32 1.696 1.664 pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst =1, set = 0, scan = 0, clk = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 en 8/16/24/32 0.023 0.022 reset 8 0.408 0.400 16 0.816 0.800 24 1.224 1.200 32 1.632 1.600 qt 8/16/24/32 0.027 0.028 (parameters : qn = 0, q = 1, tri = 0, rst = 1, set = 1, scan = 0, clk = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.031 0.031 reset 8 0.416 0.416 16 0.832 0.832 24 1.248 1.248 32 1.664 1.664 setn 8 0.416 0.408 16 0.832 0.816 24 1.248 1.224 32 1.664 1.632
sec asic 6-63 STD80/stdm80 d flip-flop pin capacitance (cont.) pin name bit value (pf) dp80 dpm80 (parameters : qn = 1, q = 1, tri = 0, rst =1, set = 1, scan = 0, clk = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.031 0.030 reset 8 0.424 0.408 16 0.848 0.832 24 1.272 1.248 32 1.696 1.664 setn 8 0.424 0.408 16 0.848 0.832 24 1.272 1.224 32 1.696 1.632 (parameters : qn = 0, q = 1, tri = 1, rst =1, set = 1, scan = 0, clk = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.031 0.030 en 8/16/24/32 0.023 0.023 reset 8 0.416 0.392 16 0.832 0.784 24 1.248 1.176 32 1.664 1.568 setn 8 0.400 0.400 16 0.800 0.800 24 1.200 1.200 32 1.600 1.600 qt 8/16/24/32 0.027 0.029 pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst =1, set = 1, scan = 1, clk = 0, drv = 1) clk 8 0.272 0.264 16 0.544 0.528 24 0.816 0.792 32 1.088 1.056 d 8/16/24/32 0.051 0.049 en 8/16/24/32 0.023 0.023 te 8 0.192 0.192 16 0.384 0.384 24 0.576 0.576 32 0.768 0.768 ti 8/16/24/32 0.052 0.050 qt 8/16/24/32 0.026 0.028 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan = 1, clk = 0, drv = 1) clk 8 0.272 0.264 16 0.544 0.528 24 0.816 0.792 32 1.088 1.056 d 8/16/24/32 0.053 0.051 en 8/16/24/32 0.023 0.023 reset 8 0.424 0.416 16 0.848 0.832 24 1.272 1.248 32 1.696 1.664 setn 8 0.416 0.408 16 0.832 0.816 24 1.248 1.224 32 1.664 1.632 te 8 0.192 0.200 16 0.384 0.400 24 0.576 0.600 32 0.768 0.800 ti 8/16/24/32 0.052 0.050 qt 8/16/24/32 0.027 0.029
STD80/stdm80 6-64 sec asic d flip-flop pin capacitance (cont.) pin name bit value (pf) dp80 dpm80 (parameters : qn = 1, q = 1, tri = 0, rst =0, set = 0, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 (parameters : qn = 0, q = 1, tri = 1, rst =0, set = 0, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 en 8/16/24/32 0.023 0.023 qt 8/16/24/32 0.027 0.028 (parameters : qn = 1, q = 1, tri = 0, rst 01, set = 0, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 reset 8 0.416 0.392 16 0.832 0.784 24 1.248 1.176 32 1.664 1.568 pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst =1, set = 0, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 en 8/16/24/32 0.023 0.022 reset 8 0.400 0.392 16 0.800 0.784 24 1.200 1.176 32 1.600 1.568 qt 8/16/24/32 0.027 0.028 (parameters : qn = 1, q = 1, tri = 0, rst =1, set = 1, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 reset 8 40.8 0.400 16 0.816 0.800 24 1.224 1.200 32 1.632 1.600 setn 8 0.408 0.400 16 0.816 0.800 24 1.224 1.200 32 1.632 1.600
sec asic 6-65 STD80/stdm80 d flip-flop pin capacitance (cont.) pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 0, rst = 1, set = 1, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.031 0.030 reset 8 0.416 0.392 16 0.832 0.784 24 1.248 1.176 32 1.664 1.568 setn 8 0.408 0.400 16 0.816 0.800 24 1.224 1.200 32 1.632 1.600 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan = 0, clk = 1, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.031 0.030 en 8/16/24/32 0.023 0.023 reset 8 0.408 0.416 16 0.816 0.832 24 1.224 1.248 32 1.632 1.664 setn 8 0.408 0.400 16 0.816 0.800 24 1.224 1.200 32 1.632 1.600 qt 8/16/24/32 0.027 0.029 pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 1, clk = 1, drv = 1) clk 8 0.256 0.256 16 0.512 0.512 24 0.768 0.768 32 1.024 1.024 d 8/16/24/32 0.052 0.051 en 8/16/24/32 0.023 0.023 te 8 0.192 0.200 16 0.384 0.400 24 0.576 0.600 32 0.768 0.800 ti 8/16/24/32 0.024 0.025 qt 8/16/24/32 0.027 0.028 (parameters : qn = 0, q = 1, tri = 1, rst =1, set = 1, scan = 1, clk = 1, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.052 0.050 en 8/16/24/32 0.023 0.023 reset 8 0.416 0.408 16 0.832 0.816 24 1.248 1.224 32 1.664 1.632 setn 8 0.408 0.400 16 0.816 0.800 24 1.224 1.200 32 1,632 1.600 te 8 0.192 0.200 16 0.384 0.400 24 0.576 0.600 32 0.768 0.800 ti 8/16/24/32 0.024 0.025 qt 8/16/24/32 0.027 0.029
STD80/stdm80 6-66 sec asic d flip-flop performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 0, rst = 0, set = 0, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 73.6 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.200 0.400 hold_falling d clk 0.200 0.200 setup_falling d clk 0.500 0.600 t plh 1.277 1.774 t phl 1.138 1.508 (parameters : qn = 1, q = 1, tri = 0, rst = 0, set = 0, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 77.8 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.200 0.400 hold_falling d clk 0.200 0.200 setup_falling d clk 0.500 0.600 t plh 1.327 1.837 t phl 1.168 1.543 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 88.3 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 hold_falling d clk 0.200 0.200 setup_falling d clk 0.500 0.600 t plh 1.903 2.964 t phl 1.383 1.940 (parameters : qn = 1, q = 1, tri = 0, rst = 1, set = 0, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 84.1 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.200 0.400 min_pulse_width_high reset 0.250 0.350 hold_falling d clk 0.200 0.200 setup_falling d clk 0.500 0.600 t plh 1.397 1.985 t phl 1.158 1.519
sec asic 6-67 STD80/stdm80 d flip-flop performance table (cont.) (t = 25 c, slope = 1.0ns, cap. = 0.4pf) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 0, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 92.5 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 hold_falling d clk 0.200 0.200 setup_falling d clk 0.500 0.600 t plh 1.963 3.013 t phl 1.383 1.949 (parameters : qn = 0, q = 1, tri = 0, rst = 1, set = 1, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits delay (ns) height 79.9 min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.200 0.400 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.200 0.400 hold_falling d clk 0.200 0.200 setup_falling d clk 0.500 0.600 t plh 1.337 1.869 t phl 1.158 1.525 (parameters : qn = 1, q = 1, tri = 0, rst = 1, set = 1, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 84.1 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.200 0.400 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.200 0.400 hold_falling d clk 0.200 0.200 setup_falling d clk 0.500 0.600 t plh 1.407 1.983 t ph 1.208 1.597
STD80/stdm80 6-68 sec asic d flip-flop performance table (cont.) (t = 25 c, slope = 1.0ns, cap. = 0.4pf) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan = 0, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 92.5 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.250 0.350 hold_falling d clk 0.100 0.100 setup_falling d clk 0.500 0.600 t plh 1.973 3.059 t phl 1.423 1.994 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 1, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 94.6 delay (ns) min_pulse_width_high clk 0.400 0.350 min_pulse_width_low clk 0.250 0.350 hold_falling d clk 0.100 0.100 hold_falling ti clk 0.100 0.100 setup_falling d clk 0.600 0.700 setup_falling ti clk 0.600 0.700 t plh 1.903 2.927 t phl 1.383 1.953 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan = 1, clk = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 100.5 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.300 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.250 0.300 hold_falling d clk 0.100 0.000 hold_falling ti clk 0.100 0.000 setup_falling d clk 0.600 0.800 setup_falling ti clk 0.600 0.700 t plh 1.973 3.067 t phl 1.423 2.013
sec asic 6-69 STD80/stdm80 d flip-flop performance table (cont.) (t = 25 c, slope = 1.0ns, cap. = 0.4pf) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 0, rst = 0, set = 0, scan = 0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 73.6 delay (ns) min_pulse_width_high clk 0.200 0.300 min_pulse_width_low clk 0.250 0.350 hold_falling d clk e0.100 e0.100 setup_falling d clk 0.500 0.600 t plh 1.167 1.726 t phl 0.858 1.254 (parameters : qn = 1, q = 1, tri = 0, rst = 0, set = 0, scan = 0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 77.8 delay (ns) min_pulse_width_high clk 0.200 0.300 min_pulse_width_low clk 0.250 0.350 hold_falling d clk e0.100 e0.100 setup_falling d clk 0.500 0.600 t plh 1.217 1.767 t phl 0.989 1.283 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 88.3 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 hold_falling d clk e0.100 e0.100 setup_falling d clk 0.500 0.600 t plh 1.823 2.897 t phl 1.143 1.689 (parameters : qn = 1, q = 1, tri = 0, rst = 1, set = 0, scan = 0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 84.1 delay (ns) min_pulse_width_high clk 0.200 0.300 min_pulse_width_low clk 0.400 0.350 min_pulse_width_high reset 0.200 0.300 hold_falling d clk e0.100 e0.100 setup_falling d clk 0.500 0.600 t plh 1.297 1.913 t phl 0.933 1.406
STD80/stdm80 6-70 sec asic d flip-flop performance table (cont.) (t = 25 c, slope = 1.0ns, cap. = 0.4pf) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 0, scan = 0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 92.5 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 hold_falling d clk e0.100 e0.100 setup_falling d clk 0.500 0.600 t plh 1.853 2.942 t phl 1.113 1.627 (parameters : qn = 0, q = 1, tri = 0, rst = 1, set = 1, scan =0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 79.9 delay (ns) min_pulse_width_high clk 0.200 0.300 min_pulse_width_low clk 0.250 0.400 min_pulse_width_high reset 0.200 0.300 min_pulse_width_low setn 0.350 0.400 hold_falling d clk e0.100 e0.100 setup_falling d clk 0.500 0.600 t plh 1.237 1.831 t phl 0.898 1.315 (parameters : qn = 1, q = 1, tri = 0, rst = 1, set = 1, scan = 0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 84.1 delay (ns) min_pulse_width_high clk 0.250 0.300 min_pulse_width_low clk 0.300 0.400 min_pulse_width_high reset 0.250 0.300 min_pulse_width_low setn 0.300 0.400 hold_rising d clk e0.100 e0.100 t plh 1.297 0.000 t phl 0.938 0.000
sec asic 6-71 STD80/stdm80 d flip-flop performance table (cont.) (t = 25 c, slope = 1.0ns, cap. = 0.4pf) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan = 0, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 92.5 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.250 0.350 hold_rising d clk e0.100 e0.100 setup_rising d clk 0.500 0.600 t plh 1.863 2.946 t phl 1.153 1.691 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 1, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 94.6 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 hold_falling d clk e0.100 e0.200 hold_rising ti clk e0.100 e0.200 setup_rising d clk 0.500 0.700 setup_falling ti clk 0.500 0.700 t plh 1.823 2.907 t phl 1.143 1.683 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan = 1, clk = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 100.5 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_low clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.250 0.350 hold_falling d clk e0.100 e0.200 hold_rising ti clk e0.100 e0.300 setup_rising d clk 0.500 0.700 setup_falling ti clk 0.500 0.700 t plh 1.863 2.946 t phl 1.153 1.683
STD80/stdm80 6-72 sec asic full adder features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? two drive strength options for output general description the high performance datapath full adder design can be optimized for multiple-targeted technologies. this generator can build full adders ranging from 4-bits to 128-bits, supporting two different drive strengths. design description the full adder design has schematic and layout generators that can build a variety of full adders. the design supports two different drive strengths (1x and 2x). the sum output is expressed as: sout = ain ? bin ? cin the carry output is expressed as: cout = {(ain | bin) & cin} | (ain & bin) symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 drv drive strength 1/2 sout [bitsC1:0] cout [bitsC1:0] ain [bitsC1:0] bin [bitsC1:0] cin [bitsC1:0] +
sec asic 6-73 STD80/stdm80 full adder pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) pin name i/o description ain [bitsC1:0] i input ain bin [bitsC1:0] input bin cin [bitsC1:0] carry-in cin sout [bitsC1:0] o sum output cout [bitsC1:0] carry output inputs outputs ain bin cin sout cout 00000 00110 01010 01101 10010 10101 11001 11111 pin name value (pf) dp80 dpm80 ain 0.056 0.056 bin 0.072 0.065 cin 0.067 0.064 bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl 8/16/24/32 26.4 x bits 75.7 1.287 0.936 1.817 1.448
STD80/stdm80 6-74 sec asic latch features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? separate load enable line ? scan logic, set, reset and tri-stated output with enable high input options ? tri-stated, normal and inverted output ? two drive strength options for output general description the high performance latch design can be optimized for multiple-targeted technologies. the generator can build latches ranging from 4-bits to 128-bits, with scan logic and set, reset and tri-stated output with enable high input options.this generator supports two different drive strengths. design description the latch design has schematic and layout generators that can build a variety of latches depending on the parameters set. the design supports scan inputs with test enable input. you can also have set or reset input, and tri-stated output with enable high input. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 scan scan inputs C 0: no scan; 1: scan 0/1 set set C 0: no; 1: set 0/1 rst reset C 0: no; 1: reset 0/1 tri tri-stated output with enable high input 0/1 q normal data output 0/1 qn inverted data output 0/1 drv drive strength 1/4 d [bitsC1:0] q [bitsC1:0] qt [bitsC1:0] (optional) en [bitsC1:0] (optional) ti [bitsC1:0] (optional) te (optional) setn (optional) reset (optional) clk latch qn [bitsC1:0] (optional)
sec asic 6-75 STD80/stdm80 latch pin description truth table pin capacitance pin name i/o description d [bitsC1:0] i data input en [bitsC1:0] enable input (optional when tri = 1) ti [bitsC1:0] test input (optional when scan = 1) te test enable input (optional when scan = 1) setn set input (optional when set = 1) reset reset input (optional when rst = 1) clk clock input q [bitsC1:0] o normal data output qn [bitsC1:0] inverted data output (optional when qn = 1) qt [bitsC1:0] tri-stated data output (optional when tri = 1) inputs outputs d clk en setn reset ti te q (n+1) qn (n+1) qt (n+1) x x 0 x x x x x x hi-z xx100xx 1 0 1 xx101xx 1 0 1 xx111xx 0 1 0 d0110x0q (n)qn (n)qt (n) d1110x0d~dd x0110d1q (n)qn (n)qt (n) x1110d1d~dd pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 0, rst = 0, set = 0, scan = 0, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.032 0.031 (parameters : qn = 1, q = 1, tri = 0, rst =0, set = 0, scan = 0, drv = 1) clk 8 0.256 0.256 16 0.512 0.512 24 0.768 0.768 32 1.024 1.024 d 8/16/24/32 0.032 0.031 pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 0, tri = 1, rst =0, set = 0, scan = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.032 0.031 en 8/16/24/32 0.023 0.022 qt 8/16/24/32 0.029 0.029
STD80/stdm80 6-76 sec asic latch pin capacitance (cont.) pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst =0, set = 0, scan = 0, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.032 0.031 en 8/16/24/32 0.023 0.022 qt 8/16/24/32 0.029 0.029 (parameters : qn = 0, q = 1, tri = 0, rst = 1, set = 0, scan = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.032 0.031 reset 8 0.248 0.240 16 0.496 0.480 24 0.744 0.720 32 0.992 0.960 (parameters : qn = 1, q = 1, tri = 0, rst = 1, set = 0, scan = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.032 0.031 reset 8 0.248 0.240 16 0.496 0.480 24 0.744 0.720 32 0.992 0.960 pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 0, tri = 1, rst = 1, set = 0, scan = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.032 0.031 en 8/16/24/32 0.023 0.022 reset 8 0.248 0.248 16 0.496 0.496 24 0.744 0.744 32 0.992 0.992 qt 8/16/24/32 0.028 0.029 (parameters : qn = 0, q = 1, tri =1, rst =1, set = 0, scan = 0, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.032 0.031 en 8/16/24/32 0.023 0.023 reset 8 0.256 0.240 16 0.512 0.480 24 0.768 0.720 32 1.024 0.960 qt 8/16/24/32 0.028 0.029 (parameters : qn = 0, q = 1, tri = 0, rst = 0, set = 0, scan = 1, drv = 1) clk 8 0.264 0.264 16 0.528 0.528 24 0.792 0.792 32 1.056 1.056 d 8/16/24/32 0.053 0.051 te 8 0.192 0.192 16 0.384 0.384 24 0.576 0.576 32 0.768 0.768 ti 8/16/24/32 0.053 0.052
sec asic 6-77 STD80/stdm80 latch pin capacitance (cont.) pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 1, drv = 1) clk 8 0.264 0.256 16 0.528 0.512 24 0.792 0.768 32 1.056 1.024 d 8/16/24/32 0.052 0.050 en 8/16/24/32 0.023 0.023 te 8 0.240 0.232 16 0.480 0.464 24 0.720 0.696 32 0.960 0.928 ti 8/16/24/32 0.051 0.050 qt 8/16/24/32 0.029 0.030 (parameters : qn = 0, q = 1, tri =1, rst =1, set = 1, scan = 0, drv = 1) clk 8 0.272 0.264 16 0.544 0.528 24 0.816 0.792 32 1.088 1.056 d 8/16/24/32 0.033 0.032 en 8/16/24/32 0.023 0.022 reset 8 0.256 0.256 16 0.512 0.512 24 0.768 0.768 32 1.024 1.024 setn 8 0.256 0.248 16 0.512 0.496 24 0.768 0.744 32 1.024 0.992 qt 8/16/24/32 0.027 0.029 pin name bit value (pf) dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan = 1, drv = 1) clk 8 0.272 0.264 16 0.544 0.528 24 0.816 0.792 32 1.088 1.056 d 8/16/24/32 0.046 0.045 en 8/16/24/32 0.023 0.022 reset 8 0.248 0.256 16 0.496 0.512 24 0.744 0.768 32 0.992 1.024 setn 8 0.248 0.248 16 0.496 0.496 24 0.744 0.744 32 0.992 0.992 te 8 0.232 0.232 16 0.464 0.464 24 0.696 0.696 32 0.928 0.928 ti 8/16/24/32 0.046 0.044 qt 8/16/24/32 0.027 0.029
STD80/stdm80 6-78 sec asic latch performance table ( t = 25 c, slope = 1.0ns, cap. = 0.4pf ) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 0, rst = 0, set = 0, scan =0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 64.6 delay (ns) min_pulse_width_high clk 0.250 0.350 hold_falling d clk 0.200 0.100 setup_falling d clk 0.500 0.600 t plh 1.127 1.694 t phl 0.932 1.237 (parameters : qn = 1, q = 1, tri = 0, rst = 0, set = 0, scan = 0, drv = 1) 8/16/24/3 area ( m m x m m) width 26.4 x bits height 69.4 delay (ns) min_pulse_width_high clk 0.250 0.350 hold_falling d clk 0.100 0.100 setup_falling d clk 0.500 0.700 t plh 1.197 1.743 t phl 0.972 1.279 (parameters : qn = 0, q = 0, tri = 1, rst = 0, set = 0, scan = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 75.7 delay (ns) min_pulse_width_high clk 0.250 0.350 hold_falling d clk 0.200 0.100 setup_falling d clk 0.500 0.600 t plh 1.723 2,759 t phl 1.083 1.605 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 82.0 delay (ns) min_pulse_width_high clk 0.250 0.350 hold_falling d clk 0.100 0.100 setup_falling d clk 0.500 0.700 t plh 1.743 2.791 t phl 1.113 1.617
sec asic 6-79 STD80/stdm80 latch performance table (cont.) ( t = 25 c, slope = 1.0ns, cap. = 0.4pf ) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 0, rst = 1, set = 0, scan =0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 67.3 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 hold_falling d clk 0.100 0.100 setup_falling d clk 0.500 0.600 t plh 1.197 1.777 t phl 0.998 1.384 (parameters : qn = 1, q = 1, tri = 0, rst = 1, set = 0, scan = 0, drv = 1) 8/16/24/3 area ( m m x m m) width 26.4 x bits height 71.5 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 hold_rising d clk e1.300 e1.600 setup_rising d clk 1.600 2.000 t plh 1.247 1.865 t phl 0.942 1.352 (parameters : qn = 0, q = 0, tri = 1, rst = 1, set = 0, scan = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits delay (ns) height 77.8 min_pulse_width_high clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 hold_rising d clk e1.500 e1.900 setup_rising d clk 1.600 2.000 t plh 1.793 2.861 t phl 1.093 1.639 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 0, scan = 0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 82.0 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 hold_rising d clk e1.500 e1.900 setup_rising d clk 1.700 2.000 t plh 1.823 2.918 t phl 1.153 1.736
STD80/stdm80 6-80 sec asic latch performance table (cont.) ( t = 25 c, slope = 1.0ns, cap. = 0.4pf ) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan =0, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 82.2 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.250 0.350 hold_rising d clk e1.600 e1.900 setup_rising d clk 1.700 2.100 t plh 1.803 2.867 t phl 1.361 1.851 (parameters : qn = 0, q = 1, tri = 0, rst = 0, set = 0, scan = 1, drv = 1) 8/16/24/3 area ( m m x m m) width 26.4 x bits height 71.0 delay (ns) min_pulse_width_high clk 0.250 0.350 hold_rising d clk e1.500 e2.000 hold_rising ti clk e1.500 e2.000 setup_rising d clk 1.600 2.100 setup_rising ti clk 1.600 2.000 t plh 1.237 1.880 t phl 1.146 1.732 (parameters : qn = 0, q = 1, tri = 1, rst = 0, set = 0, scan = 1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 88.3 delay (ns) min_pulse_width_high clk 0.250 0.350 hold_rising d clk e1.600 e2.000 hold_rising ti clk e1.500 e2.000 setup_rising d clk 1.700 2.100 setup_rising ti clk 1.700 2.100 t plh 1.873 3.051 t phl 1.361 1.873
sec asic 6-81 STD80/stdm80 latch performance table (cont.) ( t = 25 c, slope = 1.0ns, cap. = 0.4pf ) bits parameters dp80 dpm80 (parameters : qn = 0, q = 1, tri = 1, rst = 1, set = 1, scan =1, drv = 1) 8/16/24/32 area ( m m x m m) width 26.4 x bits height 93.8 delay (ns) min_pulse_width_high clk 0.250 0.350 min_pulse_width_high reset 0.250 0.350 min_pulse_width_low setn 0.250 0.350 hold_rising d clk e1.600 e2.000 hold_rising ti clk e1.600 e2.000 setup_rising d clk 1.700 2.200 setup_rising ti clk 1.700 2.200 t plh 1.907 3.112 t phl 1.391 1.931
STD80/stdm80 6-82 sec asic multiplexer features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for 2:1 to 8:1 multiplexing inputs with a variable number of bits ? inverting and non-inverting options ? configurable select inputs according to decoding and non-decoding options ? three drive strength options for output general description the multiplexer is optimized for multiple-targeted technologies. the generator n has the capability to build 2:1, 3:1, 4:1 and 8:1 multiplexer configurations from 4 to 128 bits range, with inverting and non-inverting, decoding and non-decoding options and three different drive strength capability. design description the multiplexer has schematic and layout generators that can build a variety of multiplexers. you have options to select among two types of output buffering (inverting and non-inverting), two types of select inputs (decoding and non-decoding), three different sizes of output buffers, variable number of bits (4 to 128), and inputs ranging from 2 to 8. symbol (in case of 3:1 mux) (case 1: with decoding option) (case 2: without decoding option) ii1 [bitsC1:0] o [bitsC1:0] ii0 [bitsC1:0] s0 ii2 [bitsC1:0] s1 0 1 ii1 [bitsC1:0] o [bitsC1:0] ii0 [bitsC1:0] ii2 [bitsC1:0] s [2:0] 0 1
sec asic 6-83 STD80/stdm80 multiplexer pin description (case 1) (case 2) round-up truth table (case 1) (case 2) parameter description pin name i/o description ii0/ii1/ii2 [bitsC1:0] i data input s0, s1 select lines o o data output C the multiplexer generator can produce an inverted or non-inverted output. pin name i/o description ii0/ii1/ii2 [bitsC1:0] i data input s [ log 2 ins e1:0] select lines o o data output e the multiplexer generator can produce an inverted or non-inverted output. non-inverted output inputs output ii0 ii1 ii2 s0 s1 o 10000 1 01001 1 0011x 1 non-inverted output inputs output ii0 ii1 ii2 s[0] s[1] s[2] o 100 1 0 0 1 010 0 1 0 1 001 0 0 1 1 parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 ins number of inputs 2/3/4/8 type output buffering: inverting or non-inverting 0/1 sel select controlling: decoding of non-decoding 0/1 drv drive strengths 1/2/4 inverted output inputs output ii0 ii1 ii2 s0 s1 o 10000 0 01001 0 0011x 0 inverted output inputs output ii0 ii1 ii2 s[0] s[1] s[2] o 100 1 0 0 0 010 0 1 0 0 001 0 0 1 0
STD80/stdm80 6-84 sec asic multiplexer pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) 3-1 mux with decoding option pin name bit value (pf) dp80 dpm80 ii2 8/16/24/32 0.052 0.050 ii1 8/16/24/32 0.053 0.050 ii0 8/16/24/32 0.052 0.050 s1 8/16/24/32 0.030 0.029 s0 8/16/24/32 0.030 0.029 bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl 3-1 mux with decoding option 8 26.4 x bits 71.5 1.564 1.276 2.292 1.765 16 1.704 1.402 2.572 2.036 24 1.843 1.528 2.842 2.316 32 1.980 1.653 3.122 2.596 3-1 mux without decoding option 8/16/24/32 26.4 x bits 65.2 0.897 0.588 1.431 0.911 3-1 mux without decoding option pin name bit value (pf) dp80 dpm80 ii2 8/16/24/32 0.052 0.050 ii1 8/16/24/32 0.053 0.050 ii0 8/16/24/32 0.052 0.050 s 8 0.184 0.192 16 0.368 0.384 24 0.552 0.576 32 0.736 0.768
sec asic 6-85 STD80/stdm80 nand/and features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for 2, 3 and 4 inputs ? three drive strength options for input general description the high performance datapath nand/and design can be optimized for multiple-targeted technologies. this generator can build nand/and gates ranging from 4-bits to 128-bits for 2, 3 and 4 input configurations, supporting three different drive strengths. design description the nand/and design has schematic and layout generators that can build a variety of nand and and gates. you have an option to select either nand or and by setting the "type" parameter to 0 or 1 respectively. the design supports three different drive strengths (1x, 2x and 4x) and is also configured to build 2, 3 and 4-input gates. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 ins number of inputs 2/3/4 type 0: nand; 1: and 0/1 drv drive strength 1/2/4 nand2 and2 ii1 ii0 o ii1 ii0 o
STD80/stdm80 6-86 sec asic nand/and pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) pin name i/o description ii0 [bitsC1:0] i input pin C 2, 3, 4 input nand/and ii1 [bitsC1:0] input pin C 2, 3, 4 input nand/and ii2 [bitsC1:0] input pin C 3, 4 input nand/and ii3 [bitsC1:0] input pin C 4 input nand/and o o output pin nand2 inputs output ii0 ii1 o 001 011 101 110 pin name value (pf) nand4 and4 dp80 dpm80 dp80 dpm80 ii3 0.034 0.033 0.031 0.031 ii2 0.034 0.033 0.031 0.030 ii1 0.033 0.032 0.031 0.030 ii0 0.031 0.030 0.031 0.030 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl nand4 8/16/24/32 26.4 x bits 59.6 0.963 1.111 1.381 1.773 and4 8/16/24/32 26.4 x bits 59.0 1.053 0.758 1.503 1.048 and2 inputs output ii0 ii1 o 000 010 100 111
sec asic 6-87 STD80/stdm80 nor/or features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for 2, 3 and 4 inputs ? three drive strength options for output general description the high performance datapath nor/or design can be optimized for multiple-targeted technologies. this generator can build nor/or gates ranging from 4-bits to 128-bits for 2, 3 and 4 input configurations, supporting three different drive strengths. design description the nor/or design has schematic and layout generators that can build a variety of nor and or gates. you have an option to select either nor or or by setting the "type" parameter to 0 or 1 respectively. the design supports three different drive strengths (1x, 2x and 4x) and is also configured to build 2, 3 and 4-input gates. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 ins number of inputs 2/3/4 type 0: nor; 1: or 0/1 drv drive strength 1/2/4 nor2 or2 ii1 ii0 o ii1 ii0 o
STD80/stdm80 6-88 sec asic nor/or pin description truth table pin capacitance performance table (t = 25c, slope = 1.0ns, cap. = 0.4pf) pin name i/o description ii0 [bitsC1:0] i input pin C 2-, 3-, 4-input nor/or ii1 [bitsC1:0] input pin C 2-, 3-, 4-input nor/or ii2 [bitsC1:0] input pin C 3-, 4-input nor/or ii3 [bitsC1:0] input pin C 4-input nor/or o o output pin nor2 inputs output ii0 ii1 o 001 010 100 110 pin name value (pf) nor4 or4 dp80 dpm80 dp80 dpm80 ii3 0.035 0.034 0.027 0.027 ii2 0.036 0.035 0.028 0.028 ii1 0.037 0.036 0.030 0.029 ii0 0.037 0.036 0.029 0.028 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl nor4 8/16/24/32 26.4 x bits 58.9 1.909 0.561 3.048 0.816 or4 8/16/24/32 26.4 x bits 58.9 1.023 0.860 1.466 1.470 or2 inputs output ii0 ii1 o 000 011 101 111
sec asic 6-89 STD80/stdm80 or-and features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for types 21 and 22 ? two drive strength options for output general description the high performance datapath or-and design can be optimized for multiple-targeted technologies. this generator can build or-and gates ranging from 4-bits to 128-bits for two different configurations (21 and 22) and two different drive strengths (1x and 2x). design description the or-and design has schematic and layout generators that can build a variety of or-and gates. you have an option to build the different kinds of oa structure configurations by setting the "type" parameter to 21 or 22 depending on your application. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type con?guration type 21/22 drv drive strength 1/2 oa21 oa22 ii00 ii01 o ii10 o ii00 ii01 ii11 ii10
STD80/stdm80 6-90 sec asic or-and pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) oa22 pin name i/o description ii00 [bitsC1:0] i data input ii01 [bitsC1:0] data input ii10 [bitsC1:0] data input ii11 [bitsC1:0] data input o o data output oa21 inputs output ii00 ii01 ii10 o 1x11 x111 xx00 00x0 oa21 pin name value (pf) dp80 dpm80 ii10 0.033 0.032 ii01 0.031 0.031 ii00 0.032 0.031 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl oa21 8/16/24/32 26.4 x bits 56.8 0.913 0.732 1.337 1.079 oa22 8/16/24/32 26.4 x bits 58.9 0.928 0.881 1.317 1.487 oa22 inputs output ii00 ii01 ii10 ii11 0 1x1x1 x11x1 1xx11 x1x11 00xx0 xx000 oa22 pin name value (pf) dp80 dpm80 ii11 0.031 0.031 ii10 0.034 0.033 ii01 0.031 0.030 ii00 0.032 0.031
sec asic 6-91 STD80/stdm80 or-and-invert features ? functional model, test vector, schematic and layout generators ? timing model with auto-characterization ? variable word width of 4 to 128 bits ? configurable for types 21 and 22 ? two drive strength options for output general description the high performance datapath or-and-invert design can be optimized for multiple-targeted technologies. this generator can build or-and-invert gates ranging from 4-bits to 128-bits for two different configurations (21 and 22) and two different drive strengths (1x and 2x). design description the or-and-invert design has schematic and layout generators that can build a variety of or-and-invert gates. you have an option to build the different kinds of oai structure configurations by setting the "type" parameter to 21 or 22 depending on your application. symbol parameter description parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type con?guration type 21/22 drv drive strength 1/2 oai21 oai22 ii00 ii01 o ii10 o ii00 ii01 ii11 ii10
STD80/stdm80 6-92 sec asic or-and-invert pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) oai22 pin name i/o description ii00 [bitsC1:0] i data input ii01 [bitsC1:0] data input ii10 [bitsC1:0] data input ii11 [bitsC1:0] data input o o data output oai21 inputs output ii00 ii01 ii10 o 1x10 x111 xx01 00x1 oai21 pin name value (pf) dp80 dpm80 ii10 0.024 0.024 ii01 0.025 0.025 ii00 0.025 0.024 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl oai21 8/16/24/32 26.4 x bits 54.5 1.163 0.778 1.671 1.109 oai22 8/16/24/32 26.4 x bits 58.4 1.283 0.758 1.825 1.103 oai22 inputs output ii00 ii01 ii10 ii11 o 1x1x0 x11x0 1xx10 x1x10 00xx1 xx001 oai22 pin name value (pf) dp80 dpm80 ii11 0.023 0.023 ii10 0.022 0.022 ii01 0.023 0.023 ii00 0.024 0.024
sec asic 6-93 STD80/stdm80 tri-state buffer/inverter features ? technology-independent generator ? variable word width of 4 to 128 bits ? configurable for tri-state buffer/inverter design ? four drive strength options for output general description the high performance tri-state buffer/inverter design is optimized for multiple-targeted technologies. the generator design has the capability to build tri-state buffers/inverters ranging from 4-bits to 128-bits for various drive strength configurations. design description the tri-state buffer/inverter design has schematic and layout generators that can build a variety of tri-state buffers and inverters. you have an option to select either tri-state buffer or a tri-state inverter by setting the "type" parameter to 1 or 0 respectively. the design supports 4 different drive strength options (1x, 2x, 4x, 8x) for the tri-state buffer and 2 drive strength options (1x and 2x) for the tri-state inverter. symbol parameter description note : for type = 0, only 1x and 2x supported. parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 type 0: tri-state inverter; 1: tri-state buffer 0/1 drv drive strength 1/2/4/8 tri-state buffer tri-state inverter io en i o en
STD80/stdm80 6-94 sec asic tri-state buffer/inverter pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) pin name description i [bitsC1:0] input en [bitsC1:0] high enable o [bitsC1:0] output tri-state buffer inputs output ieno x 0 hi-z 010 111 pin name value (pf) tri-state buffer tri-state inverter dp80 dpm80 dp80 dpm80 en 0.049 0.047 0.034 0.033 i 0.050 0.049 0.049 0.048 o 0.026 0.027 0.059 0.058 bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl tri-state buffer 8/16/24/32 26.4 x bits 63.7 0.831 0.773 1.238 1.027 tri-state inverter 8/16/24/32 26.4 x bits 61.0 0.884 0.525 1.286 0.773 tri-state inverter inputs output ieno x 0 hi-z 011 110
sec asic 6-95 STD80/stdm80 xnor/xor features ? technology-independent generator ? variable word width of 4 to 128 bits ? configurable for 2 and 3 inputs ? configurable for xnor/xor design ? three drive strength options for output general description the high performance datapath xnor/xor design can be optimized for multiple targeted technologies. the generator can build xnor/xor gates ranging from 4-bits to 128-bits for 2 and 3 input configurations, supporting three different drive strengths. design description the xnor/xor design has schematic and layout generators that can build a variety of xnor and xor gates. you have an option to select either xnor or xor by setting the type parameter to 0 or 1 respectively. the design supports three different drive strengths (1x, 2x and 4x) and is also configured to build 2- and 3-input gates. symbol parameter description note : when ins = 3, only drv = 1 and 2 are supported. parameter name description range instance_name name of the instance any string bits number of bits in the input data bus 4 to 128 ins number of inputs 2/3 type 0: xnor; 1: xor 0/1 drv drive strength 1/2/4 xnor2 xor2 o ii0 ii1 o ii0 ii1
STD80/stdm80 6-96 sec asic xnor/xor pin description truth table pin capacitance performance table (t = 25 c, slope = 1.0ns, cap. = 0.4pf) pin name i/o description ii0 [bitsC1:0] i input pin C 2-, 3-input xnor/xor ii1 [bitsC1:0] input pin C 2-, 3-input xnor/xor ii2 [bitsC1:0] input pin C 3-input xnor/xor o o output pin xnor2 inputs output ii0 ii1 o 001 010 100 111 pin name value (pf) xnor3 xor3 dp80 dpm80 dp80 dpm80 ii2 0.027 0.027 0.027 0.027 ii1 0.030 0.030 0.030 0.030 ii0 0.035 0.034 0.035 0.034 cell name bit area ( m m x m m) delay (ns) width height dp80 dpm80 t plh t phl t plh t phl xnor3 8/16/24/32 26.4 x bits 65.2 1.315 0.965 1.892 1.468 xor3 8/16/24/32 26.4 x bits 65.2 1.008 0.885 1.497 1.415 xor2 inputs output ii0 ii1 o 000 011 101 110
jtag boundary scans 7
contents overview .............................................................................................................................. 7-1 boundary scan architecture................................................................................................. 7-2 boundary scan register macrocells .................................................................................... 7-4 jtbi1 ........................................................................................................................... 7-5 jtck............................................................................................................................ 7-12 jtin1 ........................................................................................................................... 7-14 jtint1 ......................................................................................................................... 7-18 jtout1 ....................................................................................................................... 7-24 jtag tap controller macrofunction..................................................................................... 7-28 instruction register/decoder macrofunction ........................................................................ 7-31 implementation of ieee p1149.1/jtag ............................................................................... 7-32 system clock considerations .............................................................................................. 7-32
jtag boundary scans overview sec asic 7-1 STD80/stdm80 overview a board test is typically achieved by using in-circuit test techniques. however, in-circuit test techniques demonstrate signi?cant limitations for surface mount technology (smt) and fine pitch technology (fpt) boards. the pin and pad spacings getting tighter make it dif?cult to test boards with traditional methods economically and reliably. a boundary scan design reduces the cost of a function test. a boundary scan design circuitry allows boards to be tested using the equivalent in-circuit test technique without bed-of-nails ?xture. in recognition of the increasing acceptance of the boundary scan test, ieee and jtag (joint test action group) developed ieee standard test access port and boundary scan architecture (ieee std 1149.1). a boundary scan technique requires to place a boundary scan cell adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principles. each boundary scan cell for a given component is able to capture data from an input pin or from its internal logic, and to drive its internal logic or an output pin. boundary scan cells for the pins of a given component are interconnected so as to form a shift-register chain around the border of the design, known as a boundary scan register. boundary scan registers for individual components can be connected in series to form a single path through the complete design as shown in the ?gure 9-1. alternatively, a board design can contain several independent boundary scan paths that allow individual components to be tested as well as the interconnections between components. to test component interconnections, test data are ?rst shifted into all boundary scan register cells associated with component output test pins. test data are then loaded into parallel inputs of boundary scan cells associated with input pins through the component interconnections, and data captured in these cells are shifted out from the boundary cells for evaluation. for an individual component test, a boundary scan register is used to isolate on-chip system logic from stimuli received from surrounding components. an actual test can be performed through the boundary scan path or the built-in self-test hardware. figure 7-1. board design for boundary scan logic logic logic logic data i n serial data out serial test interconnect system interconnect serial
boundary scan architecture jtag boundary scans STD80/stdm80 7-2 sec asic boundary scan architecture a boundary scan architecture contains tap (test access port), tap controller, instruction register and a group of test data registers. the instruction and test data registers are separate shift-register-based paths connected in parallel with a common serial data input and a common serial data output which are connected to tap, tdi and tdo signals. tap controller selects the alternative instruction and test data register paths between tdi and tdo. the schematic view of the top level design of the test logic architecture is shown in the ?gure 9-2. figure 7-2. jtag test access port (tap) block diagram boundary scan functional block descriptions tap (test access port) tap is a general-purpose port that can provide with an access to many test support functions built into a component, including the test logic. it includes three inputs (tck; test clock signal, tms; test mode signal and tdi; test data input) and one output (tdo; test data output) required by the test logic. an optional fourth input (trstn; test reset) is provided for the asynchronous initialization of the test logic. the values applied at tms and tdi pins are sampled on the rising edge of tck, and the value placed on tdo pin changes on the falling edge of tck. tap controller tap controller receives tck, interprets the signals on tms, and generates clock and control signals for both instruction and test data registers and for other parts of the test circuitries as required. instruction register/instruction decoder test instructions are shifted into and held by the instruction register. test instructions include a selection of tests to be performed or the test data register to be accessed. a basic 3-bit instruction register and its instruction decoder are provided as macrofunctions in the library. multiplexer scannable register device identity register bypass register instruction register ta p controller system logic boundary scan path tdi tms tck tdo test access port (tap) mux
jtag boundary scans boundary scan architecture sec asic 7-3 STD80/stdm80 test data registers data registers include a bypass register, a boundary scan register, a device identi?cation register and other design speci?c registers. only the bypass- and boundary scan registers are mandatory; the rest are optional. bypass register: the bypass register provides a single-bit serial connection through the circuit when none of the other test data registers is selected. it can be used to allow test data to ?ow through a given device to the other components in a product without affecting a normal operation. boundary scan register: the boundary scan register detects typical production defects in board interconnects, such as opens, shorts, etc. it also allows an access to component inputs and outputs when you test their logic or sample ?ow-through signals. special boundary scan register macrocells are provided for this purpose. these special registers is discussed in the next section of next pages. design-speci?c test data register: these optional registers may be provided to allow an access to design-speci?c test support features in the integrated circuit, such as self-test, scan test. device identi?cation register: this is an optional test data register that allows the manufacturer part number and variant of a components to be identi?ed. the 32-bit identi?cation register is partitioned into four ?elds: device version identi?er 1st ?eld the ?rst four bits beginning from msb device part number 2nd ?eld 16 bits manufacturers jedec number 3rd ?eld 11 bits lsb 4th ?eld 1 bit tied in high the asic designer is free to ?ll the version and part number in any manner as long as the total twenty bits are used. secs jedec code: 78 decimal = 1001110 continuation ?eld (4 bits) = 0000 contents of device identi?cation register: xxxx xxxxxxxxxxxxxxxx 0000 1001110 1 users can de?ne these two ?elds.
boundary scan register macrocells jtag boundary scans STD80/stdm80 7-4 sec asic boundary scan register macrocells the boundary scan register allows testing of circuitry external to the integrated circuit and provides for de?ned conditions to be established at the periphery of the on-chip system logic while it is tested itself. it also permits signals ?owing through system pins to be sampled and examined without interfering with the operation of the on-chip system logic. the boundary scan register has four capabilities: capture: loads data into the boundary scan register in parallel on the rising edge of tck. it does not affect the output until update is executed. shift: shifts data from one boundary scan register to the next register towards the serial data output pin on the rising edge of tck. update: loads data in the boundary scan register into the parallel data output pin on the falling edge of tck when extest or intest instruction is selected. set: sets the parallel output pin. sec supports ?ve types of boundary scan registers. four of them, jtck, jtbi1, jtin1 and jtout1 are to be implemented around the periphery of the die next to i/o cells. for this reason, two i/o pads at each corner, that is, the total of eight i/o pads for the entire chip are not scannable. an implementation is automatically performed during a placement to achieve the most optimum placement with a minimum performance penalty. the ?fth cell, jtint1, is to be placed in the core area of the die for tri-state i/o control. applications for each type of boundary scan register cell are summarized as follows. cell list cell name function description page jtbi1 bi-directional i/o boundary scan cell 7-5 jtck special input (such as clock input) boundary scan cell 7-12 jtin1 input boundary scan cell 7-14 jtint1 tri-state i/o control boundary scan cell 7-18 jtout1 output boundary scan cell 7-24
sec asic 7-5 STD80/stdm80 jtbi1 bi-directional i/o scan cell with capture, shift and update logic symbol pin description pin name i/o description dinp0n i parallel data input active low for the input part of the bi-directional pin tdi0 i serial test data input for input part of the bi-directional pin mode0 i mode select for input partlow for data input and high for internal register data value dinp1 i parallel data input active low for the output part of the bi-directional pin tdi1 i serial test data input for input part of the bi-directional pin mode1 i mode select for output partlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update tck i test clock input enb i active high test clock enable dout0 o parallel data output for input part of the bi-directional pin tdo0 o serial test data output for input part of the bi-directional pin dout1 o parallel data output for output part of the bi-directional pin tdo1 o serial test data output for output part of the bi-directional pin dinp0n tdi0 mode0 tdi1 mode1 tdo0 shift update enb dout1 dinp1 tck dout0 tdo1 cell data input loading (sl) STD80 stdm80 dinp0n 0 4 tdi0 2 1 mode0 1 1 dinp1 2 3 tdi1 2 1 mode1 1 1 shift 2 2 update 3 2 tck 1 1 enb 0 0 gate count 22
STD80/stdm80 7-6 sec asic jtbi1 bi-directional i/o scan cell with capture, shift and update truth table notes: 1. outputs are de?ned in separate truth tables. in addition, the internal states known as latchq and latchqn are de?ned as the output of the latch in the logic diagram. 2. jtbi1 has a similar truth table to jtin1 and jtout1 macrocells without setn input. it has similar delays to jtin1 and jtout1. dinp0n tdi0 mode0 shift update tck enb output dout0 0x0xxxx1 1x0xxxx0 x x 1 x x x x latchqn tdo0 x x x x x 0 tdo0o 0x00x 11 1x00x 10 x x 1 0 x 1 latchqn x0x1x 10 x1x1x 11 x x x x x 0 x tdo0o x x x x x 1 x tdo0o x x x x x x tdo0o latchqn x x x x 0 x x tdo0 x x x x 1 x x latchqno dinp1 tdi1 mode1 shift update tck enb output dout1 0x0xxxx0 1x0xxxx1 xx1xxxx latchq tdo1 xxxxx 0 tdo1o 0xx0x 10 1xx0x 11 x0x1x 10 x1x1x 11 xxxxx0x tdo1o xxxxx1x tdo1o xxxxx x tdo1o latchq xxxx0xx tdo1 xxxx1xx latchqo
sec asic 7-7 STD80/stdm80 jtbi1 bi-directional i/o scan cell with capture, shift and update timing requirements (typical process, 25 c, 5v, 3.3v) parameter symbol value (ns) STD80 stdm80 input setup time (tdi0 to tck) t su 0.46 0.60 input hold time (tdi0 to tck) t hd 0.41 0.41 input setup time (tdi0 to enb) t su 0.46 0.57 input hold time (tdi0 to enb) t hd 0.38 0.41 input setup time (tdi1 to tck) t su 0.46 0.60 input hold time (tdi1 to tck) t hd 0.41 0.41 input setup time (tdi1 to enb) t su 0.46 0.57 input hold time (tdi1 to enb) t hd 0.38 0.41 input setup time (dinp0n to tck) t su 0.74 1.01 input hold time (dinp0n to tck) t hd 0.33 0.33 input setup time (dinp0n to enb) t su 0.74 1.01 input hold time (dinp0n to enb) t hd 0.33 0.33 input setup time (dinp1 to tck) t su 0.46 0.60 input hold time (dinp1 to tck) t hd 0.41 0.41 input setup time (dinp1 to enb) t su 0.49 0.60 input hold time (dinp1 to enb) t hd 0.38 0.41 input setup time (shift to tck) t su 0.60 0.76 input hold time (shift to tck) t hd 0.52 0.33 input setup time (shift to enb) t su 0.60 0.74 input hold time (shift to enb) t hd 0.74 0.33 input setup time (mode0 to tck) t su 0.82 1.15 input hold time (mode0 to tck) t hd 0.33 0.33 input setup time (mode0 to enb) t su 0.82 1.12 input hold time (mode0 to enb) t hd 0.33 0.33
STD80/stdm80 7-8 sec asic jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 jtbi1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo0 t plh 0.94 0.88 + 0.030*sl 0.90 + 0.024*sl 0.90 + 0.024*sl t phl 0.81 0.73 + 0.043*sl 0.74 + 0.038*sl 0.74 + 0.037*sl t r 0.22 0.14 + 0.041*sl 0.12 + 0.048*sl 0.09 + 0.052*sl t f 0.24 0.11 + 0.064*sl 0.11 + 0.067*sl 0.08 + 0.069*sl enb to tdo0 t plh 0.93 0.93 + 0.003*sl 0.87 + 0.029*sl 0.92 + 0.024*sl t phl 0.80 0.73 + 0.032*sl 0.71 + 0.042*sl 0.76 + 0.037*sl t r 0.21 0.14 + 0.038*sl 0.11 + 0.049*sl 0.08 + 0.052*sl t f 0.24 0.12 + 0.063*sl 0.11 + 0.067*sl 0.08 + 0.069*sl tck to tdo1 t plh 0.92 0.86 + 0.028*sl 0.87 + 0.024*sl 0.87 + 0.024*sl t phl 0.78 0.70 + 0.041*sl 0.71 + 0.037*sl 0.71 + 0.037*sl t r 0.20 0.13 + 0.039*sl 0.11 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.09 + 0.068*sl 0.09 + 0.069*sl enb to tdo1 t plh 0.90 0.90 + -0.001*sl 0.84 + 0.029*sl 0.89 + 0.024*sl t phl 0.79 0.65 + 0.070*sl 0.72 + 0.038*sl 0.73 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.066*sl 0.10 + 0.068*sl 0.08 + 0.069*sl dinp0n to dout0 t plh 0.18 0.14 + 0.021*sl 0.14 + 0.018*sl 0.20 + 0.012*sl t phl 0.23 0.15 + 0.043*sl 0.20 + 0.018*sl 0.20 + 0.018*sl t r 0.23 0.19 + 0.018*sl 0.19 + 0.019*sl 0.12 + 0.026*sl t f 0.27 0.12 + 0.074*sl 0.23 + 0.026*sl 0.15 + 0.033*sl mode0 to dout0 t plh 0.34 0.27 + 0.034*sl 0.32 + 0.011*sl 0.31 + 0.012*sl t phl 0.47 0.40 + 0.034*sl 0.42 + 0.025*sl 0.48 + 0.018*sl t r 0.16 0.13 + 0.014*sl 0.11 + 0.024*sl 0.09 + 0.026*sl t f 0.29 0.22 + 0.038*sl 0.23 + 0.033*sl 0.23 + 0.033*sl update to dout0 t plh 0.62 0.58 + 0.021*sl 0.59 + 0.016*sl 0.62 + 0.012*sl t phl 0.87 0.80 + 0.034*sl 0.82 + 0.028*sl 0.92 + 0.018*sl t r 0.20 0.15 + 0.025*sl 0.15 + 0.024*sl 0.14 + 0.026*sl t f 0.35 0.27 + 0.041*sl 0.29 + 0.029*sl 0.25 + 0.033*sl tck to dout0 t plh 1.42 1.38 + 0.019*sl 1.39 + 0.015*sl 1.42 + 0.012*sl t phl 1.38 1.31 + 0.033*sl 1.33 + 0.024*sl 1.39 + 0.018*sl t r 0.20 0.16 + 0.024*sl 0.15 + 0.025*sl 0.15 + 0.025*sl t f 0.33 0.25 + 0.037*sl 0.27 + 0.031*sl 0.25 + 0.033*sl enb to dout0 t plh 1.44 1.40 + 0.018*sl 1.41 + 0.015*sl 1.44 + 0.012*sl t phl 1.39 1.33 + 0.033*sl 1.34 + 0.024*sl 1.40 + 0.018*sl t r 0.20 0.16 + 0.019*sl 0.15 + 0.024*sl 0.14 + 0.026*sl t f 0.33 0.25 + 0.036*sl 0.27 + 0.031*sl 0.25 + 0.033*sl dinp1 to dout1 t plh 0.31 0.25 + 0.030*sl 0.26 + 0.025*sl 0.28 + 0.024*sl t phl 0.40 0.31 + 0.044*sl 0.32 + 0.041*sl 0.36 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.049*sl 0.09 + 0.052*sl t f 0.27 0.14 + 0.068*sl 0.14 + 0.066*sl 0.11 + 0.069*sl
sec asic 7-9 STD80/stdm80 jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 jtbi1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* mode1 to dout1 t plh 0.38 0.32 + 0.031*sl 0.33 + 0.025*sl 0.34 + 0.024*sl t phl 0.37 0.28 + 0.044*sl 0.29 + 0.041*sl 0.34 + 0.037*sl t r 0.29 0.05 + 0.120*sl 0.23 + 0.038*sl 0.10 + 0.052*sl t f 0.26 0.13 + 0.066*sl 0.13 + 0.067*sl 0.11 + 0.069*sl update to dout1 t plh 0.78 0.68 + 0.048*sl 0.73 + 0.025*sl 0.75 + 0.024*sl t phl 0.71 0.62 + 0.045*sl 0.63 + 0.042*sl 0.68 + 0.037*sl t r 0.22 0.14 + 0.043*sl 0.12 + 0.050*sl 0.10 + 0.052*sl t f 0.27 0.15 + 0.064*sl 0.14 + 0.065*sl 0.11 + 0.069*sl tck to dout1 t plh 1.57 1.51 + 0.029*sl 1.52 + 0.024*sl 1.52 + 0.024*sl t phl 1.38 1.29 + 0.044*sl 1.30 + 0.039*sl 1.32 + 0.037*sl t r 0.22 0.13 + 0.048*sl 0.12 + 0.050*sl 0.11 + 0.052*sl t f 0.27 0.14 + 0.064*sl 0.13 + 0.068*sl 0.12 + 0.069*sl enb to dout1 t plh 1.58 1.52 + 0.028*sl 1.53 + 0.025*sl 1.54 + 0.024*sl t phl 1.39 1.30 + 0.047*sl 1.32 + 0.039*sl 1.33 + 0.037*sl t r 0.22 0.13 + 0.044*sl 0.12 + 0.049*sl 0.10 + 0.052*sl t f 0.28 0.13 + 0.070*sl 0.14 + 0.066*sl 0.11 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 7-10 sec asic jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 jtbi1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo0 t plh 1.41 1.33 + 0.040*sl 1.34 + 0.035*sl 1.35 + 0.034*sl t phl 1.19 1.09 + 0.053*sl 1.11 + 0.046*sl 1.11 + 0.046*sl t r 0.30 0.18 + 0.058*sl 0.15 + 0.069*sl 0.14 + 0.070*sl t f 0.31 0.15 + 0.081*sl 0.16 + 0.079*sl 0.12 + 0.085*sl enb to tdo0 t plh 1.39 1.29 + 0.048*sl 1.33 + 0.035*sl 1.34 + 0.034*sl t phl 1.17 1.06 + 0.053*sl 1.08 + 0.046*sl 1.09 + 0.045*sl t r 0.29 0.17 + 0.063*sl 0.15 + 0.069*sl 0.14 + 0.071*sl t f 0.31 0.15 + 0.080*sl 0.15 + 0.080*sl 0.15 + 0.081*sl tck to tdo1 t plh 1.36 1.27 + 0.045*sl 1.31 + 0.035*sl 1.31 + 0.034*sl t phl 1.14 1.04 + 0.052*sl 1.06 + 0.045*sl 1.07 + 0.045*sl t r 0.29 0.17 + 0.061*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.079*sl 0.12 + 0.083*sl enb to tdo1 t plh 1.36 1.28 + 0.038*sl 1.29 + 0.034*sl 1.30 + 0.034*sl t phl 1.12 1.02 + 0.051*sl 1.04 + 0.045*sl 1.05 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.080*sl 0.12 + 0.083*sl dinp0n to dout0 t plh 0.26 0.22 + 0.020*sl 0.22 + 0.019*sl 0.23 + 0.017*sl t phl 0.31 0.21 + 0.049*sl 0.27 + 0.030*sl 0.31 + 0.025*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.035*sl 0.17 + 0.031*sl t f 0.26 0.11 + 0.075*sl 0.24 + 0.033*sl 0.19 + 0.039*sl mode0 to dout0 t plh 0.37 0.30 + 0.032*sl 0.33 + 0.022*sl 0.35 + 0.020*sl t phl 0.51 0.43 + 0.038*sl 0.46 + 0.029*sl 0.50 + 0.024*sl t r 0.24 0.17 + 0.034*sl 0.16 + 0.035*sl 0.17 + 0.034*sl t f 0.26 0.17 + 0.044*sl 0.18 + 0.041*sl 0.22 + 0.036*sl update to dout0 t plh 0.85 0.77 + 0.041*sl 0.83 + 0.023*sl 0.89 + 0.015*sl t phl 1.27 1.18 + 0.047*sl 1.21 + 0.036*sl 1.26 + 0.030*sl t r 0.25 0.18 + 0.036*sl 0.17 + 0.040*sl 0.23 + 0.032*sl t f 0.44 0.35 + 0.048*sl 0.36 + 0.043*sl 0.41 + 0.037*sl tck to dout0 t plh 2.13 2.08 + 0.026*sl 2.09 + 0.022*sl 2.11 + 0.019*sl t phl 2.06 1.97 + 0.045*sl 1.99 + 0.036*sl 2.04 + 0.030*sl t r 0.25 0.18 + 0.038*sl 0.18 + 0.036*sl 0.19 + 0.034*sl t f 0.44 0.34 + 0.048*sl 0.36 + 0.042*sl 0.37 + 0.040*sl enb to dout0 t plh 2.12 2.07 + 0.026*sl 2.08 + 0.022*sl 2.10 + 0.019*sl t phl 2.04 1.95 + 0.045*sl 1.98 + 0.036*sl 2.02 + 0.030*sl t r 0.25 0.18 + 0.037*sl 0.18 + 0.036*sl 0.15 + 0.040*sl t f 0.44 0.35 + 0.049*sl 0.36 + 0.044*sl 0.40 + 0.038*sl dinp1 to dout1 t plh 0.41 0.33 + 0.040*sl 0.35 + 0.035*sl 0.38 + 0.031*sl t phl 0.55 0.43 + 0.057*sl 0.46 + 0.049*sl 0.48 + 0.046*sl t r 0.29 0.16 + 0.067*sl 0.14 + 0.073*sl 0.14 + 0.072*sl t f 0.34 0.18 + 0.082*sl 0.19 + 0.080*sl 0.17 + 0.081*sl
sec asic 7-11 STD80/stdm80 jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 jtbi1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* mode1 to dout1 t plh 0.34 0.28 + 0.032*sl 0.25 + 0.041*sl 0.31 + 0.033*sl t phl 0.51 0.40 + 0.054*sl 0.40 + 0.055*sl 0.50 + 0.040*sl t r 0.29 0.15 + 0.071*sl 0.16 + 0.068*sl 0.14 + 0.071*sl t f 0.35 0.17 + 0.085*sl 0.19 + 0.081*sl 0.19 + 0.081*sl update to dout1 t plh 1.11 1.02 + 0.042*sl 1.04 + 0.035*sl 1.05 + 0.034*sl t phl 1.02 0.91 + 0.058*sl 0.91 + 0.055*sl 1.01 + 0.041*sl t r 0.30 0.16 + 0.069*sl 0.17 + 0.067*sl 0.14 + 0.070*sl t f 0.36 0.20 + 0.081*sl 0.18 + 0.084*sl 0.23 + 0.077*sl tck to dout1 t plh 2.33 2.25 + 0.041*sl 2.26 + 0.035*sl 2.28 + 0.033*sl t phl 2.07 1.95 + 0.062*sl 1.99 + 0.047*sl 2.00 + 0.046*sl t r 0.31 0.16 + 0.074*sl 0.17 + 0.071*sl 0.22 + 0.064*sl t f 0.37 0.20 + 0.085*sl 0.21 + 0.082*sl 0.26 + 0.076*sl enb to dout1 t plh 2.32 2.24 + 0.040*sl 2.25 + 0.035*sl 2.25 + 0.034*sl t phl 2.05 1.93 + 0.057*sl 1.96 + 0.050*sl 1.98 + 0.046*sl t r 0.30 0.17 + 0.065*sl 0.16 + 0.070*sl 0.16 + 0.070*sl t f 0.38 0.18 + 0.097*sl 0.24 + 0.078*sl 0.24 + 0.078*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 7-12 sec asic jtck special input scan cell with capture and shift logic symbol general description jtck is a special input boundary scan cell for clock pad. it has capture and shift capabilities only. jtck doesnt have update and set capabilities, but has clock enable capability. pin description truth table pin name i/o description dinp i parallel system data input tdi i serial test data input shift i active high shift control input tck i test clock input enb i active high test clock enable input tdo o serial test data output dinp tdi shift tck enb tdo x x x 0 tdoo 0x0 10 1x0 11 x01 10 x11 11 x x x 0 x tdoo x x x 1 x tdoo x x x x tdoo dinp tdi shift enb tck tdo cell data input loading (sl) STD80 stdm80 dinp 1 1 tdi 1 0 shift 1 1 tck 1 1 enb 1 0 gate count 7
sec asic 7-13 STD80/stdm80 jtck special input scan cell with capture and shift timing requirements (typical process, 25 c, 5v, 3.3v) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 jtck switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 jtck parameter symbol value (ns) STD80 stdm80 input setup time (tdi to tck) t su 0.74 1.07 input hold time (tdi to tck) t hd 0.74 0.33 input setup time (tdi to enb) t su 0.74 1.04 input hold time (tdi to enb) t hd 0.33 0.33 input setup time (dinp to tck) t su 0.66 0.96 input hold time (dinp to tck) t hd 0.33 0.33 input setup time (dinp to enb) t su 0.66 0.93 input hold time (dinp to enb) t hd 0.33 0.33 input setup time (shift to tck) t su 0.60 0.79 input hold time (shift to tck) t hd 0.33 0.33 input setup time (shift to enb) t su 0.63 0.79 input hold time (shift to enb) t hd 0.33 0.33 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.64 0.58 + 0.029*sl 0.59 + 0.024*sl 0.60 + 0.024*sl t phl 0.72 0.64 + 0.041*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.20 0.11 + 0.046*sl 0.10 + 0.049*sl 0.08 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.08 + 0.069*sl enb to tdo t plh 0.64 0.58 + 0.029*sl 0.59 + 0.024*sl 0.60 + 0.024*sl t phl 0.70 0.62 + 0.041*sl 0.62 + 0.038*sl 0.63 + 0.037*sl t r 0.20 0.11 + 0.047*sl 0.10 + 0.052*sl 0.10 + 0.052*sl t f 0.23 0.10 + 0.064*sl 0.10 + 0.067*sl 0.07 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.90 0.83 + 0.038*sl 0.81 + 0.043*sl 0.88 + 0.033*sl t phl 1.04 0.94 + 0.051*sl 0.96 + 0.045*sl 0.96 + 0.045*sl t r 0.28 0.15 + 0.067*sl 0.11 + 0.079*sl 0.18 + 0.069*sl t f 0.30 0.15 + 0.078*sl 0.15 + 0.078*sl 0.11 + 0.084*sl enb to tdo t plh 0.91 0.84 + 0.037*sl 0.84 + 0.035*sl 0.83 + 0.037*sl t phl 1.05 0.95 + 0.051*sl 0.97 + 0.045*sl 0.98 + 0.044*sl t r 0.28 0.15 + 0.065*sl 0.15 + 0.068*sl 0.12 + 0.072*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.082*sl 0.16 + 0.079*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 7-14 sec asic jtin1 input scan cell with capture, shift, update and set logic symbol pin description pin name i/o description dinpn i parallel data input active low tdi i serial test data input mode i mode select inputlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update setn i active low set input tck i test clock input enb i active high test clock enable input dout o parallel data output tdo o serial test data output dinpn tdi mode update setn tdo tck enb shift dout cell data input loading (sl) STD80 stdm80 dinpn 1 4 tdi 0 1 mode 1 1 shift 1 1 update 1 1 setn 0 0 tck 1 1 enb 0 0 gate count 13
sec asic 7-15 STD80/stdm80 jtin1 input scan cell with capture, shift, update and set truth table note : outputs are de?ned in separate truth tables. in addition, an internal state known as latchq is de?ned as the output of the latch in the logic diagram. timing requirements (typical process, 25 c, 5v, 3.3v) dinpn tdi mode shift update tck enb output dout 0x0xxxx1 1x0xxxx0 xx1xxxx latchq tdo xxxxx 0 tdoo 0x00x 11 1x00x 10 x x 1 0 x 1 latchq x0x1x 10 x1x1x 11 xxxxx0x tdoo xxxxx1x tdoo xxxxx x tdoo latchq xxxx0xx0 xxxx1 0xtdo xxxx1 1x latchqo parameter symbol value (ns) STD80 stdm80 input setup time (tdi to tck) t su 0.52 0.66 input hold time (tdi to tck) t hd 0.33 0.33 input setup time (tdi to enb) t su 0.52 0.66 input hold time (tdi to enb) t hd 0.33 0.33 input setup time (dinpn to tck) t su 0.82 1.12 input hold time (dinpn to tck) t hd 0.33 0.33 input setup time (dinpn to enb) t su 0.82 1.12 input hold time (dinpn to enb) t hd 0.33 0.33 input setup time (shift to tck) t su 0.60 0.79 input hold time (shift to tck) t hd 0.33 0.33 input setup time (shift to enb) t su 0.63 0.79 input hold time (shift to enb) t hd 0.33 0.33 input setup time (mode to tck) t su 0.87 1.20 input hold time (mode to tck) t hd 0.33 0.33 input setup time (mode to enb) t su 0.87 1.20 input hold time (mode to enb) t hd 0.33 0.33 input hold time (setn to update) t hd 0.33 recovery time (setn) t rc 0.33 0.49
STD80/stdm80 7-16 sec asic jtin1 input scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 jtin1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.64 0.59 + 0.023*sl 0.59 + 0.025*sl 0.60 + 0.024*sl t phl 0.72 0.64 + 0.041*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.20 0.11 + 0.048*sl 0.11 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.067*sl 0.07 + 0.069*sl enb to tdo t plh 0.66 0.60 + 0.029*sl 0.61 + 0.024*sl 0.62 + 0.024*sl t phl 0.72 0.63 + 0.042*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.20 0.11 + 0.046*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.068*sl 0.10 + 0.067*sl 0.07 + 0.069*sl dinpn to dout t plh 0.18 0.14 + 0.021*sl 0.14 + 0.018*sl 0.33 + -0.001*sl t phl 0.25 0.20 + 0.023*sl 0.20 + 0.021*sl 0.43 + -0.002*sl t r 0.23 0.19 + 0.019*sl 0.19 + 0.021*sl 0.41 + -0.002*sl t f 0.27 0.20 + 0.034*sl 0.22 + 0.028*sl 0.51 + -0.002*sl mode to dout t plh 0.33 0.29 + 0.018*sl 0.30 + 0.013*sl 0.44 + -0.001*sl t phl 0.40 0.34 + 0.026*sl 0.35 + 0.021*sl 0.58 + -0.002*sl t r 0.16 0.13 + 0.017*sl 0.11 + 0.025*sl 0.38 + -0.002*sl t f 0.19 0.12 + 0.034*sl 0.13 + 0.032*sl 0.47 + -0.003*sl update to dout t plh 0.77 0.75 + 0.011*sl 0.74 + 0.015*sl 0.90 + -0.001*sl t phl 0.82 0.75 + 0.039*sl 0.78 + 0.022*sl 1.01 + -0.002*sl t r 0.19 0.15 + 0.024*sl 0.14 + 0.025*sl 0.41 + -0.002*sl t f 0.26 0.19 + 0.034*sl 0.20 + 0.032*sl 0.54 + -0.003*sl setn to dout t plh 0.57 0.53 + 0.021*sl 0.55 + 0.015*sl 0.70 + -0.001*sl t phl 0.61 0.56 + 0.029*sl 0.57 + 0.023*sl 0.81 + -0.002*sl t r 0.20 0.14 + 0.028*sl 0.15 + 0.026*sl 0.43 + -0.002*sl t f 0.26 0.19 + 0.035*sl 0.20 + 0.031*sl 0.53 + -0.003*sl tck to dout t plh 1.34 1.31 + 0.013*sl 1.31 + 0.016*sl 1.48 + -0.001*sl t phl 1.41 1.35 + 0.029*sl 1.37 + 0.023*sl 1.61 + -0.002*sl t r 0.20 0.15 + 0.024*sl 0.15 + 0.024*sl 0.41 + -0.002*sl t f 0.26 0.18 + 0.039*sl 0.20 + 0.032*sl 0.54 + -0.003*sl enb to dout t plh 1.36 1.32 + 0.019*sl 1.33 + 0.015*sl 1.49 + -0.001*sl t phl 1.41 1.35 + 0.027*sl 1.36 + 0.023*sl 1.61 + -0.002*sl t r 0.19 0.14 + 0.025*sl 0.15 + 0.024*sl 0.40 + -0.002*sl t f 0.27 0.18 + 0.043*sl 0.21 + 0.030*sl 0.53 + -0.003*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 7-17 STD80/stdm80 jtin1 input scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 jtin1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.90 0.82 + 0.038*sl 0.83 + 0.035*sl 0.84 + 0.034*sl t phl 1.03 0.93 + 0.051*sl 0.95 + 0.046*sl 0.96 + 0.044*sl t r 0.29 0.16 + 0.063*sl 0.15 + 0.068*sl 0.13 + 0.071*sl t f 0.30 0.14 + 0.081*sl 0.14 + 0.080*sl 0.13 + 0.081*sl enb to tdo t plh 0.94 0.85 + 0.045*sl 0.89 + 0.031*sl 0.87 + 0.033*sl t phl 1.00 0.90 + 0.051*sl 0.92 + 0.046*sl 0.92 + 0.045*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.068*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.081*sl 0.15 + 0.079*sl 0.13 + 0.081*sl dinpn to dout t plh 0.26 0.21 + 0.022*sl 0.22 + 0.018*sl 0.52 + -0.023*sl t phl 0.33 0.26 + 0.033*sl 0.28 + 0.027*sl 0.76 + -0.041*sl t r 0.22 0.14 + 0.037*sl 0.15 + 0.036*sl 0.77 + -0.052*sl t f 0.29 0.19 + 0.052*sl 0.23 + 0.040*sl 0.95 + -0.063*sl mode to dout t plh 0.45 0.41 + 0.023*sl 0.42 + 0.019*sl 0.77 + -0.030*sl t phl 0.53 0.46 + 0.035*sl 0.48 + 0.029*sl 1.01 + -0.046*sl t r 0.20 0.13 + 0.033*sl 0.12 + 0.036*sl 0.71 + -0.048*sl t f 0.26 0.18 + 0.042*sl 0.19 + 0.038*sl 0.86 + -0.057*sl update to dout t plh 1.09 1.01 + 0.038*sl 1.06 + 0.022*sl 1.50 + -0.040*sl t phl 1.18 1.10 + 0.040*sl 1.12 + 0.033*sl 1.71 + -0.052*sl t r 0.25 0.19 + 0.029*sl 0.17 + 0.036*sl 0.76 + -0.048*sl t f 0.35 0.25 + 0.052*sl 0.27 + 0.043*sl 1.04 + -0.066*sl setn to dout t plh 0.76 0.71 + 0.027*sl 0.72 + 0.023*sl 1.14 + -0.036*sl t phl 0.84 0.76 + 0.040*sl 0.78 + 0.033*sl 1.38 + -0.052*sl t r 0.25 0.17 + 0.039*sl 0.17 + 0.037*sl 0.80 + -0.053*sl t f 0.35 0.26 + 0.047*sl 0.26 + 0.047*sl 1.06 + -0.067*sl tck to dout t plh 1.93 1.88 + 0.024*sl 1.89 + 0.023*sl 2.30 + -0.037*sl t phl 2.11 2.03 + 0.039*sl 2.05 + 0.032*sl 2.65 + -0.052*sl t r 0.24 0.17 + 0.034*sl 0.17 + 0.036*sl 0.78 + -0.051*sl t f 0.34 0.25 + 0.049*sl 0.27 + 0.041*sl 0.99 + -0.061*sl enb to dout t plh 1.97 1.90 + 0.032*sl 1.95 + 0.019*sl 2.33 + -0.036*sl t phl 2.08 2.00 + 0.040*sl 2.02 + 0.032*sl 2.63 + -0.055*sl t r 0.24 0.17 + 0.036*sl 0.16 + 0.038*sl 0.80 + -0.052*sl t f 0.35 0.25 + 0.048*sl 0.27 + 0.041*sl 1.00 + -0.061*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 7-18 sec asic jtint1 tri-state i/o control scan cell with capture, shift, update and set logic symbol pin description pin name i/o description dinp i parallel data input active low tdi i serial test data input mode i mode select inputlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update setn i active low set input tck i test clock input enb i active high test clock enable input dout o parallel data output tdo o serial test data output inst o updated instruction output dinp tdi mode update setn inst tck enb tdo shift dout cell data input loading (sl) STD80 stdm80 dinp 3 3 tdi 0 1 mode 1 1 shift 1 1 update 1 1 setn 0 0 tck 1 1 enb 0 0 gate count 13
sec asic 7-19 STD80/stdm80 jtint1 tri-state i/o control scan cell with capture, shift, update and set truth table note : outputs are de?ned in separate truth tables. timing requirements (typical process, 25 c, 5v, 3.3v) dinp tdi mode shift update setn tck enb output dout 0x0xxxxx0 1x0xxxxx1 x x 1 x x x x x inst tdo x x x x x x 0 tdoo 0xx0xx 10 1xx0xx 11 x0x1xx 10 x1x1xx 11 x x x x x x 0 x tdoo x x x x x x 1 x tdoo x x x x x x x tdoo inst xxxxx0xx1 xxxx0 1xxtdo x x x x 1 1 x x insto parameter symbol value (ns) STD80 stdm80 input setup time (tdi to tck) t su 0.52 0.66 input hold time (tdi to tck) t hd 0.33 0.33 input setup time (tdi to enb) t su 0.52 0.66 input hold time (tdi to enb) t hd 0.33 0.33 input setup time (dinpn to tck) t su 0.52 0.66 input hold time (dinpn to tck) t hd 0.33 0.33 input setup time (dinpn to enb) t su 0.52 0.66 input hold time (dinpn to enb) t hd 0.33 0.33 input setup time (shift to tck) t su 0.60 0.79 input hold time (shift to tck) t hd 0.33 0.33 input setup time (shift to enb) t su 0.63 0.79 input hold time (shift to enb) t hd 0.33 0.33 input hold time (setn to update) t hd 0.33 recovery time (setn) t rc 0.33 0.49
STD80/stdm80 7-20 sec asic jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 jtint1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.64 0.58 + 0.031*sl 0.60 + 0.024*sl 0.59 + 0.024*sl t phl 0.72 0.63 + 0.044*sl 0.65 + 0.038*sl 0.65 + 0.037*sl t r 0.20 0.12 + 0.040*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.066*sl 0.10 + 0.067*sl 0.07 + 0.069*sl enb to tdo t plh 0.66 0.56 + 0.052*sl 0.63 + 0.020*sl 0.59 + 0.024*sl t phl 0.74 0.61 + 0.062*sl 0.67 + 0.035*sl 0.65 + 0.037*sl t r 0.20 0.12 + 0.038*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.068*sl 0.10 + 0.067*sl 0.07 + 0.069*sl dinp to dout t plh 0.32 0.28 + 0.018*sl 0.29 + 0.015*sl 0.32 + 0.012*sl t phl 0.41 0.35 + 0.026*sl 0.37 + 0.021*sl 0.39 + 0.018*sl t r 0.19 0.14 + 0.029*sl 0.15 + 0.022*sl 0.12 + 0.026*sl t f 0.22 0.15 + 0.033*sl 0.15 + 0.032*sl 0.14 + 0.034*sl mode to dout t plh 0.36 0.32 + 0.023*sl 0.34 + 0.015*sl 0.36 + 0.012*sl t phl 0.36 0.31 + 0.028*sl 0.32 + 0.022*sl 0.36 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.16 + 0.022*sl 0.12 + 0.026*sl t f 0.21 0.14 + 0.033*sl 0.14 + 0.032*sl 0.13 + 0.034*sl update to dout t plh 0.79 0.75 + 0.021*sl 0.77 + 0.012*sl 0.77 + 0.012*sl t phl 0.80 0.77 + 0.015*sl 0.75 + 0.023*sl 0.80 + 0.018*sl t r 0.19 0.14 + 0.027*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.16 + 0.034*sl 0.16 + 0.031*sl 0.14 + 0.033*sl setn to dout t plh 0.55 0.51 + 0.021*sl 0.52 + 0.016*sl 0.56 + 0.012*sl t phl 0.59 0.54 + 0.029*sl 0.55 + 0.022*sl 0.59 + 0.018*sl t r 0.19 0.14 + 0.026*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.16 + 0.034*sl 0.16 + 0.033*sl 0.15 + 0.033*sl tck to dout t plh 1.35 1.31 + 0.020*sl 1.32 + 0.014*sl 1.34 + 0.012*sl t phl 1.39 1.34 + 0.025*sl 1.35 + 0.021*sl 1.38 + 0.018*sl t r 0.19 0.16 + 0.017*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.16 + 0.034*sl 0.16 + 0.032*sl 0.15 + 0.033*sl enb to dout t plh 1.35 1.31 + 0.018*sl 1.32 + 0.014*sl 1.35 + 0.012*sl t phl 1.41 1.36 + 0.026*sl 1.37 + 0.021*sl 1.40 + 0.018*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.023*sl 0.12 + 0.026*sl t f 0.22 0.16 + 0.033*sl 0.16 + 0.033*sl 0.15 + 0.033*sl update to inst t plh 0.69 0.64 + 0.026*sl 0.65 + 0.021*sl 0.62 + 0.024*sl t phl 0.70 0.62 + 0.040*sl 0.63 + 0.036*sl 0.62 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.09 + 0.050*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.063*sl 0.09 + 0.068*sl 0.09 + 0.069*sl setn to inst t plh 0.48 0.42 + 0.027*sl 0.43 + 0.024*sl 0.43 + 0.024*sl t phl 0.48 0.40 + 0.040*sl 0.41 + 0.038*sl 0.42 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.11 + 0.060*sl 0.09 + 0.068*sl 0.09 + 0.069*sl
sec asic 7-21 STD80/stdm80 jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 jtint1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to inst t plh 1.26 1.20 + 0.028*sl 1.21 + 0.023*sl 1.20 + 0.024*sl t phl 1.29 1.21 + 0.042*sl 1.22 + 0.038*sl 1.23 + 0.037*sl t r 0.20 0.11 + 0.044*sl 0.10 + 0.050*sl 0.08 + 0.052*sl t f 0.23 0.11 + 0.060*sl 0.10 + 0.068*sl 0.08 + 0.069*sl enb to inst t plh 1.27 1.18 + 0.047*sl 1.24 + 0.020*sl 1.20 + 0.024*sl t phl 1.31 1.18 + 0.063*sl 1.24 + 0.038*sl 1.25 + 0.037*sl t r 0.20 0.11 + 0.045*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.24 0.10 + 0.067*sl 0.10 + 0.068*sl 0.09 + 0.069*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
STD80/stdm80 7-22 sec asic jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 jtint1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.93 0.83 + 0.048*sl 0.87 + 0.034*sl 0.87 + 0.034*sl t phl 1.04 0.93 + 0.051*sl 0.95 + 0.046*sl 0.96 + 0.044*sl t r 0.28 0.16 + 0.063*sl 0.14 + 0.069*sl 0.12 + 0.071*sl t f 0.30 0.14 + 0.080*sl 0.14 + 0.081*sl 0.13 + 0.082*sl enb to tdo t plh 0.95 0.87 + 0.037*sl 0.88 + 0.035*sl 0.95 + 0.025*sl t phl 1.05 0.95 + 0.051*sl 0.96 + 0.046*sl 1.00 + 0.041*sl t r 0.28 0.14 + 0.069*sl 0.14 + 0.069*sl 0.13 + 0.071*sl t f 0.31 0.16 + 0.075*sl 0.15 + 0.079*sl 0.12 + 0.082*sl dinp to dout t plh 0.41 0.37 + 0.020*sl 0.37 + 0.021*sl 0.37 + 0.021*sl t phl 0.55 0.48 + 0.035*sl 0.50 + 0.029*sl 0.53 + 0.025*sl t r 0.23 0.16 + 0.037*sl 0.16 + 0.035*sl 0.17 + 0.033*sl t f 0.28 0.20 + 0.042*sl 0.20 + 0.041*sl 0.23 + 0.037*sl mode to dout t plh 0.51 0.46 + 0.027*sl 0.49 + 0.016*sl 0.45 + 0.023*sl t phl 0.51 0.43 + 0.036*sl 0.45 + 0.030*sl 0.45 + 0.030*sl t r 0.25 0.20 + 0.024*sl 0.16 + 0.036*sl 0.18 + 0.033*sl t f 0.29 0.20 + 0.045*sl 0.23 + 0.038*sl 0.21 + 0.040*sl update to dout t plh 1.10 1.03 + 0.037*sl 1.09 + 0.017*sl 1.07 + 0.019*sl t phl 1.16 1.11 + 0.027*sl 1.10 + 0.030*sl 1.12 + 0.026*sl t r 0.24 0.17 + 0.035*sl 0.16 + 0.037*sl 0.19 + 0.034*sl t f 0.30 0.21 + 0.045*sl 0.23 + 0.039*sl 0.20 + 0.043*sl setn to dout t plh 0.79 0.74 + 0.028*sl 0.76 + 0.022*sl 0.77 + 0.020*sl t phl 0.84 0.77 + 0.037*sl 0.79 + 0.031*sl 0.83 + 0.025*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.035*sl 0.19 + 0.032*sl t f 0.30 0.21 + 0.043*sl 0.21 + 0.044*sl 0.23 + 0.040*sl tck to dout t plh 1.95 1.90 + 0.024*sl 1.91 + 0.022*sl 1.93 + 0.019*sl t phl 2.06 1.98 + 0.037*sl 2.00 + 0.030*sl 2.03 + 0.025*sl t r 0.24 0.17 + 0.035*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.30 0.21 + 0.046*sl 0.22 + 0.041*sl 0.20 + 0.045*sl enb to dout t plh 1.99 1.93 + 0.032*sl 1.97 + 0.018*sl 1.97 + 0.018*sl t phl 2.10 2.03 + 0.036*sl 2.05 + 0.029*sl 2.06 + 0.027*sl t r 0.24 0.17 + 0.037*sl 0.13 + 0.048*sl 0.29 + 0.025*sl t f 0.30 0.21 + 0.044*sl 0.21 + 0.045*sl 0.26 + 0.038*sl update to inst t plh 0.96 0.86 + 0.048*sl 0.90 + 0.035*sl 0.94 + 0.029*sl t phl 0.98 0.86 + 0.060*sl 0.92 + 0.042*sl 0.91 + 0.044*sl t r 0.27 0.14 + 0.066*sl 0.13 + 0.069*sl 0.08 + 0.077*sl t f 0.31 0.15 + 0.081*sl 0.15 + 0.079*sl 0.13 + 0.082*sl setn to inst t plh 0.65 0.58 + 0.038*sl 0.59 + 0.034*sl 0.59 + 0.033*sl t phl 0.65 0.55 + 0.050*sl 0.59 + 0.037*sl 0.48 + 0.052*sl t r 0.28 0.14 + 0.074*sl 0.16 + 0.067*sl 0.11 + 0.074*sl t f 0.33 0.14 + 0.095*sl 0.21 + 0.074*sl 0.15 + 0.082*sl
sec asic 7-23 STD80/stdm80 jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 jtint1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to inst t plh 1.83 1.74 + 0.045*sl 1.78 + 0.034*sl 1.77 + 0.035*sl t phl 1.89 1.76 + 0.066*sl 1.82 + 0.044*sl 1.82 + 0.044*sl t r 0.28 0.14 + 0.067*sl 0.13 + 0.071*sl 0.11 + 0.074*sl t f 0.31 0.14 + 0.084*sl 0.16 + 0.077*sl 0.12 + 0.083*sl enb to inst t plh 1.86 1.79 + 0.035*sl 1.79 + 0.033*sl 1.84 + 0.027*sl t phl 1.92 1.82 + 0.050*sl 1.83 + 0.046*sl 1.84 + 0.045*sl t r 0.28 0.14 + 0.069*sl 0.14 + 0.070*sl 0.10 + 0.075*sl t f 0.31 0.15 + 0.077*sl 0.13 + 0.084*sl 0.17 + 0.079*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
STD80/stdm80 7-24 sec asic jtout1 output scan cell with capture, shift, update and set logic symbol pin description pin name i/o description dinp i parallel data input active low tdi i serial test data input mode i mode select inputlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update setn i active low set input tck i test clock input enb i active high test clock enable input dout o parallel data output tdo o serial test data output dinp tdi mode update setn tck enb tdo shift dout cell data input loading (sl) STD80 stdm80 dinp 3 3 tdi 0 1 mode 1 1 shift 1 1 update 1 1 setn 0 0 tck 1 1 enb 0 0 gate count 12
sec asic 7-25 STD80/stdm80 jtout1 output scan cell with capture, shift, update and set truth table note : outputs are de?ned in separate truth tables. in addition, an internal state known as latchq is de?ned as the output of the latch in the logic diagram. timing requirements (typical process, 25 c, 5v, 3.3v) dinp tdi mode shift update setn tck enb output dout 0x0xxxxx0 1x0xxxxx1 x x 1 x x x x x latchq tdo x x x x x x 0 tdoo 0xx0xx 10 1xx0xx 11 x0x1xx 10 x1x1xx 11 x x x x x x 0 x tdoo x x x x x x 1 x tdoo x x x x x x x tdoo latchq xxxxx0xx1 xxxx0 1xxtdo x x x x 1 1 x x latchqo parameter symbol value (ns) STD80 stdm80 input setup time (tdi to tck) t su 0.52 0.66 input hold time (tdi to tck) t hd 0.33 0.33 input setup time (tdi to enb) t su 0.52 0.66 input hold time (tdi to enb) t hd 0.33 0.33 input setup time (dinp to tck) t su 0.52 0.66 input hold time (dinp to tck) t hd 0.33 0.33 input setup time (dinp to enb) t su 0.52 0.66 input hold time (dinp to enb) t hd 0.33 0.33 input setup time (shift to tck) t su 0.60 0.79 input hold time (shift to tck) t hd 0.33 0.33 input setup time (shift to enb) t su 0.63 0.79 input hold time (shift to enb) t hd 0.33 0.33 input hold time (setn to update) t hd 0.33 recovery time (setn) t rc 0.33 0.49
STD80/stdm80 7-26 sec asic jtout1 output scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.44ns, sl: standard load) STD80 jtout1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.64 0.58 + 0.028*sl 0.59 + 0.025*sl 0.59 + 0.024*sl t phl 0.71 0.63 + 0.041*sl 0.64 + 0.038*sl 0.65 + 0.037*sl t r 0.20 0.11 + 0.043*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.23 0.10 + 0.067*sl 0.10 + 0.067*sl 0.08 + 0.069*sl enb to tdo t plh 0.64 0.58 + 0.028*sl 0.59 + 0.024*sl 0.59 + 0.024*sl t phl 0.71 0.63 + 0.040*sl 0.64 + 0.037*sl 0.64 + 0.037*sl t r 0.20 0.12 + 0.039*sl 0.10 + 0.049*sl 0.07 + 0.052*sl t f 0.24 0.10 + 0.067*sl 0.10 + 0.067*sl 0.08 + 0.069*sl dinp to dout t plh 0.32 0.28 + 0.018*sl 0.29 + 0.015*sl 0.32 + 0.012*sl t phl 0.41 0.35 + 0.026*sl 0.37 + 0.021*sl 0.39 + 0.018*sl t r 0.19 0.14 + 0.029*sl 0.15 + 0.022*sl 0.12 + 0.026*sl t f 0.22 0.15 + 0.033*sl 0.15 + 0.032*sl 0.14 + 0.034*sl mode to dout t plh 0.36 0.32 + 0.023*sl 0.34 + 0.015*sl 0.36 + 0.012*sl t phl 0.36 0.31 + 0.028*sl 0.32 + 0.022*sl 0.36 + 0.018*sl t r 0.20 0.15 + 0.023*sl 0.16 + 0.022*sl 0.12 + 0.026*sl t f 0.21 0.14 + 0.033*sl 0.14 + 0.033*sl 0.13 + 0.034*sl update to dout t plh 0.77 0.71 + 0.030*sl 0.74 + 0.014*sl 0.76 + 0.012*sl t phl 0.76 0.73 + 0.019*sl 0.72 + 0.023*sl 0.77 + 0.018*sl t r 0.20 0.15 + 0.027*sl 0.16 + 0.023*sl 0.13 + 0.026*sl t f 0.23 0.16 + 0.034*sl 0.16 + 0.032*sl 0.15 + 0.033*sl setn to dout t plh 0.54 0.50 + 0.021*sl 0.51 + 0.016*sl 0.55 + 0.012*sl t phl 0.58 0.50 + 0.039*sl 0.54 + 0.022*sl 0.58 + 0.018*sl t r 0.19 0.14 + 0.026*sl 0.15 + 0.023*sl 0.12 + 0.026*sl t f 0.23 0.16 + 0.038*sl 0.17 + 0.031*sl 0.15 + 0.033*sl tck to dout t plh 1.33 1.29 + 0.019*sl 1.30 + 0.015*sl 1.33 + 0.012*sl t phl 1.37 1.32 + 0.028*sl 1.33 + 0.021*sl 1.36 + 0.018*sl t r 0.19 0.16 + 0.018*sl 0.14 + 0.024*sl 0.13 + 0.026*sl t f 0.23 0.16 + 0.034*sl 0.17 + 0.032*sl 0.15 + 0.033*sl enb to dout t plh 1.33 1.29 + 0.018*sl 1.30 + 0.015*sl 1.33 + 0.012*sl t phl 1.37 1.32 + 0.026*sl 1.33 + 0.021*sl 1.36 + 0.018*sl t r 0.19 0.15 + 0.021*sl 0.14 + 0.024*sl 0.13 + 0.026*sl t f 0.22 0.16 + 0.032*sl 0.16 + 0.032*sl 0.15 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 10, *group3 : 10 < sl < < = =
sec asic 7-27 STD80/stdm80 jtout1 output scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.39ns, sl: standard load) stdm80 jtout1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.90 0.82 + 0.038*sl 0.83 + 0.035*sl 0.84 + 0.034*sl t phl 1.01 0.90 + 0.051*sl 0.92 + 0.046*sl 0.93 + 0.044*sl t r 0.29 0.16 + 0.063*sl 0.15 + 0.068*sl 0.13 + 0.071*sl t f 0.31 0.16 + 0.076*sl 0.15 + 0.079*sl 0.10 + 0.085*sl enb to tdo t plh 0.93 0.86 + 0.038*sl 0.87 + 0.035*sl 0.87 + 0.033*sl t phl 1.05 0.95 + 0.051*sl 0.96 + 0.046*sl 0.97 + 0.044*sl t r 0.28 0.15 + 0.066*sl 0.14 + 0.068*sl 0.12 + 0.072*sl t f 0.31 0.16 + 0.075*sl 0.15 + 0.079*sl 0.12 + 0.082*sl dinp to dout t plh 0.41 0.37 + 0.020*sl 0.37 + 0.021*sl 0.37 + 0.021*sl t phl 0.55 0.48 + 0.035*sl 0.50 + 0.029*sl 0.53 + 0.025*sl t r 0.23 0.16 + 0.037*sl 0.16 + 0.035*sl 0.17 + 0.033*sl t f 0.28 0.20 + 0.042*sl 0.20 + 0.041*sl 0.23 + 0.037*sl mode to dout t plh 0.49 0.42 + 0.032*sl 0.44 + 0.026*sl 0.49 + 0.019*sl t phl 0.51 0.43 + 0.036*sl 0.44 + 0.035*sl 0.50 + 0.026*sl t r 0.26 0.22 + 0.021*sl 0.19 + 0.031*sl 0.17 + 0.034*sl t f 0.29 0.20 + 0.045*sl 0.22 + 0.038*sl 0.21 + 0.040*sl update to dout t plh 1.07 1.04 + 0.017*sl 1.03 + 0.022*sl 1.04 + 0.020*sl t phl 1.13 1.04 + 0.044*sl 1.09 + 0.029*sl 1.12 + 0.024*sl t r 0.24 0.17 + 0.033*sl 0.17 + 0.034*sl 0.16 + 0.035*sl t f 0.30 0.21 + 0.042*sl 0.20 + 0.045*sl 0.27 + 0.036*sl setn to dout t plh 0.75 0.70 + 0.027*sl 0.71 + 0.023*sl 0.71 + 0.023*sl t phl 0.83 0.76 + 0.035*sl 0.77 + 0.032*sl 0.82 + 0.024*sl t r 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.15 + 0.037*sl t f 0.30 0.20 + 0.049*sl 0.22 + 0.043*sl 0.25 + 0.039*sl tck to dout t plh 1.92 1.87 + 0.024*sl 1.88 + 0.022*sl 1.90 + 0.019*sl t phl 2.02 1.94 + 0.041*sl 1.98 + 0.028*sl 1.98 + 0.028*sl t r 0.24 0.18 + 0.029*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t f 0.30 0.21 + 0.043*sl 0.22 + 0.041*sl 0.22 + 0.042*sl enb to dout t plh 1.95 1.90 + 0.026*sl 1.92 + 0.021*sl 1.93 + 0.019*sl t phl 2.06 2.00 + 0.030*sl 1.99 + 0.033*sl 2.05 + 0.025*sl t r 0.24 0.17 + 0.035*sl 0.16 + 0.036*sl 0.17 + 0.035*sl t f 0.32 0.19 + 0.063*sl 0.28 + 0.035*sl 0.25 + 0.038*sl *group1 : sl < 3, *group2 : 3 sl 7, *group3 : 7 < sl < < = =
jtag tap controller macrofunction jtag boundary scans STD80/stdm80 7-28 sec asic jtag tap controller macrofunction tap controller macrofunction consists of instruction register and data register scan paths, a bypass register, multiplexers and a 16-state ?nite state machine. the bypass register and instruction register are jtag devices. tap controller uses the largest available internal buffers (ivd8) to drive data register control signals. instruction register/decoder are external to tap controller since the register length and instruction codes vary from one asic design to another. the instruction register consists of three jtint1 macrocells. the instruction decoder is used to implement a minimum tap con?guration with a boundary scan register and an optional identi?cation register. tap controller input pin description name mandatory description bpsel bypass select dregdi data register scan path data-in iregdi instruction register scan path data-in tck ? test clock tdi ? test data input to the bypass register tms ? test mode select controlling state transitions of a finite state machine trstn test reset input tap controller output pin description name mandatory description dre data register enable control output ire instruction register enable control output rsto reset output shfdr data register shift control output shfir instruction register shift control output tdo ? test data output tdoe tdo tri-state enable output updatedr data register update control output updateir instruction register update control output the bulleted pins (tck, tdi, tms and tdo) are mandatory pins associated with the ieee p1149.1 standard test bus interface. trstn is an optional test reset input. it is possible to implement tap without the test reset input indicated in the ieee p1149.1 standard by setting trstn pin to high logic state. alternatively, if a power-on reset capability is desired, trstn pin should be set to active low and connected to the power-on reset circuitry. the 16 states of the ?nite state machine, diagrammed in the ?gure 9-3, also comply with the proposed ieee p1149.1 standard. state transitions occur on the rising edge of tck and are controlled by tms. to ensure stable state transitions, tms transitions occur on the falling edges of tck. capture, shift or update of test data take place on the next rising edge of tck after the state transition or on each subsequent rising edge of tck if no state transition occurs.
jtag boundary scans jtag tap controller macrofunction sec asic 7-29 STD80/stdm80 figure 7-3. tap controller i/o pin-out diagram figure 7-4. tap controller state diagram behavior of tap controller states test-logic-reset an initialization of the instruction register disables the test logic, allowing the on-chip system logic to operate normally. irrespective of its original state, tap controller reverts to test-logic-reset when tms is maintained high for ?ve rising edges of tck. run-test/idle idles in the state between scan operations or self-tests. capture-dr loads data parallelly into test data registers selected by the current instruction on the rising edge of tck. tdi bpsel dregdi trstn iregdi tms tck tdo shift-dr dre update-dr tdoe rsto shift-ir ire update-ir test-logic-reset run-test/idle select-dr scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 00 0 0 1 1 0 0 0 1 0 1
jtag tap controller macrofunction jtag boundary scans STD80/stdm80 7-30 sec asic shift-dr shifts data in the test data register between tdi and tdo one stage towards its serial output on each rising edge of tck. pause-dr temporarily halts test data register shifts in the serial path between tdi and tdo. update-dr latches the data from the shift register path to the parallel output of test data registers on the falling edge of tck. capture-ir the shift-register contained in the instruction register loads a pattern of ?xed logic value on the rising edge of tck. it is possible to load design-speci?c data into shift-register stages that are not set to ?xed values. shift-ir shifts data contained in the shift-register of the instruction register between tdi and tdo one stage towards its serial output on each rising edge of tck. pause-ir temporarily halts shifting of the instruction register. update-ir latches the instruction shifted into the instruction register to the parallel output from the shift register path on the falling edge of tck. select-dr-scan, select-ir-scan, exit1-dr, exit2-dr, exit1-ir, exit2-ir they are temporary controller states. state assignments for tap controller table 7-1. state assignments the bypass circuitry captures a low state during the data capture state of the ?nite state machine data cycle, as required by the proposed ieee 1149.1 standard. controller state state [3:0] controller state state [3:0] exit2-dr 0 exit2-ir 8 exit1-dr 1 exit1-ir 9 shift-dr 2 shift-ir a pause-dr 3 pause-ir b select-ir scan 4 run-test/idle c update-dr 5 update-ir d capture-dr 6 capture-ir e select-dr-scan 7 test-logic-reset f
jtag boundary scans instruction register/decoder macrofunction sec asic 7-31 STD80/stdm80 instruction register/decoder macrofunction instruction register macrofunction the instruction register provides eight instructions in a minimum 3-bit device. these 3 bits are suf?cient for operations of boundary scan cells and an instruction register, and three other operations such as the internal scan chains. devices requiring more than eight instructions need a customer-speci?c design. the instruction register allows an instruction to be shifted into the design. the instruction de?nes the test to be performed or the test data register to access or both. if a device identi?cation register is present, the output register must be initialized to idcode instruction when tap controller is in the test-logic-reset state. alternatively, it may be initialized to the bypass instruction. to support a fault isolation at the board-level, a constant binary 01 pattern is loaded into the least signi?cant bits of the instruction register when it is in the capture-ir state. instruction decoder macrofunction the instruction decoder operates with the instruction register to provide boundary scan control. designs requiring other options need a customer-speci?c design. instruction decoder input pin description: name descr iption inst (2:0) instruction register input instruction decoder output pin description: name descr iption 0_mode boundary scan output mode control i_mode boundary scan input mode control the instruction decoder has the following truth table. inst(2) inst(1) inst(0) i_mode 0_mode 00001 00111 01000 01100 10000 10100 11000 11100
implementation of ieee p1149.1/jtag jtag boundary scans STD80/stdm80 7-32 sec asic implementation of ieee p1149.1/jtag the following design procedures should be followed for asic implementation of ieee p1149.1/jtag using sec boundary scan cells: 1. allocate four (optionally ?ve) package pins for testing. 2. generate a bonding diagram, including provision for the corner pads that cannot be used for boundary scan i/os. 3. con?gure the top level device symbol with the same pin-out sequence as the packaged device. 4. select appropriate boundary scan macrocells, jtbi1, jtck, jtin1 and jtout1, for the boundary- scan i/o pads. jtck and jtin1 must be associated with inputs; jtout1 with outputs and jtbi1 with bi-directional inputs and outputs. 5. asic clock inputs generally use jtck macrocell, but it may be used for other critical inputs where performance considerations dominate. jtout1 macrocells are used for each output pin and jtbi1 macrocells are used by bi-directional pins. 6. jtag inputs (tdi, tck, tms), output (tdo) and optional trstn are connected to tap controller. the boundary scan register and the instruction register are connected to tdi and tck inputs. inputs, tdi, tms and trstn should have input pull-up resistors. 7. to start the boundary scan chain sequence, connect any tdi input to jtbi1, jtck, jtin1, or jtout1 macrocells. the chain sequence proceeds to each adjacent macrocell i/o pad until terminated. tdo output of the ?nal macrocell is connected to dregdi input of tap controller. similarly, the terminal tdo output of the instruction register is connected to iregdi of tap controller. 8. instruction register and data register control signals are connected to the instruction register and boundary scan registers, and inst signal lines from the instruction register are connected to the instruction decoder which supplies the control signals bpsel, i_mode and o_mode for tap controller and the boundary scan register. i_mode is connected to jtin1 macrocells and o_mode is connected to jtout1 macrocells. i_mode, o_mode and mode1 are also connected to the appropriate inputs of jtbi1 macrocells. 9. i_mode output is connected to a ivd8 macrocell and tn inputs of the bi-directional and tri-state output buffers associated with the respective i/o pads. other buffers may be required if there are a large number of bi-directional or tri-state pads. 10. if the design requires internal tri-state enable control signals, an additional jtint1 macrocell is needed for each enable. internal enable macrocells should be connected to tap controller rsto signal and o_mode control line. jtin1 macrocell is used for external tri-state enable input signals and should be connected to tap controller rsto signal and i_mode control line. 11. generate the test patterns to test jtag portion of the design. system clock considerations test and system clocks must be synchronized carefully. all phases of the system clock should be gated on and off at a central point within the system. when tms input is high, tck can run continuously and test modes is disabled.

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