View HCD66710A00_7086075.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 hd66710 (dot matrix liquid crystal display controller/driver) ade-207-306(z) '99.9 rev. 0.0 description the hd66710 dot-matrix liquid crystal display controller and driver lsi displays alphanumerics, numbers, and symbols. it can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8- bit microprocessor. since all the functions such as display ram, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimum system can be interfaced with this controller/driver. a single hd66710 is capable of displaying a single16-character line, two 16-character lines, or up to four 8-character lines. the hd66710 software is upwardly compatible with the lcd-ii (hd44780) which allows the user to easily replace an lcd-ii with an hd66710. in addition, the hd66710 is equipped with functions such as segment displays for icon marks, a 4-line display mode, and a horizontal smooth scroll, and thus supports various display forms. this achieves various display forms. the hd66710 character generator rom is extended to generate 240 5 8 dot characters. the low voltage version (2.7v) of the hd66710, combined with a low power mode, is suitable for any portable battery-driven product requiring low power dissipation. features 5 8 dot matrix possible low power operation support: ? 2.7v to 5.5v (low voltage) booster for liquid crystal voltage ? two/three times (13v max.) wide range of liquid crystal display driver voltage ? 3.0v to 13v extension driver interface high-speed mpu bus interface (2 mhz at 5-v operation) 4-bit or 8-bit mpu interface capability 80 8-bit display ram (80 characters max.)
hd66710 2 9,600-bit character generator rom ? 240 characters (5 8 dot) 64 8-bit character generator ram ? 8 characters (5 8 dot) 8 8-bit segment ram ? 40-segment icon mark 33-common 40-segment liquid crystal display driver programmable duty cycle (see list 1) wide range of instruction functions: ? functions compatible with lcd-ii: display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift ? additional functions: icon mark control, 4-line display, horizontal smooth scroll, 6-dot character width control, white-black inverting blinking cursor software upwardly compatible with hd44780 automatic reset circuit that initializes the controller/driver after power on internal oscillator with an external resistor low power consumption qfp1420-100 pin, tqfp1414-100 pin, bare-chip list 1 programmable duty cycles number of displayed maximum number of displayed characters lines duty ratio character single-chip operation 1 1/17 5 8-dot one 16-character line + 40 segments 2 1/33 5 8-dot two 16-character lines + 40 segments 4 1/33 5 8-dot four 8-character lines + 40 segments ordering information type no. package cgrom hd66710a00fs qfp1420-100 (fp-100a) japanese standard hd66710a00tf tqfp1414-100 (tfp-100b) HCD66710A00 chip hd66710a02fs qfp1420-100 (fp-100a) european font hd66710a02tf tqfp1414-100 (tfp-100b) hcd66710a02 chip
hd66710 3 lcd-ii family comparison item lcd-ii (hd44780u) hd66702r hd66710 hd66712u power supply voltage 2.7v to 5.5v 5v 10% (standard) 2.7v to 5.5v (low voltage) 2.7v to 5.5v 2.7v to 5.5v liquid crystal drive voltage 3.0v to 11v 3.0v to 8.3v 3.0v to 13.0v 2.7v to 11.0v maximum display digits per chip 8 characters 2 lines 20 characters 2 lines 16 characters 2 lines/ 8 characters 4 lines 24 characters 2 lines/ 12 characters 4 lines segment display none none 40 segments 60 segments display duty cycle 1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 1/17 and 1/33 1/17 and 1/33 cgrom 9,920 bits (208 5 8 dot characters and 32 5 10 dot characters) 7,200 bits (160 5 7 dot characters and 32 5 10 dot characters) 9,600 bits (240 5 8 dot characters) 9,600 bits (240 5 8 dot characters) cgram 64 bytes 64 bytes 64 bytes 64 bytes ddram 80 bytes 80 bytes 80 bytes 80 bytes segram none none 8 bytes 16 bytes segment signals 40 100 40 60 common signals 16 16 33 34 liquid crystal drive waveform abbb bleeder resistor for lcd power supply external (adjustable) external (adjustable) external (adjustable) external (adjustable) clock source extenal resistor or external clock external resistor or external clock external resistor or external clock external resistor or external clock r f oscillation frequency (frame frequency) 270 khz 30% (59 to 110 hz for 1/8 and 1/16 duty cycle; 43 to 80 hz for 1/11 duty cycle) 320 khz 30% (70 to 130 hz for 1/8 and 1/16 duty cycle; 51 to 95 hz for 1/11 duty cycle) 270 khz 30% (56 to 103 hz for 1/17 duty cycle; 57 to 106 hz for 1/33 duty cycle) 270 khz 30% (56 to 103 hz for 1/17 duty cycle; 57 to 106 hz for 1/33 duty cycle) r f resistance 91 k w : 5-v operation; 75 k w : 3-v operation 68 k w : 5-v operation; 56 k w : (3-v operation) 91 k w : 5-v operation; 75 k w : 3-v operation) 130 k w : 5-v operation; 110 k w : 3-v operation liquid crystal voltage booster circuit none none 2-3 times step- up circuit 2-3 times step- up circuit
hd66710 4 item lcd-ii (hd44780u) hd66702r hd66710 hd66712u extension driver control signal independent control signal independent control signal used in common with a driver output pin independent control signal reset function power on automatic reset power on automatic reset power on automatic reset power on automatic reset or reset input instructions lcd-ii (hd44780) fully compatible with the lcd-ii upper compatible with the lcd-ii upper compatible with the lcd-ii number of displayed lines 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 low power mode none none available available horizontal scroll character unit character unit dot unit dot unit bus interface 4 bits/8 bits 4 bits/8 bits 4 bits/8 bits serial; 4 bits/8 bits cpu bus timing 2 mhz: 5-v operation; 1 mhz: 3-v operation 1 mhz 2 mhz: 5-v operation; 1 mhz: 3-v operation 2 mhz: 5-v operation; 1 mhz: 3-v operation package qfp-1420-80 80-pin bare chip lqfp-2020-144 144-pin bare chip qfp-1420-100 100-pin bare chip tqfp1414-100 tcp-128 128-pin bare chip
hd66710 5 hd66710 block diagram com1 com33 v1 v2 v3 v4 v5 rs r/w e db4?b7 db3?b0 v cc gnd seg1 seg36 osc1 osc2 8 7 8 8 7 7 8 7 7 8 8 5/6 5 vci c1 c2 v5out2 8 3 v5out3 seg37/cl1 seg38/cl2 seg39/d seg40/m ext 33-bit shift register common signal driver timing generator display data ram (ddram) 80 8 bits address counter instruction decoder cpg instruction register (i r) reset circuit acl 40-bit shift register 40-bit latch circuit segment signal driver lcd drive voltage selector cursor and bling controller character generator rom (cgrom) 9,600 bytes character generator ram (cgram) 64 bytes segment ram (sgram) 8 bytes parallel/serial converter and attribute circuit booster busy flag data register (dr) input/ output buffer mpu interface
hd66710 6 hd66710 pin arrangement seg6 seg5 seg4 seg3 seg2 seg1 v cc test ext db7 db6 db5 db4 db3 db2 db1 db0 e r/w rs osc2 osc1 vci c2 c1 gnd v5out2 v5out3 v5 v4 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 com24 com23 com22 com21 com20 com19 com18 com17 com8 com7 com6 com5 com4 com3 com2 com1 com33 v1 v2 v3 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37/cl1 seg38/cl2 seg39/d seg40/m com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 hd66710 (fp-100a) ( top view )
hd66710 7 hd66710 pin arrangement (tqfp1414-100 pin) seg3 seg2 seg1 v cc test ext db7 db6 db5 db4 db3 db2 db1 db0 e r/w rs osc2 osc1 vci c2 c1 gnd v5out2 v5out3 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 com30 com31 com32 com24 com23 com22 com21 com20 com19 com18 com17 com8 com7 com6 com5 com4 com3 com2 com1 com33 v1 v2 v3 v4 v5 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37/cl1 seg38/cl2 seg39/d seg40/m com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 hd66710 (tfp-100b) (top view) 80 79 78 77 76 30 29 28 27 26
hd66710 8 hd66710 pad arrangement 79 81 80 1 100 2 y 29 30 31 x 50 51 52 type code chip size (x y) coordinate origin pad size (x y) : : : : 5.36 mm 6.06 mm pad center chip center 100 m 100 m hd66710
hd66710 9 hd66710 pad location coordinates pin no. pad name x y pin no. pad name x y 1 seg27 ?495 2910 51 v4 2458 ?910 2 seg28 ?695 2730 52 v5 2660 ?731 3 seg29 ?695 2499 53 v5out3 2660 ?500 4 seg30 ?695 2300 54 v5out2 2660 ?300 5 seg31 ?695 2100 55 gnd 2640 ?090 6 seg32 ?695 1901 56 c1 2650 ?887 7 seg33 ?695 1698 57 c2 2675 ?702 8 seg34 ?695 1498 58 vci 2675 ?502 9 seg35 ?695 1295 59 osc1 2675 ?303 10 seg36 ?695 1099 60 osc2 2675 ?103 11 seg37 ?695 900 61 rs 2675 ?00 12 seg38 ?695 700 62 r/ w 2675 ?01 13 seg39 ?695 501 63 e 2675 ?01 14 seg40 ?695 301 64 db0 2675 ?02 15 com9 ?695 98 65 db1 2675 ?9 16 com10 ?695 ?13 66 db2 2675 98 17 com11 ?695 ?02 67 db3 2675 301 18 com12 ?695 ?01 68 db4 2675 501 19 com13 ?695 ?01 69 db5 2675 700 20 com14 ?695 ?00 70 db6 2675 900 21 com15 ?695 ?100 71 db7 2675 1099 22 com16 ?695 ?303 72 ext 2675 1299 23 com25 ?695 ?502 73 test 2675 1502 24 com26 ?695 ?702 74 v cc 2695 1698 25 com27 ?695 ?901 75 seg1 2695 1901 26 com28 ?695 ?101 76 seg2 2695 2104 27 com29 ?695 ?300 77 seg3 2695 2300 28 com30 ?695 ?500 78 seg4 2695 2503 29 com31 ?695 ?731 79 seg5 2695 2730 30 com32 ?495 ?910 80 seg6 2495 2910 31 com24 ?051 ?910 81 seg7 2049 2910 32 com23 ?701 ?910 82 seg8 1699 2910 33 com22 ?498 ?910 83 seg9 1499 2910 34 com21 ?302 ?910 84 seg10 1300 2910 35 com20 ?102 ?910 85 seg11 1100 2910 36 com19 ?99 ?910 86 seg12 901 2910 37 com18 ?00 ?910 87 seg13 701 2910 38 com17 ?00 ?910 88 seg14 502 2910 39 com8 ?01 ?910 89 seg15 299 2910 40 com7 ?01 ?910 90 seg16 99 2910 41 com6 99 ?910 91 seg17 ?01 2910 42 com5 302 ?910 92 seg18 ?01 2910 43 com4 502 ?910 93 seg19 ?00 2910 44 com3 698 ?910 94 seg20 ?00 2910 45 com2 887 ?910 95 seg21 ?99 2910 46 com1 1077 ?910 96 seg22 ?099 2910 47 com33 1266 ?910 97 seg23 ?302 2910 48 v1 1488 ?910 98 seg24 ?501 2910 49 v2 1710 ?910 99 seg25 ?701 2910 50 v3 2063 ?910 100 seg26 ?051 2910
hd66710 10 pin functions table 1 pin functional description signal i/o device interfaced with function rs i mpu selects registers 0: instruction register (for write) busy flag: address counter (for read) 1: data register (for write and read) r/ w i mpu selects read or write 0: write 1: read e i mpu starts data read/write db4 to db7 i/o mpu four high order bidirectional tristate data bus pins. used for data transfer between the mpu and the hd66710. db7 can be used as a busy flag. db0 to db3 i/o mpu four low order bidirectional tristate data bus pins. used for data transfer between the mpu and the hd66710. these pins are not used during 4-bit operation. com1 to com33 o lcd common signals; those are not used become non-selected waveforms. at 1/17 duty rate, com1 to com16 are used for character display, com17 for icon display, and com18 to com33 become non-selected waveforms. at 1/33 duty rate, com1 to com32 are used for character display, and com33 for icon display. seg1 to seg35 o lcd segment signals seg36 o lcd segment signal. when ext = high, the same data as that of the first dot of the extension driver is output. seg37/cl1 o lcd/ extension driver segment signal when ext = low. when ext = high, outputs the extension driver latch pulse. seg38/cl2 o lcd/ extension driver segment signal when ext = low. when ext = high, outputs the extension driver shift clock. seg39/d o lcd/ extension driver segment signal at ext = low. at ext = high, the extension driver data. data on and after the 36th dot is output. seg40/m o lcd/ extension driver segment signal when ext = low. when ext = high, outputs the extension driver ac signal. ext i extension driver enable signal. when ext = high, seg37 to seg40 become extension driver interface signals. at this time, make sure that v5 level is lower than gnd level (0 v). v5 (low) gnd (high). v1 to v5 power supply power supply for lcd drive v cc ?v5 = 13v (max)
hd66710 11 table 1 pin functional description (cont) signal i/o device interfaced with function v cc , gnd power supply v cc : +2.7v to 5.5v, gnd: 0v osc1, osc2 oscillation resistor clock when cr oscillation is performed, a resistor must be connected externally. when the pin input is an external clock, it must be input to osc1. vci i input voltage to the booster, from which the liquid crystal display drive voltage is generated. vci is reference voltage and power supply for the booster. vci = 1.0v to 5.0v v cc v5out2 o v5 pin/ booster capacitance voltage input to the vci pin is boosted twice and output when the voltage is boosted three times, the same capacity as that of c1?2 should be connected. v5out3 o v5 pin voltage input to the vci pin is boosted three times and output. c1/c2 booster capacitance external capacitance should be connected when using the booster. test i test pin. should be wired to ground.
hd66710 12 function description registers the hd66710 has two 8-bit registers, an instruction register (ir) and a data register (dr). the ir stores instruction codes, such as display clear and cursor shift, and address information for the display data ram (ddram), the character generator ram (cgram), and the segment ram (segram). the mpu can only write to ir, and cannot be read from. the dr temporarily stores data to be written into ddram, cgram, or segram. data written into the dr from the mpu is automatically written into ddram, cgram, or segram by an internal operation. the dr is also used for data storage when reading data from ddram, cgram, or segram. when address infor-mation is written into the ir, data is read and then stored into the dr from ddram, cgram, or segram by an internal operation. data transfer between the mpu is then completed when the mpu reads the dr. after the read, data in ddram, cgram, or segram at the next address is sent to the dr for the next read from the mpu. by the register selector (rs) signal, these two registers can be selected (table 2). busy flag (bf) when the busy flag is 1, the hd66710 is in the internal operation mode, and the next instruction will not be accepted. when rs = 0 and r/ w = 1 (table 2), the busy flag is output from db7. the next instruction must be written after ensuring that the busy flag is 0. address counter (ac) the address counter (ac) assigns addresses to ddram, cgram, or segram. when an address of an instruction is written into the ir, the address information is sent from the ir to the ac. selection of ddram, cgram, and segram is also determined concurrently by the instruction. after writing into (reading from) ddram, cgram, or segram, the ac is automatically incremented by 1 (decremented by 1). the ac contents are then output to db0 to db6 when rs = 0 and r/ w = 1 (table 2). table 2 register selection rs r/ w operation 0 0 ir write as an internal operation (display clear, etc.) 0 1 read busy flag (db7) and address counter (db0 to db6) 1 0 dr write as an internal operation (dr to ddram, cgram, or segram) 1 1 dr read as an internal operation (ddram, cgram, or segram to dr)
hd66710 13 display data ram (ddram) display data ram (ddram) stores display data represented in 8-bit character codes. its capacity is 80 8 bits, or 80 characters. the area in display data ram (ddram) that is not used for display can be used as general data ram. see figure 1 for the relationships between ddram addresses and positions on the liquid crystal display. the ddram address (add) is set in the address counter (ac) as hexadecimal. 1-line display (n = 0) (figure 2) ? when there are fewer than 80 display characters, the display begins at the head position. for example, if using only the hd66710, 16 characters are displayed. see figure 3. when the display shift operation is performed, the ddram address shifts. see figure 3. ac6 ac5 ac4 ac3 ac2 ac1 ac0 1001110 ac (hexadecimal) example: ddram address 4e high order bits low order bits figure 1 ddram address 00 01 02 03 04 4e 4f ddram address (hexadecimal) display position (digit) 123 45 7980 . . . . . . . . . . . . . . . . . . figure 2 1-line display com1 to 8 com9 to 16 com1 to 8 com9 to 16 (left shift display) com1 to 8 com9 to 16 (right shift display) display position dram address 00 01 02 03 04 06 05 12345678 07 com1 to 8 08 09 0a 0b 0c 0e 0d 910111213141516 0f 01 02 03 04 05 07 06 12345678 08 09 0a 0b 0c 0d 0f 0e 910111213141516 10 4f 00 01 02 03 05 04 06 07 08 09 0a 0b 0d 0c 0e figure 3 1-line by 16-character display example
hd66710 14 2-line display (n = 1, and nw = 0) ? case 1: the first line is displayed from com1 to com16, and the second line is displayed from com17 to com32. care is required because the end address of the first line and the start address of the second line are not consecutive. for example, the case is shown in figure 5 where 16 2-line display is performed using the hd66710. when a display shift operation is performed, the ddram address shifts. see figure 4. com1 to 8 com17 to 24 com9 to 16 com25 to 32 display position ddram address com1 to 8 com17 to 24 com9 to 16 com25 to 32 com1 to 8 com17 to 24 com9 to 16 com25 to 32 (left shift display) (right shift display) 00 01 02 03 04 06 05 12345678 07 08 09 0a 0b 0c 0e 0d 910111213141516 0f 40 41 42 43 44 46 45 47 48 49 4a 4b 4c 4e 4d 4f 01 02 03 04 05 07 06 08 09 0a 0b 0c 0d 0f 0e 10 41 42 43 44 45 47 46 48 49 4a 4b 4c 4d 4f 4e 50 27 00 01 02 03 05 04 06 07 08 09 0a 0b 0d 0c 0e 67 40 41 42 43 45 44 46 47 48 49 4a 4b 4d 4c 4e figure 4 2-line by 16-character display example ? case 2: figure 5 shows the case where the ext pin is fixed to high, the hd66710 and the 40-output extension driver are used to extend the number of display characters. in this case, the start address from com9 to com16 of the hd66710 is 0ah, and that from com25 to com32 of the hd66710 is 4ah. to display 24 characters, the addresses starting at seg11 should be used. when a display shift operation is performed, the ddram address shifts. see figure 5. 00 01 02 03 04 06 05 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 com9 to com16 1234567 89101112 131415161718192021222324 hd66710 seg1 to seg35 hd66710 seg11 to seg35 (seg1 to seg10: skip) extension driver (1) seg1 to seg25 extension driver (1) seg1 to seg35 display position ddram address (left shift display) 01 02 03 04 06 05 08 09 41 42 43 44 45 46 07 47 48 49 0a 0b 4a 4b 0c 4c 12 13 52 53 14 15 16 54 55 56 17 57 com9 to com16 com25 to com32 00 01 02 03 04 06 05 07 08 09 40 41 42 43 44 45 46 47 48 49 0a 0b 4a 4b 0c 0d 0e 0f 10 4c 4d 4e 4f 50 11 12 13 51 52 53 14 15 16 54 55 56 com9 to com16 com25 to com32 1 2 3 4 5 6 7 8 9 101112 1314151617 18192021222324 18 58 27 67 (right shift display) 0d 0e 0f 10 11 4d 4e 4f 50 51 com1 to com8 com1 to com8 com17 to com24 com1 to com8 com17 to com24 figure 5 2-line by 24 character display example
hd66710 15 4-line display (nw = 1) ? case 1: the first line is displayed from com1 to com8, the second line is displayed from com9 to com16, the third line is displayed from com17 to com24, and the fourth line is displayed from com25 to com32. care is required because the ddram addresses of each line are not consecutive. for example, the case is shown in figure 6 where 8 4-line display is performed using the hd66710. when a display shift operation is performed, the ddram address shifts. see figure 6. (left shift display) 01 02 03 04 05 06 21 22 23 24 25 26 com1 to 8 com17 to 24 com9 to 16 com25 to 32 12 3456 7 41 42 43 44 45 46 61 62 63 64 65 66 07 27 67 8 28 48 47 08 68 (right shift display) 1 2 3456 7 13 33 53 00 01 02 03 04 05 06 20 21 22 23 24 25 26 40 41 42 43 44 45 46 60 61 62 63 64 65 66 73 8 00 01 02 03 04 05 06 20 21 22 23 24 25 26 com1 to 8 com17 to 24 com9 to 16 com25 to 32 123456 7 40 41 42 43 44 45 46 60 61 62 63 64 65 66 display position ddram address 07 27 8 47 67 figure 6 4-line display
hd66710 16 ? case 2: the case is shown in figure where the ext pin is fixed high, and the hd66710 and the 40- output extension driver are used to extend the number of display characters. when a display shift operation is performed, the ddram address shifts. see figure 7. 1 2 3 4 5 6 7 8 9 1011121314151617181920 4e 1 2 3 4 5 6 7 8 9 1011121314151617181920 01 02 03 04 05 06 11 12 13 0a 0b 0c 0d 0e 0f 10 07 08 09 00 21 22 23 24 25 26 31 32 33 2a 2b 2c 2d 2e 2f 30 27 28 29 20 41 42 43 44 45 46 51 52 53 4a 4b 4c 4d 4f 50 47 48 49 40 61 62 63 64 65 66 71 72 73 6a 6b 6c 6d 6e 6f 70 67 68 69 60 00 01 02 03 04 05 06 11 12 0a 0b 0c 0d 0e 0f 10 07 08 09 13 20 21 22 23 24 25 26 31 32 2a 2b 2c 2d 2e 2f 30 27 28 29 33 40 41 42 43 44 45 46 51 52 4a 4b 4c 4d 4e 4f 50 47 48 49 53 60 61 62 63 64 65 66 71 72 6a 6b 6c 6d 6e 6f 70 67 68 69 73 (display shift right) (display shift left) 00 01 02 03 04 05 06 20 21 22 23 24 25 26 com1 to 8 com17 to 24 com9 to 16 com25 to 32 1234 567 891011121314151617181920 40 41 42 43 44 45 46 60 61 62 63 64 65 66 11 12 13 0a 0b 0c 0d 0e 0f 10 07 08 09 31 32 33 2a 2b 2c 2d 2e 2f 30 27 28 29 51 52 53 4a 4b 4c 4d 4e 4f 50 47 48 49 71 72 73 6a 6b 6c 6d 6e 6f 70 67 68 69 hd66710 extension driver (1) extension driver (2) display position ddram address figure 7 4-line by 20-character display example
hd66710 17 character generator rom (cgrom) the character generator rom generates 5 8 dot character patterns from 8-bit character codes (table 3). it can generate 240 5 8 dot character patterns. user-defined character patterns are also available using a mask-programmed rom. character generator ram (cgram) the character generator ram allows the user to redefine the character patterns. in the case of 5 8 characters, up to eight may be redefined. write the character codes at the addresses shown as the left column of table 3 to show the character patterns stored in cgram. see table 5 for the relationship between cgram addresses and data and display patterns. segment ram (segram) the segment ram (segram) is used to enable control of segments such as an icon and a mark by the user program. for a 1-line display, segram is read from the com17 output, and as for 2- or 4-line displays, it is from the com33 output, to performs 40-segment display. as shown in table 6, bits in segram corresponding to segments to be displayed are directly set by the mpu, regardless of the contents of ddram and cgram. segram data is stored in eight bits. the lower six bits control the display of each segment, and the upper two bits control segment blinking. modifying character patterns character pattern development procedure the following operations correspond to the numbers listed in figure 8: 1. determine the correspondence between character codes and character patterns. 2. create a listing indicating the correspondence between eprom addresses and data. 3. program the character patterns into an eprom. 4. send the eprom to hitachi. 5. computer processing of the eprom is performed at hitachi to create a character pattern listing, which is sent to the user. 6. if there are no problems within the character pattern listing, a trial lsi is created at hitachi and samples are sent to the user for evaluation. when it is confirmed by the user that the character patterns are correctly written, mass production of the lsi will proceed at hitachi.
hd66710 18 determine character patterns create eprom address data listing write eprom eprom ? hitachi computer processing create character pattern listing evaluate character patterns ok? art work sample evaluation ok? masking trial sample no yes no yes m/t 1 3 2 4 5 6 note: for a description of the numbers used in this figure, refer to the preceding page. user hitachi mass production start figure 8 character pattern development procedure
hd66710 19 table 3 correspondence between character codes and character patterns (rom code: a00) xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits cg ram (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8) 0001 1000 1001 note: the user can specify any pattern in the character-generator ram.
hd66710 20 table 4 relationship between character codes and character patterns (rom code: a02) xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper bits lower bits cg ram (1) 0001 1000 1001 cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8) cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8) note: the character codes of the characters enclosed in the bold frame are the same as those of the first edition of the iso8859 and the character code compatible.
hd66710 21 programming character patterns this section explains the correspondence between addresses and data used to program character patterns in eprom. the hd66710 character generator rom can generate 240 5 8 dot character patterns. ? character patterns eprom address data and character pattern data correspond with each other to form a 5 8 dot character pattern (table 5). table 5 example of correspondence between eprom address data and character pattern (5 8 dots) a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 000 00 1 010 011 100 101 11 0 111 1 000 1 o4 o3 o2 o1 o0 1 0001 1 0001 01 010 0 0100 0 0100 00 1 00 0 0000 character code line position eprom address data lsb msb 0 0 0 0 0 0 0 0 ? a11 0 1011001 notes: 1. eprom addresses a11 to a4 correspond to a character code. 2. eprom addresses a2 to a0 specify a line position of the character pattern. eprom address a3 should be set to 0. 3. eprom data o4 to o0 correspond to character pattern data. 4. area which are lit (indicated by shading) are stored as 1, and unlit are as 0. 5. the eighth line is also stored in the cgrom, and should also be programmed. if the eighth line is used for a cursor, this data should all be set to zero. 6. eprom data bits o7 to o5 are invalid. 0 should be written in all bits.
hd66710 22 ? handling unused character patterns 1. eprom data outside the character pattern area: this is ignored by the character generator rom for display operation so any data is acceptable. 2. eprom data in cgram area: always fill with zeros. (eprom addresses 00h to ffh.) 3. treatment of unused user patterns in the hd66710 eprom: according to the user application, these are handled in either of two ways: a. when unused character patterns are not programmed: if an unused character code is written into ddram, all its dots are lit, because the eprom is filled with 1s after it is erased. b. when unused character patterns are programmed as 0s: nothing is displayed even if unused character codes are written into ddram. (this is equivalent to a space.) table 6 example of correspondence between character code and character pattern (5 8 dots) in cgram d7 d6 d5 d4 d3 d2 d1 d0 character code (ddram data) cgram data lsb msb a2 a1 a0 a5 a4 a3 0 000 00 1 010 0 11 100 101 110 111 0 0 * 0 0 0 0 10001 10001 10001 01010 00100 00100 00100 00000 000 *** o4 o3 o2 o1 o0 o5 o6 o7 cgram address 1 1 1 00000 ** 1 000 00 1 0 1 0 011 100 101 11 0 1 1 * 0 0 0 0 10001 10001 10001 0 1 0 1 0 00100 00100 00 1 00 111 * character pattern (1) character pattern (8) a) when character pattern in 5 8 dots
hd66710 23 table 6 example of correspondence between character code and character pattern (5 8 dots) in cgram (cont) d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a2 a1 a0 a5 a4 a3 o4 o3 o2 o1 o0 o5 o6 o7 0 000 001 010 011 100 101 110 111 0 0 * 0 0 0 0 10001 10001 10001 01010 00100 00100 00100 00000 000 ** 0 0 0 0 0 0 0 0 0 111 0000 1 000 00 1 010 0 11 100 101 110 1 1 * 0 0 0 0 10001 10001 10001 01010 00100 00100 00100 111 * 0 0 0 0 0 0 0 0 character pattern (1) character pattern (8) character code (ddram data) cgram address cgram data * b) when character pattern in 6 8 dots notes: 1. character code bits 0 to 2 correspond to cgram address bits 3 to 5 (3 bits: 8 types). 2. cgram address bits 0 to 2 designate the character pattern line position. the 8th line is the cursor position and its display is formed by a logical or with the cursor. 3. the character data is stored with the rightmost character element in bit 0, as shown in table 5. characters with 5 dots in width (fw = 0) are stored in bits 0 to 4, and characters with 6 dots in width (fw = 1) are stored in bits 0 to 5. 4. when the upper four bits (bits 7 to 4) of the character code are 0, cgram is selected. bit 3 of the character code is invalid (*). therefore, for example, the character codes 00 (hexadecimal) and 08 (hexadecimal) correspond to the same cgram address. 5. a set bit in the cgram data corresponds to display selection, and 0 to non-selection. 6. when the be bit of the function set register is 1, pattern blinking control of the lower six bits is controlled using the upper two bits (bits 7 and 6) in cgram. when bit 7 is 1, of the lower six bits, only those which are set are blinked on the display. when bit 6 is 1, a bit 4 pattern can be blinked as for a 5-dot font width, and a bit 5 pattern can be blinked as for a 6-dot font width. * indicates no effect.
hd66710 24 table 7 relationships between segram addresses and display patterns b1 b0 * s1 s2 s3 s4 s5 b1 b0 s1 s2 s3 s4 s5 s6 * s6 s7 s8 s9 s10 b1 b0 * s11 s12 s13 s14 s15 b1 b0 * s16 s17 s18 s19 s20 b1 b0 * s21 s22 s23 s24 s25 b1 b0 * s26 s27 s28 s29 s30 b1 b0 * s31 s32 s33 s34 s35 b1 b0 * s36 s37 s38 s39 s40 b1 b0 blinking control pattern on/off s7 s8 s9 s10 s11 s12 b1 b0 s13 s14 s15 s16 s17 s18 b1 b0 s19 s20 s21 s22 s23 s24 b1 b0 s25 s26 s27 s28 s29 s30 b1 b0 s31 s32 s33 s34 s35 s36 b1 b0 s37 s38 s39 s40 s41 s42 b1 b0 s43 s44 s45 s46 s47 s48 b1 b0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 a0 a1 a2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 segram address segram data blinking control pattern on/off a) 5-dot font width b) 6-dot font width notes: 1. data set to segram is output when com17 is selected, as for a 1-line display, and output when com33 is selected, as for a 2-line or a 4-line display. 2. s1 to s48 are pin numbers of the segment output driver. s1 is positioned to the left of the monitor. s37 to s48 are extension driver outputs for a 6-dot character width. 3. after s40 output at 5-dot font and s48 output at 6-dot font, s1 output is repeated again. 4. as for a 5-dot font width, lower five bits (d4 to d0) are display on.off information of each segment. for a 6-dot character width, the lower six bits (d5 to d0) are the display information for each segment. 5. when the be bit of the function set register is 1, pattern blinking of the lower six bits is controlled using the upper two bits (bits 7 and 6) in segram. when bit 7 is 1, only a bit set to ??of the lower six bits is blinked on the display. when bit 6 is 1, only a bit 4 pattern can be blinked as for a 5-dot font width, and only a bit 5 pattern can be blinked as for 6-dot font width. 6. bit 5 (d5) is invalid for a 5-dot font width. 7. set bits in the cgram data correspond to display selection, and zeros to non-selection.
hd66710 25 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg36 seg37 seg38 seg39 seg40 seg1 seg2 seg3 seg4 seg5 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg9 seg10 seg11 seg12 seg13 seg11 seg12 seg8 seg14 seg15 seg16 seg17 seg18 seg19 << extension driver >> i) 5-dot font width (fw = 0) ii) 6-dot font width (fw = 1) s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s36 s37 s38 s39 s40 s1 s2 s3 s4 s5 s1 s2 s3 s4 s5 s7 s8 s9 s10 s11 s43 s44 s45 s46 s47 s6 s12 s1 s2 s3 s4 s48 s5 s6 figure 9 relationships between segram data and display
hd66710 26 timing generation circuit the timing generation circuit generates timing signals for the operation of internal circuits such as ddram, cgrom, cgram, and segram. ram read timing for display and internal operation timing by mpu access are generated separately to avoid interfering with each other. therefore, when writing data to ddram, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 33 common signal drivers and 40 segment signal drivers. when the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. character pattern data is sent serially through a 40-bit shift register and latched when all needed data has arrived. the latched data then enables the driver to generate drive waveform outputs. sending serial data always starts at the display data character pattern corresponding to the last address of the display data ram (ddram). since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the hd66710 drives from the head display. cursor/blink control circuit the cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the display at a position corresponding to the location in stored in the address counter (ac). for example (figure 10), when the address counter is 08h, a cursor is displayed at a position corresponding to ddram address 08h.
hd66710 27 ac6 0 ac5 0 ac4 0 ac3 1 ac2 0 ac1 0 ac0 0 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0a 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0a 4a ac cursor position cursor position display position ddram address (hexadecimal) display position ddram address (hexadecimal) for a 1-line display for a 2-line display note: even if the address counter (ac) points to an address in the character generator ram (cgram) or segment ram (segram), cursor/blink black-white inversion will still occur, although it will produce meaningless results. figure 10 cursor/blink display example
hd66710 28 interfacing to the mpu the hd66710 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit mpus. for 4-bit interface data, only four bus lines (db4 to db7) are used for transfer. bus lines db0 to db3 are disabled. the data transfer between the hd66710 and the mpu is completed after the 4-bit data has been transferred twice. as for the order of data transfer, the four high order bits (for 8-bit operation, db4 to db7) are transfered before the four low order bits (for 8-bit operation, db0 to db3). the busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. two more 4-bit operations then transfer the busy flag and address counter data. for 8-bit interface data, all eight bus lines (db0 to db7) are used. rs r/w e ir7 ir6 ir5 ir4 bf ac6 ac5 ac4 db7 db6 db5 db4 instruction register (ir) write busy flag (bf) and address counter (ac) read data register (dr) read ir3 ir2 ir1 ir0 ac3 ac2 ac1 ac0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 figure 11 4-bit transfer example
hd66710 29 reset function initializing by internal reset circuit an internal reset circuit automatically initializes the hd66710 when the power is turned on. the following instructions are executed during the initialization. the busy flag (bf) is kept in the busy state until the initialization ends (bf = 1). the busy state lasts for 15 ms after v cc rises to 4.5v or 40 ms after the v cc rises to 2.7v. 1. display clear 2. function set: dl = 1; 8-bit interface data n = 0; 1-line display re = 0; extension register write disable 3. display on/off control: d = 0; display off c = 0; cursor off b = 0; blinking off be = 0; cgram/segram blinking off lp = 0; not in low power mode 4. entry mode set: i/d = 1; increment by 1 s = 0; no shift 5. extension function set: fw = 0; 5-dot character width b/w = 0; normal cursor (eighth line) nw = 0; 1- or 2-line display (depending on n) 6. segram address set: hds = 000; no scroll note: if the electrical characteristics conditions listed under the table power supply conditions using internal reset circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the hd66710. for such a case, initialization must be performed by the mpu as explained in the section, initializing by instruction.
hd66710 30 instructions outline only the instruction register (ir) and the data register (dr) of the hd66710 can be controlled by the mpu. before starting internal operation of the hd66710, control information is temporarily stored in these registers to allow interfacing with various mpus, which operate at different speeds, or various peripheral control devices. the internal operation of the hd66710 is determined by signals sent from the mpu. these signals, which include register selection (rs), read/write (r/ w ), and the data bus (db0 to db7), make up the hd66710 instructions (table 8). there are four categories of instructions that: designate hd66710 functions, such as display format, data length, etc. set internal ram addresses perform data transfer with internal ram perform miscellaneous functions normally, instructions that perform data transfer with internal ram are used the most. however, auto- incrementation by 1 (or auto-decrementation by 1) of internal hd66710 ram addresses after each data write can lighten the program load of the mpu. since the display shift instruction (table 8) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. when an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed. because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the mpu. note: be sure the hd66710 is not in the busy state (bf = 1) before sending an instruction from the mpu to the hd66710. if an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. refer to table 8 for the list of each instruction execution time.
hd66710 31 table 8 instructions code execution time (max) (when f cp or instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description f osc is 270 khz) clear display 0 0000 0000 1 clears entire display and sets ddram address 0 in address counter. 1.52 ms return home 0 0000 0001 sets ddram address 0 in address counter. also returns display from being shifted to original position. ddram contents remain unchanged. 1.52 ms entry mode set 0 0000 001i/ds sets cursor move direction and specifies display shift. these operations are performed during data write and read. 37 m s display on/off control (re = 0) 0 0000 01dcb sets entire display (d) on/off, cursor on/off (c), and blinking of cursor position character (b). 37 m s extension function set (re = 1) 0 0000 01fwb/wnw sets a font width, a black- white inverting cursor (b/w), a 6-dot font width (fw), and a 4-line display (nw). 37 m s cursor or display shift 0 0000 1s/cr/l moves cursor and shifts display without changing ddram contents. 37 m s function set (re = 0) 0 0001 dlnre sets interface data length (dl), number of display lines (n), and extension register write enable (re). 37 m s (re = 1) 0 0001 dlnrebelp sets cgram/segram blinking enable (be), and low power mode (lp). lp is available when the ext pin is low. 37 m s set cgram address (re = 0) 0 0 0 1 acg acg acg acg acg acg sets cgram address. cgram data is sent and received after this setting. 37 m s set ddram address (re = 0) 0 0 1 add add add add add add add sets ddram address. ddram data is sent and received after this setting. 37 m s set segram address (re = 1) 0 0 1 hds hds hds * asg asg asg sets segram address. ddram data is sent and received after this setting. also sets a horizontal dot scroll quantity (hds). 37 m s
hd66710 32 table 8 instructions (cont) code execution time (max) (when f cp or instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description f osc is 270 khz) read busy flag & address 0 1 bf ac ac ac ac ac ac ac reads busy flag (bf) indicating internal operation is being performed and reads address counter contents. 0 m s write data to ram (re = 0/1) 1 0 write data writes data into ddram, cgram, or segram. to write data to ddram cgram, clear re to 0; or to write data to segram, set re to 1. 37 m s t add = 5.5 m s* read data from ram (re = 0/1) 1 1 read data reads data from ddram, cgram, or segram. to read data from ddram or cgram, clear re to 0; to read data from segram, set re to 1. 37 m s t add = 5.5 m s* i/d = 1: increment i/d = 0: decrement s = 1: accompanies display shift d = 1: display on c = 1: cursor on b = 1: blink on fw = 1: 6-dot font width b/w = 1: black-white inverting cursor on nw = 1: four lines nw = 0: one or two lines s/c = 1: display shift s/c = 0: cursor move r/l = 1: shift to the right r/l = 0: shift to the left dl = 1: 8 bits, dl = 0: 4 bits n = 1: 2 lines, n = 0: 1 line re = 1: extension register access enable be = 1: cgram/segram blinking enable lp = 1: low power mode bf = 1: internally operating bf = 0: instructions acceptable ddram: display data ram cgram: character generator ram segram: segment ram acg: cgram address add: ddram address (corresponds to cursor address) aseg: segment ram address hds: horizontal dot scroll quantity ac: address counter used for both dd, cg, and segram addresses. notes: 1. indicates no effect. * after execution of the cgram/ddram/segram data write or read instruction, the ram address counter is incremented or decremented by 1. the ram address counter is updated after the busy flag turns off. in figure 12, t add is the time elapsed after the busy flag turns off until the address counter is updated. 2. extension time changes as frequency changes. for example, when f is 300 khz, the execution time is: 37 m s 270/300 = 33 m s. 3. execution time in a low power mode (lp = 1 & ext = low) becomes four times as long as for a 1-line mode, and twice as long as for a 2- or 4-line mode.
hd66710 33 busy state busy state (db7 pin) address counter (db0 to db6 pins) t add a a + 1 note: t depends on the operation frequency t = 1.5/(f or f ) seconds add add cp osc figure 12 address counter update
hd66710 34 instruction description clear display clear display writes space code (20)h (character pattern for character code (20)h must be a blank pattern) into all ddram addresses. it then sets ddram address 0 into the address counter, and returns the display to its original status if it was shifted. in other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). it also sets i/d to 1 (increment mode) in entry mode. s of entry mode does not change. it resets the extended register enable bit (re) to 0 in function set. return home return home sets ddram address 0 into the address counter, and returns the display to its original status if it was shifted. the ddram contents do not change. the cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). it resets the extended register enable bit (re) to 0 in function set. in addition, flicker may occur in a moment at the time of this instruction issue. entry mode set i/d: increments (i/d = 1) or decrements (i/d = 0) the ddram address by 1 when a character code is written into or read from ddram. the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to writing and reading of cgram and segram. s: shifts the entire display either to the right (i/d = 0) or to the left (i/d = 1) when s is 1 during ddram write. the display does not shift if s is 0. if s is 1, it will seem as if the cursor does not move but the display does. the display does not shift when reading from ddram. also, writing into or reading out from cgram and segram does not shift the display. in a low power mode (lp = 1), do not set s = 1 because the whole display does not normally shift. display on/off control when extension register enable bit (re) is 0, bits d, c, and b are accessed. d: the display is on when d is 1 and off when d is 0. when off, the display data remains in ddram, but can be displayed instantly by setting d to 1. c: the cursor is displayed when c is 1 and not displayed when c is 0. even if the cursor disappears, the function of i/d or other specifications will not change during display data write. the cursor is displayed using 5 dots in the 8th line for 5 8 dot character font.
hd66710 35 b: the character indicated by the cursor blinks when b is 1 (figure 13). the blinking is displayed as switching between all blank dots and displayed characters at a speed of 370-ms intervals when f cp or f osc is 270 khz. the cursor and blinking can be set to display simultaneously. (the blinking frequency changes according to f osc or the reciprocal of f cp . for example, when f cp is 300 khz, 370 270/300 = 333 ms.) extended function set when the extended register enable bit (re) is 1, fw, b/w, and nw bit shown below are accessed. once these registers are accessed, the set values are held even if the re bit is set to zero. fw: when fw is 1, each displayed character is controlled with a 6-dot width. the user font in cgram is displayed with a 6-bit character width from bits 5 to 0. as for fonts stored in cgrom, no display area is assigned to the leftmost bit, and the font is displayed with a 5-bit character width. if the fw bit is changed, data in ddram and cgram segram is destroyed. therefore, set fw before data is written to ram. when font width is set to 6 dots, the frame frequency decreases to 5/6 compared to 5-dot time. see ?scillator circuit?for details. b/w: when b/w is 1, the character at the cursor position is cyclically displayed with black-white invertion. at this time, bits c and b in display on/off control register are ?on? care? when f cp or f osc is 270 khz, display is changed by switching every 370 ms. nw: when nw is 1, 4-line display is performed. at this time, bit n in the function set register is ?on? care? note: after changing the n or nw or lp bit, please issue the return home or clear display instructions to cancel to shift display. i) cursor display example ii) blink display example white-black inverting display example iii) alternating display alternating display figure 13 cursor blink width control
hd66710 36 i) 5-dot character width ii) 6-dot character width figure 14 character width control cursor or display shift cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (table 9). this function is used to correct or search the display. in a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. in a 4-line display, the cursor moves to the second line when it passes the 20th character of the line. note that, all line displays will shift at the same time. when the displayed data is shifted repeatedly each line moves only horizontally. the second line display does not shift into the first line position. these instruction reset the extended register enable bit (re) to 0 in function set. the address counter (ac) contents will not change if the only action performed is a display shift. in low power mode (lp = 1), whole-display shift cannot be normally performed. function set only when the extended register enable bit (re) is 1, the be bit shown below can be accessed. bits dl and n can be accessed regardless of re. dl: sets the interface data length. data is sent or received in 8-bit lengths (db7 to db0) when dl is 1, and in 4-bit lengths (db7 to db4) when dl is 0. when 4-bit length is selected, data must be sent or received twice. table 9 shift function s/c r/l 0 0 shifts the cursor position to the left. (ac is decremented by one.) 0 1 shifts the cursor position to the right. (ac is incremented by one.) 1 0 shifts the entire display to the left. the cursor follows the display shift. 1 1 shifts the entire display to the right. the cursor follows the display shift.
hd66710 37 n: when bit nw in the extended function set is 0, a 1- or a 2-line display is set. when n is 0, 1-line display is selected; when n is 1, 2-line display is selected. when nw is 1, a 4-line display is set. at this time, n is ?on? care? re: when the re bit is 1, bit be and lp in the extended function set registe, the segram address set register, and the extended function set register can be accessed. when bit re is 0, the registers described above cannot be accessed, and the data in these registers is held. to maintain compatibility with the hd44780, the re bit should be fixed to 0. clear display, return home and cursor or display shift instruction a reset the re bit to 0. be: when the re bit is 1, this bit can be rewritten. when this bit is 1, the user font in cgram and the segment in segram can be blinked according to the upper two bits of cgram and segram. lp: when the re bit is 1, this bit can be rewritten. when lp is set to 1 and the ext pin is low (without an extended driver), the hd66710 operates in low power mode. in 1-line display mode, the hd66710 operates on a 4-division clock, and in a 2-line or a 4-line display mode, the hd66710 operates on a 2-division clock. according to these operations, instruction execution takes four times or twice as long. notice that in a low power mode, display shift cannot be performed. note: perform the dl, n, nw, fw functions at the head of the program before executing any instructions (except for the read busy flag and address instruction). from this point, if bit n, nw, or fw is changed after other instructions are executed, ram contents may be lost. after changing the n or nw or lp bit, please issue the return home or clear display instruction cancel to shift display. set cgram address a cgram address can be set while the re bit is cleared to 0. set cgram address sets the cgram address binary aaaaaa into the address counter. data is then written to or read from the mpu for cgram. table 10 display line set nnw no. of display lines character font duty factor maximum number of characters/1 line with extended drivers 0015 8 dots 1/17 50 characters 1025 8 dots 1/33 30 characters *145 8 dots 1/33 20 characters note: * indicates don? care.
hd66710 38 set ddram address set ddram address sets the ddram address binary aaaaaaa into the address counter while the re bit is cleared to 0. data is then written to or read from the mpu for ddram. however, when n and nw is 0 (1-line display), aaaaaaa can be 00h to 4fh. when n is 1 and nw is 0 (2-line display), aaaaaaa is (00)h to (27)h for the first line, and (40)h to (67)h for the second line. when nw is 1 (4-line display), aaaaaaa is (00)h to (13)h for the first line, (20)h to (33)h for the second line, (40)h to (53)h for the third line, and (60)h to (73)h for the fourth line. set segram address only when the extended register enable bit (re) is 1, hs2 to hs0 and the segram address can be set. the segram address in the binary form aaa is set to the address counter. segram can then be written to or read from by the mpu. note: when performing a horizontal scroll is described above by connecting an extended driver, the maximum number of characters per line decreases by one. in other words, 49 characters, 29 characters, and 19 characters are displayed in 1-line, 2-line, and 4-line modes, respectively. notice that in low power mode (lp = 1), the display shift and scroll cannot be performed. read busy flag and address read busy flag and address reads the busy flag (bf) indicating that the system is now internally operating on a previously received instruction. if bf is 1, the internal operation is in progress. the next instruction will not be accepted until bf is reset to 0. check the bf status before the next write operation. at the same time, the value of the address counter in binary aaaaaaa is read out. this address counter is used by all cg, dd, and segram addresses, and its value is determined by the previous instruction. the address contents are the same as for cgram, ddram, and segram address set instructions. table 11 hs2 to hs0 settings hs2 hs1 hs0 description 0 0 0 no shift. 0 0 1 shift the display position to the left by one dot. 0 1 0 shift the display position to the left by two dots. 0 1 1 shift the display position to the left by three dots. 1 0 0 shift the display position to the left by four dots. 1 0 1 shift the display position to the left by five dots. 1 1 0 or 1 no shift.
hd66710 39 code note: don? care. * code code code rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 0 db0 1 rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 0 db2 0 db1 1 db0 * rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 0 db2 1 db1 i/d db0 s rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 1 db2 d db1 c db0 b rs 0 r/w 0 db7 0 db6 0 db5 0 db4 0 db3 1 db2 fw db1 b/w db0 nw rs 0 r/w 0 db7 0 db6 0 db5 0 db4 1 db3 3/c db2 r/l db1 * db0 * rs 0 r/w 0 db7 0 db6 0 db5 0 db4 dl db3 n db2 re db1 be* db0 lp* rs 0 r/w 0 db7 0 db6 1 db5 a db4 a db3 a db2 a db1 a db0 a return home clear display entry mode set display on/off control code code note: * re = 0 code highest order bit lowest order bit cursor or display shift function set set cgram address note: don? care. * extended function set re = 1 code be and lp can be rewritten while re = 1. figure 15 character width control
hd66710 40 rs 0 r/w 1 db7 bf db6 a db5 a db4 a db3 a code db2 a db1 a db0 a highest order bit lowest order bit highest order bit lowest order bit rs 0 r/w 0 db7 1 db6 a db5 a db4 a db3 a db2 a db1 a db0 a read busy flag and address set segram address set ddram address re = 0 rs 0 r/w 0 db7 1 db2 a db1 a db0 a re = 1 db6 hs2 db5 hs1 db4 hs0 db3 * figure 15 character width control (cont)
hd66710 41 write data to cg, dd, or segram this instruction writes 8-bit binary data dddddddd to cg, dd or segram. if the re bit is cleared, cg or ddram is selected, as determined by the previous specification of the address set instruction; if the re bit is set, segram is selected. after a write, the address is automatically incremented or decremented by 1 according to the entry mode. the entry mode also determines the display shift direction. read data from cg, dd, or segram this instruction reads 8-bit binary data dddddddd from cg, dd, or segram. if the re bit is cleared, cg or ddram is selected, as determined by the previous specification of the address set instruction; if the re bit is set, segram is selected. if no address is specified, the first data read will be invalid. when executing serial read instructions, the next address is normally read from the next address. an address set instruction need not be executed just before this read instruction when shifting the cursor by a cursor shift instruction (when reading from ddram). a cursor shift instruction is the same as a set ddram address instruction. after a read, the entry mode automatically increases or decreases the address by 1. however, a display shift is not executed regardless of the entry mode. note: the address counter (ac) is automatically incremented or decremented after write instructions to cg, dd or segram. the ram data selected by the ac cannot be read out at this time even if read instructions are executed. therefore, to read data correctly, execute either an address set instruction or a cursor shift instruction (only with ddram), or alternatively, execute a preliminary read instruction to ensure the address is correctly set up before accessing the data. higher order bits lower order bits rs 1 r/w 0 db7 d db6 d db5 d db4 d db3 d re = 0/1 code db2 d db1 d db0 d rs 1 r/w 0 db7 d db6 d db5 d db4 d db3 d db2 d db1 d db0 d higher order bits lower order bits read data from cg, dd, or segram write data to cg, dd, or segram re = 0/1 code figure 15 character width control (cont)
hd66710 42 interfacing the hd66710 1) interface to 8-bit mpus hd66710 can interface to 8-bit mpu directly with e clock, or to 8-bit mcu through i/o port. when number of i/o port in mcu, or interfacing bus width, 4-bit interface function is useful.
r/w e internal signal db7 internal operation data busy busy not busy data instruction write busy flag check busy flag check busy flag check instruction write rs figure 16 example of 8-bit data transfer timing sequence c0 c1 c2 a0?7 e rs r/w db0?b7 8 h8/325 hd66710 connection to h8/325 with port (when single chip mode) figure 17 8-bit mpu interface
hd66710 43 2) interface to 4-bit mpus hd66710 can interface to 4-bit mcu through i/o port. 4-bit data for high and low order must be transferred twice continuously. the dl bit in function set selects the interface data length.

e internal signal db7 internal operation instruction write busy flag check busy flag check instruction write rs ir7 busy not busy ir3 ac3 ac3 d7 d3 r/w figure 18 example of 4-bit data transfer timing sequence d15 d14 d13 r10?13 rs r/w e db4 ?b7 hmcs4019r hd66710 4 com1 com16 seg1 seg40 16 40 connected to the lcd figure 19 interface to hmcs4019r
hd66710 44 oscillator circuit relationship between oscillation frequency and liquid crystal display frame frequency the liquid crystal display frame frequencies of figure 21 apply only when the oscillation frequency is 270 khz (one clock period: 3.7 m s). osc1 osc1 osc2 clock rf the oscillator frequency can be adjusted by oscillator resistance (rf). if rf is increased or power supply voltage is decreased, the oscillator frequency decreases. the recommended oscillator resistor is as follows. hd66710 hd66710 ?rf = 91 k w 2% (v cc = 5v) ?rf = 75 k w 2% (v cc = 3v) 1) when an external clock is used 2) when an internal oscillator is used figure 20 oscillator circuit 1 2 3 4 32 33 1 2 3 32 33 v cc v1 v4 v5 com1 100 clocks (6-dot font width: 120 clocks) (2) 1 /33 duty cycle 1 frame 1 frame 1 2 3 4 16 17 1 2 3 16 17 200 clocks (6-dot font width: 240 clocks) v cc v1 v4 v5 com1 1 frame 1 frame (1) 1 /17 duty cycle item line selection period frame frequency normal display mode (lp = 0) 5-dot font width low power mode (lp = 1) 5-dot font width 200 clocks 79.4 hz 240 clocks 66.2 hz 50 clocks 79.4 hz 60 clocks 66.2 hz item line selection period frame frequency normal display mode (lp = 0) low power mode (lp = 1) 100 clocks 81.8 hz 120 clocks 68.2 hz 50 clocks 81.8 hz 60 clocks 68.2 hz 6-dot font width 6-dot font width 5-dot font width 5-dot font width 6-dot font width 6-dot font width figure 21 frame frequency
hd66710 45 power supply for liquid crystal display drive 1) when an external power supply is used v cc v1 v2 v3 v4 v5 v cc r r r0 r r vr v ee 2) when an internal booster is used v cc v1 v2 v3 v4 v5 v cc c1 c2 vci gnd v5out2 r r r0 r r c1 c2 vci gnd v5out2 r r r0 r r v5out3 v5out3 m 1f + m 1f + m 1f + m 1f + m 1f + (boosting twice) (boosting three times) v cc v1 v2 v3 v4 v5 v cc notes: 1. 2. 3. boosting output voltage should not exceed the power supply voltage (2) (13v max.) in the absolute maximum ratings. especially, voltage of over 4.3v should not be input to the reference voltage (vci) when boosting three times. vci input terminal is used for reference voltage and power supply for the internal booster. input current into the vci pin needs three times or more of load current through the bleeder resistor for lcd. so, when it adjusts lcd driving voltage (vlcd), input voltage should be controlled with transistor to supply lcd load current. please notice connection (+/? when it uses capacitors with poler. ntc-type thermistor ntc-type thermistor gnd gnd gnd gnd
hd66710 46 table 12 duty factor and power supply for liquid crystal display drive item data number of lines 1 2/4 duty factor 1/17 1/33 bias 1/5 1/6.7 divided resistance r r r r0 r 2.7r note: r changes depending on the size of liquid crystal penel. normally, r must be 4.7 k w to 20 k w .
hd66710 47 extension driver lsi interface by bringing the ext pin high, segment driver pins (seg37 to seg40) functions as the extended driver interface outputs. from these pins, a latch pulse (cl1), a shift clock (cl2), data (d), and an ac signal (m) are output. the same data is output from the seg36 pin of the hd66710 and the start segment pin (seg1) of the extension driver. due to the character baundary, the seg1 output is used for the 5-dot font width. for the 6-dot font width, the seg36 output is used, and the seg1 output of the extension driver must not be used. when the extension driver lsi interface is used, ground level (gnd) must be higher than the v5 level. table 13 required number of 40-output extension driver controller hd66710* hd44780 hd66702 display line 5-dot width 6-dot width 5-dot width 5-dot width 16 2 lines not required 1 1 not required 20 2 lines 1 1 2 not required 24 2 lines 1 2 2 1 40 2 lines disabled disabled 4 3 12 4 lines 1 1 disabled disabled 16 4 lines 2 2 disabled disabled 20 4 lines 2 3 disabled disabled note: * the number of display lines can be extended to 30 2 lines or 20 4 lines. com1 com33 seg1?eg40 ext seg1 seg40 gnd hd66710 com1 com33 ext seg37/cl1 v cc cl2 m d cl1 hd66710 seg1 seg35 extension driver seg1 seg35 seg38/cl2 seg39/d seg40/m 1) 1-chip operation (ext = low, 5-dot font width) 2) when using the extension driver (ext = high, 5-dot font width) 16 2-line display 24 2-line display figure 22 hd66710 and the extension driver connection
hd66710 48 when using one hd66710, the start address of com9?om16/com25?om33 is calculated by adding 8 to the start address of com9?om16 com25?om32. when extending the address, the start address is calculated by adding a(10) to com9?om16/com25 to com32. the relationship betweenmodes and display start addresses is shown below. table 14 display start address in each mode number of lines 1-line mode 2-line mode 4-line mode output ext low ext high ext low ext high ext low/high com1?om8 d00 1 d00 1 d00 1 d00 1 d00 1 com9?om16 d08 1 d0a 1 d08 1 d0a 1 d20 1 com17?om24 d40 1 d40 1 d40 1 com25?om32 d48 1 d4a 1 d60 1 com17 s00 s00 com33 s00 s00 s00 notes: 1. when an ext pin is low, the extension driver is not used; otherwise, the extension driver is used. 2. d?is the start address of display data ram (ddram) for each display line. 3. s?is the start address of segment ram (segram). 4. 1 following d?indicates increment or decrement at display shift.
hd66710 49 interface to liquid crystal display example of 5-dot font width connection com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg4 seg5 seg40 com17 hd66710 18916 seg6 ext hd66710 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 seg1 seg2 seg3 seg4 seg5 seg40 com33 18916 seg6 ext a) 16 1-line + 40-segment display (5-dot font, 1/17 duty) b) 16 2-line + 40-segment display (5-dot font, 1/33 duty) + ? x = 1 + ? x = 1 figure 23 liquid crystal display and hd66710 connections (single-chip operation)
hd66710 50 example of 6-dot font width connection hd66710 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 com9 com11 com12 com14 seg1 seg2 seg3 seg4 seg5 seg7 seg8 seg9 com33 16712 seg6 seg36 28 seg10 ext com10 com13 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 a) 12 2-line + 36-segment display (6-dot font, 1/33 duty) + ? x = 1 note: the ddram address between 6th and 7th digits is not contiguous. figure 24 liquid crystal display and hd66710 connections (6-dot font width)
hd66710 51 instruction and display correspondence 8-bit operation, 16-digit 1-line display with internal reset refer to table 15 for an example of an 16-digit 1-line display in 8-bit operation. the hd66710 functions must be set by the function set instruction prior to the display. since the display data ram can store data for 80 characters, a character unit scroll can be performed by a display shift instruction. a dot unit smooth scroll can also be performed by a horizontal scroll instruction. since data of display ram (ddram) is not changed by a display shift instruction, the display can be returned to the first set display when the return home operation is performed. 4-bit operation, 16-digit 1-line display with internal reset the program must set all functions prior to the 4-bit operation (table 16). when the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation. since db0 to db3 are not connected, a rewrite is then required. however, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see table 16). thus, db4 to db7 of the function set instruction is written twice. 8-bit operation, 16-digit 2-line display with internal reset for a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 16 characters in the first line, the ddram address must be again set after the 16th character is completed (see table 17). the display shift is performed for the first and second lines. if the shift is repeated, the display of the second line will not move to the first line. the same display will only shift within its own line for the number of times the shift is repeated. 8-bit operation, 8-digit 4-line display with internal reset the re bit must be set by the function set instruction and then the nw bit must be set by an extension function set instruction. in this case, 4-line display is always performed regardless of the n bit setting (table 18). in a 4-line display, the cursor automatically moves from the first to the second line after the 20th digit of the first line has been written. thus, if there are only 8 characters in the first line, the ddram address must be set again after the 8th character is completed. display shifts are performed on all lines simultaneously. note: when using the internal reset, the electrical characteristics in the power supply conditions using internal reset circuit table must be satisfied. if not, the hd66710 must be initialized by instructions. see the section, initializing by instruction.
hd66710 52 table 15 8-bit operation, 16-digit 1-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66710 is initialized by the internal reset circuit) initialized. no display. 2 function set 00001100* * sets to 8-bit operation and selects 1-line display. bit 2 must always be cleared. 3 display on/off control 0000001110 _ turns on display and cursor. entire display is in space mode because of initialization. 4 entry mode set 0000000110 _ sets mode to increment the address by one and to shift the cursor to the right at the time of write to the ram. display is not shifted. 5 write data to cgram/ddram 1001001000 h_ writes h. ddram has already been selected by initialization when the power was turned on. 6 write data to cgram/ddram 1001001001 hi_ writes i. 7 8 write data to cgram/ddram 1001001001 hitachi_ writes i. 9 entry mode set 0000000111 hitachi_ sets mode to shift display at the time of write. 10 write data to cgram/ddram 1000100000 itachi _ writes a space.
hd66710 53 table 15 8-bit operation, 16-digit 1-line display example with internal reset (cont) step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 11 write data to cgram/ddram 1001001101 tachi m_ writes m. 12 13 write data to cgram/ddram 1001001111 microko_ writes o. 14 cursor or display shift 00000100* * microko _ shifts only the cursor position to the left. 15 cursor or display shift 00000100* * microko _ shifts only the cursor position to the left. 16 write data to cgram/ddram 1001000011 icroco _ writes c over k. the display moves to the left. 17 cursor or display shift 00000111* * microco _ shifts the display and cursor position to the right. 18 cursor or display shift 00000101* * microco_ shifts the display and cursor position to the right. 19 write data to cgram/ddram 1001001101 icrocom_ writes m. 20 21 return home 0000000010 hitachi _ returns both display and cursor to the original position (address 0).
hd66710 54 table 16 4-bit operation, 16-digit 1-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66710 is initialized by the internal reset circuit) initialized. no display. 2 function set 000010 sets to 4-bit operation. clear bit 2. in this case, operation is handled as 8 bits by initialization. * 3 function set 000010 000100 sets 4-bit operation and selects1-line display. clear be, lp bits. 4-bit operation starts from this step. 4 function set 000010 0000** sets 4-bit operation and selects1-line display. clear re bit. 5 return home 000000 000010 returns both display and cursor to the original position (address 0). 6 display on/off control 000000 001110 _ turns on display and cursor. entire display is in space mode because of initialization. 7 entry mode set 000000 000110 _ sets mode to increment the address by one and to shift the cursor to the right at the time of write to the dd/cgram. display is not shifted. 8 write data to cgram/ddram 100100 101000 h_ writes h. ddram has already been selected by initialization. note: 1. the control is the same as for 8-bit operation beyond step #8. 2. when db3 to db0 pins are open in 4-bit mode, the re, be, lp bits are set to ??at step #2. so, these bits are clear to ??at step #3.
hd66710 55 table 17 8-bit operation, 16-digit 2-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66710 is initialized by the internal reset circuit) initialized. no display. 2 function set 00001110* * sets to 8-bit operation and selects 1-line display. clear bit 2. 3 display on/off control 0000001110 _ turns on display and cursor. all display is in space mode because of initialization. 4 entry mode set 0000000110 _ sets mode to increment the address by one and to shift the cursor to the right at the time of write to the ram. display is not shifted. 5 write data to cgram/ddram 1001001000 h_ writes h. ddram has already been selected by initialization when the power was turned on. 6 7 write data to cgram/ddram 1001001001 hitachi_ writes i. 8 set ddram address 0011000000 hitachi _ sets ram address so that the cursor is positioned at the head of the second line.
hd66710 56 table 17 8-bit operation, 16-digit 2-line display example with internal reset (cont) step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 9 write data to cgram/ddram 1001001101 hitachi m_ writes a space. 10 11 write data to cgram/ddram 1001001111 hitachi microco_ writes o. 12 entry mode set 0000000111 hitachi microco_ sets mode to shift display at the time of write. 13 write data to cgram/ddram 1001001101 itachi icrocom_ writes m. 14 15 return home 0000000010 hitachi microcom _ returns both display and cursor to the original position (address 0).
hd66710 57 table 18 8-bit operation, 8-digit 4-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66710 is initialized by the internal reset circuit) initialized. no display. 2 function set 00001101* * sets to 8 bit operation and the extended register enable bit. 3 4-line mode set 0000001001 sets 4-line display. 4 function set clear extended register enable bit 00001100* * clears the extended register enable bit. setting the n bit is ?on? care? 5 display on/off control 0000001110 _ turns on display and cursor. entire display is in space mode because of initialization. 6 entry mode set 0000000110 _ sets mode to increment the address by one and to shift the cursor to the right at the time of write to the ram. display is not shifted. 7 write data to cgram/ddram 1001001000 h_ writes h. ddram has already been selected by initialization when the power was turned on. 8
hd66710 58 table 18 8-bit operation, 8-digit 4-line display example with internal reset (cont) step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 9 write data to cgram/ddram 1001001001 hitachi_ writes i. 10 set ddram address 0010100000 hitachi _ sets ram address so that the cursor is positioned at the head of the second line. 11 write data to cgram/ddram 1000110000 hitachi 0_ writes 0.
hd66710 59 initializing by instruction if the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary. power on wait for more than 4.1 ms wait for more than 100 s rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 db2 db1 db0 **** rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 db2 db1 db0 **** rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 db2 db1 db0 **** rs 0 r/w 0 db7 0 db6 0 db5 1 db4 1 db3 n db2 0 db1 db0 ** 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 i/d 0 1 s initialization ends bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instuction time. (see table 7.) function set display off display clear entry mode set ?wait for more than 15 ms after v cc rises to 4.5v (v cc = 5v) ?wait for more than 40 ms after v cc rises to 2.7v (v cc = 3v) figure 25 8-bit interface
hd66710 60 initialization ends ?wait for more than 15 ms after v cc rises to 4.5v (v cc = 5v) ?wait for more than 40 ms after v cc rises to 2.7v (v cc = 3v) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) db7 0 db6 0 db5 1 db4 1 rs 0 r/w 0 wait for more than 4.1 ms db7 0 db6 0 db5 1 db4 1 rs 0 r/w 0 wait for more than 100 s db7 0 db6 0 db5 1 db4 1 rs 0 r/w 0 db7 0 db6 0 db5 1 db4 0 rs 0 r/w 0 0 n 0 n 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 * 0 0 0 0 0 i/d 0 0 0 * 0 0 0 1 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instuction time. (see table 7.) function set (4-bit mode). display off display clear entry mode set (i/d, s specification) function set (4-bit mode, n specification). be, lp are clear to ? power on function set (4-bit mode, n specification). * 1 * 1 * 2 important notice when db3 to db0 pins are open in 4-bit mode, the n, re, be, lp bits are set to ?? in this case, instruction time becomes four times in a low power mode (lp = ??. the low power mode is available in this step, so instruction time takes four times. notes: 1. 2. figure 26 4-bit interface
hd66710 61 horizontal dot scroll dot unit shifts are performed by setting the horizontal dot scroll bit (hds) when the extension register is enabled (re = 1). by combining this with character unit display shift instructions, smooth horizontal scrolling can be performed on a 6-dot font width display as shown below. no shift performed shift to the left by one dot 5-dot font width (fw = 0) shift to the left by two dots shift to the left by three dots shift to the left by four dots 6-dot font width (fw = 1) no shift performed shift to the left by one dot shift to the left by two dots shift to the left by three dots shift to the left by four dots shift to the left by five dots figure 27 shift in 5- and 6-dot font width db7 db6 db5 db4 db3 db2 db1 db0 rs r/w 00001dln 1 ** enable the extension register 1 0000 01 1 ** shift the whole display to the left by one character cpu wait 001 001 ** ** shift the whole display to the left by one dot 001 010 ** ** shift the whole display to the left by two dots 001 011 ** ** shift the whole display to the left by three dots 001 10 ** ** shift the whole display to the left by four dots cpu wait cpu wait cpu wait 001 00 ** ** perform no shift cpu wait 8 2 3 4 5 7 (1) method of smooth scroll to the left 001 101 ** ** shift the whole display to the left by five dots cpu wait 6 notes: 1. 2. * 1 * 2 0 0 when the font width is five (fw = 0), this step is skipped. the extended re g ister enable bit ( re ) is cleared. 0 figure 28 smooth scroll to the left
hd66710 62 db7 db6 db5 db4 db3 db2 db1 db0 rs r/w 00001dln 1 ** enable the extension register 1 000001 11 ** cpu wait 001 100 **** 001 011 **** 001 010 **** 001 001 **** cpu wait cpu wait cpu wait 001 000 **** cpu wait 2 4 5 6 7 8 (2) method of smooth scroll to the right 001 101 **** cpu wait 3 shift the whole display to the right by one character shift the whole display to the left by one dot shift the whole display to the left by two dots shift the whole display to the left by three dots shift the whole display to the left by four dots * 2 shift the whole display to the left by five dots perform no shift notes: 1. 2. * 1 when the font width is five (fw = 0), this step is skipped. the extended re g ister enable bit ( re ) is cleared. figure 28 smooth scroll to the left (cont)
hd66710 63 low power mode when lp bit is 1 and the ext pin is low (without an extended driver), the hd66710 operates in low power mode. in 1-line display mode, the hd66710 operates on a 4-division clock, and in 2-line or 4-line display mode, it operates on 2-division clock. so, instruction execution takes four times or twice as long. notice that in this mode, display shift and scroll cannot be performed. clear display shift with the return home instruction, and the horizontal scroll quantity. rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00000000 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00001dln be0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 as2 as1 as0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00001dln be rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00001dln be note: in this operation, instruction execution time takes four times or twice as long. return home extended register enable clear horizontal scroll quantity hds = ?00 set a low power mode reset a power mode low power operation 1 1 1 1 000 1 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00000000 0 return home 1 figure 29 low power mode operation
hd66710 64 absolute maximum ratings item symbol value unit notes* power supply voltage (1) v cc ?.3 to +7.0 v 1 power supply voltage (2) v cc ?5 ?.3 to +15.0 v 1, 2 input voltage vt ?.3 to v cc +0.3 v 1 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c4 notes: if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. * refer to the electrical characteristics notes section following these tables.
hd66710 65 dc characteristics (v cc = 2.7v to 5.5v, t a = ?0 c to +75 c* 3 ) item symbol min typ max unit test condition notes* input high voltage (1) (except osc1) vih1 0.7v cc ? cc v6 input low voltage (1) vil1 ?.3 0.2v cc v6 (except osc1) ?.3 0.6 input high voltage (2) (osc1) vih2 0.7v cc ? cc v15 input low voltage (2) (osc1) vil2 0.2v cc v15 output high voltage (1) (d0?7) voh1 0.75v cc v i oh = 0.1 ma 7 output low voltage (1) (d0?7) vol1 0.2v cc vi ol = 0.1 ma 7 output high voltage (2) (except d0?7) voh2 0.8v cc v i oh = 0.04 ma 8 output low voltage (2) (except d0?7) vol2 0.2v cc vi ol = 0.04 ma 8 driver on resistance (com) r com 2 20 k w id = 0.05 ma (com) vlcd = 4v 13 driver on resistance (seg) r seg 2 30 k w id = 0.05 ma (seg) vlcd = 4v 13 i/o leakage current i li ? 1 m a vin = 0 to v cc 9 pull-up mos current (d0?7, rs, r/ w ) ?p 5 50 120 m av cc = 3v vin = 0v power supply current i cc 150 300 m ar f oscillation, external clock v cc = 3v, f osc = 270 khz 10, 14 i lp1 ?0 m a lp mode, 1/17 duty v cc = 3v, f osc = 270 khz i lp2 100 m a lp mode, 1/33 duty v cc = 3v, f osc = 270 khz lcd voltage vlcd1 3.0 13.0 v v cc ?5, 1/5 bias 16 vlcd2 3.0 13.0 v v cc ?5, 1/6.7 bias note: * refer to the electrical characteristics notes section following these tables. booster characteristics item symbol min typ max unit test condition notes* output voltage (v5out2 pin) vup2 7.5 8.7 v vci = 4.5v, i0 = 0.25 ma, c = 1 m f, f osc = 270 khz, t a = 25 c 18, 19 output voltage(v5out3 pin) vup3 7.0 7.7 v vci = 2.7v, i0 = 0.25 ma, c = 1 m f, f osc = 270 khz, t a = 25 c 18, 19 input voltage vci 1.0 5.0 v vci v cc , t a = 25 c 18, 19, 20 note: * refer to the electrical characteristics notes section following these tables.
hd66710 66 ac characteristics (v cc = 2.7v to 5.5v, t a = ?0 c to +75 c* 3 ) clock characteristics item symbol min typ max unit test condition notes* external external clock frequency f cp 125 270 350 khz 11 clock external clock duty duty 45 50 55 % operation external clock rise time t rcp 0.2 m s external clock fall time t fcp 0.2 m s r f oscillation clock oscillation frequency f osc 190 270 350 khz r f = 91 k w , v cc = 5v 12 note: * refer to the electrical characteristics notes section following these tables. bus timing characteristics (1) (v cc = 2.7v to 4.5v, t a = ?0 c to +75 c* 3 ) write operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 30 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ w to e) t as 60 address hold time t ah 20 data set-up time t dsw 195 data hold time t h 10 read operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 31 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/ w to e) t as 60 address hold time t ah 20 data delay time t ddr 360 data hold time t dhr 5
hd66710 67 bus timing characteristics (2) (v cc = 4.5v to 5.5v, t a = ?0 c to +75 c* 3 ) write operation item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 30 enable pulse width (high level) pw eh 230 enable rise/fall time t er , t ef 20 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 10 data set-up time t dsw 80 data hold time t h 10 read operation item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 31 enable pulse width (high level) pw eh 230 enable rise/fall time t er , t ef 20 address set-up time (rs, r/ w to e) t as 40 address hold time t ah 10 data delay time t ddr 160 data hold time t dhr 5 segment extension signal timing (v cc = 2.7v to 5.5v, t a = ?0 c to +75 c* 3 ) item symbol min typ max unit test condition clock pulse width high level t cwh 500 ns figure 32 low level t cwl 500 clock set-up time t csu 500 data set-up time t su 300 data hold time t dh 300 m delay time t dm ?000 1000 clock rise/fall time t ct 600
hd66710 68 power supply conditions using internal reset circuit item symbol min typ max unit test condition power supply rise time t rcc 0.1 10 ms figure 33 power supply off time t off 1 electrical characteristics notes 1. all voltage values are referred to gnd = 0v. if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 2. v cc 3 v5 must be maintained. in addition, if the seg37/cl1, seg38/cl2, seg39/d, and seg40/m are used as extension driver interface signals (ext = high), gnd 3 v5 must be maintained. 3. for die products, specified at 75 c. 4. for die products, specified by the die shipment specification. 5. the following four circuits are i/o pin configurations except for liquid crystal display output. v cc pmos nmos v cc v cc pmos nmos (pull up mos) pmos v cc nmos nmos v cc pmos nmos (output circuit) (tristate) output enable data (pull-up mos) i/o pin pins: db0 ?b7 (mos with pull-up) input pin pin: e (mos without pull-up) pins: rs, r/w (mos with pull-up) v cc (input circuit) pmos pmos input enable
hd66710 69 6. applies to input pins and i/o pins, excluding the osc1 pin. 7. applies to i/o pins. 8. applies to output pins. 9. current flowing through pull-up moss, excluding output drive moss. 10. input/output current is excluded. when input is at an intermediate level with cmos, the excessive current flows through the input circuit to the power supply. to avoid this from happening, the input level must be fixed high or low. 11. applies only to external clock operation. oscillator osc1 osc2 0.7 v cc 0.5 v cc 0.3 v cc t h t l t rcp t fcp duty = 100% t h t h + t l open 12. applies only to the internal oscillator operation using oscillation resistor rf. osc1 osc2 r f r : r : f f 75 k 2% (when v = 3 v to 4v) 91 k 2% (when v = 4 v to 5v) w w 500 400 300 200 100 50 100 150 (91) r (k ) f w f osc (khz) v cc = 5v typ. 500 400 300 200 100 50 100 150 (75) r (k ) f w f osc (khz) v cc = 3v typ. since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. cc cc (270) (270) max. min. min. max.
hd66710 70 13. rcom is the resistance between the power supply pins (v cc , v1, v4, v5) and each common signal pin (com1 to com33). rseg is the resistance between the power supply pins (v cc , v2, v3, v5) and each segment signal pin (seg1 to seg40). 14. the following graphs show the relationship between operation frequency and current consumption. 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 100 200 300 400 500 v cc = 5v i cc (ma) f osc or f cp (khz) max. typ. 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 100 200 300 400 500 v cc = 3v i cc (ma) f osc or f cp (khz) max. typ. typ. (lp mode) 15. applies to the osc1 pin. 16. each com and seg output voltage is within 0.15v of the lcd voltage (v cc , v1, v2, v3, v4, v5) when there is no load. 17. the test pin must be fixed to the ground, and the ext or v cc pin must also be connected to the ground. 18. booster characteristics test circuits are shown below. gnd v cc 1 m f 1 m f vci c1 c2 v5out2 v5out3 + boosting three times + 1 m f + gnd v cc 1 m f vci c1 c2 v5out2 v5out3 boosting twice + 1 m f + rload rload i o i o
hd66710 71 19. reference data the following graphs show the liquid crystal voltage booster characteristics. vup2 = v cc ?5out2 vup3 = v cc ?5out3 2.0 3.0 4.0 5.0 11 10 9 8 7 6 5 4 boosting twice vci (v) vup2 (v) test condition: vci = v cc , f cp = 270 khz t a = 25 c, rload = 25 k w (1) vup2, vup3 vs vci 2.0 3.0 4.0 5.0 15 14 13 12 11 10 9 8 7 6 boosting three times vci (v) vup3 (v) test condition: vci = v cc , f cp = 270 khz ta = 25 c, rload = 25 k w 0.0 0.5 1.0 1.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 boosting twice i o (ma) vup2 (v) test condition: vci = v cc = 4.5v r f = 91 k w , t a = 25 c (2) vup2, vup3 vs i o 2.0 test condition: vci = v cc = 2.7v r f = 75 k w , t a = 25 c 8.0 7.5 7.0 6.5 6.0 5.5 5.0 boosting three times i o (ma) vup3 (v) 0.0 0.5 1.0 1.5 2.0 boosting twice (3) vup2, vup3 vs t a 9.0 8.5 8.0 7.5 7.0 ?0 ?0 20 60 t a ( c) test condition: vci = v cc = 4.5v r f = 91 k w , i o = 0.25 ma 100 0 vup2 (v) typ. min. typ. min. typ. min. typ. min. 8.0 7.5 7.0 6.5 6.0 vup3 (v) boosting three times ?0 ?0 20 60 t a ( c) test condition: vci = v cc = 2.7v r f = 75 k w , i o = 0.25 ma 100 0 typ. typ.
hd66710 72 boosting twice (4) vup2, vup3 vs capacitance 9.0 8.5 8.0 7.5 7.0 0.5 1.0 c ( m f) test condition: vci = v cc = 4.5v r f = 91 k w , i o = 0.25 ma 1.5 vup2 (v) typ. min. 8.0 7.5 7.0 6.5 6.0 vup2 (v) 0.5 1.0 test condition: vci = v cc = 2.7v r f = 75 k w , i o = 0.25 ma 1.5 c ( m f) typ. min. boosting three times 20. vci v cc must be maintained. load circuits ac characteristics test load circuits data bus: db0?b7 test point 50 pf segment extension signals: cl1, cl2, d, m 30 pf test point
hd66710 73 timing characteristics rs r/w e db0 to db7 vih1 vil1 vih1 vil1 t as t ah vil1 vil1 t ah pw eh t ef vih1 vil1 vih1 vil1 t er t dsw h t vih1 vil1 vih1 vil1 t cyce vil1 valid data figure 30 write operation rs r/w e db0 to db7 vih1 vil1 vih1 vil1 t as t ah vih1 vih1 t ah pw eh t ef vih1 vil1 vih1 vil1 t ddr dhr t t er vil1 voh1 vol1 voh1 vol1 valid data t cyce * * note: vol1 is assumed to be 0.8v at 2 mhz operation. figure 31 read operation
hd66710 74 cl1 cl2 d m voh2 voh2 voh2 vol2 voh2 vol2 t ct t cwh t cwh t csu t cwl t ct t dh t su vol2 t dm vol2 figure 32 interface timing with external driver v cc 0.2v 2.7v/4.5v * 2 0.2v 0.2v t rcc t off * 1 0.1 ms t 10 ms rcc t 1 ms 3 off notes: 1. 2. 3. t compensates for the power oscillation period caused by momentary power supply oscillations. specified at 4.5v for standard voltage operation, and at 2.7v for low voltage operation. if the above electrical conditions are not satisfied, the internal reset circuit will not operate normally. in this case, the lsi must be initialized by software. (refer to the initializing by instruction section.) off figure 33 power supply sequemce
hd66710 75 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

▲Up To Search▲

Price & Availability of HCD66710A00

	To Download HCD66710A00 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .