1 ? fn7435 preliminary el7532 monolithic 2a step-down regulator the el7532 is a synchronous, integrated fet 2a step-down regulator with inte rnal compensation. it operates with an input voltage range from 2.5v to 5.5v, which accommodates supplies of 3.3v, 5v, or a li-ion battery source. the output can be externally set from 0.8v to v in with a resistive divider. the el7532 features pwm mode control. the operating frequency is typically 1.5mhz. additional features include a 100ms power-on-reset output, <1a shut-down current, short-circuit protection, a nd over-temperature protection. the el7532 is available in the 10-pin msop and 10-pin dfn (3x3 mm) packages, making the entire converter occupy less than 0.15 in 2 of pcb area with components on one side only. both packages are specified for operation over the full -40c to +85c temperature range. features ? less than 0.15 in 2 (0.97 cm 2 ) footprint for the complete 2a converter ? components on one side of pcb ? max height 1.1mm msop10 or 1mm dfn 10 package ? 100ms power-on-reset output (por) ? internally-compensated voltage mode controller ? up to 94% efficiency ? <1a shut-down current ? over-current and over-temperature protection applications ? pda and pocket pc computers ? bar code readers ? cellular phones ? portable test equipment ? li-ion battery powered devices ? small form factor (sfp) modules pinout and typical a pplication diagram el7532 top view ordering information part number package tape & reel pkg. dwg. # el7532iy 10-pin msop - mdp0043 el7532iy-t7 10-pin msop 7? mdp0043 el7532iy-t13 10-pin msop 13? mdp0043 el7532il 10-pin dfn - mdp0047 el7532il-t7 10-pin dfn 7? mdp0047 EL7532IL-T13 10-pin dfn 13? mdp0047 * v o = 0.8v * (1 + r 2 / r 1 ) 1 2 3 4 10 9 8 7 5 6 sgnd fb vdd rsi vin en lx por pgnd vo 1.8h v o (1.8v@ 2a) c 1 por r 2 * r 1 * 124k ? 100k ? en rsi 100k ? c 2 v in (2.5v-6v) 100k ? r 4 r 5 10f 10f l 1 r 6 100k ? 0.1f r 3 100 ? c 3 data sheet april 26, 2004 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved. elantec is a registered trademark of elantec semiconductor, inc. all other trademarks mentioned are the property of their respective owners.
2 important note: all parameters having min/max specifications ar e guaranteed. typ values are for information purposes only. unle ss otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute m aximum ratings (t a = 25c) v in , v dd , por to sgnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v lx to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (v in + +0.3v) rsi, en, v o , fb to sgnd . . . . . . . . . . . . . . . -0.3v to (v in + +0.3v) pgnd to sgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4a operating ambient temperature . . . . . . . . . . . . . . . .-40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +145c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v dd = v in = v en = 3.3v, c1 = c2 = 10f, l = 1.8h, v o = 1.8v, unless otherwise specified. parameter description conditions min typ max unit dc characteristics v fb feedback input voltage 790 800 810 mv i fb feedback input current 250 na v in , v dd input voltage 2.5 5.5 v v in,off minimum voltage for shutdown v in falling 2 2.2 v v in,on maximum voltage for startup v in rising 2.2 2.4 v i dd supply current pwm, v in = v dd = 5v 400 500 a en = 0, v in = v dd = 5v 0.1 1 a r ds(on)-pmos pmos fet resistance v dd = 5v, wafer test only 52 80 m ? r ds(on)-nmos nmos fet resistance v dd = 5v, wafer test only 35 65 m ? i lmax current limit 3 a t ot,off over-temperature threshold t rising 145 c t ot,on over-temperature hysteresis t falling 130 c i en , i rsi en, rsi current v en , v rsi = 0v and 3.3v -1 1 v v en1 , v rsi1 en, rsi rising threshold v dd = 3.3v 2.4 v v en2 , v rsi2 en, rsi falling threshold v dd = 3.3v 0.8 v v por minimum v fb for por, wrt targeted v fb value v fb rising 95 % v fb falling 86 % v olpor por voltage drop i sink = 5ma 35 70 mv ac characteristics f pwm pwm switching frequency 1.35 1.5 1.65 mhz t rsi minimum rsi pulse width guaranteed by design 25 50 ns t ss soft-start time 650 s t por power on reset delay time 50 100 150 ms el7532
3 block diagram pin descriptions pin number pin name pin function 1 sgnd negative supply for the controller stage 2 pgnd negative supply for the power stage 3 lx inductor drive pin; high current di gital output with average voltage equal to the regulator output voltage 4 vin positive supply for the power stage 5 vdd power supply for the controller stage 6 rsi resets por timer 7 en enable 8 por power on reset open drain output 9 vo output voltage sense 10 fb voltage feedback input; connected to an ex ternal resistor divider between v o and sgnd for variable output - + - + - + control logic pwm compen- sation por clock 1.5mhz soft- start bandgap reference temperature sense + ? v in lx pgnd por v o fb en v dd sgnd 10pf 5m 124k 100k 10f 2.5v- 5v en pwm comparator n-driver p-driver current limit 1.8 10f 100k pg 1.8v 2a rsi ramp generator under- voltage lockout el7532
4 typical performance curves figure 1. efficiency vs i out @ v in =5v figure 2. efficiency vs i out @ v in =3.3v figure 3. efficiency vs i out @ v in =2.5v figure 4. line regulation figure 5. load regulation @ v in =5v figure 6. load regulation @ v in =3.3v 01 0.5 1.5 2 2.5 100 80 60 40 20 0 i out (a) efficiency (%) maximum efficiency, =95% v o =1.2v v o =1v v o =0.8v v o =3.3v v o =2.5v v o =1.8v 01 0.5 1.5 2 2.5 100 80 60 40 20 0 i out (a) efficiency (%) maximum efficiency, =95% v o =1.2v v o =1v v o =0.8v v o =2.5v v o =1.8v 01 0.5 1.5 2 2.5 100 80 60 40 20 0 i out (a) efficiency (%) maximum efficiency, =94% v o =1v v o =0.8v v o =1.8v v o =1.2v 2.5 4 355.56 1 0.6 0.2 -0.2 -0.6 -1 v in (v) v o changes (%) 4.5 3.5 i o =2a v o =0.8v v o =2.5v v o =3.3v 01.5 0.5 2.5 1 0.6 0.2 -0.2 -0.6 -1 i out (a) v o changes (%) 2 1 v o =0.8v v o =3.3v 01.5 0.5 2.5 1 0.6 0.2 -0.2 -0.6 -1 i out (a) v o changes (%) 2 1 v o =0.8v v o =2.5v el7532
5 figure 7. load regulation @ v in =2.5v figure 8. package power dissipation vs ambient temperature figure 9. package power dissipation vs ambient temperature typical performance curves 01.5 0.5 2.5 1 -0.5 -1 i out (a) v o changes (%) 2 1 v o =1.8v v o =0.8v 0.5 0 jedec jesd51-7 high effective thermal conductivity test board 1.2 1 0.4 0 0 255075100 150 ambient temperature (c) power dissipation (w) 85 1.087w j a = 1 1 5 c / w m s o p 1 0 0.8 0.2 0.6 125 jedec jesd51-3 low effective thermal conductivity test board 0.7 0.6 0.4 0.3 0.2 0.1 0 0 255075100 150 ambient temperature (c) power dissipation (w) 85 607mw j a = 2 0 6 c / w m s o p 1 0 0.5 125 el7532
6 applications information product description the el7532 is a synchronous, integrated fet 2a step-down regulator which operates from an input of 2.5v to 6v. the output voltage is user-adjusta ble with a pair of external resistors. the internally-compensated controller makes it possible to use only two ceramic capacitors and one inductor to form a complete, very small footprint 2a dc-dc converter. start-up and shut-down when the en pin is tied to v in , and v in reaches approximately 2.4v, the regulator begins to switch. the output voltage is gradually increased to ensure proper soft- start operation. when the en pin is connected to a logic low, the el7532 is in the shut-down mode. all th e control circuitry and both mosfets are off, and v out falls to zero. in this mode, the total input current is less than 1a. when the en reaches logic hi, the regulator repeats the start-up procedure, including the soft-start function. pwm operation in the pwm mode, the p channel mosfet and n channel mosfet always operate complementary. when the pmosfet is on and the nmosfet off, the inductor current increases linearly. the input energy is transferred to the output and also stored in the inductor. when the p channel mosfet is off and the n channel mosfet on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. hence, the average current through the inductor is the output current. since the inductor and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to v o divided by v in . the output lc filter has a second order effect. to maintain the stability of the converter, the overall controller must be compensated. this is done with the fixed internally compensated error amplifier and the pwm compensator. because the compensations are fixed, the values of input and output capacitors are 10f to 22f ceramic. the inductor is nominally 1.8h, though 1.5a to 2.2h can be used. 100% duty ratio operation el7532 utilizes cmos power fet's as the internal synchronous power switches. the upper switch is a pmos and lower switch a nmos. this not only saves a boot capacitor, it also allows 100% turn-on of the upper pfet switch, achieving v o close to v in . the maximum achievable v o is, where rl is the dc resistance on the inductor and r dson1 the pfet on-resistance, nominal 70m ? at room temperature with tempco of 0.2m ? /c. as the input voltage drops gradually close or even bellow the preset v o , the converter gets into 100% duty ratio. at this condition, the upper pfet needs some minimum turn-off time if it is turned off. this of f-time is related to input/output conditions. this makes the dut y ratio appears randomly and increases the output ripple somewhat until the 100% duty ratio is reached. larger outpu t capacitor could reduce the random-looking ripple. users need to verify if this condition has adverse effect on overall circuit if close to 100% duty ratio is expected. rsi/por function when powering up, the open-collector power-on-reset output holds low for about 100ms after v o reaches the preset voltage. when the active-hi reset signal rsi is issued, por goes to low immediately and holds for the same period of time after rsi comes back to low. the output voltage is unaffected. (please refer to the timing diagram). when the function is not used, connect rsi to ground and leave open the pull-up resister r 4 at por pin. the por output also serves as a 100ms delayed power good signal when the pull-up resister r 4 is installed. the rsi pin needs to be directly (or indirectly through a resister r 6 ) connected to ground for this to function properly. output voltage selection users can set the output voltage of the converter with a resister divider, which can be chosen based on the following formula: component selection because of the fixed internal compensation, the component choice is relatively narrow. we recommend 10f to 22f multi-layer ceramic capacitors with x5r or x7r rating for both the input and output capacitors, and 1.5h to 2.2h inductance for the inductor. v o v in r l r dson1 + () i o ? = 100ms min 25ns 100ms por rsi v o figure 10. rsi & por timing diagram v o 0.8 1 r 2 r 1 ------ - + ?? ?? ?? = el7532
7 at extreme conditions (v in < 3v, i o > 0.7a, and junction temperature higher than 75c), input cap c 1 is recommended to be 22f. otherwise, if any of the above 3 conditions is not true, c 1 can remain as low as 10f. the rms current present at the input capacitor is decided by the following formula: this is about half of the output current i o for all the v o . this input capacitor must be able to handle this current. the inductor peak-to-peak ripple current is given as: ? l is the inductance ?f s the switching frequency (nominally 1.5mhz) the inductor must be able to handle i o for the rms load current, and to assure that the inductor is reliable, it must handle the 3a surge current that can occur during a current limit condition. current limit and short-circuit protection the current limit is set at about 3a for the pmos. when a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to dr op below the preset voltage. in the meantime, the excessive current heats up the regulator until it reaches t he thermal shut-down point. thermal shut-down once the junction reaches about 145c, the regulator shuts down. both the p channel and the n channel mosfets turn off. the output voltage will drop to zero. with the output mosfets turned off, the regulator will soon cool down. once the junction temperature drops to about 130c, the regulator will restart again in the same manner as en pin connects to logic hi. thermal performance the el7532 is in a fused-lead msop10 package. compared with regular msop10 package, the fused-lead package provides lower thermal resistance. the ja is 100c/w on a 4-layer board and 125c/w on 2- layer board. maximizing the copper area around the pins will further improve the thermal performance. layout considerations the layout is very important for the converter to function properly. the following pc layout guidelines should be followed: ? separate the power ground ( ) and signal ground ( ); connect them only at one point right at the pins ? place the input capacitor as close to v in and pgnd pins as possible ? make the following pc traces as small as possible: - from l x pin to l - from c o to pgnd ? if used, connect the trace from the fb pin to r 1 and r 2 as close as possible ? maximize the copper area around the pgnd pin ? place several via holes under the chip to additional ground plane to improve heat dissipation the demo board is a good example of layout based on this outline. please refer to the el7532 application brief. i inrms v o v in - v o () v in ----------------------------------------------- - i o = ? i il v in ( - v o ) v o lv in f s -------------------------------------------- = el7532
8 msop package outline drawing el7532
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com dfn package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil website at el7532
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