EDI8F8259C 256kx8 sram module 1 EDI8F8259C rev. 9 6/97 eco #8421 features 256kx8 bit cmos static random access memory ? access times 20 thru 35ns ? ttl compatible inputs and outputs ? common data inputs/outputs ? output enable function ? fully static, no clocks jedec approved pinout ? 32 pin dip, no. 61 single +5v (10%) supply operation 256kx8 static ram cmos, module the EDI8F8259C is a 2 megabit cmos static ram based on two high speed 256kx4 static rams mounted on a multi-layered epoxy laminate (fr4) substrate. the 32 pin dip pinout adheres to the jedec standard for the two megabit device, to ensure compatibility with future monolithics. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the EDI8F8259C requires no clocks or refreshing for opera- tion. pin names pin configurations and block diagram pin configuration and block diagram a?-a17 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v10%) vss ground nc no connection a?-a17 w g e dq?-dq3 dq4-dq7 electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 http://www.electronic-designs.com n c a1 6 a1 4 a1 2 a 7 a 6 a 5 a 4 a 3 a 2 a1 a ? dq ? dq 1 dq 2 vs s 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 1 5 1 6 vcc a15 a17 w a13 a8 a9 a11 g a10 e dq7 dq6 dq5 dq4 dq3 nc 1 a16 2 a14 3 a12 4 a7 5 a6 6 a5 7 a4 8 a3 9 a2 10 a1 11 a ? 12 dq ? 13 dq1 14 dq2 15 dq3 16
EDI8F8259C 256kx8 sram module 2 EDI8F8259C rev. 9 6/97 eco #8421 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter sym conditions min typ* max units operating power icc1 w, e = vil, ii/o = 0ma, -- 230 390 ma supply current min cycle standby (ttl) power icc2 e ? vih, vin - vil -- 30 50 ma supply current vin ? vih full standby power icc3 e ? vcc-0.2v -- 2 20 ma supply current (cmos) vin ? vcc-0.2v or vin - 0.2v input leakage current ili vin = 0v to vcc -10 -- 10 a output leakage current ilo v i/o = 0v to vcc -10 -- 10 a output high voltage voh ioh =-4.0ma 2.4 -- -- v output low voltage vol iol = 8.0ma -- -- 0.4 v *typical: ta = 25c, vcc = 5.0v capacitance truth table (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ci 22 pf data lines cd/q 20 pf ac test conditions input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl = 30pf voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature plastic -55c to +125c power dissipation 2.25 watt output current. 20ma *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. (note: for tehqz,tghqz and twlqz, cl = 5pf) parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 these parameters are sampled, not 100% tested.
EDI8F8259C 256kx8 sram module 3 EDI8F8259C rev. 9 6/97 eco #8421 ac characteristics read cycle symbol 20ns 25ns 35ns parameter jedec alt. min max min max min max units read cycle time tavav trc 20 25 35 ns address access time tavqv taa 20 25 35 ns chip enable access time telqv tacs 20 25 35 ns chip enable to output in low z (1) telqx tclz 3 3 3 ns chip disable to output in high z (1) tehqz tchz 10 12 15 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 13 15 20 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z(1) tghqz tohz 8 10 12 ns note 1: parameter guaranteed, but not tested. read cycle 2 - w high read cycle 1 - w high, g, e low tavav tavqv tavqx data 2 a q address 1 address 2 data 1 telqv telqx e q a tavav tglqv tglqx tavqv g tghqz tehqz
EDI8F8259C 256kx8 sram module 4 EDI8F8259C rev. 9 6/97 eco #8421 note 1: parameter guaranteed, but not tested. write cycle 1 - w controlled symbol 20ns 25ns 35ns parameter jedec alt. min max min max min max units write cycle time tavav twc 20 25 35 ns chip enable to end of write telwh tcw 15 20 30 ns teleh tcw 15 20 30 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 15 20 30 ns taveh taw 15 20 30 ns write pulse width twlwh twp 15 20 25 ns twleh twp 15 20 25 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 3 3 3 ns tehdx tdh 3 3 3 ns write to output in high z (1) twlqz twhz 0 10 0 12 0 15 ns data to write time tdvwh tdw 12 15 20 ns tdveh tdw 12 15 20 ns output active from end of write (1) twhqx twlz 3 3 3 ns ac characteristics write cycle a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax
EDI8F8259C 256kx8 sram module 5 EDI8F8259C rev. 9 6/97 eco #8421 package no. 61 32 pin dual-in-line package package description ordering information note: to order an industrial grade product substitute the letter c in the suffix with the letter i. standard power speed package (ns) no. EDI8F8259C20m6c 20 61 EDI8F8259C25m6c 25 61 EDI8F8259C35m6c 35 61 write cycle 2 - e controlled electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 pin 1 ind icator 0.175 0.125 0.100 typ 15 x 0.100 =1.500 0.620 0.590 1.630 max. 0.150 0.138 0.365 max. 0.020 0.016 .640 max. a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh
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