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asahi kasei [AK8411] ms0457-e-00 2006/05 1 AK8411 single channel input, 16 bit 5 msps video adc device outline the AK8411 is a +3.3 v cmos, single channel 16 bit 5 msps adc which integrates on-chip offset adjust dac, gain adjust pga and cds circuit. features ? ccd i/f number of channels 1 channel range 1.98 vpp (typ.) signal input range 0~3.3v @ dc direc t coupled input mode at avdd = 3.3 v integrated on-chip cds circuit compatible with both positive an d negative signal polarities ? adc maximum conversion rate 5 msps resolution 16 bit (straight binary code) ? black level correction dac correctable range 240 mv (typ.) resolution 8 bit ? gain adjust adjustable range 0 db ~ +13.9 db (typ.) (1.0 ~ 4.9) resolution 6 bit ? total performance ( input ~ video adc ) output noise 5 lsbs rms (typ.) @ pga gain = 0 db setting ? data output 2 bit wide 8 cycles ? power supplies analog part: +3.3v 5 % / digit al output part: +3.3v 0.3v ? cpu i/f 3-wire serial interface (write only) clock, data are commonly shared with a/d data output pins ? power dissipation 71 mw (typ.) with dc direct coup led input mode at avdd= 3.3v ? operating temperature range 0 c ~ +70 c ? package 16 pin tssop pin pitch: 0.65 mm, (pin edge to edge: 6.4) 5 mm, mold size: 4.4 mm 5 mm
asahi kasei [AK8411] ms0457-e-00 2006/05 2 circuit block description cisin vclp vco m vrp vrn t sm p mcl k cds s/h 8bit dac pga 16bit adc output control d0/sdcl k sdenb a vdd a vss reference voltage 16 6 d1/sdat a control registers 8 drvdd drvss dc connect mode cds mode clamp switch testo resetb fig. 1 block diagram ? sensor interface part circuit to sample & hold input signal which is fed on cisin pin. signal input range is 1.98v (typ.). there are two input modes, dc direct coupled mode and cds mode. in dc direct coupled mode, positive polarity signal is handled. in cds mode, negative polarity signal is handled. signal reference voltage should be input on vclp pin in dc direct coupled mode. in cds mode, voltage level to clamp signal is internally generated and it is output on vclp pin. ? black level correction circuit circuit to add an offset voltage to the samp led signal level. voltage range of dac which generates offset is 240 mv (typ.) and its resolution is 8 bit. ? pga part circuit to adjust signal amplitude, prior to ad conversion. adjustable gain range is from 0db to 13.9db ( typ. ) (1.0 ~ 4.9) and its resolution is 6 bit. ? adc part ad conversion circuit to convert into digital data an analog signal after both black level correction and gain adjustment are made. it s resolution is 16 bit with its maximum conversion rate of 5msps. data output is in a straight binary code. 0000h is output at black level input ( 0vpp input ) and ffffh is output at white level input ( maximum input ). ? output control part a 16 bit-wide adc output data is re-arranged into 2 bit 8 cycle stream at this part. in single edge mode operation, data is output at the rising edge of mclk. in double edge mode operation, it is output at bo th rising and falling edges of mclk. ? reference voltage generator circuit to generate internal reference volt ages. clamp reference voltage vclp, internal
asahi kasei [AK8411] ms0457-e-00 2006/05 3 common voltage vcom and adc reference voltages vrp and vrn are generated. each reference voltage is output on respective devi ce pins. for voltage stabilization, capacitors should be connected between respective pins and avss. ? serial interface part a 3-wire interface circuit to access setting-reg isters. sdclk (clock) and sdata (data) pins are shared with d0 and d1 pins of adc data output. when sdenb pin is at low, d0 and d1pins function as sdclk and sdata input pins. in order to avoid both sdclk and sdata pins to become floating condition, proper pull-down resistors should be connected between d0 / sdclk pin, d1 / sdata pin and avss respectively. pin functions no. name io description 1 tsmp i sampling timing 2 mclk i main clock single edge mode : 8 sampling frequency double edge mode : 4 sampling frequency 3 resetb i reset pin : ac tive low, on chip pull-up resister : 100k ? (typ.) 4 d1/sdata o i sdenb=high ; a/d data output : upper bit sdenb=low ; serial interface data input 5 drvdd pwr a/d output buffer power supply 6 drvss pwr a/d output buffer ground 7 d0/sdclk o i sdenb=high ; a/d data output : lower bit sdenb=low ; serial interface clock input 8 sdenb i serial interface enable 9 vcom o internal reference voltage 10 vrn o adc negative reference voltage 11 vrp o adc positive reference voltage 12 vclp i o sensor reference level input at dc direct coupled mode clamp level output at cds mode 13 cisin i sensor signal input 14 avss pwr analog ground 15 avdd pwr analog power supply 16 testo o test output pin. should be left open i: input , o: output , pwr: power supply pin allocation 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 tsmp mclk resetb d1/sdata drvdd drvss d0/sdclk sdenb testo a vdd a vss cisin v clp v rp v rn v com top view fig. 2 pin allocation
asahi kasei [AK8411] ms0457-e-00 2006/05 4 functional description ? main clock (mclk) the AK8411 has two clock modes, single edge mode and double edge mode. a required clock frequency differs in each mode. in the si ngle edge mode, the required mclk frequency is 8 times of the pixel clock rate and in the doub le edge mode, it is 4 times of the pixel clock rate. when to change mclk frequency, a time required from frequency change to valid data output is 10 ms maximum. ? sampling timing pulse (tsmp) tsmp is a pixel-period-equivalent input pulse to decide sampling timing of input signal. as mclk and tsmp are also used to generate internal common voltage, it takes 10 ms maximum to output valid data upon stabilization of internal common voltage after re-start of mclk and tsmp when mclk or tsmp is st opped longer than 2000 ns. when the stopped time of mclk or tsmp is equal to or shorter than 2000 ns, a valid data is output right after the recovery of mclk or tsmp application. ? clamp circuit circuit to pull-in the feed-through level of ccd signal to vclp voltage so that ccd signal to be input is set within the input range of samp le & hold circuit. this circuit is enabled at cds mode operation. ? sampling pulses shd, shr (internal pulses) shd is an internal pulse to sample data leve l of cis signal. cis signal is sampled at the falling edge of shd. there are two types of sampling modes. one is mclk synchronous sampling mode where shd is internally genera ted from mclk and tsmp, and the other is tsmp sampling mode where tsmp is directly us ed as shd as is. shr is a pulse to sample feed-through level of cis signal in cds mode operation. cis signal is sampled at the falling edge of shr. shr is also used to control clam p switch. clamp switch is on (close) at shr = high and clamp switch is off (open) at shr = low.
asahi kasei [AK8411] ms0457-e-00 2006/05 5 ? input circuit dc direct coupled mode a mode to capture a difference between the sa mpled signal level at the sample & hold circuit and the reference level to be input on vc lp. it is effective when the pixel signal level is output at higher than the reference level. sample & hold shd cis cisin vclp h: sample l: hold 0.1uf offset dac timing control mclk tsmp fig. 3 in dc direct coupled mode cds mode a mode to sample feed-through level of cis signal (ccd type) and data level, and its difference is captured. in this scheme, thermal noise overlapped with cis signal and shift of clamp level is cancelled out. it is effective when the pixel signal level is output at lower than the reference level. sample & hold #1 sample & hold #2 shr shd shr clamp switch cis cisin vclp h: sample l: hold h: sample l: hold h: close l: open clamp circuit offset dac timing control mcl k tsmp vclp fig. 4 in cds mode
asahi kasei [AK8411] ms0457-e-00 2006/05 6 ? d0, d1 a/d data output a/d data is output in 2 bit wide x 8 cycles. in single edge mode operation, a/d data d0 & d1 are output in sync with the rising edges of mclk. in double edge mode operation, d0 & d1 are output in sync with both rising and falling edges of mclk. mclk tsmp shd (internal) shr (internal) r0b3~b2= 00b 01b 10b 11b feed through level sampling d15 d14 d13 d11d9d7d5d3d1 d12 d10d8d6d4d2d0 d15 d13 d11 d9 d7 d5 d3 d1 d14 d12 d10 d8 d6 d4 d2 d0 d5 d3 d1 d4 d2 d0 d15 d14 d13 d12 d1 d0 cisin r3b4~b3= 00b 01b 10b 11b data level sampling fig. 5 sampling timing and adc output ( in single edge, mclk sync sampling mode ) in single edge mode operation, it is required that 1 ~ 3 rising edges of mclk occur during the tsmp high duration time. when mclk rises twice or more during the tsmp high duration time, the last mclk rising edge be comes effective. when rising edges of mclk during tsmp high duration time occur 4 times and more, correct operation is not made. when the data level sampling mode is mclk sync sampling, shd falls at the next mclk rise after the last mclk rise which detected ts mp = high condition. high duration time of shd can be set by register. when the clock mode is in single edge mode, it can be set from one to four mclk periods in a single period unit. when the clock mode is in double edge mode, it can be set from a half to 2 mclk periods in a half period unit. in single edge mode operation, pulse width of shr is equal to a single mclk period. falling edge position of shr is pre-settable in mclk-period resolution in the range from 2 clock mclk delay to 5 clock mclk delay , counting from the next mclk rising edge after the
asahi kasei [AK8411] ms0457-e-00 2006/05 7 rising edge of mclk where the last tsmp = high condition is detected. mclk tsmp shd (internal) shr (internal) r0b3~b2= 00b 01b 10b 11b feed through level sampling d15 d14 d13 d11d9d7d5d3d1 d12 d10d8d6d4d2d0 d15 d13 d11 d9 d7 d5 d3 d1 d14 d12 d10 d8 d6 d4 d2 d0 d5 d3 d1 d4 d2 d0 d15 d14 d13 d12 d1 d0 cisin data level sampling fig. 6 sampling timing and adc output ( in single edge, tsmp sampling mode ) when the data level sampling pulse mode is tsmp sampling, tsmp pulse is directly used as internal shd as is. shd pulse width setting register becomes invalid in tsmp sampling mode.
asahi kasei [AK8411] ms0457-e-00 2006/05 8 mclk tsmp shr (internal) r0b3~b2= 00b 01b 10b 11b data level sampling feed through level samplin g d15 d14 d13 d11d9d7d5d3d1 d12 d10d8d6d4d2d0 d15 d13 d11 d9 d7 d5 d3 d1 d14 d12 d10 d8 d6 d4 d2 d0 d5 d3 d1 d4 d2 d0 d15 d14 d13 d12 d1 d0 cisin shd (internal) r3b4~b3= 00b 01b 10b 11b fig. 7 sampling timing and adc output ( in double edge, mclk sync sampling mode ) in double edge mode operation, it is required that a single rising edge of mclk occurs during tsmp high duration. when rising edge of mclk during tsmp high duration occurs twice and more, proper operation is not made. shr pulse width in double edge mode is eq ual to a half of mclk period. falling edge position of shr is pre-settable in 1/2 mclk-period resolution in the range from a single mclk clock delay to 2.5 clock delay, counting from the next mclk rising edge after the rising edge of mclk where tsmp = high condition is detected.
asahi kasei [AK8411] ms0457-e-00 2006/05 9 mclk tsmp shr (internal) r0b3~b2= 00b 01b 10b 11b data level sampling feed through level samplin g d15 d14 d13 d11d9d7d5d3d1 d12 d10d8d6d4d2d0 d15 d13 d11 d9 d7 d5 d3 d1 d14 d12 d10 d8 d6 d4 d2 d0 d5 d3 d1 d4 d2 d0 d15 d14 d13 d12 d1 d0 cisin shd (internal) fig. 8 sampling timing and adc output ( in double edge, tsmp sampling mode ) ? power-on-reset a vdd resetb AK8411 100k ? 0.33 f a vdd resetb 3.135v a vdd rising time max. 10ms register can be written after 100ms later max. 100ms fig. 9 power-on-reset at the power-on, power-on-reset must be executed by using resetb pin. when a 0.33 uf external capacitor on resetb pin is used, the rise time of avdd must be shorter than 10 ms in order to assure proper power-on-reset operation. maximum time from avdd power-on to the release from power-on-reset is 100 ms. registers should be written after waiting for longer than 100 ms after avdd power-on. as electric charge is retained in the extern al capacitor even after avdd is made to 0v, voltage on resetb pin does not go to 0v imme diately. if avdd is po wered-up again before resetb pin returns to 0v, a proper power-on-reset operation is not made. in order to assure proper power-on-reset operation when to power-up avdd again, it is required that avdd time to be kept at 0v is longer than 300 ms. if the 300 ms avdd time to be kept at 0v, is not obtainable, the device must be reset by applying a low pulse externally on resetb pin.
asahi kasei [AK8411] ms0457-e-00 2006/05 10 absolute maximum ratings voltages are referenced to correspondi ng ground level. avss = dvss = 0v item symbol min. max. unit note power supplies analog power supply output buffer power supply avdd drvdd ? 0.3 ? 0.3 4.5 4.5 v v digital input voltage vtd ? 0.3 avdd+0.3 v analog input voltage vta ? 0.3 avdd+0.3 v storage temperature tstg ? 65 150 c operation under a condition exceeding above limits may cause permanent damage to the device. normal operation is not guaranteed under the above extreme conditions. recommended operating conditions voltages are referenced to correspon ding ground level. avss=drvss= 0v item symbol min. typ. max. unit note power supplies analog power supply output buffer power supply avdd drvdd 3.135 3.0 3.3 3.3 3.465 3.6 v v operating temperature ta 0 70 c electrical characteristics ? dc characteristics (avdd=3.135~3.465v, drvdd=3.0~3.6v, ta=0 70 c, unless otherwise specified) item symbol pin min. typ. max. unit note h level input voltage vih note 1, 2, 4 0.7 avdd v l level input voltage vil note 1, 2, 4 0.3 avdd v h level output voltage voh note 3 0.7 drvdd v ioh= ? 2ma l level output voltage vol note 3 0.3 drvdd v iol=2ma input leakage current 1 il1 note 1 ? 10 10 a input leakage current 2 il2 note 2 ? 69.3 10 a apply 0v ~ avdd high-z leakage current ilz note 4 ? 10 10 a pull-up resistor rpu note 2 50 100 150 k ? (note 1) tsmp, mclk, sdenb (note 2) resetb (note 3) d0, d1 (at sdenb=high) (note 4) sdata, sdclk (at sdenb=low)
asahi kasei [AK8411] ms0457-e-00 2006/05 11 ? analog characteristics (avdd=3.3v, drvdd=3.3v, mclk=40m hz, single edge mode, ta=25 c, unless otherwise specified) item min. typ. max. unit note reference voltage vcom voltage vrp voltage vrn voltage 1.4 1.9 0.9 1.5 2.0 1.0 1.6 2.1 1.1 v v v analog input maximum signal input level 1.98 v p-p ?0.7 0 0.7 db at dc mode (note 1) absolute gain ?1.45 ?0.45 0.55 db at cds mode (note 1) sampling rate 1 5 msps input reference level 0 1.1 1.5 v at dc mode vclp input resistance 10 60 k ? at dc mode signal input range 0 avdd v at dc mode (note 2) clamp level (vclp voltage ) 1.95 2.05 2.15 v at cds mode clamp resister 7 10 k ? at cds mode black level correction dac resolution 8 bit (note 3) correctable range 215 240 265 mv (note 4) internal offset voltage ?50 50 mv (note 5) pga (programmable gain amp.) circuit resolution 6 bit 0 db minimum gain maximum gain 12.9 13.9 14.9 db (note 6) video adc resolution 16 bit differential non-linearity ?16 +16 lsb integral non-linearity 32 lsb noise 5 lsb rms pga min. output noise 15 lsb rms pga max. power consumption 21.5 31.5 ma at dc mode (note 7) 24.5 34.5 ma at cds mode (note 7) analog part power dissipations 0.1 ma at power down (note 8) digital output driver power dissipation 3 10 ma (note 9) (note 1) 0db is defined at the gain where adc output reaches its full-scale when 1.98vpp signal is input with pga setting at 00h. (note 2) cisin input signal must be in this range which is referenced to avss. (note 3) monotonicity guaranteed. (note 4) 50 mv of the total correctable range is used for internal offset adjustment. (note 5) it defines that a boundary point of adc output codes between 0000h and 0001h exists within 50mv range of the offset adjustment dac setting when 1.1v is fed on cisin & vclp pins in dc direct coupled mode, and when pga gain is set to 0db.
asahi kasei [AK8411] ms0457-e-00 2006/05 12 (note 6) relative value to the gain at pga setting is 00h. (note 7) a full-scale minus 2 db, 1 mhz sine-wave signal is input. (note 8) a clock supply to mclk is stopped. (note 9) at the capacitive load is 20pf. ? switching characteristics (avdd=3.135~3.465v, drvdd=3.0~3.6v, ta=0 70 c, unless otherwise specified) #. item pin min. typ. max . unit conditions 25 125 ns single edge 1 mclk cycle time (t) mclk 50 250 ns double edge 10 ns single edge 2 mclk ?h? , ?l? width mclk 25 ns double edge 3 tsmp set-up time (referenced to mclk ) tsmp 5 ns (note 1) 4 tsmp hold time (referenced from mclk ) tsmp 5 ns (note 1) 5 aperture delay (referenced from mclk ) cisin 2 ns data level 6 aperture delay (referenced from mclk ) cisin 2 ns reference level 8t single edge 7 tsmp period (mclk period-unit ) tsmp 4t double edge 2 25 ns single edge at load:20pf, (note 2) data output delay (referenced from mclk ) d0, d1 2 20 ns single edge at load:20pf, (note 3) 2 25 ns double edge at load :20pf, (note 2) 8 data output delay (referenced from mclk ) d0, d1 2 20 ns double edge at load :20pf, (note 3) 9 pipeline delay d0, d1 4 tsmp period-unit 10 reset pulse width resetb 50 ns (note 1) number of mclk rising edges during tsmp = h duration is allowed to be 1 to 3 times in single edge mode op eration, and only a single edge is allowed in double edge mode operation. (note 2) when output buffer drivability is set at normal setting (note 3) when output buffer drivability is set at 2 setting
asahi kasei [AK8411] ms0457-e-00 2006/05 13 mclk tsmp 0.7avdd 0.7avdd 1 (t) 4 3 shd (internal) cisin 5 sample point 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 fig. 10 sampling timing (in dc dire ct coupled, single edge mode) mcl k tsmp 0.5avdd 1 2 shd (internal) cisin 5 sample point shr (internal) 6 sample point 2 0.3avdd 0.7avdd 0.7avdd 4 3 0.3avdd 43 7 fig. 11 sampling timing (in cds, single edge mode) shd (internal) cisin 5 sample point mclk tsmp 0.7avdd 0.7avdd 1 (t) 4 3 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 fig. 12 sampling timing (in dc dire ct coupled, double edge mode)
asahi kasei [AK8411] ms0457-e-00 2006/05 14 shd (internal) cisin 5 sample point shr (internal) 6 sample point mclk tsmp 0.7avdd 0.7avdd 1 (t) 4 3 0.5avdd 2 2 0.7avdd 0.3avdd 0.3avdd 43 7 fig. 13 sampling timing (in cds, double edge mode) mcl k d0, d1 0.7avdd 0.7drvdd 8 0.3avdd 0.3 drvdd fig. 14 data output timing (single edge mode) mcl k d0, d1 0.7avdd 0.7drvdd 8 0.3avdd 0.3drvdd 8 fig. 15 data output timing ( double edge mode ) resetb 10 0.3avdd 0.3avdd fig. 16 reset pulse width
asahi kasei [AK8411] ms0457-e-00 2006/05 15 mclk tsmp shd (internal) cisin n+5 n+4 n+3 n+2 n+1 n d1 d0 n ? 4 n ? ? ? ? 5 n ? 5 n ? 4 n ? ? ? ? 4 n ? ? ? ? 5 n ? 5 n ? 4 n ? ? ?
asahi kasei [AK8411] ms0457-e-00 2006/05 16 mcl k tsmp n ? 4 d15 n ? 4 d14 n ? ? ? ? ? ? ? ? ? ? ? ? ? 4 d1 n ? 4 d0 n ? 3 d15 n ? 3 d14 n ? 5 d1 n ? ? ? 5 d0 d1 d0 cisin n n+1 n ? ? 4 d15 n ? 4 d14 n ? ? ? ? ? ? ? ? ? ? ? ? ? 4 d1 n ? 4 d0 n ? 3 d15 n ? 3 d14 n ? 5 d1 n ? ? ? 5 d0 d1 d0 cisin n n+1 n ?
asahi kasei [AK8411] ms0457-e-00 2006/05 17 ? switching characteristics : serial interface ( avdd = 3.135 ~3.465v, drvdd = 3.0 ~3.6v, ta = 0 ~70c , unless otherwise specified ) # item pins min. typ. max. unit conditions 1 clock period sdclk 0.1 10 mhz 2 clock pulse width (h duration) sdclk 40 ns 3 clock pulse width ( l duration ) sdclk 40 ns 4 sdenb setup time (to sdclk rising edge ) sdenb 80 ns 5 sdenb hold time (from sdclk rising edge ) sdenb 80 ns 6 data high-z delay (from sdenb falling edge ) d0, d1 0 40 ns 7 data enable delay (from sdenb rising edge ) d0, d1 0 40 ns 8 sdata setup time (to sdclk rising edge ) sdata 40 ns 9 sdata hold time ( from sdclk rising edge ) sdata sdenb 40 ns 10 sdclk,sdenb rise time sdclk sdenb 6 ns 11 sdclk,sdenb fall time sdclk sdenb 6 ns 12 sdenb high level pulse width sdenb 40 ns sdcl k sdata sdenb 0.7avdd 0.7avdd 8 0.3avdd 0.3avdd 9 0.3avdd 32 1 12 10 11 0.7avdd 10 11 0.7avdd 0.3avdd d0 4 d1 7 7 6 6 0.7drvdd 0.3drvdd 0.7drvdd 0.3drvdd 5 fig. 21 serial interface timing
asahi kasei [AK8411] ms0457-e-00 2006/05 18 serial interface clock input pin sdclk and data input pin sdat a for serial interface are shared with a/d data output pins, d0 and d1 respectively. when sdenb becomes low, d0 and d1 are put into high-z conditions and it is enabled to input sdclk and sdata. sdata is captured at the rising edge of sdclk. sdata is 16 bit long. write ?zeros? from the 1 st bit to the 5 th bit. 6 th ~8 th bits are assigned for register address where the 6 th bit is msb and the 8 th bit is lsb. 9 th ~ 16 th bits are assigned for data where the 9 th bit is msb and the 16 th bit is lsb. 16 and more rising edges of sdclk are required while sdenb is low, from the time to fall to the time to rise. when it is less than 16 rises, registers will not be written properly. if it is more than 16 rises while sdenb is low, from falling to rising, the last 16 edges become effective. there is a possibility that an erroneous data will be written into registers if noises occur on d0 output / sdclk input pin and d1 output / sdata input pin when these pins are at high-z conditions. to avoid this, resistors should be connected between d0 / sdclk pin, d1 / sdata pin and avss respectively to pull-down these pins. 0 0 sdenb d0 sdcl k d1 sdata 0 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 0 high-z high-z 0 0 0 high-z high-z fig. 22 register write operation control registers it takes 10 ms maximum from register contents to be modified till valid data to be output on d0 & d1 pins. when to modify register contents when r0 b7 is set to ?zero? (reset condition), set r0 b7 to ?one? (release from reset) first, then modify ot her registers, including b6 ~b0 bits at address zero. un-used bits can be written with either ?zeros? or ?ones?. address init. b7 b6 b5 b4 b3 b2 b1 b0 0 00h reset 0 output buffer drivability input mode reference level sampling position clock mode power down 1 80h offset dac data ( 8bit ) 2 00h un-used pga gain data (6bit) 3 00h un-used shd mode shd width 0 0 output order 4 00h for testing purpose 5 00h for testing purpose
asahi kasei [AK8411] ms0457-e-00 2006/05 19 ? r0 b7 register reset b7 operation 0 reset ( at reset ) 1 release from reset when this bit is set to ?0?, all other registers are set to initial values, except for this bit. when this bit is ?0?, write operation into all ot her registers except for this bit is ignored. ? r0 b6 reserved write ? 0 ?. ? r0 b5 output buffer drivability b5 output mode 0 normal ( at reset ) 1 2 ( double ) when output buffer drivability is set to ?2?, maximum output current of the output buffers increases. this selection is used when the data output delay which is referenced to data capture clock becomes too large, due to capacitive loading. ? r0 b4 input mode b4 input mode 0 dc direct-coupled mode ( at reset ) 1 cds mode signal polarity which can be processed by th e AK8411 is determined by the type of input modes. in dc direct-coupled mode, it handles positive polarity (signal is output toward higher voltage than reference level) and in cds mode, it handles negative polarity (signal is output toward lower voltage than reference level). ? r0 b3~b2 feed-through level sampling pulse (shr) position b3 b2 shr position at single edge mode shr position at double edge mode 0 0 2 mclk delay ( at reset ) from the data level sampling position 1 mclk delay ( at reset ) from the data level sampling position 0 1 3 mclk delay 1.5 mclk delay 1 0 4 mclk delay 2 mclk delay 1 1 5 mclk delay 2.5 mclk delay this register is to set fall position of intern al pulse shr, at which feed-through level is sampled. pulse width of shr is fixed. shr is enabled only when the device is in cds mode operation. shr stops while it is in dc direct-coupled mode operation.
asahi kasei [AK8411] ms0457-e-00 2006/05 20 ? r0 b1 clock mode b1 clock mode 0 single edge ( at reset ) 1 double edge in single edge mode operation, d0 & d1 data of adc are output in sync with rising edge of mclk. required mclk frequency is 8 x pixel ra te. in double edge mode operation, data are output in sync with both rising and fallin g edges of mclk. requir ed mclk frequency is 4 x pixel rate. ? r0 b0 operation mode select b0 operation mode 0 power down ( at reset ) 1 normal operation when this bit is set to ?0?, logic circuit excl uding serial interface stops its operation while analog part is powered-down. register contents just before being put into power-down operation are retained even during power-down operation. ? r1 offset dac setting b7 b0 offset level 00000000 : 01111111 10000000 10000001 : 11111111 ? 240mv : ? 1.88mv (at reset ) 0mv +1.88mv : +238mv mv] [ 256 / 480 240 x offset(x) + ? = ( x =0~255) where x is a register set value. at reset : x= 128, offset(128)=0mv s/h black correction ffh 00h 80h offset dac setting s/h output level cis signal after black correction pga adc max. min. output code fig. 23 level changes by offset setting (in dc direct-coupled mode operatio n = positive polarity operation)
asahi kasei [AK8411] ms0457-e-00 2006/05 21 cds black correction 00h ffh 80h offset dac setting cds output level cis signal (ccd type ) after black correctio n pga adc min. max. output code fig. 24 level changes by offset setting (in cds mode operation = negative polarity operation) offset dac output is added to the sampled & he ld signal level. both in dc direct-coupled mode operation (positive polarity) and in cds mode operation (negative polarity), when setting code to the offset dac is smaller, th e adc output code beco mes smaller, and when it is larger, the adc output code becomes larger. ? r2h pga gain setting ] [ ) 63 ( 16 80 0 . 2 98 . 1 times x gain(x) ? + = ( x =0~63) where x is a register setting value. at reset, x =0 then gain (0) = 1.0 time. 0 1 2 3 4 5 016324864 register setting[dec] gain[times] 0 0.1 0.2 0.3 0.4 0.5 gain step[times] gain[times] step[times] 0 3 6 9 12 15 0 16324864 register setting[dec] gain[db] 0 0.2 0.4 0.6 0.8 1 gain step[db] gain[db] step[db] fig. 25 gain curves (theoretical values)
asahi kasei [AK8411] ms0457-e-00 2006/05 22 ? r3 b5 data level sampling pulse (shd) mode select b5 data level sampling pulse (shd) 0 mclk synchronous sampling ( at reset ) 1 tsmp sampling ? r3 b4~b3 data level sampling pulse width (shd) select b4 b3 shd pulse width in single edge mode shd pulse width in double edge mode 0 0 1 mclk period (at reset) 0.5 mclk period( at reset ) 0 1 2 mclk period 1 mclk period 1 0 3 mclk period 1.5 mclk period 1 1 4 mclk period 2 mclk period falling edge position of shd, namely data le vel sampling point is fixed. only the rising edge of shd changes by register setting. this register becomes invalid when the sampling pulse mode is at tsmp. ? r3 b2-b1 reserved write 00b to these bits. ? r3 b0 output order select b0 output order 0 normal ( at reset ) 1 msb 8bit / lbs 8bit split d15 d14 d13 d11 d9 d7 d5 d3 d1 d12 d10 d8 d6 d4 d2 d0 d15 d13 d11 d9 d7 d5 d3 d1 d14 d12 d10 d8 d6 d4 d2 d0 d5 d3 d1 d4 d2 d0 d15 d14 d13 d12 d1 d0 fig. 26 normal d15 d7 d14 d13 d12 d11 d10 d9 d8 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 d9 d8 d2 d1 d0 d15 d7 d14 d6 d1 d0 fig. 27 msb 8bit / lsb 8bit split mode timing diagrams shown in this data sheet are a case of normal order of output data, unless otherwise noted.
asahi kasei [AK8411] ms0457-e-00 2006/05 23 external circuit examples v com v rn v rp v clp cisin a vss a vdd testo sdenb d0/sdcl k drvss drvdd d1/sdata resetb mclk tsmp top view 3.3v 3.3v reference v oltage sensor signal c2 c5 r2 r1 0.1 f 10% c5: 0.33 f 10% r1~r2: min. 10k ? c1 c3 c4 fig. 28 in dc direct-coupled mode operation v com v rn v rp v clp cisin a vss a vdd testo sdenb d0/sdcl k drvss drvdd d1/sdata resetb mclk tsmp top view 3.3v 3.3v sensor signal c1 c2 c6 c3 c4 c5 r2 r1 0.1 f 10% c5: 0.33 f 10% c6: 0.1 f 10% r1~r2: min. 10k ? fig. 29 in cds mode operation
asahi kasei [AK8411] ms0457-e-00 2006/05 24 package ? package dimensions 5.00 0.1 0.65 0.13 m 0.17 0.2 0.5 0.2 0 ~10 1.00 0.05 0.10 1.07+0.03 ? 0.07 0.07+0.03 ? 0.04 0.22 ? package markings 1. akm logo : akm 2. marketing code : 8411vt 3. date code : xxx week code : yy akm?s factory control code akm 8411vt xxxyy fig. 31 package marking
asahi kasei [AK8411] ms0457-e-00 2006/05 25 important notice z these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. z akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval und er the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor author ized for use as critical components in any safety, life support, or other hazard relate d device or system, and akm assumes no responsibility relating to any such use, exce pt with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant in jury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system cont aining it, and which must therefore meet very high standards of performance and reliability. z it is the responsibility of the buyer or dist ributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions , and the buyer or distributor agrees to assume any and all responsibility and liabilit y for and hold akm harmless from any and all claims arising from the use of said prod uct in the absence of such notification.

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