stk11c48 3-1 stk11c48 cmos nvsram high performance 2k x 8 nonvolatile static ram logic block diagram pin configurations features ? 30, 35 and 45ns access times ? 15, 20 and 25ns output enable access ? unlimited read and write to sram ? software store initiation ? automatic store timing ? 100,000 store cycles to eeprom ? 10 year data retention in eeprom ? automatic recall on power up ? software recall initiation ? unlimited recall cycles from eeprom ? single 5v 10% operation ? commercial and industrial temperatures ? available in multiple standard packages description the simtek stk11c48 is a fast static ram (30, 35, 45ns), with a nonvolatile electrically-erasable prom ( eeprom ) element incorporated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resides in eeprom . data transfers from the sram to the eeprom ( store ), or from the eeprom to the sram ( recall ) are initiated through software se- quences. it combines the high performance and ease of use of a fast sram with nonvolatile data integrity. the stk11c48 is pin compatible with industry stan- dard sram s and is available in a 28-pin 300 mil plastic dip, 28-pin 600 mil plastic dip package and 28 pin soic packages. a a a a a a 3 4 5 6 7 8 eeprom array 256 x 64 store recall static ram array 256 x 64 row decoder store/ recall control aaaaa 0 12g 10 dq dq dq dq dq dq dq dq 0 1 2 3 4 5 6 7 g e w column i/o column decoder input buffers aa 010 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc a a a a a a a a dq dq dq dq dq dq dq dq v v w nc a a nc g a e ss 7 6 5 4 3 2 1 0 0 1 2 8 9 10 7 6 5 4 3 cc nc pin names a 0 - a 10 address inputs w write enable dq 0 - dq 7 data in/out e chip enable g output enable v cc power (+5v) v ss ground 28 - 350 soic 28 - 300 pdip 28 - 600 pdip
stk11c48 3-2 i cc b average v cc current 80 85 ma t avav = 30ns 75 80 ma t avav = 35ns 65 75 ma t avav = 45ns i cc d average v cc current 50 50 ma all inputs at during store cycle v in 0.2v or 3 (v cc ?0.2v) i sb c average v cc current 27 30 ma t avav = 30ns (standby, cycling ttl input levels) 23 27 ma t avav = 35ns 20 23 ma t avav = 45ns e 3 v ih ; all others cycling i sb c average v cc current 1 1 ma e 3 (v cc ?0.2v) (standby, stable cmos input levels) all others v in 0.2v or 3 (v cc ?0.2v) i ilk input leakage current (any input) 1 1 m av cc = max v in = v ss to v cc i olk off state output leakage current 5 5 m av cc = max v in = v ss to v cc v ih input logic "1" voltage 2.2 v cc +.5 2.2 v cc +.5 v all inputs v il input logic "0" voltage v ss ?5 0.8 v ss ?5 0.8 v all inputs v oh output logic "1" voltage 2.4 2.4 v i out = ?ma v ol output logic "0" voltage 0.4 0.4 v i out = 8ma t a operating temperature 0 70 ?0 85 c note b: i cc is dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. note c: bringing e 3 v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. see mode selection table. note d: i cc is the average current required for the duration of the store cycle (t store ) after the sequence (t wc ) that initiates the cycle. absolute maximum ratings figure 1: ac output loading voltage on typical input relative to v ss . . . . . . . . . . . . . ?.6v to 7.0v voltage on dq 0-7 and g. . . . . . . . . . . . . . . . . . .?.5v to (v cc +0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . . . ?5 c to 125 c storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . ?5 c to 150 c power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1w dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15ma note a: stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. (one output at a time, one second duration) dc characteristics (v cc = 5.0v 10%) 5.0v output 480 ohms 30pf including scope and fixture 255 ohms ac test conditions input pulse levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss to 3v input rise and fall times. . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels. . . . . . . . . . . . . . 1.5v output load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 capacitance (t a =25 c, f=1.0mhz) e a commercial industrial symbol parameter units notes min max min max 1 2 1 2 1 2 c in input capacitance 7 pf d v = 0 to 3v c out output capacitance 7 pf d v = 0 to 3v symbol parameter max units conditions note e: these parameters are guaranteed but not tested.
stk11c48 3-3 read cycles #1 & #2 (v cc = 5.0v 10%) read cycle #2 g w dq (data out) address data valid 5 t axqx 11a t whqv 2 t avavr 3 t avqv address e g dq (data out) data valid i cc w 2 t avavr 1 t elqv 6 t elqx 4 t glqv 8 t glqx 11 t ehiccl 7 t ehqz 9 t ghqz 10 t elicch 11a t whqv active standby 1t elqv t acs chip enable access time 30 35 45 ns 2t avavr g t rc read cycle time 30 35 45 ns 3t avqv h t aa address access time 30 35 45 ns 4t glqv t oe output enable to data valid 15 20 25 ns 5t axqx t oh output hold after address change 5 5 5 ns 6t elqx t lz chip enable to output active 5 5 5 ns 7t ehqz i t hz chip disable to output inactive 18 20 25 ns 8t glqx t olz output enable to output active 0 0 0 ns 9t ghqz i t ohz output disable to output inactive 18 20 25 ns 10 t elicch e t pa chip enable to power active 0 0 0 ns 11 t ehiccl c,e t ps chip disable to power standby 25 25 25 ns 11a t whqv t wr write recovery time 35 45 55 ns #1, #2 alt. min max min max min max symbols stk11c48-30 stk11c48-35 stk11c48-45 no. parameter units note c: bringing e high will not produce standby currents until any nonvolatile cycle in progress has timed out. see mode sel ection table. note e: parameter guaranteed but not tested. note g: for read cycle #1 and #2, w must be high for entire cycle. note h: device is continuously selected with e low and g low. note i: measured 200mv from steady state output voltage. read cycle #1 g,h
stk11c48 3-4 write cycles #1 & #2 (v cc = 5.0v 10%) write cycle #1: w controlled write cycle #2: e controlled k k 12 t avavw t avavw t wc write cycle time 45 45 45 ns 13 t wlwh t wleh t wp write pulse width 35 35 35 ns 14 t elwh t eleh t cw chip enable to end of write 35 35 35 ns 15 t dvwh t dveh t dw data set-up to end of write 30 30 30 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 35 35 35 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz i,m t wz write enable to output disable 35 35 35 ns 21 t whqx t ow output active after end of write 5 5 5 ns symbols stk11c48-30 stk11c48-35 stk11c48-45 no. parameter units #1 #2 alt. min max min max min max note i: measured 200mv from steady state output voltage. note k: e or w must be high during address transitions. note m: if w is low when e goes low, the outputs remain in the high impedance state. previous data address e w data in data out data valid high impedance 12 t avavw 14 t elwh 19 t whax 17 t avwh 18 t avwl 13 t wlwh 15 t dvwh 16 t whdx 20 t wlqz 21 t whqx address e w data in data out high impedance data valid 12 t avavw 18 t avel 14 t eleh 19 t ehax 17 t aveh 13 t wleh 15 t dveh 16 t ehdx
stk11c48 3-5 note n: the six consecutive addresses must be in order listed - (000, 555, 2aa, 7ff, 0f0, 70f) for a store cycle or (000, 555, 2aa, 7ff, 0f0, 70e) for a recall cycle . w must be high during all six consecutive cycles. see store cycle and recall cycle tables and diagrams for further details. note o: i/o state assumes that g is low. initiation and operation of nonvolatile cycles does not depend on the state of g. h x x not selected output high z standby l h x read sram output data active o l l x write sram input data active l h 000 read sram output data active n,o 555 read sram output data n,o 2aa read sram output data n,o 7ff read sram output data n,o 0f0 read sram output data n,o 70f nonvolatile store output high z i cc n l h 000 read sram output data active n,o 555 read sram output data n,o 2aa read sram output data n,o 7ff read sram output data n,o 0f0 read sram output data n,o 70e nonvolatile recall output high z n store cycle inhibit and automatic power-up recall 3.8v 5.0v t store inhibit automatic recall v cc nonvolatile memory operation mode selection ew a 10 - a 0 (hex) mode i/o power notes 2
stk11c48 3-6 22 t avavn t rc store/recall initiation cycle time 30 35 45 ns 23 t elqz p chip enable to output inactive 75 75 75 ns 24 t elqxs t store q store cycle time 10 10 10 ms 25 t elqxr t recall r recall cycle time 20 20 20 m s 26 t aveln s t ae address set-up to chip enable 0 0 0 ns 27 t elehn s,t t ep chip enable pulse width 20 25 35 ns 28 t ehaxn s t ea chip disable to address change 0 0 0 ns (v cc = 5.0v 10%) store/recall cycle address e data out data valid address #6 address #1 data valid high impedance 22 t avavn 22 t avavn 26 t aveln 27 t elehn 28 t ehaxn 24 t store 25 t recall 23 t elqz store/recall cycle u,v symbols stk11c48-30 stk11c48-35 stk11c48-45 no. parameter units #1 alt. min max min max min max note p: once the software store or recall cycle is initiated, it completes automatically, ignoring all inputs. note q: note that store cycles (but not recalls ) are aborted by v cc < 3.8v ( store inhibit). note r: a recall cycle is initiated automatically at power up when v cc exceeds 3.8v. t recall is measured from the point at which v cc exceeds 4.5v. note s: noise on the e pin may trigger multiple read cycles from the same address and abort the address sequence. note t: if the chip enable pulse width is less than t elqv (see read cycle #2) but greater than or equal to t elehn , then the data may not be valid at the end of the low pulse, however the store or recall will still be initiated. note u: w must be high when e is low during the address sequence in order to initiate a nonvolatile cycle. g may be either high or low throughout. addresses #1 through #6 are found in the mode selection table. address #6 determines whether the stk11c48 performs a store or recall . . note v: e must be used to clock in the address sequence for the software store and recall cycles.
stk11c48 3-7 the stk11c48 has two separate modes of operation: sram mode and nonvolatile mode. in sram mode, the memory operates as an ordinary static ram . in non- volatile operation, data is transferred from sram to eeprom or from eeprom to sram . in this mode sram functions are disabled. sram read the stk11c48 performs a read cycle whenever e and g are low while w is high . the address specified on pins a 0-10 determines which of the 2048 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by e or g, the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high or w is brought low . sram write a write cycle is performed whenever e and w are low . the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w go high at the end of the cycle. the data on pins dq 0-7 will be written into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low , internal circuitry will turn off the output buffers t wlqz after w goes low . nonvolatile store the stk11c48 store cycle is initiated by executing sequential read cycles from six specific address loca- tions. by relying on read cycles only, the stk11c48 implements nonvolatile operation while remaining pin- for-pin compatible with standard 2kx8 sram s. during the store cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. the program operation copies the sram data into nonvolatile elements. once a store cycle is initiated, further input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted and no store or recall will take place. to enable the store cycle the following read se- quence must be performed: 1. read address 000 (hex) valid read 2. read address 555 (hex) valid read 3. read address 2aa (hex) valid read 4. read address 7ff (hex) valid read 5. read address 0f0 (hex) valid read 6. read address 70f (hex) initiate store cycle once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. hardware protect the stk11c48 offers hardware protection against inadvertent store cycles through v cc sense. a store cycle will not be initiated, and one in progress will discontinue, if v cc goes below 3.8v. 3.8v is a typical, characterized value. nonvolatile recall a recall cycle of the eeprom data into the sram is initiated with a sequence of read operations in a manner similar to the store initiation. to initiate the recall cycle the following sequence of read opera- tion must be performed: 1. read address 000 (hex) valid read 2. read address 555 (hex) valid read 3. read address 2aa (hex) valid read 4. read address 7ff (hex) valid read 5. read address 0f0 (hex) valid read 6. read address 70e (hex) initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvolatile information is transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. on power-up, once v cc exceeds the v cc sense volt- age of 3.8v, a recall cycle is automatically initiated. the voltage on the v cc pin must not drop below 3.8v once it has risen above it in order for the recall to operate properly. due to this automatic recall , sram operation cannot commence until t recall after v cc exceeds 3.8v. 3.8v is a typical, characterized value. device operation
stk11c48 3-8 ordering information stk11c48 - p 30 i temperature range blank = commercial (0 to 70 degrees c) i = industrial (?0 to 85 degrees c) access time 30 = 30ns 35 = 35ns 45 = 45ns package p = plastic 28 pin 300 mil dip w = plastic 28 pin 600 mil dip s = plastic 28 pin soic
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